From patchwork Thu Mar 30 10:26:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 77086 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1037520vqo; Thu, 30 Mar 2023 04:01:14 -0700 (PDT) X-Google-Smtp-Source: AKy350Yfvs62Nia6gwKRIR/n+UxpfOSPtcw6hpMS88wUhHffBzCTyGE6tZuL/Dw5vPiNXJP4QbcZ X-Received: by 2002:a17:906:2a84:b0:932:e9c7:c32 with SMTP id l4-20020a1709062a8400b00932e9c70c32mr25011097eje.59.1680174074614; Thu, 30 Mar 2023 04:01:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680174074; cv=none; d=google.com; s=arc-20160816; b=qnDUzjZm+4dqvEol2reTuJJnU92THUZ2MMofMCNtsMa47ERdWXoDWHn7j8paYS3yy3 owJldg7t7FbC5y0lKPYLncxNoPqISQSDyH+Hd6DoOH3Vqseqp3I0ARvO3LD0Knkzh51p gZLukITcClYXiWdCPfadoqDycqbfDWRvzaaz98qTBo+J4uDX5ws4flKGdtGsWWVXHhcI T+B/2dNIsw5U+3VaK7UDP5672kLbi8CEoHCtuLFrCziPmbBu/dVrkfl8H4oEVFms3TOJ de1Z+QQeprKVHX8USl79XWt4EmeZNYPPNOpHi0Mb2jBB5VyvSBxivop/0lAEgmgFs8hS uAzQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:dmarc-filter:delivered-to :dkim-signature:dkim-filter; bh=Gmm4BS8XEjgiOQdvhknSo+TS7cLDxB9G5XfGsGWYJng=; b=N1iKtDyJHkRWKs7LlyxoA5V0ITSGxp+KxTzvQSauGoh3RhuDA7zJDq6umFG+uzHB6w aGcrVqXGqDrF1+2sIRZPs47K2hpadOdi3wfmWdUdaF9d4UDl/tyIGD0KAtSlPtBgN88h nl45JbggpNalS62OhhEkkzA8rBTfJ/iVEZCJ+GCDOF0ZNcLDNEE1bNNrIpBQx40RoVkq j3pk562bOHw05oekvqeT9Y6qpwaiCmVDAVXjNbfnsDo4nlWp8L14EJDXZMV/BpKbtVr5 fRhrdcJ08siH6ggZiZo9kHl/Z0ipXCrMmVk84+b0IzXN0r7zMDf8Q4+3i7iENKQyV+eq ctdA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=TjbLisKZ; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id w19-20020a170906b19300b009477d131256si175868ejy.566.2023.03.30.04.01.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Mar 2023 04:01:14 -0700 (PDT) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=TjbLisKZ; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id CE4903AA888A for ; Thu, 30 Mar 2023 10:42:10 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org CE4903AA888A DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1680172930; bh=Gmm4BS8XEjgiOQdvhknSo+TS7cLDxB9G5XfGsGWYJng=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=TjbLisKZbe8RlK1RRqgeTWH+yEjdaqDQVMnk6+Bxka6DgcSPj+S0oIAS2EFltyqiq e58xT2GKF/Hi1dOnL8heawOgLcV9J4s4kDHCOvGlgwStqS00t7hsHiGzSlluRdHozw 9a9XiXXM5rLTsMhQXgTEJ0909OuakM5L6QmPZJLk= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 46B9F3895FCD for ; Thu, 30 Mar 2023 10:26:54 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 46B9F3895FCD Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6644E12FC; Thu, 30 Mar 2023 03:27:38 -0700 (PDT) Received: from e121540-lin.manchester.arm.com (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 9D3DE3F663; Thu, 30 Mar 2023 03:26:53 -0700 (PDT) To: binutils@sourceware.org Cc: Richard Sandiford Subject: [PATCH 01/31] aarch64: Add +sme2 Date: Thu, 30 Mar 2023 11:26:16 +0100 Message-Id: <20230330102646.3327818-2-richard.sandiford@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230330102646.3327818-1-richard.sandiford@arm.com> References: <20230330102646.3327818-1-richard.sandiford@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-32.3 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KAM_NUMSUBJECT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Richard Sandiford via Binutils From: Richard Sandiford Reply-To: Richard Sandiford Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761790210653660745?= X-GMAIL-MSGID: =?utf-8?q?1761790210653660745?= This patch adds bare-bones support for +sme2. Later patches fill in the rest. --- gas/NEWS | 2 ++ gas/config/tc-aarch64.c | 2 ++ gas/doc/c-aarch64.texi | 2 ++ include/opcode/aarch64.h | 1 + 4 files changed, 7 insertions(+) diff --git a/gas/NEWS b/gas/NEWS index 4ae2089901c..05fbed113c2 100644 --- a/gas/NEWS +++ b/gas/NEWS @@ -1,5 +1,7 @@ -*- text -*- +* Add SME2 support to the AArch64 port. + Changes in 2.40: * Add support for Intel RAO-INT instructions. diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 2d4c6106506..6ebfcda7dff 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -10183,6 +10183,8 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = { AARCH64_FEATURE (AARCH64_FEATURE_SME, 0)}, {"sme-i16i64", AARCH64_FEATURE (AARCH64_FEATURE_SME_I16I64, 0), AARCH64_FEATURE (AARCH64_FEATURE_SME, 0)}, + {"sme2", AARCH64_FEATURE (AARCH64_FEATURE_SME2, 0), + AARCH64_FEATURE (AARCH64_FEATURE_SME, 0)}, {"bf16", AARCH64_FEATURE (AARCH64_FEATURE_BFLOAT16, 0), AARCH64_FEATURE (AARCH64_FEATURE_FP, 0)}, {"i8mm", AARCH64_FEATURE (AARCH64_FEATURE_I8MM, 0), diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi index 3921c0d368e..acde4a77dd2 100644 --- a/gas/doc/c-aarch64.texi +++ b/gas/doc/c-aarch64.texi @@ -235,6 +235,8 @@ automatically cause those extensions to be disabled. @tab Enable SME F64F64 Extension. @item @code{sme-i16i64} @tab Armv9-A @tab No @tab Enable SME I16I64 Extension. +@item @code{sme2} @tab Armv9-A @tab No + @tab Enable SME2. This implies @code{sme}. @item @code{ssbs} @tab ARMv8-A @tab ARMv8.5-A or later @tab Enable Speculative Store Bypassing Safe state read and write. @item @code{sve} @tab ARMv8.2-A @tab Armv9-A or later diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index ef59d531d17..5c9b5e5dac1 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -100,6 +100,7 @@ typedef uint32_t aarch64_insn; #define AARCH64_FEATURE_SME_I16I64 (1ULL << 58) /* SME I16I64. */ #define AARCH64_FEATURE_V8_8 (1ULL << 59) /* Armv8.8 processors. */ #define AARCH64_FEATURE_CSSC (1ULL << 60) /* Common Short Sequence Compression instructions. */ +#define AARCH64_FEATURE_SME2 (1ULL << 61) /* SME2. */ /* Crypto instructions are the combination of AES and SHA2. */ #define AARCH64_FEATURE_CRYPTO (AARCH64_FEATURE_SHA2 | AARCH64_FEATURE_AES) From patchwork Thu Mar 30 10:26:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 77090 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1038642vqo; Thu, 30 Mar 2023 04:02:40 -0700 (PDT) X-Google-Smtp-Source: AKy350ZBkx2FFl7S6LP5PGPfUHfKryZfKHhDrNNuxMDUBdrfNDW3bz4SC3uIUZyNfPMKEOIsCjCF X-Received: by 2002:a17:907:7f0c:b0:93f:870f:a9e2 with SMTP id qf12-20020a1709077f0c00b0093f870fa9e2mr21140925ejc.16.1680174160451; Thu, 30 Mar 2023 04:02:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680174160; cv=none; d=google.com; s=arc-20160816; b=SgviuR6M1cBK8kDHEiLH9KnUXiePIIkwDBC2+qqHaUpUav5B5xBcI6azyarvyKOzSz ppSjL+Z5Ga8BxfHBNm8HbBFzvHcgxdchgz0yfTP6B1UEo/Wflknb3ALFZ3Lw/U/luTMY gidZix/qMPz0+ws79+Ol8YAJMRqGeBqESmh+r2tWRqiyaxE9PV3ktfYGKgaVNK35SXEp Gnylaenqy1Dx5vvE3dw4QGpKENYptumZqFwCS8GwJjW/LtIG5XJjzANW002ATbXFERfC SPh2SkbC7gPcBLJoeV0H4mhTLpXE08GX9UVn9gs9N9j/Ea4Ejbr3DEYdjhfOwc9cArER ML0Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:dmarc-filter:delivered-to :dkim-signature:dkim-filter; bh=RkJX1nDuw427bW7jxalx2K0ABkqzZdEzS8Ay2rP7fqY=; b=zBLm5b9Qewduq9GUXABabwT2VrClocvygYvnUVVMZiKrxIhkCusf/bQsJJmFVx/qO3 eZoCy7xATDrD4GJ++JQnJZmq+qaHLo+Lz0BYE+5pYmf56y8VyVzkQLYtk+otAoI5Wt6u PwptoHs0No9m/C/7lrnAsCrSOYfz4rCU1v+EfXT26FWj+++SwBUU1q8MwneB/cueNXb3 xI9L26ZInOQFSV9UUI4E+b7GQoT1047kNFHIGc9oamIXTFz3KtfFeSdtnsyNU1HZhigf 46eD//W9ys5v/+ypk36G/YVe3/s/MWp3a0T7giKcIBx2XAg+OQWSoLSmD0r7J8Ap49yc dTmw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=Zou42Lgp; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id q23-20020a056402033700b004c10381668csi36023490edw.286.2023.03.30.04.02.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Mar 2023 04:02:40 -0700 (PDT) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=Zou42Lgp; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 8EE353AA9916 for ; Thu, 30 Mar 2023 10:43:12 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 8EE353AA9916 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1680172992; bh=RkJX1nDuw427bW7jxalx2K0ABkqzZdEzS8Ay2rP7fqY=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=Zou42LgpRky9ySRapvDI4HiUO4Nou7z132Yl4qOUmmmEfiFEwub8xqTEffn+emdYf egnEIW6G2VQC+Srduz0wmJ1kSikkrVStuaJ0F75ExkwesXBA9IpLTfQ2NK1nwNA/Bt zx4nVN3M3tX8TDybOK4G9ntjJM/F3TniPA9WcSro= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id EC7CD3881D0E for ; Thu, 30 Mar 2023 10:26:54 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org EC7CD3881D0E Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 19E3F1595; Thu, 30 Mar 2023 03:27:39 -0700 (PDT) Received: from e121540-lin.manchester.arm.com (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 4FA8B3F663; Thu, 30 Mar 2023 03:26:54 -0700 (PDT) To: binutils@sourceware.org Cc: Richard Sandiford Subject: [PATCH 02/31] aarch64: Add a _10 suffix to FLD_imm3 Date: Thu, 30 Mar 2023 11:26:17 +0100 Message-Id: <20230330102646.3327818-3-richard.sandiford@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230330102646.3327818-1-richard.sandiford@arm.com> References: <20230330102646.3327818-1-richard.sandiford@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-32.3 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KAM_NUMSUBJECT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Richard Sandiford via Binutils From: Richard Sandiford Reply-To: Richard Sandiford Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761790300875994906?= X-GMAIL-MSGID: =?utf-8?q?1761790300875994906?= SME2 adds various new 3-bit immediate fields, so this patch adds an lsb position suffix to the name of the field that we already have. --- opcodes/aarch64-asm.c | 4 ++-- opcodes/aarch64-dis.c | 4 ++-- opcodes/aarch64-opc-2.c | 2 +- opcodes/aarch64-opc.c | 2 +- opcodes/aarch64-opc.h | 2 +- opcodes/aarch64-tbl.h | 2 +- 6 files changed, 8 insertions(+), 8 deletions(-) diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c index 7351c2417b2..5a9ca5a980d 100644 --- a/opcodes/aarch64-asm.c +++ b/opcodes/aarch64-asm.c @@ -943,7 +943,7 @@ aarch64_ins_reg_extended (const aarch64_operand *self ATTRIBUTE_UNUSED, ? AARCH64_MOD_UXTW : AARCH64_MOD_UXTX; insert_field (FLD_option, code, aarch64_get_operand_modifier_value (kind), 0); /* imm3 */ - insert_field (FLD_imm3, code, info->shifter.amount, 0); + insert_field (FLD_imm3_10, code, info->shifter.amount, 0); return true; } @@ -1016,7 +1016,7 @@ aarch64_ins_sve_addr_ri_s9xvl (const aarch64_operand *self, int factor = 1 + get_operand_specific_data (self); insert_field (self->fields[0], code, info->addr.base_regno, 0); insert_fields (code, info->addr.offset.imm / factor, 0, - 2, FLD_imm3, FLD_SVE_imm6); + 2, FLD_imm3_10, FLD_SVE_imm6); return true; } diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c index e722514053e..49bfd46906e 100644 --- a/opcodes/aarch64-dis.c +++ b/opcodes/aarch64-dis.c @@ -1395,7 +1395,7 @@ aarch64_ext_reg_extended (const aarch64_operand *self ATTRIBUTE_UNUSED, info->shifter.kind = aarch64_get_operand_modifier_from_value (value, true /* extend_p */); /* imm3 */ - info->shifter.amount = extract_field (FLD_imm3, code, 0); + info->shifter.amount = extract_field (FLD_imm3_10, code, 0); /* This makes the constraint checking happy. */ info->shifter.operator_present = 1; @@ -1512,7 +1512,7 @@ aarch64_ext_sve_addr_ri_s9xvl (const aarch64_operand *self, { int offset; - offset = extract_fields (code, 0, 2, FLD_SVE_imm6, FLD_imm3); + offset = extract_fields (code, 0, 2, FLD_SVE_imm6, FLD_imm3_10); offset = (((offset + 256) & 511) - 256); return aarch64_ext_sve_addr_reg_mul_vl (self, info, code, offset); } diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c index 1d59a8bd332..fe67dbc9b62 100644 --- a/opcodes/aarch64-opc-2.c +++ b/opcodes/aarch64-opc-2.c @@ -214,7 +214,7 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm3}, "a 3-bit unsigned immediate"}, {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM7", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm7}, "a 7-bit unsigned immediate"}, {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM8", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm8}, "an 8-bit unsigned immediate"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM8_53", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm5,FLD_imm3}, "an 8-bit unsigned immediate"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM8_53", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm5,FLD_imm3_10}, "an 8-bit unsigned immediate"}, {AARCH64_OPND_CLASS_SIMD_REG, "SVE_VZn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "a SIMD register"}, {AARCH64_OPND_CLASS_SIMD_REG, "SVE_Vd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Vd}, "a SIMD register"}, {AARCH64_OPND_CLASS_SIMD_REG, "SVE_Vm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Vm}, "a SIMD register"}, diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 1a1e1bd22f3..969362a56cd 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -296,7 +296,7 @@ const aarch64_field fields[] = { 0, 4 }, /* cond2: condition in truly conditional-executed inst. */ { 5, 5 }, /* defgh: d:e:f:g:h bits in AdvSIMD modified immediate. */ { 21, 2 }, /* hw: in move wide constant instructions. */ - { 10, 3 }, /* imm3: in add/sub extended reg instructions. */ + { 10, 3 }, /* imm3_10: in add/sub extended reg instructions. */ { 0, 4 }, /* imm4_0: in rmif instructions. */ { 5, 4 }, /* imm4_5: in SME instructions. */ { 10, 4 }, /* imm4_10: in adddg/subg instructions. */ diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h index 3ded6ab7958..e142ae6ee76 100644 --- a/opcodes/aarch64-opc.h +++ b/opcodes/aarch64-opc.h @@ -124,7 +124,7 @@ enum aarch64_field_kind FLD_cond2, FLD_defgh, FLD_hw, - FLD_imm3, + FLD_imm3_10, FLD_imm4_0, FLD_imm4_5, FLD_imm4_10, diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 82f4af2839f..aa05ca0f4a9 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -5863,7 +5863,7 @@ const struct aarch64_opcode aarch64_opcode_table[] = "a 7-bit unsigned immediate") \ Y(IMMEDIATE, imm, "SVE_UIMM8", 0, F(FLD_SVE_imm8), \ "an 8-bit unsigned immediate") \ - Y(IMMEDIATE, imm, "SVE_UIMM8_53", 0, F(FLD_imm5,FLD_imm3), \ + Y(IMMEDIATE, imm, "SVE_UIMM8_53", 0, F(FLD_imm5,FLD_imm3_10), \ "an 8-bit unsigned immediate") \ Y(SIMD_REG, regno, "SVE_VZn", 0, F(FLD_SVE_Zn), "a SIMD register") \ Y(SIMD_REG, regno, "SVE_Vd", 0, F(FLD_SVE_Vd), "a SIMD register") \ From patchwork Thu Mar 30 10:26:18 2023 Content-Type: text/plain; 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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id r9-20020aa7cb89000000b004fb4859cd4csi35866023edt.562.2023.03.30.03.52.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Mar 2023 03:52:17 -0700 (PDT) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=WiaNNOE6; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 1FA9339540BC for ; Thu, 30 Mar 2023 10:37:12 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 1FA9339540BC DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1680172632; bh=bBZg6/iKyDKxKa1CCv+EwOX4Rcrc4NzLZyCJsVnZNp0=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=WiaNNOE6u++CCJdFSJEuRzJ4OGY3MThBaknbgPc3Z3J7tm2l18w+9tzv40tjVUsGx LlANaHqqXjOMs/EFe+Fgm6jVggKAUKj1fLODMb7qMCwO5O5lV9NrLzcySuQ+q+ZKtV fio4OTcDn9olPCaHZnn1ntSE/1reI0l8J9gO372E= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id A58A63851C01 for ; Thu, 30 Mar 2023 10:26:55 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org A58A63851C01 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BF0291596; Thu, 30 Mar 2023 03:27:39 -0700 (PDT) Received: from e121540-lin.manchester.arm.com (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 01F443F663; Thu, 30 Mar 2023 03:26:54 -0700 (PDT) To: binutils@sourceware.org Cc: Richard Sandiford Subject: [PATCH 03/31] aarch64: Add _off4 suffix to AARCH64_OPND_SME_ZA_array Date: Thu, 30 Mar 2023 11:26:18 +0100 Message-Id: <20230330102646.3327818-4-richard.sandiford@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230330102646.3327818-1-richard.sandiford@arm.com> References: <20230330102646.3327818-1-richard.sandiford@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-32.5 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Richard Sandiford via Binutils From: Richard Sandiford Reply-To: Richard Sandiford Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761789646802425913?= X-GMAIL-MSGID: =?utf-8?q?1761789646802425913?= SME2 adds various new fields that are similar to AARCH64_OPND_SME_ZA_array, but are distinguished by the size of their offset fields. This patch adds _off4 to the name of the field that we already have. --- gas/config/tc-aarch64.c | 2 +- include/opcode/aarch64.h | 6 +++--- opcodes/aarch64-opc-2.c | 2 +- opcodes/aarch64-opc.c | 6 +++--- opcodes/aarch64-tbl.h | 6 +++--- 5 files changed, 11 insertions(+), 11 deletions(-) diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 6ebfcda7dff..b4e0b937605 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -7647,7 +7647,7 @@ parse_operands (char *str, const aarch64_opcode *opcode) info->imm.value = val; break; - case AARCH64_OPND_SME_ZA_array: + case AARCH64_OPND_SME_ZA_array_off4: if (!parse_dual_indexed_reg (&str, REG_TYPE_ZA, &info->indexed_za, &qualifier, 0)) goto failure; diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 5c9b5e5dac1..94584668517 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -487,11 +487,11 @@ enum aarch64_opnd AARCH64_OPND_SME_ZA_HV_idx_dest, /* SME destination ZA tile vector. */ AARCH64_OPND_SME_Pm, /* SME scalable predicate register, bits [15:13]. */ AARCH64_OPND_SME_list_of_64bit_tiles, /* SME list of ZA tiles. */ - AARCH64_OPND_SME_ZA_HV_idx_ldstr, /* SME destination ZA tile vector. */ - AARCH64_OPND_SME_ZA_array, /* SME ZA[{, #}]. */ + AARCH64_OPND_SME_ZA_HV_idx_ldstr, /* SME destination ZA tile vector. */ + AARCH64_OPND_SME_ZA_array_off4, /* SME ZA[{, #}]. */ AARCH64_OPND_SME_ADDR_RI_U4xVL, /* SME [{, #, MUL VL}]. */ AARCH64_OPND_SME_SM_ZA, /* SME {SM | ZA}. */ - AARCH64_OPND_SME_PnT_Wm_imm, /* SME .[, #]. */ + AARCH64_OPND_SME_PnT_Wm_imm, /* SME .[, #]. */ AARCH64_OPND_TME_UIMM16, /* TME unsigned 16-bit immediate. */ AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */ AARCH64_OPND_MOPS_ADDR_Rd, /* [Rd]!, in bits [0, 4]. */ diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c index fe67dbc9b62..65ce8d42b0a 100644 --- a/opcodes/aarch64-opc-2.c +++ b/opcodes/aarch64-opc-2.c @@ -241,7 +241,7 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_PRED_REG, "SME_Pm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Pm}, "an SVE predicate register"}, {AARCH64_OPND_CLASS_SVE_REG, "SME_list_of_64bit_tiles", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_zero_mask}, "a list of 64-bit ZA element tiles"}, {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_ldstr", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_22,FLD_index2,FLD_SME_V,FLD_SME_Rv,FLD_imm4_0}, "an SME horizontal or vertical vector access register"}, - {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rv,FLD_imm4_0}, "ZA array"}, + {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_off4", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rv,FLD_imm4_0}, "ZA array"}, {AARCH64_OPND_CLASS_ADDRESS, "SME_ADDR_RI_U4xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_imm4_0}, "memory offset"}, {AARCH64_OPND_CLASS_ADDRESS, "SME_SM_ZA", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm}, "streaming mode"}, {AARCH64_OPND_CLASS_SVE_REG, "SME_PnT_Wm_imm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rm,FLD_SVE_Pn,FLD_SME_i1,FLD_SME_tszh,FLD_SME_tszl}, "Source scalable predicate register with index "}, diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 969362a56cd..e97201bb03a 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -1684,7 +1684,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, return 0; break; - case AARCH64_OPND_SME_ZA_array: + case AARCH64_OPND_SME_ZA_array_off4: if (!check_za_access (opnd, mismatch_detail, idx, 12, 15)) return 0; break; @@ -2882,7 +2882,7 @@ aarch64_match_operands_constraint (aarch64_inst *inst, */ case sme_ldr: case sme_str: - assert (inst->operands[0].type == AARCH64_OPND_SME_ZA_array); + assert (inst->operands[0].type == AARCH64_OPND_SME_ZA_array_off4); assert (inst->operands[1].type == AARCH64_OPND_SME_ADDR_RI_U4xVL); if (inst->operands[0].indexed_za.index.imm != inst->operands[1].addr.offset.imm) @@ -3686,7 +3686,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, print_sme_za_list (buf, size, opnd->reg.regno, styler); break; - case AARCH64_OPND_SME_ZA_array: + case AARCH64_OPND_SME_ZA_array_off4: snprintf (buf, size, "%s[%s, %s]", style_reg (styler, "za"), style_reg (styler, "w%d", opnd->indexed_za.index.regno), diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index aa05ca0f4a9..75497ea6065 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -5265,8 +5265,8 @@ const struct aarch64_opcode aarch64_opcode_table[] = SME_INSN ("st1d", 0xe0e00000, 0xffe00010, sve_misc, 0, OP3 (SME_ZA_HV_idx_ldstr, SVE_Pg3, SVE_ADDR_R), OP_SVE_DUU, 0, 0), SME_INSN ("st1q", 0xe1e00000, 0xffe00010, sve_misc, 0, OP3 (SME_ZA_HV_idx_ldstr, SVE_Pg3, SVE_ADDR_R), OP_SVE_QUU, 0, 0), - SME_INSN ("ldr", 0xe1000000, 0xffff9c10, sme_ldr, 0, OP2 (SME_ZA_array, SME_ADDR_RI_U4xVL), {}, 0, 1), - SME_INSN ("str", 0xe1200000, 0xffff9c10, sme_str, 0, OP2 (SME_ZA_array, SME_ADDR_RI_U4xVL), {}, 0, 1), + SME_INSN ("ldr", 0xe1000000, 0xffff9c10, sme_ldr, 0, OP2 (SME_ZA_array_off4, SME_ADDR_RI_U4xVL), {}, 0, 1), + SME_INSN ("str", 0xe1200000, 0xffff9c10, sme_str, 0, OP2 (SME_ZA_array_off4, SME_ADDR_RI_U4xVL), {}, 0, 1), SME_INSNC ("revd", 0x52e8000, 0xffffe000, sme_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_QMQ, 0, C_SCAN_MOVPRFX, 0), SME_INSNC ("sclamp", 0x4400c000, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, C_SCAN_MOVPRFX, 0), @@ -5921,7 +5921,7 @@ const struct aarch64_opcode aarch64_opcode_table[] = Y(ZA_ACCESS, sme_za_hv_tiles, "SME_ZA_HV_idx_ldstr", 0, \ F(FLD_SME_size_22,FLD_index2,FLD_SME_V,FLD_SME_Rv,FLD_imm4_0), \ "an SME horizontal or vertical vector access register") \ - Y(ZA_ACCESS, sme_za_array, "SME_ZA_array", 0, \ + Y(ZA_ACCESS, sme_za_array, "SME_ZA_array_off4", 0, \ F(FLD_SME_Rv,FLD_imm4_0), "ZA array") \ Y(ADDRESS, sme_addr_ri_u4xvl, "SME_ADDR_RI_U4xVL", 0 << OPD_F_OD_LSB, \ F(FLD_Rn,FLD_imm4_0), "memory offset") \ From patchwork Thu Mar 30 10:26:19 2023 Content-Type: text/plain; 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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id n24-20020a05640206d800b004aaa505ac5fsi39330867edy.76.2023.03.30.03.59.05 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Mar 2023 03:59:05 -0700 (PDT) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=Ut0FKpCu; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id B9C2C38A90B5 for ; Thu, 30 Mar 2023 10:40:50 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org B9C2C38A90B5 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1680172850; bh=aVFudG0EFqN+kN8znp6oNy8eYJl3OoZ3X1V9tK6F75k=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=Ut0FKpCuFHJBehLt+NOVLtIpxYQ1WuQIBWQYcXmeIOSJgkSIGKnvp/2pWaFc6oP46 mWt/beDFzO7qlunB4eSe+8y+xw+AT6gyThMfDWHFY+uykqyjtTzlLiEqoUZzUzc7ei exjgqxyxdsn84ayKzyZshj09aKbDuoVXY5bW48XY= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 7A9993895FDF for ; Thu, 30 Mar 2023 10:26:56 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 7A9993895FDF Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 969FD12FC; Thu, 30 Mar 2023 03:27:40 -0700 (PDT) Received: from e121540-lin.manchester.arm.com (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A934A3F663; Thu, 30 Mar 2023 03:26:55 -0700 (PDT) To: binutils@sourceware.org Cc: Richard Sandiford Subject: [PATCH 04/31] aarch64: Add support for vgx2 and vgx4 Date: Thu, 30 Mar 2023 11:26:19 +0100 Message-Id: <20230330102646.3327818-5-richard.sandiford@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230330102646.3327818-1-richard.sandiford@arm.com> References: <20230330102646.3327818-1-richard.sandiford@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-32.2 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KAM_NUMSUBJECT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Richard Sandiford via Binutils From: Richard Sandiford Reply-To: Richard Sandiford Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761790075350703093?= X-GMAIL-MSGID: =?utf-8?q?1761790075350703093?= Many SME2 instructions operate on groups of 2 or 4 ZA vectors. This is indicated by adding a "vgx2" or "vgx4" group size to the ZA index. The group size is optional in assembly but preferred for disassembly. There is not a binary distinction between mnemonics that have group sizes and mnemonics that don't, nor between mnemonics that take vgx2 and mnemonics that take vgx4. We therefore get better error messages if we allow any ZA index to have a group size during parsing, and wait until constraint checking to reject invalid sizes. A quirk of the way errors are reported means that if an instruction is wrong both in its qualifiers and its use of a group size, we'll print suggested alternative instructions that also have an incorrect group size. But that's a general property that also applies to things like out-of-range immediates. It's also not obviously the wrong thing to do. We need to be relatively confident that we're looking at the right opcode before reporting detailed operand-specific errors, so doing qualifier checking first seems resonable. --- gas/config/tc-aarch64.c | 33 ++++++++++++++- gas/testsuite/gas/aarch64/sme-2-illegal.l | 3 ++ gas/testsuite/gas/aarch64/sme-2-illegal.s | 4 ++ gas/testsuite/gas/aarch64/sme-3-illegal.l | 11 +++++ gas/testsuite/gas/aarch64/sme-3-illegal.s | 6 +++ gas/testsuite/gas/aarch64/sme-5-illegal.l | 6 +++ gas/testsuite/gas/aarch64/sme-5-illegal.s | 6 +++ gas/testsuite/gas/aarch64/sme-6-illegal.l | 6 +++ gas/testsuite/gas/aarch64/sme-6-illegal.s | 6 +++ gas/testsuite/gas/aarch64/sme-7-illegal.l | 12 ++++++ gas/testsuite/gas/aarch64/sme-7-illegal.s | 11 +++++ gas/testsuite/gas/aarch64/sme-9-illegal.l | 10 +++++ gas/testsuite/gas/aarch64/sme-9-illegal.s | 6 +++ include/opcode/aarch64.h | 13 ++++++ opcodes/aarch64-opc.c | 49 +++++++++++++++++++---- 15 files changed, 173 insertions(+), 9 deletions(-) diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index b4e0b937605..2d732ea1780 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -4550,6 +4550,26 @@ parse_sme_za_index (char **str, struct aarch64_indexed_za *opnd) return false; } + opnd->group_size = 0; + if (skip_past_char (str, ',')) + { + if (strncasecmp (*str, "vgx2", 4) == 0 && !ISALPHA ((*str)[4])) + { + *str += 4; + opnd->group_size = 2; + } + else if (strncasecmp (*str, "vgx4", 4) == 0 && !ISALPHA ((*str)[4])) + { + *str += 4; + opnd->group_size = 4; + } + else + { + set_syntax_error (_("invalid vector group size")); + return false; + } + } + if (!skip_past_char (str, ']')) { set_syntax_error (_("expected ']'")); @@ -5067,6 +5087,7 @@ const char* operand_mismatch_kind_names[] = "AARCH64_OPDE_SYNTAX_ERROR", "AARCH64_OPDE_FATAL_SYNTAX_ERROR", "AARCH64_OPDE_INVALID_VARIANT", + "AARCH64_OPDE_INVALID_VG_SIZE", "AARCH64_OPDE_REG_LIST_LENGTH", "AARCH64_OPDE_REG_LIST_STRIDE", "AARCH64_OPDE_UNTIED_IMMS", @@ -5095,7 +5116,8 @@ operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs, gas_assert (AARCH64_OPDE_SYNTAX_ERROR > AARCH64_OPDE_EXPECTED_A_AFTER_B); gas_assert (AARCH64_OPDE_FATAL_SYNTAX_ERROR > AARCH64_OPDE_SYNTAX_ERROR); gas_assert (AARCH64_OPDE_INVALID_VARIANT > AARCH64_OPDE_FATAL_SYNTAX_ERROR); - gas_assert (AARCH64_OPDE_REG_LIST_LENGTH > AARCH64_OPDE_INVALID_VARIANT); + gas_assert (AARCH64_OPDE_INVALID_VG_SIZE > AARCH64_OPDE_INVALID_VARIANT); + gas_assert (AARCH64_OPDE_REG_LIST_LENGTH > AARCH64_OPDE_INVALID_VG_SIZE); gas_assert (AARCH64_OPDE_REG_LIST_STRIDE > AARCH64_OPDE_REG_LIST_LENGTH); gas_assert (AARCH64_OPDE_OUT_OF_RANGE > AARCH64_OPDE_REG_LIST_STRIDE); gas_assert (AARCH64_OPDE_UNALIGNED > AARCH64_OPDE_OUT_OF_RANGE); @@ -5749,6 +5771,15 @@ output_operand_error_record (const operand_error_record *record, char *str) detail->data[0].i, idx + 1, str); break; + case AARCH64_OPDE_INVALID_VG_SIZE: + if (detail->data[0].i == 0) + handler (_("unexpected vector group size at operand %d -- `%s'"), + idx + 1, str); + else + handler (_("operand %d must have a vector group size of %d -- `%s'"), + idx + 1, detail->data[0].i, str); + break; + case AARCH64_OPDE_REG_LIST_LENGTH: if (detail->data[0].i == (1 << 1)) handler (_("expected a single-register list at operand %d -- `%s'"), diff --git a/gas/testsuite/gas/aarch64/sme-2-illegal.l b/gas/testsuite/gas/aarch64/sme-2-illegal.l index 1df18ef2002..fd36ed78381 100644 --- a/gas/testsuite/gas/aarch64/sme-2-illegal.l +++ b/gas/testsuite/gas/aarch64/sme-2-illegal.l @@ -25,3 +25,6 @@ [^:]*:[0-9]+: Error: expected '\]' at operand 3 -- `mova z0\.q,p0/m,za0v\.q\[w12,#1a\]' [^:]*:[0-9]+: Error: expected '\]' at operand 3 -- `mova z0\.q,p0/m,za0v\.q\[w12,1a2\]' [^:]*:[0-9]+: Error: expected '\]' at operand 3 -- `mova z0\.q,p0/m,za0v\.q\[w12,#1a2\]' +[^:]*:[0-9]+: Error: unexpected vector group size at operand 3 -- `mova z0.b,p0/m,za0h.b\[w12,#0,vgx2\]' +[^:]*:[0-9]+: Error: unexpected vector group size at operand 3 -- `mova z0.b,p0/m,za0h.b\[w12,#0,vgx4\]' +[^:]*:[0-9]+: Error: invalid vector group size at operand 3 -- `mova z0.b,p0/m,za0h.b\[w12,#0,vgx8\]' diff --git a/gas/testsuite/gas/aarch64/sme-2-illegal.s b/gas/testsuite/gas/aarch64/sme-2-illegal.s index 28eb6719c91..8cc130ac9c0 100644 --- a/gas/testsuite/gas/aarch64/sme-2-illegal.s +++ b/gas/testsuite/gas/aarch64/sme-2-illegal.s @@ -30,3 +30,7 @@ mova z0.q, p0/m, za0v.q[w12, 1a] mova z0.q, p0/m, za0v.q[w12, #1a] mova z0.q, p0/m, za0v.q[w12, 1a2] mova z0.q, p0/m, za0v.q[w12, #1a2] + +mova z0.b, p0/m, za0h.b[w12, #0, vgx2] +mova z0.b, p0/m, za0h.b[w12, #0, vgx4] +mova z0.b, p0/m, za0h.b[w12, #0, vgx8] diff --git a/gas/testsuite/gas/aarch64/sme-3-illegal.l b/gas/testsuite/gas/aarch64/sme-3-illegal.l index 717af3b54be..f5fb169b78a 100644 --- a/gas/testsuite/gas/aarch64/sme-3-illegal.l +++ b/gas/testsuite/gas/aarch64/sme-3-illegal.l @@ -9,3 +9,14 @@ [^:]*:[0-9]+: Error: immediate offset out of range 0 to 3 at operand 1 -- `mova za3v\.s\[w15,#4\],p7/m,z31.s' [^:]*:[0-9]+: Error: immediate offset out of range 0 to 1 at operand 1 -- `mova za7v\.d\[w15,#2\],p7/m,z31.d' [^:]*:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `mova za15v\.q\[w15,#1\],p7/m,z31.q' +[^:]*:[0-9]+: Error: unexpected vector group size at operand 1 -- `mova za0h\.b\[w12,#0,vgx2\],p0/m,z0\.b' +[^:]*:[0-9]+: Error: unexpected vector group size at operand 1 -- `mova za0h\.b\[w12,#0,vgx4\],p0/m,z0\.b' +[^:]*:[0-9]+: Error: invalid vector group size at operand 1 -- `mova za0h\.b\[w12,#0,vgx8\],p0/m,z0\.b' +[^:]*:[0-9]+: Error: operand mismatch -- `mova za0h\.b\[w12,#0,vgx2\],p0/z,z0\.b' +[^:]*:[0-9]+: Info: did you mean this\? +[^:]*:[0-9]+: Info: mova za0h\.b\[w12, 0, vgx2\], p0/m, z0\.b +[^:]*:[0-9]+: Info: other valid variant\(s\): +[^:]*:[0-9]+: Info: mova za0h\.h\[w12, 0, vgx2\], p0/m, z0\.h +[^:]*:[0-9]+: Info: mova za0h\.s\[w12, 0, vgx2\], p0/m, z0\.s +[^:]*:[0-9]+: Info: mova za0h\.d\[w12, 0, vgx2\], p0/m, z0\.d +[^:]*:[0-9]+: Info: mova za0h\.q\[w12, 0, vgx2\], p0/m, z0\.q diff --git a/gas/testsuite/gas/aarch64/sme-3-illegal.s b/gas/testsuite/gas/aarch64/sme-3-illegal.s index 6ed58ec60a1..aeeaf549e8f 100644 --- a/gas/testsuite/gas/aarch64/sme-3-illegal.s +++ b/gas/testsuite/gas/aarch64/sme-3-illegal.s @@ -12,3 +12,9 @@ mova za1v.h[w15, #8], p7/m, z31.h mova za3v.s[w15, #4], p7/m, z31.s mova za7v.d[w15, #2], p7/m, z31.d mova za15v.q[w15, #1], p7/m, z31.q + +mova za0h.b[w12, #0, vgx2], p0/m, z0.b +mova za0h.b[w12, #0, vgx4], p0/m, z0.b +mova za0h.b[w12, #0, vgx8], p0/m, z0.b + +mova za0h.b[w12, #0, vgx2], p0/z, z0.b diff --git a/gas/testsuite/gas/aarch64/sme-5-illegal.l b/gas/testsuite/gas/aarch64/sme-5-illegal.l index f892dcd2090..f6eda9da5e2 100644 --- a/gas/testsuite/gas/aarch64/sme-5-illegal.l +++ b/gas/testsuite/gas/aarch64/sme-5-illegal.l @@ -56,3 +56,9 @@ [^:]*:[0-9]+: Error: missing braces at operand 1 -- `ld1w za0h.s\[w12,0\],p0/z,\[x0\]' [^:]*:[0-9]+: Error: missing braces at operand 1 -- `ld1d za0h.d\[w12,0\],p0/z,\[x0\]' [^:]*:[0-9]+: Error: missing braces at operand 1 -- `ld1q za0h.q\[w12,0\],p0/z,\[x0\]' +[^:]*:[0-9]+: Error: unexpected vector group size at operand 1 -- `ld1b {za0h\.b\[w12,0,vgx2\]},p0/z,\[x0\]' +[^:]*:[0-9]+: Error: unexpected vector group size at operand 1 -- `ld1b {za0h\.b\[w12,0,vgx4\]},p0/z,\[x0\]' +[^:]*:[0-9]+: Error: invalid vector group size at operand 1 -- `ld1b {za0h\.b\[w12,0,vgx8\]},p0/z,\[x0\]' +[^:]*:[0-9]+: Error: operand mismatch -- `ld1b {za0h\.b\[w12,0,vgx4\]},p0/m,\[x0\]' +[^:]*:[0-9]+: Info: did you mean this\? +[^:]*:[0-9]+: Info: ld1b {za0h\.b\[w12, 0, vgx4\]}, p0/z, \[x0, xzr\] diff --git a/gas/testsuite/gas/aarch64/sme-5-illegal.s b/gas/testsuite/gas/aarch64/sme-5-illegal.s index 29f86669043..9dbce626a6e 100644 --- a/gas/testsuite/gas/aarch64/sme-5-illegal.s +++ b/gas/testsuite/gas/aarch64/sme-5-illegal.s @@ -57,3 +57,9 @@ ld1h za0h.h[w12, 0], p0/z, [x0] ld1w za0h.s[w12, 0], p0/z, [x0] ld1d za0h.d[w12, 0], p0/z, [x0] ld1q za0h.q[w12, 0], p0/z, [x0] + +ld1b {za0h.b[w12, 0, vgx2]}, p0/z, [x0] +ld1b {za0h.b[w12, 0, vgx4]}, p0/z, [x0] +ld1b {za0h.b[w12, 0, vgx8]}, p0/z, [x0] + +ld1b {za0h.b[w12, 0, vgx4]}, p0/m, [x0] diff --git a/gas/testsuite/gas/aarch64/sme-6-illegal.l b/gas/testsuite/gas/aarch64/sme-6-illegal.l index c8141e086ab..bc0d19417fc 100644 --- a/gas/testsuite/gas/aarch64/sme-6-illegal.l +++ b/gas/testsuite/gas/aarch64/sme-6-illegal.l @@ -43,3 +43,9 @@ [^:]*:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `st1q {za15h.q\[w15,1\]},p7,\[sp\]' [^:]*:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `st1q {za15v.q\[w15,1\]},p7,\[x0,x17,lsl#4\]' [^:]*:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `st1q {za15h.q\[w15,1\]},p7,\[sp,x17,lsl#4\]' +[^:]*:[0-9]+: Error: unexpected vector group size at operand 1 -- `st1b {za0h.b\[w12,0,vgx2\]},p0,\[x0\]' +[^:]*:[0-9]+: Error: unexpected vector group size at operand 1 -- `st1b {za0h\.b\[w12,0,vgx4\]},p0,\[x0\]' +[^:]*:[0-9]+: Error: invalid vector group size at operand 1 -- `st1b {za0h\.b\[w12,0,vgx8\]},p0,\[x0\]' +[^:]*:[0-9]+: Error: operand mismatch -- `st1b {za0h\.b\[w12,0,vgx2\]},p0/z,\[x0\]' +[^:]*:[0-9]+: Info: did you mean this\? +[^:]*:[0-9]+: Info: st1b {za0h\.b\[w12, 0, vgx2\]}, p0, \[x0, xzr\] diff --git a/gas/testsuite/gas/aarch64/sme-6-illegal.s b/gas/testsuite/gas/aarch64/sme-6-illegal.s index d0de01d5a6c..04a508821bc 100644 --- a/gas/testsuite/gas/aarch64/sme-6-illegal.s +++ b/gas/testsuite/gas/aarch64/sme-6-illegal.s @@ -44,3 +44,9 @@ st1q {za15v.q[w15, 1]}, p7, [x17] st1q {za15h.q[w15, 1]}, p7, [sp] st1q {za15v.q[w15, 1]}, p7, [x0, x17, lsl #4] st1q {za15h.q[w15, 1]}, p7, [sp, x17, lsl #4] + +st1b {za0h.b[w12, 0, vgx2]}, p0, [x0] +st1b {za0h.b[w12, 0, vgx4]}, p0, [x0] +st1b {za0h.b[w12, 0, vgx8]}, p0, [x0] + +st1b {za0h.b[w12, 0, vgx2]}, p0/z, [x0] diff --git a/gas/testsuite/gas/aarch64/sme-7-illegal.l b/gas/testsuite/gas/aarch64/sme-7-illegal.l index 0023a84da71..eb0c5e6f51a 100644 --- a/gas/testsuite/gas/aarch64/sme-7-illegal.l +++ b/gas/testsuite/gas/aarch64/sme-7-illegal.l @@ -54,3 +54,15 @@ [^:]*:[0-9]+: Error: expected 'za' rather than a ZA tile at operand 1 -- `ldr za0h.h\[w12,0\],\[x0\]' [^:]*:[0-9]+: Error: expected 'za' rather than a ZA tile at operand 1 -- `ldr za0v\[w12,0\],\[x0\]' [^:]*:[0-9]+: Error: expected 'za' rather than a ZA tile at operand 1 -- `ldr za0v.s\[w12,0\],\[x0\]' +[^:]*:[0-9]+: Error: unexpected vector group size at operand 1 -- `ldr za\[w12,0,vgx2\],\[x0\]' +[^:]*:[0-9]+: Error: unexpected vector group size at operand 1 -- `ldr za\[w12,0,vgx4\],\[x0\]' +[^:]*:[0-9]+: Error: invalid vector group size at operand 1 -- `ldr za\[w12,0,vgx8\],\[x0\]' +[^:]*:[0-9]+: Error: unexpected vector group size at operand 1 -- `str za\[w12,0,vgx2\],\[x0\]' +[^:]*:[0-9]+: Error: unexpected vector group size at operand 1 -- `str za\[w12,0,vgx4\],\[x0\]' +[^:]*:[0-9]+: Error: invalid vector group size at operand 1 -- `str za\[w12,0,vgx8\],\[x0\]' +[^:]*:[0-9]+: Error: operand mismatch -- `ldr za\.b\[w12,0,vgx2\],\[x0\]' +[^:]*:[0-9]+: Info: did you mean this\? +[^:]*:[0-9]+: Info: ldr za\[w12, 0, vgx2\], \[x0\] +[^:]*:[0-9]+: Error: operand mismatch -- `str za\.b\[w12,0,vgx4\],\[x0\]' +[^:]*:[0-9]+: Info: did you mean this\? +[^:]*:[0-9]+: Info: str za\[w12, 0, vgx4\], \[x0\] diff --git a/gas/testsuite/gas/aarch64/sme-7-illegal.s b/gas/testsuite/gas/aarch64/sme-7-illegal.s index 75e2810e647..05d7d23fe29 100644 --- a/gas/testsuite/gas/aarch64/sme-7-illegal.s +++ b/gas/testsuite/gas/aarch64/sme-7-illegal.s @@ -52,3 +52,14 @@ ldr za0h[w12, 0], [x0] ldr za0h.h[w12, 0], [x0] ldr za0v[w12, 0], [x0] ldr za0v.s[w12, 0], [x0] + +ldr za[w12, 0, vgx2], [x0] +ldr za[w12, 0, vgx4], [x0] +ldr za[w12, 0, vgx8], [x0] + +str za[w12, 0, vgx2], [x0] +str za[w12, 0, vgx4], [x0] +str za[w12, 0, vgx8], [x0] + +ldr za.b[w12, 0, vgx2], [x0] +str za.b[w12, 0, vgx4], [x0] diff --git a/gas/testsuite/gas/aarch64/sme-9-illegal.l b/gas/testsuite/gas/aarch64/sme-9-illegal.l index 0243c9efcdf..d7aff825288 100644 --- a/gas/testsuite/gas/aarch64/sme-9-illegal.l +++ b/gas/testsuite/gas/aarch64/sme-9-illegal.l @@ -27,6 +27,16 @@ [^:]*:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 3 -- `psel p1,p8,p6.h\[w14,#8\]' [^:]*:[0-9]+: Error: immediate offset out of range 0 to 3 at operand 3 -- `psel p8,p4,p15.s\[w13,#4\]' [^:]*:[0-9]+: Error: immediate offset out of range 0 to 1 at operand 3 -- `psel p1,p1,p1.d\[w12,#2\]' +[^:]*:[0-9]+: Error: unexpected vector group size at operand 3 -- `psel p0,p0,p0\.b\[w12,#0,vgx2\]' +[^:]*:[0-9]+: Error: unexpected vector group size at operand 3 -- `psel p0,p0,p0\.b\[w12,#0,vgx4\]' +[^:]*:[0-9]+: Error: invalid vector group size at operand 3 -- `psel p0,p0,p0\.b\[w12,#0,vgx8\]' +[^:]*:[0-9]+: Error: operand mismatch -- `psel p0\.b,p0\.b,p0\.b\[w12,#0,vgx2\]' +[^:]*:[0-9]+: Info: did you mean this\? +[^:]*:[0-9]+: Info: psel p0, p0, p0\.b\[w12, 0\] +[^:]*:[0-9]+: Info: other valid variant\(s\): +[^:]*:[0-9]+: Info: psel p0, p0, p0\.h\[w12, 0\] +[^:]*:[0-9]+: Info: psel p0, p0, p0\.s\[w12, 0\] +[^:]*:[0-9]+: Info: psel p0, p0, p0\.d\[w12, 0\] [^:]*:[0-9]+: Error: operand mismatch -- `revd z0.q,p0/m,z0.b' [^:]*:[0-9]+: Info: did you mean this\? [^:]*:[0-9]+: Info: revd z0.q, p0/m, z0.q diff --git a/gas/testsuite/gas/aarch64/sme-9-illegal.s b/gas/testsuite/gas/aarch64/sme-9-illegal.s index f59582eeb8b..8f41298cd3c 100644 --- a/gas/testsuite/gas/aarch64/sme-9-illegal.s +++ b/gas/testsuite/gas/aarch64/sme-9-illegal.s @@ -17,6 +17,12 @@ psel p1, p8, p6.h[w14, #8] psel p8, p4, p15.s[w13, #4] psel p1, p1, p1.d[w12, #2] +psel p0, p0, p0.b[w12, #0, vgx2] +psel p0, p0, p0.b[w12, #0, vgx4] +psel p0, p0, p0.b[w12, #0, vgx8] + +psel p0.b, p0.b, p0.b[w12, #0, vgx2] + revd z0.q, p0/m, z0.b sclamp z8.b, z1.b, z31.q diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 94584668517..534bdaa869f 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -1120,6 +1120,7 @@ struct aarch64_indexed_za int regno; /* */ int64_t imm; /* */ } index; + unsigned group_size : 8; unsigned v : 1; /* horizontal or vertical vector indicator. */ }; @@ -1294,6 +1295,17 @@ struct aarch64_inst The following errors are only reported against an asm string that is syntactically valid and that has valid operand qualifiers. + AARCH64_OPDE_INVALID_VG_SIZE + Error about a "VGx" modifier in a ZA index not having the + correct . This error effectively forms a pair with + AARCH64_OPDE_REG_LIST_LENGTH, since both errors relate to the number + of vectors that an instruction operates on. However, the "VGx" + modifier is optional, whereas a register list always has a known + and explicit length. It therefore seems better to place more + importance on the register list length when selecting an opcode table + entry. This in turn means that having an incorrect register length + should be more severe than having an incorrect "VGx". + AARCH64_OPDE_REG_LIST_LENGTH Error about a register list operand having an unexpected number of registers. This error is low severity because there might be another @@ -1356,6 +1368,7 @@ enum aarch64_operand_error_kind AARCH64_OPDE_SYNTAX_ERROR, AARCH64_OPDE_FATAL_SYNTAX_ERROR, AARCH64_OPDE_INVALID_VARIANT, + AARCH64_OPDE_INVALID_VG_SIZE, AARCH64_OPDE_REG_LIST_LENGTH, AARCH64_OPDE_REG_LIST_STRIDE, AARCH64_OPDE_UNTIED_IMMS, diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index e97201bb03a..0d38ff250c4 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -1458,6 +1458,16 @@ set_reg_list_stride_error (aarch64_operand_error *mismatch_detail, int idx, mismatch_detail->data[0].i = 1 << expected_num; } +static inline void +set_invalid_vg_size (aarch64_operand_error *mismatch_detail, + int idx, int expected) +{ + if (mismatch_detail == NULL) + return; + set_error (mismatch_detail, AARCH64_OPDE_INVALID_VG_SIZE, idx, NULL); + mismatch_detail->data[0].i = expected; +} + static inline void set_other_error (aarch64_operand_error *mismatch_detail, int idx, const char* error) @@ -1517,12 +1527,14 @@ check_reglist (const aarch64_opnd_info *opnd, - a selection register in the range [MIN_WREG, MIN_WREG + 3] - - an immediate offset in the range [0, MAX_VALUE]. */ + - an immediate offset in the range [0, MAX_VALUE]. + + - a vector group size of GROUP_SIZE. */ static bool check_za_access (const aarch64_opnd_info *opnd, aarch64_operand_error *mismatch_detail, int idx, - int min_wreg, int max_value) + int min_wreg, int max_value, int group_size) { if (!value_in_range_p (opnd->indexed_za.index.regno, min_wreg, min_wreg + 3)) { @@ -1540,6 +1552,15 @@ check_za_access (const aarch64_opnd_info *opnd, set_offset_out_of_range_error (mismatch_detail, idx, 0, max_value); return false; } + + /* The vector group specifier is optional in assembly code. */ + if (opnd->indexed_za.group_size != 0 + && opnd->indexed_za.group_size != group_size) + { + set_invalid_vg_size (mismatch_detail, idx, group_size); + return false; + } + return true; } @@ -1657,7 +1678,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, case AARCH64_OPND_SME_PnT_Wm_imm: size = aarch64_get_qualifier_esize (opnd->qualifier); max_value = 16 / size - 1; - if (!check_za_access (opnd, mismatch_detail, idx, 12, max_value)) + if (!check_za_access (opnd, mismatch_detail, idx, 12, max_value, 0)) return 0; break; @@ -1680,12 +1701,14 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, case AARCH64_OPND_SME_ZA_HV_idx_ldstr: size = aarch64_get_qualifier_esize (opnd->qualifier); max_value = 16 / size - 1; - if (!check_za_access (opnd, mismatch_detail, idx, 12, max_value)) + if (!check_za_access (opnd, mismatch_detail, idx, 12, max_value, + get_opcode_dependent_value (opcode))) return 0; break; case AARCH64_OPND_SME_ZA_array_off4: - if (!check_za_access (opnd, mismatch_detail, idx, 12, 15)) + if (!check_za_access (opnd, mismatch_detail, idx, 12, 15, + get_opcode_dependent_value (opcode))) return 0; break; @@ -3671,7 +3694,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, case AARCH64_OPND_SME_ZA_HV_idx_src: case AARCH64_OPND_SME_ZA_HV_idx_dest: case AARCH64_OPND_SME_ZA_HV_idx_ldstr: - snprintf (buf, size, "%s%s[%s, %s]%s", + snprintf (buf, size, "%s%s[%s, %s%s%s]%s", opnd->type == AARCH64_OPND_SME_ZA_HV_idx_ldstr ? "{" : "", style_reg (styler, "za%d%c.%s", opnd->indexed_za.regno, @@ -3679,6 +3702,11 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, aarch64_get_qualifier_name (opnd->qualifier)), style_reg (styler, "w%d", opnd->indexed_za.index.regno), style_imm (styler, "%" PRIi64, opnd->indexed_za.index.imm), + opnd->indexed_za.group_size ? ", " : "", + opnd->indexed_za.group_size == 2 + ? style_sub_mnem (styler, "vgx2") + : opnd->indexed_za.group_size == 4 + ? style_sub_mnem (styler, "vgx4") : "", opnd->type == AARCH64_OPND_SME_ZA_HV_idx_ldstr ? "}" : ""); break; @@ -3687,10 +3715,15 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, break; case AARCH64_OPND_SME_ZA_array_off4: - snprintf (buf, size, "%s[%s, %s]", + snprintf (buf, size, "%s[%s, %s%s%s]", style_reg (styler, "za"), style_reg (styler, "w%d", opnd->indexed_za.index.regno), - style_imm (styler, "%" PRIi64, opnd->indexed_za.index.imm)); + style_imm (styler, "%" PRIi64, opnd->indexed_za.index.imm), + opnd->indexed_za.group_size ? ", " : "", + opnd->indexed_za.group_size == 2 + ? style_sub_mnem (styler, "vgx2") + : opnd->indexed_za.group_size == 4 + ? style_sub_mnem (styler, "vgx4") : ""); break; case AARCH64_OPND_SME_SM_ZA: From patchwork Thu Mar 30 10:26:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 77081 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1035395vqo; Thu, 30 Mar 2023 03:56:46 -0700 (PDT) X-Google-Smtp-Source: AKy350Zl3RU7jCIAgepxqModXsMB+fsru0Ke71YZldmi3mX5zGftVSLQZAYXzSy9UlDxa7XlCaoc X-Received: by 2002:aa7:c98b:0:b0:4cd:e84d:1e74 with SMTP id c11-20020aa7c98b000000b004cde84d1e74mr27047977edt.0.1680173806648; Thu, 30 Mar 2023 03:56:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680173806; cv=none; d=google.com; s=arc-20160816; b=NfjHwZsViCRFTAqXeJ53VJOD5RB1/zs6aORf5jCWbEt4Er3A2CTxuYDZ75hZCFJ2Xc 7gKK4kQPf9KAPNicBQG/iquSMmVR2s0oHrtz6ggz1PrxDriaM723qNFS5np5A6mBLdIQ CbjthoFj/w+1HvjG/y8CTtdIVN5chkDGF7eSMate0hb1YwTBuLLSGH5Ha9AiBTEwxbkC KggniEZ5H/1QJYP0K83PRq21jL/QdP8Y47Rc5PcgtApFLZcdEMmgNsVfudI8G+yk2E0u wBwuI9TShRjg7h10cIK4Z/Phb/KyHC1K8zL6bKLWgHWEe1mGGe0CPx095+uRVhRGrWRm OENw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:dmarc-filter:delivered-to :dkim-signature:dkim-filter; bh=F11bk71KncUX7fT5fGbUxH3caIRwcuXmnCeWA33xBN0=; b=mFBJvdSP5kd7rF1FfckvLRJnH0uTa5u2RjAuh3pMPepjCJR002k3sr0CZWjyLkr4c4 ohZo4VdiMwkMMY/r5cr/t/L3CbMATZ1BzG5x7i9wqyRg+0Zzs/govWuNCum1Wma3M1Q2 fPK8Cw2XqEV1DaLCovyILAekoRxgrYkoPfCNBWg3clvQQ1bQQtUqeql9H/3sOmCNbZMM Na0gpphQKpzuwFNM5zDs7JTxQh3MQn/RW22nxa0KzBm+UnE0oocZnb8gd/z15SXf6rSm TvudJhwBzr5eItqqRhHKNoMJTtiVh6J3lKwtVZVYlHjnHY7ChhW1l6zrhOO1RN0LBagw M5Qg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=ms1ZnvTp; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id z9-20020aa7cf89000000b004aaa70a9f13si13348985edx.298.2023.03.30.03.56.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Mar 2023 03:56:46 -0700 (PDT) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=ms1ZnvTp; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id EAD8F382CC7C for ; Thu, 30 Mar 2023 10:39:45 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org EAD8F382CC7C DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1680172786; bh=F11bk71KncUX7fT5fGbUxH3caIRwcuXmnCeWA33xBN0=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=ms1ZnvTp+5zyoQQ6E8l11Vv/EV6+NZ9OGRFvqIe9Mo9BVjpHA/dAsrEkgikdLZC2y nxCkQ+FiyEvuuHs6SNyjSUVc+jUUXpLeHP/VX8s4NXg2ithWEbtjHx3YtOeI0tNf0D 3TBp9I6Uaf6LR9O/uo2ujGsoY3F7QwWEO6FFevhU= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 2A95E3896C1B for ; Thu, 30 Mar 2023 10:26:57 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 2A95E3896C1B Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 497B61650; Thu, 30 Mar 2023 03:27:41 -0700 (PDT) Received: from e121540-lin.manchester.arm.com (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 80B153F663; Thu, 30 Mar 2023 03:26:56 -0700 (PDT) To: binutils@sourceware.org Cc: Richard Sandiford Subject: [PATCH 05/31] aarch64; Add support for vector offset ranges Date: Thu, 30 Mar 2023 11:26:20 +0100 Message-Id: <20230330102646.3327818-6-richard.sandiford@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230330102646.3327818-1-richard.sandiford@arm.com> References: <20230330102646.3327818-1-richard.sandiford@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-32.5 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Richard Sandiford via Binutils From: Richard Sandiford Reply-To: Richard Sandiford Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761789929765169255?= X-GMAIL-MSGID: =?utf-8?q?1761789929765169255?= Some SME2 instructions operate on a range of consecutive ZA vectors. This is indicated by syntax such as: za[, :] Like with the earlier vgx2 and vgx4 support, we get better error messages if the parser allows all ZA indices to have a range. We can then reject invalid cases during constraint checking. --- gas/config/tc-aarch64.c | 23 +++++++++ gas/testsuite/gas/aarch64/sme-2-illegal.l | 13 ++++++ gas/testsuite/gas/aarch64/sme-2-illegal.s | 7 +++ gas/testsuite/gas/aarch64/sme-5-illegal.l | 4 ++ gas/testsuite/gas/aarch64/sme-5-illegal.s | 3 ++ gas/testsuite/gas/aarch64/sme-6-illegal.l | 4 ++ gas/testsuite/gas/aarch64/sme-6-illegal.s | 3 ++ gas/testsuite/gas/aarch64/sme-7-illegal.l | 8 ++++ gas/testsuite/gas/aarch64/sme-7-illegal.s | 6 +++ gas/testsuite/gas/aarch64/sme-9-illegal.l | 9 ++++ gas/testsuite/gas/aarch64/sme-9-illegal.s | 4 ++ include/opcode/aarch64.h | 23 +++++++-- opcodes/aarch64-opc.c | 57 +++++++++++++++++++---- 13 files changed, 151 insertions(+), 13 deletions(-) diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 2d732ea1780..5873fc754a3 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -4550,6 +4550,29 @@ parse_sme_za_index (char **str, struct aarch64_indexed_za *opnd) return false; } + if (skip_past_char (str, ':')) + { + int64_t end; + if (!parse_sme_immediate (str, &end)) + { + set_syntax_error (_("expected a constant immediate offset")); + return false; + } + if (end < opnd->index.imm) + { + set_syntax_error (_("the last offset is less than the" + " first offset")); + return false; + } + if (end == opnd->index.imm) + { + set_syntax_error (_("the last offset is equal to the" + " first offset")); + return false; + } + opnd->index.countm1 = (uint64_t) end - opnd->index.imm; + } + opnd->group_size = 0; if (skip_past_char (str, ',')) { diff --git a/gas/testsuite/gas/aarch64/sme-2-illegal.l b/gas/testsuite/gas/aarch64/sme-2-illegal.l index fd36ed78381..71a104a2ecf 100644 --- a/gas/testsuite/gas/aarch64/sme-2-illegal.l +++ b/gas/testsuite/gas/aarch64/sme-2-illegal.l @@ -28,3 +28,16 @@ [^:]*:[0-9]+: Error: unexpected vector group size at operand 3 -- `mova z0.b,p0/m,za0h.b\[w12,#0,vgx2\]' [^:]*:[0-9]+: Error: unexpected vector group size at operand 3 -- `mova z0.b,p0/m,za0h.b\[w12,#0,vgx4\]' [^:]*:[0-9]+: Error: invalid vector group size at operand 3 -- `mova z0.b,p0/m,za0h.b\[w12,#0,vgx8\]' +[^:]*:[0-9]+: Error: the last offset is less than the first offset at operand 3 -- `mova z0.b,p0/m,za0h.b\[w12,1:0\]' +[^:]*:[0-9]+: Error: the last offset is equal to the first offset at operand 3 -- `mova z0.b,p0/m,za0h.b\[w12,0:0\]' +[^:]*:[0-9]+: Error: expected a single offset rather than a range at operand 3 -- `mova z0.b,p0/m,za0h.b\[w12,0:1\]' +[^:]*:[0-9]+: Error: expected a single offset rather than a range at operand 3 -- `mova z0.b,p0/m,za0h.b\[w12,0:2\]' +[^:]+:[0-9]+: Error: operand mismatch -- `mova z0\.b,p0/m,za0h\.h\[w12,0:1\]' +[^:]+:[0-9]+: Info: did you mean this\? +[^:]+:[0-9]+: Info: mova z0\.b, p0/m, za0h\.b\[w12, 0:1\] +[^:]+:[0-9]+: Info: other valid variant\(s\): +[^:]+:[0-9]+: Info: mova z0\.h, p0/m, za0h\.h\[w12, 0:1\] +[^:]+:[0-9]+: Info: mova z0\.s, p0/m, za0h\.s\[w12, 0:1\] +[^:]+:[0-9]+: Info: mova z0\.d, p0/m, za0h\.d\[w12, 0:1\] +[^:]+:[0-9]+: Info: mova z0\.q, p0/m, za0h\.q\[w12, 0:1\] +[^:]*:[0-9]+: Error: expected a constant immediate offset at operand 3 -- `mova z0.b,p0/m,za0h.b\[w12,0:foo\]' diff --git a/gas/testsuite/gas/aarch64/sme-2-illegal.s b/gas/testsuite/gas/aarch64/sme-2-illegal.s index 8cc130ac9c0..41bbe4e930b 100644 --- a/gas/testsuite/gas/aarch64/sme-2-illegal.s +++ b/gas/testsuite/gas/aarch64/sme-2-illegal.s @@ -34,3 +34,10 @@ mova z0.q, p0/m, za0v.q[w12, #1a2] mova z0.b, p0/m, za0h.b[w12, #0, vgx2] mova z0.b, p0/m, za0h.b[w12, #0, vgx4] mova z0.b, p0/m, za0h.b[w12, #0, vgx8] + +mova z0.b, p0/m, za0h.b[w12, 1:0] +mova z0.b, p0/m, za0h.b[w12, 0:0] +mova z0.b, p0/m, za0h.b[w12, 0:1] +mova z0.b, p0/m, za0h.b[w12, 0:2] +mova z0.b, p0/m, za0h.h[w12, 0:1] +mova z0.b, p0/m, za0h.b[w12, 0:foo] diff --git a/gas/testsuite/gas/aarch64/sme-5-illegal.l b/gas/testsuite/gas/aarch64/sme-5-illegal.l index f6eda9da5e2..c4bfc1f8b5a 100644 --- a/gas/testsuite/gas/aarch64/sme-5-illegal.l +++ b/gas/testsuite/gas/aarch64/sme-5-illegal.l @@ -62,3 +62,7 @@ [^:]*:[0-9]+: Error: operand mismatch -- `ld1b {za0h\.b\[w12,0,vgx4\]},p0/m,\[x0\]' [^:]*:[0-9]+: Info: did you mean this\? [^:]*:[0-9]+: Info: ld1b {za0h\.b\[w12, 0, vgx4\]}, p0/z, \[x0, xzr\] +[^:]*:[0-9]+: Error: expected a single offset rather than a range at operand 1 -- `ld1b {za0h\.b\[w12,0:1\]},p0/z,\[x0\]' +[^:]+:[0-9]+: Error: operand mismatch -- `ld1b {za0h\.b\[w12,0:1\]},p0/m,\[x0\]' +[^:]+:[0-9]+: Info: did you mean this\? +[^:]*:[0-9]+: Info: ld1b {za0h\.b\[w12, 0:1\]}, p0/z, \[x0, xzr\] diff --git a/gas/testsuite/gas/aarch64/sme-5-illegal.s b/gas/testsuite/gas/aarch64/sme-5-illegal.s index 9dbce626a6e..942a5cf9588 100644 --- a/gas/testsuite/gas/aarch64/sme-5-illegal.s +++ b/gas/testsuite/gas/aarch64/sme-5-illegal.s @@ -63,3 +63,6 @@ ld1b {za0h.b[w12, 0, vgx4]}, p0/z, [x0] ld1b {za0h.b[w12, 0, vgx8]}, p0/z, [x0] ld1b {za0h.b[w12, 0, vgx4]}, p0/m, [x0] + +ld1b {za0h.b[w12, 0:1]}, p0/z, [x0] +ld1b {za0h.b[w12, 0:1]}, p0/m, [x0] diff --git a/gas/testsuite/gas/aarch64/sme-6-illegal.l b/gas/testsuite/gas/aarch64/sme-6-illegal.l index bc0d19417fc..b98b76faaed 100644 --- a/gas/testsuite/gas/aarch64/sme-6-illegal.l +++ b/gas/testsuite/gas/aarch64/sme-6-illegal.l @@ -49,3 +49,7 @@ [^:]*:[0-9]+: Error: operand mismatch -- `st1b {za0h\.b\[w12,0,vgx2\]},p0/z,\[x0\]' [^:]*:[0-9]+: Info: did you mean this\? [^:]*:[0-9]+: Info: st1b {za0h\.b\[w12, 0, vgx2\]}, p0, \[x0, xzr\] +[^:]*:[0-9]+: Error: expected a single offset rather than a range at operand 1 -- `st1b {za0h\.b\[w12,0:1,vgx2\]},p0,\[x0\]' +[^:]+:[0-9]+: Error: operand mismatch -- `st1b {za0h\.b\[w12,0:1,vgx2\]},p0/m,\[x0\]' +[^:]+:[0-9]+: Info: did you mean this\? +[^:]*:[0-9]+: Info: st1b {za0h\.b\[w12, 0:1, vgx2\]}, p0, \[x0, xzr\] diff --git a/gas/testsuite/gas/aarch64/sme-6-illegal.s b/gas/testsuite/gas/aarch64/sme-6-illegal.s index 04a508821bc..bebbcb658e8 100644 --- a/gas/testsuite/gas/aarch64/sme-6-illegal.s +++ b/gas/testsuite/gas/aarch64/sme-6-illegal.s @@ -50,3 +50,6 @@ st1b {za0h.b[w12, 0, vgx4]}, p0, [x0] st1b {za0h.b[w12, 0, vgx8]}, p0, [x0] st1b {za0h.b[w12, 0, vgx2]}, p0/z, [x0] + +st1b {za0h.b[w12, 0:1, vgx2]}, p0, [x0] +st1b {za0h.b[w12, 0:1, vgx2]}, p0/m, [x0] diff --git a/gas/testsuite/gas/aarch64/sme-7-illegal.l b/gas/testsuite/gas/aarch64/sme-7-illegal.l index eb0c5e6f51a..5ab025cc27e 100644 --- a/gas/testsuite/gas/aarch64/sme-7-illegal.l +++ b/gas/testsuite/gas/aarch64/sme-7-illegal.l @@ -66,3 +66,11 @@ [^:]*:[0-9]+: Error: operand mismatch -- `str za\.b\[w12,0,vgx4\],\[x0\]' [^:]*:[0-9]+: Info: did you mean this\? [^:]*:[0-9]+: Info: str za\[w12, 0, vgx4\], \[x0\] +[^:]*:[0-9]+: Error: expected a single offset rather than a range at operand 1 -- `ldr za\[w12,0:1\],\[x0\]' +[^:]*:[0-9]+: Error: expected a single offset rather than a range at operand 1 -- `str za\[w12,0:2,vgx4\],\[x0\]' +[^:]*:[0-9]+: Error: operand mismatch -- `ldr za\.b\[w12,0:1\],\[x0\]' +[^:]*:[0-9]+: Info: did you mean this\? +[^:]*:[0-9]+: Info: ldr za\[w12, 0:1\], \[x0\] +[^:]*:[0-9]+: Error: operand mismatch -- `str za\.b\[w12,0:2,vgx4\],\[x0\]' +[^:]*:[0-9]+: Info: did you mean this\? +[^:]*:[0-9]+: Info: str za\[w12, 0:2, vgx4\], \[x0\] diff --git a/gas/testsuite/gas/aarch64/sme-7-illegal.s b/gas/testsuite/gas/aarch64/sme-7-illegal.s index 05d7d23fe29..7e97f910cf8 100644 --- a/gas/testsuite/gas/aarch64/sme-7-illegal.s +++ b/gas/testsuite/gas/aarch64/sme-7-illegal.s @@ -63,3 +63,9 @@ str za[w12, 0, vgx8], [x0] ldr za.b[w12, 0, vgx2], [x0] str za.b[w12, 0, vgx4], [x0] + +ldr za[w12, 0:1], [x0] +str za[w12, 0:2, vgx4], [x0] + +ldr za.b[w12, 0:1], [x0] +str za.b[w12, 0:2, vgx4], [x0] diff --git a/gas/testsuite/gas/aarch64/sme-9-illegal.l b/gas/testsuite/gas/aarch64/sme-9-illegal.l index d7aff825288..7f44435ef08 100644 --- a/gas/testsuite/gas/aarch64/sme-9-illegal.l +++ b/gas/testsuite/gas/aarch64/sme-9-illegal.l @@ -37,6 +37,15 @@ [^:]*:[0-9]+: Info: psel p0, p0, p0\.h\[w12, 0\] [^:]*:[0-9]+: Info: psel p0, p0, p0\.s\[w12, 0\] [^:]*:[0-9]+: Info: psel p0, p0, p0\.d\[w12, 0\] +[^:]*:[0-9]+: Error: expected a single offset rather than a range at operand 3 -- `psel p0,p0,p0\.b\[w12,0:1\]' +[^:]*:[0-9]+: Error: expected a single offset rather than a range at operand 3 -- `psel p0,p0,p0\.b\[w12,0:1,vgx2\]' +[^:]*:[0-9]+: Error: operand mismatch -- `psel p0\.b,p0\.b,p0\.b\[w12,0:1,vgx2\]' +[^:]*:[0-9]+: Info: did you mean this\? +[^:]*:[0-9]+: Info: psel p0, p0, p0\.b\[w12, 0\] +[^:]*:[0-9]+: Info: other valid variant\(s\): +[^:]*:[0-9]+: Info: psel p0, p0, p0\.h\[w12, 0\] +[^:]*:[0-9]+: Info: psel p0, p0, p0\.s\[w12, 0\] +[^:]*:[0-9]+: Info: psel p0, p0, p0\.d\[w12, 0\] [^:]*:[0-9]+: Error: operand mismatch -- `revd z0.q,p0/m,z0.b' [^:]*:[0-9]+: Info: did you mean this\? [^:]*:[0-9]+: Info: revd z0.q, p0/m, z0.q diff --git a/gas/testsuite/gas/aarch64/sme-9-illegal.s b/gas/testsuite/gas/aarch64/sme-9-illegal.s index 8f41298cd3c..3c07e2d6fcb 100644 --- a/gas/testsuite/gas/aarch64/sme-9-illegal.s +++ b/gas/testsuite/gas/aarch64/sme-9-illegal.s @@ -23,6 +23,10 @@ psel p0, p0, p0.b[w12, #0, vgx8] psel p0.b, p0.b, p0.b[w12, #0, vgx2] +psel p0, p0, p0.b[w12, 0:1] +psel p0, p0, p0.b[w12, 0:1, vgx2] +psel p0.b, p0.b, p0.b[w12, 0:1, vgx2] + revd z0.q, p0/m, z0.b sclamp z8.b, z1.b, z31.q diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 534bdaa869f..7ccbb0eda7c 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -1114,14 +1114,29 @@ const aarch64_cond* get_inverted_cond (const aarch64_cond *cond); /* Information about a reference to part of ZA. */ struct aarch64_indexed_za { - int regno; /* */ + /* Which tile is being accessed. Unused (and 0) for an index into ZA. */ + int regno; + struct { - int regno; /* */ - int64_t imm; /* */ + /* The 32-bit index register. */ + int regno; + + /* The first (or only) immediate offset. */ + int64_t imm; + + /* The last immediate offset minus the first immediate offset. + Unlike the range size, this is guaranteed not to overflow + when the end offset > the start offset. */ + uint64_t countm1; } index; + + /* The vector group size, or 0 if none. */ unsigned group_size : 8; - unsigned v : 1; /* horizontal or vertical vector indicator. */ + + /* True if a tile access is vertical, false if it is horizontal. + Unused (and 0) for an index into ZA. */ + unsigned v : 1; }; /* Information about a list of registers. */ diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 0d38ff250c4..4df1dc2cda8 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -1527,14 +1527,18 @@ check_reglist (const aarch64_opnd_info *opnd, - a selection register in the range [MIN_WREG, MIN_WREG + 3] - - an immediate offset in the range [0, MAX_VALUE]. + - RANGE_SIZE consecutive immediate offsets. + + - an initial immediate offset that is a multiple of RANGE_SIZE + in the range [0, MAX_VALUE * RANGE_SIZE] - a vector group size of GROUP_SIZE. */ static bool check_za_access (const aarch64_opnd_info *opnd, aarch64_operand_error *mismatch_detail, int idx, - int min_wreg, int max_value, int group_size) + int min_wreg, int max_value, unsigned int range_size, + int group_size) { if (!value_in_range_p (opnd->indexed_za.index.regno, min_wreg, min_wreg + 3)) { @@ -1547,9 +1551,31 @@ check_za_access (const aarch64_opnd_info *opnd, return false; } - if (!value_in_range_p (opnd->indexed_za.index.imm, 0, max_value)) + int max_index = max_value * range_size; + if (!value_in_range_p (opnd->indexed_za.index.imm, 0, max_index)) + { + set_offset_out_of_range_error (mismatch_detail, idx, 0, max_index); + return false; + } + + if ((opnd->indexed_za.index.imm % range_size) != 0) + { + assert (range_size == 2 || range_size == 4); + set_other_error (mismatch_detail, idx, + range_size == 2 + ? _("starting offset is not a multiple of 2") + : _("starting offset is not a multiple of 4")); + return false; + } + + if (opnd->indexed_za.index.countm1 != range_size - 1) { - set_offset_out_of_range_error (mismatch_detail, idx, 0, max_value); + if (range_size == 1) + set_other_error (mismatch_detail, idx, + _("expected a single offset rather than" + " a range")); + else + abort (); return false; } @@ -1678,7 +1704,8 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, case AARCH64_OPND_SME_PnT_Wm_imm: size = aarch64_get_qualifier_esize (opnd->qualifier); max_value = 16 / size - 1; - if (!check_za_access (opnd, mismatch_detail, idx, 12, max_value, 0)) + if (!check_za_access (opnd, mismatch_detail, idx, + 12, max_value, 1, 0)) return 0; break; @@ -1701,13 +1728,13 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, case AARCH64_OPND_SME_ZA_HV_idx_ldstr: size = aarch64_get_qualifier_esize (opnd->qualifier); max_value = 16 / size - 1; - if (!check_za_access (opnd, mismatch_detail, idx, 12, max_value, + if (!check_za_access (opnd, mismatch_detail, idx, 12, max_value, 1, get_opcode_dependent_value (opcode))) return 0; break; case AARCH64_OPND_SME_ZA_array_off4: - if (!check_za_access (opnd, mismatch_detail, idx, 12, 15, + if (!check_za_access (opnd, mismatch_detail, idx, 12, 15, 1, get_opcode_dependent_value (opcode))) return 0; break; @@ -3694,7 +3721,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, case AARCH64_OPND_SME_ZA_HV_idx_src: case AARCH64_OPND_SME_ZA_HV_idx_dest: case AARCH64_OPND_SME_ZA_HV_idx_ldstr: - snprintf (buf, size, "%s%s[%s, %s%s%s]%s", + snprintf (buf, size, "%s%s[%s, %s%s%s%s%s]%s", opnd->type == AARCH64_OPND_SME_ZA_HV_idx_ldstr ? "{" : "", style_reg (styler, "za%d%c.%s", opnd->indexed_za.regno, @@ -3702,6 +3729,12 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, aarch64_get_qualifier_name (opnd->qualifier)), style_reg (styler, "w%d", opnd->indexed_za.index.regno), style_imm (styler, "%" PRIi64, opnd->indexed_za.index.imm), + opnd->indexed_za.index.countm1 ? ":" : "", + (opnd->indexed_za.index.countm1 + ? style_imm (styler, "%d", + opnd->indexed_za.index.imm + + opnd->indexed_za.index.countm1) + : ""), opnd->indexed_za.group_size ? ", " : "", opnd->indexed_za.group_size == 2 ? style_sub_mnem (styler, "vgx2") @@ -3715,10 +3748,16 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, break; case AARCH64_OPND_SME_ZA_array_off4: - snprintf (buf, size, "%s[%s, %s%s%s]", + snprintf (buf, size, "%s[%s, %s%s%s%s%s]", style_reg (styler, "za"), style_reg (styler, "w%d", opnd->indexed_za.index.regno), style_imm (styler, "%" PRIi64, opnd->indexed_za.index.imm), + opnd->indexed_za.index.countm1 ? ":" : "", + (opnd->indexed_za.index.countm1 + ? style_imm (styler, "%d", + opnd->indexed_za.index.imm + + opnd->indexed_za.index.countm1) + : ""), opnd->indexed_za.group_size ? ", " : "", opnd->indexed_za.group_size == 2 ? style_sub_mnem (styler, "vgx2") From patchwork Thu Mar 30 10:26:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 77085 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1037342vqo; Thu, 30 Mar 2023 04:00:59 -0700 (PDT) X-Google-Smtp-Source: AKy350aHgR2V8gXROPcDRrNN2r1VRIHvaH3wRCGIB4EqIeffD+Wb6Jo92Eepana30dCvJsP8G3LH X-Received: by 2002:a17:906:5592:b0:878:72f7:bd87 with SMTP id y18-20020a170906559200b0087872f7bd87mr22086172ejp.6.1680174059538; Thu, 30 Mar 2023 04:00:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680174059; cv=none; d=google.com; s=arc-20160816; b=EehVEHOiET2UeX9sJu+53EScQHRFqmGVtKvi/Q8WE1Pig9enH5chevjtsNxUoLF4I2 KR/jnH17uR3JxUrrU1vI8LT7GlKPHPRgzvmhyB270V0eD3GRpt1uMYp0gbJF+dI0o0T3 AHxXtTuf0aF8Mmec7/lal+k4EcP8r6D+naxwgY56k0XDN8Olymm7r+GhPyo0WxvwVqBD whYWiUPxKq0F0QHmyFKaa5HCmVSOXDzS/MqFm1muwdSiYO33hlJuVScNmtdra87IOWGZ kmT2DTCp/3cMAH2uDhbYx6FZu4ioLDjCvzW8G+9T1CoJpCWU/KY/B8jW0QOL2LQmgrQZ n5Tg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:dmarc-filter:delivered-to :dkim-signature:dkim-filter; bh=PbK2EPo5ulHgTXPISlx06gtgrhogK8hxkHIQGM9B1H0=; b=dn8UFXqI/CtELpeJ7300TNBvSVg7hKv1MmarslPLCx81iX2ZOGWZo9LSmYYMIGQT3+ GZNt0HSM6t4G9GlKfJg88PGQZVY4TKaDhOBCLNLOb3DHfor+4TqXK1izpFO8eP7UXS+s iNWOUC9RkaGRUZUHaeqsoYV9i2CBXAB6EIO7ppwAFrDzmtXkNMBbEZB3YToVKMCgesno zsgwdgPOQjSCv3LkvzGH/J7baKtP+vhP9a+aq9rGyxreP04rVpAS7zuxqfNE7M+r0oMP 0s926OxPHThHJkLAVJtuTheNCcGRrvAa3K+4wH/2gFCHTZb7KOXUXiGKoz4tY3FuTmSF h3Zg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b="lKFL/444"; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from sourceware.org (server2.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id ne28-20020a1709077b9c00b009372a2a6e7fsi32160517ejc.563.2023.03.30.04.00.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Mar 2023 04:00:59 -0700 (PDT) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b="lKFL/444"; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id E78D13982437 for ; Thu, 30 Mar 2023 10:41:58 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org E78D13982437 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1680172919; bh=PbK2EPo5ulHgTXPISlx06gtgrhogK8hxkHIQGM9B1H0=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=lKFL/444x9XNZGJkIQcpQk28+bBarEBKXtXTi7Rn6vDb0ab+xjXTm+vAzjBTz5fSl YRirr9ulBcBrv5YY+n1S/G555X6ZxArgwGVtxFyji1VuqysbodTILXhCX2M50je3bX SgoroaOJCfPrCQm7FbCbvQQdq4OGSkmRCC23PMkU= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 31DD13882035 for ; Thu, 30 Mar 2023 10:26:59 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 31DD13882035 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 536852F4; Thu, 30 Mar 2023 03:27:43 -0700 (PDT) Received: from e121540-lin.manchester.arm.com (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 89C953F663; Thu, 30 Mar 2023 03:26:58 -0700 (PDT) To: binutils@sourceware.org Cc: Richard Sandiford Subject: [PATCH 07/31] aarch64: Add the SME2 MOVA instructions Date: Thu, 30 Mar 2023 11:26:22 +0100 Message-Id: <20230330102646.3327818-8-richard.sandiford@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230330102646.3327818-1-richard.sandiford@arm.com> References: <20230330102646.3327818-1-richard.sandiford@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-32.4 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Richard Sandiford via Binutils From: Richard Sandiford Reply-To: Richard Sandiford Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761790194957722373?= X-GMAIL-MSGID: =?utf-8?q?1761790194957722373?= SME2 defines new MOVA instructions for moving multiple registers to and from ZA. As with SME, the instructions are also available through MOV aliases. One notable feature of these instructions (and many other SME2 instructions) is that some register lists must start at a multiple of the list's size. The patch uses the general error "start register out of range" when this constraint isn't met, rather than an error specifically about multiples. This ensures that the error is consistent between these simple consecutive lists and later strided lists, for which the requirements aren't a simple multiple. --- gas/config/tc-aarch64.c | 8 + gas/testsuite/gas/aarch64/legacy_reg_names.l | 2 +- gas/testsuite/gas/aarch64/sme-3-illegal.l | 2 +- gas/testsuite/gas/aarch64/sme2-1-invalid.d | 3 + gas/testsuite/gas/aarch64/sme2-1-invalid.l | 327 +++++++++ gas/testsuite/gas/aarch64/sme2-1-invalid.s | 323 +++++++++ gas/testsuite/gas/aarch64/sme2-1-noarch.d | 3 + gas/testsuite/gas/aarch64/sme2-1-noarch.l | 289 ++++++++ gas/testsuite/gas/aarch64/sme2-1.d | 305 ++++++++ gas/testsuite/gas/aarch64/sme2-1.s | 338 +++++++++ include/opcode/aarch64.h | 10 + opcodes/aarch64-asm-2.c | 34 +- opcodes/aarch64-asm.c | 50 +- opcodes/aarch64-asm.h | 2 + opcodes/aarch64-dis-2.c | 702 +++++++++++-------- opcodes/aarch64-dis.c | 60 +- opcodes/aarch64-dis.h | 2 + opcodes/aarch64-opc-2.c | 8 + opcodes/aarch64-opc.c | 79 ++- opcodes/aarch64-opc.h | 6 + opcodes/aarch64-tbl.h | 43 ++ 21 files changed, 2282 insertions(+), 314 deletions(-) create mode 100644 gas/testsuite/gas/aarch64/sme2-1-invalid.d create mode 100644 gas/testsuite/gas/aarch64/sme2-1-invalid.l create mode 100644 gas/testsuite/gas/aarch64/sme2-1-invalid.s create mode 100644 gas/testsuite/gas/aarch64/sme2-1-noarch.d create mode 100644 gas/testsuite/gas/aarch64/sme2-1-noarch.l create mode 100644 gas/testsuite/gas/aarch64/sme2-1.d create mode 100644 gas/testsuite/gas/aarch64/sme2-1.s diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 8d5cc5194de..bf9771d1010 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -6712,6 +6712,10 @@ parse_operands (char *str, const aarch64_opcode *opcode) case AARCH64_OPND_SVE_ZnxN: case AARCH64_OPND_SVE_ZtxN: + case AARCH64_OPND_SME_Zdnx2: + case AARCH64_OPND_SME_Zdnx4: + case AARCH64_OPND_SME_Znx2: + case AARCH64_OPND_SME_Znx4: reg_type = REG_TYPE_Z; goto vector_reg_list; @@ -7708,7 +7712,9 @@ parse_operands (char *str, const aarch64_opcode *opcode) break; case AARCH64_OPND_SME_ZA_HV_idx_src: + case AARCH64_OPND_SME_ZA_HV_idx_srcxN: case AARCH64_OPND_SME_ZA_HV_idx_dest: + case AARCH64_OPND_SME_ZA_HV_idx_destxN: case AARCH64_OPND_SME_ZA_HV_idx_ldstr: if (operands[i] == AARCH64_OPND_SME_ZA_HV_idx_ldstr ? !parse_sme_za_hv_tiles_operand_with_braces (&str, @@ -7727,6 +7733,8 @@ parse_operands (char *str, const aarch64_opcode *opcode) info->imm.value = val; break; + case AARCH64_OPND_SME_ZA_array_off3_0: + case AARCH64_OPND_SME_ZA_array_off3_5: case AARCH64_OPND_SME_ZA_array_off4: if (!parse_dual_indexed_reg (&str, REG_TYPE_ZA, &info->indexed_za, &qualifier, 0)) diff --git a/gas/testsuite/gas/aarch64/legacy_reg_names.l b/gas/testsuite/gas/aarch64/legacy_reg_names.l index f3dde54e418..ca5f86cdfe9 100644 --- a/gas/testsuite/gas/aarch64/legacy_reg_names.l +++ b/gas/testsuite/gas/aarch64/legacy_reg_names.l @@ -1,4 +1,4 @@ [^:]*: Assembler messages: [^:]*:5: Error: indexed vector register expected at operand 1 -- `dup v0.b,v1.b\[7\]' -[^:]*:6: Error: expected a register at operand 1 -- `mov r0.w,r1.w' +[^:]*:6: Error: expected a register or register list at operand 1 -- `mov r0.w,r1.w' [^:]*:7: Error: expected an Advanced SIMD vector register at operand 2 -- `dup s0,s1\[3\]' diff --git a/gas/testsuite/gas/aarch64/sme-3-illegal.l b/gas/testsuite/gas/aarch64/sme-3-illegal.l index f5fb169b78a..dd1bf7922f7 100644 --- a/gas/testsuite/gas/aarch64/sme-3-illegal.l +++ b/gas/testsuite/gas/aarch64/sme-3-illegal.l @@ -3,7 +3,7 @@ [^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za2v\.h\[w12,#0\],p0/m,z0.h' [^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za4v\.s\[w12,#0\],p0/m,z0.s' [^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za8v\.d\[w12,#0\],p0/m,z0.d' -[^:]*:[0-9]+: Error: expected an SVE vector register or ZA tile slice at operand 1 -- `mova za16v\.q\[w12\],p0/m,z0.q' +[^:]*:[0-9]+: Error: expected a register or register list at operand 1 -- `mova za16v\.q\[w12\],p0/m,z0.q' [^:]*:[0-9]+: Error: immediate offset out of range 0 to 15 at operand 1 -- `mova za0v\.b\[w15,#16\],p7/m,z31.b' [^:]*:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `mova za1v\.h\[w15,#8\],p7/m,z31.h' [^:]*:[0-9]+: Error: immediate offset out of range 0 to 3 at operand 1 -- `mova za3v\.s\[w15,#4\],p7/m,z31.s' diff --git a/gas/testsuite/gas/aarch64/sme2-1-invalid.d b/gas/testsuite/gas/aarch64/sme2-1-invalid.d new file mode 100644 index 00000000000..5ca0674ab0b --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-1-invalid.d @@ -0,0 +1,3 @@ +#as: -march=armv8-a +#source: sme2-1-invalid.s +#error_output: sme2-1-invalid.l diff --git a/gas/testsuite/gas/aarch64/sme2-1-invalid.l b/gas/testsuite/gas/aarch64/sme2-1-invalid.l new file mode 100644 index 00000000000..d8d2d77c0a4 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-1-invalid.l @@ -0,0 +1,327 @@ +[^ :]+: Assembler messages: +[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `mov 0,za\.b\[w8,0\]' +[^ :]+:[0-9]+: Error: expected a register at operand 2 -- `mov {z0\.b-z1\.b},0' +[^ :]+:[0-9]+: Error: operand mismatch -- `mov {z0\.d-z1\.d},za\.q\[w8,0\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: mov {z0\.d-z1\.d}, za\.d\[w8, 0\] +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: mov {z0\.b-z1\.b}, za\.b\[w8, 0\] +[^ :]+:[0-9]+: Info: mov {z0\.h-z1\.h}, za\.h\[w8, 0\] +[^ :]+:[0-9]+: Info: mov {z0\.s-z1\.s}, za\.s\[w8, 0\] +[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `mov {z1\.d-z2\.d},za\.d\[w8,0\]' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 2 -- `mov {z0\.d-z1\.d},za\.d\[w7,0\]' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 2 -- `mov {z0\.d-z1\.d},za\.d\[w12,0\]' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 2 -- `mov {z0\.d-z1\.d},za\.d\[w8,-1\]' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 2 -- `mov {z0\.d-z1\.d},za\.d\[w8,8\]' +[^ :]+:[0-9]+: Error: operand mismatch -- `mov {z0\.d-z3\.d},za\.q\[w8,0\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: mov {z0\.d-z3\.d}, za\.d\[w8, 0\] +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: mov {z0\.b-z3\.b}, za\.b\[w8, 0\] +[^ :]+:[0-9]+: Info: mov {z0\.h-z3\.h}, za\.h\[w8, 0\] +[^ :]+:[0-9]+: Info: mov {z0\.s-z3\.s}, za\.s\[w8, 0\] +[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `mov {z1\.d-z4\.d},za\.d\[w8,0\]' +[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `mov {z2\.d-z5\.d},za\.d\[w8,0\]' +[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `mov {z3\.d-z6\.d},za\.d\[w8,0\]' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 2 -- `mov {z0\.d-z3\.d},za\.d\[w7,0\]' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 2 -- `mov {z0\.d-z3\.d},za\.d\[w12,0\]' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 2 -- `mov {z0\.d-z3\.d},za\.d\[w8,-1\]' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 2 -- `mov {z0\.d-z3\.d},za\.d\[w8,8\]' +[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `mov {z1\.b-z2\.b},za0h\.b\[w8,0:1\]' +[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 2 -- `mov {z0\.b-z1\.b},za1h\.b\[w12,0:1\]' +[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 2 -- `mov {z0\.b-z1\.b},za1v\.b\[w12,0:1\]' +[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 2 -- `mov {z0\.b-z1\.b},za0h\.b\[w11,0:1\]' +[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 2 -- `mov {z0\.b-z1\.b},za0h\.b\[w16,0:1\]' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 14 at operand 2 -- `mov {z0\.b-z1\.b},za0h\.b\[w12,-2:-1\]' +[^ :]+:[0-9]+: Error: starting offset is not a multiple of 2 at operand 2 -- `mov {z0\.b-z1\.b},za0h\.b\[w12,1:2\]' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 14 at operand 2 -- `mov {z0\.b-z1\.b},za0h\.b\[w12,15:16\]' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 14 at operand 2 -- `mov {z0\.b-z1\.b},za0h\.b\[w12,16:17\]' +[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 2 -- `mov {z0\.b-z1\.b},za0h\.b\[w12,0\]' +[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 2 -- `mov {z0\.b-z1\.b},za0h\.b\[w12,0:2\]' +[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 2 -- `mov {z0\.b-z1\.b},za0h\.b\[w12,0:3\]' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 1 -- `mov {z0\.b-z1\.b},za0h\.b\[w12,0:1,vgx2\]' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 1 -- `mov {z0\.b-z1\.b},za0h\.b\[w12,0:1,vgx4\]' +[^ :]+:[0-9]+: Error: missing horizontal or vertical suffix at operand 2 -- `mov {z0\.b-z1\.b},za0\.b\[w12,0:1\]' +[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `mov {z1\.h-z2\.h},za0h\.h\[w12,0:1\]' +[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 2 -- `mov {z0\.h-z1\.h},za2h\.h\[w12,0:1\]' +[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 2 -- `mov {z0\.h-z1\.h},za2v\.h\[w12,0:1\]' +[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 2 -- `mov {z0\.h-z1\.h},za0h\.h\[w11,0:1\]' +[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 2 -- `mov {z0\.h-z1\.h},za0h\.h\[w16,0:1\]' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 6 at operand 2 -- `mov {z0\.h-z1\.h},za0h\.h\[w12,-2:-1\]' +[^ :]+:[0-9]+: Error: starting offset is not a multiple of 2 at operand 2 -- `mov {z0\.h-z1\.h},za0h\.h\[w12,1:2\]' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 6 at operand 2 -- `mov {z0\.h-z1\.h},za0h\.h\[w12,7:8\]' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 6 at operand 2 -- `mov {z0\.h-z1\.h},za0h\.h\[w12,8:9\]' +[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 2 -- `mov {z0\.h-z1\.h},za0h\.h\[w12,0\]' +[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 2 -- `mov {z0\.h-z1\.h},za0h\.h\[w12,0:2\]' +[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 2 -- `mov {z0\.h-z1\.h},za0h\.h\[w12,0:3\]' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 1 -- `mov {z0\.h-z1\.h},za0h\.h\[w12,0:1,vgx2\]' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 1 -- `mov {z0\.h-z1\.h},za0h\.h\[w12,0:1,vgx4\]' +[^ :]+:[0-9]+: Error: missing horizontal or vertical suffix at operand 2 -- `mov {z0\.h-z1\.h},za0\.h\[w12,0:1\]' +[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `mov {z1\.s-z2\.s},za0h\.s\[w12,0:1\]' +[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 2 -- `mov {z0\.s-z1\.s},za4h\.s\[w12,0:1\]' +[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 2 -- `mov {z0\.s-z1\.s},za4v\.s\[w12,0:1\]' +[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 2 -- `mov {z0\.s-z1\.s},za0h\.s\[w11,0:1\]' +[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 2 -- `mov {z0\.s-z1\.s},za0h\.s\[w16,0:1\]' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 2 at operand 2 -- `mov {z0\.s-z1\.s},za0h\.s\[w12,-2:-1\]' +[^ :]+:[0-9]+: Error: starting offset is not a multiple of 2 at operand 2 -- `mov {z0\.s-z1\.s},za0h\.s\[w12,1:2\]' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 2 at operand 2 -- `mov {z0\.s-z1\.s},za0h\.s\[w12,3:4\]' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 2 at operand 2 -- `mov {z0\.s-z1\.s},za0h\.s\[w12,4:5\]' +[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 2 -- `mov {z0\.s-z1\.s},za0h\.s\[w12,0\]' +[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 2 -- `mov {z0\.s-z1\.s},za0h\.s\[w12,0:2\]' +[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 2 -- `mov {z0\.s-z1\.s},za0h\.s\[w12,0:3\]' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 1 -- `mov {z0\.s-z1\.s},za0h\.s\[w12,0:1,vgx2\]' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 1 -- `mov {z0\.s-z1\.s},za0h\.s\[w12,0:1,vgx4\]' +[^ :]+:[0-9]+: Error: missing horizontal or vertical suffix at operand 2 -- `mov {z0\.s-z1\.s},za0\.s\[w12,0:1\]' +[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `mov {z1\.d-z2\.d},za0h\.d\[w12,0:1\]' +[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 2 -- `mov {z0\.d-z1\.d},za8h\.d\[w12,0:1\]' +[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 2 -- `mov {z0\.d-z1\.d},za8v\.d\[w12,0:1\]' +[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 2 -- `mov {z0\.d-z1\.d},za0h\.d\[w11,0:1\]' +[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 2 -- `mov {z0\.d-z1\.d},za0h\.d\[w16,0:1\]' +[^ :]+:[0-9]+: Error: immediate offset must be 0 at operand 2 -- `mov {z0\.d-z1\.d},za0h\.d\[w12,-2:-1\]' +[^ :]+:[0-9]+: Error: immediate offset must be 0 at operand 2 -- `mov {z0\.d-z1\.d},za0h\.d\[w12,1:2\]' +[^ :]+:[0-9]+: Error: immediate offset must be 0 at operand 2 -- `mov {z0\.d-z1\.d},za0h\.d\[w12,2:3\]' +[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 2 -- `mov {z0\.d-z1\.d},za0h\.d\[w12,0\]' +[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 2 -- `mov {z0\.d-z1\.d},za0h\.d\[w12,0:2\]' +[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 2 -- `mov {z0\.d-z1\.d},za0h\.d\[w12,0:3\]' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 1 -- `mov {z0\.d-z1\.d},za0h\.d\[w12,0:1,vgx2\]' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 1 -- `mov {z0\.d-z1\.d},za0h\.d\[w12,0:1,vgx4\]' +[^ :]+:[0-9]+: Error: missing horizontal or vertical suffix at operand 2 -- `mov {z0\.d-z1\.d},za0\.d\[w12,0:1\]' +[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `mov {z1\.b-z4\.b},za0h\.b\[w12,0:3\]' +[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `mov {z2\.b-z5\.b},za0h\.b\[w12,0:3\]' +[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `mov {z3\.b-z6\.b},za0h\.b\[w12,0:3\]' +[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 2 -- `mov {z0\.b-z3\.b},za1h\.b\[w12,0:3\]' +[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 2 -- `mov {z0\.b-z3\.b},za1v\.b\[w12,0:3\]' +[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 2 -- `mov {z0\.b-z3\.b},za0h\.b\[w11,0:3\]' +[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 2 -- `mov {z0\.b-z3\.b},za0h\.b\[w16,0:3\]' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 12 at operand 2 -- `mov {z0\.b-z3\.b},za0h\.b\[w12,-4:-1\]' +[^ :]+:[0-9]+: Error: starting offset is not a multiple of 4 at operand 2 -- `mov {z0\.b-z3\.b},za0h\.b\[w12,1:4\]' +[^ :]+:[0-9]+: Error: starting offset is not a multiple of 4 at operand 2 -- `mov {z0\.b-z3\.b},za0h\.b\[w12,2:5\]' +[^ :]+:[0-9]+: Error: starting offset is not a multiple of 4 at operand 2 -- `mov {z0\.b-z3\.b},za0h\.b\[w12,3:6\]' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 12 at operand 2 -- `mov {z0\.b-z3\.b},za0h\.b\[w12,13:16\]' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 12 at operand 2 -- `mov {z0\.b-z3\.b},za0h\.b\[w12,14:17\]' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 12 at operand 2 -- `mov {z0\.b-z3\.b},za0h\.b\[w12,15:18\]' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 12 at operand 2 -- `mov {z0\.b-z3\.b},za0h\.b\[w12,16:19\]' +[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 2 -- `mov {z0\.b-z3\.b},za0h\.b\[w12,0\]' +[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 2 -- `mov {z0\.b-z3\.b},za0h\.b\[w12,0:1\]' +[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 2 -- `mov {z0\.b-z3\.b},za0h\.b\[w12,0:2\]' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 1 -- `mov {z0\.b-z3\.b},za0h\.b\[w12,0:3,vgx2\]' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 1 -- `mov {z0\.b-z3\.b},za0h\.b\[w12,0:3,vgx4\]' +[^ :]+:[0-9]+: Error: missing horizontal or vertical suffix at operand 2 -- `mov {z0\.b-z3\.b},za0\.b\[w12,0:3\]' +[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `mov {z1\.h-z2\.h},za0h\.h\[w12,0:3\]' +[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `mov {z2\.h-z5\.h},za0h\.h\[w12,0:3\]' +[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `mov {z3\.h-z6\.h},za0h\.h\[w12,0:3\]' +[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 2 -- `mov {z0\.h-z3\.h},za2h\.h\[w12,0:3\]' +[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 2 -- `mov {z0\.h-z3\.h},za2v\.h\[w12,0:3\]' +[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 2 -- `mov {z0\.h-z3\.h},za0h\.h\[w11,0:3\]' +[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 2 -- `mov {z0\.h-z3\.h},za0h\.h\[w16,0:3\]' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 4 at operand 2 -- `mov {z0\.h-z3\.h},za0h\.h\[w12,-4:-1\]' +[^ :]+:[0-9]+: Error: starting offset is not a multiple of 4 at operand 2 -- `mov {z0\.h-z3\.h},za0h\.h\[w12,1:2\]' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 4 at operand 2 -- `mov {z0\.h-z3\.h},za0h\.h\[w12,5:8\]' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 4 at operand 2 -- `mov {z0\.h-z3\.h},za0h\.h\[w12,6:9\]' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 4 at operand 2 -- `mov {z0\.h-z3\.h},za0h\.h\[w12,7:10\]' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 4 at operand 2 -- `mov {z0\.h-z3\.h},za0h\.h\[w12,8:11\]' +[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 2 -- `mov {z0\.h-z3\.h},za0h\.h\[w12,0\]' +[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 2 -- `mov {z0\.h-z3\.h},za0h\.h\[w12,0:1\]' +[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 2 -- `mov {z0\.h-z3\.h},za0h\.h\[w12,0:2\]' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 1 -- `mov {z0\.h-z3\.h},za0h\.h\[w12,0:3,vgx2\]' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 1 -- `mov {z0\.h-z3\.h},za0h\.h\[w12,0:3,vgx4\]' +[^ :]+:[0-9]+: Error: missing horizontal or vertical suffix at operand 2 -- `mov {z0\.h-z3\.h},za0\.h\[w12,0:3\]' +[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `mov {z1\.s-z2\.s},za0h\.s\[w12,0:3\]' +[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `mov {z2\.s-z5\.s},za0h\.s\[w12,0:3\]' +[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `mov {z3\.s-z6\.s},za0h\.s\[w12,0:3\]' +[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 2 -- `mov {z0\.s-z3\.s},za4h\.s\[w12,0:3\]' +[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 2 -- `mov {z0\.s-z3\.s},za4v\.s\[w12,0:3\]' +[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 2 -- `mov {z0\.s-z3\.s},za0h\.s\[w11,0:3\]' +[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 2 -- `mov {z0\.s-z3\.s},za0h\.s\[w16,0:3\]' +[^ :]+:[0-9]+: Error: immediate offset must be 0 at operand 2 -- `mov {z0\.s-z3\.s},za0h\.s\[w12,-4:-1\]' +[^ :]+:[0-9]+: Error: immediate offset must be 0 at operand 2 -- `mov {z0\.s-z3\.s},za0h\.s\[w12,1:4\]' +[^ :]+:[0-9]+: Error: immediate offset must be 0 at operand 2 -- `mov {z0\.s-z3\.s},za0h\.s\[w12,2:5\]' +[^ :]+:[0-9]+: Error: immediate offset must be 0 at operand 2 -- `mov {z0\.s-z3\.s},za0h\.s\[w12,3:6\]' +[^ :]+:[0-9]+: Error: immediate offset must be 0 at operand 2 -- `mov {z0\.s-z3\.s},za0h\.s\[w12,4:7\]' +[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 2 -- `mov {z0\.s-z3\.s},za0h\.s\[w12,0\]' +[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 2 -- `mov {z0\.s-z3\.s},za0h\.s\[w12,0:1\]' +[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 2 -- `mov {z0\.s-z3\.s},za0h\.s\[w12,0:2\]' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 1 -- `mov {z0\.s-z3\.s},za0h\.s\[w12,0:3,vgx2\]' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 1 -- `mov {z0\.s-z3\.s},za0h\.s\[w12,0:3,vgx4\]' +[^ :]+:[0-9]+: Error: missing horizontal or vertical suffix at operand 2 -- `mov {z0\.s-z3\.s},za0\.s\[w12,0:3\]' +[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `mov {z1\.d-z2\.d},za0h\.d\[w12,0:3\]' +[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `mov {z2\.d-z5\.d},za0h\.d\[w12,0:3\]' +[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `mov {z3\.d-z6\.d},za0h\.d\[w12,0:3\]' +[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 2 -- `mov {z0\.d-z3\.d},za8h\.d\[w12,0:3\]' +[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 2 -- `mov {z0\.d-z3\.d},za8v\.d\[w12,0:3\]' +[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 2 -- `mov {z0\.d-z3\.d},za0h\.d\[w11,0:3\]' +[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 2 -- `mov {z0\.d-z3\.d},za0h\.d\[w16,0:3\]' +[^ :]+:[0-9]+: Error: immediate offset must be 0 at operand 2 -- `mov {z0\.d-z3\.d},za0h\.d\[w12,-4:-1\]' +[^ :]+:[0-9]+: Error: immediate offset must be 0 at operand 2 -- `mov {z0\.d-z3\.d},za0h\.d\[w12,1:4\]' +[^ :]+:[0-9]+: Error: immediate offset must be 0 at operand 2 -- `mov {z0\.d-z3\.d},za0h\.d\[w12,2:5\]' +[^ :]+:[0-9]+: Error: immediate offset must be 0 at operand 2 -- `mov {z0\.d-z3\.d},za0h\.d\[w12,3:6\]' +[^ :]+:[0-9]+: Error: immediate offset must be 0 at operand 2 -- `mov {z0\.d-z3\.d},za0h\.d\[w12,4:7\]' +[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 2 -- `mov {z0\.d-z3\.d},za0h\.d\[w12,0\]' +[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 2 -- `mov {z0\.d-z3\.d},za0h\.d\[w12,0:1\]' +[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 2 -- `mov {z0\.d-z3\.d},za0h\.d\[w12,0:2\]' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 1 -- `mov {z0\.d-z3\.d},za0h\.d\[w12,0:3,vgx2\]' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 1 -- `mov {z0\.d-z3\.d},za0h\.d\[w12,0:3,vgx4\]' +[^ :]+:[0-9]+: Error: missing horizontal or vertical suffix at operand 2 -- `mov {z0\.d-z3\.d},za0\.d\[w12,0:3\]' +[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `mova 0,za\.b\[w8,0\]' +[^ :]+:[0-9]+: Error: expected a register at operand 2 -- `mova {z0\.b-z1\.b},0' +[^ :]+:[0-9]+: Error: operand mismatch -- `mova za\.q\[w8,0\],{z0\.q-z1\.q}' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: mova za\.b\[w8, 0\], {z0\.b-z1\.b} +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: mova za\.h\[w8, 0\], {z0\.h-z1\.h} +[^ :]+:[0-9]+: Info: mova za\.s\[w8, 0\], {z0\.s-z1\.s} +[^ :]+:[0-9]+: Info: mova za\.d\[w8, 0\], {z0\.d-z1\.d} +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `mova za\.d\[w7,0\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `mova za\.d\[w12,0\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `mova za\.d\[w8,-1\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `mova za\.d\[w8,8\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `mova za\.d\[w8,0\],{z1\.d-z2\.d}' +[^ :]+:[0-9]+: Error: operand mismatch -- `mova za\.q\[w8,0\],{z0\.q-z3\.q}' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: mova za\.b\[w8, 0\], {z0\.b-z3\.b} +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: mova za\.h\[w8, 0\], {z0\.h-z3\.h} +[^ :]+:[0-9]+: Info: mova za\.s\[w8, 0\], {z0\.s-z3\.s} +[^ :]+:[0-9]+: Info: mova za\.d\[w8, 0\], {z0\.d-z3\.d} +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `mova za\.d\[w7,0\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `mova za\.d\[w12,0\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `mova za\.d\[w8,-1\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `mova za\.d\[w8,8\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `mova za\.d\[w8,0\],{z1\.d-z4\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `mova za\.d\[w8,0\],{z2\.d-z5\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `mova za\.d\[w8,0\],{z3\.d-z6\.d}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `mova za0h\.b\[w8,0:1\],{z1\.b-z2\.b}' +[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za1h\.b\[w12,0:1\],{z0\.b-z1\.b}' +[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za1v\.b\[w12,0:1\],{z0\.b-z1\.b}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `mova za0h\.b\[w11,0:1\],{z0\.b-z1\.b}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `mova za0h\.b\[w16,0:1\],{z0\.b-z1\.b}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 14 at operand 1 -- `mova za0h\.b\[w12,-2:-1\],{z0\.b-z1\.b}' +[^ :]+:[0-9]+: Error: starting offset is not a multiple of 2 at operand 1 -- `mova za0h\.b\[w12,1:2\],{z0\.b-z1\.b}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 14 at operand 1 -- `mova za0h\.b\[w12,15:16\],{z0\.b-z1\.b}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 14 at operand 1 -- `mova za0h\.b\[w12,16:17\],{z0\.b-z1\.b}' +[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.b\[w12,0\],{z0\.b-z1\.b}' +[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.b\[w12,0:2\],{z0\.b-z1\.b}' +[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.b\[w12,0:3\],{z0\.b-z1\.b}' +[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 1 -- `mova za0h\.b\[w12,0:1,vgx2\],{z0\.b-z1\.b}' +[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 1 -- `mova za0h\.b\[w12,0:1,vgx4\],{z0\.b-z1\.b}' +[^ :]+:[0-9]+: Error: missing horizontal or vertical suffix at operand 1 -- `mova za0\.b\[w12,0:1\],{z0\.b-z1\.b}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `mova za0h\.h\[w12,0:1\],{z1\.h-z2\.h}' +[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za2h\.h\[w12,0:1\],{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za2v\.h\[w12,0:1\],{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `mova za0h\.h\[w11,0:1\],{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `mova za0h\.h\[w16,0:1\],{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 6 at operand 1 -- `mova za0h\.h\[w12,-2:-1\],{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: starting offset is not a multiple of 2 at operand 1 -- `mova za0h\.h\[w12,1:2\],{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 6 at operand 1 -- `mova za0h\.h\[w12,7:8\],{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 6 at operand 1 -- `mova za0h\.h\[w12,8:9\],{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.h\[w12,0\],{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.h\[w12,0:2\],{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.h\[w12,0:3\],{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 1 -- `mova za0h\.h\[w12,0:1,vgx2\],{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 1 -- `mova za0h\.h\[w12,0:1,vgx4\],{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: missing horizontal or vertical suffix at operand 1 -- `mova za0\.h\[w12,0:1\],{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `mova za0h\.s\[w12,0:1\],{z1\.s-z2\.s}' +[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za4h\.s\[w12,0:1\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za4v\.s\[w12,0:1\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `mova za0h\.s\[w11,0:1\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `mova za0h\.s\[w16,0:1\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 2 at operand 1 -- `mova za0h\.s\[w12,-2:-1\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: starting offset is not a multiple of 2 at operand 1 -- `mova za0h\.s\[w12,1:2\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 2 at operand 1 -- `mova za0h\.s\[w12,3:4\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 2 at operand 1 -- `mova za0h\.s\[w12,4:5\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.s\[w12,0\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.s\[w12,0:2\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.s\[w12,0:3\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 1 -- `mova za0h\.s\[w12,0:1,vgx2\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 1 -- `mova za0h\.s\[w12,0:1,vgx4\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: missing horizontal or vertical suffix at operand 1 -- `mova za0\.s\[w12,0:1\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `mova za0h\.d\[w12,0:1\],{z1\.d-z2\.d}' +[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za8h\.d\[w12,0:1\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za8v\.d\[w12,0:1\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `mova za0h\.d\[w11,0:1\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `mova za0h\.d\[w16,0:1\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `mova za0h\.d\[w12,-2:-1\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `mova za0h\.d\[w12,1:2\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `mova za0h\.d\[w12,2:3\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.d\[w12,0\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.d\[w12,0:2\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.d\[w12,0:3\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 1 -- `mova za0h\.d\[w12,0:1,vgx2\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 1 -- `mova za0h\.d\[w12,0:1,vgx4\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: missing horizontal or vertical suffix at operand 1 -- `mova za0\.d\[w12,0:1\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `mova za0h\.b\[w12,0:3\],{z1\.b-z4\.b}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `mova za0h\.b\[w12,0:3\],{z2\.b-z5\.b}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `mova za0h\.b\[w12,0:3\],{z3\.b-z6\.b}' +[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za1h\.b\[w12,0:3\],{z0\.b-z3\.b}' +[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za1v\.b\[w12,0:3\],{z0\.b-z3\.b}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `mova za0h\.b\[w11,0:3\],{z0\.b-z3\.b}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `mova za0h\.b\[w16,0:3\],{z0\.b-z3\.b}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 14 at operand 1 -- `mova za0h\.b\[w12,-4:-1\],{z0\.b-z3\.b}' +[^ :]+:[0-9]+: Error: starting offset is not a multiple of 2 at operand 1 -- `mova za0h\.b\[w12,1:4\],{z0\.b-z3\.b}' +[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.b\[w12,2:5\],{z0\.b-z3\.b}' +[^ :]+:[0-9]+: Error: starting offset is not a multiple of 2 at operand 1 -- `mova za0h\.b\[w12,3:6\],{z0\.b-z3\.b}' +[^ :]+:[0-9]+: Error: starting offset is not a multiple of 2 at operand 1 -- `mova za0h\.b\[w12,13:16\],{z0\.b-z3\.b}' +[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.b\[w12,14:17\],{z0\.b-z3\.b}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 14 at operand 1 -- `mova za0h\.b\[w12,15:18\],{z0\.b-z3\.b}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 14 at operand 1 -- `mova za0h\.b\[w12,16:19\],{z0\.b-z3\.b}' +[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.b\[w12,0\],{z0\.b-z3\.b}' +[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 1 -- `mova za0h\.b\[w12,0:1\],{z0\.b-z3\.b}' +[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.b\[w12,0:2\],{z0\.b-z3\.b}' +[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.b\[w12,0:3,vgx2\],{z0\.b-z3\.b}' +[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.b\[w12,0:3,vgx4\],{z0\.b-z3\.b}' +[^ :]+:[0-9]+: Error: missing horizontal or vertical suffix at operand 1 -- `mova za0\.b\[w12,0:3\],{z0\.b-z3\.b}' +[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.h\[w12,0:3\],{z1\.h-z2\.h}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `mova za0h\.h\[w12,0:3\],{z2\.h-z5\.h}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `mova za0h\.h\[w12,0:3\],{z3\.h-z6\.h}' +[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za2h\.h\[w12,0:3\],{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za2v\.h\[w12,0:3\],{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `mova za0h\.h\[w11,0:3\],{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `mova za0h\.h\[w16,0:3\],{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 6 at operand 1 -- `mova za0h\.h\[w12,-4:-1\],{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: starting offset is not a multiple of 2 at operand 1 -- `mova za0h\.h\[w12,1:2\],{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: starting offset is not a multiple of 2 at operand 1 -- `mova za0h\.h\[w12,5:8\],{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.h\[w12,6:9\],{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 6 at operand 1 -- `mova za0h\.h\[w12,7:10\],{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 6 at operand 1 -- `mova za0h\.h\[w12,8:11\],{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.h\[w12,0\],{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 1 -- `mova za0h\.h\[w12,0:1\],{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.h\[w12,0:2\],{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.h\[w12,0:3,vgx2\],{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.h\[w12,0:3,vgx4\],{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: missing horizontal or vertical suffix at operand 1 -- `mova za0\.h\[w12,0:3\],{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.s\[w12,0:3\],{z1\.s-z2\.s}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `mova za0h\.s\[w12,0:3\],{z2\.s-z5\.s}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `mova za0h\.s\[w12,0:3\],{z3\.s-z6\.s}' +[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za4h\.s\[w12,0:3\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za4v\.s\[w12,0:3\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `mova za0h\.s\[w11,0:3\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `mova za0h\.s\[w16,0:3\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 2 at operand 1 -- `mova za0h\.s\[w12,-4:-1\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: starting offset is not a multiple of 2 at operand 1 -- `mova za0h\.s\[w12,1:4\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.s\[w12,2:5\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 2 at operand 1 -- `mova za0h\.s\[w12,3:6\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 2 at operand 1 -- `mova za0h\.s\[w12,4:7\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.s\[w12,0\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 1 -- `mova za0h\.s\[w12,0:1\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.s\[w12,0:2\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.s\[w12,0:3,vgx2\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.s\[w12,0:3,vgx4\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: missing horizontal or vertical suffix at operand 1 -- `mova za0\.s\[w12,0:3\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.d\[w12,0:3\],{z1\.d-z2\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `mova za0h\.d\[w12,0:3\],{z2\.d-z5\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `mova za0h\.d\[w12,0:3\],{z3\.d-z6\.d}' +[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za8h\.d\[w12,0:3\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za8v\.d\[w12,0:3\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `mova za0h\.d\[w11,0:3\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w12-w15 at operand 1 -- `mova za0h\.d\[w16,0:3\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `mova za0h\.d\[w12,-4:-1\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `mova za0h\.d\[w12,1:4\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `mova za0h\.d\[w12,2:5\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `mova za0h\.d\[w12,3:6\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `mova za0h\.d\[w12,4:7\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.d\[w12,0\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: expected a range of four offsets at operand 1 -- `mova za0h\.d\[w12,0:1\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.d\[w12,0:2\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.d\[w12,0:3,vgx2\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: expected a range of two offsets at operand 1 -- `mova za0h\.d\[w12,0:3,vgx4\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: missing horizontal or vertical suffix at operand 1 -- `mova za0\.d\[w12,0:3\],{z0\.d-z3\.d}' diff --git a/gas/testsuite/gas/aarch64/sme2-1-invalid.s b/gas/testsuite/gas/aarch64/sme2-1-invalid.s new file mode 100644 index 00000000000..36ee20f64f9 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-1-invalid.s @@ -0,0 +1,323 @@ + mov 0, za.b[w8, 0] + mov { z0.b - z1.b }, 0 + + mov { z0.d - z1.d }, za.q[w8, 0] + mov { z1.d - z2.d }, za.d[w8, 0] + mov { z0.d - z1.d }, za.d[w7, 0] + mov { z0.d - z1.d }, za.d[w12, 0] + mov { z0.d - z1.d }, za.d[w8, -1] + mov { z0.d - z1.d }, za.d[w8, 8] + + mov { z0.d - z3.d }, za.q[w8, 0] + mov { z1.d - z4.d }, za.d[w8, 0] + mov { z2.d - z5.d }, za.d[w8, 0] + mov { z3.d - z6.d }, za.d[w8, 0] + mov { z0.d - z3.d }, za.d[w7, 0] + mov { z0.d - z3.d }, za.d[w12, 0] + mov { z0.d - z3.d }, za.d[w8, -1] + mov { z0.d - z3.d }, za.d[w8, 8] + + mov { z1.b - z2.b }, za0h.b[w8, 0:1] + mov { z0.b - z1.b }, za1h.b[w12, 0:1] + mov { z0.b - z1.b }, za1v.b[w12, 0:1] + mov { z0.b - z1.b }, za0h.b[w11, 0:1] + mov { z0.b - z1.b }, za0h.b[w16, 0:1] + mov { z0.b - z1.b }, za0h.b[w12, -2:-1] + mov { z0.b - z1.b }, za0h.b[w12, 1:2] + mov { z0.b - z1.b }, za0h.b[w12, 15:16] + mov { z0.b - z1.b }, za0h.b[w12, 16:17] + mov { z0.b - z1.b }, za0h.b[w12, 0] + mov { z0.b - z1.b }, za0h.b[w12, 0:2] + mov { z0.b - z1.b }, za0h.b[w12, 0:3] + mov { z0.b - z1.b }, za0h.b[w12, 0:1, vgx2] + mov { z0.b - z1.b }, za0h.b[w12, 0:1, vgx4] + mov { z0.b - z1.b }, za0.b[w12, 0:1] + + mov { z1.h - z2.h }, za0h.h[w12, 0:1] + mov { z0.h - z1.h }, za2h.h[w12, 0:1] + mov { z0.h - z1.h }, za2v.h[w12, 0:1] + mov { z0.h - z1.h }, za0h.h[w11, 0:1] + mov { z0.h - z1.h }, za0h.h[w16, 0:1] + mov { z0.h - z1.h }, za0h.h[w12, -2:-1] + mov { z0.h - z1.h }, za0h.h[w12, 1:2] + mov { z0.h - z1.h }, za0h.h[w12, 7:8] + mov { z0.h - z1.h }, za0h.h[w12, 8:9] + mov { z0.h - z1.h }, za0h.h[w12, 0] + mov { z0.h - z1.h }, za0h.h[w12, 0:2] + mov { z0.h - z1.h }, za0h.h[w12, 0:3] + mov { z0.h - z1.h }, za0h.h[w12, 0:1, vgx2] + mov { z0.h - z1.h }, za0h.h[w12, 0:1, vgx4] + mov { z0.h - z1.h }, za0.h[w12, 0:1] + + mov { z1.s - z2.s }, za0h.s[w12, 0:1] + mov { z0.s - z1.s }, za4h.s[w12, 0:1] + mov { z0.s - z1.s }, za4v.s[w12, 0:1] + mov { z0.s - z1.s }, za0h.s[w11, 0:1] + mov { z0.s - z1.s }, za0h.s[w16, 0:1] + mov { z0.s - z1.s }, za0h.s[w12, -2:-1] + mov { z0.s - z1.s }, za0h.s[w12, 1:2] + mov { z0.s - z1.s }, za0h.s[w12, 3:4] + mov { z0.s - z1.s }, za0h.s[w12, 4:5] + mov { z0.s - z1.s }, za0h.s[w12, 0] + mov { z0.s - z1.s }, za0h.s[w12, 0:2] + mov { z0.s - z1.s }, za0h.s[w12, 0:3] + mov { z0.s - z1.s }, za0h.s[w12, 0:1, vgx2] + mov { z0.s - z1.s }, za0h.s[w12, 0:1, vgx4] + mov { z0.s - z1.s }, za0.s[w12, 0:1] + + mov { z1.d - z2.d }, za0h.d[w12, 0:1] + mov { z0.d - z1.d }, za8h.d[w12, 0:1] + mov { z0.d - z1.d }, za8v.d[w12, 0:1] + mov { z0.d - z1.d }, za0h.d[w11, 0:1] + mov { z0.d - z1.d }, za0h.d[w16, 0:1] + mov { z0.d - z1.d }, za0h.d[w12, -2:-1] + mov { z0.d - z1.d }, za0h.d[w12, 1:2] + mov { z0.d - z1.d }, za0h.d[w12, 2:3] + mov { z0.d - z1.d }, za0h.d[w12, 0] + mov { z0.d - z1.d }, za0h.d[w12, 0:2] + mov { z0.d - z1.d }, za0h.d[w12, 0:3] + mov { z0.d - z1.d }, za0h.d[w12, 0:1, vgx2] + mov { z0.d - z1.d }, za0h.d[w12, 0:1, vgx4] + mov { z0.d - z1.d }, za0.d[w12, 0:1] + + mov { z1.b - z4.b }, za0h.b[w12, 0:3] + mov { z2.b - z5.b }, za0h.b[w12, 0:3] + mov { z3.b - z6.b }, za0h.b[w12, 0:3] + mov { z0.b - z3.b }, za1h.b[w12, 0:3] + mov { z0.b - z3.b }, za1v.b[w12, 0:3] + mov { z0.b - z3.b }, za0h.b[w11, 0:3] + mov { z0.b - z3.b }, za0h.b[w16, 0:3] + mov { z0.b - z3.b }, za0h.b[w12, -4:-1] + mov { z0.b - z3.b }, za0h.b[w12, 1:4] + mov { z0.b - z3.b }, za0h.b[w12, 2:5] + mov { z0.b - z3.b }, za0h.b[w12, 3:6] + mov { z0.b - z3.b }, za0h.b[w12, 13:16] + mov { z0.b - z3.b }, za0h.b[w12, 14:17] + mov { z0.b - z3.b }, za0h.b[w12, 15:18] + mov { z0.b - z3.b }, za0h.b[w12, 16:19] + mov { z0.b - z3.b }, za0h.b[w12, 0] + mov { z0.b - z3.b }, za0h.b[w12, 0:1] + mov { z0.b - z3.b }, za0h.b[w12, 0:2] + mov { z0.b - z3.b }, za0h.b[w12, 0:3, vgx2] + mov { z0.b - z3.b }, za0h.b[w12, 0:3, vgx4] + mov { z0.b - z3.b }, za0.b[w12, 0:3] + + mov { z1.h - z2.h }, za0h.h[w12, 0:3] + mov { z2.h - z5.h }, za0h.h[w12, 0:3] + mov { z3.h - z6.h }, za0h.h[w12, 0:3] + mov { z0.h - z3.h }, za2h.h[w12, 0:3] + mov { z0.h - z3.h }, za2v.h[w12, 0:3] + mov { z0.h - z3.h }, za0h.h[w11, 0:3] + mov { z0.h - z3.h }, za0h.h[w16, 0:3] + mov { z0.h - z3.h }, za0h.h[w12, -4:-1] + mov { z0.h - z3.h }, za0h.h[w12, 1:2] + mov { z0.h - z3.h }, za0h.h[w12, 5:8] + mov { z0.h - z3.h }, za0h.h[w12, 6:9] + mov { z0.h - z3.h }, za0h.h[w12, 7:10] + mov { z0.h - z3.h }, za0h.h[w12, 8:11] + mov { z0.h - z3.h }, za0h.h[w12, 0] + mov { z0.h - z3.h }, za0h.h[w12, 0:1] + mov { z0.h - z3.h }, za0h.h[w12, 0:2] + mov { z0.h - z3.h }, za0h.h[w12, 0:3, vgx2] + mov { z0.h - z3.h }, za0h.h[w12, 0:3, vgx4] + mov { z0.h - z3.h }, za0.h[w12, 0:3] + + mov { z1.s - z2.s }, za0h.s[w12, 0:3] + mov { z2.s - z5.s }, za0h.s[w12, 0:3] + mov { z3.s - z6.s }, za0h.s[w12, 0:3] + mov { z0.s - z3.s }, za4h.s[w12, 0:3] + mov { z0.s - z3.s }, za4v.s[w12, 0:3] + mov { z0.s - z3.s }, za0h.s[w11, 0:3] + mov { z0.s - z3.s }, za0h.s[w16, 0:3] + mov { z0.s - z3.s }, za0h.s[w12, -4:-1] + mov { z0.s - z3.s }, za0h.s[w12, 1:4] + mov { z0.s - z3.s }, za0h.s[w12, 2:5] + mov { z0.s - z3.s }, za0h.s[w12, 3:6] + mov { z0.s - z3.s }, za0h.s[w12, 4:7] + mov { z0.s - z3.s }, za0h.s[w12, 0] + mov { z0.s - z3.s }, za0h.s[w12, 0:1] + mov { z0.s - z3.s }, za0h.s[w12, 0:2] + mov { z0.s - z3.s }, za0h.s[w12, 0:3, vgx2] + mov { z0.s - z3.s }, za0h.s[w12, 0:3, vgx4] + mov { z0.s - z3.s }, za0.s[w12, 0:3] + + mov { z1.d - z2.d }, za0h.d[w12, 0:3] + mov { z2.d - z5.d }, za0h.d[w12, 0:3] + mov { z3.d - z6.d }, za0h.d[w12, 0:3] + mov { z0.d - z3.d }, za8h.d[w12, 0:3] + mov { z0.d - z3.d }, za8v.d[w12, 0:3] + mov { z0.d - z3.d }, za0h.d[w11, 0:3] + mov { z0.d - z3.d }, za0h.d[w16, 0:3] + mov { z0.d - z3.d }, za0h.d[w12, -4:-1] + mov { z0.d - z3.d }, za0h.d[w12, 1:4] + mov { z0.d - z3.d }, za0h.d[w12, 2:5] + mov { z0.d - z3.d }, za0h.d[w12, 3:6] + mov { z0.d - z3.d }, za0h.d[w12, 4:7] + mov { z0.d - z3.d }, za0h.d[w12, 0] + mov { z0.d - z3.d }, za0h.d[w12, 0:1] + mov { z0.d - z3.d }, za0h.d[w12, 0:2] + mov { z0.d - z3.d }, za0h.d[w12, 0:3, vgx2] + mov { z0.d - z3.d }, za0h.d[w12, 0:3, vgx4] + mov { z0.d - z3.d }, za0.d[w12, 0:3] + + mova 0, za.b[w8, 0] + mova { z0.b - z1.b }, 0 + + mova za.q[w8, 0], { z0.q - z1.q } + mova za.d[w7, 0], { z0.d - z1.d } + mova za.d[w12, 0], { z0.d - z1.d } + mova za.d[w8, -1], { z0.d - z1.d } + mova za.d[w8, 8], { z0.d - z1.d } + mova za.d[w8, 0], { z1.d - z2.d } + + mova za.q[w8, 0], { z0.q - z3.q } + mova za.d[w7, 0], { z0.d - z3.d } + mova za.d[w12, 0], { z0.d - z3.d } + mova za.d[w8, -1], { z0.d - z3.d } + mova za.d[w8, 8], { z0.d - z3.d } + mova za.d[w8, 0], { z1.d - z4.d } + mova za.d[w8, 0], { z2.d - z5.d } + mova za.d[w8, 0], { z3.d - z6.d } + + mova za0h.b[w8, 0:1], { z1.b - z2.b } + mova za1h.b[w12, 0:1], { z0.b - z1.b } + mova za1v.b[w12, 0:1], { z0.b - z1.b } + mova za0h.b[w11, 0:1], { z0.b - z1.b } + mova za0h.b[w16, 0:1], { z0.b - z1.b } + mova za0h.b[w12, -2:-1], { z0.b - z1.b } + mova za0h.b[w12, 1:2], { z0.b - z1.b } + mova za0h.b[w12, 15:16], { z0.b - z1.b } + mova za0h.b[w12, 16:17], { z0.b - z1.b } + mova za0h.b[w12, 0], { z0.b - z1.b } + mova za0h.b[w12, 0:2], { z0.b - z1.b } + mova za0h.b[w12, 0:3], { z0.b - z1.b } + mova za0h.b[w12, 0:1, vgx2], { z0.b - z1.b } + mova za0h.b[w12, 0:1, vgx4], { z0.b - z1.b } + mova za0.b[w12, 0:1], { z0.b - z1.b } + + mova za0h.h[w12, 0:1], { z1.h - z2.h } + mova za2h.h[w12, 0:1], { z0.h - z1.h } + mova za2v.h[w12, 0:1], { z0.h - z1.h } + mova za0h.h[w11, 0:1], { z0.h - z1.h } + mova za0h.h[w16, 0:1], { z0.h - z1.h } + mova za0h.h[w12, -2:-1], { z0.h - z1.h } + mova za0h.h[w12, 1:2], { z0.h - z1.h } + mova za0h.h[w12, 7:8], { z0.h - z1.h } + mova za0h.h[w12, 8:9], { z0.h - z1.h } + mova za0h.h[w12, 0], { z0.h - z1.h } + mova za0h.h[w12, 0:2], { z0.h - z1.h } + mova za0h.h[w12, 0:3], { z0.h - z1.h } + mova za0h.h[w12, 0:1, vgx2], { z0.h - z1.h } + mova za0h.h[w12, 0:1, vgx4], { z0.h - z1.h } + mova za0.h[w12, 0:1], { z0.h - z1.h } + + mova za0h.s[w12, 0:1], { z1.s - z2.s } + mova za4h.s[w12, 0:1], { z0.s - z1.s } + mova za4v.s[w12, 0:1], { z0.s - z1.s } + mova za0h.s[w11, 0:1], { z0.s - z1.s } + mova za0h.s[w16, 0:1], { z0.s - z1.s } + mova za0h.s[w12, -2:-1], { z0.s - z1.s } + mova za0h.s[w12, 1:2], { z0.s - z1.s } + mova za0h.s[w12, 3:4], { z0.s - z1.s } + mova za0h.s[w12, 4:5], { z0.s - z1.s } + mova za0h.s[w12, 0], { z0.s - z1.s } + mova za0h.s[w12, 0:2], { z0.s - z1.s } + mova za0h.s[w12, 0:3], { z0.s - z1.s } + mova za0h.s[w12, 0:1, vgx2], { z0.s - z1.s } + mova za0h.s[w12, 0:1, vgx4], { z0.s - z1.s } + mova za0.s[w12, 0:1], { z0.s - z1.s } + + mova za0h.d[w12, 0:1], { z1.d - z2.d } + mova za8h.d[w12, 0:1], { z0.d - z1.d } + mova za8v.d[w12, 0:1], { z0.d - z1.d } + mova za0h.d[w11, 0:1], { z0.d - z1.d } + mova za0h.d[w16, 0:1], { z0.d - z1.d } + mova za0h.d[w12, -2:-1], { z0.d - z1.d } + mova za0h.d[w12, 1:2], { z0.d - z1.d } + mova za0h.d[w12, 2:3], { z0.d - z1.d } + mova za0h.d[w12, 0], { z0.d - z1.d } + mova za0h.d[w12, 0:2], { z0.d - z1.d } + mova za0h.d[w12, 0:3], { z0.d - z1.d } + mova za0h.d[w12, 0:1, vgx2], { z0.d - z1.d } + mova za0h.d[w12, 0:1, vgx4], { z0.d - z1.d } + mova za0.d[w12, 0:1], { z0.d - z1.d } + + mova za0h.b[w12, 0:3], { z1.b - z4.b } + mova za0h.b[w12, 0:3], { z2.b - z5.b } + mova za0h.b[w12, 0:3], { z3.b - z6.b } + mova za1h.b[w12, 0:3], { z0.b - z3.b } + mova za1v.b[w12, 0:3], { z0.b - z3.b } + mova za0h.b[w11, 0:3], { z0.b - z3.b } + mova za0h.b[w16, 0:3], { z0.b - z3.b } + mova za0h.b[w12, -4:-1], { z0.b - z3.b } + mova za0h.b[w12, 1:4], { z0.b - z3.b } + mova za0h.b[w12, 2:5], { z0.b - z3.b } + mova za0h.b[w12, 3:6], { z0.b - z3.b } + mova za0h.b[w12, 13:16], { z0.b - z3.b } + mova za0h.b[w12, 14:17], { z0.b - z3.b } + mova za0h.b[w12, 15:18], { z0.b - z3.b } + mova za0h.b[w12, 16:19], { z0.b - z3.b } + mova za0h.b[w12, 0], { z0.b - z3.b } + mova za0h.b[w12, 0:1], { z0.b - z3.b } + mova za0h.b[w12, 0:2], { z0.b - z3.b } + mova za0h.b[w12, 0:3, vgx2], { z0.b - z3.b } + mova za0h.b[w12, 0:3, vgx4], { z0.b - z3.b } + mova za0.b[w12, 0:3], { z0.b - z3.b } + + mova za0h.h[w12, 0:3], { z1.h - z2.h } + mova za0h.h[w12, 0:3], { z2.h - z5.h } + mova za0h.h[w12, 0:3], { z3.h - z6.h } + mova za2h.h[w12, 0:3], { z0.h - z3.h } + mova za2v.h[w12, 0:3], { z0.h - z3.h } + mova za0h.h[w11, 0:3], { z0.h - z3.h } + mova za0h.h[w16, 0:3], { z0.h - z3.h } + mova za0h.h[w12, -4:-1], { z0.h - z3.h } + mova za0h.h[w12, 1:2], { z0.h - z3.h } + mova za0h.h[w12, 5:8], { z0.h - z3.h } + mova za0h.h[w12, 6:9], { z0.h - z3.h } + mova za0h.h[w12, 7:10], { z0.h - z3.h } + mova za0h.h[w12, 8:11], { z0.h - z3.h } + mova za0h.h[w12, 0], { z0.h - z3.h } + mova za0h.h[w12, 0:1], { z0.h - z3.h } + mova za0h.h[w12, 0:2], { z0.h - z3.h } + mova za0h.h[w12, 0:3, vgx2], { z0.h - z3.h } + mova za0h.h[w12, 0:3, vgx4], { z0.h - z3.h } + mova za0.h[w12, 0:3], { z0.h - z3.h } + + mova za0h.s[w12, 0:3], { z1.s - z2.s } + mova za0h.s[w12, 0:3], { z2.s - z5.s } + mova za0h.s[w12, 0:3], { z3.s - z6.s } + mova za4h.s[w12, 0:3], { z0.s - z3.s } + mova za4v.s[w12, 0:3], { z0.s - z3.s } + mova za0h.s[w11, 0:3], { z0.s - z3.s } + mova za0h.s[w16, 0:3], { z0.s - z3.s } + mova za0h.s[w12, -4:-1], { z0.s - z3.s } + mova za0h.s[w12, 1:4], { z0.s - z3.s } + mova za0h.s[w12, 2:5], { z0.s - z3.s } + mova za0h.s[w12, 3:6], { z0.s - z3.s } + mova za0h.s[w12, 4:7], { z0.s - z3.s } + mova za0h.s[w12, 0], { z0.s - z3.s } + mova za0h.s[w12, 0:1], { z0.s - z3.s } + mova za0h.s[w12, 0:2], { z0.s - z3.s } + mova za0h.s[w12, 0:3, vgx2], { z0.s - z3.s } + mova za0h.s[w12, 0:3, vgx4], { z0.s - z3.s } + mova za0.s[w12, 0:3], { z0.s - z3.s } + + mova za0h.d[w12, 0:3], { z1.d - z2.d } + mova za0h.d[w12, 0:3], { z2.d - z5.d } + mova za0h.d[w12, 0:3], { z3.d - z6.d } + mova za8h.d[w12, 0:3], { z0.d - z3.d } + mova za8v.d[w12, 0:3], { z0.d - z3.d } + mova za0h.d[w11, 0:3], { z0.d - z3.d } + mova za0h.d[w16, 0:3], { z0.d - z3.d } + mova za0h.d[w12, -4:-1], { z0.d - z3.d } + mova za0h.d[w12, 1:4], { z0.d - z3.d } + mova za0h.d[w12, 2:5], { z0.d - z3.d } + mova za0h.d[w12, 3:6], { z0.d - z3.d } + mova za0h.d[w12, 4:7], { z0.d - z3.d } + mova za0h.d[w12, 0], { z0.d - z3.d } + mova za0h.d[w12, 0:1], { z0.d - z3.d } + mova za0h.d[w12, 0:2], { z0.d - z3.d } + mova za0h.d[w12, 0:3, vgx2], { z0.d - z3.d } + mova za0h.d[w12, 0:3, vgx4], { z0.d - z3.d } + mova za0.d[w12, 0:3], { z0.d - z3.d } diff --git a/gas/testsuite/gas/aarch64/sme2-1-noarch.d b/gas/testsuite/gas/aarch64/sme2-1-noarch.d new file mode 100644 index 00000000000..cb6665108da --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-1-noarch.d @@ -0,0 +1,3 @@ +#as: -march=armv8-a+sme +#source: sme2-1.s +#error_output: sme2-1-noarch.l diff --git a/gas/testsuite/gas/aarch64/sme2-1-noarch.l b/gas/testsuite/gas/aarch64/sme2-1-noarch.l new file mode 100644 index 00000000000..9d9fd083d7c --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-1-noarch.l @@ -0,0 +1,289 @@ +[^ :]+: Assembler messages: +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.b-z1\.b},za\.b\[w8,0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.h-z1\.h},za\.h\[w8,0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.s-z1\.s},za\.s\[w8,0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.d-z1\.d},za\.d\[w8,0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z30\.d-z31\.d},za\.d\[w8,0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.d-z1\.d},za\.d\[w11,0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.d-z1\.d},za\.d\[w8,7\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.b-z3\.b},za\.b\[w8,0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.h-z3\.h},za\.h\[w8,0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.s-z3\.s},za\.s\[w8,0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.d-z3\.d},za\.d\[w8,0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z28\.d-z31\.d},za\.d\[w8,0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.d-z3\.d},za\.d\[w11,0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.d-z3\.d},za\.d\[w8,7\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.b-z1\.b},za0h\.b\[w12,0:1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z30\.b-z31\.b},za0h\.b\[w12,0:1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.b-z1\.b},za0v\.b\[w12,0:1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.b-z1\.b},za0h\.b\[w15,0:1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.b-z1\.b},za0h\.b\[w12,14:15\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z8\.b-z9\.b},za0h\.b\[w14,6:7\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.h-z1\.h},za0h\.h\[w12,0:1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z30\.h-z31\.h},za0h\.h\[w12,0:1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.h-z1\.h},za0v\.h\[w12,0:1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.h-z1\.h},za1h\.h\[w12,0:1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.h-z1\.h},za1v\.h\[w12,0:1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.h-z1\.h},za0h\.h\[w15,0:1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.h-z1\.h},za0h\.h\[w12,6:7\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z10\.h-z11\.h},za0h\.h\[w13,2:3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.s-z1\.s},za0h\.s\[w12,0:1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z30\.s-z31\.s},za0h\.s\[w12,0:1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.s-z1\.s},za0v\.s\[w12,0:1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.s-z1\.s},za3h\.s\[w12,0:1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.s-z1\.s},za3v\.s\[w12,0:1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.s-z1\.s},za0h\.s\[w15,0:1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.s-z1\.s},za0h\.s\[w12,2:3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z18\.s-z19\.s},za2h\.s\[w14,0:1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.d-z1\.d},za0h\.d\[w12,0:1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z30\.d-z31\.d},za0h\.d\[w12,0:1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.d-z1\.d},za0v\.d\[w12,0:1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.d-z1\.d},za7h\.d\[w12,0:1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.d-z1\.d},za7v\.d\[w12,0:1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.d-z1\.d},za0h\.d\[w15,0:1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z22\.d-z23\.d},za6h\.d\[w13,0:1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.b-z3\.b},za0h\.b\[w12,0:3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z28\.b-z31\.b},za0h\.b\[w12,0:3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.b-z3\.b},za0v\.b\[w12,0:3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.b-z3\.b},za0h\.b\[w15,0:3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.b-z3\.b},za0h\.b\[w12,12:15\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z12\.b-z15\.b},za0h\.b\[w14,8:11\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.h-z3\.h},za0h\.h\[w12,0:3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z28\.h-z31\.h},za0h\.h\[w12,0:3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.h-z3\.h},za0v\.h\[w12,0:3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.h-z3\.h},za1h\.h\[w12,0:3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.h-z3\.h},za1v\.h\[w12,0:3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.h-z3\.h},za0h\.h\[w15,0:3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.h-z3\.h},za0h\.h\[w12,4:7\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z16\.h-z19\.h},za0h\.h\[w13,4:7\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.s-z3\.s},za0h\.s\[w12,0:3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z28\.s-z31\.s},za0h\.s\[w12,0:3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.s-z3\.s},za0v\.s\[w12,0:3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.s-z3\.s},za3h\.s\[w12,0:3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.s-z3\.s},za3v\.s\[w12,0:3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.s-z3\.s},za0h\.s\[w15,0:3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z20\.s-z23\.s},za2h\.s\[w13,0:3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.d-z3\.d},za0h\.d\[w12,0:3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z28\.d-z31\.d},za0h\.d\[w12,0:3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.d-z3\.d},za0v\.d\[w12,0:3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.d-z3\.d},za7h\.d\[w12,0:3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.d-z3\.d},za7v\.d\[w12,0:3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z0\.d-z3\.d},za0h\.d\[w15,0:3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov {z24\.d-z27\.d},za5h\.d\[w13,0:3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za\.b\[w8,0\],{z0\.b-z1\.b}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za\.h\[w8,0\],{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za\.s\[w8,0\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za\.d\[w8,0\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za\.d\[w11,0\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za\.d\[w8,7\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za\.d\[w8,0\],{z30\.d-z31\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za\.d\[w9,5\],{z2\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za\.b\[w8,0\],{z0\.b-z3\.b}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za\.h\[w8,0\],{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za\.s\[w8,0\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za\.d\[w8,0\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za\.d\[w11,0\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za\.d\[w8,7\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za\.d\[w8,0\],{z28\.d-z31\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za\.d\[w10,1\],{z20\.d-z23\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.b\[w12,0:1\],{z0\.b-z1\.b}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za0v\.b\[w12,0:1\],{z0\.b-z1\.b}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.b\[w15,0:1\],{z0\.b-z1\.b}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.b\[w12,14:15\],{z0\.b-z1\.b}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.b\[w12,0:1\],{z30\.b-z31\.b}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.b\[w14,6:7\],{z8\.b-z9\.b}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.h\[w12,0:1\],{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za0v\.h\[w12,0:1\],{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za1h\.h\[w12,0:1\],{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za1v\.h\[w12,0:1\],{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.h\[w15,0:1\],{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.h\[w12,6:7\],{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.h\[w12,0:1\],{z30\.h-z31\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.h\[w13,2:3\],{z10\.h-z11\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.s\[w12,0:1\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za0v\.s\[w12,0:1\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za3h\.s\[w12,0:1\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za3v\.s\[w12,0:1\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.s\[w15,0:1\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.s\[w12,2:3\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.s\[w12,0:1\],{z30\.s-z31\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za2h\.s\[w14,0:1\],{z18\.s-z19\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.d\[w12,0:1\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za0v\.d\[w12,0:1\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za7h\.d\[w12,0:1\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za7v\.d\[w12,0:1\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.d\[w15,0:1\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.d\[w12,0:1\],{z30\.d-z31\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za6h\.d\[w13,0:1\],{z22\.d-z23\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.b\[w12,0:3\],{z0\.b-z3\.b}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za0v\.b\[w12,0:3\],{z0\.b-z3\.b}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.b\[w15,0:3\],{z0\.b-z3\.b}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.b\[w12,12:15\],{z0\.b-z3\.b}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.b\[w12,0:3\],{z28\.b-z31\.b}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.b\[w14,8:11\],{z12\.b-z15\.b}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.h\[w12,0:3\],{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za0v\.h\[w12,0:3\],{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za1h\.h\[w12,0:3\],{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za1v\.h\[w12,0:3\],{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.h\[w15,0:3\],{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.h\[w12,4:7\],{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.h\[w12,0:3\],{z28\.h-z31\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.h\[w13,4:7\],{z16\.h-z19\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.s\[w12,0:3\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za0v\.s\[w12,0:3\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za3h\.s\[w12,0:3\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za3v\.s\[w12,0:3\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.s\[w15,0:3\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.s\[w12,0:3\],{z28\.s-z31\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za2h\.s\[w13,0:3\],{z20\.s-z23\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.d\[w12,0:3\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za0v\.d\[w12,0:3\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za7h\.d\[w12,0:3\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za7v\.d\[w12,0:3\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.d\[w15,0:3\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za0h\.d\[w12,0:3\],{z28\.d-z31\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `mov za5h\.d\[w13,0:3\],{z24\.d-z27\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.b-z1\.b},za\.b\[w8,0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.h-z1\.h},za\.h\[w8,0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.s-z1\.s},za\.s\[w8,0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.d-z1\.d},za\.d\[w8,0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z30\.d-z31\.d},za\.d\[w8,0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.d-z1\.d},za\.d\[w11,0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.d-z1\.d},za\.d\[w8,7\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.b-z3\.b},za\.b\[w8,0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.h-z3\.h},za\.h\[w8,0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.s-z3\.s},za\.s\[w8,0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.d-z3\.d},za\.d\[w8,0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z28\.d-z31\.d},za\.d\[w8,0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.d-z3\.d},za\.d\[w11,0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.d-z3\.d},za\.d\[w8,7\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.b-z1\.b},za0h\.b\[w12,0:1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z30\.b-z31\.b},za0h\.b\[w12,0:1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.b-z1\.b},za0v\.b\[w12,0:1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.b-z1\.b},za0h\.b\[w15,0:1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.b-z1\.b},za0h\.b\[w12,14:15\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z8\.b-z9\.b},za0h\.b\[w14,6:7\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.h-z1\.h},za0h\.h\[w12,0:1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z30\.h-z31\.h},za0h\.h\[w12,0:1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.h-z1\.h},za0v\.h\[w12,0:1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.h-z1\.h},za1h\.h\[w12,0:1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.h-z1\.h},za1v\.h\[w12,0:1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.h-z1\.h},za0h\.h\[w15,0:1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.h-z1\.h},za0h\.h\[w12,6:7\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z10\.h-z11\.h},za0h\.h\[w13,2:3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.s-z1\.s},za0h\.s\[w12,0:1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z30\.s-z31\.s},za0h\.s\[w12,0:1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.s-z1\.s},za0v\.s\[w12,0:1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.s-z1\.s},za3h\.s\[w12,0:1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.s-z1\.s},za3v\.s\[w12,0:1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.s-z1\.s},za0h\.s\[w15,0:1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.s-z1\.s},za0h\.s\[w12,2:3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z18\.s-z19\.s},za2h\.s\[w14,0:1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.d-z1\.d},za0h\.d\[w12,0:1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z30\.d-z31\.d},za0h\.d\[w12,0:1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.d-z1\.d},za0v\.d\[w12,0:1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.d-z1\.d},za7h\.d\[w12,0:1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.d-z1\.d},za7v\.d\[w12,0:1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.d-z1\.d},za0h\.d\[w15,0:1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z22\.d-z23\.d},za6h\.d\[w13,0:1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.b-z3\.b},za0h\.b\[w12,0:3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z28\.b-z31\.b},za0h\.b\[w12,0:3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.b-z3\.b},za0v\.b\[w12,0:3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.b-z3\.b},za0h\.b\[w15,0:3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.b-z3\.b},za0h\.b\[w12,12:15\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z12\.b-z15\.b},za0h\.b\[w14,8:11\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.h-z3\.h},za0h\.h\[w12,0:3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z28\.h-z31\.h},za0h\.h\[w12,0:3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.h-z3\.h},za0v\.h\[w12,0:3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.h-z3\.h},za1h\.h\[w12,0:3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.h-z3\.h},za1v\.h\[w12,0:3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.h-z3\.h},za0h\.h\[w15,0:3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.h-z3\.h},za0h\.h\[w12,4:7\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z16\.h-z19\.h},za0h\.h\[w13,4:7\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.s-z3\.s},za0h\.s\[w12,0:3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z28\.s-z31\.s},za0h\.s\[w12,0:3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.s-z3\.s},za0v\.s\[w12,0:3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.s-z3\.s},za3h\.s\[w12,0:3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.s-z3\.s},za3v\.s\[w12,0:3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.s-z3\.s},za0h\.s\[w15,0:3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z20\.s-z23\.s},za2h\.s\[w13,0:3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.d-z3\.d},za0h\.d\[w12,0:3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z28\.d-z31\.d},za0h\.d\[w12,0:3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.d-z3\.d},za0v\.d\[w12,0:3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.d-z3\.d},za7h\.d\[w12,0:3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.d-z3\.d},za7v\.d\[w12,0:3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z0\.d-z3\.d},za0h\.d\[w15,0:3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova {z24\.d-z27\.d},za5h\.d\[w13,0:3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za\.b\[w8,0\],{z0\.b-z1\.b}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za\.h\[w8,0\],{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za\.s\[w8,0\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za\.d\[w8,0\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za\.d\[w11,0\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za\.d\[w8,7\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za\.d\[w8,0\],{z30\.d-z31\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za\.d\[w9,5\],{z2\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za\.b\[w8,0\],{z0\.b-z3\.b}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za\.h\[w8,0\],{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za\.s\[w8,0\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za\.d\[w8,0\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za\.d\[w11,0\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za\.d\[w8,7\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za\.d\[w8,0\],{z28\.d-z31\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za\.d\[w10,1\],{z20\.d-z23\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.b\[w12,0:1\],{z0\.b-z1\.b}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za0v\.b\[w12,0:1\],{z0\.b-z1\.b}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.b\[w15,0:1\],{z0\.b-z1\.b}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.b\[w12,14:15\],{z0\.b-z1\.b}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.b\[w12,0:1\],{z30\.b-z31\.b}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.b\[w14,6:7\],{z8\.b-z9\.b}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.h\[w12,0:1\],{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za0v\.h\[w12,0:1\],{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za1h\.h\[w12,0:1\],{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za1v\.h\[w12,0:1\],{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.h\[w15,0:1\],{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.h\[w12,6:7\],{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.h\[w12,0:1\],{z30\.h-z31\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.h\[w13,2:3\],{z10\.h-z11\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.s\[w12,0:1\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za0v\.s\[w12,0:1\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za3h\.s\[w12,0:1\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za3v\.s\[w12,0:1\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.s\[w15,0:1\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.s\[w12,2:3\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.s\[w12,0:1\],{z30\.s-z31\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za2h\.s\[w14,0:1\],{z18\.s-z19\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.d\[w12,0:1\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za0v\.d\[w12,0:1\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za7h\.d\[w12,0:1\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za7v\.d\[w12,0:1\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.d\[w15,0:1\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.d\[w12,0:1\],{z30\.d-z31\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za6h\.d\[w13,0:1\],{z22\.d-z23\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.b\[w12,0:3\],{z0\.b-z3\.b}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za0v\.b\[w12,0:3\],{z0\.b-z3\.b}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.b\[w15,0:3\],{z0\.b-z3\.b}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.b\[w12,12:15\],{z0\.b-z3\.b}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.b\[w12,0:3\],{z28\.b-z31\.b}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.b\[w14,8:11\],{z12\.b-z15\.b}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.h\[w12,0:3\],{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za0v\.h\[w12,0:3\],{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za1h\.h\[w12,0:3\],{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za1v\.h\[w12,0:3\],{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.h\[w15,0:3\],{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.h\[w12,4:7\],{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.h\[w12,0:3\],{z28\.h-z31\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.h\[w13,4:7\],{z16\.h-z19\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.s\[w12,0:3\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za0v\.s\[w12,0:3\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za3h\.s\[w12,0:3\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za3v\.s\[w12,0:3\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.s\[w15,0:3\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.s\[w12,0:3\],{z28\.s-z31\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za2h\.s\[w13,0:3\],{z20\.s-z23\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.d\[w12,0:3\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za0v\.d\[w12,0:3\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za7h\.d\[w12,0:3\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za7v\.d\[w12,0:3\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.d\[w15,0:3\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za0h\.d\[w12,0:3\],{z28\.d-z31\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `mova za5h\.d\[w13,0:3\],{z24\.d-z27\.d}' diff --git a/gas/testsuite/gas/aarch64/sme2-1.d b/gas/testsuite/gas/aarch64/sme2-1.d new file mode 100644 index 00000000000..6fc248bb21f --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-1.d @@ -0,0 +1,305 @@ +#as: -march=armv8-a+sme2 +#objdump: -dr + +[^:]+: file format .* + + +[^:]+: + +[^:]+: +[^:]+: c0060800 mov {z0\.d-z1\.d}, za\.d\[w8, 0, vgx2\] +[^:]+: c0060800 mov {z0\.d-z1\.d}, za\.d\[w8, 0, vgx2\] +[^:]+: c0060800 mov {z0\.d-z1\.d}, za\.d\[w8, 0, vgx2\] +[^:]+: c0060800 mov {z0\.d-z1\.d}, za\.d\[w8, 0, vgx2\] +[^:]+: c006081e mov {z30\.d-z31\.d}, za\.d\[w8, 0, vgx2\] +[^:]+: c0066800 mov {z0\.d-z1\.d}, za\.d\[w11, 0, vgx2\] +[^:]+: c00608e0 mov {z0\.d-z1\.d}, za\.d\[w8, 7, vgx2\] +[^:]+: c0060c00 mov {z0\.d-z3\.d}, za\.d\[w8, 0, vgx4\] +[^:]+: c0060c00 mov {z0\.d-z3\.d}, za\.d\[w8, 0, vgx4\] +[^:]+: c0060c00 mov {z0\.d-z3\.d}, za\.d\[w8, 0, vgx4\] +[^:]+: c0060c00 mov {z0\.d-z3\.d}, za\.d\[w8, 0, vgx4\] +[^:]+: c0060c1c mov {z28\.d-z31\.d}, za\.d\[w8, 0, vgx4\] +[^:]+: c0066c00 mov {z0\.d-z3\.d}, za\.d\[w11, 0, vgx4\] +[^:]+: c0060ce0 mov {z0\.d-z3\.d}, za\.d\[w8, 7, vgx4\] +[^:]+: c0060000 mov {z0\.b-z1\.b}, za0h\.b\[w12, 0:1\] +[^:]+: c006001e mov {z30\.b-z31\.b}, za0h\.b\[w12, 0:1\] +[^:]+: c0068000 mov {z0\.b-z1\.b}, za0v\.b\[w12, 0:1\] +[^:]+: c0066000 mov {z0\.b-z1\.b}, za0h\.b\[w15, 0:1\] +[^:]+: c00600e0 mov {z0\.b-z1\.b}, za0h\.b\[w12, 14:15\] +[^:]+: c0064068 mov {z8\.b-z9\.b}, za0h\.b\[w14, 6:7\] +[^:]+: c0460000 mov {z0\.h-z1\.h}, za0h\.h\[w12, 0:1\] +[^:]+: c046001e mov {z30\.h-z31\.h}, za0h\.h\[w12, 0:1\] +[^:]+: c0468000 mov {z0\.h-z1\.h}, za0v\.h\[w12, 0:1\] +[^:]+: c0460080 mov {z0\.h-z1\.h}, za1h\.h\[w12, 0:1\] +[^:]+: c0468080 mov {z0\.h-z1\.h}, za1v\.h\[w12, 0:1\] +[^:]+: c0466000 mov {z0\.h-z1\.h}, za0h\.h\[w15, 0:1\] +[^:]+: c0460060 mov {z0\.h-z1\.h}, za0h\.h\[w12, 6:7\] +[^:]+: c046202a mov {z10\.h-z11\.h}, za0h\.h\[w13, 2:3\] +[^:]+: c0860000 mov {z0\.s-z1\.s}, za0h\.s\[w12, 0:1\] +[^:]+: c086001e mov {z30\.s-z31\.s}, za0h\.s\[w12, 0:1\] +[^:]+: c0868000 mov {z0\.s-z1\.s}, za0v\.s\[w12, 0:1\] +[^:]+: c08600c0 mov {z0\.s-z1\.s}, za3h\.s\[w12, 0:1\] +[^:]+: c08680c0 mov {z0\.s-z1\.s}, za3v\.s\[w12, 0:1\] +[^:]+: c0866000 mov {z0\.s-z1\.s}, za0h\.s\[w15, 0:1\] +[^:]+: c0860020 mov {z0\.s-z1\.s}, za0h\.s\[w12, 2:3\] +[^:]+: c0864092 mov {z18\.s-z19\.s}, za2h\.s\[w14, 0:1\] +[^:]+: c0c60000 mov {z0\.d-z1\.d}, za0h\.d\[w12, 0:1\] +[^:]+: c0c6001e mov {z30\.d-z31\.d}, za0h\.d\[w12, 0:1\] +[^:]+: c0c68000 mov {z0\.d-z1\.d}, za0v\.d\[w12, 0:1\] +[^:]+: c0c600e0 mov {z0\.d-z1\.d}, za7h\.d\[w12, 0:1\] +[^:]+: c0c680e0 mov {z0\.d-z1\.d}, za7v\.d\[w12, 0:1\] +[^:]+: c0c66000 mov {z0\.d-z1\.d}, za0h\.d\[w15, 0:1\] +[^:]+: c0c620d6 mov {z22\.d-z23\.d}, za6h\.d\[w13, 0:1\] +[^:]+: c0060400 mov {z0\.b-z3\.b}, za0h\.b\[w12, 0:3\] +[^:]+: c006041c mov {z28\.b-z31\.b}, za0h\.b\[w12, 0:3\] +[^:]+: c0068400 mov {z0\.b-z3\.b}, za0v\.b\[w12, 0:3\] +[^:]+: c0066400 mov {z0\.b-z3\.b}, za0h\.b\[w15, 0:3\] +[^:]+: c0060460 mov {z0\.b-z3\.b}, za0h\.b\[w12, 12:15\] +[^:]+: c006444c mov {z12\.b-z15\.b}, za0h\.b\[w14, 8:11\] +[^:]+: c0460400 mov {z0\.h-z3\.h}, za0h\.h\[w12, 0:3\] +[^:]+: c046041c mov {z28\.h-z31\.h}, za0h\.h\[w12, 0:3\] +[^:]+: c0468400 mov {z0\.h-z3\.h}, za0v\.h\[w12, 0:3\] +[^:]+: c0460440 mov {z0\.h-z3\.h}, za1h\.h\[w12, 0:3\] +[^:]+: c0468440 mov {z0\.h-z3\.h}, za1v\.h\[w12, 0:3\] +[^:]+: c0466400 mov {z0\.h-z3\.h}, za0h\.h\[w15, 0:3\] +[^:]+: c0460420 mov {z0\.h-z3\.h}, za0h\.h\[w12, 4:7\] +[^:]+: c0462430 mov {z16\.h-z19\.h}, za0h\.h\[w13, 4:7\] +[^:]+: c0860400 mov {z0\.s-z3\.s}, za0h\.s\[w12, 0:3\] +[^:]+: c086041c mov {z28\.s-z31\.s}, za0h\.s\[w12, 0:3\] +[^:]+: c0868400 mov {z0\.s-z3\.s}, za0v\.s\[w12, 0:3\] +[^:]+: c0860460 mov {z0\.s-z3\.s}, za3h\.s\[w12, 0:3\] +[^:]+: c0868460 mov {z0\.s-z3\.s}, za3v\.s\[w12, 0:3\] +[^:]+: c0866400 mov {z0\.s-z3\.s}, za0h\.s\[w15, 0:3\] +[^:]+: c0862454 mov {z20\.s-z23\.s}, za2h\.s\[w13, 0:3\] +[^:]+: c0c60400 mov {z0\.d-z3\.d}, za0h\.d\[w12, 0:3\] +[^:]+: c0c6041c mov {z28\.d-z31\.d}, za0h\.d\[w12, 0:3\] +[^:]+: c0c68400 mov {z0\.d-z3\.d}, za0v\.d\[w12, 0:3\] +[^:]+: c0c604e0 mov {z0\.d-z3\.d}, za7h\.d\[w12, 0:3\] +[^:]+: c0c684e0 mov {z0\.d-z3\.d}, za7v\.d\[w12, 0:3\] +[^:]+: c0c66400 mov {z0\.d-z3\.d}, za0h\.d\[w15, 0:3\] +[^:]+: c0c624b8 mov {z24\.d-z27\.d}, za5h\.d\[w13, 0:3\] +[^:]+: c0060480 \.inst 0xc0060480 ; undefined +[^:]+: c00604e0 \.inst 0xc00604e0 ; undefined +[^:]+: c0460480 \.inst 0xc0460480 ; undefined +[^:]+: c04604e0 \.inst 0xc04604e0 ; undefined +[^:]+: c0860480 \.inst 0xc0860480 ; undefined +[^:]+: c08604e0 \.inst 0xc08604e0 ; undefined +[^:]+: c0c60480 mov {z0\.d-z3\.d}, za4h\.d\[w12, 0:3\] +[^:]+: c0c604e0 mov {z0\.d-z3\.d}, za7h\.d\[w12, 0:3\] +[^:]+: c0040800 mov za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d} +[^:]+: c0040800 mov za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d} +[^:]+: c0040800 mov za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d} +[^:]+: c0040800 mov za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d} +[^:]+: c0046800 mov za\.d\[w11, 0, vgx2\], {z0\.d-z1\.d} +[^:]+: c0040807 mov za\.d\[w8, 7, vgx2\], {z0\.d-z1\.d} +[^:]+: c0040bc0 mov za\.d\[w8, 0, vgx2\], {z30\.d-z31\.d} +[^:]+: c0042845 mov za\.d\[w9, 5, vgx2\], {z2\.d-z3\.d} +[^:]+: c0040c00 mov za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d} +[^:]+: c0040c00 mov za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d} +[^:]+: c0040c00 mov za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d} +[^:]+: c0040c00 mov za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d} +[^:]+: c0046c00 mov za\.d\[w11, 0, vgx4\], {z0\.d-z3\.d} +[^:]+: c0040c07 mov za\.d\[w8, 7, vgx4\], {z0\.d-z3\.d} +[^:]+: c0040f80 mov za\.d\[w8, 0, vgx4\], {z28\.d-z31\.d} +[^:]+: c0044e81 mov za\.d\[w10, 1, vgx4\], {z20\.d-z23\.d} +[^:]+: c0040000 mov za0h\.b\[w12, 0:1\], {z0\.b-z1\.b} +[^:]+: c0048000 mov za0v\.b\[w12, 0:1\], {z0\.b-z1\.b} +[^:]+: c0046000 mov za0h\.b\[w15, 0:1\], {z0\.b-z1\.b} +[^:]+: c0040007 mov za0h\.b\[w12, 14:15\], {z0\.b-z1\.b} +[^:]+: c00403c0 mov za0h\.b\[w12, 0:1\], {z30\.b-z31\.b} +[^:]+: c0044103 mov za0h\.b\[w14, 6:7\], {z8\.b-z9\.b} +[^:]+: c0440000 mov za0h\.h\[w12, 0:1\], {z0\.h-z1\.h} +[^:]+: c0448000 mov za0v\.h\[w12, 0:1\], {z0\.h-z1\.h} +[^:]+: c0440004 mov za1h\.h\[w12, 0:1\], {z0\.h-z1\.h} +[^:]+: c0448004 mov za1v\.h\[w12, 0:1\], {z0\.h-z1\.h} +[^:]+: c0446000 mov za0h\.h\[w15, 0:1\], {z0\.h-z1\.h} +[^:]+: c0440003 mov za0h\.h\[w12, 6:7\], {z0\.h-z1\.h} +[^:]+: c04403c0 mov za0h\.h\[w12, 0:1\], {z30\.h-z31\.h} +[^:]+: c0442141 mov za0h\.h\[w13, 2:3\], {z10\.h-z11\.h} +[^:]+: c0840000 mov za0h\.s\[w12, 0:1\], {z0\.s-z1\.s} +[^:]+: c0848000 mov za0v\.s\[w12, 0:1\], {z0\.s-z1\.s} +[^:]+: c0840006 mov za3h\.s\[w12, 0:1\], {z0\.s-z1\.s} +[^:]+: c0848006 mov za3v\.s\[w12, 0:1\], {z0\.s-z1\.s} +[^:]+: c0846000 mov za0h\.s\[w15, 0:1\], {z0\.s-z1\.s} +[^:]+: c0840001 mov za0h\.s\[w12, 2:3\], {z0\.s-z1\.s} +[^:]+: c08403c0 mov za0h\.s\[w12, 0:1\], {z30\.s-z31\.s} +[^:]+: c0844244 mov za2h\.s\[w14, 0:1\], {z18\.s-z19\.s} +[^:]+: c0c40000 mov za0h\.d\[w12, 0:1\], {z0\.d-z1\.d} +[^:]+: c0c48000 mov za0v\.d\[w12, 0:1\], {z0\.d-z1\.d} +[^:]+: c0c40007 mov za7h\.d\[w12, 0:1\], {z0\.d-z1\.d} +[^:]+: c0c48007 mov za7v\.d\[w12, 0:1\], {z0\.d-z1\.d} +[^:]+: c0c46000 mov za0h\.d\[w15, 0:1\], {z0\.d-z1\.d} +[^:]+: c0c403c0 mov za0h\.d\[w12, 0:1\], {z30\.d-z31\.d} +[^:]+: c0c422c6 mov za6h\.d\[w13, 0:1\], {z22\.d-z23\.d} +[^:]+: c0040400 mov za0h\.b\[w12, 0:3\], {z0\.b-z3\.b} +[^:]+: c0048400 mov za0v\.b\[w12, 0:3\], {z0\.b-z3\.b} +[^:]+: c0046400 mov za0h\.b\[w15, 0:3\], {z0\.b-z3\.b} +[^:]+: c0040403 mov za0h\.b\[w12, 12:15\], {z0\.b-z3\.b} +[^:]+: c0040780 mov za0h\.b\[w12, 0:3\], {z28\.b-z31\.b} +[^:]+: c0044582 mov za0h\.b\[w14, 8:11\], {z12\.b-z15\.b} +[^:]+: c0440400 mov za0h\.h\[w12, 0:3\], {z0\.h-z3\.h} +[^:]+: c0448400 mov za0v\.h\[w12, 0:3\], {z0\.h-z3\.h} +[^:]+: c0440402 mov za1h\.h\[w12, 0:3\], {z0\.h-z3\.h} +[^:]+: c0448402 mov za1v\.h\[w12, 0:3\], {z0\.h-z3\.h} +[^:]+: c0446400 mov za0h\.h\[w15, 0:3\], {z0\.h-z3\.h} +[^:]+: c0440401 mov za0h\.h\[w12, 4:7\], {z0\.h-z3\.h} +[^:]+: c0440780 mov za0h\.h\[w12, 0:3\], {z28\.h-z31\.h} +[^:]+: c0442601 mov za0h\.h\[w13, 4:7\], {z16\.h-z19\.h} +[^:]+: c0840400 mov za0h\.s\[w12, 0:3\], {z0\.s-z3\.s} +[^:]+: c0848400 mov za0v\.s\[w12, 0:3\], {z0\.s-z3\.s} +[^:]+: c0840403 mov za3h\.s\[w12, 0:3\], {z0\.s-z3\.s} +[^:]+: c0848403 mov za3v\.s\[w12, 0:3\], {z0\.s-z3\.s} +[^:]+: c0846400 mov za0h\.s\[w15, 0:3\], {z0\.s-z3\.s} +[^:]+: c0840780 mov za0h\.s\[w12, 0:3\], {z28\.s-z31\.s} +[^:]+: c0842682 mov za2h\.s\[w13, 0:3\], {z20\.s-z23\.s} +[^:]+: c0c40400 mov za0h\.d\[w12, 0:3\], {z0\.d-z3\.d} +[^:]+: c0c48400 mov za0v\.d\[w12, 0:3\], {z0\.d-z3\.d} +[^:]+: c0c40407 mov za7h\.d\[w12, 0:3\], {z0\.d-z3\.d} +[^:]+: c0c48407 mov za7v\.d\[w12, 0:3\], {z0\.d-z3\.d} +[^:]+: c0c46400 mov za0h\.d\[w15, 0:3\], {z0\.d-z3\.d} +[^:]+: c0c40780 mov za0h\.d\[w12, 0:3\], {z28\.d-z31\.d} +[^:]+: c0c42705 mov za5h\.d\[w13, 0:3\], {z24\.d-z27\.d} +[^:]+: c0060800 mov {z0\.d-z1\.d}, za\.d\[w8, 0, vgx2\] +[^:]+: c0060800 mov {z0\.d-z1\.d}, za\.d\[w8, 0, vgx2\] +[^:]+: c0060800 mov {z0\.d-z1\.d}, za\.d\[w8, 0, vgx2\] +[^:]+: c0060800 mov {z0\.d-z1\.d}, za\.d\[w8, 0, vgx2\] +[^:]+: c006081e mov {z30\.d-z31\.d}, za\.d\[w8, 0, vgx2\] +[^:]+: c0066800 mov {z0\.d-z1\.d}, za\.d\[w11, 0, vgx2\] +[^:]+: c00608e0 mov {z0\.d-z1\.d}, za\.d\[w8, 7, vgx2\] +[^:]+: c0060c00 mov {z0\.d-z3\.d}, za\.d\[w8, 0, vgx4\] +[^:]+: c0060c00 mov {z0\.d-z3\.d}, za\.d\[w8, 0, vgx4\] +[^:]+: c0060c00 mov {z0\.d-z3\.d}, za\.d\[w8, 0, vgx4\] +[^:]+: c0060c00 mov {z0\.d-z3\.d}, za\.d\[w8, 0, vgx4\] +[^:]+: c0060c1c mov {z28\.d-z31\.d}, za\.d\[w8, 0, vgx4\] +[^:]+: c0066c00 mov {z0\.d-z3\.d}, za\.d\[w11, 0, vgx4\] +[^:]+: c0060ce0 mov {z0\.d-z3\.d}, za\.d\[w8, 7, vgx4\] +[^:]+: c0060000 mov {z0\.b-z1\.b}, za0h\.b\[w12, 0:1\] +[^:]+: c006001e mov {z30\.b-z31\.b}, za0h\.b\[w12, 0:1\] +[^:]+: c0068000 mov {z0\.b-z1\.b}, za0v\.b\[w12, 0:1\] +[^:]+: c0066000 mov {z0\.b-z1\.b}, za0h\.b\[w15, 0:1\] +[^:]+: c00600e0 mov {z0\.b-z1\.b}, za0h\.b\[w12, 14:15\] +[^:]+: c0064068 mov {z8\.b-z9\.b}, za0h\.b\[w14, 6:7\] +[^:]+: c0460000 mov {z0\.h-z1\.h}, za0h\.h\[w12, 0:1\] +[^:]+: c046001e mov {z30\.h-z31\.h}, za0h\.h\[w12, 0:1\] +[^:]+: c0468000 mov {z0\.h-z1\.h}, za0v\.h\[w12, 0:1\] +[^:]+: c0460080 mov {z0\.h-z1\.h}, za1h\.h\[w12, 0:1\] +[^:]+: c0468080 mov {z0\.h-z1\.h}, za1v\.h\[w12, 0:1\] +[^:]+: c0466000 mov {z0\.h-z1\.h}, za0h\.h\[w15, 0:1\] +[^:]+: c0460060 mov {z0\.h-z1\.h}, za0h\.h\[w12, 6:7\] +[^:]+: c046202a mov {z10\.h-z11\.h}, za0h\.h\[w13, 2:3\] +[^:]+: c0860000 mov {z0\.s-z1\.s}, za0h\.s\[w12, 0:1\] +[^:]+: c086001e mov {z30\.s-z31\.s}, za0h\.s\[w12, 0:1\] +[^:]+: c0868000 mov {z0\.s-z1\.s}, za0v\.s\[w12, 0:1\] +[^:]+: c08600c0 mov {z0\.s-z1\.s}, za3h\.s\[w12, 0:1\] +[^:]+: c08680c0 mov {z0\.s-z1\.s}, za3v\.s\[w12, 0:1\] +[^:]+: c0866000 mov {z0\.s-z1\.s}, za0h\.s\[w15, 0:1\] +[^:]+: c0860020 mov {z0\.s-z1\.s}, za0h\.s\[w12, 2:3\] +[^:]+: c0864092 mov {z18\.s-z19\.s}, za2h\.s\[w14, 0:1\] +[^:]+: c0c60000 mov {z0\.d-z1\.d}, za0h\.d\[w12, 0:1\] +[^:]+: c0c6001e mov {z30\.d-z31\.d}, za0h\.d\[w12, 0:1\] +[^:]+: c0c68000 mov {z0\.d-z1\.d}, za0v\.d\[w12, 0:1\] +[^:]+: c0c600e0 mov {z0\.d-z1\.d}, za7h\.d\[w12, 0:1\] +[^:]+: c0c680e0 mov {z0\.d-z1\.d}, za7v\.d\[w12, 0:1\] +[^:]+: c0c66000 mov {z0\.d-z1\.d}, za0h\.d\[w15, 0:1\] +[^:]+: c0c620d6 mov {z22\.d-z23\.d}, za6h\.d\[w13, 0:1\] +[^:]+: c0060400 mov {z0\.b-z3\.b}, za0h\.b\[w12, 0:3\] +[^:]+: c006041c mov {z28\.b-z31\.b}, za0h\.b\[w12, 0:3\] +[^:]+: c0068400 mov {z0\.b-z3\.b}, za0v\.b\[w12, 0:3\] +[^:]+: c0066400 mov {z0\.b-z3\.b}, za0h\.b\[w15, 0:3\] +[^:]+: c0060460 mov {z0\.b-z3\.b}, za0h\.b\[w12, 12:15\] +[^:]+: c006444c mov {z12\.b-z15\.b}, za0h\.b\[w14, 8:11\] +[^:]+: c0460400 mov {z0\.h-z3\.h}, za0h\.h\[w12, 0:3\] +[^:]+: c046041c mov {z28\.h-z31\.h}, za0h\.h\[w12, 0:3\] +[^:]+: c0468400 mov {z0\.h-z3\.h}, za0v\.h\[w12, 0:3\] +[^:]+: c0460440 mov {z0\.h-z3\.h}, za1h\.h\[w12, 0:3\] +[^:]+: c0468440 mov {z0\.h-z3\.h}, za1v\.h\[w12, 0:3\] +[^:]+: c0466400 mov {z0\.h-z3\.h}, za0h\.h\[w15, 0:3\] +[^:]+: c0460420 mov {z0\.h-z3\.h}, za0h\.h\[w12, 4:7\] +[^:]+: c0462430 mov {z16\.h-z19\.h}, za0h\.h\[w13, 4:7\] +[^:]+: c0860400 mov {z0\.s-z3\.s}, za0h\.s\[w12, 0:3\] +[^:]+: c086041c mov {z28\.s-z31\.s}, za0h\.s\[w12, 0:3\] +[^:]+: c0868400 mov {z0\.s-z3\.s}, za0v\.s\[w12, 0:3\] +[^:]+: c0860460 mov {z0\.s-z3\.s}, za3h\.s\[w12, 0:3\] +[^:]+: c0868460 mov {z0\.s-z3\.s}, za3v\.s\[w12, 0:3\] +[^:]+: c0866400 mov {z0\.s-z3\.s}, za0h\.s\[w15, 0:3\] +[^:]+: c0862454 mov {z20\.s-z23\.s}, za2h\.s\[w13, 0:3\] +[^:]+: c0c60400 mov {z0\.d-z3\.d}, za0h\.d\[w12, 0:3\] +[^:]+: c0c6041c mov {z28\.d-z31\.d}, za0h\.d\[w12, 0:3\] +[^:]+: c0c68400 mov {z0\.d-z3\.d}, za0v\.d\[w12, 0:3\] +[^:]+: c0c604e0 mov {z0\.d-z3\.d}, za7h\.d\[w12, 0:3\] +[^:]+: c0c684e0 mov {z0\.d-z3\.d}, za7v\.d\[w12, 0:3\] +[^:]+: c0c66400 mov {z0\.d-z3\.d}, za0h\.d\[w15, 0:3\] +[^:]+: c0c624b8 mov {z24\.d-z27\.d}, za5h\.d\[w13, 0:3\] +[^:]+: c0040800 mov za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d} +[^:]+: c0040800 mov za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d} +[^:]+: c0040800 mov za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d} +[^:]+: c0040800 mov za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d} +[^:]+: c0046800 mov za\.d\[w11, 0, vgx2\], {z0\.d-z1\.d} +[^:]+: c0040807 mov za\.d\[w8, 7, vgx2\], {z0\.d-z1\.d} +[^:]+: c0040bc0 mov za\.d\[w8, 0, vgx2\], {z30\.d-z31\.d} +[^:]+: c0042845 mov za\.d\[w9, 5, vgx2\], {z2\.d-z3\.d} +[^:]+: c0040c00 mov za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d} +[^:]+: c0040c00 mov za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d} +[^:]+: c0040c00 mov za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d} +[^:]+: c0040c00 mov za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d} +[^:]+: c0046c00 mov za\.d\[w11, 0, vgx4\], {z0\.d-z3\.d} +[^:]+: c0040c07 mov za\.d\[w8, 7, vgx4\], {z0\.d-z3\.d} +[^:]+: c0040f80 mov za\.d\[w8, 0, vgx4\], {z28\.d-z31\.d} +[^:]+: c0044e81 mov za\.d\[w10, 1, vgx4\], {z20\.d-z23\.d} +[^:]+: c0040000 mov za0h\.b\[w12, 0:1\], {z0\.b-z1\.b} +[^:]+: c0048000 mov za0v\.b\[w12, 0:1\], {z0\.b-z1\.b} +[^:]+: c0046000 mov za0h\.b\[w15, 0:1\], {z0\.b-z1\.b} +[^:]+: c0040007 mov za0h\.b\[w12, 14:15\], {z0\.b-z1\.b} +[^:]+: c00403c0 mov za0h\.b\[w12, 0:1\], {z30\.b-z31\.b} +[^:]+: c0044103 mov za0h\.b\[w14, 6:7\], {z8\.b-z9\.b} +[^:]+: c0440000 mov za0h\.h\[w12, 0:1\], {z0\.h-z1\.h} +[^:]+: c0448000 mov za0v\.h\[w12, 0:1\], {z0\.h-z1\.h} +[^:]+: c0440004 mov za1h\.h\[w12, 0:1\], {z0\.h-z1\.h} +[^:]+: c0448004 mov za1v\.h\[w12, 0:1\], {z0\.h-z1\.h} +[^:]+: c0446000 mov za0h\.h\[w15, 0:1\], {z0\.h-z1\.h} +[^:]+: c0440003 mov za0h\.h\[w12, 6:7\], {z0\.h-z1\.h} +[^:]+: c04403c0 mov za0h\.h\[w12, 0:1\], {z30\.h-z31\.h} +[^:]+: c0442141 mov za0h\.h\[w13, 2:3\], {z10\.h-z11\.h} +[^:]+: c0840000 mov za0h\.s\[w12, 0:1\], {z0\.s-z1\.s} +[^:]+: c0848000 mov za0v\.s\[w12, 0:1\], {z0\.s-z1\.s} +[^:]+: c0840006 mov za3h\.s\[w12, 0:1\], {z0\.s-z1\.s} +[^:]+: c0848006 mov za3v\.s\[w12, 0:1\], {z0\.s-z1\.s} +[^:]+: c0846000 mov za0h\.s\[w15, 0:1\], {z0\.s-z1\.s} +[^:]+: c0840001 mov za0h\.s\[w12, 2:3\], {z0\.s-z1\.s} +[^:]+: c08403c0 mov za0h\.s\[w12, 0:1\], {z30\.s-z31\.s} +[^:]+: c0844244 mov za2h\.s\[w14, 0:1\], {z18\.s-z19\.s} +[^:]+: c0c40000 mov za0h\.d\[w12, 0:1\], {z0\.d-z1\.d} +[^:]+: c0c48000 mov za0v\.d\[w12, 0:1\], {z0\.d-z1\.d} +[^:]+: c0c40007 mov za7h\.d\[w12, 0:1\], {z0\.d-z1\.d} +[^:]+: c0c48007 mov za7v\.d\[w12, 0:1\], {z0\.d-z1\.d} +[^:]+: c0c46000 mov za0h\.d\[w15, 0:1\], {z0\.d-z1\.d} +[^:]+: c0c403c0 mov za0h\.d\[w12, 0:1\], {z30\.d-z31\.d} +[^:]+: c0c422c6 mov za6h\.d\[w13, 0:1\], {z22\.d-z23\.d} +[^:]+: c0040400 mov za0h\.b\[w12, 0:3\], {z0\.b-z3\.b} +[^:]+: c0048400 mov za0v\.b\[w12, 0:3\], {z0\.b-z3\.b} +[^:]+: c0046400 mov za0h\.b\[w15, 0:3\], {z0\.b-z3\.b} +[^:]+: c0040403 mov za0h\.b\[w12, 12:15\], {z0\.b-z3\.b} +[^:]+: c0040780 mov za0h\.b\[w12, 0:3\], {z28\.b-z31\.b} +[^:]+: c0044582 mov za0h\.b\[w14, 8:11\], {z12\.b-z15\.b} +[^:]+: c0440400 mov za0h\.h\[w12, 0:3\], {z0\.h-z3\.h} +[^:]+: c0448400 mov za0v\.h\[w12, 0:3\], {z0\.h-z3\.h} +[^:]+: c0440402 mov za1h\.h\[w12, 0:3\], {z0\.h-z3\.h} +[^:]+: c0448402 mov za1v\.h\[w12, 0:3\], {z0\.h-z3\.h} +[^:]+: c0446400 mov za0h\.h\[w15, 0:3\], {z0\.h-z3\.h} +[^:]+: c0440401 mov za0h\.h\[w12, 4:7\], {z0\.h-z3\.h} +[^:]+: c0440780 mov za0h\.h\[w12, 0:3\], {z28\.h-z31\.h} +[^:]+: c0442601 mov za0h\.h\[w13, 4:7\], {z16\.h-z19\.h} +[^:]+: c0840400 mov za0h\.s\[w12, 0:3\], {z0\.s-z3\.s} +[^:]+: c0848400 mov za0v\.s\[w12, 0:3\], {z0\.s-z3\.s} +[^:]+: c0840403 mov za3h\.s\[w12, 0:3\], {z0\.s-z3\.s} +[^:]+: c0848403 mov za3v\.s\[w12, 0:3\], {z0\.s-z3\.s} +[^:]+: c0846400 mov za0h\.s\[w15, 0:3\], {z0\.s-z3\.s} +[^:]+: c0840780 mov za0h\.s\[w12, 0:3\], {z28\.s-z31\.s} +[^:]+: c0842682 mov za2h\.s\[w13, 0:3\], {z20\.s-z23\.s} +[^:]+: c0c40400 mov za0h\.d\[w12, 0:3\], {z0\.d-z3\.d} +[^:]+: c0c48400 mov za0v\.d\[w12, 0:3\], {z0\.d-z3\.d} +[^:]+: c0c40407 mov za7h\.d\[w12, 0:3\], {z0\.d-z3\.d} +[^:]+: c0c48407 mov za7v\.d\[w12, 0:3\], {z0\.d-z3\.d} +[^:]+: c0c46400 mov za0h\.d\[w15, 0:3\], {z0\.d-z3\.d} +[^:]+: c0c40780 mov za0h\.d\[w12, 0:3\], {z28\.d-z31\.d} +[^:]+: c0c42705 mov za5h\.d\[w13, 0:3\], {z24\.d-z27\.d} diff --git a/gas/testsuite/gas/aarch64/sme2-1.s b/gas/testsuite/gas/aarch64/sme2-1.s new file mode 100644 index 00000000000..222f8e06b96 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-1.s @@ -0,0 +1,338 @@ + mov { z0.b - z1.b }, za.b[w8, 0] + mov { z0.h - z1.h }, za.h[w8, 0] + mov { z0.s - z1.s }, za.s[w8, 0] + mov { z0.d - z1.d }, za.d[w8, 0] + mov { z30.d - z31.d }, za.d[w8, 0] + mov { z0.d - z1.d }, za.d[w11, 0] + mov { z0.d - z1.d }, za.d[w8, 7] + + mov { z0.b - z3.b }, za.b[w8, 0] + mov { z0.h - z3.h }, za.h[w8, 0] + mov { z0.s - z3.s }, za.s[w8, 0] + mov { z0.d - z3.d }, za.d[w8, 0] + mov { z28.d - z31.d }, za.d[w8, 0] + mov { z0.d - z3.d }, za.d[w11, 0] + mov { z0.d - z3.d }, za.d[w8, 7] + + mov { z0.b - z1.b }, za0h.b[w12, 0:1] + mov { z30.b - z31.b }, za0h.b[w12, 0:1] + mov { z0.b - z1.b }, za0v.b[w12, 0:1] + mov { z0.b - z1.b }, za0h.b[w15, 0:1] + mov { z0.b - z1.b }, za0h.b[w12, 14:15] + mov { z8.b - z9.b }, za0h.b[w14, 6:7] + + mov { z0.h - z1.h }, za0h.h[w12, 0:1] + mov { z30.h - z31.h }, za0h.h[w12, 0:1] + mov { z0.h - z1.h }, za0v.h[w12, 0:1] + mov { z0.h - z1.h }, za1h.h[w12, 0:1] + mov { z0.h - z1.h }, za1v.h[w12, 0:1] + mov { z0.h - z1.h }, za0h.h[w15, 0:1] + mov { z0.h - z1.h }, za0h.h[w12, 6:7] + mov { z10.h - z11.h }, za0h.h[w13, 2:3] + + mov { z0.s - z1.s }, za0h.s[w12, 0:1] + mov { z30.s - z31.s }, za0h.s[w12, 0:1] + mov { z0.s - z1.s }, za0v.s[w12, 0:1] + mov { z0.s - z1.s }, za3h.s[w12, 0:1] + mov { z0.s - z1.s }, za3v.s[w12, 0:1] + mov { z0.s - z1.s }, za0h.s[w15, 0:1] + mov { z0.s - z1.s }, za0h.s[w12, 2:3] + mov { z18.s - z19.s }, za2h.s[w14, 0:1] + + mov { z0.d - z1.d }, za0h.d[w12, 0:1] + mov { z30.d - z31.d }, za0h.d[w12, 0:1] + mov { z0.d - z1.d }, za0v.d[w12, 0:1] + mov { z0.d - z1.d }, za7h.d[w12, 0:1] + mov { z0.d - z1.d }, za7v.d[w12, 0:1] + mov { z0.d - z1.d }, za0h.d[w15, 0:1] + mov { z22.d - z23.d }, za6h.d[w13, 0:1] + + mov { z0.b - z3.b }, za0h.b[w12, 0:3] + mov { z28.b - z31.b }, za0h.b[w12, 0:3] + mov { z0.b - z3.b }, za0v.b[w12, 0:3] + mov { z0.b - z3.b }, za0h.b[w15, 0:3] + mov { z0.b - z3.b }, za0h.b[w12, 12:15] + mov { z12.b - z15.b }, za0h.b[w14, 8:11] + + mov { z0.h - z3.h }, za0h.h[w12, 0:3] + mov { z28.h - z31.h }, za0h.h[w12, 0:3] + mov { z0.h - z3.h }, za0v.h[w12, 0:3] + mov { z0.h - z3.h }, za1h.h[w12, 0:3] + mov { z0.h - z3.h }, za1v.h[w12, 0:3] + mov { z0.h - z3.h }, za0h.h[w15, 0:3] + mov { z0.h - z3.h }, za0h.h[w12, 4:7] + mov { z16.h - z19.h }, za0h.h[w13, 4:7] + + mov { z0.s - z3.s }, za0h.s[w12, 0:3] + mov { z28.s - z31.s }, za0h.s[w12, 0:3] + mov { z0.s - z3.s }, za0v.s[w12, 0:3] + mov { z0.s - z3.s }, za3h.s[w12, 0:3] + mov { z0.s - z3.s }, za3v.s[w12, 0:3] + mov { z0.s - z3.s }, za0h.s[w15, 0:3] + mov { z20.s - z23.s }, za2h.s[w13, 0:3] + + mov { z0.d - z3.d }, za0h.d[w12, 0:3] + mov { z28.d - z31.d }, za0h.d[w12, 0:3] + mov { z0.d - z3.d }, za0v.d[w12, 0:3] + mov { z0.d - z3.d }, za7h.d[w12, 0:3] + mov { z0.d - z3.d }, za7v.d[w12, 0:3] + mov { z0.d - z3.d }, za0h.d[w15, 0:3] + mov { z24.d - z27.d }, za5h.d[w13, 0:3] + + // Invalid MOVAs + .inst 0xc0060480 + .inst 0xc00604e0 + .inst 0xc0460480 + .inst 0xc04604e0 + .inst 0xc0860480 + .inst 0xc08604e0 + // Valid MOVAs + .inst 0xc0c60480 + .inst 0xc0c604e0 + + mov za.b[w8, 0], { z0.b - z1.b } + mov za.h[w8, 0], { z0.h - z1.h } + mov za.s[w8, 0], { z0.s - z1.s } + mov za.d[w8, 0], { z0.d - z1.d } + mov za.d[w11, 0], { z0.d - z1.d } + mov za.d[w8, 7], { z0.d - z1.d } + mov za.d[w8, 0], { z30.d - z31.d } + mov za.d[w9, 5], { z2.d - z3.d } + + mov za.b[w8, 0], { z0.b - z3.b } + mov za.h[w8, 0], { z0.h - z3.h } + mov za.s[w8, 0], { z0.s - z3.s } + mov za.d[w8, 0], { z0.d - z3.d } + mov za.d[w11, 0], { z0.d - z3.d } + mov za.d[w8, 7], { z0.d - z3.d } + mov za.d[w8, 0], { z28.d - z31.d } + mov za.d[w10, 1], { z20.d - z23.d } + + mov za0h.b[w12, 0:1], { z0.b - z1.b } + mov za0v.b[w12, 0:1], { z0.b - z1.b } + mov za0h.b[w15, 0:1], { z0.b - z1.b } + mov za0h.b[w12, 14:15], { z0.b - z1.b } + mov za0h.b[w12, 0:1], { z30.b - z31.b } + mov za0h.b[w14, 6:7], { z8.b - z9.b } + + mov za0h.h[w12, 0:1], { z0.h - z1.h } + mov za0v.h[w12, 0:1], { z0.h - z1.h } + mov za1h.h[w12, 0:1], { z0.h - z1.h } + mov za1v.h[w12, 0:1], { z0.h - z1.h } + mov za0h.h[w15, 0:1], { z0.h - z1.h } + mov za0h.h[w12, 6:7], { z0.h - z1.h } + mov za0h.h[w12, 0:1], { z30.h - z31.h } + mov za0h.h[w13, 2:3], { z10.h - z11.h } + + mov za0h.s[w12, 0:1], { z0.s - z1.s } + mov za0v.s[w12, 0:1], { z0.s - z1.s } + mov za3h.s[w12, 0:1], { z0.s - z1.s } + mov za3v.s[w12, 0:1], { z0.s - z1.s } + mov za0h.s[w15, 0:1], { z0.s - z1.s } + mov za0h.s[w12, 2:3], { z0.s - z1.s } + mov za0h.s[w12, 0:1], { z30.s - z31.s } + mov za2h.s[w14, 0:1], { z18.s - z19.s } + + mov za0h.d[w12, 0:1], { z0.d - z1.d } + mov za0v.d[w12, 0:1], { z0.d - z1.d } + mov za7h.d[w12, 0:1], { z0.d - z1.d } + mov za7v.d[w12, 0:1], { z0.d - z1.d } + mov za0h.d[w15, 0:1], { z0.d - z1.d } + mov za0h.d[w12, 0:1], { z30.d - z31.d } + mov za6h.d[w13, 0:1], { z22.d - z23.d } + + mov za0h.b[w12, 0:3], { z0.b - z3.b } + mov za0v.b[w12, 0:3], { z0.b - z3.b } + mov za0h.b[w15, 0:3], { z0.b - z3.b } + mov za0h.b[w12, 12:15], { z0.b - z3.b } + mov za0h.b[w12, 0:3], { z28.b - z31.b } + mov za0h.b[w14, 8:11], { z12.b - z15.b } + + mov za0h.h[w12, 0:3], { z0.h - z3.h } + mov za0v.h[w12, 0:3], { z0.h - z3.h } + mov za1h.h[w12, 0:3], { z0.h - z3.h } + mov za1v.h[w12, 0:3], { z0.h - z3.h } + mov za0h.h[w15, 0:3], { z0.h - z3.h } + mov za0h.h[w12, 4:7], { z0.h - z3.h } + mov za0h.h[w12, 0:3], { z28.h - z31.h } + mov za0h.h[w13, 4:7], { z16.h - z19.h } + + mov za0h.s[w12, 0:3], { z0.s - z3.s } + mov za0v.s[w12, 0:3], { z0.s - z3.s } + mov za3h.s[w12, 0:3], { z0.s - z3.s } + mov za3v.s[w12, 0:3], { z0.s - z3.s } + mov za0h.s[w15, 0:3], { z0.s - z3.s } + mov za0h.s[w12, 0:3], { z28.s - z31.s } + mov za2h.s[w13, 0:3], { z20.s - z23.s } + + mov za0h.d[w12, 0:3], { z0.d - z3.d } + mov za0v.d[w12, 0:3], { z0.d - z3.d } + mov za7h.d[w12, 0:3], { z0.d - z3.d } + mov za7v.d[w12, 0:3], { z0.d - z3.d } + mov za0h.d[w15, 0:3], { z0.d - z3.d } + mov za0h.d[w12, 0:3], { z28.d - z31.d } + mov za5h.d[w13, 0:3], { z24.d - z27.d } + + mova { z0.b - z1.b }, za.b[w8, 0] + mova { z0.h - z1.h }, za.h[w8, 0] + mova { z0.s - z1.s }, za.s[w8, 0] + mova { z0.d - z1.d }, za.d[w8, 0] + mova { z30.d - z31.d }, za.d[w8, 0] + mova { z0.d - z1.d }, za.d[w11, 0] + mova { z0.d - z1.d }, za.d[w8, 7] + + mova { z0.b - z3.b }, za.b[w8, 0] + mova { z0.h - z3.h }, za.h[w8, 0] + mova { z0.s - z3.s }, za.s[w8, 0] + mova { z0.d - z3.d }, za.d[w8, 0] + mova { z28.d - z31.d }, za.d[w8, 0] + mova { z0.d - z3.d }, za.d[w11, 0] + mova { z0.d - z3.d }, za.d[w8, 7] + + mova { z0.b - z1.b }, za0h.b[w12, 0:1] + mova { z30.b - z31.b }, za0h.b[w12, 0:1] + mova { z0.b - z1.b }, za0v.b[w12, 0:1] + mova { z0.b - z1.b }, za0h.b[w15, 0:1] + mova { z0.b - z1.b }, za0h.b[w12, 14:15] + mova { z8.b - z9.b }, za0h.b[w14, 6:7] + + mova { z0.h - z1.h }, za0h.h[w12, 0:1] + mova { z30.h - z31.h }, za0h.h[w12, 0:1] + mova { z0.h - z1.h }, za0v.h[w12, 0:1] + mova { z0.h - z1.h }, za1h.h[w12, 0:1] + mova { z0.h - z1.h }, za1v.h[w12, 0:1] + mova { z0.h - z1.h }, za0h.h[w15, 0:1] + mova { z0.h - z1.h }, za0h.h[w12, 6:7] + mova { z10.h - z11.h }, za0h.h[w13, 2:3] + + mova { z0.s - z1.s }, za0h.s[w12, 0:1] + mova { z30.s - z31.s }, za0h.s[w12, 0:1] + mova { z0.s - z1.s }, za0v.s[w12, 0:1] + mova { z0.s - z1.s }, za3h.s[w12, 0:1] + mova { z0.s - z1.s }, za3v.s[w12, 0:1] + mova { z0.s - z1.s }, za0h.s[w15, 0:1] + mova { z0.s - z1.s }, za0h.s[w12, 2:3] + mova { z18.s - z19.s }, za2h.s[w14, 0:1] + + mova { z0.d - z1.d }, za0h.d[w12, 0:1] + mova { z30.d - z31.d }, za0h.d[w12, 0:1] + mova { z0.d - z1.d }, za0v.d[w12, 0:1] + mova { z0.d - z1.d }, za7h.d[w12, 0:1] + mova { z0.d - z1.d }, za7v.d[w12, 0:1] + mova { z0.d - z1.d }, za0h.d[w15, 0:1] + mova { z22.d - z23.d }, za6h.d[w13, 0:1] + + mova { z0.b - z3.b }, za0h.b[w12, 0:3] + mova { z28.b - z31.b }, za0h.b[w12, 0:3] + mova { z0.b - z3.b }, za0v.b[w12, 0:3] + mova { z0.b - z3.b }, za0h.b[w15, 0:3] + mova { z0.b - z3.b }, za0h.b[w12, 12:15] + mova { z12.b - z15.b }, za0h.b[w14, 8:11] + + mova { z0.h - z3.h }, za0h.h[w12, 0:3] + mova { z28.h - z31.h }, za0h.h[w12, 0:3] + mova { z0.h - z3.h }, za0v.h[w12, 0:3] + mova { z0.h - z3.h }, za1h.h[w12, 0:3] + mova { z0.h - z3.h }, za1v.h[w12, 0:3] + mova { z0.h - z3.h }, za0h.h[w15, 0:3] + mova { z0.h - z3.h }, za0h.h[w12, 4:7] + mova { z16.h - z19.h }, za0h.h[w13, 4:7] + + mova { z0.s - z3.s }, za0h.s[w12, 0:3] + mova { z28.s - z31.s }, za0h.s[w12, 0:3] + mova { z0.s - z3.s }, za0v.s[w12, 0:3] + mova { z0.s - z3.s }, za3h.s[w12, 0:3] + mova { z0.s - z3.s }, za3v.s[w12, 0:3] + mova { z0.s - z3.s }, za0h.s[w15, 0:3] + mova { z20.s - z23.s }, za2h.s[w13, 0:3] + + mova { z0.d - z3.d }, za0h.d[w12, 0:3] + mova { z28.d - z31.d }, za0h.d[w12, 0:3] + mova { z0.d - z3.d }, za0v.d[w12, 0:3] + mova { z0.d - z3.d }, za7h.d[w12, 0:3] + mova { z0.d - z3.d }, za7v.d[w12, 0:3] + mova { z0.d - z3.d }, za0h.d[w15, 0:3] + mova { z24.d - z27.d }, za5h.d[w13, 0:3] + + mova za.b[w8, 0], { z0.b - z1.b } + mova za.h[w8, 0], { z0.h - z1.h } + mova za.s[w8, 0], { z0.s - z1.s } + mova za.d[w8, 0], { z0.d - z1.d } + mova za.d[w11, 0], { z0.d - z1.d } + mova za.d[w8, 7], { z0.d - z1.d } + mova za.d[w8, 0], { z30.d - z31.d } + mova za.d[w9, 5], { z2.d - z3.d } + + mova za.b[w8, 0], { z0.b - z3.b } + mova za.h[w8, 0], { z0.h - z3.h } + mova za.s[w8, 0], { z0.s - z3.s } + mova za.d[w8, 0], { z0.d - z3.d } + mova za.d[w11, 0], { z0.d - z3.d } + mova za.d[w8, 7], { z0.d - z3.d } + mova za.d[w8, 0], { z28.d - z31.d } + mova za.d[w10, 1], { z20.d - z23.d } + + mova za0h.b[w12, 0:1], { z0.b - z1.b } + mova za0v.b[w12, 0:1], { z0.b - z1.b } + mova za0h.b[w15, 0:1], { z0.b - z1.b } + mova za0h.b[w12, 14:15], { z0.b - z1.b } + mova za0h.b[w12, 0:1], { z30.b - z31.b } + mova za0h.b[w14, 6:7], { z8.b - z9.b } + + mova za0h.h[w12, 0:1], { z0.h - z1.h } + mova za0v.h[w12, 0:1], { z0.h - z1.h } + mova za1h.h[w12, 0:1], { z0.h - z1.h } + mova za1v.h[w12, 0:1], { z0.h - z1.h } + mova za0h.h[w15, 0:1], { z0.h - z1.h } + mova za0h.h[w12, 6:7], { z0.h - z1.h } + mova za0h.h[w12, 0:1], { z30.h - z31.h } + mova za0h.h[w13, 2:3], { z10.h - z11.h } + + mova za0h.s[w12, 0:1], { z0.s - z1.s } + mova za0v.s[w12, 0:1], { z0.s - z1.s } + mova za3h.s[w12, 0:1], { z0.s - z1.s } + mova za3v.s[w12, 0:1], { z0.s - z1.s } + mova za0h.s[w15, 0:1], { z0.s - z1.s } + mova za0h.s[w12, 2:3], { z0.s - z1.s } + mova za0h.s[w12, 0:1], { z30.s - z31.s } + mova za2h.s[w14, 0:1], { z18.s - z19.s } + + mova za0h.d[w12, 0:1], { z0.d - z1.d } + mova za0v.d[w12, 0:1], { z0.d - z1.d } + mova za7h.d[w12, 0:1], { z0.d - z1.d } + mova za7v.d[w12, 0:1], { z0.d - z1.d } + mova za0h.d[w15, 0:1], { z0.d - z1.d } + mova za0h.d[w12, 0:1], { z30.d - z31.d } + mova za6h.d[w13, 0:1], { z22.d - z23.d } + + mova za0h.b[w12, 0:3], { z0.b - z3.b } + mova za0v.b[w12, 0:3], { z0.b - z3.b } + mova za0h.b[w15, 0:3], { z0.b - z3.b } + mova za0h.b[w12, 12:15], { z0.b - z3.b } + mova za0h.b[w12, 0:3], { z28.b - z31.b } + mova za0h.b[w14, 8:11], { z12.b - z15.b } + + mova za0h.h[w12, 0:3], { z0.h - z3.h } + mova za0v.h[w12, 0:3], { z0.h - z3.h } + mova za1h.h[w12, 0:3], { z0.h - z3.h } + mova za1v.h[w12, 0:3], { z0.h - z3.h } + mova za0h.h[w15, 0:3], { z0.h - z3.h } + mova za0h.h[w12, 4:7], { z0.h - z3.h } + mova za0h.h[w12, 0:3], { z28.h - z31.h } + mova za0h.h[w13, 4:7], { z16.h - z19.h } + + mova za0h.s[w12, 0:3], { z0.s - z3.s } + mova za0v.s[w12, 0:3], { z0.s - z3.s } + mova za3h.s[w12, 0:3], { z0.s - z3.s } + mova za3v.s[w12, 0:3], { z0.s - z3.s } + mova za0h.s[w15, 0:3], { z0.s - z3.s } + mova za0h.s[w12, 0:3], { z28.s - z31.s } + mova za2h.s[w13, 0:3], { z20.s - z23.s } + + mova za0h.d[w12, 0:3], { z0.d - z3.d } + mova za0v.d[w12, 0:3], { z0.d - z3.d } + mova za7h.d[w12, 0:3], { z0.d - z3.d } + mova za7v.d[w12, 0:3], { z0.d - z3.d } + mova za0h.d[w15, 0:3], { z0.d - z3.d } + mova za0h.d[w12, 0:3], { z28.d - z31.d } + mova za5h.d[w13, 0:3], { z24.d - z27.d } diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 34893584065..4d2e054c7f8 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -485,13 +485,21 @@ enum aarch64_opnd AARCH64_OPND_SVE_ZnxN, /* SVE vector register list in Zn. */ AARCH64_OPND_SVE_Zt, /* SVE vector register in Zt. */ AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */ + AARCH64_OPND_SME_Zdnx2, /* SVE vector register list from [4:1]*2. */ + AARCH64_OPND_SME_Zdnx4, /* SVE vector register list from [4:2]*4. */ + AARCH64_OPND_SME_Znx2, /* SVE vector register list from [9:6]*2. */ + AARCH64_OPND_SME_Znx4, /* SVE vector register list from [9:7]*4. */ AARCH64_OPND_SME_ZAda_2b, /* SME .S, 2-bits. */ AARCH64_OPND_SME_ZAda_3b, /* SME .D, 3-bits. */ AARCH64_OPND_SME_ZA_HV_idx_src, /* SME source ZA tile vector. */ + AARCH64_OPND_SME_ZA_HV_idx_srcxN, /* SME N source ZA tile vectors. */ AARCH64_OPND_SME_ZA_HV_idx_dest, /* SME destination ZA tile vector. */ + AARCH64_OPND_SME_ZA_HV_idx_destxN, /* SME N dest ZA tile vectors. */ AARCH64_OPND_SME_Pm, /* SME scalable predicate register, bits [15:13]. */ AARCH64_OPND_SME_list_of_64bit_tiles, /* SME list of ZA tiles. */ AARCH64_OPND_SME_ZA_HV_idx_ldstr, /* SME destination ZA tile vector. */ + AARCH64_OPND_SME_ZA_array_off3_0, /* SME ZA[{, #}]. */ + AARCH64_OPND_SME_ZA_array_off3_5, /* SME ZA[{, #}]. */ AARCH64_OPND_SME_ZA_array_off4, /* SME ZA[{, #}]. */ AARCH64_OPND_SME_ADDR_RI_U4xVL, /* SME [{, #, MUL VL}]. */ AARCH64_OPND_SME_SM_ZA, /* SME {SM | ZA}. */ @@ -669,9 +677,11 @@ enum aarch64_insn_class sme_mov, sme_ldr, sme_psel, + sme_size_22, sme_str, sme_start, sme_stop, + sme2_mov, sve_cpy, sve_index, sve_limm, diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c index 332b3f77846..daba55b4c62 100644 --- a/opcodes/aarch64-asm-2.c +++ b/opcodes/aarch64-asm-2.c @@ -667,9 +667,9 @@ aarch64_insert_operand (const aarch64_operand *self, case 203: case 209: case 212: - case 214: - case 215: case 218: + case 219: + case 224: return aarch64_ins_regno (self, info, code, inst, errors); case 15: return aarch64_ins_reg_extended (self, info, code, inst, errors); @@ -681,7 +681,7 @@ aarch64_insert_operand (const aarch64_operand *self, case 33: case 34: case 35: - case 226: + case 234: return aarch64_ins_reglane (self, info, code, inst, errors); case 36: return aarch64_ins_reglist (self, info, code, inst, errors); @@ -726,10 +726,10 @@ aarch64_insert_operand (const aarch64_operand *self, case 192: case 193: case 194: - case 219: case 225: - case 230: - case 231: + case 233: + case 238: + case 239: return aarch64_ins_imm (self, info, code, inst, errors); case 44: case 45: @@ -889,21 +889,31 @@ aarch64_insert_operand (const aarch64_operand *self, case 211: case 213: return aarch64_ins_sve_reglist (self, info, code, inst, errors); + case 214: + case 215: case 216: case 217: + return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors); case 220: + case 222: + case 226: return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors); case 221: - return aarch64_ins_sme_za_array (self, info, code, inst, errors); - case 222: - return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors); case 223: - return aarch64_ins_sme_sm_za (self, info, code, inst, errors); - case 224: - return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors); + return aarch64_ins_sme_za_hv_tiles_range (self, info, code, inst, errors); case 227: case 228: case 229: + return aarch64_ins_sme_za_array (self, info, code, inst, errors); + case 230: + return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors); + case 231: + return aarch64_ins_sme_sm_za (self, info, code, inst, errors); + case 232: + return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors); + case 235: + case 236: + case 237: return aarch64_ins_x0_to_x30 (self, info, code, inst, errors); default: assert (0); abort (); } diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c index 10b70824b05..516aa8ecb81 100644 --- a/opcodes/aarch64-asm.c +++ b/opcodes/aarch64-asm.c @@ -1167,6 +1167,19 @@ aarch64_ins_sve_aimm (const aarch64_operand *self, return true; } +bool +aarch64_ins_sve_aligned_reglist (const aarch64_operand *self, + const aarch64_opnd_info *info, + aarch64_insn *code, + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) +{ + unsigned int num_regs = get_operand_specific_data (self); + unsigned int val = info->reglist.first_regno; + insert_field (self->fields[0], code, val / num_regs, 0); + return true; +} + /* Encode an SVE CPY/DUP immediate. */ bool aarch64_ins_sve_asimm (const aarch64_operand *self, @@ -1384,6 +1397,35 @@ aarch64_ins_sme_za_hv_tiles (const aarch64_operand *self, return true; } +bool +aarch64_ins_sme_za_hv_tiles_range (const aarch64_operand *self, + const aarch64_opnd_info *info, + aarch64_insn *code, + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors + ATTRIBUTE_UNUSED) +{ + int ebytes = aarch64_get_qualifier_esize (info->qualifier); + int range_size = get_opcode_dependent_value (inst->opcode); + int fld_v = info->indexed_za.v; + int fld_rv = info->indexed_za.index.regno - 12; + int imm = info->indexed_za.index.imm; + int max_value = 16 / range_size / ebytes; + + if (max_value == 0) + max_value = 1; + + assert (imm % range_size == 0 && (imm / range_size) < max_value); + int fld_zan_imm = (info->indexed_za.regno * max_value) | (imm / range_size); + assert (fld_zan_imm < (range_size == 4 && ebytes < 8 ? 4 : 8)); + + insert_field (self->fields[0], code, fld_v, 0); + insert_field (self->fields[1], code, fld_rv, 0); + insert_field (self->fields[2], code, fld_zan_imm, 0); + + return true; +} + /* Encode in SME instruction ZERO list of up to eight 64-bit element tile names separated by commas, encoded in the "imm8" field. @@ -1410,7 +1452,7 @@ aarch64_ins_sme_za_array (const aarch64_operand *self, const aarch64_inst *inst ATTRIBUTE_UNUSED, aarch64_operand_error *errors ATTRIBUTE_UNUSED) { - int regno = info->indexed_za.index.regno - 12; + int regno = info->indexed_za.index.regno & 3; int imm = info->indexed_za.index.imm; insert_field (self->fields[0], code, regno, 0); insert_field (self->fields[1], code, imm, 0); @@ -1858,6 +1900,11 @@ aarch64_encode_variant_using_iclass (struct aarch64_inst *inst) /* The variant is encoded as part of the immediate. */ break; + case sme_size_22: + insert_field (FLD_SME_size_22, &inst->value, + aarch64_get_variant (inst), 0); + break; + case sve_cpy: insert_fields (&inst->value, aarch64_get_variant (inst), 0, 2, FLD_SVE_M_14, FLD_size); @@ -1873,6 +1920,7 @@ aarch64_encode_variant_using_iclass (struct aarch64_inst *inst) break; case sve_limm: + case sme2_mov: /* For sve_limm, the .B, .H, and .S forms are just a convenience and depend on the immediate. They don't have a separate encoding. */ diff --git a/opcodes/aarch64-asm.h b/opcodes/aarch64-asm.h index 56f53545531..eb881707b65 100644 --- a/opcodes/aarch64-asm.h +++ b/opcodes/aarch64-asm.h @@ -87,6 +87,7 @@ AARCH64_DECL_OPD_INSERTER (ins_sve_addr_zz_lsl); AARCH64_DECL_OPD_INSERTER (ins_sve_addr_zz_sxtw); AARCH64_DECL_OPD_INSERTER (ins_sve_addr_zz_uxtw); AARCH64_DECL_OPD_INSERTER (ins_sve_aimm); +AARCH64_DECL_OPD_INSERTER (ins_sve_aligned_reglist); AARCH64_DECL_OPD_INSERTER (ins_sve_asimm); AARCH64_DECL_OPD_INSERTER (ins_sve_float_half_one); AARCH64_DECL_OPD_INSERTER (ins_sve_float_half_two); @@ -99,6 +100,7 @@ AARCH64_DECL_OPD_INSERTER (ins_sve_scale); AARCH64_DECL_OPD_INSERTER (ins_sve_shlimm); AARCH64_DECL_OPD_INSERTER (ins_sve_shrimm); AARCH64_DECL_OPD_INSERTER (ins_sme_za_hv_tiles); +AARCH64_DECL_OPD_INSERTER (ins_sme_za_hv_tiles_range); AARCH64_DECL_OPD_INSERTER (ins_sme_za_list); AARCH64_DECL_OPD_INSERTER (ins_sme_za_array); AARCH64_DECL_OPD_INSERTER (ins_sme_addr_ri_u4xvl); diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c index 53fc8122ac8..3e7ca5cc373 100644 --- a/opcodes/aarch64-dis-2.c +++ b/opcodes/aarch64-dis-2.c @@ -96,74 +96,162 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 17) & 0x1) == 0) { - if (((word >> 19) & 0x1) == 0) + if (((word >> 18) & 0x1) == 0) { - if (((word >> 20) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000000xx000x0xxxxxxxxxxxxxxxxx - mov. */ - return 2389; - } - else + if (((word >> 19) & 0x1) == 0) { - if (((word >> 16) & 0x1) == 0) + if (((word >> 20) & 0x1) == 0) { - if (((word >> 22) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000000x0010x00xxxxxxxxxxxxxxxx - addha. */ - return 2357; - } - else - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000000x1010x00xxxxxxxxxxxxxxxx - addha. */ - return 2358; - } + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000000xx00000xxxxxxxxxxxxxxxxx + mov. */ + return 2389; } else { - if (((word >> 22) & 0x1) == 0) + if (((word >> 16) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000000x0010x01xxxxxxxxxxxxxxxx - addva. */ - return 2361; + if (((word >> 22) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000000x0010000xxxxxxxxxxxxxxxx + addha. */ + return 2357; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000000x1010000xxxxxxxxxxxxxxxx + addha. */ + return 2358; + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000000x1010x01xxxxxxxxxxxxxxxx - addva. */ - return 2362; + if (((word >> 22) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000000x0010001xxxxxxxxxxxxxxxx + addva. */ + return 2361; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000000x1010001xxxxxxxxxxxxxxxx + addva. */ + return 2362; + } } } } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000000xx0x100xxxxxxxxxxxxxxxxx + zero. */ + return 2392; + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000000xx0x1x0xxxxxxxxxxxxxxxxx - zero. */ - return 2392; + if (((word >> 10) & 0x1) == 0) + { + if (((word >> 11) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000000xx0xx10xxxxx00xxxxxxxxxx + mov. */ + return 2426; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000000xx0xx10xxxxx10xxxxxxxxxx + mov. */ + return 2424; + } + } + else + { + if (((word >> 11) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000000xx0xx10xxxxx01xxxxxxxxxx + mov. */ + return 2427; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000000xx0xx10xxxxx11xxxxxxxxxx + mov. */ + return 2425; + } + } } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000000xx0xxx1xxxxxxxxxxxxxxxxx - mov. */ - return 2388; + if (((word >> 18) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000000xx0xx01xxxxxxxxxxxxxxxxx + mov. */ + return 2388; + } + else + { + if (((word >> 10) & 0x1) == 0) + { + if (((word >> 11) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000000xx0xx11xxxxx00xxxxxxxxxx + mov. */ + return 2422; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000000xx0xx11xxxxx10xxxxxxxxxx + mov. */ + return 2420; + } + } + else + { + if (((word >> 11) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000000xx0xx11xxxxx01xxxxxxxxxx + mov. */ + return 2423; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000000xx0xx11xxxxx11xxxxxxxxxx + mov. */ + return 2421; + } + } + } } } } @@ -2896,7 +2984,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 00011001000xxxxxxxxx00xxxxxxxxxx stlurb. */ - return 2460; + return 2476; } else { @@ -2904,7 +2992,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 10011001000xxxxxxxxx00xxxxxxxxxx stlur. */ - return 2468; + return 2484; } } else @@ -2915,7 +3003,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 01011001000xxxxxxxxx00xxxxxxxxxx stlurh. */ - return 2464; + return 2480; } else { @@ -2923,7 +3011,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 11011001000xxxxxxxxx00xxxxxxxxxx stlur. */ - return 2471; + return 2487; } } } @@ -2961,7 +3049,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0000x1xxxxxxxxxx cpyfp. */ - return 2520; + return 2536; } else { @@ -2969,7 +3057,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1000x1xxxxxxxxxx cpyfprn. */ - return 2526; + return 2542; } } else @@ -2980,7 +3068,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0100x1xxxxxxxxxx cpyfpwn. */ - return 2523; + return 2539; } else { @@ -2988,7 +3076,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1100x1xxxxxxxxxx cpyfpn. */ - return 2529; + return 2545; } } } @@ -3002,7 +3090,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0010x1xxxxxxxxxx cpyfprt. */ - return 2544; + return 2560; } else { @@ -3010,7 +3098,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1010x1xxxxxxxxxx cpyfprtrn. */ - return 2550; + return 2566; } } else @@ -3021,7 +3109,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0110x1xxxxxxxxxx cpyfprtwn. */ - return 2547; + return 2563; } else { @@ -3029,7 +3117,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1110x1xxxxxxxxxx cpyfprtn. */ - return 2553; + return 2569; } } } @@ -3046,7 +3134,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0001x1xxxxxxxxxx cpyfpwt. */ - return 2532; + return 2548; } else { @@ -3054,7 +3142,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1001x1xxxxxxxxxx cpyfpwtrn. */ - return 2538; + return 2554; } } else @@ -3065,7 +3153,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0101x1xxxxxxxxxx cpyfpwtwn. */ - return 2535; + return 2551; } else { @@ -3073,7 +3161,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1101x1xxxxxxxxxx cpyfpwtn. */ - return 2541; + return 2557; } } } @@ -3087,7 +3175,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0011x1xxxxxxxxxx cpyfpt. */ - return 2556; + return 2572; } else { @@ -3095,7 +3183,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1011x1xxxxxxxxxx cpyfptrn. */ - return 2562; + return 2578; } } else @@ -3106,7 +3194,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0111x1xxxxxxxxxx cpyfptwn. */ - return 2559; + return 2575; } else { @@ -3114,7 +3202,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1111x1xxxxxxxxxx cpyfptn. */ - return 2565; + return 2581; } } } @@ -3179,7 +3267,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 00011001010xxxxxxxxx00xxxxxxxxxx ldapurb. */ - return 2461; + return 2477; } else { @@ -3187,7 +3275,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 10011001010xxxxxxxxx00xxxxxxxxxx ldapur. */ - return 2469; + return 2485; } } else @@ -3198,7 +3286,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 01011001010xxxxxxxxx00xxxxxxxxxx ldapurh. */ - return 2465; + return 2481; } else { @@ -3206,7 +3294,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 11011001010xxxxxxxxx00xxxxxxxxxx ldapur. */ - return 2472; + return 2488; } } } @@ -3244,7 +3332,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0000x1xxxxxxxxxx cpyfm. */ - return 2521; + return 2537; } else { @@ -3252,7 +3340,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1000x1xxxxxxxxxx cpyfmrn. */ - return 2527; + return 2543; } } else @@ -3263,7 +3351,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0100x1xxxxxxxxxx cpyfmwn. */ - return 2524; + return 2540; } else { @@ -3271,7 +3359,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1100x1xxxxxxxxxx cpyfmn. */ - return 2530; + return 2546; } } } @@ -3285,7 +3373,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0010x1xxxxxxxxxx cpyfmrt. */ - return 2545; + return 2561; } else { @@ -3293,7 +3381,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1010x1xxxxxxxxxx cpyfmrtrn. */ - return 2551; + return 2567; } } else @@ -3304,7 +3392,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0110x1xxxxxxxxxx cpyfmrtwn. */ - return 2548; + return 2564; } else { @@ -3312,7 +3400,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1110x1xxxxxxxxxx cpyfmrtn. */ - return 2554; + return 2570; } } } @@ -3329,7 +3417,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0001x1xxxxxxxxxx cpyfmwt. */ - return 2533; + return 2549; } else { @@ -3337,7 +3425,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1001x1xxxxxxxxxx cpyfmwtrn. */ - return 2539; + return 2555; } } else @@ -3348,7 +3436,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0101x1xxxxxxxxxx cpyfmwtwn. */ - return 2536; + return 2552; } else { @@ -3356,7 +3444,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1101x1xxxxxxxxxx cpyfmwtn. */ - return 2542; + return 2558; } } } @@ -3370,7 +3458,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0011x1xxxxxxxxxx cpyfmt. */ - return 2557; + return 2573; } else { @@ -3378,7 +3466,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1011x1xxxxxxxxxx cpyfmtrn. */ - return 2563; + return 2579; } } else @@ -3389,7 +3477,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0111x1xxxxxxxxxx cpyfmtwn. */ - return 2560; + return 2576; } else { @@ -3397,7 +3485,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1111x1xxxxxxxxxx cpyfmtn. */ - return 2566; + return 2582; } } } @@ -3465,7 +3553,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 00011001100xxxxxxxxx00xxxxxxxxxx ldapursb. */ - return 2463; + return 2479; } else { @@ -3473,7 +3561,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 10011001100xxxxxxxxx00xxxxxxxxxx ldapursw. */ - return 2470; + return 2486; } } else @@ -3482,7 +3570,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1011001100xxxxxxxxx00xxxxxxxxxx ldapursh. */ - return 2467; + return 2483; } } else @@ -3493,7 +3581,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0011001110xxxxxxxxx00xxxxxxxxxx ldapursb. */ - return 2462; + return 2478; } else { @@ -3501,7 +3589,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1011001110xxxxxxxxx00xxxxxxxxxx ldapursh. */ - return 2466; + return 2482; } } } @@ -3563,7 +3651,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0000x1xxxxxxxxxx cpyfe. */ - return 2522; + return 2538; } else { @@ -3571,7 +3659,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0000x1xxxxxxxxxx setp. */ - return 2616; + return 2632; } } else @@ -3582,7 +3670,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx1000x1xxxxxxxxxx cpyfern. */ - return 2528; + return 2544; } else { @@ -3590,7 +3678,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx1000x1xxxxxxxxxx sete. */ - return 2618; + return 2634; } } } @@ -3604,7 +3692,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0100x1xxxxxxxxxx cpyfewn. */ - return 2525; + return 2541; } else { @@ -3612,7 +3700,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0100x1xxxxxxxxxx setm. */ - return 2617; + return 2633; } } else @@ -3621,7 +3709,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0110011x0xxxxx1100x1xxxxxxxxxx cpyfen. */ - return 2531; + return 2547; } } } @@ -3637,7 +3725,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0010x1xxxxxxxxxx cpyfert. */ - return 2546; + return 2562; } else { @@ -3645,7 +3733,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0010x1xxxxxxxxxx setpn. */ - return 2622; + return 2638; } } else @@ -3656,7 +3744,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx1010x1xxxxxxxxxx cpyfertrn. */ - return 2552; + return 2568; } else { @@ -3664,7 +3752,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx1010x1xxxxxxxxxx seten. */ - return 2624; + return 2640; } } } @@ -3678,7 +3766,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0110x1xxxxxxxxxx cpyfertwn. */ - return 2549; + return 2565; } else { @@ -3686,7 +3774,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0110x1xxxxxxxxxx setmn. */ - return 2623; + return 2639; } } else @@ -3695,7 +3783,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0110011x0xxxxx1110x1xxxxxxxxxx cpyfertn. */ - return 2555; + return 2571; } } } @@ -3714,7 +3802,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0001x1xxxxxxxxxx cpyfewt. */ - return 2534; + return 2550; } else { @@ -3722,7 +3810,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0001x1xxxxxxxxxx setpt. */ - return 2619; + return 2635; } } else @@ -3733,7 +3821,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx1001x1xxxxxxxxxx cpyfewtrn. */ - return 2540; + return 2556; } else { @@ -3741,7 +3829,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx1001x1xxxxxxxxxx setet. */ - return 2621; + return 2637; } } } @@ -3755,7 +3843,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0101x1xxxxxxxxxx cpyfewtwn. */ - return 2537; + return 2553; } else { @@ -3763,7 +3851,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0101x1xxxxxxxxxx setmt. */ - return 2620; + return 2636; } } else @@ -3772,7 +3860,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0110011x0xxxxx1101x1xxxxxxxxxx cpyfewtn. */ - return 2543; + return 2559; } } } @@ -3788,7 +3876,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0011x1xxxxxxxxxx cpyfet. */ - return 2558; + return 2574; } else { @@ -3796,7 +3884,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0011x1xxxxxxxxxx setptn. */ - return 2625; + return 2641; } } else @@ -3807,7 +3895,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx1011x1xxxxxxxxxx cpyfetrn. */ - return 2564; + return 2580; } else { @@ -3815,7 +3903,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx1011x1xxxxxxxxxx setetn. */ - return 2627; + return 2643; } } } @@ -3829,7 +3917,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0111x1xxxxxxxxxx cpyfetwn. */ - return 2561; + return 2577; } else { @@ -3837,7 +3925,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0111x1xxxxxxxxxx setmtn. */ - return 2626; + return 2642; } } else @@ -3846,7 +3934,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0110011x0xxxxx1111x1xxxxxxxxxx cpyfetn. */ - return 2567; + return 2583; } } } @@ -4219,7 +4307,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1x11010110xxxx0x01000xxxxxxxxxx abs. */ - return 2645; + return 2661; } else { @@ -4237,7 +4325,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010110xxxxxx11000xxxxxxxxxx smax. */ - return 2648; + return 2664; } } } @@ -4317,7 +4405,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010x00xxxxxx0xx10xxxxxxxxxx setf8. */ - return 2458; + return 2474; } else { @@ -4325,7 +4413,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010x00xxxxxx1xx10xxxxxxxxxx setf16. */ - return 2459; + return 2475; } } else @@ -4432,7 +4520,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010110xxxxxx11010xxxxxxxxxx smin. */ - return 2650; + return 2666; } } } @@ -4448,7 +4536,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010110xxxx0x00110xxxxxxxxxx ctz. */ - return 2647; + return 2663; } else { @@ -4493,7 +4581,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010000xxxxxxxxx01xxxxxxxxxx rmif. */ - return 2457; + return 2473; } else { @@ -4587,7 +4675,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010x10xxxxxx11001xxxxxxxxxx umax. */ - return 2649; + return 2665; } } } @@ -4717,7 +4805,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010xx0xxxxxx11011xxxxxxxxxx umin. */ - return 2651; + return 2667; } } } @@ -4733,7 +4821,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010xx0xxxx0x00111xxxxxxxxxx cnt. */ - return 2646; + return 2662; } else { @@ -5575,7 +5663,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x01x1xxxxx000110xxxxxxxxxx usdot. */ - return 2477; + return 2493; } } } @@ -5649,7 +5737,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x01x1xxxxx000111xxxxxxxxxx sudot. */ - return 2478; + return 2494; } } } @@ -8323,7 +8411,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x0xx0xxxxx011110xxxxxxxxxx usdot. */ - return 2476; + return 2492; } } } @@ -10027,7 +10115,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0100xxx10101xxxxxxxxxxxxx bfcvtnt. */ - return 2505; + return 2521; } } else @@ -10270,7 +10358,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x00x1xxxxxx00xxxxxxxxxxxxx ld1rob. */ - return 2481; + return 2497; } else { @@ -10278,7 +10366,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x01x1xxxxxx00xxxxxxxxxxxxx ld1roh. */ - return 2482; + return 2498; } } else @@ -10510,7 +10598,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0011xxxxx010xxxxxxxxxxxxx bfdot. */ - return 2502; + return 2518; } else { @@ -10531,7 +10619,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx010xx0xxxxxxxxxx bfmlalb. */ - return 2509; + return 2525; } else { @@ -10539,7 +10627,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx010xx1xxxxxxxxxx bfmlalt. */ - return 2508; + return 2524; } } else @@ -10594,7 +10682,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11001x0011xxxxx1x0xxxxxxxxxxxxx bfdot. */ - return 2501; + return 2517; } else { @@ -10606,7 +10694,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx1x0xx0xxxxxxxxxx bfmlalb. */ - return 2507; + return 2523; } else { @@ -10614,7 +10702,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx1x0xx1xxxxxxxxxx bfmlalt. */ - return 2506; + return 2522; } } else @@ -10665,7 +10753,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x00x1xxxxx001xxxxxxxxxxxxx ld1rob. */ - return 2485; + return 2501; } else { @@ -10673,7 +10761,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x01x1xxxxx001xxxxxxxxxxxxx ld1roh. */ - return 2486; + return 2502; } } else @@ -11032,7 +11120,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0101xxxxx111xxxxxxxxxxxxx fmmla. */ - return 2479; + return 2495; } else { @@ -11065,7 +11153,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0011xxxxx111xxxxxxxxxxxxx bfmmla. */ - return 2503; + return 2519; } else { @@ -11095,7 +11183,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx111xxxxxxxxxxxxx fmmla. */ - return 2480; + return 2496; } else { @@ -11224,7 +11312,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000x00xxxxxxxxxx zip1. */ - return 2489; + return 2505; } else { @@ -11234,7 +11322,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000010xxxxxxxxxx uzp1. */ - return 2491; + return 2507; } else { @@ -11242,7 +11330,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000110xxxxxxxxxx trn1. */ - return 2493; + return 2509; } } } @@ -11254,7 +11342,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000x01xxxxxxxxxx zip2. */ - return 2490; + return 2506; } else { @@ -11264,7 +11352,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000011xxxxxxxxxx uzp2. */ - return 2492; + return 2508; } else { @@ -11272,7 +11360,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000111xxxxxxxxxx trn2. */ - return 2494; + return 2510; } } } @@ -12331,7 +12419,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x1000xxxxx100110xxxxxxxxxx smmla. */ - return 2473; + return 2489; } else { @@ -12339,7 +12427,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x1100xxxxx100110xxxxxxxxxx usmmla. */ - return 2475; + return 2491; } } else @@ -12348,7 +12436,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x1x10xxxxx100110xxxxxxxxxx ummla. */ - return 2474; + return 2490; } } } @@ -13844,7 +13932,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x10x1xxxxx000xxxxxxxxxxxxx ld1row. */ - return 2483; + return 2499; } else { @@ -13852,7 +13940,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x11x1xxxxx000xxxxxxxxxxxxx ld1rod. */ - return 2484; + return 2500; } } } @@ -14226,7 +14314,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x10x1xxxxx001xxxxxxxxxxxxx ld1row. */ - return 2487; + return 2503; } else { @@ -14234,7 +14322,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x11x1xxxxx001xxxxxxxxxxxxx ld1rod. */ - return 2488; + return 2504; } } } @@ -15679,7 +15767,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x110001x10101xxxxxxxxxxxxx bfcvt. */ - return 2504; + return 2520; } } else @@ -17029,7 +17117,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1010100xxxxxxxxxxxxxxxxxxx1xxxx bc.c. */ - return 2640; + return 2656; } else { @@ -17609,7 +17697,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0000xxxxxxxxxxxx cpyp. */ - return 2568; + return 2584; } else { @@ -17617,7 +17705,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0000xxxxxxxxxxxx cpye. */ - return 2570; + return 2586; } } else @@ -17628,7 +17716,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1000xxxxxxxxxxxx cpyprn. */ - return 2574; + return 2590; } else { @@ -17636,7 +17724,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1000xxxxxxxxxxxx cpyern. */ - return 2576; + return 2592; } } } @@ -17650,7 +17738,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0100xxxxxxxxxxxx cpypwn. */ - return 2571; + return 2587; } else { @@ -17658,7 +17746,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0100xxxxxxxxxxxx cpyewn. */ - return 2573; + return 2589; } } else @@ -17669,7 +17757,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1100xxxxxxxxxxxx cpypn. */ - return 2577; + return 2593; } else { @@ -17677,7 +17765,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1100xxxxxxxxxxxx cpyen. */ - return 2579; + return 2595; } } } @@ -17694,7 +17782,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0010xxxxxxxxxxxx cpyprt. */ - return 2592; + return 2608; } else { @@ -17702,7 +17790,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0010xxxxxxxxxxxx cpyert. */ - return 2594; + return 2610; } } else @@ -17713,7 +17801,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1010xxxxxxxxxxxx cpyprtrn. */ - return 2598; + return 2614; } else { @@ -17721,7 +17809,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1010xxxxxxxxxxxx cpyertrn. */ - return 2600; + return 2616; } } } @@ -17735,7 +17823,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0110xxxxxxxxxxxx cpyprtwn. */ - return 2595; + return 2611; } else { @@ -17743,7 +17831,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0110xxxxxxxxxxxx cpyertwn. */ - return 2597; + return 2613; } } else @@ -17754,7 +17842,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1110xxxxxxxxxxxx cpyprtn. */ - return 2601; + return 2617; } else { @@ -17762,7 +17850,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1110xxxxxxxxxxxx cpyertn. */ - return 2603; + return 2619; } } } @@ -17782,7 +17870,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0001xxxxxxxxxxxx cpypwt. */ - return 2580; + return 2596; } else { @@ -17790,7 +17878,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0001xxxxxxxxxxxx cpyewt. */ - return 2582; + return 2598; } } else @@ -17801,7 +17889,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1001xxxxxxxxxxxx cpypwtrn. */ - return 2586; + return 2602; } else { @@ -17809,7 +17897,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1001xxxxxxxxxxxx cpyewtrn. */ - return 2588; + return 2604; } } } @@ -17823,7 +17911,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0101xxxxxxxxxxxx cpypwtwn. */ - return 2583; + return 2599; } else { @@ -17831,7 +17919,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0101xxxxxxxxxxxx cpyewtwn. */ - return 2585; + return 2601; } } else @@ -17842,7 +17930,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1101xxxxxxxxxxxx cpypwtn. */ - return 2589; + return 2605; } else { @@ -17850,7 +17938,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1101xxxxxxxxxxxx cpyewtn. */ - return 2591; + return 2607; } } } @@ -17867,7 +17955,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0011xxxxxxxxxxxx cpypt. */ - return 2604; + return 2620; } else { @@ -17875,7 +17963,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0011xxxxxxxxxxxx cpyet. */ - return 2606; + return 2622; } } else @@ -17886,7 +17974,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1011xxxxxxxxxxxx cpyptrn. */ - return 2610; + return 2626; } else { @@ -17894,7 +17982,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1011xxxxxxxxxxxx cpyetrn. */ - return 2612; + return 2628; } } } @@ -17908,7 +17996,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0111xxxxxxxxxxxx cpyptwn. */ - return 2607; + return 2623; } else { @@ -17916,7 +18004,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0111xxxxxxxxxxxx cpyetwn. */ - return 2609; + return 2625; } } else @@ -17927,7 +18015,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1111xxxxxxxxxxxx cpyptn. */ - return 2613; + return 2629; } else { @@ -17935,7 +18023,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1111xxxxxxxxxxxx cpyetn. */ - return 2615; + return 2631; } } } @@ -17969,7 +18057,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0000xxxxxxxxxxxx cpym. */ - return 2569; + return 2585; } else { @@ -17977,7 +18065,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0000xxxxxxxxxxxx setgp. */ - return 2628; + return 2644; } } else @@ -17988,7 +18076,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx1000xxxxxxxxxxxx cpymrn. */ - return 2575; + return 2591; } else { @@ -17996,7 +18084,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx1000xxxxxxxxxxxx setge. */ - return 2630; + return 2646; } } } @@ -18010,7 +18098,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0100xxxxxxxxxxxx cpymwn. */ - return 2572; + return 2588; } else { @@ -18018,7 +18106,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0100xxxxxxxxxxxx setgm. */ - return 2629; + return 2645; } } else @@ -18027,7 +18115,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011101x1xxxxxx1100xxxxxxxxxxxx cpymn. */ - return 2578; + return 2594; } } } @@ -18043,7 +18131,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0010xxxxxxxxxxxx cpymrt. */ - return 2593; + return 2609; } else { @@ -18051,7 +18139,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0010xxxxxxxxxxxx setgpn. */ - return 2634; + return 2650; } } else @@ -18062,7 +18150,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx1010xxxxxxxxxxxx cpymrtrn. */ - return 2599; + return 2615; } else { @@ -18070,7 +18158,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx1010xxxxxxxxxxxx setgen. */ - return 2636; + return 2652; } } } @@ -18084,7 +18172,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0110xxxxxxxxxxxx cpymrtwn. */ - return 2596; + return 2612; } else { @@ -18092,7 +18180,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0110xxxxxxxxxxxx setgmn. */ - return 2635; + return 2651; } } else @@ -18101,7 +18189,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011101x1xxxxxx1110xxxxxxxxxxxx cpymrtn. */ - return 2602; + return 2618; } } } @@ -18120,7 +18208,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0001xxxxxxxxxxxx cpymwt. */ - return 2581; + return 2597; } else { @@ -18128,7 +18216,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0001xxxxxxxxxxxx setgpt. */ - return 2631; + return 2647; } } else @@ -18139,7 +18227,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx1001xxxxxxxxxxxx cpymwtrn. */ - return 2587; + return 2603; } else { @@ -18147,7 +18235,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx1001xxxxxxxxxxxx setget. */ - return 2633; + return 2649; } } } @@ -18161,7 +18249,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0101xxxxxxxxxxxx cpymwtwn. */ - return 2584; + return 2600; } else { @@ -18169,7 +18257,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0101xxxxxxxxxxxx setgmt. */ - return 2632; + return 2648; } } else @@ -18178,7 +18266,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011101x1xxxxxx1101xxxxxxxxxxxx cpymwtn. */ - return 2590; + return 2606; } } } @@ -18194,7 +18282,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0011xxxxxxxxxxxx cpymt. */ - return 2605; + return 2621; } else { @@ -18202,7 +18290,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0011xxxxxxxxxxxx setgptn. */ - return 2637; + return 2653; } } else @@ -18213,7 +18301,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx1011xxxxxxxxxxxx cpymtrn. */ - return 2611; + return 2627; } else { @@ -18221,7 +18309,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx1011xxxxxxxxxxxx setgetn. */ - return 2639; + return 2655; } } } @@ -18235,7 +18323,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0111xxxxxxxxxxxx cpymtwn. */ - return 2608; + return 2624; } else { @@ -18243,7 +18331,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0111xxxxxxxxxxxx setgmtn. */ - return 2638; + return 2654; } } else @@ -18252,7 +18340,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011101x1xxxxxx1111xxxxxxxxxxxx cpymtn. */ - return 2614; + return 2630; } } } @@ -18419,7 +18507,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110xx0xxxxx1x1001xxxxxxxxxx smmla. */ - return 2495; + return 2511; } } } @@ -18452,7 +18540,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110xx0xxxxx1x0101xxxxxxxxxx sdot. */ - return 2421; + return 2437; } } else @@ -18526,7 +18614,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110xx0xxxxx1x1011xxxxxxxxxx usmmla. */ - return 2497; + return 2513; } } } @@ -18559,7 +18647,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110xx0xxxxx1x0111xxxxxxxxxx usdot. */ - return 2498; + return 2514; } } else @@ -18606,7 +18694,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110000xxxxxxxxxxxxxxxxxxxxx eor3. */ - return 2428; + return 2444; } else { @@ -18614,7 +18702,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110100xxxxxxxxxxxxxxxxxxxxx xar. */ - return 2430; + return 2446; } } else @@ -18625,7 +18713,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110x10xxxxx0xxxxxxxxxxxxxxx sm3ss1. */ - return 2432; + return 2448; } else { @@ -18639,7 +18727,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110010xxxxx1xxx00xxxxxxxxxx sm3tt1a. */ - return 2433; + return 2449; } else { @@ -18647,7 +18735,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110110xxxxx1xxx00xxxxxxxxxx sha512su0. */ - return 2426; + return 2442; } } else @@ -18656,7 +18744,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110x10xxxxx1xxx10xxxxxxxxxx sm3tt2a. */ - return 2435; + return 2451; } } else @@ -18669,7 +18757,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110010xxxxx1xxx01xxxxxxxxxx sm3tt1b. */ - return 2434; + return 2450; } else { @@ -18677,7 +18765,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110110xxxxx1xxx01xxxxxxxxxx sm4e. */ - return 2439; + return 2455; } } else @@ -18686,7 +18774,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110x10xxxxx1xxx11xxxxxxxxxx sm3tt2b. */ - return 2436; + return 2452; } } } @@ -18867,7 +18955,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx101110xx0xxxxx100101xxxxxxxxxx udot. */ - return 2420; + return 2436; } } else @@ -18898,7 +18986,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx101110xx0xxxxx101x01xxxxxxxxxx ummla. */ - return 2496; + return 2512; } else { @@ -18917,7 +19005,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx101110xx0xxxxx1x1011xxxxxxxxxx bfmmla. */ - return 2512; + return 2528; } else { @@ -18927,7 +19015,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx1011100x0xxxxx1x1111xxxxxxxxxx bfdot. */ - return 2510; + return 2526; } else { @@ -18937,7 +19025,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x01011101x0xxxxx1x1111xxxxxxxxxx bfmlalb. */ - return 2517; + return 2533; } else { @@ -18945,7 +19033,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11011101x0xxxxx1x1111xxxxxxxxxx bfmlalt. */ - return 2516; + return 2532; } } } @@ -19529,7 +19617,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000011101x1xxxx1011010xxxxxxxxxx bfcvtn. */ - return 2513; + return 2529; } else { @@ -19537,7 +19625,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010011101x1xxxx1011010xxxxxxxxxx bfcvtn2. */ - return 2514; + return 2530; } } } @@ -19855,7 +19943,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110xx1xxxxx0xxxxxxxxxxxxxxx bcax. */ - return 2431; + return 2447; } } else @@ -20466,7 +20554,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 11001110xx1xxxxx100000xxxxxxxxxx sha512h. */ - return 2424; + return 2440; } } } @@ -20518,7 +20606,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 11001110xx1xxxxx110000xxxxxxxxxx sm3partw1. */ - return 2437; + return 2453; } } } @@ -20761,7 +20849,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110xx1xxxxx100010xxxxxxxxxx sha512su1. */ - return 2427; + return 2443; } } else @@ -20837,7 +20925,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x0011100x1xxxxx110010xxxxxxxxxx sm4ekey. */ - return 2440; + return 2456; } } else @@ -21663,7 +21751,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110xx1xxxxx100001xxxxxxxxxx sha512h2. */ - return 2425; + return 2441; } } else @@ -21695,7 +21783,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x0011100x1xxxxx110001xxxxxxxxxx sm3partw2. */ - return 2438; + return 2454; } } else @@ -21935,7 +22023,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110xx1xxxxx100011xxxxxxxxxx rax1. */ - return 2429; + return 2445; } } else @@ -21967,7 +22055,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x01011100x1xxxxx110011xxxxxxxxxx fmlal2. */ - return 2443; + return 2459; } else { @@ -21975,7 +22063,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11011100x1xxxxx110011xxxxxxxxxx fmlal2. */ - return 2447; + return 2463; } } } @@ -21997,7 +22085,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x01011101x1xxxxx110011xxxxxxxxxx fmlsl2. */ - return 2444; + return 2460; } else { @@ -22005,7 +22093,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11011101x1xxxxx110011xxxxxxxxxx fmlsl2. */ - return 2448; + return 2464; } } } @@ -22044,7 +22132,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x00011100x1xxxxx111011xxxxxxxxxx fmlal. */ - return 2441; + return 2457; } else { @@ -22052,7 +22140,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10011100x1xxxxx111011xxxxxxxxxx fmlal. */ - return 2445; + return 2461; } } else @@ -22074,7 +22162,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x00011101x1xxxxx111011xxxxxxxxxx fmlsl. */ - return 2442; + return 2458; } else { @@ -22082,7 +22170,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10011101x1xxxxx111011xxxxxxxxxx fmlsl. */ - return 2446; + return 2462; } } else @@ -23890,7 +23978,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0001111xxxxxxxx0000x0xxxxxxxxxx fmlal. */ - return 2449; + return 2465; } else { @@ -23898,7 +23986,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1001111xxxxxxxx0000x0xxxxxxxxxx fmlal. */ - return 2453; + return 2469; } } else @@ -23920,7 +24008,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0001111xxxxxxxx0100x0xxxxxxxxxx fmlsl. */ - return 2450; + return 2466; } else { @@ -23928,7 +24016,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1001111xxxxxxxx0100x0xxxxxxxxxx fmlsl. */ - return 2454; + return 2470; } } else @@ -24434,7 +24522,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0101111xxxxxxxx1000x0xxxxxxxxxx fmlal2. */ - return 2451; + return 2467; } else { @@ -24442,7 +24530,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1101111xxxxxxxx1000x0xxxxxxxxxx fmlal2. */ - return 2455; + return 2471; } } } @@ -24464,7 +24552,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0101111xxxxxxxx1100x0xxxxxxxxxx fmlsl2. */ - return 2452; + return 2468; } else { @@ -24472,7 +24560,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1101111xxxxxxxx1100x0xxxxxxxxxx fmlsl2. */ - return 2456; + return 2472; } } } @@ -24528,7 +24616,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx001111xxxxxxxx1110x0xxxxxxxxxx sdot. */ - return 2423; + return 2439; } else { @@ -24536,7 +24624,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx101111xxxxxxxx1110x0xxxxxxxxxx udot. */ - return 2422; + return 2438; } } } @@ -24639,7 +24727,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx00111100xxxxxx1111x0xxxxxxxxxx sudot. */ - return 2500; + return 2516; } else { @@ -24647,7 +24735,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx00111110xxxxxx1111x0xxxxxxxxxx usdot. */ - return 2499; + return 2515; } } else @@ -24658,7 +24746,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx00111101xxxxxx1111x0xxxxxxxxxx bfdot. */ - return 2511; + return 2527; } else { @@ -24668,7 +24756,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x000111111xxxxxx1111x0xxxxxxxxxx bfmlalb. */ - return 2519; + return 2535; } else { @@ -24676,7 +24764,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x100111111xxxxxx1111x0xxxxxxxxxx bfmlalt. */ - return 2518; + return 2534; } } } @@ -25165,8 +25253,24 @@ aarch64_find_next_opcode (const aarch64_opcode *opcode) { case 2389: value = 2391; break; /* mov --> mova. */ case 2391: return NULL; /* mova --> NULL. */ + case 2426: value = 2434; break; /* mov --> mova. */ + case 2434: return NULL; /* mova --> NULL. */ + case 2424: value = 2432; break; /* mov --> mova. */ + case 2432: return NULL; /* mova --> NULL. */ + case 2427: value = 2435; break; /* mov --> mova. */ + case 2435: return NULL; /* mova --> NULL. */ + case 2425: value = 2433; break; /* mov --> mova. */ + case 2433: return NULL; /* mova --> NULL. */ case 2388: value = 2390; break; /* mov --> mova. */ case 2390: return NULL; /* mova --> NULL. */ + case 2422: value = 2430; break; /* mov --> mova. */ + case 2430: return NULL; /* mova --> NULL. */ + case 2420: value = 2428; break; /* mov --> mova. */ + case 2428: return NULL; /* mova --> NULL. */ + case 2423: value = 2431; break; /* mov --> mova. */ + case 2431: return NULL; /* mova --> NULL. */ + case 2421: value = 2429; break; /* mov --> mova. */ + case 2429: return NULL; /* mova --> NULL. */ case 2393: value = 2398; break; /* ld1b --> ld1b. */ case 2398: return NULL; /* ld1b --> NULL. */ case 2395: value = 2400; break; /* ld1w --> ld1w. */ @@ -25188,11 +25292,11 @@ aarch64_find_next_opcode (const aarch64_opcode *opcode) case 2407: value = 2412; break; /* st1q --> st1q. */ case 2412: return NULL; /* st1q --> NULL. */ case 12: value = 19; break; /* add --> addg. */ - case 19: value = 2641; break; /* addg --> smax. */ - case 2641: value = 2642; break; /* smax --> umax. */ - case 2642: value = 2643; break; /* umax --> smin. */ - case 2643: value = 2644; break; /* smin --> umin. */ - case 2644: return NULL; /* umin --> NULL. */ + case 19: value = 2657; break; /* addg --> smax. */ + case 2657: value = 2658; break; /* smax --> umax. */ + case 2658: value = 2659; break; /* umax --> smin. */ + case 2659: value = 2660; break; /* smin --> umin. */ + case 2660: return NULL; /* umin --> NULL. */ case 16: value = 20; break; /* sub --> subg. */ case 20: return NULL; /* subg --> NULL. */ case 971: value = 975; break; /* stnp --> stp. */ @@ -25350,8 +25454,8 @@ aarch64_find_next_opcode (const aarch64_opcode *opcode) case 824: return NULL; /* fsqrt --> NULL. */ case 832: value = 833; break; /* frintz --> frintz. */ case 833: return NULL; /* frintz --> NULL. */ - case 825: value = 2515; break; /* fcvt --> bfcvt. */ - case 2515: return NULL; /* bfcvt --> NULL. */ + case 825: value = 2531; break; /* fcvt --> bfcvt. */ + case 2531: return NULL; /* bfcvt --> NULL. */ case 834: value = 835; break; /* frinta --> frinta. */ case 835: return NULL; /* frinta --> NULL. */ case 836: value = 837; break; /* frintx --> frintx. */ @@ -25858,9 +25962,9 @@ aarch64_extract_operand (const aarch64_operand *self, case 203: case 209: case 212: - case 214: - case 215: case 218: + case 219: + case 224: return aarch64_ext_regno (self, info, code, inst, errors); case 10: return aarch64_ext_regrt_sysins (self, info, code, inst, errors); @@ -25876,7 +25980,7 @@ aarch64_extract_operand (const aarch64_operand *self, case 33: case 34: case 35: - case 226: + case 234: return aarch64_ext_reglane (self, info, code, inst, errors); case 36: return aarch64_ext_reglist (self, info, code, inst, errors); @@ -25922,10 +26026,10 @@ aarch64_extract_operand (const aarch64_operand *self, case 192: case 193: case 194: - case 219: case 225: - case 230: - case 231: + case 233: + case 238: + case 239: return aarch64_ext_imm (self, info, code, inst, errors); case 44: case 45: @@ -26087,21 +26191,31 @@ aarch64_extract_operand (const aarch64_operand *self, case 211: case 213: return aarch64_ext_sve_reglist (self, info, code, inst, errors); + case 214: + case 215: case 216: case 217: + return aarch64_ext_sve_aligned_reglist (self, info, code, inst, errors); case 220: + case 222: + case 226: return aarch64_ext_sme_za_hv_tiles (self, info, code, inst, errors); case 221: - return aarch64_ext_sme_za_array (self, info, code, inst, errors); - case 222: - return aarch64_ext_sme_addr_ri_u4xvl (self, info, code, inst, errors); case 223: - return aarch64_ext_sme_sm_za (self, info, code, inst, errors); - case 224: - return aarch64_ext_sme_pred_reg_with_index (self, info, code, inst, errors); + return aarch64_ext_sme_za_hv_tiles_range (self, info, code, inst, errors); case 227: case 228: case 229: + return aarch64_ext_sme_za_array (self, info, code, inst, errors); + case 230: + return aarch64_ext_sme_addr_ri_u4xvl (self, info, code, inst, errors); + case 231: + return aarch64_ext_sme_sm_za (self, info, code, inst, errors); + case 232: + return aarch64_ext_sme_pred_reg_with_index (self, info, code, inst, errors); + case 235: + case 236: + case 237: return aarch64_ext_x0_to_x30 (self, info, code, inst, errors); default: assert (0); abort (); } diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c index 49bfd46906e..7b2cf3130c4 100644 --- a/opcodes/aarch64-dis.c +++ b/opcodes/aarch64-dis.c @@ -1715,6 +1715,20 @@ aarch64_ext_sve_aimm (const aarch64_operand *self, && decode_sve_aimm (info, (uint8_t) info->imm.value)); } +bool +aarch64_ext_sve_aligned_reglist (const aarch64_operand *self, + aarch64_opnd_info *info, aarch64_insn code, + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) +{ + unsigned int num_regs = get_operand_specific_data (self); + unsigned int val = extract_field (self->fields[0], code, 0); + info->reglist.first_regno = val * num_regs; + info->reglist.num_regs = num_regs; + info->reglist.stride = 1; + return true; +} + /* Decode an SVE CPY/DUP immediate. */ bool aarch64_ext_sve_asimm (const aarch64_operand *self, @@ -1823,6 +1837,36 @@ aarch64_ext_sme_za_hv_tiles (const aarch64_operand *self, return true; } +bool +aarch64_ext_sme_za_hv_tiles_range (const aarch64_operand *self, + aarch64_opnd_info *info, aarch64_insn code, + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors + ATTRIBUTE_UNUSED) +{ + int ebytes = aarch64_get_qualifier_esize (info->qualifier); + int range_size = get_opcode_dependent_value (inst->opcode); + int fld_v = extract_field (self->fields[0], code, 0); + int fld_rv = extract_field (self->fields[1], code, 0); + int fld_zan_imm = extract_field (self->fields[2], code, 0); + int max_value = 16 / range_size / ebytes; + + if (max_value == 0) + max_value = 1; + + int regno = fld_zan_imm / max_value; + if (regno >= ebytes) + return false; + + info->indexed_za.regno = regno; + info->indexed_za.index.imm = (fld_zan_imm % max_value) * range_size; + info->indexed_za.index.countm1 = range_size - 1; + info->indexed_za.index.regno = fld_rv + 12; + info->indexed_za.v = fld_v; + + return true; +} + /* Decode in SME instruction ZERO list of up to eight 64-bit element tile names separated by commas, encoded in the "imm8" field. @@ -1850,10 +1894,15 @@ aarch64_ext_sme_za_array (const aarch64_operand *self, const aarch64_inst *inst ATTRIBUTE_UNUSED, aarch64_operand_error *errors ATTRIBUTE_UNUSED) { - int regno = extract_field (self->fields[0], code, 0) + 12; + int regno = extract_field (self->fields[0], code, 0); + if (info->type == AARCH64_OPND_SME_ZA_array_off4) + regno += 12; + else + regno += 8; int imm = extract_field (self->fields[1], code, 0); info->indexed_za.index.regno = regno; info->indexed_za.index.imm = imm; + info->indexed_za.group_size = get_opcode_dependent_value (inst->opcode); return true; } @@ -2979,6 +3028,10 @@ aarch64_decode_variant_using_iclass (aarch64_inst *inst) } break; + case sme_size_22: + variant = extract_field (FLD_SME_size_22, inst->value, 0); + break; + case sve_cpy: variant = extract_fields (inst->value, 0, 2, FLD_size, FLD_SVE_M_14); break; @@ -3006,6 +3059,11 @@ aarch64_decode_variant_using_iclass (aarch64_inst *inst) variant = 3; break; + case sme2_mov: + /* .D is preferred over the other sizes in disassembly. */ + variant = 3; + break; + case sme_misc: case sve_misc: /* These instructions have only a single variant. */ diff --git a/opcodes/aarch64-dis.h b/opcodes/aarch64-dis.h index 255445c9580..1d459858e0d 100644 --- a/opcodes/aarch64-dis.h +++ b/opcodes/aarch64-dis.h @@ -111,6 +111,7 @@ AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_zz_lsl); AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_zz_sxtw); AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_zz_uxtw); AARCH64_DECL_OPD_EXTRACTOR (ext_sve_aimm); +AARCH64_DECL_OPD_EXTRACTOR (ext_sve_aligned_reglist); AARCH64_DECL_OPD_EXTRACTOR (ext_sve_asimm); AARCH64_DECL_OPD_EXTRACTOR (ext_sve_float_half_one); AARCH64_DECL_OPD_EXTRACTOR (ext_sve_float_half_two); @@ -123,6 +124,7 @@ AARCH64_DECL_OPD_EXTRACTOR (ext_sve_scale); AARCH64_DECL_OPD_EXTRACTOR (ext_sve_shlimm); AARCH64_DECL_OPD_EXTRACTOR (ext_sve_shrimm); AARCH64_DECL_OPD_EXTRACTOR (ext_sme_za_hv_tiles); +AARCH64_DECL_OPD_EXTRACTOR (ext_sme_za_hv_tiles_range); AARCH64_DECL_OPD_EXTRACTOR (ext_sme_za_list); AARCH64_DECL_OPD_EXTRACTOR (ext_sme_za_array); AARCH64_DECL_OPD_EXTRACTOR (ext_sme_addr_ri_u4xvl); diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c index b00b22aaaf7..f1103efd23f 100644 --- a/opcodes/aarch64-opc-2.c +++ b/opcodes/aarch64-opc-2.c @@ -238,13 +238,21 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_SVE_REGLIST, "SVE_ZnxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "a list of SVE vector registers"}, {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "an SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REGLIST, "SVE_ZtxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "a list of SVE vector registers"}, + {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zdnx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zdn2}, "a list of SVE vector registers"}, + {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zdnx4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zdn4}, "a list of SVE vector registers"}, + {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Znx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zn2}, "a list of SVE vector registers"}, + {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Znx4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zn4}, "a list of SVE vector registers"}, {AARCH64_OPND_CLASS_SVE_REG, "SME_ZAda_2b", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_ZAda_2b}, "an SME ZA tile ZA0-ZA3"}, {AARCH64_OPND_CLASS_SVE_REG, "SME_ZAda_3b", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_ZAda_3b}, "an SME ZA tile ZA0-ZA7"}, {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_src", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_22,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_5}, "an SME horizontal or vertical vector access register"}, + {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_srcxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_V,FLD_SME_Rv,FLD_imm3_5}, "an SME horizontal or vertical vector access register"}, {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_dest", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_22,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_0}, "an SME horizontal or vertical vector access register"}, + {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_destxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_V,FLD_SME_Rv,FLD_imm3_0}, "an SME horizontal or vertical vector access register"}, {AARCH64_OPND_CLASS_PRED_REG, "SME_Pm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Pm}, "an SVE predicate register"}, {AARCH64_OPND_CLASS_SVE_REG, "SME_list_of_64bit_tiles", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_zero_mask}, "a list of 64-bit ZA element tiles"}, {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_ldstr", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_22,FLD_index2,FLD_SME_V,FLD_SME_Rv,FLD_imm4_0}, "an SME horizontal or vertical vector access register"}, + {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_off3_0", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rv,FLD_imm3_0}, "ZA array"}, + {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_off3_5", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rv,FLD_imm3_5}, "ZA array"}, {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_off4", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rv,FLD_imm4_0}, "ZA array"}, {AARCH64_OPND_CLASS_ADDRESS, "SME_ADDR_RI_U4xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_imm4_0}, "memory offset"}, {AARCH64_OPND_CLASS_ADDRESS, "SME_SM_ZA", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm}, "streaming mode"}, diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 1944b8fe87d..b3308955cc8 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -227,6 +227,10 @@ const aarch64_field fields[] = { 15, 1 }, /* SME_V: (horizontal / vertical tiles), bit 15. */ { 0, 2 }, /* SME_ZAda_2b: tile ZA0-ZA3. */ { 0, 3 }, /* SME_ZAda_3b: tile ZA0-ZA7. */ + { 1, 4 }, /* SME_Zdn2: Z0-Z31, multiple of 2, bits [4:1]. */ + { 2, 3 }, /* SME_Zdn4: Z0-Z31, multiple of 4, bits [4:2]. */ + { 6, 4 }, /* SME_Zn2: Z0-Z31, multiple of 2, bits [9:6]. */ + { 7, 3 }, /* SME_Zn4: Z0-Z31, multiple of 4, bits [9:7]. */ { 23, 1 }, /* SME_i1: immediate field, bit 23. */ { 22, 2 }, /* SME_size_22: size<1>, size<0> class field, [23:22]. */ { 22, 1 }, /* SME_tszh: immediate and qualifier field, bit 22. */ @@ -296,6 +300,8 @@ const aarch64_field fields[] = { 0, 4 }, /* cond2: condition in truly conditional-executed inst. */ { 5, 5 }, /* defgh: d:e:f:g:h bits in AdvSIMD modified immediate. */ { 21, 2 }, /* hw: in move wide constant instructions. */ + { 0, 3 }, /* imm3_0: general immediate in bits [2:0]. */ + { 5, 3 }, /* imm3_5: general immediate in bits [7:5]. */ { 10, 3 }, /* imm3_10: in add/sub extended reg instructions. */ { 0, 4 }, /* imm4_0: in rmif instructions. */ { 5, 4 }, /* imm4_5: in SME instructions. */ @@ -1546,6 +1552,10 @@ check_za_access (const aarch64_opnd_info *opnd, set_other_error (mismatch_detail, idx, _("expected a selection register in the" " range w12-w15")); + else if (min_wreg == 8) + set_other_error (mismatch_detail, idx, + _("expected a selection register in the" + " range w8-w11")); else abort (); return false; @@ -1574,6 +1584,12 @@ check_za_access (const aarch64_opnd_info *opnd, set_other_error (mismatch_detail, idx, _("expected a single offset rather than" " a range")); + else if (range_size == 2) + set_other_error (mismatch_detail, idx, + _("expected a range of two offsets")); + else if (range_size == 4) + set_other_error (mismatch_detail, idx, + _("expected a range of four offsets")); else abort (); return false; @@ -1715,9 +1731,33 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, break; case AARCH64_OPND_CLASS_SVE_REGLIST: - num = get_opcode_dependent_value (opcode); - if (!check_reglist (opnd, mismatch_detail, idx, num, 1)) - return 0; + switch (type) + { + case AARCH64_OPND_SME_Zdnx2: + case AARCH64_OPND_SME_Zdnx4: + case AARCH64_OPND_SME_Znx2: + case AARCH64_OPND_SME_Znx4: + num = get_operand_specific_data (&aarch64_operands[type]); + if (!check_reglist (opnd, mismatch_detail, idx, num, 1)) + return 0; + if ((opnd->reglist.first_regno % num) != 0) + { + set_other_error (mismatch_detail, idx, + _("start register out of range")); + return 0; + } + break; + + case AARCH64_OPND_SVE_ZnxN: + case AARCH64_OPND_SVE_ZtxN: + num = get_opcode_dependent_value (opcode); + if (!check_reglist (opnd, mismatch_detail, idx, num, 1)) + return 0; + break; + + default: + abort (); + } break; case AARCH64_OPND_CLASS_ZA_ACCESS: @@ -1739,6 +1779,25 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, return 0; break; + case AARCH64_OPND_SME_ZA_array_off3_0: + case AARCH64_OPND_SME_ZA_array_off3_5: + if (!check_za_access (opnd, mismatch_detail, idx, 8, 7, 1, + get_opcode_dependent_value (opcode))) + return 0; + break; + + case AARCH64_OPND_SME_ZA_HV_idx_srcxN: + case AARCH64_OPND_SME_ZA_HV_idx_destxN: + size = aarch64_get_qualifier_esize (opnd->qualifier); + num = get_opcode_dependent_value (opcode); + max_value = 16 / num / size; + if (max_value > 0) + max_value -= 1; + if (!check_za_access (opnd, mismatch_detail, idx, + 12, max_value, num, 0)) + return 0; + break; + default: abort (); } @@ -3709,6 +3768,10 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, case AARCH64_OPND_SVE_ZnxN: case AARCH64_OPND_SVE_ZtxN: + case AARCH64_OPND_SME_Zdnx2: + case AARCH64_OPND_SME_Zdnx4: + case AARCH64_OPND_SME_Znx2: + case AARCH64_OPND_SME_Znx4: print_register_list (buf, size, opnd, "z", styler); break; @@ -3732,7 +3795,9 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, break; case AARCH64_OPND_SME_ZA_HV_idx_src: + case AARCH64_OPND_SME_ZA_HV_idx_srcxN: case AARCH64_OPND_SME_ZA_HV_idx_dest: + case AARCH64_OPND_SME_ZA_HV_idx_destxN: case AARCH64_OPND_SME_ZA_HV_idx_ldstr: snprintf (buf, size, "%s%s[%s, %s%s%s%s%s]%s", opnd->type == AARCH64_OPND_SME_ZA_HV_idx_ldstr ? "{" : "", @@ -3760,9 +3825,15 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, print_sme_za_list (buf, size, opnd->reg.regno, styler); break; + case AARCH64_OPND_SME_ZA_array_off3_0: + case AARCH64_OPND_SME_ZA_array_off3_5: case AARCH64_OPND_SME_ZA_array_off4: snprintf (buf, size, "%s[%s, %s%s%s%s%s]", - style_reg (styler, "za"), + style_reg (styler, "za%s%s", + opnd->qualifier == AARCH64_OPND_QLF_NIL ? "" : ".", + (opnd->qualifier == AARCH64_OPND_QLF_NIL + ? "" + : aarch64_get_qualifier_name (opnd->qualifier))), style_reg (styler, "w%d", opnd->indexed_za.index.regno), style_imm (styler, "%" PRIi64, opnd->indexed_za.index.imm), opnd->indexed_za.index.countm1 ? ":" : "", diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h index e142ae6ee76..c604af5124c 100644 --- a/opcodes/aarch64-opc.h +++ b/opcodes/aarch64-opc.h @@ -55,6 +55,10 @@ enum aarch64_field_kind FLD_SME_V, FLD_SME_ZAda_2b, FLD_SME_ZAda_3b, + FLD_SME_Zdn2, + FLD_SME_Zdn4, + FLD_SME_Zn2, + FLD_SME_Zn4, FLD_SME_i1, FLD_SME_size_22, FLD_SME_tszh, @@ -124,6 +128,8 @@ enum aarch64_field_kind FLD_cond2, FLD_defgh, FLD_hw, + FLD_imm3_0, + FLD_imm3_5, FLD_imm3_10, FLD_imm4_0, FLD_imm4_5, diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 72f3c3ced88..93e124906d8 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -2477,6 +2477,9 @@ static const aarch64_feature_set aarch64_feature_sme_f64f64 = static const aarch64_feature_set aarch64_feature_sme_i16i64 = AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | AARCH64_FEATURE_SME | AARCH64_FEATURE_SME_I16I64, 0); +static const aarch64_feature_set aarch64_feature_sme2 = + AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | AARCH64_FEATURE_SME + | AARCH64_FEATURE_SME2, 0); static const aarch64_feature_set aarch64_feature_v8_6 = AARCH64_FEATURE (AARCH64_FEATURE_V8_6, 0); static const aarch64_feature_set aarch64_feature_v8_7 = @@ -2545,6 +2548,7 @@ static const aarch64_feature_set aarch64_feature_cssc = #define SME &aarch64_feature_sme #define SME_F64F64 &aarch64_feature_sme_f64f64 #define SME_I16I64 &aarch64_feature_sme_i16i64 +#define SME2 &aarch64_feature_sme2 #define ARMV8_6 &aarch64_feature_v8_6 #define ARMV8_6_SVE &aarch64_feature_v8_6 #define BFLOAT16_SVE &aarch64_feature_bfloat16_sve @@ -2656,6 +2660,9 @@ static const aarch64_feature_set aarch64_feature_cssc = #define SME_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SME, OPS, QUALS, \ F_STRICT | FLAGS, CONSTRAINTS, TIED, NULL } +#define SME2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ + { NAME, OPCODE, MASK, CLASS, OP, SME2, OPS, QUALS, \ + F_STRICT | FLAGS, 0, TIED, NULL } #define SVE2BITPERM_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SVE2_BITPERM, OPS, QUALS, \ FLAGS | F_STRICT, 0, TIED, NULL } @@ -5278,6 +5285,24 @@ const struct aarch64_opcode aarch64_opcode_table[] = SME_INSN ("psel", 0x25204000, 0xff20c210, sme_psel, 0, OP3 (SVE_Pd, SVE_Pg4_10, SME_PnT_Wm_imm), OP_SVE_NN_BHSD, 0, 0), SME_INSN ("psel", 0x25204000, 0xff20c210, sme_psel, 0, OP3 (SVE_PNd, SVE_PNg4_10, SME_PnT_Wm_imm), OP_SVE_NN_BHSD, 0, 0), + /* SME2 extensions to SME. */ + SME2_INSN ("mov", 0xc0060800, 0xffff9f01, sme2_mov, 0, OP2 (SME_Zdnx2, SME_ZA_array_off3_5), OP_SVE_VV_BHSD, F_OD (2), 0), + SME2_INSN ("mov", 0xc0060c00, 0xffff9f03, sme2_mov, 0, OP2 (SME_Zdnx4, SME_ZA_array_off3_5), OP_SVE_VV_BHSD, F_OD (4), 0), + SME2_INSN ("mov", 0xc0060000, 0xff3f1f01, sme_size_22, 0, OP2 (SME_Zdnx2, SME_ZA_HV_idx_srcxN), OP_SVE_VV_BHSDQ, F_OD (2), 0), + SME2_INSN ("mov", 0xc0060400, 0xff3f1f03, sme_size_22, 0, OP2 (SME_Zdnx4, SME_ZA_HV_idx_srcxN), OP_SVE_VV_BHSDQ, F_OD (4), 0), + SME2_INSN ("mov", 0xc0040800, 0xffff9c38, sme2_mov, 0, OP2 (SME_ZA_array_off3_0, SME_Znx2), OP_SVE_VV_BHSD, F_OD (2), 0), + SME2_INSN ("mov", 0xc0040c00, 0xffff9c78, sme2_mov, 0, OP2 (SME_ZA_array_off3_0, SME_Znx4), OP_SVE_VV_BHSD, F_OD (4), 0), + SME2_INSN ("mov", 0xc0040000, 0xff3f1c38, sme_size_22, 0, OP2 (SME_ZA_HV_idx_destxN, SME_Znx2), OP_SVE_VV_BHSDQ, F_OD (2), 0), + SME2_INSN ("mov", 0xc0040400, 0xff3f1c78, sme_size_22, 0, OP2 (SME_ZA_HV_idx_destxN, SME_Znx4), OP_SVE_VV_BHSDQ, F_OD (4), 0), + SME2_INSN ("mova", 0xc0060800, 0xffff9f01, sme2_mov, 0, OP2 (SME_Zdnx2, SME_ZA_array_off3_5), OP_SVE_VV_BHSD, F_OD (2), 0), + SME2_INSN ("mova", 0xc0060c00, 0xffff9f03, sme2_mov, 0, OP2 (SME_Zdnx4, SME_ZA_array_off3_5), OP_SVE_VV_BHSD, F_OD (4), 0), + SME2_INSN ("mova", 0xc0060000, 0xff3f1f01, sme_size_22, 0, OP2 (SME_Zdnx2, SME_ZA_HV_idx_srcxN), OP_SVE_VV_BHSDQ, F_OD (2), 0), + SME2_INSN ("mova", 0xc0060400, 0xff3f1f03, sme_size_22, 0, OP2 (SME_Zdnx4, SME_ZA_HV_idx_srcxN), OP_SVE_VV_BHSDQ, F_OD (4), 0), + SME2_INSN ("mova", 0xc0040800, 0xffff9c38, sme2_mov, 0, OP2 (SME_ZA_array_off3_0, SME_Znx2), OP_SVE_VV_BHSD, F_OD (2), 0), + SME2_INSN ("mova", 0xc0040c00, 0xffff9c78, sme2_mov, 0, OP2 (SME_ZA_array_off3_0, SME_Znx4), OP_SVE_VV_BHSD, F_OD (4), 0), + SME2_INSN ("mova", 0xc0040000, 0xff3f1c38, sme_size_22, 0, OP2 (SME_ZA_HV_idx_destxN, SME_Znx2), OP_SVE_VV_BHSDQ, F_OD (2), 0), + SME2_INSN ("mova", 0xc0040400, 0xff3f1c78, sme_size_22, 0, OP2 (SME_ZA_HV_idx_destxN, SME_Znx4), OP_SVE_VV_BHSDQ, F_OD (4), 0), + /* SIMD Dot Product (optional in v8.2-A). */ DOT_INSN ("udot", 0x2e009400, 0xbf20fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ), DOT_INSN ("sdot", 0xe009400, 0xbf20fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ), @@ -5917,6 +5942,14 @@ const struct aarch64_opcode aarch64_opcode_table[] = "an SVE vector register") \ Y(SVE_REGLIST, sve_reglist, "SVE_ZtxN", 0, F(FLD_SVE_Zt), \ "a list of SVE vector registers") \ + Y(SVE_REGLIST, sve_aligned_reglist, "SME_Zdnx2", 2 << OPD_F_OD_LSB, \ + F(FLD_SME_Zdn2), "a list of SVE vector registers") \ + Y(SVE_REGLIST, sve_aligned_reglist, "SME_Zdnx4", 4 << OPD_F_OD_LSB, \ + F(FLD_SME_Zdn4), "a list of SVE vector registers") \ + Y(SVE_REGLIST, sve_aligned_reglist, "SME_Znx2", 2 << OPD_F_OD_LSB, \ + F(FLD_SME_Zn2), "a list of SVE vector registers") \ + Y(SVE_REGLIST, sve_aligned_reglist, "SME_Znx4", 4 << OPD_F_OD_LSB, \ + F(FLD_SME_Zn4), "a list of SVE vector registers") \ Y(SVE_REG, regno, "SME_ZAda_2b", 0, F(FLD_SME_ZAda_2b), \ "an SME ZA tile ZA0-ZA3") \ Y(SVE_REG, regno, "SME_ZAda_3b", 0, F(FLD_SME_ZAda_3b), \ @@ -5924,9 +5957,15 @@ const struct aarch64_opcode aarch64_opcode_table[] = Y(ZA_ACCESS, sme_za_hv_tiles, "SME_ZA_HV_idx_src", 0, \ F(FLD_SME_size_22,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_5), \ "an SME horizontal or vertical vector access register") \ + Y(ZA_ACCESS, sme_za_hv_tiles_range, "SME_ZA_HV_idx_srcxN", 0, \ + F(FLD_SME_V,FLD_SME_Rv,FLD_imm3_5), \ + "an SME horizontal or vertical vector access register") \ Y(ZA_ACCESS, sme_za_hv_tiles, "SME_ZA_HV_idx_dest", 0, \ F(FLD_SME_size_22,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_0), \ "an SME horizontal or vertical vector access register") \ + Y(ZA_ACCESS, sme_za_hv_tiles_range, "SME_ZA_HV_idx_destxN", 0, \ + F(FLD_SME_V,FLD_SME_Rv,FLD_imm3_0), \ + "an SME horizontal or vertical vector access register") \ Y(PRED_REG, regno, "SME_Pm", 0, F(FLD_SME_Pm), \ "an SVE predicate register") \ Y(SVE_REG, imm, "SME_list_of_64bit_tiles", 0, \ @@ -5934,6 +5973,10 @@ const struct aarch64_opcode aarch64_opcode_table[] = Y(ZA_ACCESS, sme_za_hv_tiles, "SME_ZA_HV_idx_ldstr", 0, \ F(FLD_SME_size_22,FLD_index2,FLD_SME_V,FLD_SME_Rv,FLD_imm4_0), \ "an SME horizontal or vertical vector access register") \ + Y(ZA_ACCESS, sme_za_array, "SME_ZA_array_off3_0", 0, \ + F(FLD_SME_Rv,FLD_imm3_0), "ZA array") \ + Y(ZA_ACCESS, sme_za_array, "SME_ZA_array_off3_5", 0, \ + F(FLD_SME_Rv,FLD_imm3_5), "ZA array") \ Y(ZA_ACCESS, sme_za_array, "SME_ZA_array_off4", 0, \ F(FLD_SME_Rv,FLD_imm4_0), "ZA array") \ Y(ADDRESS, sme_addr_ri_u4xvl, "SME_ADDR_RI_U4xVL", 0 << OPD_F_OD_LSB, \ From patchwork Thu Mar 30 10:26:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 77071 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1031958vqo; Thu, 30 Mar 2023 03:49:38 -0700 (PDT) X-Google-Smtp-Source: AKy350YCpJ8CmpxL/KN3D0HUjRNaZk+XXA1S4yd79kB0+fc88Jr1LJLUSyjyttRc/C8BRWtBOeyQ X-Received: by 2002:a17:906:aad3:b0:933:be1:8f4f with SMTP id kt19-20020a170906aad300b009330be18f4fmr23403225ejb.9.1680173378317; Thu, 30 Mar 2023 03:49:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680173378; cv=none; d=google.com; s=arc-20160816; b=zENYgLcMmXLiHt66iyi5T8neU+SjUmnvZ6fmd204r82A5kfPx4Zq3puQ/44p1gSnwM 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[8.43.85.97]) by mx.google.com with ESMTPS id um7-20020a170906cf8700b0092bc3318c92si32586338ejb.682.2023.03.30.03.49.37 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Mar 2023 03:49:38 -0700 (PDT) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=X7ssiqnH; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 95F8F395200B for ; Thu, 30 Mar 2023 10:35:51 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 95F8F395200B DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1680172551; bh=hK4L+wds7SS352TYVYWU2g8A/hZglkxlDGgHEdBpiW0=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=X7ssiqnHEhoIIEPdf0gWtrDw6Nexs0UjhDi9PVoBocDcYq1jmYynLs/048d3T8pq5 Mw0ZU0uooCbgRWywjtRJg90w3REg2SVUMMXve2Z/P28dIsXshR9vt29xduB3UdjMP1 MiZaHdN/bfFnjlPRkSvatGi7zymHWrlUUUNOymTM= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 82CC93896C10 for ; Thu, 30 Mar 2023 10:27:01 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 82CC93896C10 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B30701650; Thu, 30 Mar 2023 03:27:45 -0700 (PDT) Received: from e121540-lin.manchester.arm.com (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E9A833F663; Thu, 30 Mar 2023 03:27:00 -0700 (PDT) To: binutils@sourceware.org Cc: Richard Sandiford Subject: [PATCH 10/31] aarch64: Add the SME2 ZT0 instructions Date: Thu, 30 Mar 2023 11:26:25 +0100 Message-Id: <20230330102646.3327818-11-richard.sandiford@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230330102646.3327818-1-richard.sandiford@arm.com> References: <20230330102646.3327818-1-richard.sandiford@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-31.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, SCC_5_SHORT_WORD_LINES, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Richard Sandiford via Binutils From: Richard Sandiford Reply-To: Richard Sandiford Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761789480445613477?= X-GMAIL-MSGID: =?utf-8?q?1761789480445613477?= SME2 adds lookup table instructions for quantisation. They use a new lookup table register called ZT0. LUTI2 takes an unsuffixed SVE vector index of the form Zn[], which is the first time that this syntax has been used. --- gas/config/tc-aarch64.c | 73 +- gas/testsuite/gas/aarch64/sme-4-illegal.l | 6 +- gas/testsuite/gas/aarch64/sme2-8-invalid.d | 3 + gas/testsuite/gas/aarch64/sme2-8-invalid.l | 208 +++++ gas/testsuite/gas/aarch64/sme2-8-invalid.s | 116 +++ gas/testsuite/gas/aarch64/sme2-8-noarch.d | 3 + gas/testsuite/gas/aarch64/sme2-8-noarch.l | 104 +++ gas/testsuite/gas/aarch64/sme2-8.d | 112 +++ gas/testsuite/gas/aarch64/sme2-8.s | 124 +++ gas/testsuite/gas/aarch64/sve-invalid.l | 8 + gas/testsuite/gas/aarch64/sve-invalid.s | 1 + include/opcode/aarch64.h | 11 + opcodes/aarch64-asm-2.c | 25 +- opcodes/aarch64-asm.c | 12 + opcodes/aarch64-dis-2.c | 902 ++++++++++++--------- opcodes/aarch64-dis.c | 15 + opcodes/aarch64-opc-2.c | 9 + opcodes/aarch64-opc.c | 59 +- opcodes/aarch64-opc.h | 19 +- opcodes/aarch64-tbl.h | 42 + 20 files changed, 1443 insertions(+), 409 deletions(-) create mode 100644 gas/testsuite/gas/aarch64/sme2-8-invalid.d create mode 100644 gas/testsuite/gas/aarch64/sme2-8-invalid.l create mode 100644 gas/testsuite/gas/aarch64/sme2-8-invalid.s create mode 100644 gas/testsuite/gas/aarch64/sme2-8-noarch.d create mode 100644 gas/testsuite/gas/aarch64/sme2-8-noarch.l create mode 100644 gas/testsuite/gas/aarch64/sme2-8.d create mode 100644 gas/testsuite/gas/aarch64/sme2-8.s diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index a433925e320..652fd4e6ff3 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -312,6 +312,7 @@ struct reloc_entry BASIC_REG_TYPE(ZAT) /* za[0-15] (ZA tile) */ \ BASIC_REG_TYPE(ZATH) /* za[0-15]h (ZA tile horizontal slice) */ \ BASIC_REG_TYPE(ZATV) /* za[0-15]v (ZA tile vertical slice) */ \ + BASIC_REG_TYPE(ZT0) /* zt0 */ \ /* Typecheck: any 64-bit int reg (inc SP exc XZR). */ \ MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \ /* Typecheck: same, plus SVE registers. */ \ @@ -483,11 +484,11 @@ get_reg_expected_msg (unsigned int mask, unsigned int seen) if (mask == reg_type_masks[REG_TYPE_VZP]) return N_("expected a vector or predicate register at operand %d"); - /* ZA-related registers. */ + /* SME-related registers. */ if (mask == reg_type_masks[REG_TYPE_ZA]) return N_("expected a ZA array vector at operand %d"); - if (mask == reg_type_masks[REG_TYPE_ZA_ZAT]) - return N_("expected 'za' or a ZA tile at operand %d"); + if (mask == (reg_type_masks[REG_TYPE_ZA_ZAT] | reg_type_masks[REG_TYPE_ZT0])) + return N_("expected ZT0 or a ZA mask at operand %d"); if (mask == reg_type_masks[REG_TYPE_ZAT]) return N_("expected a ZA tile at operand %d"); if (mask == reg_type_masks[REG_TYPE_ZATHV]) @@ -1279,7 +1280,10 @@ parse_typed_reg (char **ccp, aarch64_reg_type type, if (!(flags & PTR_FULL_REG) && skip_past_char (&str, '[')) { /* Reject Sn[index] syntax. */ - if (reg->type != REG_TYPE_PN && !is_typed_vecreg) + if (reg->type != REG_TYPE_Z + && reg->type != REG_TYPE_PN + && reg->type != REG_TYPE_ZT0 + && !is_typed_vecreg) { first_error (_("this type of register can't be indexed")); return NULL; @@ -6722,6 +6726,12 @@ parse_operands (char *str, const aarch64_opcode *opcode) case AARCH64_OPND_SVE_Zm4_11_INDEX: case AARCH64_OPND_SVE_Zm4_INDEX: case AARCH64_OPND_SVE_Zn_INDEX: + case AARCH64_OPND_SME_Zn_INDEX1_16: + case AARCH64_OPND_SME_Zn_INDEX2_15: + case AARCH64_OPND_SME_Zn_INDEX2_16: + case AARCH64_OPND_SME_Zn_INDEX3_14: + case AARCH64_OPND_SME_Zn_INDEX3_15: + case AARCH64_OPND_SME_Zn_INDEX4_14: reg_type = REG_TYPE_Z; goto vector_reg_index; @@ -6735,14 +6745,23 @@ parse_operands (char *str, const aarch64_opcode *opcode) reg = aarch64_reg_parse (&str, reg_type, &vectype); if (!reg) goto failure; - if (vectype.type == NT_invtype || !(vectype.defined & NTA_HASINDEX)) + if (!(vectype.defined & NTA_HASINDEX)) goto failure; + if (reg->type == REG_TYPE_Z && vectype.type == NT_invtype) + /* Unqualified Zn[index] is allowed in LUTI2 instructions. */ + info->qualifier = AARCH64_OPND_QLF_NIL; + else + { + if (vectype.type == NT_invtype) + goto failure; + info->qualifier = vectype_to_qualifier (&vectype); + if (info->qualifier == AARCH64_OPND_QLF_NIL) + goto failure; + } + info->reglane.regno = reg->number; info->reglane.index = vectype.index; - info->qualifier = vectype_to_qualifier (&vectype); - if (info->qualifier == AARCH64_OPND_QLF_NIL) - goto failure; break; case AARCH64_OPND_SVE_ZnxN: @@ -7740,6 +7759,39 @@ parse_operands (char *str, const aarch64_opcode *opcode) goto failure; break; + case AARCH64_OPND_SME_ZT0: + po_reg_or_fail (REG_TYPE_ZT0); + break; + + case AARCH64_OPND_SME_ZT0_INDEX: + reg = aarch64_reg_parse (&str, REG_TYPE_ZT0, &vectype); + if (!reg || vectype.type != NT_invtype) + goto failure; + if (!(vectype.defined & NTA_HASINDEX)) + { + set_syntax_error (_("missing register index")); + goto failure; + } + info->imm.value = vectype.index; + break; + + case AARCH64_OPND_SME_ZT0_LIST: + if (*str != '{') + { + set_expected_reglist_error (REG_TYPE_ZT0, parse_reg (&str)); + goto failure; + } + str++; + if (!parse_typed_reg (&str, REG_TYPE_ZT0, &vectype, PTR_IN_REGLIST)) + goto failure; + if (*str != '}') + { + set_syntax_error (_("expected '}' after ZT0")); + goto failure; + } + str++; + break; + case AARCH64_OPND_SME_PNn3_INDEX1: case AARCH64_OPND_SME_PNn3_INDEX2: reg = aarch64_reg_parse (&str, REG_TYPE_PN, &vectype); @@ -8462,7 +8514,10 @@ static const reg_entry reg_names[] = { REGSET16S (za, h, ZATH), REGSET16S (ZA, H, ZATH), /* SME ZA tile registers (vertical slice). */ - REGSET16S (za, v, ZATV), REGSET16S (ZA, V, ZATV) + REGSET16S (za, v, ZATV), REGSET16S (ZA, V, ZATV), + + /* SME2 ZT0. */ + REGDEF (zt0, 0, ZT0), REGDEF (ZT0, 0, ZT0) }; #undef REGDEF diff --git a/gas/testsuite/gas/aarch64/sme-4-illegal.l b/gas/testsuite/gas/aarch64/sme-4-illegal.l index 86e315476dd..a9e98524067 100644 --- a/gas/testsuite/gas/aarch64/sme-4-illegal.l +++ b/gas/testsuite/gas/aarch64/sme-4-illegal.l @@ -22,11 +22,11 @@ [^:]*:[0-9]+: Error: syntax error in register list at operand 1 -- `zero {za,}' [^:]*:[0-9]+: Error: unexpected character `}' in element size at operand 1 -- `zero {za.}' [^:]*:[0-9]+: Error: expected '}' at operand 1 -- `zero {za-}' -[^:]*:[0-9]+: Error: expected 'za' or a ZA tile at operand 1 -- `zero {za_}' +[^:]*:[0-9]+: Error: expected ZT0 or a ZA mask at operand 1 -- `zero {za_}' [^:]*:[0-9]+: Error: expected '}' at operand 1 -- `zero {za#}' -[^:]*:[0-9]+: Error: expected 'za' or a ZA tile at operand 1 -- `zero {zaX}' +[^:]*:[0-9]+: Error: expected ZT0 or a ZA mask at operand 1 -- `zero {zaX}' [^:]*:[0-9]+: Error: missing ZA tile size at operand 1 -- `zero {za0}' -[^:]*:[0-9]+: Error: expected 'za' or a ZA tile at operand 1 -- `zero {zax}' +[^:]*:[0-9]+: Error: expected ZT0 or a ZA mask at operand 1 -- `zero {zax}' [^:]*:[0-9]+: Error: expected '}' at operand 1 -- `zero {za{}' [^:]*:[0-9]+: Error: unexpected characters following instruction at operand 1 -- `zero {za}}' [^:]*:[0-9]+: Error: ZA tile masks do not operate at .Q granularity at operand 1 -- `zero {za0\.q}' diff --git a/gas/testsuite/gas/aarch64/sme2-8-invalid.d b/gas/testsuite/gas/aarch64/sme2-8-invalid.d new file mode 100644 index 00000000000..d9f587d6019 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-8-invalid.d @@ -0,0 +1,3 @@ +#as: -march=armv8-a +#source: sme2-8-invalid.s +#error_output: sme2-8-invalid.l diff --git a/gas/testsuite/gas/aarch64/sme2-8-invalid.l b/gas/testsuite/gas/aarch64/sme2-8-invalid.l new file mode 100644 index 00000000000..afea8bb6735 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-8-invalid.l @@ -0,0 +1,208 @@ +[^ :]+: Assembler messages: +[^ :]+:[0-9]+: Error: expected '{' at operand 1 -- `zero 0' +[^ :]+:[0-9]+: Error: expected '{' at operand 1 -- `zero zt0' +[^ :]+:[0-9]+: Error: syntax error in register list at operand 1 -- `zero {' +[^ :]+:[0-9]+: Error: expected ZT0 or a ZA mask at operand 1 -- `zero {foo}' +[^ :]+:[0-9]+: Error: expected ZT0 or a ZA mask at operand 1 -- `zero {zt}' +[^ :]+:[0-9]+: Error: expected ZT0 or a ZA mask at operand 1 -- `zero {x0}' +[^ :]+:[0-9]+: Error: expected ZT0 or a ZA mask at operand 1 -- `zero {z0}' +[^ :]+:[0-9]+: Error: expected '}' after ZT0 at operand 1 -- `zero {zt0' +[^ :]+:[0-9]+: Error: expected '}' after ZT0 at operand 1 -- `zero {zt0\.b}' +[^ :]+:[0-9]+: Error: expected '}' after ZT0 at operand 1 -- `zero {zt0,zt0}' +[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `movt 0,zt0\[0\]' +[^ :]+:[0-9]+: Error: expected a register at operand 2 -- `movt x0,0' +[^ :]+:[0-9]+: Error: missing register index at operand 1 -- `movt zt0,x0' +[^ :]+:[0-9]+: Error: unexpected register type at operand 1 -- `movt za\[0\],x0' +[^ :]+:[0-9]+: Error: unexpected register type at operand 1 -- `movt za0\[0\],x0' +[^ :]+:[0-9]+: Error: bad expression at operand 1 -- `movt zt0\[#0\],x0' +[^ :]+:[0-9]+: Error: register element index out of range 0 to 56 at operand 1 -- `movt zt0\[-1\],x0' +[^ :]+:[0-9]+: Error: byte index must be a multiple of 8 at operand 1 -- `movt zt0\[1\],x0' +[^ :]+:[0-9]+: Error: byte index must be a multiple of 8 at operand 1 -- `movt zt0\[2\],x0' +[^ :]+:[0-9]+: Error: byte index must be a multiple of 8 at operand 1 -- `movt zt0\[4\],x0' +[^ :]+:[0-9]+: Error: byte index must be a multiple of 8 at operand 1 -- `movt zt0\[7\],x0' +[^ :]+:[0-9]+: Error: byte index must be a multiple of 8 at operand 1 -- `movt zt0\[49\],x0' +[^ :]+:[0-9]+: Error: byte index must be a multiple of 8 at operand 1 -- `movt zt0\[50\],x0' +[^ :]+:[0-9]+: Error: byte index must be a multiple of 8 at operand 1 -- `movt zt0\[52\],x0' +[^ :]+:[0-9]+: Error: register element index out of range 0 to 56 at operand 1 -- `movt zt0\[57\],x0' +[^ :]+:[0-9]+: Error: register element index out of range 0 to 56 at operand 1 -- `movt zt0\[64\],x0' +[^ :]+:[0-9]+: Error: register element index out of range 0 to 56 at operand 1 -- `movt zt0\[1<<32\],x0' +[^ :]+:[0-9]+: Error: missing register index at operand 1 -- `movt zt0\.b\[0\],x0' +[^ :]+:[0-9]+: Error: missing register index at operand 1 -- `movt zt0/z\[0\],x0' +[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `movt zt0\[0\],sp' +[^ :]+:[0-9]+: Error: operand mismatch -- `movt zt0\[0\],w0' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: movt zt0\[0\], x0 +[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `movt zt0\[0\],wsp' +[^ :]+:[0-9]+: Error: operand mismatch -- `movt zt0\[0\],wzr' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: movt zt0\[0\], xzr +[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `movt zt0\[0\],0' +[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `ldr 0,\[x0\]' +[^ :]+:[0-9]+: Error: invalid addressing mode at operand 2 -- `ldr zt0,0' +[^ :]+:[0-9]+: Error: operand 2 must be an address with base register \(no offset\) -- `ldr zt0,\[x0,#0\]' +[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `ldr Zt0,\[x0\]' +[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `ldr zT0,\[x0\]' +[^ :]+:[0-9]+: Error: '\]' expected at operand 2 -- `ldr zt0,\[x0,#0,mul vl\]' +[^ :]+:[0-9]+: Error: expected a 64-bit base register at operand 2 -- `ldr zt0,\[w0\]' +[^ :]+:[0-9]+: Error: missing offset in the pre-indexed address at operand 2 -- `ldr zt0,\[x0\]!' +[^ :]+:[0-9]+: Error: invalid base register at operand 2 -- `ldr zt0,\[xzr\]' +[^ :]+:[0-9]+: Error: expected a 64-bit base register at operand 2 -- `ldr zt0,\[wsp\]' +[^ :]+:[0-9]+: Error: invalid addressing mode at operand 2 -- `ldr zt0,\[x0,xzr\]' +[^ :]+:[0-9]+: Error: invalid addressing mode at operand 2 -- `ldr zt0,\[x1,x2\]' +[^ :]+:[0-9]+: Error: register element index out of range 0 to 15 at operand 3 -- `luti2 z0\.b,zt0,z0\[-1\]' +[^ :]+:[0-9]+: Error: register element index out of range 0 to 15 at operand 3 -- `luti2 z0\.b,zt0,z0\[16\]' +[^ :]+:[0-9]+: Error: operand mismatch -- `luti2 z0\.b,zt0,z0\.b\[0\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: luti2 z0\.b, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: luti2 z0\.h, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: luti2 z0\.s, zt0, z0\[0\] +[^ :]+:[0-9]+: Error: operand mismatch -- `luti2 z0,zt0,z0\[0\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: luti2 z0\.b, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: luti2 z0\.h, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: luti2 z0\.s, zt0, z0\[0\] +[^ :]+:[0-9]+: Error: operand mismatch -- `luti2 z0\.d,zt0,z0\[0\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: luti2 z0\.b, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: luti2 z0\.h, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: luti2 z0\.s, zt0, z0\[0\] +[^ :]+:[0-9]+: Error: operand mismatch -- `luti2 z0\.q,zt0,z0\[0\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: luti2 z0\.b, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: luti2 z0\.h, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: luti2 z0\.s, zt0, z0\[0\] +[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `luti2 z0\.b,zt0,zt0' +[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `luti2 0,zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: expected a register at operand 2 -- `luti2 z0\.b,0,z0\[0\]' +[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `luti2 z0\.b,zt0,0' +[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `luti2 {z1\.b-z2\.b},zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: unexpected register type at operand 2 -- `luti2 {z0\.b-z1\.b},z0,z0\[0\]' +[^ :]+:[0-9]+: Error: unexpected register type at operand 2 -- `luti2 {z0\.b-z1\.b},za,z0\[0\]' +[^ :]+:[0-9]+: Error: operand mismatch -- `luti2 {z0\.h-z1\.h},zt0,z0\.h\[0\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: luti2 {z0\.h-z1\.h}, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: luti2 {z0\.b-z1\.b}, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: luti2 {z0\.s-z1\.s}, zt0, z0\[0\] +[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `luti2 {z0\.h-z1\.h},zt0,z0\[-1\]' +[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `luti2 {z0\.h-z1\.h},zt0,z0\[8\]' +[^ :]+:[0-9]+: Error: operand mismatch -- `luti2 {z0\.d-z1\.d},zt0,z0\[0\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: luti2 {z0\.b-z1\.b}, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: luti2 {z0\.h-z1\.h}, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: luti2 {z0\.s-z1\.s}, zt0, z0\[0\] +[^ :]+:[0-9]+: Error: operand mismatch -- `luti2 {z0\.q-z1\.q},zt0,z0\[0\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: luti2 {z0\.b-z1\.b}, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: luti2 {z0\.h-z1\.h}, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: luti2 {z0\.s-z1\.s}, zt0, z0\[0\] +[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `luti2 {z1\.s-z4\.s},zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `luti2 {z2\.s-z5\.s},zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `luti2 {z3\.s-z6\.s},zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: unexpected register type at operand 2 -- `luti2 {z0\.s-z3\.s},z0,z0\[0\]' +[^ :]+:[0-9]+: Error: unexpected register type at operand 2 -- `luti2 {z0\.b-z3\.b},za,z0\[0\]' +[^ :]+:[0-9]+: Error: operand mismatch -- `luti2 {z0\.b-z3\.b},zt0,z0\.b\[0\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: luti2 {z0\.b-z3\.b}, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: luti2 {z0\.h-z3\.h}, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: luti2 {z0\.s-z3\.s}, zt0, z0\[0\] +[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `luti2 {z0\.b-z3\.b},zt0,z0\[-1\]' +[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `luti2 {z0\.b-z3\.b},zt0,z0\[4\]' +[^ :]+:[0-9]+: Error: operand mismatch -- `luti2 {z0\.d-z3\.d},zt0,z0\[0\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: luti2 {z0\.b-z3\.b}, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: luti2 {z0\.h-z3\.h}, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: luti2 {z0\.s-z3\.s}, zt0, z0\[0\] +[^ :]+:[0-9]+: Error: operand mismatch -- `luti2 {z0\.q-z3\.q},zt0,z0\[0\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: luti2 {z0\.b-z3\.b}, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: luti2 {z0\.h-z3\.h}, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: luti2 {z0\.s-z3\.s}, zt0, z0\[0\] +[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `luti4 0,zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: expected a register at operand 2 -- `luti4 z0\.b,0,z0\[0\]' +[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `luti4 z0\.b,zt0,0' +[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `luti4 z0\.h,zt0,z0\[-1\]' +[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `luti4 z0\.h,zt0,z0\[8\]' +[^ :]+:[0-9]+: Error: operand mismatch -- `luti4 z0\.h,zt0,z0\.h\[0\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: luti4 z0\.h, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: luti4 z0\.b, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: luti4 z0\.s, zt0, z0\[0\] +[^ :]+:[0-9]+: Error: operand mismatch -- `luti4 z0,zt0,z0\[0\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: luti4 z0\.b, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: luti4 z0\.h, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: luti4 z0\.s, zt0, z0\[0\] +[^ :]+:[0-9]+: Error: operand mismatch -- `luti4 z0\.d,zt0,z0\[0\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: luti4 z0\.b, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: luti4 z0\.h, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: luti4 z0\.s, zt0, z0\[0\] +[^ :]+:[0-9]+: Error: operand mismatch -- `luti4 z0\.q,zt0,z0\[0\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: luti4 z0\.b, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: luti4 z0\.h, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: luti4 z0\.s, zt0, z0\[0\] +[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `luti4 z0\.h,zt0,zt0' +[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `luti4 {z1\.h-z2\.h},zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: unexpected register type at operand 2 -- `luti4 {z0\.h-z1\.h},z0,z0\[0\]' +[^ :]+:[0-9]+: Error: unexpected register type at operand 2 -- `luti4 {z0\.h-z1\.h},za,z0\[0\]' +[^ :]+:[0-9]+: Error: operand mismatch -- `luti4 {z0\.h-z1\.h},zt0,z0\.h\[0\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: luti4 {z0\.h-z1\.h}, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: luti4 {z0\.b-z1\.b}, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: luti4 {z0\.s-z1\.s}, zt0, z0\[0\] +[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `luti4 {z0\.h-z1\.h},zt0,z0\[-1\]' +[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `luti4 {z0\.h-z1\.h},zt0,z0\[4\]' +[^ :]+:[0-9]+: Error: operand mismatch -- `luti4 {z0\.d-z1\.d},zt0,z0\[0\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: luti4 {z0\.b-z1\.b}, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: luti4 {z0\.h-z1\.h}, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: luti4 {z0\.s-z1\.s}, zt0, z0\[0\] +[^ :]+:[0-9]+: Error: operand mismatch -- `luti4 {z0\.q-z1\.q},zt0,z0\[0\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: luti4 {z0\.b-z1\.b}, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: luti4 {z0\.h-z1\.h}, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: luti4 {z0\.s-z1\.s}, zt0, z0\[0\] +[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `luti4 {z1\.s-z4\.s},zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `luti4 {z2\.s-z5\.s},zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `luti4 {z3\.s-z6\.s},zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: unexpected register type at operand 2 -- `luti4 {z0\.s-z3\.s},z0,z0\[0\]' +[^ :]+:[0-9]+: Error: unexpected register type at operand 2 -- `luti4 {z0\.s-z3\.s},za,z0\[0\]' +[^ :]+:[0-9]+: Error: operand mismatch -- `luti4 {z0\.s-z3\.s},zt0,z0\.s\[0\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: luti4 {z0\.s-z3\.s}, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: luti4 {z0\.b-z3\.b}, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: luti4 {z0\.h-z3\.h}, zt0, z0\[0\] +[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `luti4 {z0\.s-z3\.s},zt0,z0\[-1\]' +[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `luti4 {z0\.s-z3\.s},zt0,z0\[2\]' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 1 -- `luti4 {z0\.b-z3\.b},zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: operand mismatch -- `luti4 {z0\.d-z3\.d},zt0,z0\[0\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: luti4 {z0\.b-z3\.b}, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: luti4 {z0\.h-z3\.h}, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: luti4 {z0\.s-z3\.s}, zt0, z0\[0\] +[^ :]+:[0-9]+: Error: operand mismatch -- `luti4 {z0\.q-z3\.q},zt0,z0\[0\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: luti4 {z0\.b-z3\.b}, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: luti4 {z0\.h-z3\.h}, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: luti4 {z0\.s-z3\.s}, zt0, z0\[0\] diff --git a/gas/testsuite/gas/aarch64/sme2-8-invalid.s b/gas/testsuite/gas/aarch64/sme2-8-invalid.s new file mode 100644 index 00000000000..a9712c7aa13 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-8-invalid.s @@ -0,0 +1,116 @@ + zero 0 + + zero zt0 + zero { + zero { foo } + zero { zt } + zero { x0 } + zero { z0 } + zero { zt0 + zero { zt0.b } + zero { zt0, zt0 } + + movt 0, zt0[0] + movt x0, 0 + + movt zt0, x0 + movt za[0], x0 + movt za0[0], x0 + movt zt0[#0], x0 + movt zt0[-1], x0 + movt zt0[1],x0 + movt zt0[2],x0 + movt zt0[4],x0 + movt zt0[7],x0 + movt zt0[49],x0 + movt zt0[50],x0 + movt zt0[52],x0 + movt zt0[57],x0 + movt zt0[64], x0 + movt zt0[1<<32], x0 + movt zt0.b[0], x0 + movt zt0/z[0], x0 + movt zt0[0], sp + movt zt0[0], w0 + movt zt0[0], wsp + movt zt0[0], wzr + movt zt0[0], 0 + + ldr 0, [x0] + ldr zt0, 0 + + ldr zt0, [x0, #0] + ldr Zt0, [x0] + ldr zT0, [x0] + ldr zt0, [x0, #0, mul vl] + ldr zt0, [w0] + ldr zt0, [x0]! + ldr zt0, [xzr] + ldr zt0, [wsp] + ldr zt0, [x0, xzr] + ldr zt0, [x1, x2] + + luti2 z0.b, zt0, z0[-1] + luti2 z0.b, zt0, z0[16] + luti2 z0.b, zt0, z0.b[0] + luti2 z0, zt0, z0[0] + luti2 z0.d, zt0, z0[0] + luti2 z0.q, zt0, z0[0] + luti2 z0.b, zt0, zt0 + + luti2 0, zt0, z0[0] + luti2 z0.b, 0, z0[0] + luti2 z0.b, zt0, 0 + + luti2 { z1.b - z2.b }, zt0, z0[0] + luti2 { z0.b - z1.b }, z0, z0[0] + luti2 { z0.b - z1.b }, za, z0[0] + luti2 { z0.h - z1.h }, zt0, z0.h[0] + luti2 { z0.h - z1.h }, zt0, z0[-1] + luti2 { z0.h - z1.h }, zt0, z0[8] + luti2 { z0.d - z1.d }, zt0, z0[0] + luti2 { z0.q - z1.q }, zt0, z0[0] + + luti2 { z1.s - z4.s }, zt0, z0[0] + luti2 { z2.s - z5.s }, zt0, z0[0] + luti2 { z3.s - z6.s }, zt0, z0[0] + luti2 { z0.s - z3.s }, z0, z0[0] + luti2 { z0.b - z3.b }, za, z0[0] + luti2 { z0.b - z3.b }, zt0, z0.b[0] + luti2 { z0.b - z3.b }, zt0, z0[-1] + luti2 { z0.b - z3.b }, zt0, z0[4] + luti2 { z0.d - z3.d }, zt0, z0[0] + luti2 { z0.q - z3.q }, zt0, z0[0] + + luti4 0, zt0, z0[0] + luti4 z0.b, 0, z0[0] + luti4 z0.b, zt0, 0 + + luti4 z0.h, zt0, z0[-1] + luti4 z0.h, zt0, z0[8] + luti4 z0.h, zt0, z0.h[0] + luti4 z0, zt0, z0[0] + luti4 z0.d, zt0, z0[0] + luti4 z0.q, zt0, z0[0] + luti4 z0.h, zt0, zt0 + + luti4 { z1.h - z2.h }, zt0, z0[0] + luti4 { z0.h - z1.h }, z0, z0[0] + luti4 { z0.h - z1.h }, za, z0[0] + luti4 { z0.h - z1.h }, zt0, z0.h[0] + luti4 { z0.h - z1.h }, zt0, z0[-1] + luti4 { z0.h - z1.h }, zt0, z0[4] + luti4 { z0.d - z1.d }, zt0, z0[0] + luti4 { z0.q - z1.q }, zt0, z0[0] + + luti4 { z1.s - z4.s }, zt0, z0[0] + luti4 { z2.s - z5.s }, zt0, z0[0] + luti4 { z3.s - z6.s }, zt0, z0[0] + luti4 { z0.s - z3.s }, z0, z0[0] + luti4 { z0.s - z3.s }, za, z0[0] + luti4 { z0.s - z3.s }, zt0, z0.s[0] + luti4 { z0.s - z3.s }, zt0, z0[-1] + luti4 { z0.s - z3.s }, zt0, z0[2] + luti4 { z0.b - z3.b }, zt0, z0[0] + luti4 { z0.d - z3.d }, zt0, z0[0] + luti4 { z0.q - z3.q }, zt0, z0[0] diff --git a/gas/testsuite/gas/aarch64/sme2-8-noarch.d b/gas/testsuite/gas/aarch64/sme2-8-noarch.d new file mode 100644 index 00000000000..116e9d67b66 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-8-noarch.d @@ -0,0 +1,3 @@ +#as: -march=armv8-a+sme +#source: sme2-8.s +#error_output: sme2-8-noarch.l diff --git a/gas/testsuite/gas/aarch64/sme2-8-noarch.l b/gas/testsuite/gas/aarch64/sme2-8-noarch.l new file mode 100644 index 00000000000..994b359532d --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-8-noarch.l @@ -0,0 +1,104 @@ +[^ :]+: Assembler messages: +[^ :]+:[0-9]+: Error: selected processor does not support `zero {zt0}' +[^ :]+:[0-9]+: Error: selected processor does not support `zero {ZT0}' +[^ :]+:[0-9]+: Error: selected processor does not support `movt x0,zt0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `movt X0,ZT0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `movt x30,zt0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `movt xzr,zt0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `movt x0,zt0\[56\]' +[^ :]+:[0-9]+: Error: selected processor does not support `movt x9,zt0\[24\]' +[^ :]+:[0-9]+: Error: selected processor does not support `movt x15,zt0\[40\]' +[^ :]+:[0-9]+: Error: selected processor does not support `movt x22,zt0\[48\]' +[^ :]+:[0-9]+: Error: selected processor does not support `movt zt0\[0\],x0' +[^ :]+:[0-9]+: Error: selected processor does not support `movt ZT0\[0\],X0' +[^ :]+:[0-9]+: Error: selected processor does not support `movt zt0\[56\],x0' +[^ :]+:[0-9]+: Error: selected processor does not support `movt zt0\[0\],x30' +[^ :]+:[0-9]+: Error: selected processor does not support `movt zt0\[0\],xzr' +[^ :]+:[0-9]+: Error: selected processor does not support `movt zt0\[8\],x20' +[^ :]+:[0-9]+: Error: selected processor does not support `movt zt0\[16\],x25' +[^ :]+:[0-9]+: Error: selected processor does not support `movt zt0\[32\],x27' +[^ :]+:[0-9]+: Error: selected processor does not support `movt zt0\[24\],x29' +[^ :]+:[0-9]+: Error: selected processor does not support `ldr zt0,\[x0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `ldr ZT0,\[X0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `ldr zt0,\[x30\]' +[^ :]+:[0-9]+: Error: selected processor does not support `ldr zt0,\[sp\]' +[^ :]+:[0-9]+: Error: selected processor does not support `str zt0,\[x0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `str ZT0,\[X0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `str zt0,\[x30\]' +[^ :]+:[0-9]+: Error: selected processor does not support `str zt0,\[sp\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 z0\.b,zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 Z0\.B,ZT0,Z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 z31\.b,zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 z0\.b,zt0,z31\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 z0\.b,zt0,z0\[15\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 z0\.h,zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 z31\.h,zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 z0\.h,zt0,z31\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 z0\.h,zt0,z0\[15\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 z0\.s,zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 z31\.s,zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 z0\.s,zt0,z31\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 z0\.s,zt0,z0\[15\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.b-z1\.b},zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {Z0\.B-Z1\.B},ZT0,Z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z30\.b-z31\.b},zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.b-z1\.b},zt0,z31\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.b-z1\.b},zt0,z0\[7\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.h-z1\.h},zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z30\.h-z31\.h},zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.h-z1\.h},zt0,z31\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.h-z1\.h},zt0,z0\[7\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.s-z1\.s},zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z30\.s-z31\.s},zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.s-z1\.s},zt0,z31\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.s-z1\.s},zt0,z0\[7\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.b-z3\.b},zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {Z0\.B-Z3\.B},ZT0,Z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z28\.b-z31\.b},zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.b-z3\.b},zt0,z31\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.b-z3\.b},zt0,z0\[3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.h-z3\.h},zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z28\.h-z31\.h},zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.h-z3\.h},zt0,z31\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.h-z3\.h},zt0,z0\[3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.s-z3\.s},zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z28\.s-z31\.s},zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.s-z3\.s},zt0,z31\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.s-z3\.s},zt0,z0\[3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 z0\.b,zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 Z0\.b,ZT0,Z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 z31\.b,zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 z0\.b,zt0,z31\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 z0\.b,zt0,z0\[7\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 z0\.h,zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 Z0\.H,ZT0,Z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 z31\.h,zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 z0\.h,zt0,z31\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 z0\.h,zt0,z0\[7\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 z0\.s,zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 z31\.s,zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 z0\.s,zt0,z31\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 z0\.s,zt0,z0\[7\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z0\.b-z1\.b},zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {Z0\.b-Z1\.b},ZT0,Z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z30\.b-z31\.b},zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z0\.b-z1\.b},zt0,z31\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z0\.b-z1\.b},zt0,z0\[3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z0\.h-z1\.h},zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {Z0\.H-Z1\.H},ZT0,Z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z30\.h-z31\.h},zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z0\.h-z1\.h},zt0,z31\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z0\.h-z1\.h},zt0,z0\[3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z0\.s-z1\.s},zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z30\.s-z31\.s},zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z0\.s-z1\.s},zt0,z31\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z0\.s-z1\.s},zt0,z0\[3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z0\.h-z3\.h},zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {Z0\.H-Z3\.H},ZT0,Z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z28\.h-z31\.h},zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z0\.h-z3\.h},zt0,z31\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z0\.h-z3\.h},zt0,z0\[1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z0\.s-z3\.s},zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z28\.s-z31\.s},zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z0\.s-z3\.s},zt0,z31\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z0\.s-z3\.s},zt0,z0\[1\]' diff --git a/gas/testsuite/gas/aarch64/sme2-8.d b/gas/testsuite/gas/aarch64/sme2-8.d new file mode 100644 index 00000000000..a129dff4d70 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-8.d @@ -0,0 +1,112 @@ +#as: -march=armv8-a+sme2 +#objdump: -dr + +[^:]+: file format .* + + +[^:]+: + +[^:]+: +[^:]+: c0480001 zero {zt0} +[^:]+: c0480001 zero {zt0} +[^:]+: c04c03e0 movt x0, zt0\[0\] +[^:]+: c04c03e0 movt x0, zt0\[0\] +[^:]+: c04c03fe movt x30, zt0\[0\] +[^:]+: c04c03ff movt xzr, zt0\[0\] +[^:]+: c04c73e0 movt x0, zt0\[56\] +[^:]+: c04c33e9 movt x9, zt0\[24\] +[^:]+: c04c53ef movt x15, zt0\[40\] +[^:]+: c04c63f6 movt x22, zt0\[48\] +[^:]+: c04e03e0 movt zt0\[0\], x0 +[^:]+: c04e03e0 movt zt0\[0\], x0 +[^:]+: c04e73e0 movt zt0\[56\], x0 +[^:]+: c04e03fe movt zt0\[0\], x30 +[^:]+: c04e03ff movt zt0\[0\], xzr +[^:]+: c04e13f4 movt zt0\[8\], x20 +[^:]+: c04e23f9 movt zt0\[16\], x25 +[^:]+: c04e43fb movt zt0\[32\], x27 +[^:]+: c04e33fd movt zt0\[24\], x29 +[^:]+: e11f8000 ldr zt0, \[x0\] +[^:]+: e11f8000 ldr zt0, \[x0\] +[^:]+: e11f83c0 ldr zt0, \[x30\] +[^:]+: e11f83e0 ldr zt0, \[sp\] +[^:]+: e13f8000 str zt0, \[x0\] +[^:]+: e13f8000 str zt0, \[x0\] +[^:]+: e13f83c0 str zt0, \[x30\] +[^:]+: e13f83e0 str zt0, \[sp\] +[^:]+: c0cc0000 luti2 z0\.b, zt0, z0\[0\] +[^:]+: c0cc0000 luti2 z0\.b, zt0, z0\[0\] +[^:]+: c0cc001f luti2 z31\.b, zt0, z0\[0\] +[^:]+: c0cc03e0 luti2 z0\.b, zt0, z31\[0\] +[^:]+: c0cfc000 luti2 z0\.b, zt0, z0\[15\] +[^:]+: c0cc1000 luti2 z0\.h, zt0, z0\[0\] +[^:]+: c0cc101f luti2 z31\.h, zt0, z0\[0\] +[^:]+: c0cc13e0 luti2 z0\.h, zt0, z31\[0\] +[^:]+: c0cfd000 luti2 z0\.h, zt0, z0\[15\] +[^:]+: c0cc2000 luti2 z0\.s, zt0, z0\[0\] +[^:]+: c0cc201f luti2 z31\.s, zt0, z0\[0\] +[^:]+: c0cc23e0 luti2 z0\.s, zt0, z31\[0\] +[^:]+: c0cfe000 luti2 z0\.s, zt0, z0\[15\] +[^:]+: c08c4000 luti2 {z0\.b-z1\.b}, zt0, z0\[0\] +[^:]+: c08c4000 luti2 {z0\.b-z1\.b}, zt0, z0\[0\] +[^:]+: c08c401e luti2 {z30\.b-z31\.b}, zt0, z0\[0\] +[^:]+: c08c43e0 luti2 {z0\.b-z1\.b}, zt0, z31\[0\] +[^:]+: c08fc000 luti2 {z0\.b-z1\.b}, zt0, z0\[7\] +[^:]+: c08c5000 luti2 {z0\.h-z1\.h}, zt0, z0\[0\] +[^:]+: c08c501e luti2 {z30\.h-z31\.h}, zt0, z0\[0\] +[^:]+: c08c53e0 luti2 {z0\.h-z1\.h}, zt0, z31\[0\] +[^:]+: c08fd000 luti2 {z0\.h-z1\.h}, zt0, z0\[7\] +[^:]+: c08c6000 luti2 {z0\.s-z1\.s}, zt0, z0\[0\] +[^:]+: c08c601e luti2 {z30\.s-z31\.s}, zt0, z0\[0\] +[^:]+: c08c63e0 luti2 {z0\.s-z1\.s}, zt0, z31\[0\] +[^:]+: c08fe000 luti2 {z0\.s-z1\.s}, zt0, z0\[7\] +[^:]+: c08c8000 luti2 {z0\.b-z3\.b}, zt0, z0\[0\] +[^:]+: c08c8000 luti2 {z0\.b-z3\.b}, zt0, z0\[0\] +[^:]+: c08c801c luti2 {z28\.b-z31\.b}, zt0, z0\[0\] +[^:]+: c08c83e0 luti2 {z0\.b-z3\.b}, zt0, z31\[0\] +[^:]+: c08f8000 luti2 {z0\.b-z3\.b}, zt0, z0\[3\] +[^:]+: c08c9000 luti2 {z0\.h-z3\.h}, zt0, z0\[0\] +[^:]+: c08c901c luti2 {z28\.h-z31\.h}, zt0, z0\[0\] +[^:]+: c08c93e0 luti2 {z0\.h-z3\.h}, zt0, z31\[0\] +[^:]+: c08f9000 luti2 {z0\.h-z3\.h}, zt0, z0\[3\] +[^:]+: c08ca000 luti2 {z0\.s-z3\.s}, zt0, z0\[0\] +[^:]+: c08ca01c luti2 {z28\.s-z31\.s}, zt0, z0\[0\] +[^:]+: c08ca3e0 luti2 {z0\.s-z3\.s}, zt0, z31\[0\] +[^:]+: c08fa000 luti2 {z0\.s-z3\.s}, zt0, z0\[3\] +[^:]+: c0ca0000 luti4 z0\.b, zt0, z0\[0\] +[^:]+: c0ca0000 luti4 z0\.b, zt0, z0\[0\] +[^:]+: c0ca001f luti4 z31\.b, zt0, z0\[0\] +[^:]+: c0ca03e0 luti4 z0\.b, zt0, z31\[0\] +[^:]+: c0cbc000 luti4 z0\.b, zt0, z0\[7\] +[^:]+: c0ca1000 luti4 z0\.h, zt0, z0\[0\] +[^:]+: c0ca1000 luti4 z0\.h, zt0, z0\[0\] +[^:]+: c0ca101f luti4 z31\.h, zt0, z0\[0\] +[^:]+: c0ca13e0 luti4 z0\.h, zt0, z31\[0\] +[^:]+: c0cbd000 luti4 z0\.h, zt0, z0\[7\] +[^:]+: c0ca2000 luti4 z0\.s, zt0, z0\[0\] +[^:]+: c0ca201f luti4 z31\.s, zt0, z0\[0\] +[^:]+: c0ca23e0 luti4 z0\.s, zt0, z31\[0\] +[^:]+: c0cbe000 luti4 z0\.s, zt0, z0\[7\] +[^:]+: c08a4000 luti4 {z0\.b-z1\.b}, zt0, z0\[0\] +[^:]+: c08a4000 luti4 {z0\.b-z1\.b}, zt0, z0\[0\] +[^:]+: c08a401e luti4 {z30\.b-z31\.b}, zt0, z0\[0\] +[^:]+: c08a43e0 luti4 {z0\.b-z1\.b}, zt0, z31\[0\] +[^:]+: c08bc000 luti4 {z0\.b-z1\.b}, zt0, z0\[3\] +[^:]+: c08a5000 luti4 {z0\.h-z1\.h}, zt0, z0\[0\] +[^:]+: c08a5000 luti4 {z0\.h-z1\.h}, zt0, z0\[0\] +[^:]+: c08a501e luti4 {z30\.h-z31\.h}, zt0, z0\[0\] +[^:]+: c08a53e0 luti4 {z0\.h-z1\.h}, zt0, z31\[0\] +[^:]+: c08bd000 luti4 {z0\.h-z1\.h}, zt0, z0\[3\] +[^:]+: c08a6000 luti4 {z0\.s-z1\.s}, zt0, z0\[0\] +[^:]+: c08a601e luti4 {z30\.s-z31\.s}, zt0, z0\[0\] +[^:]+: c08a63e0 luti4 {z0\.s-z1\.s}, zt0, z31\[0\] +[^:]+: c08be000 luti4 {z0\.s-z1\.s}, zt0, z0\[3\] +[^:]+: c08a9000 luti4 {z0\.h-z3\.h}, zt0, z0\[0\] +[^:]+: c08a9000 luti4 {z0\.h-z3\.h}, zt0, z0\[0\] +[^:]+: c08a901c luti4 {z28\.h-z31\.h}, zt0, z0\[0\] +[^:]+: c08a93e0 luti4 {z0\.h-z3\.h}, zt0, z31\[0\] +[^:]+: c08b9000 luti4 {z0\.h-z3\.h}, zt0, z0\[1\] +[^:]+: c08aa000 luti4 {z0\.s-z3\.s}, zt0, z0\[0\] +[^:]+: c08aa01c luti4 {z28\.s-z31\.s}, zt0, z0\[0\] +[^:]+: c08aa3e0 luti4 {z0\.s-z3\.s}, zt0, z31\[0\] +[^:]+: c08ba000 luti4 {z0\.s-z3\.s}, zt0, z0\[1\] diff --git a/gas/testsuite/gas/aarch64/sme2-8.s b/gas/testsuite/gas/aarch64/sme2-8.s new file mode 100644 index 00000000000..2bd5449c214 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-8.s @@ -0,0 +1,124 @@ + zero { zt0 } + ZERO { ZT0 } + + movt x0, zt0[0] + MOVT X0, ZT0[0] + movt x30, zt0[0] + movt xzr, zt0[0] + movt x0, zt0[56] + movt x9, zt0[24] + movt x15, zt0[40] + movt x22, zt0[48] + + movt zt0[0], x0 + MOVT ZT0[0], X0 + movt zt0[56], x0 + movt zt0[0], x30 + movt zt0[0], xzr + movt zt0[8], x20 + movt zt0[16], x25 + movt zt0[32], x27 + movt zt0[24], x29 + + ldr zt0, [x0] + LDR ZT0, [X0] + ldr zt0, [x30] + ldr zt0, [sp] + + str zt0, [x0] + STR ZT0, [X0] + str zt0, [x30] + str zt0, [sp] + + luti2 z0.b, zt0, z0[0] + LUTI2 Z0.B, ZT0, Z0[0] + luti2 z31.b, zt0, z0[0] + luti2 z0.b, zt0, z31[0] + luti2 z0.b, zt0, z0[15] + + luti2 z0.h, zt0, z0[0] + luti2 z31.h, zt0, z0[0] + luti2 z0.h, zt0, z31[0] + luti2 z0.h, zt0, z0[15] + + luti2 z0.s, zt0, z0[0] + luti2 z31.s, zt0, z0[0] + luti2 z0.s, zt0, z31[0] + luti2 z0.s, zt0, z0[15] + + luti2 { z0.b - z1.b }, zt0, z0[0] + LUTI2 { Z0.B - Z1.B }, ZT0, Z0[0] + luti2 { z30.b - z31.b }, zt0, z0[0] + luti2 { z0.b - z1.b }, zt0, z31[0] + luti2 { z0.b - z1.b }, zt0, z0[7] + + luti2 { z0.h - z1.h }, zt0, z0[0] + luti2 { z30.h - z31.h }, zt0, z0[0] + luti2 { z0.h - z1.h }, zt0, z31[0] + luti2 { z0.h - z1.h }, zt0, z0[7] + + luti2 { z0.s - z1.s }, zt0, z0[0] + luti2 { z30.s - z31.s }, zt0, z0[0] + luti2 { z0.s - z1.s }, zt0, z31[0] + luti2 { z0.s - z1.s }, zt0, z0[7] + + luti2 { z0.b - z3.b }, zt0, z0[0] + LUTI2 { Z0.B - Z3.B }, ZT0, Z0[0] + luti2 { z28.b - z31.b }, zt0, z0[0] + luti2 { z0.b - z3.b }, zt0, z31[0] + luti2 { z0.b - z3.b }, zt0, z0[3] + + luti2 { z0.h - z3.h }, zt0, z0[0] + luti2 { z28.h - z31.h }, zt0, z0[0] + luti2 { z0.h - z3.h }, zt0, z31[0] + luti2 { z0.h - z3.h }, zt0, z0[3] + + luti2 { z0.s - z3.s }, zt0, z0[0] + luti2 { z28.s - z31.s }, zt0, z0[0] + luti2 { z0.s - z3.s }, zt0, z31[0] + luti2 { z0.s - z3.s }, zt0, z0[3] + + luti4 z0.b, zt0, z0[0] + LUTI4 Z0.b, ZT0, Z0[0] + luti4 z31.b, zt0, z0[0] + luti4 z0.b, zt0, z31[0] + luti4 z0.b, zt0, z0[7] + + luti4 z0.h, zt0, z0[0] + LUTI4 Z0.H, ZT0, Z0[0] + luti4 z31.h, zt0, z0[0] + luti4 z0.h, zt0, z31[0] + luti4 z0.h, zt0, z0[7] + + luti4 z0.s, zt0, z0[0] + luti4 z31.s, zt0, z0[0] + luti4 z0.s, zt0, z31[0] + luti4 z0.s, zt0, z0[7] + + luti4 { z0.b - z1.b }, zt0, z0[0] + LUTI4 { Z0.b - Z1.b }, ZT0, Z0[0] + luti4 { z30.b - z31.b }, zt0, z0[0] + luti4 { z0.b - z1.b }, zt0, z31[0] + luti4 { z0.b - z1.b }, zt0, z0[3] + + luti4 { z0.h - z1.h }, zt0, z0[0] + LUTI4 { Z0.H - Z1.H }, ZT0, Z0[0] + luti4 { z30.h - z31.h }, zt0, z0[0] + luti4 { z0.h - z1.h }, zt0, z31[0] + luti4 { z0.h - z1.h }, zt0, z0[3] + + luti4 { z0.s - z1.s }, zt0, z0[0] + luti4 { z30.s - z31.s }, zt0, z0[0] + luti4 { z0.s - z1.s }, zt0, z31[0] + luti4 { z0.s - z1.s }, zt0, z0[3] + + luti4 { z0.h - z3.h }, zt0, z0[0] + LUTI4 { Z0.H - Z3.H }, ZT0, Z0[0] + luti4 { z28.h - z31.h }, zt0, z0[0] + luti4 { z0.h - z3.h }, zt0, z31[0] + luti4 { z0.h - z3.h }, zt0, z0[1] + + luti4 { z0.s - z3.s }, zt0, z0[0] + luti4 { z28.s - z31.s }, zt0, z0[0] + luti4 { z0.s - z3.s }, zt0, z31[0] + luti4 { z0.s - z3.s }, zt0, z0[1] diff --git a/gas/testsuite/gas/aarch64/sve-invalid.l b/gas/testsuite/gas/aarch64/sve-invalid.l index 00352f88f52..a02fbfe28ef 100644 --- a/gas/testsuite/gas/aarch64/sve-invalid.l +++ b/gas/testsuite/gas/aarch64/sve-invalid.l @@ -932,6 +932,14 @@ .*: Error: register element index out of range 0 to 63 at operand 2 -- `dup z0\.b,z1\.b\[-1\]' .*: Error: register element index out of range 0 to 63 at operand 2 -- `dup z0\.b,z1\.b\[64\]' .*: Error: constant expression required at operand 2 -- `dup z0\.b,z1\.b\[x0\]' +.*: Error: operand mismatch -- `dup z0\.b,z1\[0\]' +.*: Info: did you mean this\? +.*: Info: dup z0\.b, z1\.b\[0\] +.*: Info: other valid variant\(s\): +.*: Info: dup z0\.h, z1\.h\[0\] +.*: Info: dup z0\.s, z1\.s\[0\] +.*: Info: dup z0\.d, z1\.d\[0\] +.*: Info: dup z0\.q, z1\.q\[0\] .*: Error: register element index out of range 0 to 31 at operand 2 -- `dup z0\.h,z1\.h\[-1\]' .*: Error: register element index out of range 0 to 31 at operand 2 -- `dup z0\.h,z1\.h\[32\]' .*: Error: constant expression required at operand 2 -- `dup z0\.h,z1\.h\[x0\]' diff --git a/gas/testsuite/gas/aarch64/sve-invalid.s b/gas/testsuite/gas/aarch64/sve-invalid.s index b56a08dc15c..c374396ebb3 100644 --- a/gas/testsuite/gas/aarch64/sve-invalid.s +++ b/gas/testsuite/gas/aarch64/sve-invalid.s @@ -1143,6 +1143,7 @@ dup z0.b, z1.b[63] // OK dup z0.b, z1.b[64] dup z0.b, z1.b[x0] + dup z0.b, z1[0] dup z0.h, z1.h[-1] dup z0.h, z1.h[0] // OK diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index ee0a3b65ab0..69e0f833170 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -515,8 +515,17 @@ enum aarch64_opnd AARCH64_OPND_SME_ADDR_RI_U4xVL, /* SME [{, #, MUL VL}]. */ AARCH64_OPND_SME_SM_ZA, /* SME {SM | ZA}. */ AARCH64_OPND_SME_PnT_Wm_imm, /* SME .[, #]. */ + AARCH64_OPND_SME_Zn_INDEX1_16, /* Zn[index], bits [9:5] and [16:16]. */ + AARCH64_OPND_SME_Zn_INDEX2_15, /* Zn[index], bits [9:5] and [16:15]. */ + AARCH64_OPND_SME_Zn_INDEX2_16, /* Zn[index], bits [9:5] and [17:16]. */ + AARCH64_OPND_SME_Zn_INDEX3_14, /* Zn[index], bits [9:5] and [16:14]. */ + AARCH64_OPND_SME_Zn_INDEX3_15, /* Zn[index], bits [9:5] and [17:15]. */ + AARCH64_OPND_SME_Zn_INDEX4_14, /* Zn[index], bits [9:5] and [17:14]. */ AARCH64_OPND_SME_VLxN_10, /* VLx2 or VLx4, in bit 10. */ AARCH64_OPND_SME_VLxN_13, /* VLx2 or VLx4, in bit 13. */ + AARCH64_OPND_SME_ZT0, /* The fixed token zt0/ZT0 (not encoded). */ + AARCH64_OPND_SME_ZT0_INDEX, /* ZT0[], bits [14:12]. */ + AARCH64_OPND_SME_ZT0_LIST, /* { zt0/ZT0 } (not encoded). */ AARCH64_OPND_TME_UIMM16, /* TME unsigned 16-bit immediate. */ AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */ AARCH64_OPND_MOPS_ADDR_Rd, /* [Rd]!, in bits [0, 4]. */ @@ -690,6 +699,8 @@ enum aarch64_insn_class sme_mov, sme_ldr, sme_psel, + sme_size_12_bhs, + sme_size_12_hs, sme_size_22, sme_str, sme_start, diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c index 9302253db59..cdc9e465d13 100644 --- a/opcodes/aarch64-asm-2.c +++ b/opcodes/aarch64-asm-2.c @@ -684,7 +684,7 @@ aarch64_insert_operand (const aarch64_operand *self, case 33: case 34: case 35: - case 247: + case 256: return aarch64_ins_reglane (self, info, code, inst, errors); case 36: return aarch64_ins_reglist (self, info, code, inst, errors); @@ -730,11 +730,12 @@ aarch64_insert_operand (const aarch64_operand *self, case 193: case 194: case 236: - case 244: - case 245: - case 246: + case 250: case 251: - case 252: + case 253: + case 255: + case 260: + case 261: return aarch64_ins_imm (self, info, code, inst, errors); case 44: case 45: @@ -803,6 +804,8 @@ aarch64_insert_operand (const aarch64_operand *self, case 107: return aarch64_ins_prfop (self, info, code, inst, errors); case 108: + case 252: + case 254: return aarch64_ins_none (self, info, code, inst, errors); case 109: return aarch64_ins_hint (self, info, code, inst, errors); @@ -915,6 +918,12 @@ aarch64_insert_operand (const aarch64_operand *self, return aarch64_ins_sme_za_hv_tiles_range (self, info, code, inst, errors); case 234: case 235: + case 244: + case 245: + case 246: + case 247: + case 248: + case 249: return aarch64_ins_simple_index (self, info, code, inst, errors); case 238: case 239: @@ -926,9 +935,9 @@ aarch64_insert_operand (const aarch64_operand *self, return aarch64_ins_sme_sm_za (self, info, code, inst, errors); case 243: return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors); - case 248: - case 249: - case 250: + case 257: + case 258: + case 259: return aarch64_ins_x0_to_x30 (self, info, code, inst, errors); default: assert (0); abort (); } diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c index acfec3773dc..bd03f4116cc 100644 --- a/opcodes/aarch64-asm.c +++ b/opcodes/aarch64-asm.c @@ -404,6 +404,8 @@ aarch64_ins_imm (const aarch64_operand *self, const aarch64_opnd_info *info, imm = info->imm.value; if (operand_need_shift_by_two (self)) imm >>= 2; + if (operand_need_shift_by_three (self)) + imm >>= 3; if (operand_need_shift_by_four (self)) imm >>= 4; insert_all_fields (self, code, imm); @@ -1946,11 +1948,21 @@ aarch64_encode_variant_using_iclass (struct aarch64_inst *inst) /* The variant is encoded as part of the immediate. */ break; + case sme_size_12_bhs: + insert_field (FLD_SME_size_12, &inst->value, + aarch64_get_variant (inst), 0); + break; + case sme_size_22: insert_field (FLD_SME_size_22, &inst->value, aarch64_get_variant (inst), 0); break; + case sme_size_12_hs: + insert_field (FLD_SME_size_12, &inst->value, + aarch64_get_variant (inst) + 1, 0); + break; + case sve_cpy: insert_fields (&inst->value, aarch64_get_variant (inst), 0, 2, FLD_SVE_M_14, FLD_size); diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c index 5210db3b008..f69f30f8884 100644 --- a/opcodes/aarch64-dis-2.c +++ b/opcodes/aarch64-dis-2.c @@ -94,9 +94,9 @@ aarch64_opcode_lookup_1 (uint32_t word) } else { - if (((word >> 17) & 0x1) == 0) + if (((word >> 18) & 0x1) == 0) { - if (((word >> 18) & 0x1) == 0) + if (((word >> 17) & 0x1) == 0) { if (((word >> 19) & 0x1) == 0) { @@ -152,95 +152,194 @@ aarch64_opcode_lookup_1 (uint32_t word) } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000000xx0x100xxxxxxxxxxxxxxxxx - zero. */ - return 2392; + if (((word >> 22) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000000x00x100xxxxxxxxxxxxxxxxx + zero. */ + return 2392; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000000x10x100xxxxxxxxxxxxxxxxx + zero. */ + return 2596; + } } } else { - if (((word >> 10) & 0x1) == 0) + if (((word >> 19) & 0x1) == 0) { - if (((word >> 11) & 0x1) == 0) + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000000xx0x001xxxxxxxxxxxxxxxxx + mov. */ + return 2388; + } + else + { + if (((word >> 22) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000000xx0xx10xxxxx00xxxxxxxxxx - mov. */ - return 2499; + if (((word >> 14) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000000x00x101xx0xxxxxxxxxxxxxx + luti4. */ + return 2499; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000000x00x101xx1xxxxxxxxxxxxxx + luti4. */ + return 2498; + } } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x1000000xx0xx10xxxxx10xxxxxxxxxx - mov. */ + x1000000x10x101xxxxxxxxxxxxxxxxx + luti4. */ return 2497; } } + } + } + else + { + if (((word >> 10) & 0x1) == 0) + { + if (((word >> 11) & 0x1) == 0) + { + if (((word >> 19) & 0x1) == 0) + { + if (((word >> 17) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000000xx0x010xxxxx00xxxxxxxxxx + mov. */ + return 2506; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000000xx0x011xxxxx00xxxxxxxxxx + mov. */ + return 2502; + } + } + else + { + if (((word >> 22) & 0x1) == 0) + { + if (((word >> 14) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000000x00x11xxx0xx00xxxxxxxxxx + luti2. */ + return 2496; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000000x00x11xxx1xx00xxxxxxxxxx + luti2. */ + return 2495; + } + } + else + { + if (((word >> 23) & 0x1) == 0) + { + if (((word >> 17) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000000010x110xxxxx00xxxxxxxxxx + movt. */ + return 2517; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000000010x111xxxxx00xxxxxxxxxx + movt. */ + return 2516; + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000000110x11xxxxxx00xxxxxxxxxx + luti2. */ + return 2494; + } + } + } + } else { - if (((word >> 11) & 0x1) == 0) + if (((word >> 17) & 0x1) == 0) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x1000000xx0xx10xxxxx01xxxxxxxxxx + x1000000xx0xx10xxxxx10xxxxxxxxxx mov. */ - return 2500; + return 2504; } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x1000000xx0xx10xxxxx11xxxxxxxxxx + x1000000xx0xx11xxxxx10xxxxxxxxxx mov. */ - return 2498; + return 2500; } } } - } - else - { - if (((word >> 18) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000000xx0xx01xxxxxxxxxxxxxxxxx - mov. */ - return 2388; - } else { - if (((word >> 10) & 0x1) == 0) + if (((word >> 11) & 0x1) == 0) { - if (((word >> 11) & 0x1) == 0) + if (((word >> 17) & 0x1) == 0) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x1000000xx0xx11xxxxx00xxxxxxxxxx + x1000000xx0xx10xxxxx01xxxxxxxxxx mov. */ - return 2495; + return 2507; } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x1000000xx0xx11xxxxx10xxxxxxxxxx + x1000000xx0xx11xxxxx01xxxxxxxxxx mov. */ - return 2493; + return 2503; } } else { - if (((word >> 11) & 0x1) == 0) + if (((word >> 17) & 0x1) == 0) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x1000000xx0xx11xxxxx01xxxxxxxxxx + x1000000xx0xx10xxxxx11xxxxxxxxxx mov. */ - return 2496; + return 2505; } else { @@ -248,7 +347,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000xx0xx11xxxxx11xxxxxxxxxx mov. */ - return 2494; + return 2501; } } } @@ -713,7 +812,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx000xxxxxxxxxxxx0 st1b. */ - return 2518; + return 2527; } else { @@ -721,7 +820,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx100xxxxxxxxxxxx0 st1b. */ - return 2519; + return 2528; } } else @@ -732,7 +831,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx010xxxxxxxxxxxx0 st1w. */ - return 2542; + return 2551; } else { @@ -740,7 +839,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx110xxxxxxxxxxxx0 st1w. */ - return 2543; + return 2552; } } } @@ -754,7 +853,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx001xxxxxxxxxxxx0 st1h. */ - return 2534; + return 2543; } else { @@ -762,7 +861,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx101xxxxxxxxxxxx0 st1h. */ - return 2535; + return 2544; } } else @@ -773,7 +872,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx011xxxxxxxxxxxx0 st1d. */ - return 2526; + return 2535; } else { @@ -781,7 +880,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx111xxxxxxxxxxxx0 st1d. */ - return 2527; + return 2536; } } } @@ -798,7 +897,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx000xxxxxxxxxxxx1 stnt1b. */ - return 2550; + return 2559; } else { @@ -806,7 +905,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx100xxxxxxxxxxxx1 stnt1b. */ - return 2551; + return 2560; } } else @@ -817,7 +916,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx010xxxxxxxxxxxx1 stnt1w. */ - return 2574; + return 2583; } else { @@ -825,7 +924,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx110xxxxxxxxxxxx1 stnt1w. */ - return 2575; + return 2584; } } } @@ -839,7 +938,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx001xxxxxxxxxxxx1 stnt1h. */ - return 2566; + return 2575; } else { @@ -847,7 +946,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx101xxxxxxxxxxxx1 stnt1h. */ - return 2567; + return 2576; } } else @@ -858,7 +957,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx011xxxxxxxxxxxx1 stnt1d. */ - return 2558; + return 2567; } else { @@ -866,7 +965,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx111xxxxxxxxxxxx1 stnt1d. */ - return 2559; + return 2568; } } } @@ -930,7 +1029,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx000xxxxxxxxxxxx0 st1b. */ - return 2514; + return 2523; } else { @@ -938,7 +1037,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx100xxxxxxxxxxxx0 st1b. */ - return 2515; + return 2524; } } else @@ -949,7 +1048,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx010xxxxxxxxxxxx0 st1w. */ - return 2538; + return 2547; } else { @@ -957,7 +1056,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx110xxxxxxxxxxxx0 st1w. */ - return 2539; + return 2548; } } } @@ -971,7 +1070,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx001xxxxxxxxxxxx0 st1h. */ - return 2530; + return 2539; } else { @@ -979,7 +1078,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx101xxxxxxxxxxxx0 st1h. */ - return 2531; + return 2540; } } else @@ -990,7 +1089,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx011xxxxxxxxxxxx0 st1d. */ - return 2522; + return 2531; } else { @@ -998,7 +1097,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx111xxxxxxxxxxxx0 st1d. */ - return 2523; + return 2532; } } } @@ -1015,7 +1114,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx000xxxxxxxxxxxx1 stnt1b. */ - return 2546; + return 2555; } else { @@ -1023,7 +1122,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx100xxxxxxxxxxxx1 stnt1b. */ - return 2547; + return 2556; } } else @@ -1034,7 +1133,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx010xxxxxxxxxxxx1 stnt1w. */ - return 2570; + return 2579; } else { @@ -1042,7 +1141,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx110xxxxxxxxxxxx1 stnt1w. */ - return 2571; + return 2580; } } } @@ -1056,7 +1155,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx001xxxxxxxxxxxx1 stnt1h. */ - return 2562; + return 2571; } else { @@ -1064,7 +1163,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx101xxxxxxxxxxxx1 stnt1h. */ - return 2563; + return 2572; } } else @@ -1075,7 +1174,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx011xxxxxxxxxxxx1 stnt1d. */ - return 2554; + return 2563; } else { @@ -1083,7 +1182,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx111xxxxxxxxxxxx1 stnt1d. */ - return 2555; + return 2564; } } } @@ -1265,11 +1364,22 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 14) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx00001000xxxxx100xxxxxxxxx0xxx - ld1b. */ - return 2436; + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0x00001000xxxxx100xxxxxxxxx0xxx + ld1b. */ + return 2436; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1x00001000xxxxx100xxxxxxxxx0xxx + ldr. */ + return 2493; + } } else { @@ -1623,7 +1733,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxx0xxxxxxxxxxxxxxxx sel. */ - return 2512; + return 2521; } else { @@ -1631,7 +1741,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxx1xxxxxxxxxxxxxxxx sel. */ - return 2513; + return 2522; } } } @@ -1655,7 +1765,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx000xxxxxxxxx0xxx st1b. */ - return 2520; + return 2529; } else { @@ -1663,7 +1773,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx010xxxxxxxxx0xxx st1w. */ - return 2544; + return 2553; } } else @@ -1674,7 +1784,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx001xxxxxxxxx0xxx st1h. */ - return 2536; + return 2545; } else { @@ -1682,7 +1792,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx011xxxxxxxxx0xxx st1d. */ - return 2528; + return 2537; } } } @@ -1696,7 +1806,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx000xxxxxxxxx1xxx stnt1b. */ - return 2552; + return 2561; } else { @@ -1704,7 +1814,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx010xxxxxxxxx1xxx stnt1w. */ - return 2576; + return 2585; } } else @@ -1715,7 +1825,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx001xxxxxxxxx1xxx stnt1h. */ - return 2568; + return 2577; } else { @@ -1723,7 +1833,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx011xxxxxxxxx1xxx stnt1d. */ - return 2560; + return 2569; } } } @@ -1745,11 +1855,22 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 14) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx100001001xxxxx100xxxxxxxxx0xxx - st1b. */ - return 2521; + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0100001001xxxxx100xxxxxxxxx0xxx + st1b. */ + return 2530; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1100001001xxxxx100xxxxxxxxx0xxx + str. */ + return 2587; + } } else { @@ -1757,7 +1878,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001001xxxxx110xxxxxxxxx0xxx st1w. */ - return 2545; + return 2554; } } else @@ -1768,7 +1889,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001001xxxxx101xxxxxxxxx0xxx st1h. */ - return 2537; + return 2546; } else { @@ -1776,7 +1897,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001001xxxxx111xxxxxxxxx0xxx st1d. */ - return 2529; + return 2538; } } } @@ -1790,7 +1911,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001001xxxxx100xxxxxxxxx1xxx stnt1b. */ - return 2553; + return 2562; } else { @@ -1798,7 +1919,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001001xxxxx110xxxxxxxxx1xxx stnt1w. */ - return 2577; + return 2586; } } else @@ -1809,7 +1930,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001001xxxxx101xxxxxxxxx1xxx stnt1h. */ - return 2569; + return 2578; } else { @@ -1817,7 +1938,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001001xxxxx111xxxxxxxxx1xxx stnt1d. */ - return 2561; + return 2570; } } } @@ -1859,7 +1980,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx000xxxxxxxxx0xxx st1b. */ - return 2516; + return 2525; } else { @@ -1867,7 +1988,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx100xxxxxxxxx0xxx st1b. */ - return 2517; + return 2526; } } else @@ -1878,7 +1999,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx010xxxxxxxxx0xxx st1w. */ - return 2540; + return 2549; } else { @@ -1886,7 +2007,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx110xxxxxxxxx0xxx st1w. */ - return 2541; + return 2550; } } } @@ -1900,7 +2021,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx001xxxxxxxxx0xxx st1h. */ - return 2532; + return 2541; } else { @@ -1908,7 +2029,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx101xxxxxxxxx0xxx st1h. */ - return 2533; + return 2542; } } else @@ -1919,7 +2040,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx011xxxxxxxxx0xxx st1d. */ - return 2524; + return 2533; } else { @@ -1927,7 +2048,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx111xxxxxxxxx0xxx st1d. */ - return 2525; + return 2534; } } } @@ -1944,7 +2065,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx000xxxxxxxxx1xxx stnt1b. */ - return 2548; + return 2557; } else { @@ -1952,7 +2073,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx100xxxxxxxxx1xxx stnt1b. */ - return 2549; + return 2558; } } else @@ -1963,7 +2084,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx010xxxxxxxxx1xxx stnt1w. */ - return 2572; + return 2581; } else { @@ -1971,7 +2092,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx110xxxxxxxxx1xxx stnt1w. */ - return 2573; + return 2582; } } } @@ -1985,7 +2106,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx001xxxxxxxxx1xxx stnt1h. */ - return 2564; + return 2573; } else { @@ -1993,7 +2114,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx101xxxxxxxxx1xxx stnt1h. */ - return 2565; + return 2574; } } else @@ -2004,7 +2125,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx011xxxxxxxxx1xxx stnt1d. */ - return 2556; + return 2565; } else { @@ -2012,7 +2133,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx111xxxxxxxxx1xxx stnt1d. */ - return 2557; + return 2566; } } } @@ -4414,7 +4535,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 00011001000xxxxxxxxx00xxxxxxxxxx stlurb. */ - return 2626; + return 2637; } else { @@ -4422,7 +4543,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 10011001000xxxxxxxxx00xxxxxxxxxx stlur. */ - return 2634; + return 2645; } } else @@ -4433,7 +4554,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 01011001000xxxxxxxxx00xxxxxxxxxx stlurh. */ - return 2630; + return 2641; } else { @@ -4441,7 +4562,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 11011001000xxxxxxxxx00xxxxxxxxxx stlur. */ - return 2637; + return 2648; } } } @@ -4479,7 +4600,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0000x1xxxxxxxxxx cpyfp. */ - return 2686; + return 2697; } else { @@ -4487,7 +4608,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1000x1xxxxxxxxxx cpyfprn. */ - return 2692; + return 2703; } } else @@ -4498,7 +4619,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0100x1xxxxxxxxxx cpyfpwn. */ - return 2689; + return 2700; } else { @@ -4506,7 +4627,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1100x1xxxxxxxxxx cpyfpn. */ - return 2695; + return 2706; } } } @@ -4520,7 +4641,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0010x1xxxxxxxxxx cpyfprt. */ - return 2710; + return 2721; } else { @@ -4528,7 +4649,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1010x1xxxxxxxxxx cpyfprtrn. */ - return 2716; + return 2727; } } else @@ -4539,7 +4660,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0110x1xxxxxxxxxx cpyfprtwn. */ - return 2713; + return 2724; } else { @@ -4547,7 +4668,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1110x1xxxxxxxxxx cpyfprtn. */ - return 2719; + return 2730; } } } @@ -4564,7 +4685,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0001x1xxxxxxxxxx cpyfpwt. */ - return 2698; + return 2709; } else { @@ -4572,7 +4693,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1001x1xxxxxxxxxx cpyfpwtrn. */ - return 2704; + return 2715; } } else @@ -4583,7 +4704,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0101x1xxxxxxxxxx cpyfpwtwn. */ - return 2701; + return 2712; } else { @@ -4591,7 +4712,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1101x1xxxxxxxxxx cpyfpwtn. */ - return 2707; + return 2718; } } } @@ -4605,7 +4726,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0011x1xxxxxxxxxx cpyfpt. */ - return 2722; + return 2733; } else { @@ -4613,7 +4734,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1011x1xxxxxxxxxx cpyfptrn. */ - return 2728; + return 2739; } } else @@ -4624,7 +4745,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0111x1xxxxxxxxxx cpyfptwn. */ - return 2725; + return 2736; } else { @@ -4632,7 +4753,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1111x1xxxxxxxxxx cpyfptn. */ - return 2731; + return 2742; } } } @@ -4697,7 +4818,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 00011001010xxxxxxxxx00xxxxxxxxxx ldapurb. */ - return 2627; + return 2638; } else { @@ -4705,7 +4826,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 10011001010xxxxxxxxx00xxxxxxxxxx ldapur. */ - return 2635; + return 2646; } } else @@ -4716,7 +4837,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 01011001010xxxxxxxxx00xxxxxxxxxx ldapurh. */ - return 2631; + return 2642; } else { @@ -4724,7 +4845,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 11011001010xxxxxxxxx00xxxxxxxxxx ldapur. */ - return 2638; + return 2649; } } } @@ -4762,7 +4883,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0000x1xxxxxxxxxx cpyfm. */ - return 2687; + return 2698; } else { @@ -4770,7 +4891,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1000x1xxxxxxxxxx cpyfmrn. */ - return 2693; + return 2704; } } else @@ -4781,7 +4902,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0100x1xxxxxxxxxx cpyfmwn. */ - return 2690; + return 2701; } else { @@ -4789,7 +4910,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1100x1xxxxxxxxxx cpyfmn. */ - return 2696; + return 2707; } } } @@ -4803,7 +4924,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0010x1xxxxxxxxxx cpyfmrt. */ - return 2711; + return 2722; } else { @@ -4811,7 +4932,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1010x1xxxxxxxxxx cpyfmrtrn. */ - return 2717; + return 2728; } } else @@ -4822,7 +4943,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0110x1xxxxxxxxxx cpyfmrtwn. */ - return 2714; + return 2725; } else { @@ -4830,7 +4951,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1110x1xxxxxxxxxx cpyfmrtn. */ - return 2720; + return 2731; } } } @@ -4847,7 +4968,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0001x1xxxxxxxxxx cpyfmwt. */ - return 2699; + return 2710; } else { @@ -4855,7 +4976,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1001x1xxxxxxxxxx cpyfmwtrn. */ - return 2705; + return 2716; } } else @@ -4866,7 +4987,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0101x1xxxxxxxxxx cpyfmwtwn. */ - return 2702; + return 2713; } else { @@ -4874,7 +4995,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1101x1xxxxxxxxxx cpyfmwtn. */ - return 2708; + return 2719; } } } @@ -4888,7 +5009,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0011x1xxxxxxxxxx cpyfmt. */ - return 2723; + return 2734; } else { @@ -4896,7 +5017,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1011x1xxxxxxxxxx cpyfmtrn. */ - return 2729; + return 2740; } } else @@ -4907,7 +5028,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0111x1xxxxxxxxxx cpyfmtwn. */ - return 2726; + return 2737; } else { @@ -4915,7 +5036,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1111x1xxxxxxxxxx cpyfmtn. */ - return 2732; + return 2743; } } } @@ -4983,7 +5104,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 00011001100xxxxxxxxx00xxxxxxxxxx ldapursb. */ - return 2629; + return 2640; } else { @@ -4991,7 +5112,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 10011001100xxxxxxxxx00xxxxxxxxxx ldapursw. */ - return 2636; + return 2647; } } else @@ -5000,7 +5121,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1011001100xxxxxxxxx00xxxxxxxxxx ldapursh. */ - return 2633; + return 2644; } } else @@ -5011,7 +5132,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0011001110xxxxxxxxx00xxxxxxxxxx ldapursb. */ - return 2628; + return 2639; } else { @@ -5019,7 +5140,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1011001110xxxxxxxxx00xxxxxxxxxx ldapursh. */ - return 2632; + return 2643; } } } @@ -5081,7 +5202,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0000x1xxxxxxxxxx cpyfe. */ - return 2688; + return 2699; } else { @@ -5089,7 +5210,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0000x1xxxxxxxxxx setp. */ - return 2782; + return 2793; } } else @@ -5100,7 +5221,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx1000x1xxxxxxxxxx cpyfern. */ - return 2694; + return 2705; } else { @@ -5108,7 +5229,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx1000x1xxxxxxxxxx sete. */ - return 2784; + return 2795; } } } @@ -5122,7 +5243,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0100x1xxxxxxxxxx cpyfewn. */ - return 2691; + return 2702; } else { @@ -5130,7 +5251,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0100x1xxxxxxxxxx setm. */ - return 2783; + return 2794; } } else @@ -5139,7 +5260,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0110011x0xxxxx1100x1xxxxxxxxxx cpyfen. */ - return 2697; + return 2708; } } } @@ -5155,7 +5276,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0010x1xxxxxxxxxx cpyfert. */ - return 2712; + return 2723; } else { @@ -5163,7 +5284,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0010x1xxxxxxxxxx setpn. */ - return 2788; + return 2799; } } else @@ -5174,7 +5295,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx1010x1xxxxxxxxxx cpyfertrn. */ - return 2718; + return 2729; } else { @@ -5182,7 +5303,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx1010x1xxxxxxxxxx seten. */ - return 2790; + return 2801; } } } @@ -5196,7 +5317,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0110x1xxxxxxxxxx cpyfertwn. */ - return 2715; + return 2726; } else { @@ -5204,7 +5325,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0110x1xxxxxxxxxx setmn. */ - return 2789; + return 2800; } } else @@ -5213,7 +5334,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0110011x0xxxxx1110x1xxxxxxxxxx cpyfertn. */ - return 2721; + return 2732; } } } @@ -5232,7 +5353,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0001x1xxxxxxxxxx cpyfewt. */ - return 2700; + return 2711; } else { @@ -5240,7 +5361,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0001x1xxxxxxxxxx setpt. */ - return 2785; + return 2796; } } else @@ -5251,7 +5372,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx1001x1xxxxxxxxxx cpyfewtrn. */ - return 2706; + return 2717; } else { @@ -5259,7 +5380,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx1001x1xxxxxxxxxx setet. */ - return 2787; + return 2798; } } } @@ -5273,7 +5394,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0101x1xxxxxxxxxx cpyfewtwn. */ - return 2703; + return 2714; } else { @@ -5281,7 +5402,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0101x1xxxxxxxxxx setmt. */ - return 2786; + return 2797; } } else @@ -5290,7 +5411,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0110011x0xxxxx1101x1xxxxxxxxxx cpyfewtn. */ - return 2709; + return 2720; } } } @@ -5306,7 +5427,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0011x1xxxxxxxxxx cpyfet. */ - return 2724; + return 2735; } else { @@ -5314,7 +5435,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0011x1xxxxxxxxxx setptn. */ - return 2791; + return 2802; } } else @@ -5325,7 +5446,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx1011x1xxxxxxxxxx cpyfetrn. */ - return 2730; + return 2741; } else { @@ -5333,7 +5454,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx1011x1xxxxxxxxxx setetn. */ - return 2793; + return 2804; } } } @@ -5347,7 +5468,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0111x1xxxxxxxxxx cpyfetwn. */ - return 2727; + return 2738; } else { @@ -5355,7 +5476,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0111x1xxxxxxxxxx setmtn. */ - return 2792; + return 2803; } } else @@ -5364,7 +5485,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0110011x0xxxxx1111x1xxxxxxxxxx cpyfetn. */ - return 2733; + return 2744; } } } @@ -5737,7 +5858,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1x11010110xxxx0x01000xxxxxxxxxx abs. */ - return 2811; + return 2822; } else { @@ -5755,7 +5876,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010110xxxxxx11000xxxxxxxxxx smax. */ - return 2814; + return 2825; } } } @@ -5835,7 +5956,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010x00xxxxxx0xx10xxxxxxxxxx setf8. */ - return 2624; + return 2635; } else { @@ -5843,7 +5964,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010x00xxxxxx1xx10xxxxxxxxxx setf16. */ - return 2625; + return 2636; } } else @@ -5950,7 +6071,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010110xxxxxx11010xxxxxxxxxx smin. */ - return 2816; + return 2827; } } } @@ -5966,7 +6087,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010110xxxx0x00110xxxxxxxxxx ctz. */ - return 2813; + return 2824; } else { @@ -6011,7 +6132,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010000xxxxxxxxx01xxxxxxxxxx rmif. */ - return 2623; + return 2634; } else { @@ -6105,7 +6226,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010x10xxxxxx11001xxxxxxxxxx umax. */ - return 2815; + return 2826; } } } @@ -6235,7 +6356,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010xx0xxxxxx11011xxxxxxxxxx umin. */ - return 2817; + return 2828; } } } @@ -6251,7 +6372,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010xx0xxxx0x00111xxxxxxxxxx cnt. */ - return 2812; + return 2823; } else { @@ -7093,7 +7214,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x01x1xxxxx000110xxxxxxxxxx usdot. */ - return 2643; + return 2654; } } } @@ -7167,7 +7288,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x01x1xxxxx000111xxxxxxxxxx sudot. */ - return 2644; + return 2655; } } } @@ -9841,7 +9962,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x0xx0xxxxx011110xxxxxxxxxx usdot. */ - return 2642; + return 2653; } } } @@ -11545,7 +11666,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0100xxx10101xxxxxxxxxxxxx bfcvtnt. */ - return 2671; + return 2682; } } else @@ -11788,7 +11909,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x00x1xxxxxx00xxxxxxxxxxxxx ld1rob. */ - return 2647; + return 2658; } else { @@ -11796,7 +11917,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x01x1xxxxxx00xxxxxxxxxxxxx ld1roh. */ - return 2648; + return 2659; } } else @@ -12028,7 +12149,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0011xxxxx010xxxxxxxxxxxxx bfdot. */ - return 2668; + return 2679; } else { @@ -12049,7 +12170,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx010xx0xxxxxxxxxx bfmlalb. */ - return 2675; + return 2686; } else { @@ -12057,7 +12178,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx010xx1xxxxxxxxxx bfmlalt. */ - return 2674; + return 2685; } } else @@ -12112,7 +12233,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11001x0011xxxxx1x0xxxxxxxxxxxxx bfdot. */ - return 2667; + return 2678; } else { @@ -12124,7 +12245,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx1x0xx0xxxxxxxxxx bfmlalb. */ - return 2673; + return 2684; } else { @@ -12132,7 +12253,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx1x0xx1xxxxxxxxxx bfmlalt. */ - return 2672; + return 2683; } } else @@ -12183,7 +12304,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x00x1xxxxx001xxxxxxxxxxxxx ld1rob. */ - return 2651; + return 2662; } else { @@ -12191,7 +12312,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x01x1xxxxx001xxxxxxxxxxxxx ld1roh. */ - return 2652; + return 2663; } } else @@ -12550,7 +12671,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0101xxxxx111xxxxxxxxxxxxx fmmla. */ - return 2645; + return 2656; } else { @@ -12583,7 +12704,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0011xxxxx111xxxxxxxxxxxxx bfmmla. */ - return 2669; + return 2680; } else { @@ -12613,7 +12734,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx111xxxxxxxxxxxxx fmmla. */ - return 2646; + return 2657; } else { @@ -12742,7 +12863,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000x00xxxxxxxxxx zip1. */ - return 2655; + return 2666; } else { @@ -12752,7 +12873,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000010xxxxxxxxxx uzp1. */ - return 2657; + return 2668; } else { @@ -12760,7 +12881,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000110xxxxxxxxxx trn1. */ - return 2659; + return 2670; } } } @@ -12772,7 +12893,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000x01xxxxxxxxxx zip2. */ - return 2656; + return 2667; } else { @@ -12782,7 +12903,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000011xxxxxxxxxx uzp2. */ - return 2658; + return 2669; } else { @@ -12790,7 +12911,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000111xxxxxxxxxx trn2. */ - return 2660; + return 2671; } } } @@ -13849,7 +13970,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x1000xxxxx100110xxxxxxxxxx smmla. */ - return 2639; + return 2650; } else { @@ -13857,7 +13978,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x1100xxxxx100110xxxxxxxxxx usmmla. */ - return 2641; + return 2652; } } else @@ -13866,7 +13987,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x1x10xxxxx100110xxxxxxxxxx ummla. */ - return 2640; + return 2651; } } } @@ -15362,7 +15483,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x10x1xxxxx000xxxxxxxxxxxxx ld1row. */ - return 2649; + return 2660; } else { @@ -15370,7 +15491,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x11x1xxxxx000xxxxxxxxxxxxx ld1rod. */ - return 2650; + return 2661; } } } @@ -15744,7 +15865,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x10x1xxxxx001xxxxxxxxxxxxx ld1row. */ - return 2653; + return 2664; } else { @@ -15752,7 +15873,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x11x1xxxxx001xxxxxxxxxxxxx ld1rod. */ - return 2654; + return 2665; } } } @@ -16113,7 +16234,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x000xxxxx10xxx whilege. */ - return 2578; + return 2588; } else { @@ -16121,7 +16242,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x000xxxxx11xxx whilegt. */ - return 2579; + return 2589; } } else @@ -16151,7 +16272,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx011100xxxxx1xxxx pext. */ - return 2509; + return 2518; } } } @@ -16165,7 +16286,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x010xxxxx10xxx whilehs. */ - return 2581; + return 2591; } else { @@ -16173,7 +16294,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x010xxxxx11xxx whilehi. */ - return 2580; + return 2590; } } else @@ -16203,7 +16324,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx011110xxxxx1xxxx ptrue. */ - return 2511; + return 2520; } } } @@ -16220,7 +16341,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x001xxxxx10xxx whilelt. */ - return 2585; + return 2595; } else { @@ -16228,7 +16349,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x001xxxxx11xxx whilele. */ - return 2582; + return 2592; } } else @@ -16258,7 +16379,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx011101xxxxx1xxxx pext. */ - return 2510; + return 2519; } } } @@ -16272,7 +16393,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x011xxxxx10xxx whilelo. */ - return 2583; + return 2593; } else { @@ -16280,7 +16401,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x011xxxxx11xxx whilels. */ - return 2584; + return 2594; } } else @@ -17406,7 +17527,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x110001x10101xxxxxxxxxxxxx bfcvt. */ - return 2670; + return 2681; } } else @@ -18767,7 +18888,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1010100xxxxxxxxxxxxxxxxxxx1xxxx bc.c. */ - return 2806; + return 2817; } else { @@ -19347,7 +19468,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0000xxxxxxxxxxxx cpyp. */ - return 2734; + return 2745; } else { @@ -19355,7 +19476,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0000xxxxxxxxxxxx cpye. */ - return 2736; + return 2747; } } else @@ -19366,7 +19487,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1000xxxxxxxxxxxx cpyprn. */ - return 2740; + return 2751; } else { @@ -19374,7 +19495,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1000xxxxxxxxxxxx cpyern. */ - return 2742; + return 2753; } } } @@ -19388,7 +19509,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0100xxxxxxxxxxxx cpypwn. */ - return 2737; + return 2748; } else { @@ -19396,7 +19517,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0100xxxxxxxxxxxx cpyewn. */ - return 2739; + return 2750; } } else @@ -19407,7 +19528,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1100xxxxxxxxxxxx cpypn. */ - return 2743; + return 2754; } else { @@ -19415,7 +19536,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1100xxxxxxxxxxxx cpyen. */ - return 2745; + return 2756; } } } @@ -19432,7 +19553,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0010xxxxxxxxxxxx cpyprt. */ - return 2758; + return 2769; } else { @@ -19440,7 +19561,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0010xxxxxxxxxxxx cpyert. */ - return 2760; + return 2771; } } else @@ -19451,7 +19572,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1010xxxxxxxxxxxx cpyprtrn. */ - return 2764; + return 2775; } else { @@ -19459,7 +19580,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1010xxxxxxxxxxxx cpyertrn. */ - return 2766; + return 2777; } } } @@ -19473,7 +19594,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0110xxxxxxxxxxxx cpyprtwn. */ - return 2761; + return 2772; } else { @@ -19481,7 +19602,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0110xxxxxxxxxxxx cpyertwn. */ - return 2763; + return 2774; } } else @@ -19492,7 +19613,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1110xxxxxxxxxxxx cpyprtn. */ - return 2767; + return 2778; } else { @@ -19500,7 +19621,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1110xxxxxxxxxxxx cpyertn. */ - return 2769; + return 2780; } } } @@ -19520,7 +19641,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0001xxxxxxxxxxxx cpypwt. */ - return 2746; + return 2757; } else { @@ -19528,7 +19649,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0001xxxxxxxxxxxx cpyewt. */ - return 2748; + return 2759; } } else @@ -19539,7 +19660,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1001xxxxxxxxxxxx cpypwtrn. */ - return 2752; + return 2763; } else { @@ -19547,7 +19668,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1001xxxxxxxxxxxx cpyewtrn. */ - return 2754; + return 2765; } } } @@ -19561,7 +19682,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0101xxxxxxxxxxxx cpypwtwn. */ - return 2749; + return 2760; } else { @@ -19569,7 +19690,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0101xxxxxxxxxxxx cpyewtwn. */ - return 2751; + return 2762; } } else @@ -19580,7 +19701,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1101xxxxxxxxxxxx cpypwtn. */ - return 2755; + return 2766; } else { @@ -19588,7 +19709,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1101xxxxxxxxxxxx cpyewtn. */ - return 2757; + return 2768; } } } @@ -19605,7 +19726,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0011xxxxxxxxxxxx cpypt. */ - return 2770; + return 2781; } else { @@ -19613,7 +19734,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0011xxxxxxxxxxxx cpyet. */ - return 2772; + return 2783; } } else @@ -19624,7 +19745,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1011xxxxxxxxxxxx cpyptrn. */ - return 2776; + return 2787; } else { @@ -19632,7 +19753,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1011xxxxxxxxxxxx cpyetrn. */ - return 2778; + return 2789; } } } @@ -19646,7 +19767,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0111xxxxxxxxxxxx cpyptwn. */ - return 2773; + return 2784; } else { @@ -19654,7 +19775,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0111xxxxxxxxxxxx cpyetwn. */ - return 2775; + return 2786; } } else @@ -19665,7 +19786,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1111xxxxxxxxxxxx cpyptn. */ - return 2779; + return 2790; } else { @@ -19673,7 +19794,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1111xxxxxxxxxxxx cpyetn. */ - return 2781; + return 2792; } } } @@ -19707,7 +19828,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0000xxxxxxxxxxxx cpym. */ - return 2735; + return 2746; } else { @@ -19715,7 +19836,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0000xxxxxxxxxxxx setgp. */ - return 2794; + return 2805; } } else @@ -19726,7 +19847,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx1000xxxxxxxxxxxx cpymrn. */ - return 2741; + return 2752; } else { @@ -19734,7 +19855,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx1000xxxxxxxxxxxx setge. */ - return 2796; + return 2807; } } } @@ -19748,7 +19869,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0100xxxxxxxxxxxx cpymwn. */ - return 2738; + return 2749; } else { @@ -19756,7 +19877,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0100xxxxxxxxxxxx setgm. */ - return 2795; + return 2806; } } else @@ -19765,7 +19886,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011101x1xxxxxx1100xxxxxxxxxxxx cpymn. */ - return 2744; + return 2755; } } } @@ -19781,7 +19902,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0010xxxxxxxxxxxx cpymrt. */ - return 2759; + return 2770; } else { @@ -19789,7 +19910,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0010xxxxxxxxxxxx setgpn. */ - return 2800; + return 2811; } } else @@ -19800,7 +19921,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx1010xxxxxxxxxxxx cpymrtrn. */ - return 2765; + return 2776; } else { @@ -19808,7 +19929,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx1010xxxxxxxxxxxx setgen. */ - return 2802; + return 2813; } } } @@ -19822,7 +19943,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0110xxxxxxxxxxxx cpymrtwn. */ - return 2762; + return 2773; } else { @@ -19830,7 +19951,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0110xxxxxxxxxxxx setgmn. */ - return 2801; + return 2812; } } else @@ -19839,7 +19960,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011101x1xxxxxx1110xxxxxxxxxxxx cpymrtn. */ - return 2768; + return 2779; } } } @@ -19858,7 +19979,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0001xxxxxxxxxxxx cpymwt. */ - return 2747; + return 2758; } else { @@ -19866,7 +19987,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0001xxxxxxxxxxxx setgpt. */ - return 2797; + return 2808; } } else @@ -19877,7 +19998,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx1001xxxxxxxxxxxx cpymwtrn. */ - return 2753; + return 2764; } else { @@ -19885,7 +20006,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx1001xxxxxxxxxxxx setget. */ - return 2799; + return 2810; } } } @@ -19899,7 +20020,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0101xxxxxxxxxxxx cpymwtwn. */ - return 2750; + return 2761; } else { @@ -19907,7 +20028,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0101xxxxxxxxxxxx setgmt. */ - return 2798; + return 2809; } } else @@ -19916,7 +20037,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011101x1xxxxxx1101xxxxxxxxxxxx cpymwtn. */ - return 2756; + return 2767; } } } @@ -19932,7 +20053,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0011xxxxxxxxxxxx cpymt. */ - return 2771; + return 2782; } else { @@ -19940,7 +20061,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0011xxxxxxxxxxxx setgptn. */ - return 2803; + return 2814; } } else @@ -19951,7 +20072,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx1011xxxxxxxxxxxx cpymtrn. */ - return 2777; + return 2788; } else { @@ -19959,7 +20080,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx1011xxxxxxxxxxxx setgetn. */ - return 2805; + return 2816; } } } @@ -19973,7 +20094,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0111xxxxxxxxxxxx cpymtwn. */ - return 2774; + return 2785; } else { @@ -19981,7 +20102,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0111xxxxxxxxxxxx setgmtn. */ - return 2804; + return 2815; } } else @@ -19990,7 +20111,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011101x1xxxxxx1111xxxxxxxxxxxx cpymtn. */ - return 2780; + return 2791; } } } @@ -20157,7 +20278,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110xx0xxxxx1x1001xxxxxxxxxx smmla. */ - return 2661; + return 2672; } } } @@ -20190,7 +20311,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110xx0xxxxx1x0101xxxxxxxxxx sdot. */ - return 2587; + return 2598; } } else @@ -20264,7 +20385,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110xx0xxxxx1x1011xxxxxxxxxx usmmla. */ - return 2663; + return 2674; } } } @@ -20297,7 +20418,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110xx0xxxxx1x0111xxxxxxxxxx usdot. */ - return 2664; + return 2675; } } else @@ -20344,7 +20465,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110000xxxxxxxxxxxxxxxxxxxxx eor3. */ - return 2594; + return 2605; } else { @@ -20352,7 +20473,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110100xxxxxxxxxxxxxxxxxxxxx xar. */ - return 2596; + return 2607; } } else @@ -20363,7 +20484,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110x10xxxxx0xxxxxxxxxxxxxxx sm3ss1. */ - return 2598; + return 2609; } else { @@ -20377,7 +20498,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110010xxxxx1xxx00xxxxxxxxxx sm3tt1a. */ - return 2599; + return 2610; } else { @@ -20385,7 +20506,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110110xxxxx1xxx00xxxxxxxxxx sha512su0. */ - return 2592; + return 2603; } } else @@ -20394,7 +20515,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110x10xxxxx1xxx10xxxxxxxxxx sm3tt2a. */ - return 2601; + return 2612; } } else @@ -20407,7 +20528,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110010xxxxx1xxx01xxxxxxxxxx sm3tt1b. */ - return 2600; + return 2611; } else { @@ -20415,7 +20536,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110110xxxxx1xxx01xxxxxxxxxx sm4e. */ - return 2605; + return 2616; } } else @@ -20424,7 +20545,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110x10xxxxx1xxx11xxxxxxxxxx sm3tt2b. */ - return 2602; + return 2613; } } } @@ -20605,7 +20726,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx101110xx0xxxxx100101xxxxxxxxxx udot. */ - return 2586; + return 2597; } } else @@ -20636,7 +20757,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx101110xx0xxxxx101x01xxxxxxxxxx ummla. */ - return 2662; + return 2673; } else { @@ -20655,7 +20776,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx101110xx0xxxxx1x1011xxxxxxxxxx bfmmla. */ - return 2678; + return 2689; } else { @@ -20665,7 +20786,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx1011100x0xxxxx1x1111xxxxxxxxxx bfdot. */ - return 2676; + return 2687; } else { @@ -20675,7 +20796,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x01011101x0xxxxx1x1111xxxxxxxxxx bfmlalb. */ - return 2683; + return 2694; } else { @@ -20683,7 +20804,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11011101x0xxxxx1x1111xxxxxxxxxx bfmlalt. */ - return 2682; + return 2693; } } } @@ -21267,7 +21388,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000011101x1xxxx1011010xxxxxxxxxx bfcvtn. */ - return 2679; + return 2690; } else { @@ -21275,7 +21396,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010011101x1xxxx1011010xxxxxxxxxx bfcvtn2. */ - return 2680; + return 2691; } } } @@ -21593,7 +21714,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110xx1xxxxx0xxxxxxxxxxxxxxx bcax. */ - return 2597; + return 2608; } } else @@ -22204,7 +22325,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 11001110xx1xxxxx100000xxxxxxxxxx sha512h. */ - return 2590; + return 2601; } } } @@ -22256,7 +22377,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 11001110xx1xxxxx110000xxxxxxxxxx sm3partw1. */ - return 2603; + return 2614; } } } @@ -22499,7 +22620,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110xx1xxxxx100010xxxxxxxxxx sha512su1. */ - return 2593; + return 2604; } } else @@ -22575,7 +22696,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x0011100x1xxxxx110010xxxxxxxxxx sm4ekey. */ - return 2606; + return 2617; } } else @@ -23401,7 +23522,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110xx1xxxxx100001xxxxxxxxxx sha512h2. */ - return 2591; + return 2602; } } else @@ -23433,7 +23554,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x0011100x1xxxxx110001xxxxxxxxxx sm3partw2. */ - return 2604; + return 2615; } } else @@ -23673,7 +23794,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110xx1xxxxx100011xxxxxxxxxx rax1. */ - return 2595; + return 2606; } } else @@ -23705,7 +23826,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x01011100x1xxxxx110011xxxxxxxxxx fmlal2. */ - return 2609; + return 2620; } else { @@ -23713,7 +23834,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11011100x1xxxxx110011xxxxxxxxxx fmlal2. */ - return 2613; + return 2624; } } } @@ -23735,7 +23856,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x01011101x1xxxxx110011xxxxxxxxxx fmlsl2. */ - return 2610; + return 2621; } else { @@ -23743,7 +23864,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11011101x1xxxxx110011xxxxxxxxxx fmlsl2. */ - return 2614; + return 2625; } } } @@ -23782,7 +23903,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x00011100x1xxxxx111011xxxxxxxxxx fmlal. */ - return 2607; + return 2618; } else { @@ -23790,7 +23911,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10011100x1xxxxx111011xxxxxxxxxx fmlal. */ - return 2611; + return 2622; } } else @@ -23812,7 +23933,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x00011101x1xxxxx111011xxxxxxxxxx fmlsl. */ - return 2608; + return 2619; } else { @@ -23820,7 +23941,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10011101x1xxxxx111011xxxxxxxxxx fmlsl. */ - return 2612; + return 2623; } } else @@ -25628,7 +25749,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0001111xxxxxxxx0000x0xxxxxxxxxx fmlal. */ - return 2615; + return 2626; } else { @@ -25636,7 +25757,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1001111xxxxxxxx0000x0xxxxxxxxxx fmlal. */ - return 2619; + return 2630; } } else @@ -25658,7 +25779,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0001111xxxxxxxx0100x0xxxxxxxxxx fmlsl. */ - return 2616; + return 2627; } else { @@ -25666,7 +25787,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1001111xxxxxxxx0100x0xxxxxxxxxx fmlsl. */ - return 2620; + return 2631; } } else @@ -26172,7 +26293,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0101111xxxxxxxx1000x0xxxxxxxxxx fmlal2. */ - return 2617; + return 2628; } else { @@ -26180,7 +26301,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1101111xxxxxxxx1000x0xxxxxxxxxx fmlal2. */ - return 2621; + return 2632; } } } @@ -26202,7 +26323,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0101111xxxxxxxx1100x0xxxxxxxxxx fmlsl2. */ - return 2618; + return 2629; } else { @@ -26210,7 +26331,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1101111xxxxxxxx1100x0xxxxxxxxxx fmlsl2. */ - return 2622; + return 2633; } } } @@ -26266,7 +26387,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx001111xxxxxxxx1110x0xxxxxxxxxx sdot. */ - return 2589; + return 2600; } else { @@ -26274,7 +26395,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx101111xxxxxxxx1110x0xxxxxxxxxx udot. */ - return 2588; + return 2599; } } } @@ -26377,7 +26498,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx00111100xxxxxx1111x0xxxxxxxxxx sudot. */ - return 2666; + return 2677; } else { @@ -26385,7 +26506,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx00111110xxxxxx1111x0xxxxxxxxxx usdot. */ - return 2665; + return 2676; } } else @@ -26396,7 +26517,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx00111101xxxxxx1111x0xxxxxxxxxx bfdot. */ - return 2677; + return 2688; } else { @@ -26406,7 +26527,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x000111111xxxxxx1111x0xxxxxxxxxx bfmlalb. */ - return 2685; + return 2696; } else { @@ -26414,7 +26535,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x100111111xxxxxx1111x0xxxxxxxxxx bfmlalt. */ - return 2684; + return 2695; } } } @@ -26903,24 +27024,24 @@ aarch64_find_next_opcode (const aarch64_opcode *opcode) { case 2389: value = 2391; break; /* mov --> mova. */ case 2391: return NULL; /* mova --> NULL. */ - case 2499: value = 2507; break; /* mov --> mova. */ - case 2507: return NULL; /* mova --> NULL. */ - case 2497: value = 2505; break; /* mov --> mova. */ - case 2505: return NULL; /* mova --> NULL. */ - case 2500: value = 2508; break; /* mov --> mova. */ - case 2508: return NULL; /* mova --> NULL. */ - case 2498: value = 2506; break; /* mov --> mova. */ - case 2506: return NULL; /* mova --> NULL. */ case 2388: value = 2390; break; /* mov --> mova. */ case 2390: return NULL; /* mova --> NULL. */ - case 2495: value = 2503; break; /* mov --> mova. */ - case 2503: return NULL; /* mova --> NULL. */ - case 2493: value = 2501; break; /* mov --> mova. */ - case 2501: return NULL; /* mova --> NULL. */ - case 2496: value = 2504; break; /* mov --> mova. */ - case 2504: return NULL; /* mova --> NULL. */ - case 2494: value = 2502; break; /* mov --> mova. */ - case 2502: return NULL; /* mova --> NULL. */ + case 2506: value = 2514; break; /* mov --> mova. */ + case 2514: return NULL; /* mova --> NULL. */ + case 2502: value = 2510; break; /* mov --> mova. */ + case 2510: return NULL; /* mova --> NULL. */ + case 2504: value = 2512; break; /* mov --> mova. */ + case 2512: return NULL; /* mova --> NULL. */ + case 2500: value = 2508; break; /* mov --> mova. */ + case 2508: return NULL; /* mova --> NULL. */ + case 2507: value = 2515; break; /* mov --> mova. */ + case 2515: return NULL; /* mova --> NULL. */ + case 2503: value = 2511; break; /* mov --> mova. */ + case 2511: return NULL; /* mova --> NULL. */ + case 2505: value = 2513; break; /* mov --> mova. */ + case 2513: return NULL; /* mova --> NULL. */ + case 2501: value = 2509; break; /* mov --> mova. */ + case 2509: return NULL; /* mova --> NULL. */ case 2393: value = 2398; break; /* ld1b --> ld1b. */ case 2398: return NULL; /* ld1b --> NULL. */ case 2395: value = 2400; break; /* ld1w --> ld1w. */ @@ -26942,11 +27063,11 @@ aarch64_find_next_opcode (const aarch64_opcode *opcode) case 2407: value = 2412; break; /* st1q --> st1q. */ case 2412: return NULL; /* st1q --> NULL. */ case 12: value = 19; break; /* add --> addg. */ - case 19: value = 2807; break; /* addg --> smax. */ - case 2807: value = 2808; break; /* smax --> umax. */ - case 2808: value = 2809; break; /* umax --> smin. */ - case 2809: value = 2810; break; /* smin --> umin. */ - case 2810: return NULL; /* umin --> NULL. */ + case 19: value = 2818; break; /* addg --> smax. */ + case 2818: value = 2819; break; /* smax --> umax. */ + case 2819: value = 2820; break; /* umax --> smin. */ + case 2820: value = 2821; break; /* smin --> umin. */ + case 2821: return NULL; /* umin --> NULL. */ case 16: value = 20; break; /* sub --> subg. */ case 20: return NULL; /* subg --> NULL. */ case 971: value = 975; break; /* stnp --> stp. */ @@ -27104,8 +27225,8 @@ aarch64_find_next_opcode (const aarch64_opcode *opcode) case 824: return NULL; /* fsqrt --> NULL. */ case 832: value = 833; break; /* frintz --> frintz. */ case 833: return NULL; /* frintz --> NULL. */ - case 825: value = 2681; break; /* fcvt --> bfcvt. */ - case 2681: return NULL; /* bfcvt --> NULL. */ + case 825: value = 2692; break; /* fcvt --> bfcvt. */ + case 2692: return NULL; /* bfcvt --> NULL. */ case 834: value = 835; break; /* frinta --> frinta. */ case 835: return NULL; /* frinta --> NULL. */ case 836: value = 837; break; /* frintx --> frintx. */ @@ -27633,7 +27754,7 @@ aarch64_extract_operand (const aarch64_operand *self, case 33: case 34: case 35: - case 247: + case 256: return aarch64_ext_reglane (self, info, code, inst, errors); case 36: return aarch64_ext_reglist (self, info, code, inst, errors); @@ -27680,11 +27801,12 @@ aarch64_extract_operand (const aarch64_operand *self, case 193: case 194: case 236: - case 244: - case 245: - case 246: + case 250: case 251: - case 252: + case 253: + case 255: + case 260: + case 261: return aarch64_ext_imm (self, info, code, inst, errors); case 44: case 45: @@ -27755,6 +27877,8 @@ aarch64_extract_operand (const aarch64_operand *self, case 107: return aarch64_ext_prfop (self, info, code, inst, errors); case 108: + case 252: + case 254: return aarch64_ext_none (self, info, code, inst, errors); case 109: return aarch64_ext_hint (self, info, code, inst, errors); @@ -27867,6 +27991,12 @@ aarch64_extract_operand (const aarch64_operand *self, return aarch64_ext_sme_za_hv_tiles_range (self, info, code, inst, errors); case 234: case 235: + case 244: + case 245: + case 246: + case 247: + case 248: + case 249: return aarch64_ext_simple_index (self, info, code, inst, errors); case 238: case 239: @@ -27878,9 +28008,9 @@ aarch64_extract_operand (const aarch64_operand *self, return aarch64_ext_sme_sm_za (self, info, code, inst, errors); case 243: return aarch64_ext_sme_pred_reg_with_index (self, info, code, inst, errors); - case 248: - case 249: - case 250: + case 257: + case 258: + case 259: return aarch64_ext_x0_to_x30 (self, info, code, inst, errors); default: assert (0); abort (); } diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c index a2f69186355..0475adbc31d 100644 --- a/opcodes/aarch64-dis.c +++ b/opcodes/aarch64-dis.c @@ -702,6 +702,8 @@ aarch64_ext_imm (const aarch64_operand *self, aarch64_opnd_info *info, if (operand_need_shift_by_two (self)) imm <<= 2; + else if (operand_need_shift_by_three (self)) + imm <<= 3; else if (operand_need_shift_by_four (self)) imm <<= 4; @@ -3072,6 +3074,19 @@ aarch64_decode_variant_using_iclass (aarch64_inst *inst) } break; + case sme_size_12_bhs: + variant = extract_field (FLD_SME_size_12, inst->value, 0); + if (variant >= 3) + return false; + break; + + case sme_size_12_hs: + variant = extract_field (FLD_SME_size_12, inst->value, 0); + if (variant != 1 && variant != 2) + return false; + variant -= 1; + break; + case sme_size_22: variant = extract_field (FLD_SME_size_22, inst->value, 0); break; diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c index 9f2b670c49a..21e06e6114f 100644 --- a/opcodes/aarch64-opc-2.c +++ b/opcodes/aarch64-opc-2.c @@ -268,8 +268,17 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_ADDRESS, "SME_ADDR_RI_U4xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_imm4_0}, "memory offset"}, {AARCH64_OPND_CLASS_ADDRESS, "SME_SM_ZA", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm}, "streaming mode"}, {AARCH64_OPND_CLASS_SVE_REG, "SME_PnT_Wm_imm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rm,FLD_SVE_Pn,FLD_SME_i1,FLD_SME_tszh,FLD_SME_tszl}, "Source scalable predicate register with index "}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX1_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm1_16}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX2_15", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm2_15}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX2_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm2_16}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX3_14", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm3_14}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX3_15", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm3_15}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX4_14", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm4_14}, "an indexed SVE vector register"}, {AARCH64_OPND_CLASS_IMMEDIATE, "SME_VLxN_10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_VL_10}, "VLx2 or VLx4"}, {AARCH64_OPND_CLASS_IMMEDIATE, "SME_VLxN_13", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_VL_13}, "VLx2 or VLx4"}, + {AARCH64_OPND_CLASS_SYSTEM, "SME_ZT0", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "ZT0"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "SME_ZT0_INDEX", OPD_F_SHIFT_BY_3 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm3_12}, "a ZT0 index"}, + {AARCH64_OPND_CLASS_SYSTEM, "SME_ZT0_LIST", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "{ ZT0 }"}, {AARCH64_OPND_CLASS_IMMEDIATE, "TME_UIMM16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16_5}, "a 16-bit unsigned immediate for TME tcancel"}, {AARCH64_OPND_CLASS_SIMD_ELEMENT, "SM3_IMM2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SM3_imm2}, "an indexed SM3 vector immediate"}, {AARCH64_OPND_CLASS_INT_REG, "MOPS_ADDR_Rd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "a register destination address with writeback"}, diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 3b4397d0f06..cd185b8af29 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -249,6 +249,7 @@ const aarch64_field fields[] = { 0, 3 }, /* SME_Zt3: lower 3 bits of Zt, bits [2:0]. */ { 0, 2 }, /* SME_Zt2: lower 2 bits of Zt, bits [1:0]. */ { 23, 1 }, /* SME_i1: immediate field, bit 23. */ + { 12, 2 }, /* SME_size_12: bits [13:12]. */ { 22, 2 }, /* SME_size_22: size<1>, size<0> class field, [23:22]. */ { 22, 1 }, /* SME_tszh: immediate and qualifier field, bit 22. */ { 18, 3 }, /* SME_tszl: immediate and qualifier field, bits [20:18]. */ @@ -318,14 +319,21 @@ const aarch64_field fields[] = { 5, 5 }, /* defgh: d:e:f:g:h bits in AdvSIMD modified immediate. */ { 21, 2 }, /* hw: in move wide constant instructions. */ { 8, 1 }, /* imm1_8: general immediate in bits [8]. */ + { 16, 1 }, /* imm1_16: general immediate in bits [16]. */ { 8, 2 }, /* imm2_8: general immediate in bits [9:8]. */ + { 15, 2 }, /* imm2_15: 2-bit immediate, bits [16:15] */ + { 16, 2 }, /* imm2_16: 2-bit immediate, bits [17:16] */ { 0, 3 }, /* imm3_0: general immediate in bits [2:0]. */ { 5, 3 }, /* imm3_5: general immediate in bits [7:5]. */ { 10, 3 }, /* imm3_10: in add/sub extended reg instructions. */ + { 12, 3 }, /* imm3_12: general immediate in bits [14:12]. */ + { 14, 3 }, /* imm3_14: general immediate in bits [16:14]. */ + { 15, 3 }, /* imm3_15: general immediate in bits [17:15]. */ { 0, 4 }, /* imm4_0: in rmif instructions. */ { 5, 4 }, /* imm4_5: in SME instructions. */ { 10, 4 }, /* imm4_10: in adddg/subg instructions. */ { 11, 4 }, /* imm4_11: in advsimd ext and advsimd ins instructions. */ + { 14, 4 }, /* imm4_14: general immediate in bits [17:14]. */ { 16, 5 }, /* imm5: in conditional compare (immediate) instructions. */ { 10, 6 }, /* imm6_10: in add/sub reg shifted instructions. */ { 15, 6 }, /* imm6_15: in rmif instructions. */ @@ -1744,6 +1752,18 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, return 0; break; + case AARCH64_OPND_SME_Zn_INDEX1_16: + case AARCH64_OPND_SME_Zn_INDEX2_15: + case AARCH64_OPND_SME_Zn_INDEX2_16: + case AARCH64_OPND_SME_Zn_INDEX3_14: + case AARCH64_OPND_SME_Zn_INDEX3_15: + case AARCH64_OPND_SME_Zn_INDEX4_14: + size = get_operand_fields_width (get_operand_from_code (type)) - 5; + if (!check_reglane (opnd, mismatch_detail, idx, "z", 0, 31, + 0, (1 << size) - 1)) + return 0; + break; + case AARCH64_OPND_SME_PnT_Wm_imm: size = aarch64_get_qualifier_esize (opnd->qualifier); max_value = 16 / size - 1; @@ -2862,6 +2882,20 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, } break; + case AARCH64_OPND_SME_ZT0_INDEX: + if (!value_in_range_p (opnd->imm.value, 0, 56)) + { + set_elem_idx_out_of_range_error (mismatch_detail, idx, 0, 56); + return 0; + } + if (opnd->imm.value % 8 != 0) + { + set_other_error (mismatch_detail, idx, + _("byte index must be a multiple of 8")); + return 0; + } + break; + default: break; } @@ -3867,9 +3901,17 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, case AARCH64_OPND_SVE_Zm4_11_INDEX: case AARCH64_OPND_SVE_Zm4_INDEX: case AARCH64_OPND_SVE_Zn_INDEX: + case AARCH64_OPND_SME_Zn_INDEX1_16: + case AARCH64_OPND_SME_Zn_INDEX2_15: + case AARCH64_OPND_SME_Zn_INDEX2_16: + case AARCH64_OPND_SME_Zn_INDEX3_14: + case AARCH64_OPND_SME_Zn_INDEX3_15: + case AARCH64_OPND_SME_Zn_INDEX4_14: snprintf (buf, size, "%s[%s]", - style_reg (styler, "z%d.%s", opnd->reglane.regno, - aarch64_get_qualifier_name (opnd->qualifier)), + (opnd->qualifier == AARCH64_OPND_QLF_NIL + ? style_reg (styler, "z%d", opnd->reglane.regno) + : style_reg (styler, "z%d.%s", opnd->reglane.regno, + aarch64_get_qualifier_name (opnd->qualifier))), style_imm (styler, "%" PRIi64, opnd->reglane.index)); break; @@ -4450,6 +4492,19 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, snprintf (buf, size, "%s", style_sub_mnem (styler, "csync")); break; + case AARCH64_OPND_SME_ZT0: + snprintf (buf, size, "%s", style_reg (styler, "zt0")); + break; + + case AARCH64_OPND_SME_ZT0_INDEX: + snprintf (buf, size, "%s[%s]", style_reg (styler, "zt0"), + style_imm (styler, "%d", (int) opnd->imm.value)); + break; + + case AARCH64_OPND_SME_ZT0_LIST: + snprintf (buf, size, "{%s}", style_reg (styler, "zt0")); + break; + case AARCH64_OPND_BTI_TARGET: if ((HINT_FLAG (opnd->hint_option->value) & HINT_OPD_F_NOPRINT) == 0) snprintf (buf, size, "%s", diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h index e505786e60e..8422be4c9db 100644 --- a/opcodes/aarch64-opc.h +++ b/opcodes/aarch64-opc.h @@ -70,6 +70,7 @@ enum aarch64_field_kind FLD_SME_Zt3, FLD_SME_Zt2, FLD_SME_i1, + FLD_SME_size_12, FLD_SME_size_22, FLD_SME_tszh, FLD_SME_tszl, @@ -139,14 +140,21 @@ enum aarch64_field_kind FLD_defgh, FLD_hw, FLD_imm1_8, + FLD_imm1_16, FLD_imm2_8, + FLD_imm2_15, + FLD_imm2_16, FLD_imm3_0, FLD_imm3_5, FLD_imm3_10, + FLD_imm3_12, + FLD_imm3_14, + FLD_imm3_15, FLD_imm4_0, FLD_imm4_5, FLD_imm4_10, FLD_imm4_11, + FLD_imm4_14, FLD_imm5, FLD_imm6_10, FLD_imm6_15, @@ -242,7 +250,10 @@ verify_constraints (const struct aarch64_inst *, const aarch64_insn, bfd_vma, #define OPD_F_OD_MASK 0x000001e0 /* Operand-dependent data. */ #define OPD_F_OD_LSB 5 #define OPD_F_NO_ZR 0x00000200 /* ZR index not allowed. */ -#define OPD_F_SHIFT_BY_4 0x00000400 /* Need to left shift the field +#define OPD_F_SHIFT_BY_3 0x00000400 /* Need to left shift the field + value by 3 to get the value + of an immediate operand. */ +#define OPD_F_SHIFT_BY_4 0x00000800 /* Need to left shift the field value by 4 to get the value of an immediate operand. */ @@ -329,6 +340,12 @@ operand_need_shift_by_two (const aarch64_operand *operand) return (operand->flags & OPD_F_SHIFT_BY_2) != 0; } +static inline bool +operand_need_shift_by_three (const aarch64_operand *operand) +{ + return (operand->flags & OPD_F_SHIFT_BY_3) != 0; +} + static inline bool operand_need_shift_by_four (const aarch64_operand *operand) { diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index cff35b127bd..0f881681aab 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -1755,6 +1755,10 @@ { \ QLF3(NIL,NIL,S_S), \ } +#define OP_SVE_UX \ +{ \ + QLF2(NIL,X), \ +} #define OP_SVE_VMR_BHSD \ { \ QLF3(S_B,P_M,W), \ @@ -1905,6 +1909,12 @@ QLF3(S_S,NIL,W), \ QLF3(S_D,NIL,X), \ } +#define OP_SVE_VUU_BHS \ +{ \ + QLF3(S_B,NIL,NIL), \ + QLF3(S_H,NIL,NIL), \ + QLF3(S_S,NIL,NIL), \ +} #define OP_SVE_VUU_BHSD \ { \ QLF3(S_B,NIL,NIL), \ @@ -1919,6 +1929,11 @@ QLF4(S_S,NIL,S_S,S_S), \ QLF4(S_D,NIL,S_D,S_D), \ } +#define OP_SVE_VUU_HS \ +{ \ + QLF3(S_H,NIL,NIL), \ + QLF3(S_S,NIL,NIL), \ +} #define OP_SVE_VUVV_HSD \ { \ QLF4(S_H,NIL,S_H,S_H), \ @@ -5375,6 +5390,13 @@ const struct aarch64_opcode aarch64_opcode_table[] = SME2_INSN ("ldnt1w", 0xa000c001, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SZU, 0, 0), SME2_INSN ("ldnt1w", 0xa1004008, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SZU, 0, 0), SME2_INSN ("ldnt1w", 0xa100c008, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SZU, 0, 0), + SME2_INSN ("ldr", 0xe11f8000, 0xfffffc1f, sme_misc, 0, OP2 (SME_ZT0, SIMD_ADDR_SIMPLE), {}, 0, 0), + SME2_INSN ("luti2", 0xc0cc0000, 0xfffc0c00, sme_size_12_bhs, 0, OP3 (SVE_Zd, SME_ZT0, SME_Zn_INDEX4_14), OP_SVE_VUU_BHS, 0, 0), + SME2_INSN ("luti2", 0xc08c4000, 0xfffc4c01, sme_size_12_bhs, 0, OP3 (SME_Zdnx2, SME_ZT0, SME_Zn_INDEX3_15), OP_SVE_VUU_BHS, 0, 0), + SME2_INSN ("luti2", 0xc08c8000, 0xfffccc03, sme_size_12_bhs, 0, OP3 (SME_Zdnx4, SME_ZT0, SME_Zn_INDEX2_16), OP_SVE_VUU_BHS, 0, 0), + SME2_INSN ("luti4", 0xc0ca0000, 0xfffe0c00, sme_size_12_bhs, 0, OP3 (SVE_Zd, SME_ZT0, SME_Zn_INDEX3_14), OP_SVE_VUU_BHS, 0, 0), + SME2_INSN ("luti4", 0xc08a4000, 0xfffe4c01, sme_size_12_bhs, 0, OP3 (SME_Zdnx2, SME_ZT0, SME_Zn_INDEX2_15), OP_SVE_VUU_BHS, 0, 0), + SME2_INSN ("luti4", 0xc08a8000, 0xfffecc03, sme_size_12_hs, 0, OP3 (SME_Zdnx4, SME_ZT0, SME_Zn_INDEX1_16), OP_SVE_VUU_HS, 0, 0), SME2_INSN ("mov", 0xc0060800, 0xffff9f01, sme2_mov, 0, OP2 (SME_Zdnx2, SME_ZA_array_off3_5), OP_SVE_VV_BHSD, F_OD (2), 0), SME2_INSN ("mov", 0xc0060c00, 0xffff9f03, sme2_mov, 0, OP2 (SME_Zdnx4, SME_ZA_array_off3_5), OP_SVE_VV_BHSD, F_OD (4), 0), SME2_INSN ("mov", 0xc0060000, 0xff3f1f01, sme_size_22, 0, OP2 (SME_Zdnx2, SME_ZA_HV_idx_srcxN), OP_SVE_VV_BHSDQ, F_OD (2), 0), @@ -5391,6 +5413,8 @@ const struct aarch64_opcode aarch64_opcode_table[] = SME2_INSN ("mova", 0xc0040c00, 0xffff9c78, sme2_mov, 0, OP2 (SME_ZA_array_off3_0, SME_Znx4), OP_SVE_VV_BHSD, F_OD (4), 0), SME2_INSN ("mova", 0xc0040000, 0xff3f1c38, sme_size_22, 0, OP2 (SME_ZA_HV_idx_destxN, SME_Znx2), OP_SVE_VV_BHSDQ, F_OD (2), 0), SME2_INSN ("mova", 0xc0040400, 0xff3f1c78, sme_size_22, 0, OP2 (SME_ZA_HV_idx_destxN, SME_Znx4), OP_SVE_VV_BHSDQ, F_OD (4), 0), + SME2_INSN ("movt", 0xc04e03e0, 0xffff8fe0, sme_misc, 0, OP2 (SME_ZT0_INDEX, Rt), OP_SVE_UX, 0, 0), + SME2_INSN ("movt", 0xc04c03e0, 0xffff8fe0, sme_misc, 0, OP2 (Rt, SME_ZT0_INDEX), OP_SVE_XU, 0, 0), SME2_INSN ("pext", 0x25207010, 0xff3ffc10, sme_size_22, 0, OP2 (SVE_Pd, SME_PNn3_INDEX2), OP_SVE_VU_BHSD, 0, 0), SME2_INSN ("pext", 0x25207410, 0xff3ffe10, sme_size_22, 0, OP2 (SME_PdxN, SME_PNn3_INDEX1), OP_SVE_VU_BHSD, F_OD (2), 0), SME2_INSN ("ptrue", 0x25207810, 0xff3ffff8, sme_size_22, 0, OP1 (SME_PNd3), OP_SVE_V_BHSD, 0, 0), @@ -5460,6 +5484,7 @@ const struct aarch64_opcode aarch64_opcode_table[] = SME2_INSN ("stnt1w", 0xa020c001, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SUU, 0, 0), SME2_INSN ("stnt1w", 0xa1204008, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SUU, 0, 0), SME2_INSN ("stnt1w", 0xa120c008, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SUU, 0, 0), + SME2_INSN ("str", 0xe13f8000, 0xfffffc1f, sme_misc, 0, OP2 (SME_ZT0, SIMD_ADDR_SIMPLE), {}, 0, 0), SME2_INSN ("whilege", 0x25204010, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0), SME2_INSN ("whilegt", 0x25204018, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0), SME2_INSN ("whilehi", 0x25204818, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0), @@ -5468,6 +5493,7 @@ const struct aarch64_opcode aarch64_opcode_table[] = SME2_INSN ("whilelo", 0x25204c10, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0), SME2_INSN ("whilels", 0x25204c18, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0), SME2_INSN ("whilelt", 0x25204410, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0), + SME2_INSN ("zero", 0xc0480001, 0xffffffff, sme_misc, 0, OP1 (SME_ZT0_LIST), {}, 0, 0), /* SIMD Dot Product (optional in v8.2-A). */ DOT_INSN ("udot", 0x2e009400, 0xbf20fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ), @@ -6178,10 +6204,26 @@ const struct aarch64_opcode aarch64_opcode_table[] = Y(SVE_REG, sme_pred_reg_with_index, "SME_PnT_Wm_imm", 0, \ F(FLD_SME_Rm,FLD_SVE_Pn,FLD_SME_i1,FLD_SME_tszh,FLD_SME_tszl), \ "Source scalable predicate register with index ") \ + Y(SVE_REG, simple_index, "SME_Zn_INDEX1_16", 0, \ + F(FLD_SVE_Zn, FLD_imm1_16), "an indexed SVE vector register") \ + Y(SVE_REG, simple_index, "SME_Zn_INDEX2_15", 0, \ + F(FLD_SVE_Zn, FLD_imm2_15), "an indexed SVE vector register") \ + Y(SVE_REG, simple_index, "SME_Zn_INDEX2_16", 0, \ + F(FLD_SVE_Zn, FLD_imm2_16), "an indexed SVE vector register") \ + Y(SVE_REG, simple_index, "SME_Zn_INDEX3_14", 0, \ + F(FLD_SVE_Zn, FLD_imm3_14), "an indexed SVE vector register") \ + Y(SVE_REG, simple_index, "SME_Zn_INDEX3_15", 0, \ + F(FLD_SVE_Zn, FLD_imm3_15), "an indexed SVE vector register") \ + Y(SVE_REG, simple_index, "SME_Zn_INDEX4_14", 0, \ + F(FLD_SVE_Zn, FLD_imm4_14), "an indexed SVE vector register") \ Y(IMMEDIATE, imm, "SME_VLxN_10", 0, F(FLD_SME_VL_10), \ "VLx2 or VLx4") \ Y(IMMEDIATE, imm, "SME_VLxN_13", 0, F(FLD_SME_VL_13), \ "VLx2 or VLx4") \ + Y(SYSTEM, none, "SME_ZT0", 0, F (), "ZT0") \ + Y(IMMEDIATE, imm, "SME_ZT0_INDEX", OPD_F_SHIFT_BY_3, \ + F (FLD_imm3_12), "a ZT0 index") \ + Y(SYSTEM, none, "SME_ZT0_LIST", 0, F (), "{ ZT0 }") \ Y(IMMEDIATE, imm, "TME_UIMM16", 0, F(FLD_imm16_5), \ "a 16-bit unsigned immediate for TME tcancel") \ Y(SIMD_ELEMENT, reglane, "SM3_IMM2", 0, F(FLD_SM3_imm2), \ From patchwork Thu Mar 30 10:26:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit 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[8.43.85.97]) by mx.google.com with ESMTPS id a24-20020aa7d758000000b00501d39f793esi14712766eds.157.2023.03.30.03.56.21 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Mar 2023 03:56:22 -0700 (PDT) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=N+qFCXcd; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 6630C395BC78 for ; Thu, 30 Mar 2023 10:39:30 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 6630C395BC78 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1680172770; bh=ndTB/9CjnPRf+2sozXXo6xYfivQk5NxNQPzmPwdNQdc=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=N+qFCXcdEw9MUFgrom4oezYCPZY4yqDVFnc0YHRjOgW4CP5sIoz6CLEE0cFIP43DF paBTtjS/G5bjlvPFzQHOk070MJKmjBlJSd0WdrGg4dfMJGoi3uQuqAHVcG07Pzpwsl EHUiUJ6zviQATIcpBPTJ+O+wzZmBfzZ4lcyxhFE0= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 588D23898399 for ; Thu, 30 Mar 2023 10:27:02 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 588D23898399 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6F6C01655; Thu, 30 Mar 2023 03:27:46 -0700 (PDT) Received: from e121540-lin.manchester.arm.com (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A5A853F663; Thu, 30 Mar 2023 03:27:01 -0700 (PDT) To: binutils@sourceware.org Cc: Richard Sandiford Subject: [PATCH 11/31] aarch64: Add the SME2 ADD and SUB instructions Date: Thu, 30 Mar 2023 11:26:26 +0100 Message-Id: <20230330102646.3327818-12-richard.sandiford@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230330102646.3327818-1-richard.sandiford@arm.com> References: <20230330102646.3327818-1-richard.sandiford@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-30.3 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, SCC_10_SHORT_WORD_LINES, SCC_20_SHORT_WORD_LINES, SCC_35_SHORT_WORD_LINES, SCC_5_SHORT_WORD_LINES, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Richard Sandiford via Binutils From: Richard Sandiford Reply-To: Richard Sandiford Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761789903805785737?= X-GMAIL-MSGID: =?utf-8?q?1761789903805785737?= Add support for the SME2 ADD. SUB, FADD and FSUB instructions. SUB and FSUB have the same form as ADD and FADD, except that ADD also has a 2-operand accumulating form. The 64-bit ADD/SUB instructions require FEAT_SME_I16I64 and the 64-bit FADD/FSUB instructions require FEAT_SME_F64F64. These are the first instructions to have tied register list operands, as opposed to tied single registers. The parse_operands change prevents unsuffixed Z registers (width==-1) from being treated as though they had an Advanced SIMD-style suffix (.4s etc.). It means that: Error: expected element type rather than vector type at operand 2 -- `add za\.s\[w8,0\],{z0-z1}' becomes: Error: missing type suffix at operand 2 -- `add za\.s\[w8,0\],{z0-z1}' --- gas/config/tc-aarch64.c | 3 +- gas/testsuite/gas/aarch64/sme2-9-invalid.d | 3 + gas/testsuite/gas/aarch64/sme2-9-invalid.l | 179 +++ gas/testsuite/gas/aarch64/sme2-9-invalid.s | 128 ++ gas/testsuite/gas/aarch64/sme2-9-noarch.d | 3 + gas/testsuite/gas/aarch64/sme2-9-noarch.l | 177 +++ gas/testsuite/gas/aarch64/sme2-9.d | 185 +++ gas/testsuite/gas/aarch64/sme2-9.s | 199 +++ .../gas/aarch64/sme2-f64f64-1-invalid.d | 3 + .../gas/aarch64/sme2-f64f64-1-invalid.l | 27 + .../gas/aarch64/sme2-f64f64-1-invalid.s | 20 + .../gas/aarch64/sme2-f64f64-1-noarch.d | 3 + .../gas/aarch64/sme2-f64f64-1-noarch.l | 33 + gas/testsuite/gas/aarch64/sme2-f64f64-1.d | 41 + gas/testsuite/gas/aarch64/sme2-f64f64-1.s | 35 + .../gas/aarch64/sme2-i16i64-1-invalid.d | 3 + .../gas/aarch64/sme2-i16i64-1-invalid.l | 111 ++ .../gas/aarch64/sme2-i16i64-1-invalid.s | 86 ++ .../gas/aarch64/sme2-i16i64-1-noarch.d | 3 + .../gas/aarch64/sme2-i16i64-1-noarch.l | 57 + gas/testsuite/gas/aarch64/sme2-i16i64-1.d | 65 + gas/testsuite/gas/aarch64/sme2-i16i64-1.s | 61 + include/opcode/aarch64.h | 3 + opcodes/aarch64-asm-2.c | 51 +- opcodes/aarch64-asm.c | 2 + opcodes/aarch64-dis-2.c | 1089 ++++++++++------- opcodes/aarch64-dis.c | 2 + opcodes/aarch64-opc-2.c | 1 + opcodes/aarch64-opc.c | 71 +- opcodes/aarch64-opc.h | 1 + opcodes/aarch64-tbl.h | 20 + 31 files changed, 2177 insertions(+), 488 deletions(-) create mode 100644 gas/testsuite/gas/aarch64/sme2-9-invalid.d create mode 100644 gas/testsuite/gas/aarch64/sme2-9-invalid.l create mode 100644 gas/testsuite/gas/aarch64/sme2-9-invalid.s create mode 100644 gas/testsuite/gas/aarch64/sme2-9-noarch.d create mode 100644 gas/testsuite/gas/aarch64/sme2-9-noarch.l create mode 100644 gas/testsuite/gas/aarch64/sme2-9.d create mode 100644 gas/testsuite/gas/aarch64/sme2-9.s create mode 100644 gas/testsuite/gas/aarch64/sme2-f64f64-1-invalid.d create mode 100644 gas/testsuite/gas/aarch64/sme2-f64f64-1-invalid.l create mode 100644 gas/testsuite/gas/aarch64/sme2-f64f64-1-invalid.s create mode 100644 gas/testsuite/gas/aarch64/sme2-f64f64-1-noarch.d create mode 100644 gas/testsuite/gas/aarch64/sme2-f64f64-1-noarch.l create mode 100644 gas/testsuite/gas/aarch64/sme2-f64f64-1.d create mode 100644 gas/testsuite/gas/aarch64/sme2-f64f64-1.s create mode 100644 gas/testsuite/gas/aarch64/sme2-i16i64-1-invalid.d create mode 100644 gas/testsuite/gas/aarch64/sme2-i16i64-1-invalid.l create mode 100644 gas/testsuite/gas/aarch64/sme2-i16i64-1-invalid.s create mode 100644 gas/testsuite/gas/aarch64/sme2-i16i64-1-noarch.d create mode 100644 gas/testsuite/gas/aarch64/sme2-i16i64-1-noarch.l create mode 100644 gas/testsuite/gas/aarch64/sme2-i16i64-1.d create mode 100644 gas/testsuite/gas/aarch64/sme2-i16i64-1.s diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 652fd4e6ff3..5e023152c17 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -6659,6 +6659,7 @@ parse_operands (char *str, const aarch64_opcode *opcode) case AARCH64_OPND_SVE_Zm_16: case AARCH64_OPND_SVE_Zn: case AARCH64_OPND_SVE_Zt: + case AARCH64_OPND_SME_Zm: reg_type = REG_TYPE_Z; goto vector_reg; @@ -6811,7 +6812,7 @@ parse_operands (char *str, const aarch64_opcode *opcode) goto failure; } - if (vectype.width != 0 && *str != ',') + if ((int) vectype.width > 0 && *str != ',') { set_fatal_syntax_error (_("expected element type rather than vector type")); diff --git a/gas/testsuite/gas/aarch64/sme2-9-invalid.d b/gas/testsuite/gas/aarch64/sme2-9-invalid.d new file mode 100644 index 00000000000..78b3fa2875b --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-9-invalid.d @@ -0,0 +1,3 @@ +#as: -march=armv8-a +#source: sme2-9-invalid.s +#error_output: sme2-9-invalid.l diff --git a/gas/testsuite/gas/aarch64/sme2-9-invalid.l b/gas/testsuite/gas/aarch64/sme2-9-invalid.l new file mode 100644 index 00000000000..e181f0b7378 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-9-invalid.l @@ -0,0 +1,179 @@ +[^ :]+: Assembler messages: +[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `add 0,{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: expected '{' at operand 2 -- `add za\.s\[w8,0\],0' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.s\[w7,0\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.s\[w12,0\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.s\[w8,-1\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.s\[w8,8\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `add za\.s\[w8,0\],{z0\.s-z2\.s}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `add za\.s\[w8,0\],{z1\.s-z2\.s}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.s\[w7,0\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.s\[w12,0\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.s\[w8,-1\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.s\[w8,8\],{z1\.s-z3\.s}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `add za\.s\[w8,0\],{z1\.s-z4\.s}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `add za\.s\[w8,0\],{z2\.s-z5\.s}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `add za\.s\[w8,0\],{z3\.s-z6\.s}' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `add za\.s\[w8,0,vgx4\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `add za\.s\[w8,0,vgx2\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: operand mismatch -- `add za\[w8,0\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: add za\.s\[w8, 0\], {z0\.s-z1\.s} +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: add za\.d\[w8, 0\], {z0\.d-z1\.d} +[^ :]+:[0-9]+: Error: missing type suffix at operand 2 -- `add za\.s\[w8,0\],{z0-z1}' +[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `add 0,{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: expected '{' at operand 2 -- `add za\.s\[w8,0\],0,z0\.s' +[^ :]+:[0-9]+: Error: expected a register or register list at operand 3 -- `add za\.s\[w8,0\],{z0\.s-z1\.s},0' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.s\[w0,0\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: expected a 32-bit selection register at operand 1 -- `add za\.s\[w31,0\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.s\[w8,1<<63\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `add za\.s\[w8,0\],{z0\.s-z1\.s},z31\.s' +[^ :]+:[0-9]+: Error: the last offset is equal to the first offset at operand 1 -- `add za\.s\[w8,0:0\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: the last offset is less than the first offset at operand 1 -- `add za\.s\[w8,0:-1\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: expected a single offset rather than a range at operand 1 -- `add za\.s\[w8,0:1\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: expected a single offset rather than a range at operand 1 -- `add za\.s\[w8,0:100\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.s\[w7,0\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.s\[w12,0\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.s\[w8,-1\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.s\[w8,8\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `add za\.s\[w8,0\],{z0\.s-z1\.s},z16\.s' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.s\[w7,0\],{z0\.s-z3\.s},z0\.s' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.s\[w12,0\],{z0\.s-z3\.s},z0\.s' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.s\[w8,-1\],{z0\.s-z3\.s},z0\.s' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.s\[w8,8\],{z0\.s-z3\.s},z0\.s' +[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `add za\.s\[w8,0\],{z0\.s-z3\.s},z16\.s' +[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `add za\.s\[w8,0\],{z0\.s-z2\.s},z0\.s' +[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 2 -- `add za\.s\[w8,0\],{z0\.s-z4\.s},z0\.s' +[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `add za\.s\[w8,0\],{z0\.s,z1\.s,z2\.s},z0\.s' +[^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `add za\.s\[w8,0\],{z0\.s,z1\.s,z5\.s},z0\.s' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `add za\.s\[w8,0,vgx4\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `add za\.s\[w8,0,vgx2\],{z0\.s-z3\.s},z0\.s' +[^ :]+:[0-9]+: Error: operand mismatch -- `add za\[w8,0\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: add za\.s\[w8, 0\], {z0\.s-z1\.s}, z0\.s +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: add za\.d\[w8, 0\], {z0\.d-z1\.d}, z0\.d +[^ :]+:[0-9]+: Error: missing type suffix at operand 2 -- `add za\.s\[w8,0\],{z0-z1},z0\.s' +[^ :]+:[0-9]+: Error: operand mismatch -- `add za\.s\[w8,0\],{z0\.s-z1\.s},z0' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: add za\.s\[w8, 0\], {z0\.s-z1\.s}, z0\.s +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: add za\.d\[w8, 0\], {z0\.d-z1\.d}, z0\.d +[^ :]+:[0-9]+: Error: operand mismatch -- `add za\[w8,0\],{z0\.s-z1\.s},z0' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: add za\.s\[w8, 0\], {z0\.s-z1\.s}, z0\.s +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: add za\.d\[w8, 0\], {z0\.d-z1\.d}, z0\.d +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.s\[w7,0\],{z0\.s-z1\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.s\[w12,0\],{z0\.s-z1\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.s\[w8,-1\],{z0\.s-z1\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.s\[w8,8\],{z0\.s-z1\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `add za\.s\[w8,0\],{z1\.s-z2\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `add za\.s\[w8,0\],{z0\.s-z1\.s},{z15\.s-z16\.s}' +[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `add za\.s\[w8,0\],{z0\.s-z1\.s},{z31\.s,z0\.s}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.s\[w7,0\],{z0\.s-z3\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.s\[w12,0\],{z0\.s-z3\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.s\[w8,-1\],{z0\.s-z3\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.s\[w8,8\],{z0\.s-z3\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `add za\.s\[w8,0\],{z1\.s-z4\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `add za\.s\[w8,0\],{z2\.s-z5\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `add za\.s\[w8,0\],{z3\.s-z6\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `add za\.s\[w8,0\],{z0\.s-z3\.s},{z15\.s-z18\.s}' +[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `add za\.s\[w8,0\],{z0\.s-z3\.s},{z29\.s,z30\.s,z31\.s,z0\.s}' +[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `add za\.s\[w8,0\],{z0\.s-z2\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 3 -- `add za\.s\[w8,0\],{z0\.s-z3\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `add za\.s\[w8,0\],{z0\.s-z1\.s},{z0\.s-z2\.s}' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `add za\.s\[w8,0\],{z0\.s-z1\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 3 -- `add za\.s\[w8,0\],{z0\.s-z1\.s},{z0\.s-z4\.s}' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `add za\.s\[w8,0,vgx4\],{z0\.s-z1\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 3 -- `add za\.s\[w8,0,vgx4\],{z0\.s-z3\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `add za\.s\[w8,0,vgx2\],{z0\.s-z1\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `add za\.s\[w8,0,vgx2\],{z0\.s-z3\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: operand mismatch -- `add za\[w8,0\],{z0\.s-z1\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: add za\.s\[w8, 0\], {z0\.s-z1\.s}, {z0\.s-z1\.s} +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: add za\.d\[w8, 0\], {z0\.d-z1\.d}, {z0\.d-z1\.d} +[^ :]+:[0-9]+: Error: operand mismatch -- `add za\[w8,0\],{z0\.s-z3\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: add za\.s\[w8, 0\], {z0\.s-z3\.s}, {z0\.s-z3\.s} +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: add za\.d\[w8, 0\], {z0\.d-z3\.d}, {z0\.d-z3\.d} +[^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `add {z0\.b-z1\.b},{z0\.b-z2\.b},z0\.b' +[^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `add {z0\.b-z1\.b},{z0\.b-z3\.b},z0\.b' +[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 1 -- `add {z0\.b-z2\.b},{z0\.b-z2\.b},z0\.b' +[^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `add {z0\.b-z1\.b},{z2\.b-z3\.b},z0\.b' +[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `add {z1\.b-z2\.b},{z1\.b-z2\.b},z0\.b' +[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `add {z31\.b,z0\.b},{z31\.b,z0\.b},z0\.b' +[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `add {z0\.b-z1\.b},{z0\.b-z1\.b},z16\.b' +[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `add {z0\.b-z1\.b},{z0\.b-z1\.b},z31\.b' +[^ :]+:[0-9]+: Error: operand mismatch -- `add {z0\.b-z1\.b},{z0\.h-z1\.h},z0\.b' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: add {z0\.b-z1\.b}, {z0\.b-z1\.b}, z0\.b +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: add {z0\.h-z1\.h}, {z0\.h-z1\.h}, z0\.h +[^ :]+:[0-9]+: Info: add {z0\.s-z1\.s}, {z0\.s-z1\.s}, z0\.s +[^ :]+:[0-9]+: Info: add {z0\.d-z1\.d}, {z0\.d-z1\.d}, z0\.d +[^ :]+:[0-9]+: Error: operand mismatch -- `add {z0\.b-z1\.b},{z0\.b-z1\.b},z0\.h' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: add {z0\.b-z1\.b}, {z0\.b-z1\.b}, z0\.b +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: add {z0\.h-z1\.h}, {z0\.h-z1\.h}, z0\.h +[^ :]+:[0-9]+: Info: add {z0\.s-z1\.s}, {z0\.s-z1\.s}, z0\.s +[^ :]+:[0-9]+: Info: add {z0\.d-z1\.d}, {z0\.d-z1\.d}, z0\.d +[^ :]+:[0-9]+: Error: operand mismatch -- `add {z0\.q-z1\.q},{z0\.q-z1\.q},z0\.q' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: add {z0\.b-z1\.b}, {z0\.b-z1\.b}, z0\.b +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: add {z0\.h-z1\.h}, {z0\.h-z1\.h}, z0\.h +[^ :]+:[0-9]+: Info: add {z0\.s-z1\.s}, {z0\.s-z1\.s}, z0\.s +[^ :]+:[0-9]+: Info: add {z0\.d-z1\.d}, {z0\.d-z1\.d}, z0\.d +[^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `add {z0\.b-z3\.b},{z0\.b-z2\.b},z0\.b' +[^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `add {z0\.b-z3\.b},{z0\.b-z1\.b},z0\.b' +[^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `add {z0\.b-z3\.b},{z2\.b-z5\.b},z0\.b' +[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `add {z1\.b-z4\.b},{z1\.b-z4\.b},z0\.b' +[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `add {z2\.b-z5\.b},{z2\.b-z5\.b},z0\.b' +[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `add {z3\.b-z6\.b},{z3\.b-z6\.b},z0\.b' +[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `add {z31\.b,z0\.b,z1\.b,z2\.b},{z31\.b,z0\.b,z1\.b,z2\.b},z0\.b' +[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `add {z0\.b-z3\.b},{z0\.b-z3\.b},z16\.b' +[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `add {z0\.b-z3\.b},{z0\.b-z3\.b},z31\.b' +[^ :]+:[0-9]+: Error: operand mismatch -- `add {z0\.b-z3\.b},{z0\.h-z3\.h},z0\.b' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: add {z0\.b-z3\.b}, {z0\.b-z3\.b}, z0\.b +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: add {z0\.h-z3\.h}, {z0\.h-z3\.h}, z0\.h +[^ :]+:[0-9]+: Info: add {z0\.s-z3\.s}, {z0\.s-z3\.s}, z0\.s +[^ :]+:[0-9]+: Info: add {z0\.d-z3\.d}, {z0\.d-z3\.d}, z0\.d +[^ :]+:[0-9]+: Error: operand mismatch -- `add {z0\.b-z3\.b},{z0\.b-z3\.b},z0\.h' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: add {z0\.b-z3\.b}, {z0\.b-z3\.b}, z0\.b +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: add {z0\.h-z3\.h}, {z0\.h-z3\.h}, z0\.h +[^ :]+:[0-9]+: Info: add {z0\.s-z3\.s}, {z0\.s-z3\.s}, z0\.s +[^ :]+:[0-9]+: Info: add {z0\.d-z3\.d}, {z0\.d-z3\.d}, z0\.d +[^ :]+:[0-9]+: Error: operand mismatch -- `add {z0\.q-z3\.q},{z0\.q-z3\.q},z0\.q' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: add {z0\.b-z3\.b}, {z0\.b-z3\.b}, z0\.b +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: add {z0\.h-z3\.h}, {z0\.h-z3\.h}, z0\.h +[^ :]+:[0-9]+: Info: add {z0\.s-z3\.s}, {z0\.s-z3\.s}, z0\.s +[^ :]+:[0-9]+: Info: add {z0\.d-z3\.d}, {z0\.d-z3\.d}, z0\.d +[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sub {z0\.b-z1\.b},{z0\.b-z1\.b},z0\.b' +[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sub {z0\.h-z1\.h},{z0\.h-z1\.h},z0\.h' +[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sub {z0\.s-z1\.s},{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sub {z0\.d-z1\.d},{z0\.d-z1\.d},z0\.d' +[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sub {z0\.b-z3\.b},{z0\.b-z3\.b},z0\.b' +[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sub {z0\.h-z3\.h},{z0\.h-z3\.h},z0\.h' +[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sub {z0\.s-z3\.s},{z0\.s-z3\.s},z0\.s' +[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sub {z0\.d-z3\.d},{z0\.d-z3\.d},z0\.d' +[^ :]+:[0-9]+: Error: operand mismatch -- `fadd za\.b\[w8,0\],{z0\.b-z1\.b}' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: fadd za\.s\[w8, 0\], {z0\.s-z1\.s} +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: fadd za\.d\[w8, 0\], {z0\.d-z1\.d} +[^ :]+:[0-9]+: Error: operand mismatch -- `fadd za\.h\[w8,0\],{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: fadd za\.s\[w8, 0\], {z0\.s-z1\.s} +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: fadd za\.d\[w8, 0\], {z0\.d-z1\.d} diff --git a/gas/testsuite/gas/aarch64/sme2-9-invalid.s b/gas/testsuite/gas/aarch64/sme2-9-invalid.s new file mode 100644 index 00000000000..d5bfc095e21 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-9-invalid.s @@ -0,0 +1,128 @@ + add 0, { z0.s - z1.s } + add za.s[w8, 0], 0 + + add za.s[w7, 0], { z0.s - z1.s } + add za.s[w12, 0], { z0.s - z1.s } + add za.s[w8, -1], { z0.s - z1.s } + add za.s[w8, 8], { z0.s - z1.s } + add za.s[w8, 0], { z0.s - z2.s } + add za.s[w8, 0], { z1.s - z2.s } + + add za.s[w7, 0], { z0.s - z3.s } + add za.s[w12, 0], { z0.s - z3.s } + add za.s[w8, -1], { z0.s - z3.s } + add za.s[w8, 8], { z1.s - z3.s } + add za.s[w8, 0], { z1.s - z4.s } + add za.s[w8, 0], { z2.s - z5.s } + add za.s[w8, 0], { z3.s - z6.s } + + add za.s[w8, 0, vgx4], { z0.s - z1.s } + add za.s[w8, 0, vgx2], { z0.s - z3.s } + add za[w8, 0], { z0.s - z1.s } + add za.s[w8, 0], { z0 - z1 } + + add 0, { z0.s - z1.s }, z0.s + add za.s[w8, 0], 0, z0.s + add za.s[w8, 0], { z0.s - z1.s }, 0 + + add za.s[w0, 0], { z0.s - z1.s }, z0.s + add za.s[w31, 0], { z0.s - z1.s }, z0.s + add za.s[w8, 1<<63], { z0.s - z1.s }, z0.s + add za.s[w8, 0], { z0.s - z1.s }, z31.s + add za.s[w8, 0:0], { z0.s - z1.s }, z0.s + add za.s[w8, 0:-1], { z0.s - z1.s }, z0.s + add za.s[w8, 0:1], { z0.s - z1.s }, z0.s + add za.s[w8, 0:100], { z0.s - z1.s }, z0.s + + add za.s[w7, 0], { z0.s - z1.s }, z0.s + add za.s[w12, 0], { z0.s - z1.s }, z0.s + add za.s[w8, -1], { z0.s - z1.s }, z0.s + add za.s[w8, 8], { z0.s - z1.s }, z0.s + add za.s[w8, 0], { z0.s - z1.s }, z16.s + + add za.s[w7, 0], { z0.s - z3.s }, z0.s + add za.s[w12, 0], { z0.s - z3.s }, z0.s + add za.s[w8, -1], { z0.s - z3.s }, z0.s + add za.s[w8, 8], { z0.s - z3.s }, z0.s + add za.s[w8, 0], { z0.s - z3.s }, z16.s + + add za.s[w8, 0], { z0.s - z2.s }, z0.s + add za.s[w8, 0], { z0.s - z4.s }, z0.s + add za.s[w8, 0], { z0.s, z1.s, z2.s }, z0.s + add za.s[w8, 0], { z0.s, z1.s, z5.s }, z0.s + + add za.s[w8, 0, vgx4], { z0.s - z1.s }, z0.s + add za.s[w8, 0, vgx2], { z0.s - z3.s }, z0.s + add za[w8, 0], { z0.s - z1.s }, z0.s + add za.s[w8, 0], { z0 - z1 }, z0.s + add za.s[w8, 0], { z0.s - z1.s }, z0 + add za[w8, 0], { z0.s - z1.s }, z0 + + add za.s[w7, 0], { z0.s - z1.s }, { z0.s - z1.s } + add za.s[w12, 0], { z0.s - z1.s }, { z0.s - z1.s } + add za.s[w8, -1], { z0.s - z1.s }, { z0.s - z1.s } + add za.s[w8, 8], { z0.s - z1.s }, { z0.s - z1.s } + add za.s[w8, 0], { z1.s - z2.s }, { z0.s - z1.s } + add za.s[w8, 0], { z0.s - z1.s }, { z15.s - z16.s } + add za.s[w8, 0], { z0.s - z1.s }, { z31.s, z0.s } + + add za.s[w7, 0], { z0.s - z3.s }, { z0.s - z3.s } + add za.s[w12, 0], { z0.s - z3.s }, { z0.s - z3.s } + add za.s[w8, -1], { z0.s - z3.s }, { z0.s - z3.s } + add za.s[w8, 8], { z0.s - z3.s }, { z0.s - z3.s } + add za.s[w8, 0], { z1.s - z4.s }, { z0.s - z3.s } + add za.s[w8, 0], { z2.s - z5.s }, { z0.s - z3.s } + add za.s[w8, 0], { z3.s - z6.s }, { z0.s - z3.s } + add za.s[w8, 0], { z0.s - z3.s }, { z15.s - z18.s } + add za.s[w8, 0], { z0.s - z3.s }, { z29.s, z30.s, z31.s, z0.s } + + add za.s[w8, 0], { z0.s - z2.s }, { z0.s - z1.s } + add za.s[w8, 0], { z0.s - z3.s }, { z0.s - z1.s } + add za.s[w8, 0], { z0.s - z1.s }, { z0.s - z2.s } + add za.s[w8, 0], { z0.s - z1.s }, { z0.s - z3.s } + add za.s[w8, 0], { z0.s - z1.s }, { z0.s - z4.s } + + add za.s[w8, 0, vgx4], { z0.s - z1.s }, { z0.s - z3.s } + add za.s[w8, 0, vgx4], { z0.s - z3.s }, { z0.s - z1.s } + add za.s[w8, 0, vgx2], { z0.s - z1.s }, { z0.s - z3.s } + add za.s[w8, 0, vgx2], { z0.s - z3.s }, { z0.s - z1.s } + add za[w8, 0], { z0.s - z1.s }, { z0.s - z1.s } + add za[w8, 0], { z0.s - z3.s }, { z0.s - z3.s } + + add { z0.b - z1.b }, { z0.b - z2.b }, z0.b + add { z0.b - z1.b }, { z0.b - z3.b }, z0.b + add { z0.b - z2.b }, { z0.b - z2.b }, z0.b + add { z0.b - z1.b }, { z2.b - z3.b }, z0.b + add { z1.b - z2.b }, { z1.b - z2.b }, z0.b + add { z31.b, z0.b }, { z31.b, z0.b }, z0.b + add { z0.b - z1.b }, { z0.b - z1.b }, z16.b + add { z0.b - z1.b }, { z0.b - z1.b }, z31.b + add { z0.b - z1.b }, { z0.h - z1.h }, z0.b + add { z0.b - z1.b }, { z0.b - z1.b }, z0.h + add { z0.q - z1.q }, { z0.q - z1.q }, z0.q + + add { z0.b - z3.b }, { z0.b - z2.b }, z0.b + add { z0.b - z3.b }, { z0.b - z1.b }, z0.b + add { z0.b - z3.b }, { z2.b - z5.b }, z0.b + add { z1.b - z4.b }, { z1.b - z4.b }, z0.b + add { z2.b - z5.b }, { z2.b - z5.b }, z0.b + add { z3.b - z6.b }, { z3.b - z6.b }, z0.b + add { z31.b, z0.b, z1.b, z2.b }, { z31.b, z0.b, z1.b, z2.b }, z0.b + add { z0.b - z3.b }, { z0.b - z3.b }, z16.b + add { z0.b - z3.b }, { z0.b - z3.b }, z31.b + add { z0.b - z3.b }, { z0.h - z3.h }, z0.b + add { z0.b - z3.b }, { z0.b - z3.b }, z0.h + add { z0.q - z3.q }, { z0.q - z3.q }, z0.q + + sub { z0.b - z1.b }, { z0.b - z1.b }, z0.b + sub { z0.h - z1.h }, { z0.h - z1.h }, z0.h + sub { z0.s - z1.s }, { z0.s - z1.s }, z0.s + sub { z0.d - z1.d }, { z0.d - z1.d }, z0.d + + sub { z0.b - z3.b }, { z0.b - z3.b }, z0.b + sub { z0.h - z3.h }, { z0.h - z3.h }, z0.h + sub { z0.s - z3.s }, { z0.s - z3.s }, z0.s + sub { z0.d - z3.d }, { z0.d - z3.d }, z0.d + + fadd za.b[w8, 0], { z0.b - z1.b } + fadd za.h[w8, 0], { z0.h - z1.h } diff --git a/gas/testsuite/gas/aarch64/sme2-9-noarch.d b/gas/testsuite/gas/aarch64/sme2-9-noarch.d new file mode 100644 index 00000000000..076b3dabf58 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-9-noarch.d @@ -0,0 +1,3 @@ +#as: -march=armv8-a+sme +#source: sme2-9.s +#error_output: sme2-9-noarch.l diff --git a/gas/testsuite/gas/aarch64/sme2-9-noarch.l b/gas/testsuite/gas/aarch64/sme2-9-noarch.l new file mode 100644 index 00000000000..1a2ad07a209 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-9-noarch.l @@ -0,0 +1,177 @@ +[^ :]+: Assembler messages: +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0,vgx2\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.s\[W8,0,VGx2\],{Z0\.s-Z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.S\[W8,0,VGX2\],{Z0\.S-Z1\.S}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w11,0\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,7\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0\],{z30\.s-z31\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w10,3\],{z10\.s-z11\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0,vgx4\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.s\[W8,0,VGx4\],{Z0\.s-Z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.S\[W8,0,VGX4\],{Z0\.S-Z3\.S}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w11,0\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,7\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0\],{z28\.s-z31\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w11,1\],{z12\.s-z15\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0,vgx2\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.s\[W8,0,VGx2\],{Z0\.s-Z1\.s},Z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.S\[W8,0,VGX2\],{Z0\.S-Z1\.S},Z0\.S' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w11,0\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,7\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0\],{z30\.s-z31\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0\],{z31\.s,z0\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0\],{z31\.s-z0\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0\],{z0\.s-z1\.s},z15\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w9,5\],{z9\.s-z10\.s},z6\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0\],{z0\.s-z3\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0,vgx4\],{z0\.s-z3\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.s\[W8,0,VGx4\],{Z0\.s-Z3\.s},Z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.S\[W8,0,VGX4\],{Z0\.S-Z3\.S},Z0\.S' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w11,0\],{z0\.s-z3\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,7\],{z0\.s-z3\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0\],{z28\.s-z31\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0\],{z31\.s,z0\.s,z1\.s,z2\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0\],{z31\.s-z2\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0\],{z0\.s-z3\.s},z15\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w11,2\],{z23\.s-z26\.s},z13\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0\],{z0\.s-z1\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0,vgx2\],{z0\.s-z1\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.s\[W8,0,VGx2\],{Z0\.s-Z1\.s},{Z0\.s-Z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.S\[W8,0,VGX2\],{Z0\.S-Z1\.S},{Z0\.S-Z1\.S}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w11,0\],{z0\.s-z1\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,7\],{z0\.s-z1\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0\],{z30\.s-z31\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0\],{z0\.s-z1\.s},{z30\.s-z31\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w10,1\],{z22\.s-z23\.s},{z18\.s-z19\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0\],{z0\.s-z3\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0,vgx4\],{z0\.s-z3\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.s\[W8,0,VGx4\],{Z0\.s-Z3\.s},{Z0\.s-Z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.S\[W8,0,VGX4\],{Z0\.S-Z3\.S},{Z0\.S-Z3\.S}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w11,0\],{z0\.s-z3\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,7\],{z0\.s-z3\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0\],{z28\.s-z31\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0\],{z0\.s-z3\.s},{z28\.s-z31\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w11,3\],{z16\.s-z19\.s},{z24\.s-z27\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z0\.b-z1\.b},{z0\.b-z1\.b},z0\.b' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z30\.b-z31\.b},{z30\.b-z31\.b},z0\.b' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z0\.b-z1\.b},{z0\.b-z1\.b},z15\.b' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z14\.b-z15\.b},{z14\.b-z15\.b},z5\.b' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z0\.h-z1\.h},{z0\.h-z1\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z30\.h-z31\.h},{z30\.h-z31\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z0\.h-z1\.h},{z0\.h-z1\.h},z15\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z20\.h-z21\.h},{z20\.h-z21\.h},z11\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z0\.s-z1\.s},{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z30\.s-z31\.s},{z30\.s-z31\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z0\.s-z1\.s},{z0\.s-z1\.s},z15\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z2\.s-z3\.s},{z2\.s-z3\.s},z9\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z0\.d-z1\.d},{z0\.d-z1\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z30\.d-z31\.d},{z30\.d-z31\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z0\.d-z1\.d},{z0\.d-z1\.d},z15\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z28\.d-z29\.d},{z28\.d-z29\.d},z1\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z0\.b-z3\.b},{z0\.b-z3\.b},z0\.b' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z28\.b-z31\.b},{z28\.b-z31\.b},z0\.b' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z0\.b-z3\.b},{z0\.b-z3\.b},z15\.b' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z24\.b-z27\.b},{z24\.b-z27\.b},z5\.b' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z0\.h-z3\.h},{z0\.h-z3\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z28\.h-z31\.h},{z28\.h-z31\.h},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z0\.h-z3\.h},{z0\.h-z3\.h},z15\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z20\.h-z23\.h},{z20\.h-z23\.h},z11\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z0\.s-z3\.s},{z0\.s-z3\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z28\.s-z31\.s},{z28\.s-z31\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z0\.s-z3\.s},{z0\.s-z3\.s},z15\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z4\.s-z7\.s},{z4\.s-z7\.s},z9\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z0\.d-z3\.d},{z0\.d-z3\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z28\.d-z31\.d},{z28\.d-z31\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z0\.d-z3\.d},{z0\.d-z3\.d},z15\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add {z16\.d-z19\.d},{z16\.d-z19\.d},z3\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0,vgx2\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub ZA\.s\[W8,0,VGx2\],{Z0\.s-Z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub ZA\.S\[W8,0,VGX2\],{Z0\.S-Z1\.S}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w11,0\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,7\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0\],{z30\.s-z31\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w10,3\],{z10\.s-z11\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0,vgx4\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub ZA\.s\[W8,0,VGx4\],{Z0\.s-Z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub ZA\.S\[W8,0,VGX4\],{Z0\.S-Z3\.S}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w11,0\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,7\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0\],{z28\.s-z31\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w11,1\],{z12\.s-z15\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0,vgx2\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `sub ZA\.s\[W8,0,VGx2\],{Z0\.s-Z1\.s},Z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `sub ZA\.S\[W8,0,VGX2\],{Z0\.S-Z1\.S},Z0\.S' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w11,0\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,7\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0\],{z30\.s-z31\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0\],{z31\.s,z0\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0\],{z31\.s-z0\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0\],{z0\.s-z1\.s},z15\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w9,5\],{z9\.s-z10\.s},z6\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0\],{z0\.s-z3\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0,vgx4\],{z0\.s-z3\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `sub ZA\.s\[W8,0,VGx4\],{Z0\.s-Z3\.s},Z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `sub ZA\.S\[W8,0,VGX4\],{Z0\.S-Z3\.S},Z0\.S' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w11,0\],{z0\.s-z3\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,7\],{z0\.s-z3\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0\],{z28\.s-z31\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0\],{z31\.s,z0\.s,z1\.s,z2\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0\],{z31\.s-z2\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0\],{z0\.s-z3\.s},z15\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w11,2\],{z23\.s-z26\.s},z13\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0\],{z0\.s-z1\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0,vgx2\],{z0\.s-z1\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub ZA\.s\[W8,0,VGx2\],{Z0\.s-Z1\.s},{Z0\.s-Z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub ZA\.S\[W8,0,VGX2\],{Z0\.S-Z1\.S},{Z0\.S-Z1\.S}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w11,0\],{z0\.s-z1\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,7\],{z0\.s-z1\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0\],{z30\.s-z31\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0\],{z0\.s-z1\.s},{z30\.s-z31\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w10,1\],{z22\.s-z23\.s},{z18\.s-z19\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0\],{z0\.s-z3\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0,vgx4\],{z0\.s-z3\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub ZA\.s\[W8,0,VGx4\],{Z0\.s-Z3\.s},{Z0\.s-Z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub ZA\.S\[W8,0,VGX4\],{Z0\.S-Z3\.S},{Z0\.S-Z3\.S}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w11,0\],{z0\.s-z3\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,7\],{z0\.s-z3\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0\],{z28\.s-z31\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0\],{z0\.s-z3\.s},{z28\.s-z31\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w11,3\],{z16\.s-z19\.s},{z24\.s-z27\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.s\[w8,0\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.s\[w8,0,vgx2\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd ZA\.s\[W8,0,VGx2\],{Z0\.s-Z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd ZA\.S\[W8,0,VGX2\],{Z0\.S-Z1\.S}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.s\[w11,0\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.s\[w8,7\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.s\[w8,0\],{z30\.s-z31\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.s\[w10,3\],{z10\.s-z11\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.s\[w8,0\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.s\[w8,0,vgx4\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd ZA\.s\[W8,0,VGx4\],{Z0\.s-Z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd ZA\.S\[W8,0,VGX4\],{Z0\.S-Z3\.S}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.s\[w11,0\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.s\[w8,7\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.s\[w8,0\],{z28\.s-z31\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.s\[w11,1\],{z12\.s-z15\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.s\[w8,0\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.s\[w8,0,vgx2\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub ZA\.s\[W8,0,VGx2\],{Z0\.s-Z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub ZA\.S\[W8,0,VGX2\],{Z0\.S-Z1\.S}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.s\[w11,0\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.s\[w8,7\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.s\[w8,0\],{z30\.s-z31\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.s\[w10,3\],{z10\.s-z11\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.s\[w8,0\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.s\[w8,0,vgx4\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub ZA\.s\[W8,0,VGx4\],{Z0\.s-Z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub ZA\.S\[W8,0,VGX4\],{Z0\.S-Z3\.S}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.s\[w11,0\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.s\[w8,7\],{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.s\[w8,0\],{z28\.s-z31\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.s\[w11,1\],{z12\.s-z15\.s}' diff --git a/gas/testsuite/gas/aarch64/sme2-9.d b/gas/testsuite/gas/aarch64/sme2-9.d new file mode 100644 index 00000000000..ece09550d66 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-9.d @@ -0,0 +1,185 @@ +#as: -march=armv8-a+sme2 +#objdump: -dr + +[^:]+: file format .* + + +[^:]+: + +[^:]+: +[^:]+: c1a01c10 add za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a01c10 add za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a01c10 add za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a01c10 add za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a07c10 add za\.s\[w11, 0, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a01c17 add za\.s\[w8, 7, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a01fd0 add za\.s\[w8, 0, vgx2\], {z30\.s-z31\.s} +[^:]+: c1a05d53 add za\.s\[w10, 3, vgx2\], {z10\.s-z11\.s} +[^:]+: c1a11c10 add za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a11c10 add za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a11c10 add za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a11c10 add za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a17c10 add za\.s\[w11, 0, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a11c17 add za\.s\[w8, 7, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a11f90 add za\.s\[w8, 0, vgx4\], {z28\.s-z31\.s} +[^:]+: c1a17d91 add za\.s\[w11, 1, vgx4\], {z12\.s-z15\.s} +[^:]+: c1201810 add za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s +[^:]+: c1201810 add za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s +[^:]+: c1201810 add za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s +[^:]+: c1201810 add za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s +[^:]+: c1207810 add za\.s\[w11, 0, vgx2\], {z0\.s-z1\.s}, z0\.s +[^:]+: c1201817 add za\.s\[w8, 7, vgx2\], {z0\.s-z1\.s}, z0\.s +[^:]+: c1201bd0 add za\.s\[w8, 0, vgx2\], {z30\.s-z31\.s}, z0\.s +[^:]+: c1201bf0 add za\.s\[w8, 0, vgx2\], {z31\.s-z0\.s}, z0\.s +[^:]+: c1201bf0 add za\.s\[w8, 0, vgx2\], {z31\.s-z0\.s}, z0\.s +[^:]+: c12f1810 add za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z15\.s +[^:]+: c1263935 add za\.s\[w9, 5, vgx2\], {z9\.s-z10\.s}, z6\.s +[^:]+: c1301810 add za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s +[^:]+: c1301810 add za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s +[^:]+: c1301810 add za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s +[^:]+: c1301810 add za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s +[^:]+: c1307810 add za\.s\[w11, 0, vgx4\], {z0\.s-z3\.s}, z0\.s +[^:]+: c1301817 add za\.s\[w8, 7, vgx4\], {z0\.s-z3\.s}, z0\.s +[^:]+: c1301b90 add za\.s\[w8, 0, vgx4\], {z28\.s-z31\.s}, z0\.s +[^:]+: c1301bf0 add za\.s\[w8, 0, vgx4\], {z31\.s-z2\.s}, z0\.s +[^:]+: c1301bf0 add za\.s\[w8, 0, vgx4\], {z31\.s-z2\.s}, z0\.s +[^:]+: c13f1810 add za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z15\.s +[^:]+: c13d7af2 add za\.s\[w11, 2, vgx4\], {z23\.s-z26\.s}, z13\.s +[^:]+: c1a01810 add za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s} +[^:]+: c1a01810 add za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s} +[^:]+: c1a01810 add za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s} +[^:]+: c1a01810 add za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s} +[^:]+: c1a07810 add za\.s\[w11, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s} +[^:]+: c1a01817 add za\.s\[w8, 7, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s} +[^:]+: c1a01bd0 add za\.s\[w8, 0, vgx2\], {z30\.s-z31\.s}, {z0\.s-z1\.s} +[^:]+: c1be1810 add za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z30\.s-z31\.s} +[^:]+: c1b25ad1 add za\.s\[w10, 1, vgx2\], {z22\.s-z23\.s}, {z18\.s-z19\.s} +[^:]+: c1a11810 add za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s} +[^:]+: c1a11810 add za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s} +[^:]+: c1a11810 add za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s} +[^:]+: c1a11810 add za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s} +[^:]+: c1a17810 add za\.s\[w11, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s} +[^:]+: c1a11817 add za\.s\[w8, 7, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s} +[^:]+: c1a11b90 add za\.s\[w8, 0, vgx4\], {z28\.s-z31\.s}, {z0\.s-z3\.s} +[^:]+: c1bd1810 add za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z28\.s-z31\.s} +[^:]+: c1b97a13 add za\.s\[w11, 3, vgx4\], {z16\.s-z19\.s}, {z24\.s-z27\.s} +[^:]+: c120a300 add {z0\.b-z1\.b}, {z0\.b-z1\.b}, z0\.b +[^:]+: c120a31e add {z30\.b-z31\.b}, {z30\.b-z31\.b}, z0\.b +[^:]+: c12fa300 add {z0\.b-z1\.b}, {z0\.b-z1\.b}, z15\.b +[^:]+: c125a30e add {z14\.b-z15\.b}, {z14\.b-z15\.b}, z5\.b +[^:]+: c160a300 add {z0\.h-z1\.h}, {z0\.h-z1\.h}, z0\.h +[^:]+: c160a31e add {z30\.h-z31\.h}, {z30\.h-z31\.h}, z0\.h +[^:]+: c16fa300 add {z0\.h-z1\.h}, {z0\.h-z1\.h}, z15\.h +[^:]+: c16ba314 add {z20\.h-z21\.h}, {z20\.h-z21\.h}, z11\.h +[^:]+: c1a0a300 add {z0\.s-z1\.s}, {z0\.s-z1\.s}, z0\.s +[^:]+: c1a0a31e add {z30\.s-z31\.s}, {z30\.s-z31\.s}, z0\.s +[^:]+: c1afa300 add {z0\.s-z1\.s}, {z0\.s-z1\.s}, z15\.s +[^:]+: c1a9a302 add {z2\.s-z3\.s}, {z2\.s-z3\.s}, z9\.s +[^:]+: c1e0a300 add {z0\.d-z1\.d}, {z0\.d-z1\.d}, z0\.d +[^:]+: c1e0a31e add {z30\.d-z31\.d}, {z30\.d-z31\.d}, z0\.d +[^:]+: c1efa300 add {z0\.d-z1\.d}, {z0\.d-z1\.d}, z15\.d +[^:]+: c1e1a31c add {z28\.d-z29\.d}, {z28\.d-z29\.d}, z1\.d +[^:]+: c120ab00 add {z0\.b-z3\.b}, {z0\.b-z3\.b}, z0\.b +[^:]+: c120ab1c add {z28\.b-z31\.b}, {z28\.b-z31\.b}, z0\.b +[^:]+: c12fab00 add {z0\.b-z3\.b}, {z0\.b-z3\.b}, z15\.b +[^:]+: c125ab18 add {z24\.b-z27\.b}, {z24\.b-z27\.b}, z5\.b +[^:]+: c160ab00 add {z0\.h-z3\.h}, {z0\.h-z3\.h}, z0\.h +[^:]+: c160ab1c add {z28\.h-z31\.h}, {z28\.h-z31\.h}, z0\.h +[^:]+: c16fab00 add {z0\.h-z3\.h}, {z0\.h-z3\.h}, z15\.h +[^:]+: c16bab14 add {z20\.h-z23\.h}, {z20\.h-z23\.h}, z11\.h +[^:]+: c1a0ab00 add {z0\.s-z3\.s}, {z0\.s-z3\.s}, z0\.s +[^:]+: c1a0ab1c add {z28\.s-z31\.s}, {z28\.s-z31\.s}, z0\.s +[^:]+: c1afab00 add {z0\.s-z3\.s}, {z0\.s-z3\.s}, z15\.s +[^:]+: c1a9ab04 add {z4\.s-z7\.s}, {z4\.s-z7\.s}, z9\.s +[^:]+: c1e0ab00 add {z0\.d-z3\.d}, {z0\.d-z3\.d}, z0\.d +[^:]+: c1e0ab1c add {z28\.d-z31\.d}, {z28\.d-z31\.d}, z0\.d +[^:]+: c1efab00 add {z0\.d-z3\.d}, {z0\.d-z3\.d}, z15\.d +[^:]+: c1e3ab10 add {z16\.d-z19\.d}, {z16\.d-z19\.d}, z3\.d +[^:]+: c1a01c18 sub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a01c18 sub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a01c18 sub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a01c18 sub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a07c18 sub za\.s\[w11, 0, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a01c1f sub za\.s\[w8, 7, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a01fd8 sub za\.s\[w8, 0, vgx2\], {z30\.s-z31\.s} +[^:]+: c1a05d5b sub za\.s\[w10, 3, vgx2\], {z10\.s-z11\.s} +[^:]+: c1a11c18 sub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a11c18 sub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a11c18 sub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a11c18 sub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a17c18 sub za\.s\[w11, 0, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a11c1f sub za\.s\[w8, 7, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a11f98 sub za\.s\[w8, 0, vgx4\], {z28\.s-z31\.s} +[^:]+: c1a17d99 sub za\.s\[w11, 1, vgx4\], {z12\.s-z15\.s} +[^:]+: c1201818 sub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s +[^:]+: c1201818 sub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s +[^:]+: c1201818 sub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s +[^:]+: c1201818 sub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s +[^:]+: c1207818 sub za\.s\[w11, 0, vgx2\], {z0\.s-z1\.s}, z0\.s +[^:]+: c120181f sub za\.s\[w8, 7, vgx2\], {z0\.s-z1\.s}, z0\.s +[^:]+: c1201bd8 sub za\.s\[w8, 0, vgx2\], {z30\.s-z31\.s}, z0\.s +[^:]+: c1201bf8 sub za\.s\[w8, 0, vgx2\], {z31\.s-z0\.s}, z0\.s +[^:]+: c1201bf8 sub za\.s\[w8, 0, vgx2\], {z31\.s-z0\.s}, z0\.s +[^:]+: c12f1818 sub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z15\.s +[^:]+: c126393d sub za\.s\[w9, 5, vgx2\], {z9\.s-z10\.s}, z6\.s +[^:]+: c1301818 sub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s +[^:]+: c1301818 sub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s +[^:]+: c1301818 sub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s +[^:]+: c1301818 sub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s +[^:]+: c1307818 sub za\.s\[w11, 0, vgx4\], {z0\.s-z3\.s}, z0\.s +[^:]+: c130181f sub za\.s\[w8, 7, vgx4\], {z0\.s-z3\.s}, z0\.s +[^:]+: c1301b98 sub za\.s\[w8, 0, vgx4\], {z28\.s-z31\.s}, z0\.s +[^:]+: c1301bf8 sub za\.s\[w8, 0, vgx4\], {z31\.s-z2\.s}, z0\.s +[^:]+: c1301bf8 sub za\.s\[w8, 0, vgx4\], {z31\.s-z2\.s}, z0\.s +[^:]+: c13f1818 sub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z15\.s +[^:]+: c13d7afa sub za\.s\[w11, 2, vgx4\], {z23\.s-z26\.s}, z13\.s +[^:]+: c1a01818 sub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s} +[^:]+: c1a01818 sub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s} +[^:]+: c1a01818 sub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s} +[^:]+: c1a01818 sub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s} +[^:]+: c1a07818 sub za\.s\[w11, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s} +[^:]+: c1a0181f sub za\.s\[w8, 7, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s} +[^:]+: c1a01bd8 sub za\.s\[w8, 0, vgx2\], {z30\.s-z31\.s}, {z0\.s-z1\.s} +[^:]+: c1be1818 sub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z30\.s-z31\.s} +[^:]+: c1b25ad9 sub za\.s\[w10, 1, vgx2\], {z22\.s-z23\.s}, {z18\.s-z19\.s} +[^:]+: c1a11818 sub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s} +[^:]+: c1a11818 sub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s} +[^:]+: c1a11818 sub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s} +[^:]+: c1a11818 sub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s} +[^:]+: c1a17818 sub za\.s\[w11, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s} +[^:]+: c1a1181f sub za\.s\[w8, 7, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s} +[^:]+: c1a11b98 sub za\.s\[w8, 0, vgx4\], {z28\.s-z31\.s}, {z0\.s-z3\.s} +[^:]+: c1bd1818 sub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z28\.s-z31\.s} +[^:]+: c1b97a1b sub za\.s\[w11, 3, vgx4\], {z16\.s-z19\.s}, {z24\.s-z27\.s} +[^:]+: c1a01c00 fadd za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a01c00 fadd za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a01c00 fadd za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a01c00 fadd za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a07c00 fadd za\.s\[w11, 0, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a01c07 fadd za\.s\[w8, 7, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a01fc0 fadd za\.s\[w8, 0, vgx2\], {z30\.s-z31\.s} +[^:]+: c1a05d43 fadd za\.s\[w10, 3, vgx2\], {z10\.s-z11\.s} +[^:]+: c1a11c00 fadd za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a11c00 fadd za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a11c00 fadd za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a11c00 fadd za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a17c00 fadd za\.s\[w11, 0, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a11c07 fadd za\.s\[w8, 7, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a11f80 fadd za\.s\[w8, 0, vgx4\], {z28\.s-z31\.s} +[^:]+: c1a17d81 fadd za\.s\[w11, 1, vgx4\], {z12\.s-z15\.s} +[^:]+: c1a01c08 fsub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a01c08 fsub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a01c08 fsub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a01c08 fsub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a07c08 fsub za\.s\[w11, 0, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a01c0f fsub za\.s\[w8, 7, vgx2\], {z0\.s-z1\.s} +[^:]+: c1a01fc8 fsub za\.s\[w8, 0, vgx2\], {z30\.s-z31\.s} +[^:]+: c1a05d4b fsub za\.s\[w10, 3, vgx2\], {z10\.s-z11\.s} +[^:]+: c1a11c08 fsub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a11c08 fsub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a11c08 fsub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a11c08 fsub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a17c08 fsub za\.s\[w11, 0, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a11c0f fsub za\.s\[w8, 7, vgx4\], {z0\.s-z3\.s} +[^:]+: c1a11f88 fsub za\.s\[w8, 0, vgx4\], {z28\.s-z31\.s} +[^:]+: c1a17d89 fsub za\.s\[w11, 1, vgx4\], {z12\.s-z15\.s} diff --git a/gas/testsuite/gas/aarch64/sme2-9.s b/gas/testsuite/gas/aarch64/sme2-9.s new file mode 100644 index 00000000000..838e75b684e --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-9.s @@ -0,0 +1,199 @@ + add za.s[w8, 0], { z0.s - z1.s } + add za.s[w8, 0, vgx2], { z0.s - z1.s } + ADD ZA.s[W8, 0, VGx2], { Z0.s - Z1.s } + ADD ZA.S[W8, 0, VGX2], { Z0.S - Z1.S } + add za.s[w11, 0], { z0.s - z1.s } + add za.s[w8, 7], { z0.s - z1.s } + add za.s[w8, 0], { z30.s - z31.s } + add za.s[w10, 3], { z10.s - z11.s } + + add za.s[w8, 0], { z0.s - z3.s } + add za.s[w8, 0, vgx4], { z0.s - z3.s } + ADD ZA.s[W8, 0, VGx4], { Z0.s - Z3.s } + ADD ZA.S[W8, 0, VGX4], { Z0.S - Z3.S } + add za.s[w11, 0], { z0.s - z3.s } + add za.s[w8, 7], { z0.s - z3.s } + add za.s[w8, 0], { z28.s - z31.s } + add za.s[w11, 1], { z12.s - z15.s } + + add za.s[w8, 0], { z0.s - z1.s }, z0.s + add za.s[w8, 0, vgx2], { z0.s - z1.s }, z0.s + ADD ZA.s[W8, 0, VGx2], { Z0.s - Z1.s }, Z0.s + ADD ZA.S[W8, 0, VGX2], { Z0.S - Z1.S }, Z0.S + add za.s[w11, 0], { z0.s - z1.s }, z0.s + add za.s[w8, 7], { z0.s - z1.s }, z0.s + add za.s[w8, 0], { z30.s - z31.s }, z0.s + add za.s[w8, 0], { z31.s, z0.s }, z0.s + add za.s[w8, 0], { z31.s - z0.s }, z0.s + add za.s[w8, 0], { z0.s - z1.s }, z15.s + add za.s[w9, 5], { z9.s - z10.s }, z6.s + + add za.s[w8, 0], { z0.s - z3.s }, z0.s + add za.s[w8, 0, vgx4], { z0.s - z3.s }, z0.s + ADD ZA.s[W8, 0, VGx4], { Z0.s - Z3.s }, Z0.s + ADD ZA.S[W8, 0, VGX4], { Z0.S - Z3.S }, Z0.S + add za.s[w11, 0], { z0.s - z3.s }, z0.s + add za.s[w8, 7], { z0.s - z3.s }, z0.s + add za.s[w8, 0], { z28.s - z31.s }, z0.s + add za.s[w8, 0], { z31.s, z0.s, z1.s, z2.s }, z0.s + add za.s[w8, 0], { z31.s - z2.s }, z0.s + add za.s[w8, 0], { z0.s - z3.s }, z15.s + add za.s[w11, 2], { z23.s - z26.s }, z13.s + + add za.s[w8, 0], { z0.s - z1.s }, { z0.s - z1.s } + add za.s[w8, 0, vgx2], { z0.s - z1.s }, { z0.s - z1.s } + ADD ZA.s[W8, 0, VGx2], { Z0.s - Z1.s }, { Z0.s - Z1.s } + ADD ZA.S[W8, 0, VGX2], { Z0.S - Z1.S }, { Z0.S - Z1.S } + add za.s[w11, 0], { z0.s - z1.s }, { z0.s - z1.s } + add za.s[w8, 7], { z0.s - z1.s }, { z0.s - z1.s } + add za.s[w8, 0], { z30.s - z31.s }, { z0.s - z1.s } + add za.s[w8, 0], { z0.s - z1.s }, { z30.s - z31.s } + add za.s[w10, 1], { z22.s - z23.s }, { z18.s - z19.s } + + add za.s[w8, 0], { z0.s - z3.s }, { z0.s - z3.s } + add za.s[w8, 0, vgx4], { z0.s - z3.s }, { z0.s - z3.s } + ADD ZA.s[W8, 0, VGx4], { Z0.s - Z3.s }, { Z0.s - Z3.s } + ADD ZA.S[W8, 0, VGX4], { Z0.S - Z3.S }, { Z0.S - Z3.S } + add za.s[w11, 0], { z0.s - z3.s }, { z0.s - z3.s } + add za.s[w8, 7], { z0.s - z3.s }, { z0.s - z3.s } + add za.s[w8, 0], { z28.s - z31.s }, { z0.s - z3.s } + add za.s[w8, 0], { z0.s - z3.s }, { z28.s - z31.s } + add za.s[w11, 3], { z16.s - z19.s }, { z24.s - z27.s } + + add { z0.b - z1.b }, { z0.b - z1.b }, z0.b + add { z30.b - z31.b }, { z30.b - z31.b }, z0.b + add { z0.b - z1.b }, { z0.b - z1.b }, z15.b + add { z14.b - z15.b }, { z14.b - z15.b }, z5.b + + add { z0.h - z1.h }, { z0.h - z1.h }, z0.h + add { z30.h - z31.h }, { z30.h - z31.h }, z0.h + add { z0.h - z1.h }, { z0.h - z1.h }, z15.h + add { z20.h - z21.h }, { z20.h - z21.h }, z11.h + + add { z0.s - z1.s }, { z0.s - z1.s }, z0.s + add { z30.s - z31.s }, { z30.s - z31.s }, z0.s + add { z0.s - z1.s }, { z0.s - z1.s }, z15.s + add { z2.s - z3.s }, { z2.s - z3.s }, z9.s + + add { z0.d - z1.d }, { z0.d - z1.d }, z0.d + add { z30.d - z31.d }, { z30.d - z31.d }, z0.d + add { z0.d - z1.d }, { z0.d - z1.d }, z15.d + add { z28.d - z29.d }, { z28.d - z29.d }, z1.d + + add { z0.b - z3.b }, { z0.b - z3.b }, z0.b + add { z28.b - z31.b }, { z28.b - z31.b }, z0.b + add { z0.b - z3.b }, { z0.b - z3.b }, z15.b + add { z24.b - z27.b }, { z24.b - z27.b }, z5.b + + add { z0.h - z3.h }, { z0.h - z3.h }, z0.h + add { z28.h - z31.h }, { z28.h - z31.h }, z0.h + add { z0.h - z3.h }, { z0.h - z3.h }, z15.h + add { z20.h - z23.h }, { z20.h - z23.h }, z11.h + + add { z0.s - z3.s }, { z0.s - z3.s }, z0.s + add { z28.s - z31.s }, { z28.s - z31.s }, z0.s + add { z0.s - z3.s }, { z0.s - z3.s }, z15.s + add { z4.s - z7.s }, { z4.s - z7.s }, z9.s + + add { z0.d - z3.d }, { z0.d - z3.d }, z0.d + add { z28.d - z31.d }, { z28.d - z31.d }, z0.d + add { z0.d - z3.d }, { z0.d - z3.d }, z15.d + add { z16.d - z19.d }, { z16.d - z19.d }, z3.d + + sub za.s[w8, 0], { z0.s - z1.s } + sub za.s[w8, 0, vgx2], { z0.s - z1.s } + SUB ZA.s[W8, 0, VGx2], { Z0.s - Z1.s } + SUB ZA.S[W8, 0, VGX2], { Z0.S - Z1.S } + sub za.s[w11, 0], { z0.s - z1.s } + sub za.s[w8, 7], { z0.s - z1.s } + sub za.s[w8, 0], { z30.s - z31.s } + sub za.s[w10, 3], { z10.s - z11.s } + + sub za.s[w8, 0], { z0.s - z3.s } + sub za.s[w8, 0, vgx4], { z0.s - z3.s } + SUB ZA.s[W8, 0, VGx4], { Z0.s - Z3.s } + SUB ZA.S[W8, 0, VGX4], { Z0.S - Z3.S } + sub za.s[w11, 0], { z0.s - z3.s } + sub za.s[w8, 7], { z0.s - z3.s } + sub za.s[w8, 0], { z28.s - z31.s } + sub za.s[w11, 1], { z12.s - z15.s } + + sub za.s[w8, 0], { z0.s - z1.s }, z0.s + sub za.s[w8, 0, vgx2], { z0.s - z1.s }, z0.s + SUB ZA.s[W8, 0, VGx2], { Z0.s - Z1.s }, Z0.s + SUB ZA.S[W8, 0, VGX2], { Z0.S - Z1.S }, Z0.S + sub za.s[w11, 0], { z0.s - z1.s }, z0.s + sub za.s[w8, 7], { z0.s - z1.s }, z0.s + sub za.s[w8, 0], { z30.s - z31.s }, z0.s + sub za.s[w8, 0], { z31.s, z0.s }, z0.s + sub za.s[w8, 0], { z31.s - z0.s }, z0.s + sub za.s[w8, 0], { z0.s - z1.s }, z15.s + sub za.s[w9, 5], { z9.s - z10.s }, z6.s + + sub za.s[w8, 0], { z0.s - z3.s }, z0.s + sub za.s[w8, 0, vgx4], { z0.s - z3.s }, z0.s + SUB ZA.s[W8, 0, VGx4], { Z0.s - Z3.s }, Z0.s + SUB ZA.S[W8, 0, VGX4], { Z0.S - Z3.S }, Z0.S + sub za.s[w11, 0], { z0.s - z3.s }, z0.s + sub za.s[w8, 7], { z0.s - z3.s }, z0.s + sub za.s[w8, 0], { z28.s - z31.s }, z0.s + sub za.s[w8, 0], { z31.s, z0.s, z1.s, z2.s }, z0.s + sub za.s[w8, 0], { z31.s - z2.s }, z0.s + sub za.s[w8, 0], { z0.s - z3.s }, z15.s + sub za.s[w11, 2], { z23.s - z26.s }, z13.s + + sub za.s[w8, 0], { z0.s - z1.s }, { z0.s - z1.s } + sub za.s[w8, 0, vgx2], { z0.s - z1.s }, { z0.s - z1.s } + SUB ZA.s[W8, 0, VGx2], { Z0.s - Z1.s }, { Z0.s - Z1.s } + SUB ZA.S[W8, 0, VGX2], { Z0.S - Z1.S }, { Z0.S - Z1.S } + sub za.s[w11, 0], { z0.s - z1.s }, { z0.s - z1.s } + sub za.s[w8, 7], { z0.s - z1.s }, { z0.s - z1.s } + sub za.s[w8, 0], { z30.s - z31.s }, { z0.s - z1.s } + sub za.s[w8, 0], { z0.s - z1.s }, { z30.s - z31.s } + sub za.s[w10, 1], { z22.s - z23.s }, { z18.s - z19.s } + + sub za.s[w8, 0], { z0.s - z3.s }, { z0.s - z3.s } + sub za.s[w8, 0, vgx4], { z0.s - z3.s }, { z0.s - z3.s } + SUB ZA.s[W8, 0, VGx4], { Z0.s - Z3.s }, { Z0.s - Z3.s } + SUB ZA.S[W8, 0, VGX4], { Z0.S - Z3.S }, { Z0.S - Z3.S } + sub za.s[w11, 0], { z0.s - z3.s }, { z0.s - z3.s } + sub za.s[w8, 7], { z0.s - z3.s }, { z0.s - z3.s } + sub za.s[w8, 0], { z28.s - z31.s }, { z0.s - z3.s } + sub za.s[w8, 0], { z0.s - z3.s }, { z28.s - z31.s } + sub za.s[w11, 3], { z16.s - z19.s }, { z24.s - z27.s } + + fadd za.s[w8, 0], { z0.s - z1.s } + fadd za.s[w8, 0, vgx2], { z0.s - z1.s } + FADD ZA.s[W8, 0, VGx2], { Z0.s - Z1.s } + FADD ZA.S[W8, 0, VGX2], { Z0.S - Z1.S } + fadd za.s[w11, 0], { z0.s - z1.s } + fadd za.s[w8, 7], { z0.s - z1.s } + fadd za.s[w8, 0], { z30.s - z31.s } + fadd za.s[w10, 3], { z10.s - z11.s } + + fadd za.s[w8, 0], { z0.s - z3.s } + fadd za.s[w8, 0, vgx4], { z0.s - z3.s } + FADD ZA.s[W8, 0, VGx4], { Z0.s - Z3.s } + FADD ZA.S[W8, 0, VGX4], { Z0.S - Z3.S } + fadd za.s[w11, 0], { z0.s - z3.s } + fadd za.s[w8, 7], { z0.s - z3.s } + fadd za.s[w8, 0], { z28.s - z31.s } + fadd za.s[w11, 1], { z12.s - z15.s } + + fsub za.s[w8, 0], { z0.s - z1.s } + fsub za.s[w8, 0, vgx2], { z0.s - z1.s } + FSUB ZA.s[W8, 0, VGx2], { Z0.s - Z1.s } + FSUB ZA.S[W8, 0, VGX2], { Z0.S - Z1.S } + fsub za.s[w11, 0], { z0.s - z1.s } + fsub za.s[w8, 7], { z0.s - z1.s } + fsub za.s[w8, 0], { z30.s - z31.s } + fsub za.s[w10, 3], { z10.s - z11.s } + + fsub za.s[w8, 0], { z0.s - z3.s } + fsub za.s[w8, 0, vgx4], { z0.s - z3.s } + FSUB ZA.s[W8, 0, VGx4], { Z0.s - Z3.s } + FSUB ZA.S[W8, 0, VGX4], { Z0.S - Z3.S } + fsub za.s[w11, 0], { z0.s - z3.s } + fsub za.s[w8, 7], { z0.s - z3.s } + fsub za.s[w8, 0], { z28.s - z31.s } + fsub za.s[w11, 1], { z12.s - z15.s } diff --git a/gas/testsuite/gas/aarch64/sme2-f64f64-1-invalid.d b/gas/testsuite/gas/aarch64/sme2-f64f64-1-invalid.d new file mode 100644 index 00000000000..f3a623dd9e8 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-f64f64-1-invalid.d @@ -0,0 +1,3 @@ +#as: -march=armv8-a +#source: sme2-f64f64-1-invalid.s +#error_output: sme2-f64f64-1-invalid.l diff --git a/gas/testsuite/gas/aarch64/sme2-f64f64-1-invalid.l b/gas/testsuite/gas/aarch64/sme2-f64f64-1-invalid.l new file mode 100644 index 00000000000..60ee8bd0f8e --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-f64f64-1-invalid.l @@ -0,0 +1,27 @@ +[^ :]+: Assembler messages: +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fadd za\.d\[w7,0\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fadd za\.d\[w12,0\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fadd za\.d\[w8,-1\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fadd za\.d\[w8,8\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `fadd za\.d\[w8,0\],{z0\.d-z2\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fadd za\.d\[w8,0\],{z1\.d-z2\.d}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fadd za\.d\[w7,0\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fadd za\.d\[w12,0\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fadd za\.d\[w8,-1\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fadd za\.d\[w8,8\],{z1\.d-z3\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fadd za\.d\[w8,0\],{z1\.d-z4\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fadd za\.d\[w8,0\],{z2\.d-z5\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fadd za\.d\[w8,0\],{z3\.d-z6\.d}' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `fadd za\.d\[w8,0,vgx4\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `fadd za\.d\[w8,0,vgx2\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: operand mismatch -- `fadd za\[w8,0\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: fadd za\.d\[w8, 0\], {z0\.d-z1\.d} +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: fadd za\.s\[w8, 0\], {z0\.s-z1\.s} +[^ :]+:[0-9]+: Error: missing type suffix at operand 2 -- `fadd za\.d\[w8,0\],{z0-z1}' +[^ :]+:[0-9]+: Error: operand mismatch -- `fadd za\.d\[w8,0\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: fadd za\.s\[w8, 0\], {z0\.s-z1\.s} +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: fadd za\.d\[w8, 0\], {z0\.d-z1\.d} diff --git a/gas/testsuite/gas/aarch64/sme2-f64f64-1-invalid.s b/gas/testsuite/gas/aarch64/sme2-f64f64-1-invalid.s new file mode 100644 index 00000000000..e045dcd984a --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-f64f64-1-invalid.s @@ -0,0 +1,20 @@ + fadd za.d[w7, 0], { z0.d - z1.d } + fadd za.d[w12, 0], { z0.d - z1.d } + fadd za.d[w8, -1], { z0.d - z1.d } + fadd za.d[w8, 8], { z0.d - z1.d } + fadd za.d[w8, 0], { z0.d - z2.d } + fadd za.d[w8, 0], { z1.d - z2.d } + + fadd za.d[w7, 0], { z0.d - z3.d } + fadd za.d[w12, 0], { z0.d - z3.d } + fadd za.d[w8, -1], { z0.d - z3.d } + fadd za.d[w8, 8], { z1.d - z3.d } + fadd za.d[w8, 0], { z1.d - z4.d } + fadd za.d[w8, 0], { z2.d - z5.d } + fadd za.d[w8, 0], { z3.d - z6.d } + + fadd za.d[w8, 0, vgx4], { z0.d - z1.d } + fadd za.d[w8, 0, vgx2], { z0.d - z3.d } + fadd za[w8, 0], { z0.d - z1.d } + fadd za.d[w8, 0], { z0 - z1 } + fadd za.d[w8, 0], { z0.s - z1.s } diff --git a/gas/testsuite/gas/aarch64/sme2-f64f64-1-noarch.d b/gas/testsuite/gas/aarch64/sme2-f64f64-1-noarch.d new file mode 100644 index 00000000000..fe14d018a2f --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-f64f64-1-noarch.d @@ -0,0 +1,3 @@ +#as: -march=armv8-a+sme2 +#source: sme2-f64f64-1.s +#error_output: sme2-f64f64-1-noarch.l diff --git a/gas/testsuite/gas/aarch64/sme2-f64f64-1-noarch.l b/gas/testsuite/gas/aarch64/sme2-f64f64-1-noarch.l new file mode 100644 index 00000000000..f3750f5b171 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-f64f64-1-noarch.l @@ -0,0 +1,33 @@ +[^ :]+: Assembler messages: +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.d\[w8,0\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.d\[w8,0,vgx2\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd ZA\.d\[W8,0,VGx2\],{Z0\.d-Z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd ZA\.D\[W8,0,VGX2\],{Z0\.D-Z1\.D}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.d\[w11,0\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.d\[w8,7\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.d\[w8,0\],{z30\.d-z31\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.d\[w10,3\],{z10\.d-z11\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.d\[w8,0\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.d\[w8,0,vgx4\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd ZA\.d\[W8,0,VGx4\],{Z0\.d-Z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd ZA\.D\[W8,0,VGX4\],{Z0\.D-Z3\.D}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.d\[w11,0\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.d\[w8,7\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.d\[w8,0\],{z28\.d-z31\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.d\[w11,1\],{z12\.d-z15\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.d\[w8,0\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.d\[w8,0,vgx2\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub ZA\.d\[W8,0,VGx2\],{Z0\.d-Z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub ZA\.D\[W8,0,VGX2\],{Z0\.D-Z1\.D}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.d\[w11,0\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.d\[w8,7\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.d\[w8,0\],{z30\.d-z31\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.d\[w10,3\],{z10\.d-z11\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.d\[w8,0\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.d\[w8,0,vgx4\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub ZA\.d\[W8,0,VGx4\],{Z0\.d-Z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub ZA\.D\[W8,0,VGX4\],{Z0\.D-Z3\.D}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.d\[w11,0\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.d\[w8,7\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.d\[w8,0\],{z28\.d-z31\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.d\[w11,1\],{z12\.d-z15\.d}' diff --git a/gas/testsuite/gas/aarch64/sme2-f64f64-1.d b/gas/testsuite/gas/aarch64/sme2-f64f64-1.d new file mode 100644 index 00000000000..3f3d167a4e8 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-f64f64-1.d @@ -0,0 +1,41 @@ +#as: -march=armv8-a+sme2+sme-f64f64 +#objdump: -dr + +[^:]+: file format .* + + +[^:]+: + +[^:]+: +[^:]+: c1e01c00 fadd za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d} +[^:]+: c1e01c00 fadd za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d} +[^:]+: c1e01c00 fadd za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d} +[^:]+: c1e01c00 fadd za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d} +[^:]+: c1e07c00 fadd za\.d\[w11, 0, vgx2\], {z0\.d-z1\.d} +[^:]+: c1e01c07 fadd za\.d\[w8, 7, vgx2\], {z0\.d-z1\.d} +[^:]+: c1e01fc0 fadd za\.d\[w8, 0, vgx2\], {z30\.d-z31\.d} +[^:]+: c1e05d43 fadd za\.d\[w10, 3, vgx2\], {z10\.d-z11\.d} +[^:]+: c1e11c00 fadd za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d} +[^:]+: c1e11c00 fadd za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d} +[^:]+: c1e11c00 fadd za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d} +[^:]+: c1e11c00 fadd za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d} +[^:]+: c1e17c00 fadd za\.d\[w11, 0, vgx4\], {z0\.d-z3\.d} +[^:]+: c1e11c07 fadd za\.d\[w8, 7, vgx4\], {z0\.d-z3\.d} +[^:]+: c1e11f80 fadd za\.d\[w8, 0, vgx4\], {z28\.d-z31\.d} +[^:]+: c1e17d81 fadd za\.d\[w11, 1, vgx4\], {z12\.d-z15\.d} +[^:]+: c1e01c08 fsub za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d} +[^:]+: c1e01c08 fsub za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d} +[^:]+: c1e01c08 fsub za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d} +[^:]+: c1e01c08 fsub za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d} +[^:]+: c1e07c08 fsub za\.d\[w11, 0, vgx2\], {z0\.d-z1\.d} +[^:]+: c1e01c0f fsub za\.d\[w8, 7, vgx2\], {z0\.d-z1\.d} +[^:]+: c1e01fc8 fsub za\.d\[w8, 0, vgx2\], {z30\.d-z31\.d} +[^:]+: c1e05d4b fsub za\.d\[w10, 3, vgx2\], {z10\.d-z11\.d} +[^:]+: c1e11c08 fsub za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d} +[^:]+: c1e11c08 fsub za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d} +[^:]+: c1e11c08 fsub za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d} +[^:]+: c1e11c08 fsub za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d} +[^:]+: c1e17c08 fsub za\.d\[w11, 0, vgx4\], {z0\.d-z3\.d} +[^:]+: c1e11c0f fsub za\.d\[w8, 7, vgx4\], {z0\.d-z3\.d} +[^:]+: c1e11f88 fsub za\.d\[w8, 0, vgx4\], {z28\.d-z31\.d} +[^:]+: c1e17d89 fsub za\.d\[w11, 1, vgx4\], {z12\.d-z15\.d} diff --git a/gas/testsuite/gas/aarch64/sme2-f64f64-1.s b/gas/testsuite/gas/aarch64/sme2-f64f64-1.s new file mode 100644 index 00000000000..546f20dd44d --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-f64f64-1.s @@ -0,0 +1,35 @@ + fadd za.d[w8, 0], { z0.d - z1.d } + fadd za.d[w8, 0, vgx2], { z0.d - z1.d } + FADD ZA.d[W8, 0, VGx2], { Z0.d - Z1.d } + FADD ZA.D[W8, 0, VGX2], { Z0.D - Z1.D } + fadd za.d[w11, 0], { z0.d - z1.d } + fadd za.d[w8, 7], { z0.d - z1.d } + fadd za.d[w8, 0], { z30.d - z31.d } + fadd za.d[w10, 3], { z10.d - z11.d } + + fadd za.d[w8, 0], { z0.d - z3.d } + fadd za.d[w8, 0, vgx4], { z0.d - z3.d } + FADD ZA.d[W8, 0, VGx4], { Z0.d - Z3.d } + FADD ZA.D[W8, 0, VGX4], { Z0.D - Z3.D } + fadd za.d[w11, 0], { z0.d - z3.d } + fadd za.d[w8, 7], { z0.d - z3.d } + fadd za.d[w8, 0], { z28.d - z31.d } + fadd za.d[w11, 1], { z12.d - z15.d } + + fsub za.d[w8, 0], { z0.d - z1.d } + fsub za.d[w8, 0, vgx2], { z0.d - z1.d } + FSUB ZA.d[W8, 0, VGx2], { Z0.d - Z1.d } + FSUB ZA.D[W8, 0, VGX2], { Z0.D - Z1.D } + fsub za.d[w11, 0], { z0.d - z1.d } + fsub za.d[w8, 7], { z0.d - z1.d } + fsub za.d[w8, 0], { z30.d - z31.d } + fsub za.d[w10, 3], { z10.d - z11.d } + + fsub za.d[w8, 0], { z0.d - z3.d } + fsub za.d[w8, 0, vgx4], { z0.d - z3.d } + FSUB ZA.d[W8, 0, VGx4], { Z0.d - Z3.d } + FSUB ZA.D[W8, 0, VGX4], { Z0.D - Z3.D } + fsub za.d[w11, 0], { z0.d - z3.d } + fsub za.d[w8, 7], { z0.d - z3.d } + fsub za.d[w8, 0], { z28.d - z31.d } + fsub za.d[w11, 1], { z12.d - z15.d } diff --git a/gas/testsuite/gas/aarch64/sme2-i16i64-1-invalid.d b/gas/testsuite/gas/aarch64/sme2-i16i64-1-invalid.d new file mode 100644 index 00000000000..01172951481 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-i16i64-1-invalid.d @@ -0,0 +1,3 @@ +#as: -march=armv8-a +#source: sme2-i16i64-1-invalid.s +#error_output: sme2-i16i64-1-invalid.l diff --git a/gas/testsuite/gas/aarch64/sme2-i16i64-1-invalid.l b/gas/testsuite/gas/aarch64/sme2-i16i64-1-invalid.l new file mode 100644 index 00000000000..d9d537a63d4 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-i16i64-1-invalid.l @@ -0,0 +1,111 @@ +[^ :]+: Assembler messages: +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.d\[w7,0\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.d\[w12,0\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.d\[w8,-1\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.d\[w8,8\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `add za\.d\[w8,0\],{z0\.d-z2\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `add za\.d\[w8,0\],{z1\.d-z2\.d}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.d\[w7,0\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.d\[w12,0\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.d\[w8,-1\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.d\[w8,8\],{z1\.d-z3\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `add za\.d\[w8,0\],{z1\.d-z4\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `add za\.d\[w8,0\],{z2\.d-z5\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `add za\.d\[w8,0\],{z3\.d-z6\.d}' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `add za\.d\[w8,0,vgx4\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `add za\.d\[w8,0,vgx2\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: operand mismatch -- `add za\[w8,0\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: add za\.d\[w8, 0\], {z0\.d-z1\.d} +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: add za\.s\[w8, 0\], {z0\.s-z1\.s} +[^ :]+:[0-9]+: Error: missing type suffix at operand 2 -- `add za\.d\[w8,0\],{z0-z1}' +[^ :]+:[0-9]+: Error: operand mismatch -- `add za\.d\[w8,0\],{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: add za\.s\[w8, 0\], {z0\.s-z1\.s} +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: add za\.d\[w8, 0\], {z0\.d-z1\.d} +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.d\[w0,0\],{z0\.d-z1\.d},z0\.d' +[^ :]+:[0-9]+: Error: expected a 32-bit selection register at operand 1 -- `add za\.d\[w31,0\],{z0\.d-z1\.d},z0\.d' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.d\[w8,1<<63\],{z0\.d-z1\.d},z0\.d' +[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `add za\.d\[w8,0\],{z0\.d-z1\.d},z31\.d' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.d\[w7,0\],{z0\.d-z1\.d},z0\.d' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.d\[w12,0\],{z0\.d-z1\.d},z0\.d' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.d\[w8,-1\],{z0\.d-z1\.d},z0\.d' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.d\[w8,8\],{z0\.d-z1\.d},z0\.d' +[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `add za\.d\[w8,0\],{z0\.d-z1\.d},z16\.d' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.d\[w7,0\],{z0\.d-z3\.d},z0\.d' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.d\[w12,0\],{z0\.d-z3\.d},z0\.d' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.d\[w8,-1\],{z0\.d-z3\.d},z0\.d' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.d\[w8,8\],{z0\.d-z3\.d},z0\.d' +[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `add za\.d\[w8,0\],{z0\.d-z3\.d},z16\.d' +[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `add za\.d\[w8,0\],{z0\.d-z2\.d},z0\.d' +[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 2 -- `add za\.d\[w8,0\],{z0\.d-z4\.d},z0\.d' +[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `add za\.d\[w8,0\],{z0\.d,z1\.d,z2\.d},z0\.d' +[^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `add za\.d\[w8,0\],{z0\.d,z1\.d,z5\.d},z0\.d' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `add za\.d\[w8,0,vgx4\],{z0\.d-z1\.d},z0\.d' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `add za\.d\[w8,0,vgx2\],{z0\.d-z3\.d},z0\.d' +[^ :]+:[0-9]+: Error: operand mismatch -- `add za\[w8,0\],{z0\.d-z1\.d},z0\.d' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: add za\.d\[w8, 0\], {z0\.d-z1\.d}, z0\.d +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: add za\.s\[w8, 0\], {z0\.s-z1\.s}, z0\.s +[^ :]+:[0-9]+: Error: missing type suffix at operand 2 -- `add za\.d\[w8,0\],{z0-z1},z0\.d' +[^ :]+:[0-9]+: Error: operand mismatch -- `add za\.d\[w8,0\],{z0\.d-z1\.d},z0' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: add za\.d\[w8, 0\], {z0\.d-z1\.d}, z0\.d +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: add za\.s\[w8, 0\], {z0\.s-z1\.s}, z0\.s +[^ :]+:[0-9]+: Error: operand mismatch -- `add za\[w8,0\],{z0\.d-z1\.d},z0' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: add za\.d\[w8, 0\], {z0\.d-z1\.d}, z0\.d +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: add za\.s\[w8, 0\], {z0\.s-z1\.s}, z0\.s +[^ :]+:[0-9]+: Error: operand mismatch -- `add za\.s\[w8,0\],{z0\.d-z1\.d},z0\.s' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: add za\.s\[w8, 0\], {z0\.s-z1\.s}, z0\.s +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: add za\.d\[w8, 0\], {z0\.d-z1\.d}, z0\.d +[^ :]+:[0-9]+: Error: operand mismatch -- `add za\.d\[w8,0\],{z0\.s-z1\.s},z0\.d' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: add za\.d\[w8, 0\], {z0\.d-z1\.d}, z0\.d +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: add za\.s\[w8, 0\], {z0\.s-z1\.s}, z0\.s +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.d\[w0,0\],{z0\.d-z1\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: expected a 32-bit selection register at operand 1 -- `add za\.d\[w31,0\],{z0\.d-z1\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.d\[w8,1<<63\],{z0\.d-z1\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.d\[w7,0\],{z0\.d-z1\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.d\[w12,0\],{z0\.d-z1\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.d\[w8,-1\],{z0\.d-z1\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.d\[w8,8\],{z0\.d-z1\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.d\[w8,8\],{z1\.d-z2\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `add za\.d\[w8,0\],{z0\.d-z1\.d},{z15\.d-z16\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `add za\.d\[w8,0\],{z0\.d-z1\.d},{z31\.d,z0\.d}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.d\[w7,0\],{z0\.d-z3\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.d\[w12,0\],{z0\.d-z3\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.d\[w8,-1\],{z0\.d-z3\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.d\[w8,8\],{z0\.d-z3\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `add za\.d\[w8,0\],{z1\.d-z4\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `add za\.d\[w8,0\],{z2\.d-z5\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `add za\.d\[w8,0\],{z3\.d-z6\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `add za\.d\[w8,0\],{z0\.d-z3\.d},{z15\.d-z18\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `add za\.d\[w8,0\],{z0\.d-z3\.d},{z29\.d,z30\.d,z31\.d,z0\.d}' +[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `add za\.d\[w8,0\],{z0\.d-z2\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 3 -- `add za\.d\[w8,0\],{z0\.d-z3\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `add za\.d\[w8,0\],{z0\.d-z1\.d},{z0\.d-z2\.d}' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `add za\.d\[w8,0\],{z0\.d-z1\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 3 -- `add za\.d\[w8,0\],{z0\.d-z1\.d},{z0\.d-z4\.d}' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `add za\.d\[w8,0,vgx4\],{z0\.d-z1\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 3 -- `add za\.d\[w8,0,vgx4\],{z0\.d-z3\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `add za\.d\[w8,0,vgx2\],{z0\.d-z1\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `add za\.d\[w8,0,vgx2\],{z0\.d-z3\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: operand mismatch -- `add za\[w8,0\],{z0\.d-z1\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: add za\.d\[w8, 0\], {z0\.d-z1\.d}, {z0\.d-z1\.d} +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: add za\.s\[w8, 0\], {z0\.s-z1\.s}, {z0\.s-z1\.s} +[^ :]+:[0-9]+: Error: operand mismatch -- `add za\[w8,0\],{z0\.d-z3\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: add za\.d\[w8, 0\], {z0\.d-z3\.d}, {z0\.d-z3\.d} +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: add za\.s\[w8, 0\], {z0\.s-z3\.s}, {z0\.s-z3\.s} diff --git a/gas/testsuite/gas/aarch64/sme2-i16i64-1-invalid.s b/gas/testsuite/gas/aarch64/sme2-i16i64-1-invalid.s new file mode 100644 index 00000000000..ef2e48d2477 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-i16i64-1-invalid.s @@ -0,0 +1,86 @@ + add za.d[w7, 0], { z0.d - z1.d } + add za.d[w12, 0], { z0.d - z1.d } + add za.d[w8, -1], { z0.d - z1.d } + add za.d[w8, 8], { z0.d - z1.d } + add za.d[w8, 0], { z0.d - z2.d } + add za.d[w8, 0], { z1.d - z2.d } + + add za.d[w7, 0], { z0.d - z3.d } + add za.d[w12, 0], { z0.d - z3.d } + add za.d[w8, -1], { z0.d - z3.d } + add za.d[w8, 8], { z1.d - z3.d } + add za.d[w8, 0], { z1.d - z4.d } + add za.d[w8, 0], { z2.d - z5.d } + add za.d[w8, 0], { z3.d - z6.d } + + add za.d[w8, 0, vgx4], { z0.d - z1.d } + add za.d[w8, 0, vgx2], { z0.d - z3.d } + add za[w8, 0], { z0.d - z1.d } + add za.d[w8, 0], { z0 - z1 } + add za.d[w8, 0], { z0.s - z1.s } + + add za.d[w0, 0], { z0.d - z1.d }, z0.d + add za.d[w31, 0], { z0.d - z1.d }, z0.d + add za.d[w8, 1<<63], { z0.d - z1.d }, z0.d + add za.d[w8, 0], { z0.d - z1.d }, z31.d + + add za.d[w7, 0], { z0.d - z1.d }, z0.d + add za.d[w12, 0], { z0.d - z1.d }, z0.d + add za.d[w8, -1], { z0.d - z1.d }, z0.d + add za.d[w8, 8], { z0.d - z1.d }, z0.d + add za.d[w8, 0], { z0.d - z1.d }, z16.d + + add za.d[w7, 0], { z0.d - z3.d }, z0.d + add za.d[w12, 0], { z0.d - z3.d }, z0.d + add za.d[w8, -1], { z0.d - z3.d }, z0.d + add za.d[w8, 8], { z0.d - z3.d }, z0.d + add za.d[w8, 0], { z0.d - z3.d }, z16.d + + add za.d[w8, 0], { z0.d - z2.d }, z0.d + add za.d[w8, 0], { z0.d - z4.d }, z0.d + add za.d[w8, 0], { z0.d, z1.d, z2.d }, z0.d + add za.d[w8, 0], { z0.d, z1.d, z5.d }, z0.d + + add za.d[w8, 0, vgx4], { z0.d - z1.d }, z0.d + add za.d[w8, 0, vgx2], { z0.d - z3.d }, z0.d + add za[w8, 0], { z0.d - z1.d }, z0.d + add za.d[w8, 0], { z0 - z1 }, z0.d + add za.d[w8, 0], { z0.d - z1.d }, z0 + add za[w8, 0], { z0.d - z1.d }, z0 + add za.s[w8, 0], { z0.d - z1.d }, z0.s + add za.d[w8, 0], { z0.s - z1.s }, z0.d + + add za.d[w0, 0], { z0.d - z1.d }, { z0.d - z1.d } + add za.d[w31, 0], { z0.d - z1.d }, { z0.d - z1.d } + add za.d[w8, 1<<63], { z0.d - z1.d }, { z0.d - z1.d } + + add za.d[w7, 0], { z0.d - z1.d }, { z0.d - z1.d } + add za.d[w12, 0], { z0.d - z1.d }, { z0.d - z1.d } + add za.d[w8, -1], { z0.d - z1.d }, { z0.d - z1.d } + add za.d[w8, 8], { z0.d - z1.d }, { z0.d - z1.d } + add za.d[w8, 8], { z1.d - z2.d }, { z0.d - z1.d } + add za.d[w8, 0], { z0.d - z1.d }, { z15.d - z16.d } + add za.d[w8, 0], { z0.d - z1.d }, { z31.d, z0.d } + + add za.d[w7, 0], { z0.d - z3.d }, { z0.d - z3.d } + add za.d[w12, 0], { z0.d - z3.d }, { z0.d - z3.d } + add za.d[w8, -1], { z0.d - z3.d }, { z0.d - z3.d } + add za.d[w8, 8], { z0.d - z3.d }, { z0.d - z3.d } + add za.d[w8, 0], { z1.d - z4.d }, { z0.d - z3.d } + add za.d[w8, 0], { z2.d - z5.d }, { z0.d - z3.d } + add za.d[w8, 0], { z3.d - z6.d }, { z0.d - z3.d } + add za.d[w8, 0], { z0.d - z3.d }, { z15.d - z18.d } + add za.d[w8, 0], { z0.d - z3.d }, { z29.d, z30.d, z31.d, z0.d } + + add za.d[w8, 0], { z0.d - z2.d }, { z0.d - z1.d } + add za.d[w8, 0], { z0.d - z3.d }, { z0.d - z1.d } + add za.d[w8, 0], { z0.d - z1.d }, { z0.d - z2.d } + add za.d[w8, 0], { z0.d - z1.d }, { z0.d - z3.d } + add za.d[w8, 0], { z0.d - z1.d }, { z0.d - z4.d } + + add za.d[w8, 0, vgx4], { z0.d - z1.d }, { z0.d - z3.d } + add za.d[w8, 0, vgx4], { z0.d - z3.d }, { z0.d - z1.d } + add za.d[w8, 0, vgx2], { z0.d - z1.d }, { z0.d - z3.d } + add za.d[w8, 0, vgx2], { z0.d - z3.d }, { z0.d - z1.d } + add za[w8, 0], { z0.d - z1.d }, { z0.d - z1.d } + add za[w8, 0], { z0.d - z3.d }, { z0.d - z3.d } diff --git a/gas/testsuite/gas/aarch64/sme2-i16i64-1-noarch.d b/gas/testsuite/gas/aarch64/sme2-i16i64-1-noarch.d new file mode 100644 index 00000000000..fe924efd561 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-i16i64-1-noarch.d @@ -0,0 +1,3 @@ +#as: -march=armv8-a+sme2 +#source: sme2-i16i64-1.s +#error_output: sme2-i16i64-1-noarch.l diff --git a/gas/testsuite/gas/aarch64/sme2-i16i64-1-noarch.l b/gas/testsuite/gas/aarch64/sme2-i16i64-1-noarch.l new file mode 100644 index 00000000000..bbdccc7ac63 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-i16i64-1-noarch.l @@ -0,0 +1,57 @@ +[^ :]+: Assembler messages: +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0,vgx2\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.d\[W8,0,VGx2\],{Z0\.d-Z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.D\[W8,0,VGX2\],{Z0\.D-Z1\.D}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w11,0\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,7\],{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0\],{z30\.d-z31\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w10,3\],{z10\.d-z11\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0,vgx4\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.d\[W8,0,VGx4\],{Z0\.d-Z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.D\[W8,0,VGX4\],{Z0\.D-Z3\.D}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w11,0\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,7\],{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0\],{z28\.d-z31\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w11,1\],{z12\.d-z15\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0\],{z0\.d-z1\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0,vgx2\],{z0\.d-z1\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.d\[W8,0,VGx2\],{Z0\.d-Z1\.d},Z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.D\[W8,0,VGX2\],{Z0\.D-Z1\.D},Z0\.D' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w11,0\],{z0\.d-z1\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,7\],{z0\.d-z1\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0\],{z30\.d-z31\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0\],{z31\.d,z0\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0\],{z31\.d-z0\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0\],{z0\.d-z1\.d},z15\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w9,5\],{z9\.d-z10\.d},z6\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0\],{z0\.d-z3\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0,vgx4\],{z0\.d-z3\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.d\[W8,0,VGx4\],{Z0\.d-Z3\.d},Z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.D\[W8,0,VGX4\],{Z0\.D-Z3\.D},Z0\.D' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w11,0\],{z0\.d-z3\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,7\],{z0\.d-z3\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0\],{z28\.d-z31\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0\],{z31\.d,z0\.d,z1\.d,z2\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0\],{z31\.d-z2\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0\],{z0\.d-z3\.d},z15\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w11,2\],{z23\.d-z26\.d},z13\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0\],{z0\.d-z1\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0,vgx2\],{z0\.d-z1\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.d\[W8,0,VGx2\],{Z0\.d-Z1\.d},{Z0\.d-Z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.D\[W8,0,VGX2\],{Z0\.D-Z1\.D},{Z0\.D-Z1\.D}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w11,0\],{z0\.d-z1\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,7\],{z0\.d-z1\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0\],{z30\.d-z31\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0\],{z0\.d-z1\.d},{z30\.d-z31\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w10,1\],{z22\.d-z23\.d},{z18\.d-z19\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0\],{z0\.d-z3\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0,vgx4\],{z0\.d-z3\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.d\[W8,0,VGx4\],{Z0\.d-Z3\.d},{Z0\.d-Z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.D\[W8,0,VGX4\],{Z0\.D-Z3\.D},{Z0\.D-Z3\.D}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w11,0\],{z0\.d-z3\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,7\],{z0\.d-z3\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0\],{z28\.d-z31\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0\],{z0\.d-z3\.d},{z28\.d-z31\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w11,3\],{z16\.d-z19\.d},{z24\.d-z27\.d}' diff --git a/gas/testsuite/gas/aarch64/sme2-i16i64-1.d b/gas/testsuite/gas/aarch64/sme2-i16i64-1.d new file mode 100644 index 00000000000..8b95f5d3974 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-i16i64-1.d @@ -0,0 +1,65 @@ +#as: -march=armv8-a+sme2+sme-i16i64 +#objdump: -dr + +[^:]+: file format .* + + +[^:]+: + +[^:]+: +[^:]+: c1e01c10 add za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d} +[^:]+: c1e01c10 add za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d} +[^:]+: c1e01c10 add za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d} +[^:]+: c1e01c10 add za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d} +[^:]+: c1e07c10 add za\.d\[w11, 0, vgx2\], {z0\.d-z1\.d} +[^:]+: c1e01c17 add za\.d\[w8, 7, vgx2\], {z0\.d-z1\.d} +[^:]+: c1e01fd0 add za\.d\[w8, 0, vgx2\], {z30\.d-z31\.d} +[^:]+: c1e05d53 add za\.d\[w10, 3, vgx2\], {z10\.d-z11\.d} +[^:]+: c1e11c10 add za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d} +[^:]+: c1e11c10 add za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d} +[^:]+: c1e11c10 add za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d} +[^:]+: c1e11c10 add za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d} +[^:]+: c1e17c10 add za\.d\[w11, 0, vgx4\], {z0\.d-z3\.d} +[^:]+: c1e11c17 add za\.d\[w8, 7, vgx4\], {z0\.d-z3\.d} +[^:]+: c1e11f90 add za\.d\[w8, 0, vgx4\], {z28\.d-z31\.d} +[^:]+: c1e17d91 add za\.d\[w11, 1, vgx4\], {z12\.d-z15\.d} +[^:]+: c1601810 add za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d +[^:]+: c1601810 add za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d +[^:]+: c1601810 add za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d +[^:]+: c1601810 add za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d +[^:]+: c1607810 add za\.d\[w11, 0, vgx2\], {z0\.d-z1\.d}, z0\.d +[^:]+: c1601817 add za\.d\[w8, 7, vgx2\], {z0\.d-z1\.d}, z0\.d +[^:]+: c1601bd0 add za\.d\[w8, 0, vgx2\], {z30\.d-z31\.d}, z0\.d +[^:]+: c1601bf0 add za\.d\[w8, 0, vgx2\], {z31\.d-z0\.d}, z0\.d +[^:]+: c1601bf0 add za\.d\[w8, 0, vgx2\], {z31\.d-z0\.d}, z0\.d +[^:]+: c16f1810 add za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z15\.d +[^:]+: c1663935 add za\.d\[w9, 5, vgx2\], {z9\.d-z10\.d}, z6\.d +[^:]+: c1701810 add za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d +[^:]+: c1701810 add za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d +[^:]+: c1701810 add za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d +[^:]+: c1701810 add za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d +[^:]+: c1707810 add za\.d\[w11, 0, vgx4\], {z0\.d-z3\.d}, z0\.d +[^:]+: c1701817 add za\.d\[w8, 7, vgx4\], {z0\.d-z3\.d}, z0\.d +[^:]+: c1701b90 add za\.d\[w8, 0, vgx4\], {z28\.d-z31\.d}, z0\.d +[^:]+: c1701bf0 add za\.d\[w8, 0, vgx4\], {z31\.d-z2\.d}, z0\.d +[^:]+: c1701bf0 add za\.d\[w8, 0, vgx4\], {z31\.d-z2\.d}, z0\.d +[^:]+: c17f1810 add za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z15\.d +[^:]+: c17d7af2 add za\.d\[w11, 2, vgx4\], {z23\.d-z26\.d}, z13\.d +[^:]+: c1e01810 add za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d} +[^:]+: c1e01810 add za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d} +[^:]+: c1e01810 add za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d} +[^:]+: c1e01810 add za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d} +[^:]+: c1e07810 add za\.d\[w11, 0, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d} +[^:]+: c1e01817 add za\.d\[w8, 7, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d} +[^:]+: c1e01bd0 add za\.d\[w8, 0, vgx2\], {z30\.d-z31\.d}, {z0\.d-z1\.d} +[^:]+: c1fe1810 add za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, {z30\.d-z31\.d} +[^:]+: c1f25ad1 add za\.d\[w10, 1, vgx2\], {z22\.d-z23\.d}, {z18\.d-z19\.d} +[^:]+: c1e11810 add za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d} +[^:]+: c1e11810 add za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d} +[^:]+: c1e11810 add za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d} +[^:]+: c1e11810 add za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d} +[^:]+: c1e17810 add za\.d\[w11, 0, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d} +[^:]+: c1e11817 add za\.d\[w8, 7, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d} +[^:]+: c1e11b90 add za\.d\[w8, 0, vgx4\], {z28\.d-z31\.d}, {z0\.d-z3\.d} +[^:]+: c1fd1810 add za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, {z28\.d-z31\.d} +[^:]+: c1f97a13 add za\.d\[w11, 3, vgx4\], {z16\.d-z19\.d}, {z24\.d-z27\.d} diff --git a/gas/testsuite/gas/aarch64/sme2-i16i64-1.s b/gas/testsuite/gas/aarch64/sme2-i16i64-1.s new file mode 100644 index 00000000000..537669a1b93 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-i16i64-1.s @@ -0,0 +1,61 @@ + add za.d[w8, 0], { z0.d - z1.d } + add za.d[w8, 0, vgx2], { z0.d - z1.d } + ADD ZA.d[W8, 0, VGx2], { Z0.d - Z1.d } + ADD ZA.D[W8, 0, VGX2], { Z0.D - Z1.D } + add za.d[w11, 0], { z0.d - z1.d } + add za.d[w8, 7], { z0.d - z1.d } + add za.d[w8, 0], { z30.d - z31.d } + add za.d[w10, 3], { z10.d - z11.d } + + add za.d[w8, 0], { z0.d - z3.d } + add za.d[w8, 0, vgx4], { z0.d - z3.d } + ADD ZA.d[W8, 0, VGx4], { Z0.d - Z3.d } + ADD ZA.D[W8, 0, VGX4], { Z0.D - Z3.D } + add za.d[w11, 0], { z0.d - z3.d } + add za.d[w8, 7], { z0.d - z3.d } + add za.d[w8, 0], { z28.d - z31.d } + add za.d[w11, 1], { z12.d - z15.d } + + add za.d[w8, 0], { z0.d - z1.d }, z0.d + add za.d[w8, 0, vgx2], { z0.d - z1.d }, z0.d + ADD ZA.d[W8, 0, VGx2], { Z0.d - Z1.d }, Z0.d + ADD ZA.D[W8, 0, VGX2], { Z0.D - Z1.D }, Z0.D + add za.d[w11, 0], { z0.d - z1.d }, z0.d + add za.d[w8, 7], { z0.d - z1.d }, z0.d + add za.d[w8, 0], { z30.d - z31.d }, z0.d + add za.d[w8, 0], { z31.d, z0.d }, z0.d + add za.d[w8, 0], { z31.d - z0.d }, z0.d + add za.d[w8, 0], { z0.d - z1.d }, z15.d + add za.d[w9, 5], { z9.d - z10.d }, z6.d + + add za.d[w8, 0], { z0.d - z3.d }, z0.d + add za.d[w8, 0, vgx4], { z0.d - z3.d }, z0.d + ADD ZA.d[W8, 0, VGx4], { Z0.d - Z3.d }, Z0.d + ADD ZA.D[W8, 0, VGX4], { Z0.D - Z3.D }, Z0.D + add za.d[w11, 0], { z0.d - z3.d }, z0.d + add za.d[w8, 7], { z0.d - z3.d }, z0.d + add za.d[w8, 0], { z28.d - z31.d }, z0.d + add za.d[w8, 0], { z31.d, z0.d, z1.d, z2.d }, z0.d + add za.d[w8, 0], { z31.d - z2.d }, z0.d + add za.d[w8, 0], { z0.d - z3.d }, z15.d + add za.d[w11, 2], { z23.d - z26.d }, z13.d + + add za.d[w8, 0], { z0.d - z1.d }, { z0.d - z1.d } + add za.d[w8, 0, vgx2], { z0.d - z1.d }, { z0.d - z1.d } + ADD ZA.d[W8, 0, VGx2], { Z0.d - Z1.d }, { Z0.d - Z1.d } + ADD ZA.D[W8, 0, VGX2], { Z0.D - Z1.D }, { Z0.D - Z1.D } + add za.d[w11, 0], { z0.d - z1.d }, { z0.d - z1.d } + add za.d[w8, 7], { z0.d - z1.d }, { z0.d - z1.d } + add za.d[w8, 0], { z30.d - z31.d }, { z0.d - z1.d } + add za.d[w8, 0], { z0.d - z1.d }, { z30.d - z31.d } + add za.d[w10, 1], { z22.d - z23.d }, { z18.d - z19.d } + + add za.d[w8, 0], { z0.d - z3.d }, { z0.d - z3.d } + add za.d[w8, 0, vgx4], { z0.d - z3.d }, { z0.d - z3.d } + ADD ZA.d[W8, 0, VGx4], { Z0.d - Z3.d }, { Z0.d - Z3.d } + ADD ZA.D[W8, 0, VGX4], { Z0.D - Z3.D }, { Z0.D - Z3.D } + add za.d[w11, 0], { z0.d - z3.d }, { z0.d - z3.d } + add za.d[w8, 7], { z0.d - z3.d }, { z0.d - z3.d } + add za.d[w8, 0], { z28.d - z31.d }, { z0.d - z3.d } + add za.d[w8, 0], { z0.d - z3.d }, { z28.d - z31.d } + add za.d[w11, 3], { z16.d - z19.d }, { z24.d - z27.d } diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 69e0f833170..3689fff81f1 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -487,6 +487,7 @@ enum aarch64_opnd AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */ AARCH64_OPND_SME_Zdnx2, /* SVE vector register list from [4:1]*2. */ AARCH64_OPND_SME_Zdnx4, /* SVE vector register list from [4:2]*4. */ + AARCH64_OPND_SME_Zm, /* SVE vector register list in 4-bit Zm. */ AARCH64_OPND_SME_Zmx2, /* SVE vector register list from [20:17]*2. */ AARCH64_OPND_SME_Zmx4, /* SVE vector register list from [20:18]*4. */ AARCH64_OPND_SME_Znx2, /* SVE vector register list from [9:6]*2. */ @@ -695,6 +696,8 @@ enum aarch64_insn_class movewide, pcreladdr, ic_system, + sme_fp_sd, + sme_int_sd, sme_misc, sme_mov, sme_ldr, diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c index cdc9e465d13..5dba041483c 100644 --- a/opcodes/aarch64-asm-2.c +++ b/opcodes/aarch64-asm-2.c @@ -667,12 +667,13 @@ aarch64_insert_operand (const aarch64_operand *self, case 203: case 209: case 212: - case 222: + case 216: case 223: - case 230: + case 224: case 231: case 232: case 233: + case 234: return aarch64_ins_regno (self, info, code, inst, errors); case 15: return aarch64_ins_reg_extended (self, info, code, inst, errors); @@ -684,7 +685,7 @@ aarch64_insert_operand (const aarch64_operand *self, case 33: case 34: case 35: - case 256: + case 257: return aarch64_ins_reglane (self, info, code, inst, errors); case 36: return aarch64_ins_reglist (self, info, code, inst, errors); @@ -729,13 +730,13 @@ aarch64_insert_operand (const aarch64_operand *self, case 192: case 193: case 194: - case 236: - case 250: + case 237: case 251: - case 253: - case 255: - case 260: + case 252: + case 254: + case 256: case 261: + case 262: return aarch64_ins_imm (self, info, code, inst, errors); case 44: case 45: @@ -804,8 +805,8 @@ aarch64_insert_operand (const aarch64_operand *self, case 107: return aarch64_ins_prfop (self, info, code, inst, errors); case 108: - case 252: - case 254: + case 253: + case 255: return aarch64_ins_none (self, info, code, inst, errors); case 109: return aarch64_ins_hint (self, info, code, inst, errors); @@ -896,48 +897,48 @@ aarch64_insert_operand (const aarch64_operand *self, return aarch64_ins_sve_index (self, info, code, inst, errors); case 211: case 213: - case 229: + case 230: return aarch64_ins_sve_reglist (self, info, code, inst, errors); case 214: case 215: - case 216: case 217: case 218: case 219: - case 228: - return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors); case 220: + case 229: + return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors); case 221: + case 222: return aarch64_ins_sve_strided_reglist (self, info, code, inst, errors); - case 224: - case 226: - case 237: - return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors); case 225: case 227: + case 238: + return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors); + case 226: + case 228: return aarch64_ins_sme_za_hv_tiles_range (self, info, code, inst, errors); - case 234: case 235: - case 244: + case 236: case 245: case 246: case 247: case 248: case 249: + case 250: return aarch64_ins_simple_index (self, info, code, inst, errors); - case 238: case 239: case 240: - return aarch64_ins_sme_za_array (self, info, code, inst, errors); case 241: - return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors); + return aarch64_ins_sme_za_array (self, info, code, inst, errors); case 242: - return aarch64_ins_sme_sm_za (self, info, code, inst, errors); + return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors); case 243: + return aarch64_ins_sme_sm_za (self, info, code, inst, errors); + case 244: return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors); - case 257: case 258: case 259: + case 260: return aarch64_ins_x0_to_x30 (self, info, code, inst, errors); default: assert (0); abort (); } diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c index bd03f4116cc..ae699ec2cd5 100644 --- a/opcodes/aarch64-asm.c +++ b/opcodes/aarch64-asm.c @@ -2008,6 +2008,8 @@ aarch64_encode_variant_using_iclass (struct aarch64_inst *inst) insert_field (FLD_size, &inst->value, aarch64_get_variant (inst) % 3 + 1, 0); break; + case sme_fp_sd: + case sme_int_sd: case sve_size_bh: case sve_size_sd: insert_field (FLD_SVE_sz, &inst->value, aarch64_get_variant (inst), 0); diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c index f69f30f8884..c38880201e1 100644 --- a/opcodes/aarch64-dis-2.c +++ b/opcodes/aarch64-dis-2.c @@ -166,7 +166,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000x10x100xxxxxxxxxxxxxxxxx zero. */ - return 2596; + return 2614; } } } @@ -190,7 +190,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000x00x101xx0xxxxxxxxxxxxxx luti4. */ - return 2499; + return 2511; } else { @@ -198,7 +198,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000x00x101xx1xxxxxxxxxxxxxx luti4. */ - return 2498; + return 2510; } } else @@ -207,7 +207,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000x10x101xxxxxxxxxxxxxxxxx luti4. */ - return 2497; + return 2509; } } } @@ -226,7 +226,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000xx0x010xxxxx00xxxxxxxxxx mov. */ - return 2506; + return 2518; } else { @@ -234,7 +234,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000xx0x011xxxxx00xxxxxxxxxx mov. */ - return 2502; + return 2514; } } else @@ -247,7 +247,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000x00x11xxx0xx00xxxxxxxxxx luti2. */ - return 2496; + return 2508; } else { @@ -255,7 +255,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000x00x11xxx1xx00xxxxxxxxxx luti2. */ - return 2495; + return 2507; } } else @@ -268,7 +268,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000010x110xxxxx00xxxxxxxxxx movt. */ - return 2517; + return 2529; } else { @@ -276,7 +276,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000010x111xxxxx00xxxxxxxxxx movt. */ - return 2516; + return 2528; } } else @@ -285,7 +285,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000110x11xxxxxx00xxxxxxxxxx luti2. */ - return 2494; + return 2506; } } } @@ -298,7 +298,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000xx0xx10xxxxx10xxxxxxxxxx mov. */ - return 2504; + return 2516; } else { @@ -306,7 +306,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000xx0xx11xxxxx10xxxxxxxxxx mov. */ - return 2500; + return 2512; } } } @@ -320,7 +320,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000xx0xx10xxxxx01xxxxxxxxxx mov. */ - return 2507; + return 2519; } else { @@ -328,7 +328,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000xx0xx11xxxxx01xxxxxxxxxx mov. */ - return 2503; + return 2515; } } else @@ -339,7 +339,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000xx0xx10xxxxx11xxxxxxxxxx mov. */ - return 2505; + return 2517; } else { @@ -347,7 +347,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000xx0xx11xxxxx11xxxxxxxxxx mov. */ - return 2501; + return 2513; } } } @@ -374,7 +374,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx000xxxxxxxxxxxx0 ld1b. */ - return 2433; + return 2445; } else { @@ -382,7 +382,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx100xxxxxxxxxxxx0 ld1b. */ - return 2434; + return 2446; } } else @@ -393,7 +393,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx010xxxxxxxxxxxx0 ld1w. */ - return 2457; + return 2469; } else { @@ -401,7 +401,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx110xxxxxxxxxxxx0 ld1w. */ - return 2458; + return 2470; } } } @@ -415,7 +415,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx001xxxxxxxxxxxx0 ld1h. */ - return 2449; + return 2461; } else { @@ -423,7 +423,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx101xxxxxxxxxxxx0 ld1h. */ - return 2450; + return 2462; } } else @@ -434,7 +434,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx011xxxxxxxxxxxx0 ld1d. */ - return 2441; + return 2453; } else { @@ -442,7 +442,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx111xxxxxxxxxxxx0 ld1d. */ - return 2442; + return 2454; } } } @@ -459,7 +459,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx000xxxxxxxxxxxx1 ldnt1b. */ - return 2465; + return 2477; } else { @@ -467,7 +467,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx100xxxxxxxxxxxx1 ldnt1b. */ - return 2466; + return 2478; } } else @@ -478,7 +478,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx010xxxxxxxxxxxx1 ldnt1w. */ - return 2489; + return 2501; } else { @@ -486,7 +486,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx110xxxxxxxxxxxx1 ldnt1w. */ - return 2490; + return 2502; } } } @@ -500,7 +500,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx001xxxxxxxxxxxx1 ldnt1h. */ - return 2481; + return 2493; } else { @@ -508,7 +508,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx101xxxxxxxxxxxx1 ldnt1h. */ - return 2482; + return 2494; } } else @@ -519,7 +519,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx011xxxxxxxxxxxx1 ldnt1d. */ - return 2473; + return 2485; } else { @@ -527,7 +527,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx111xxxxxxxxxxxx1 ldnt1d. */ - return 2474; + return 2486; } } } @@ -591,7 +591,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx000xxxxxxxxxxxx0 ld1b. */ - return 2429; + return 2441; } else { @@ -599,7 +599,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx100xxxxxxxxxxxx0 ld1b. */ - return 2430; + return 2442; } } else @@ -610,7 +610,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx010xxxxxxxxxxxx0 ld1w. */ - return 2453; + return 2465; } else { @@ -618,7 +618,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx110xxxxxxxxxxxx0 ld1w. */ - return 2454; + return 2466; } } } @@ -632,7 +632,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx001xxxxxxxxxxxx0 ld1h. */ - return 2445; + return 2457; } else { @@ -640,7 +640,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx101xxxxxxxxxxxx0 ld1h. */ - return 2446; + return 2458; } } else @@ -651,7 +651,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx011xxxxxxxxxxxx0 ld1d. */ - return 2437; + return 2449; } else { @@ -659,7 +659,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx111xxxxxxxxxxxx0 ld1d. */ - return 2438; + return 2450; } } } @@ -676,7 +676,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx000xxxxxxxxxxxx1 ldnt1b. */ - return 2461; + return 2473; } else { @@ -684,7 +684,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx100xxxxxxxxxxxx1 ldnt1b. */ - return 2462; + return 2474; } } else @@ -695,7 +695,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx010xxxxxxxxxxxx1 ldnt1w. */ - return 2485; + return 2497; } else { @@ -703,7 +703,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx110xxxxxxxxxxxx1 ldnt1w. */ - return 2486; + return 2498; } } } @@ -717,7 +717,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx001xxxxxxxxxxxx1 ldnt1h. */ - return 2477; + return 2489; } else { @@ -725,7 +725,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx101xxxxxxxxxxxx1 ldnt1h. */ - return 2478; + return 2490; } } else @@ -736,7 +736,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx011xxxxxxxxxxxx1 ldnt1d. */ - return 2469; + return 2481; } else { @@ -744,7 +744,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx111xxxxxxxxxxxx1 ldnt1d. */ - return 2470; + return 2482; } } } @@ -812,7 +812,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx000xxxxxxxxxxxx0 st1b. */ - return 2527; + return 2539; } else { @@ -820,7 +820,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx100xxxxxxxxxxxx0 st1b. */ - return 2528; + return 2540; } } else @@ -831,7 +831,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx010xxxxxxxxxxxx0 st1w. */ - return 2551; + return 2563; } else { @@ -839,7 +839,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx110xxxxxxxxxxxx0 st1w. */ - return 2552; + return 2564; } } } @@ -853,7 +853,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx001xxxxxxxxxxxx0 st1h. */ - return 2543; + return 2555; } else { @@ -861,7 +861,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx101xxxxxxxxxxxx0 st1h. */ - return 2544; + return 2556; } } else @@ -872,7 +872,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx011xxxxxxxxxxxx0 st1d. */ - return 2535; + return 2547; } else { @@ -880,7 +880,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx111xxxxxxxxxxxx0 st1d. */ - return 2536; + return 2548; } } } @@ -897,7 +897,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx000xxxxxxxxxxxx1 stnt1b. */ - return 2559; + return 2571; } else { @@ -905,7 +905,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx100xxxxxxxxxxxx1 stnt1b. */ - return 2560; + return 2572; } } else @@ -916,7 +916,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx010xxxxxxxxxxxx1 stnt1w. */ - return 2583; + return 2595; } else { @@ -924,7 +924,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx110xxxxxxxxxxxx1 stnt1w. */ - return 2584; + return 2596; } } } @@ -938,7 +938,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx001xxxxxxxxxxxx1 stnt1h. */ - return 2575; + return 2587; } else { @@ -946,7 +946,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx101xxxxxxxxxxxx1 stnt1h. */ - return 2576; + return 2588; } } else @@ -957,7 +957,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx011xxxxxxxxxxxx1 stnt1d. */ - return 2567; + return 2579; } else { @@ -965,7 +965,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx111xxxxxxxxxxxx1 stnt1d. */ - return 2568; + return 2580; } } } @@ -1029,7 +1029,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx000xxxxxxxxxxxx0 st1b. */ - return 2523; + return 2535; } else { @@ -1037,7 +1037,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx100xxxxxxxxxxxx0 st1b. */ - return 2524; + return 2536; } } else @@ -1048,7 +1048,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx010xxxxxxxxxxxx0 st1w. */ - return 2547; + return 2559; } else { @@ -1056,7 +1056,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx110xxxxxxxxxxxx0 st1w. */ - return 2548; + return 2560; } } } @@ -1070,7 +1070,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx001xxxxxxxxxxxx0 st1h. */ - return 2539; + return 2551; } else { @@ -1078,7 +1078,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx101xxxxxxxxxxxx0 st1h. */ - return 2540; + return 2552; } } else @@ -1089,7 +1089,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx011xxxxxxxxxxxx0 st1d. */ - return 2531; + return 2543; } else { @@ -1097,7 +1097,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx111xxxxxxxxxxxx0 st1d. */ - return 2532; + return 2544; } } } @@ -1114,7 +1114,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx000xxxxxxxxxxxx1 stnt1b. */ - return 2555; + return 2567; } else { @@ -1122,7 +1122,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx100xxxxxxxxxxxx1 stnt1b. */ - return 2556; + return 2568; } } else @@ -1133,7 +1133,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx010xxxxxxxxxxxx1 stnt1w. */ - return 2579; + return 2591; } else { @@ -1141,7 +1141,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx110xxxxxxxxxxxx1 stnt1w. */ - return 2580; + return 2592; } } } @@ -1155,7 +1155,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx001xxxxxxxxxxxx1 stnt1h. */ - return 2571; + return 2583; } else { @@ -1163,7 +1163,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx101xxxxxxxxxxxx1 stnt1h. */ - return 2572; + return 2584; } } else @@ -1174,7 +1174,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx011xxxxxxxxxxxx1 stnt1d. */ - return 2563; + return 2575; } else { @@ -1182,7 +1182,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx111xxxxxxxxxxxx1 stnt1d. */ - return 2564; + return 2576; } } } @@ -1274,7 +1274,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00001000xxxxx000xxxxxxxxx0xxx ld1b. */ - return 2435; + return 2447; } else { @@ -1282,7 +1282,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00001000xxxxx010xxxxxxxxx0xxx ld1w. */ - return 2459; + return 2471; } } else @@ -1293,7 +1293,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00001000xxxxx001xxxxxxxxx0xxx ld1h. */ - return 2451; + return 2463; } else { @@ -1301,7 +1301,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00001000xxxxx011xxxxxxxxx0xxx ld1d. */ - return 2443; + return 2455; } } } @@ -1315,7 +1315,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00001000xxxxx000xxxxxxxxx1xxx ldnt1b. */ - return 2467; + return 2479; } else { @@ -1323,7 +1323,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00001000xxxxx010xxxxxxxxx1xxx ldnt1w. */ - return 2491; + return 2503; } } else @@ -1334,7 +1334,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00001000xxxxx001xxxxxxxxx1xxx ldnt1h. */ - return 2483; + return 2495; } else { @@ -1342,7 +1342,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00001000xxxxx011xxxxxxxxx1xxx ldnt1d. */ - return 2475; + return 2487; } } } @@ -1370,7 +1370,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00001000xxxxx100xxxxxxxxx0xxx ld1b. */ - return 2436; + return 2448; } else { @@ -1378,7 +1378,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1x00001000xxxxx100xxxxxxxxx0xxx ldr. */ - return 2493; + return 2505; } } else @@ -1387,7 +1387,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001000xxxxx110xxxxxxxxx0xxx ld1w. */ - return 2460; + return 2472; } } else @@ -1398,7 +1398,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001000xxxxx101xxxxxxxxx0xxx ld1h. */ - return 2452; + return 2464; } else { @@ -1406,7 +1406,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001000xxxxx111xxxxxxxxx0xxx ld1d. */ - return 2444; + return 2456; } } } @@ -1420,7 +1420,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001000xxxxx100xxxxxxxxx1xxx ldnt1b. */ - return 2468; + return 2480; } else { @@ -1428,7 +1428,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001000xxxxx110xxxxxxxxx1xxx ldnt1w. */ - return 2492; + return 2504; } } else @@ -1439,7 +1439,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001000xxxxx101xxxxxxxxx1xxx ldnt1h. */ - return 2484; + return 2496; } else { @@ -1447,7 +1447,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001000xxxxx111xxxxxxxxx1xxx ldnt1d. */ - return 2476; + return 2488; } } } @@ -1511,7 +1511,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001010xxxxx000xxxxxxxxx0xxx ld1b. */ - return 2431; + return 2443; } else { @@ -1519,7 +1519,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001010xxxxx100xxxxxxxxx0xxx ld1b. */ - return 2432; + return 2444; } } else @@ -1530,7 +1530,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001010xxxxx010xxxxxxxxx0xxx ld1w. */ - return 2455; + return 2467; } else { @@ -1538,7 +1538,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001010xxxxx110xxxxxxxxx0xxx ld1w. */ - return 2456; + return 2468; } } } @@ -1552,7 +1552,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001010xxxxx001xxxxxxxxx0xxx ld1h. */ - return 2447; + return 2459; } else { @@ -1560,7 +1560,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001010xxxxx101xxxxxxxxx0xxx ld1h. */ - return 2448; + return 2460; } } else @@ -1571,7 +1571,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001010xxxxx011xxxxxxxxx0xxx ld1d. */ - return 2439; + return 2451; } else { @@ -1579,7 +1579,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001010xxxxx111xxxxxxxxx0xxx ld1d. */ - return 2440; + return 2452; } } } @@ -1596,7 +1596,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001010xxxxx000xxxxxxxxx1xxx ldnt1b. */ - return 2463; + return 2475; } else { @@ -1604,7 +1604,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001010xxxxx100xxxxxxxxx1xxx ldnt1b. */ - return 2464; + return 2476; } } else @@ -1615,7 +1615,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001010xxxxx010xxxxxxxxx1xxx ldnt1w. */ - return 2487; + return 2499; } else { @@ -1623,7 +1623,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001010xxxxx110xxxxxxxxx1xxx ldnt1w. */ - return 2488; + return 2500; } } } @@ -1637,7 +1637,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001010xxxxx001xxxxxxxxx1xxx ldnt1h. */ - return 2479; + return 2491; } else { @@ -1645,7 +1645,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001010xxxxx101xxxxxxxxx1xxx ldnt1h. */ - return 2480; + return 2492; } } else @@ -1656,7 +1656,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001010xxxxx011xxxxxxxxx1xxx ldnt1d. */ - return 2471; + return 2483; } else { @@ -1664,7 +1664,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001010xxxxx111xxxxxxxxx1xxx ldnt1d. */ - return 2472; + return 2484; } } } @@ -1727,21 +1727,219 @@ aarch64_opcode_lookup_1 (uint32_t word) } else { - if (((word >> 16) & 0x1) == 0) + if (((word >> 15) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx1xxxx0xxxxxxxxxxxxxxxx - sel. */ - return 2521; + if (((word >> 3) & 0x1) == 0) + { + if (((word >> 4) & 0x1) == 0) + { + if (((word >> 16) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xxxx00xxxxxxxxxx00xxx + fadd. */ + return 2437; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xxxx10xxxxxxxxxx00xxx + fadd. */ + return 2438; + } + } + else + { + if (((word >> 10) & 0x1) == 0) + { + if (((word >> 23) & 0x1) == 0) + { + if (((word >> 20) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000010x10xxxx0xxxx0xxxxx10xxx + add. */ + return 2430; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000010x11xxxx0xxxx0xxxxx10xxx + add. */ + return 2431; + } + } + else + { + if (((word >> 16) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000011x1xxxx00xxxx0xxxxx10xxx + add. */ + return 2432; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000011x1xxxx10xxxx0xxxxx10xxx + add. */ + return 2433; + } + } + } + else + { + if (((word >> 16) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xxxx00xxxx1xxxxx10xxx + add. */ + return 2428; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xxxx10xxxx1xxxxx10xxx + add. */ + return 2429; + } + } + } + } + else + { + if (((word >> 4) & 0x1) == 0) + { + if (((word >> 16) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xxxx00xxxxxxxxxx01xxx + fsub. */ + return 2439; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xxxx10xxxxxxxxxx01xxx + fsub. */ + return 2440; + } + } + else + { + if (((word >> 10) & 0x1) == 0) + { + if (((word >> 23) & 0x1) == 0) + { + if (((word >> 20) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000010x10xxxx0xxxx0xxxxx11xxx + sub. */ + return 2602; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000010x11xxxx0xxxx0xxxxx11xxx + sub. */ + return 2603; + } + } + else + { + if (((word >> 16) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000011x1xxxx00xxxx0xxxxx11xxx + sub. */ + return 2604; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000011x1xxxx10xxxx0xxxxx11xxx + sub. */ + return 2605; + } + } + } + else + { + if (((word >> 16) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xxxx00xxxx1xxxxx11xxx + sub. */ + return 2600; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xxxx10xxxx1xxxxx11xxx + sub. */ + return 2601; + } + } + } + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx1xxxx1xxxxxxxxxxxxxxxx - sel. */ - return 2522; + if (((word >> 13) & 0x1) == 0) + { + if (((word >> 16) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xxxx01x0xxxxxxxxxxxxx + sel. */ + return 2533; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xxxx11x0xxxxxxxxxxxxx + sel. */ + return 2534; + } + } + else + { + if (((word >> 11) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xxxxx1x1x0xxxxxxxxxxx + add. */ + return 2434; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xxxxx1x1x1xxxxxxxxxxx + add. */ + return 2435; + } + } } } } @@ -1765,7 +1963,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx000xxxxxxxxx0xxx st1b. */ - return 2529; + return 2541; } else { @@ -1773,7 +1971,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx010xxxxxxxxx0xxx st1w. */ - return 2553; + return 2565; } } else @@ -1784,7 +1982,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx001xxxxxxxxx0xxx st1h. */ - return 2545; + return 2557; } else { @@ -1792,7 +1990,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx011xxxxxxxxx0xxx st1d. */ - return 2537; + return 2549; } } } @@ -1806,7 +2004,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx000xxxxxxxxx1xxx stnt1b. */ - return 2561; + return 2573; } else { @@ -1814,7 +2012,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx010xxxxxxxxx1xxx stnt1w. */ - return 2585; + return 2597; } } else @@ -1825,7 +2023,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx001xxxxxxxxx1xxx stnt1h. */ - return 2577; + return 2589; } else { @@ -1833,7 +2031,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx011xxxxxxxxx1xxx stnt1d. */ - return 2569; + return 2581; } } } @@ -1861,7 +2059,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx100xxxxxxxxx0xxx st1b. */ - return 2530; + return 2542; } else { @@ -1869,7 +2067,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1100001001xxxxx100xxxxxxxxx0xxx str. */ - return 2587; + return 2599; } } else @@ -1878,7 +2076,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001001xxxxx110xxxxxxxxx0xxx st1w. */ - return 2554; + return 2566; } } else @@ -1889,7 +2087,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001001xxxxx101xxxxxxxxx0xxx st1h. */ - return 2546; + return 2558; } else { @@ -1897,7 +2095,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001001xxxxx111xxxxxxxxx0xxx st1d. */ - return 2538; + return 2550; } } } @@ -1911,7 +2109,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001001xxxxx100xxxxxxxxx1xxx stnt1b. */ - return 2562; + return 2574; } else { @@ -1919,7 +2117,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001001xxxxx110xxxxxxxxx1xxx stnt1w. */ - return 2586; + return 2598; } } else @@ -1930,7 +2128,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001001xxxxx101xxxxxxxxx1xxx stnt1h. */ - return 2578; + return 2590; } else { @@ -1938,7 +2136,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001001xxxxx111xxxxxxxxx1xxx stnt1d. */ - return 2570; + return 2582; } } } @@ -1980,7 +2178,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx000xxxxxxxxx0xxx st1b. */ - return 2525; + return 2537; } else { @@ -1988,7 +2186,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx100xxxxxxxxx0xxx st1b. */ - return 2526; + return 2538; } } else @@ -1999,7 +2197,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx010xxxxxxxxx0xxx st1w. */ - return 2549; + return 2561; } else { @@ -2007,7 +2205,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx110xxxxxxxxx0xxx st1w. */ - return 2550; + return 2562; } } } @@ -2021,7 +2219,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx001xxxxxxxxx0xxx st1h. */ - return 2541; + return 2553; } else { @@ -2029,7 +2227,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx101xxxxxxxxx0xxx st1h. */ - return 2542; + return 2554; } } else @@ -2040,7 +2238,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx011xxxxxxxxx0xxx st1d. */ - return 2533; + return 2545; } else { @@ -2048,7 +2246,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx111xxxxxxxxx0xxx st1d. */ - return 2534; + return 2546; } } } @@ -2065,7 +2263,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx000xxxxxxxxx1xxx stnt1b. */ - return 2557; + return 2569; } else { @@ -2073,7 +2271,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx100xxxxxxxxx1xxx stnt1b. */ - return 2558; + return 2570; } } else @@ -2084,7 +2282,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx010xxxxxxxxx1xxx stnt1w. */ - return 2581; + return 2593; } else { @@ -2092,7 +2290,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx110xxxxxxxxx1xxx stnt1w. */ - return 2582; + return 2594; } } } @@ -2106,7 +2304,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx001xxxxxxxxx1xxx stnt1h. */ - return 2573; + return 2585; } else { @@ -2114,7 +2312,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx101xxxxxxxxx1xxx stnt1h. */ - return 2574; + return 2586; } } else @@ -2125,7 +2323,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx011xxxxxxxxx1xxx stnt1d. */ - return 2565; + return 2577; } else { @@ -2133,7 +2331,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx111xxxxxxxxx1xxx stnt1d. */ - return 2566; + return 2578; } } } @@ -4535,7 +4733,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 00011001000xxxxxxxxx00xxxxxxxxxx stlurb. */ - return 2637; + return 2655; } else { @@ -4543,7 +4741,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 10011001000xxxxxxxxx00xxxxxxxxxx stlur. */ - return 2645; + return 2663; } } else @@ -4554,7 +4752,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 01011001000xxxxxxxxx00xxxxxxxxxx stlurh. */ - return 2641; + return 2659; } else { @@ -4562,7 +4760,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 11011001000xxxxxxxxx00xxxxxxxxxx stlur. */ - return 2648; + return 2666; } } } @@ -4600,7 +4798,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0000x1xxxxxxxxxx cpyfp. */ - return 2697; + return 2715; } else { @@ -4608,7 +4806,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1000x1xxxxxxxxxx cpyfprn. */ - return 2703; + return 2721; } } else @@ -4619,7 +4817,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0100x1xxxxxxxxxx cpyfpwn. */ - return 2700; + return 2718; } else { @@ -4627,7 +4825,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1100x1xxxxxxxxxx cpyfpn. */ - return 2706; + return 2724; } } } @@ -4641,7 +4839,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0010x1xxxxxxxxxx cpyfprt. */ - return 2721; + return 2739; } else { @@ -4649,7 +4847,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1010x1xxxxxxxxxx cpyfprtrn. */ - return 2727; + return 2745; } } else @@ -4660,7 +4858,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0110x1xxxxxxxxxx cpyfprtwn. */ - return 2724; + return 2742; } else { @@ -4668,7 +4866,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1110x1xxxxxxxxxx cpyfprtn. */ - return 2730; + return 2748; } } } @@ -4685,7 +4883,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0001x1xxxxxxxxxx cpyfpwt. */ - return 2709; + return 2727; } else { @@ -4693,7 +4891,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1001x1xxxxxxxxxx cpyfpwtrn. */ - return 2715; + return 2733; } } else @@ -4704,7 +4902,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0101x1xxxxxxxxxx cpyfpwtwn. */ - return 2712; + return 2730; } else { @@ -4712,7 +4910,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1101x1xxxxxxxxxx cpyfpwtn. */ - return 2718; + return 2736; } } } @@ -4726,7 +4924,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0011x1xxxxxxxxxx cpyfpt. */ - return 2733; + return 2751; } else { @@ -4734,7 +4932,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1011x1xxxxxxxxxx cpyfptrn. */ - return 2739; + return 2757; } } else @@ -4745,7 +4943,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0111x1xxxxxxxxxx cpyfptwn. */ - return 2736; + return 2754; } else { @@ -4753,7 +4951,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1111x1xxxxxxxxxx cpyfptn. */ - return 2742; + return 2760; } } } @@ -4818,7 +5016,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 00011001010xxxxxxxxx00xxxxxxxxxx ldapurb. */ - return 2638; + return 2656; } else { @@ -4826,7 +5024,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 10011001010xxxxxxxxx00xxxxxxxxxx ldapur. */ - return 2646; + return 2664; } } else @@ -4837,7 +5035,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 01011001010xxxxxxxxx00xxxxxxxxxx ldapurh. */ - return 2642; + return 2660; } else { @@ -4845,7 +5043,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 11011001010xxxxxxxxx00xxxxxxxxxx ldapur. */ - return 2649; + return 2667; } } } @@ -4883,7 +5081,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0000x1xxxxxxxxxx cpyfm. */ - return 2698; + return 2716; } else { @@ -4891,7 +5089,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1000x1xxxxxxxxxx cpyfmrn. */ - return 2704; + return 2722; } } else @@ -4902,7 +5100,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0100x1xxxxxxxxxx cpyfmwn. */ - return 2701; + return 2719; } else { @@ -4910,7 +5108,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1100x1xxxxxxxxxx cpyfmn. */ - return 2707; + return 2725; } } } @@ -4924,7 +5122,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0010x1xxxxxxxxxx cpyfmrt. */ - return 2722; + return 2740; } else { @@ -4932,7 +5130,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1010x1xxxxxxxxxx cpyfmrtrn. */ - return 2728; + return 2746; } } else @@ -4943,7 +5141,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0110x1xxxxxxxxxx cpyfmrtwn. */ - return 2725; + return 2743; } else { @@ -4951,7 +5149,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1110x1xxxxxxxxxx cpyfmrtn. */ - return 2731; + return 2749; } } } @@ -4968,7 +5166,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0001x1xxxxxxxxxx cpyfmwt. */ - return 2710; + return 2728; } else { @@ -4976,7 +5174,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1001x1xxxxxxxxxx cpyfmwtrn. */ - return 2716; + return 2734; } } else @@ -4987,7 +5185,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0101x1xxxxxxxxxx cpyfmwtwn. */ - return 2713; + return 2731; } else { @@ -4995,7 +5193,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1101x1xxxxxxxxxx cpyfmwtn. */ - return 2719; + return 2737; } } } @@ -5009,7 +5207,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0011x1xxxxxxxxxx cpyfmt. */ - return 2734; + return 2752; } else { @@ -5017,7 +5215,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1011x1xxxxxxxxxx cpyfmtrn. */ - return 2740; + return 2758; } } else @@ -5028,7 +5226,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0111x1xxxxxxxxxx cpyfmtwn. */ - return 2737; + return 2755; } else { @@ -5036,7 +5234,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1111x1xxxxxxxxxx cpyfmtn. */ - return 2743; + return 2761; } } } @@ -5104,7 +5302,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 00011001100xxxxxxxxx00xxxxxxxxxx ldapursb. */ - return 2640; + return 2658; } else { @@ -5112,7 +5310,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 10011001100xxxxxxxxx00xxxxxxxxxx ldapursw. */ - return 2647; + return 2665; } } else @@ -5121,7 +5319,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1011001100xxxxxxxxx00xxxxxxxxxx ldapursh. */ - return 2644; + return 2662; } } else @@ -5132,7 +5330,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0011001110xxxxxxxxx00xxxxxxxxxx ldapursb. */ - return 2639; + return 2657; } else { @@ -5140,7 +5338,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1011001110xxxxxxxxx00xxxxxxxxxx ldapursh. */ - return 2643; + return 2661; } } } @@ -5202,7 +5400,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0000x1xxxxxxxxxx cpyfe. */ - return 2699; + return 2717; } else { @@ -5210,7 +5408,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0000x1xxxxxxxxxx setp. */ - return 2793; + return 2811; } } else @@ -5221,7 +5419,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx1000x1xxxxxxxxxx cpyfern. */ - return 2705; + return 2723; } else { @@ -5229,7 +5427,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx1000x1xxxxxxxxxx sete. */ - return 2795; + return 2813; } } } @@ -5243,7 +5441,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0100x1xxxxxxxxxx cpyfewn. */ - return 2702; + return 2720; } else { @@ -5251,7 +5449,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0100x1xxxxxxxxxx setm. */ - return 2794; + return 2812; } } else @@ -5260,7 +5458,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0110011x0xxxxx1100x1xxxxxxxxxx cpyfen. */ - return 2708; + return 2726; } } } @@ -5276,7 +5474,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0010x1xxxxxxxxxx cpyfert. */ - return 2723; + return 2741; } else { @@ -5284,7 +5482,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0010x1xxxxxxxxxx setpn. */ - return 2799; + return 2817; } } else @@ -5295,7 +5493,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx1010x1xxxxxxxxxx cpyfertrn. */ - return 2729; + return 2747; } else { @@ -5303,7 +5501,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx1010x1xxxxxxxxxx seten. */ - return 2801; + return 2819; } } } @@ -5317,7 +5515,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0110x1xxxxxxxxxx cpyfertwn. */ - return 2726; + return 2744; } else { @@ -5325,7 +5523,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0110x1xxxxxxxxxx setmn. */ - return 2800; + return 2818; } } else @@ -5334,7 +5532,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0110011x0xxxxx1110x1xxxxxxxxxx cpyfertn. */ - return 2732; + return 2750; } } } @@ -5353,7 +5551,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0001x1xxxxxxxxxx cpyfewt. */ - return 2711; + return 2729; } else { @@ -5361,7 +5559,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0001x1xxxxxxxxxx setpt. */ - return 2796; + return 2814; } } else @@ -5372,7 +5570,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx1001x1xxxxxxxxxx cpyfewtrn. */ - return 2717; + return 2735; } else { @@ -5380,7 +5578,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx1001x1xxxxxxxxxx setet. */ - return 2798; + return 2816; } } } @@ -5394,7 +5592,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0101x1xxxxxxxxxx cpyfewtwn. */ - return 2714; + return 2732; } else { @@ -5402,7 +5600,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0101x1xxxxxxxxxx setmt. */ - return 2797; + return 2815; } } else @@ -5411,7 +5609,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0110011x0xxxxx1101x1xxxxxxxxxx cpyfewtn. */ - return 2720; + return 2738; } } } @@ -5427,7 +5625,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0011x1xxxxxxxxxx cpyfet. */ - return 2735; + return 2753; } else { @@ -5435,7 +5633,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0011x1xxxxxxxxxx setptn. */ - return 2802; + return 2820; } } else @@ -5446,7 +5644,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx1011x1xxxxxxxxxx cpyfetrn. */ - return 2741; + return 2759; } else { @@ -5454,7 +5652,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx1011x1xxxxxxxxxx setetn. */ - return 2804; + return 2822; } } } @@ -5468,7 +5666,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0111x1xxxxxxxxxx cpyfetwn. */ - return 2738; + return 2756; } else { @@ -5476,7 +5674,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0111x1xxxxxxxxxx setmtn. */ - return 2803; + return 2821; } } else @@ -5485,7 +5683,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0110011x0xxxxx1111x1xxxxxxxxxx cpyfetn. */ - return 2744; + return 2762; } } } @@ -5858,7 +6056,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1x11010110xxxx0x01000xxxxxxxxxx abs. */ - return 2822; + return 2840; } else { @@ -5876,7 +6074,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010110xxxxxx11000xxxxxxxxxx smax. */ - return 2825; + return 2843; } } } @@ -5956,7 +6154,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010x00xxxxxx0xx10xxxxxxxxxx setf8. */ - return 2635; + return 2653; } else { @@ -5964,7 +6162,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010x00xxxxxx1xx10xxxxxxxxxx setf16. */ - return 2636; + return 2654; } } else @@ -6071,7 +6269,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010110xxxxxx11010xxxxxxxxxx smin. */ - return 2827; + return 2845; } } } @@ -6087,7 +6285,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010110xxxx0x00110xxxxxxxxxx ctz. */ - return 2824; + return 2842; } else { @@ -6132,7 +6330,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010000xxxxxxxxx01xxxxxxxxxx rmif. */ - return 2634; + return 2652; } else { @@ -6226,7 +6424,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010x10xxxxxx11001xxxxxxxxxx umax. */ - return 2826; + return 2844; } } } @@ -6356,7 +6554,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010xx0xxxxxx11011xxxxxxxxxx umin. */ - return 2828; + return 2846; } } } @@ -6372,7 +6570,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010xx0xxxx0x00111xxxxxxxxxx cnt. */ - return 2823; + return 2841; } else { @@ -7214,7 +7412,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x01x1xxxxx000110xxxxxxxxxx usdot. */ - return 2654; + return 2672; } } } @@ -7288,7 +7486,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x01x1xxxxx000111xxxxxxxxxx sudot. */ - return 2655; + return 2673; } } } @@ -9962,7 +10160,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x0xx0xxxxx011110xxxxxxxxxx usdot. */ - return 2653; + return 2671; } } } @@ -11666,7 +11864,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0100xxx10101xxxxxxxxxxxxx bfcvtnt. */ - return 2682; + return 2700; } } else @@ -11909,7 +12107,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x00x1xxxxxx00xxxxxxxxxxxxx ld1rob. */ - return 2658; + return 2676; } else { @@ -11917,7 +12115,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x01x1xxxxxx00xxxxxxxxxxxxx ld1roh. */ - return 2659; + return 2677; } } else @@ -12149,7 +12347,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0011xxxxx010xxxxxxxxxxxxx bfdot. */ - return 2679; + return 2697; } else { @@ -12170,7 +12368,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx010xx0xxxxxxxxxx bfmlalb. */ - return 2686; + return 2704; } else { @@ -12178,7 +12376,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx010xx1xxxxxxxxxx bfmlalt. */ - return 2685; + return 2703; } } else @@ -12233,7 +12431,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11001x0011xxxxx1x0xxxxxxxxxxxxx bfdot. */ - return 2678; + return 2696; } else { @@ -12245,7 +12443,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx1x0xx0xxxxxxxxxx bfmlalb. */ - return 2684; + return 2702; } else { @@ -12253,7 +12451,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx1x0xx1xxxxxxxxxx bfmlalt. */ - return 2683; + return 2701; } } else @@ -12304,7 +12502,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x00x1xxxxx001xxxxxxxxxxxxx ld1rob. */ - return 2662; + return 2680; } else { @@ -12312,7 +12510,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x01x1xxxxx001xxxxxxxxxxxxx ld1roh. */ - return 2663; + return 2681; } } else @@ -12671,7 +12869,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0101xxxxx111xxxxxxxxxxxxx fmmla. */ - return 2656; + return 2674; } else { @@ -12704,7 +12902,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0011xxxxx111xxxxxxxxxxxxx bfmmla. */ - return 2680; + return 2698; } else { @@ -12734,7 +12932,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx111xxxxxxxxxxxxx fmmla. */ - return 2657; + return 2675; } else { @@ -12863,7 +13061,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000x00xxxxxxxxxx zip1. */ - return 2666; + return 2684; } else { @@ -12873,7 +13071,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000010xxxxxxxxxx uzp1. */ - return 2668; + return 2686; } else { @@ -12881,7 +13079,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000110xxxxxxxxxx trn1. */ - return 2670; + return 2688; } } } @@ -12893,7 +13091,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000x01xxxxxxxxxx zip2. */ - return 2667; + return 2685; } else { @@ -12903,7 +13101,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000011xxxxxxxxxx uzp2. */ - return 2669; + return 2687; } else { @@ -12911,7 +13109,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000111xxxxxxxxxx trn2. */ - return 2671; + return 2689; } } } @@ -13970,7 +14168,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x1000xxxxx100110xxxxxxxxxx smmla. */ - return 2650; + return 2668; } else { @@ -13978,7 +14176,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x1100xxxxx100110xxxxxxxxxx usmmla. */ - return 2652; + return 2670; } } else @@ -13987,7 +14185,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x1x10xxxxx100110xxxxxxxxxx ummla. */ - return 2651; + return 2669; } } } @@ -15483,7 +15681,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x10x1xxxxx000xxxxxxxxxxxxx ld1row. */ - return 2660; + return 2678; } else { @@ -15491,7 +15689,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x11x1xxxxx000xxxxxxxxxxxxx ld1rod. */ - return 2661; + return 2679; } } } @@ -15865,7 +16063,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x10x1xxxxx001xxxxxxxxxxxxx ld1row. */ - return 2664; + return 2682; } else { @@ -15873,7 +16071,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x11x1xxxxx001xxxxxxxxxxxxx ld1rod. */ - return 2665; + return 2683; } } } @@ -16234,7 +16432,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x000xxxxx10xxx whilege. */ - return 2588; + return 2606; } else { @@ -16242,7 +16440,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x000xxxxx11xxx whilegt. */ - return 2589; + return 2607; } } else @@ -16272,7 +16470,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx011100xxxxx1xxxx pext. */ - return 2518; + return 2530; } } } @@ -16286,7 +16484,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x010xxxxx10xxx whilehs. */ - return 2591; + return 2609; } else { @@ -16294,7 +16492,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x010xxxxx11xxx whilehi. */ - return 2590; + return 2608; } } else @@ -16324,7 +16522,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx011110xxxxx1xxxx ptrue. */ - return 2520; + return 2532; } } } @@ -16341,7 +16539,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x001xxxxx10xxx whilelt. */ - return 2595; + return 2613; } else { @@ -16349,7 +16547,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x001xxxxx11xxx whilele. */ - return 2592; + return 2610; } } else @@ -16379,7 +16577,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx011101xxxxx1xxxx pext. */ - return 2519; + return 2531; } } } @@ -16393,7 +16591,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x011xxxxx10xxx whilelo. */ - return 2593; + return 2611; } else { @@ -16401,7 +16599,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x011xxxxx11xxx whilels. */ - return 2594; + return 2612; } } else @@ -17527,7 +17725,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x110001x10101xxxxxxxxxxxxx bfcvt. */ - return 2681; + return 2699; } } else @@ -18186,7 +18384,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx10xxxx10xxxx1xxxxxxxxx cntp. */ - return 2428; + return 2436; } } else @@ -18888,7 +19086,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1010100xxxxxxxxxxxxxxxxxxx1xxxx bc.c. */ - return 2817; + return 2835; } else { @@ -19468,7 +19666,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0000xxxxxxxxxxxx cpyp. */ - return 2745; + return 2763; } else { @@ -19476,7 +19674,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0000xxxxxxxxxxxx cpye. */ - return 2747; + return 2765; } } else @@ -19487,7 +19685,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1000xxxxxxxxxxxx cpyprn. */ - return 2751; + return 2769; } else { @@ -19495,7 +19693,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1000xxxxxxxxxxxx cpyern. */ - return 2753; + return 2771; } } } @@ -19509,7 +19707,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0100xxxxxxxxxxxx cpypwn. */ - return 2748; + return 2766; } else { @@ -19517,7 +19715,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0100xxxxxxxxxxxx cpyewn. */ - return 2750; + return 2768; } } else @@ -19528,7 +19726,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1100xxxxxxxxxxxx cpypn. */ - return 2754; + return 2772; } else { @@ -19536,7 +19734,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1100xxxxxxxxxxxx cpyen. */ - return 2756; + return 2774; } } } @@ -19553,7 +19751,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0010xxxxxxxxxxxx cpyprt. */ - return 2769; + return 2787; } else { @@ -19561,7 +19759,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0010xxxxxxxxxxxx cpyert. */ - return 2771; + return 2789; } } else @@ -19572,7 +19770,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1010xxxxxxxxxxxx cpyprtrn. */ - return 2775; + return 2793; } else { @@ -19580,7 +19778,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1010xxxxxxxxxxxx cpyertrn. */ - return 2777; + return 2795; } } } @@ -19594,7 +19792,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0110xxxxxxxxxxxx cpyprtwn. */ - return 2772; + return 2790; } else { @@ -19602,7 +19800,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0110xxxxxxxxxxxx cpyertwn. */ - return 2774; + return 2792; } } else @@ -19613,7 +19811,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1110xxxxxxxxxxxx cpyprtn. */ - return 2778; + return 2796; } else { @@ -19621,7 +19819,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1110xxxxxxxxxxxx cpyertn. */ - return 2780; + return 2798; } } } @@ -19641,7 +19839,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0001xxxxxxxxxxxx cpypwt. */ - return 2757; + return 2775; } else { @@ -19649,7 +19847,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0001xxxxxxxxxxxx cpyewt. */ - return 2759; + return 2777; } } else @@ -19660,7 +19858,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1001xxxxxxxxxxxx cpypwtrn. */ - return 2763; + return 2781; } else { @@ -19668,7 +19866,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1001xxxxxxxxxxxx cpyewtrn. */ - return 2765; + return 2783; } } } @@ -19682,7 +19880,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0101xxxxxxxxxxxx cpypwtwn. */ - return 2760; + return 2778; } else { @@ -19690,7 +19888,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0101xxxxxxxxxxxx cpyewtwn. */ - return 2762; + return 2780; } } else @@ -19701,7 +19899,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1101xxxxxxxxxxxx cpypwtn. */ - return 2766; + return 2784; } else { @@ -19709,7 +19907,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1101xxxxxxxxxxxx cpyewtn. */ - return 2768; + return 2786; } } } @@ -19726,7 +19924,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0011xxxxxxxxxxxx cpypt. */ - return 2781; + return 2799; } else { @@ -19734,7 +19932,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0011xxxxxxxxxxxx cpyet. */ - return 2783; + return 2801; } } else @@ -19745,7 +19943,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1011xxxxxxxxxxxx cpyptrn. */ - return 2787; + return 2805; } else { @@ -19753,7 +19951,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1011xxxxxxxxxxxx cpyetrn. */ - return 2789; + return 2807; } } } @@ -19767,7 +19965,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0111xxxxxxxxxxxx cpyptwn. */ - return 2784; + return 2802; } else { @@ -19775,7 +19973,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0111xxxxxxxxxxxx cpyetwn. */ - return 2786; + return 2804; } } else @@ -19786,7 +19984,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1111xxxxxxxxxxxx cpyptn. */ - return 2790; + return 2808; } else { @@ -19794,7 +19992,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1111xxxxxxxxxxxx cpyetn. */ - return 2792; + return 2810; } } } @@ -19828,7 +20026,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0000xxxxxxxxxxxx cpym. */ - return 2746; + return 2764; } else { @@ -19836,7 +20034,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0000xxxxxxxxxxxx setgp. */ - return 2805; + return 2823; } } else @@ -19847,7 +20045,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx1000xxxxxxxxxxxx cpymrn. */ - return 2752; + return 2770; } else { @@ -19855,7 +20053,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx1000xxxxxxxxxxxx setge. */ - return 2807; + return 2825; } } } @@ -19869,7 +20067,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0100xxxxxxxxxxxx cpymwn. */ - return 2749; + return 2767; } else { @@ -19877,7 +20075,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0100xxxxxxxxxxxx setgm. */ - return 2806; + return 2824; } } else @@ -19886,7 +20084,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011101x1xxxxxx1100xxxxxxxxxxxx cpymn. */ - return 2755; + return 2773; } } } @@ -19902,7 +20100,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0010xxxxxxxxxxxx cpymrt. */ - return 2770; + return 2788; } else { @@ -19910,7 +20108,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0010xxxxxxxxxxxx setgpn. */ - return 2811; + return 2829; } } else @@ -19921,7 +20119,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx1010xxxxxxxxxxxx cpymrtrn. */ - return 2776; + return 2794; } else { @@ -19929,7 +20127,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx1010xxxxxxxxxxxx setgen. */ - return 2813; + return 2831; } } } @@ -19943,7 +20141,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0110xxxxxxxxxxxx cpymrtwn. */ - return 2773; + return 2791; } else { @@ -19951,7 +20149,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0110xxxxxxxxxxxx setgmn. */ - return 2812; + return 2830; } } else @@ -19960,7 +20158,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011101x1xxxxxx1110xxxxxxxxxxxx cpymrtn. */ - return 2779; + return 2797; } } } @@ -19979,7 +20177,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0001xxxxxxxxxxxx cpymwt. */ - return 2758; + return 2776; } else { @@ -19987,7 +20185,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0001xxxxxxxxxxxx setgpt. */ - return 2808; + return 2826; } } else @@ -19998,7 +20196,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx1001xxxxxxxxxxxx cpymwtrn. */ - return 2764; + return 2782; } else { @@ -20006,7 +20204,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx1001xxxxxxxxxxxx setget. */ - return 2810; + return 2828; } } } @@ -20020,7 +20218,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0101xxxxxxxxxxxx cpymwtwn. */ - return 2761; + return 2779; } else { @@ -20028,7 +20226,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0101xxxxxxxxxxxx setgmt. */ - return 2809; + return 2827; } } else @@ -20037,7 +20235,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011101x1xxxxxx1101xxxxxxxxxxxx cpymwtn. */ - return 2767; + return 2785; } } } @@ -20053,7 +20251,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0011xxxxxxxxxxxx cpymt. */ - return 2782; + return 2800; } else { @@ -20061,7 +20259,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0011xxxxxxxxxxxx setgptn. */ - return 2814; + return 2832; } } else @@ -20072,7 +20270,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx1011xxxxxxxxxxxx cpymtrn. */ - return 2788; + return 2806; } else { @@ -20080,7 +20278,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx1011xxxxxxxxxxxx setgetn. */ - return 2816; + return 2834; } } } @@ -20094,7 +20292,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0111xxxxxxxxxxxx cpymtwn. */ - return 2785; + return 2803; } else { @@ -20102,7 +20300,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0111xxxxxxxxxxxx setgmtn. */ - return 2815; + return 2833; } } else @@ -20111,7 +20309,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011101x1xxxxxx1111xxxxxxxxxxxx cpymtn. */ - return 2791; + return 2809; } } } @@ -20278,7 +20476,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110xx0xxxxx1x1001xxxxxxxxxx smmla. */ - return 2672; + return 2690; } } } @@ -20311,7 +20509,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110xx0xxxxx1x0101xxxxxxxxxx sdot. */ - return 2598; + return 2616; } } else @@ -20385,7 +20583,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110xx0xxxxx1x1011xxxxxxxxxx usmmla. */ - return 2674; + return 2692; } } } @@ -20418,7 +20616,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110xx0xxxxx1x0111xxxxxxxxxx usdot. */ - return 2675; + return 2693; } } else @@ -20465,7 +20663,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110000xxxxxxxxxxxxxxxxxxxxx eor3. */ - return 2605; + return 2623; } else { @@ -20473,7 +20671,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110100xxxxxxxxxxxxxxxxxxxxx xar. */ - return 2607; + return 2625; } } else @@ -20484,7 +20682,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110x10xxxxx0xxxxxxxxxxxxxxx sm3ss1. */ - return 2609; + return 2627; } else { @@ -20498,7 +20696,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110010xxxxx1xxx00xxxxxxxxxx sm3tt1a. */ - return 2610; + return 2628; } else { @@ -20506,7 +20704,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110110xxxxx1xxx00xxxxxxxxxx sha512su0. */ - return 2603; + return 2621; } } else @@ -20515,7 +20713,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110x10xxxxx1xxx10xxxxxxxxxx sm3tt2a. */ - return 2612; + return 2630; } } else @@ -20528,7 +20726,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110010xxxxx1xxx01xxxxxxxxxx sm3tt1b. */ - return 2611; + return 2629; } else { @@ -20536,7 +20734,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110110xxxxx1xxx01xxxxxxxxxx sm4e. */ - return 2616; + return 2634; } } else @@ -20545,7 +20743,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110x10xxxxx1xxx11xxxxxxxxxx sm3tt2b. */ - return 2613; + return 2631; } } } @@ -20726,7 +20924,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx101110xx0xxxxx100101xxxxxxxxxx udot. */ - return 2597; + return 2615; } } else @@ -20757,7 +20955,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx101110xx0xxxxx101x01xxxxxxxxxx ummla. */ - return 2673; + return 2691; } else { @@ -20776,7 +20974,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx101110xx0xxxxx1x1011xxxxxxxxxx bfmmla. */ - return 2689; + return 2707; } else { @@ -20786,7 +20984,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx1011100x0xxxxx1x1111xxxxxxxxxx bfdot. */ - return 2687; + return 2705; } else { @@ -20796,7 +20994,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x01011101x0xxxxx1x1111xxxxxxxxxx bfmlalb. */ - return 2694; + return 2712; } else { @@ -20804,7 +21002,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11011101x0xxxxx1x1111xxxxxxxxxx bfmlalt. */ - return 2693; + return 2711; } } } @@ -21388,7 +21586,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000011101x1xxxx1011010xxxxxxxxxx bfcvtn. */ - return 2690; + return 2708; } else { @@ -21396,7 +21594,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010011101x1xxxx1011010xxxxxxxxxx bfcvtn2. */ - return 2691; + return 2709; } } } @@ -21714,7 +21912,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110xx1xxxxx0xxxxxxxxxxxxxxx bcax. */ - return 2608; + return 2626; } } else @@ -22325,7 +22523,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 11001110xx1xxxxx100000xxxxxxxxxx sha512h. */ - return 2601; + return 2619; } } } @@ -22377,7 +22575,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 11001110xx1xxxxx110000xxxxxxxxxx sm3partw1. */ - return 2614; + return 2632; } } } @@ -22620,7 +22818,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110xx1xxxxx100010xxxxxxxxxx sha512su1. */ - return 2604; + return 2622; } } else @@ -22696,7 +22894,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x0011100x1xxxxx110010xxxxxxxxxx sm4ekey. */ - return 2617; + return 2635; } } else @@ -23522,7 +23720,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110xx1xxxxx100001xxxxxxxxxx sha512h2. */ - return 2602; + return 2620; } } else @@ -23554,7 +23752,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x0011100x1xxxxx110001xxxxxxxxxx sm3partw2. */ - return 2615; + return 2633; } } else @@ -23794,7 +23992,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110xx1xxxxx100011xxxxxxxxxx rax1. */ - return 2606; + return 2624; } } else @@ -23826,7 +24024,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x01011100x1xxxxx110011xxxxxxxxxx fmlal2. */ - return 2620; + return 2638; } else { @@ -23834,7 +24032,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11011100x1xxxxx110011xxxxxxxxxx fmlal2. */ - return 2624; + return 2642; } } } @@ -23856,7 +24054,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x01011101x1xxxxx110011xxxxxxxxxx fmlsl2. */ - return 2621; + return 2639; } else { @@ -23864,7 +24062,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11011101x1xxxxx110011xxxxxxxxxx fmlsl2. */ - return 2625; + return 2643; } } } @@ -23903,7 +24101,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x00011100x1xxxxx111011xxxxxxxxxx fmlal. */ - return 2618; + return 2636; } else { @@ -23911,7 +24109,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10011100x1xxxxx111011xxxxxxxxxx fmlal. */ - return 2622; + return 2640; } } else @@ -23933,7 +24131,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x00011101x1xxxxx111011xxxxxxxxxx fmlsl. */ - return 2619; + return 2637; } else { @@ -23941,7 +24139,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10011101x1xxxxx111011xxxxxxxxxx fmlsl. */ - return 2623; + return 2641; } } else @@ -25749,7 +25947,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0001111xxxxxxxx0000x0xxxxxxxxxx fmlal. */ - return 2626; + return 2644; } else { @@ -25757,7 +25955,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1001111xxxxxxxx0000x0xxxxxxxxxx fmlal. */ - return 2630; + return 2648; } } else @@ -25779,7 +25977,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0001111xxxxxxxx0100x0xxxxxxxxxx fmlsl. */ - return 2627; + return 2645; } else { @@ -25787,7 +25985,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1001111xxxxxxxx0100x0xxxxxxxxxx fmlsl. */ - return 2631; + return 2649; } } else @@ -26293,7 +26491,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0101111xxxxxxxx1000x0xxxxxxxxxx fmlal2. */ - return 2628; + return 2646; } else { @@ -26301,7 +26499,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1101111xxxxxxxx1000x0xxxxxxxxxx fmlal2. */ - return 2632; + return 2650; } } } @@ -26323,7 +26521,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0101111xxxxxxxx1100x0xxxxxxxxxx fmlsl2. */ - return 2629; + return 2647; } else { @@ -26331,7 +26529,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1101111xxxxxxxx1100x0xxxxxxxxxx fmlsl2. */ - return 2633; + return 2651; } } } @@ -26387,7 +26585,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx001111xxxxxxxx1110x0xxxxxxxxxx sdot. */ - return 2600; + return 2618; } else { @@ -26395,7 +26593,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx101111xxxxxxxx1110x0xxxxxxxxxx udot. */ - return 2599; + return 2617; } } } @@ -26498,7 +26696,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx00111100xxxxxx1111x0xxxxxxxxxx sudot. */ - return 2677; + return 2695; } else { @@ -26506,7 +26704,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx00111110xxxxxx1111x0xxxxxxxxxx usdot. */ - return 2676; + return 2694; } } else @@ -26517,7 +26715,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx00111101xxxxxx1111x0xxxxxxxxxx bfdot. */ - return 2688; + return 2706; } else { @@ -26527,7 +26725,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x000111111xxxxxx1111x0xxxxxxxxxx bfmlalb. */ - return 2696; + return 2714; } else { @@ -26535,7 +26733,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x100111111xxxxxx1111x0xxxxxxxxxx bfmlalt. */ - return 2695; + return 2713; } } } @@ -27026,22 +27224,22 @@ aarch64_find_next_opcode (const aarch64_opcode *opcode) case 2391: return NULL; /* mova --> NULL. */ case 2388: value = 2390; break; /* mov --> mova. */ case 2390: return NULL; /* mova --> NULL. */ - case 2506: value = 2514; break; /* mov --> mova. */ - case 2514: return NULL; /* mova --> NULL. */ - case 2502: value = 2510; break; /* mov --> mova. */ - case 2510: return NULL; /* mova --> NULL. */ - case 2504: value = 2512; break; /* mov --> mova. */ - case 2512: return NULL; /* mova --> NULL. */ - case 2500: value = 2508; break; /* mov --> mova. */ - case 2508: return NULL; /* mova --> NULL. */ - case 2507: value = 2515; break; /* mov --> mova. */ - case 2515: return NULL; /* mova --> NULL. */ - case 2503: value = 2511; break; /* mov --> mova. */ - case 2511: return NULL; /* mova --> NULL. */ - case 2505: value = 2513; break; /* mov --> mova. */ - case 2513: return NULL; /* mova --> NULL. */ - case 2501: value = 2509; break; /* mov --> mova. */ - case 2509: return NULL; /* mova --> NULL. */ + case 2518: value = 2526; break; /* mov --> mova. */ + case 2526: return NULL; /* mova --> NULL. */ + case 2514: value = 2522; break; /* mov --> mova. */ + case 2522: return NULL; /* mova --> NULL. */ + case 2516: value = 2524; break; /* mov --> mova. */ + case 2524: return NULL; /* mova --> NULL. */ + case 2512: value = 2520; break; /* mov --> mova. */ + case 2520: return NULL; /* mova --> NULL. */ + case 2519: value = 2527; break; /* mov --> mova. */ + case 2527: return NULL; /* mova --> NULL. */ + case 2515: value = 2523; break; /* mov --> mova. */ + case 2523: return NULL; /* mova --> NULL. */ + case 2517: value = 2525; break; /* mov --> mova. */ + case 2525: return NULL; /* mova --> NULL. */ + case 2513: value = 2521; break; /* mov --> mova. */ + case 2521: return NULL; /* mova --> NULL. */ case 2393: value = 2398; break; /* ld1b --> ld1b. */ case 2398: return NULL; /* ld1b --> NULL. */ case 2395: value = 2400; break; /* ld1w --> ld1w. */ @@ -27063,11 +27261,11 @@ aarch64_find_next_opcode (const aarch64_opcode *opcode) case 2407: value = 2412; break; /* st1q --> st1q. */ case 2412: return NULL; /* st1q --> NULL. */ case 12: value = 19; break; /* add --> addg. */ - case 19: value = 2818; break; /* addg --> smax. */ - case 2818: value = 2819; break; /* smax --> umax. */ - case 2819: value = 2820; break; /* umax --> smin. */ - case 2820: value = 2821; break; /* smin --> umin. */ - case 2821: return NULL; /* umin --> NULL. */ + case 19: value = 2836; break; /* addg --> smax. */ + case 2836: value = 2837; break; /* smax --> umax. */ + case 2837: value = 2838; break; /* umax --> smin. */ + case 2838: value = 2839; break; /* smin --> umin. */ + case 2839: return NULL; /* umin --> NULL. */ case 16: value = 20; break; /* sub --> subg. */ case 20: return NULL; /* subg --> NULL. */ case 971: value = 975; break; /* stnp --> stp. */ @@ -27225,8 +27423,8 @@ aarch64_find_next_opcode (const aarch64_opcode *opcode) case 824: return NULL; /* fsqrt --> NULL. */ case 832: value = 833; break; /* frintz --> frintz. */ case 833: return NULL; /* frintz --> NULL. */ - case 825: value = 2692; break; /* fcvt --> bfcvt. */ - case 2692: return NULL; /* bfcvt --> NULL. */ + case 825: value = 2710; break; /* fcvt --> bfcvt. */ + case 2710: return NULL; /* bfcvt --> NULL. */ case 834: value = 835; break; /* frinta --> frinta. */ case 835: return NULL; /* frinta --> NULL. */ case 836: value = 837; break; /* frintx --> frintx. */ @@ -27733,12 +27931,13 @@ aarch64_extract_operand (const aarch64_operand *self, case 203: case 209: case 212: - case 222: + case 216: case 223: - case 230: + case 224: case 231: case 232: case 233: + case 234: return aarch64_ext_regno (self, info, code, inst, errors); case 10: return aarch64_ext_regrt_sysins (self, info, code, inst, errors); @@ -27754,7 +27953,7 @@ aarch64_extract_operand (const aarch64_operand *self, case 33: case 34: case 35: - case 256: + case 257: return aarch64_ext_reglane (self, info, code, inst, errors); case 36: return aarch64_ext_reglist (self, info, code, inst, errors); @@ -27800,13 +27999,13 @@ aarch64_extract_operand (const aarch64_operand *self, case 192: case 193: case 194: - case 236: - case 250: + case 237: case 251: - case 253: - case 255: - case 260: + case 252: + case 254: + case 256: case 261: + case 262: return aarch64_ext_imm (self, info, code, inst, errors); case 44: case 45: @@ -27877,8 +28076,8 @@ aarch64_extract_operand (const aarch64_operand *self, case 107: return aarch64_ext_prfop (self, info, code, inst, errors); case 108: - case 252: - case 254: + case 253: + case 255: return aarch64_ext_none (self, info, code, inst, errors); case 109: return aarch64_ext_hint (self, info, code, inst, errors); @@ -27969,48 +28168,48 @@ aarch64_extract_operand (const aarch64_operand *self, return aarch64_ext_sve_index (self, info, code, inst, errors); case 211: case 213: - case 229: + case 230: return aarch64_ext_sve_reglist (self, info, code, inst, errors); case 214: case 215: - case 216: case 217: case 218: case 219: - case 228: - return aarch64_ext_sve_aligned_reglist (self, info, code, inst, errors); case 220: + case 229: + return aarch64_ext_sve_aligned_reglist (self, info, code, inst, errors); case 221: + case 222: return aarch64_ext_sve_strided_reglist (self, info, code, inst, errors); - case 224: - case 226: - case 237: - return aarch64_ext_sme_za_hv_tiles (self, info, code, inst, errors); case 225: case 227: + case 238: + return aarch64_ext_sme_za_hv_tiles (self, info, code, inst, errors); + case 226: + case 228: return aarch64_ext_sme_za_hv_tiles_range (self, info, code, inst, errors); - case 234: case 235: - case 244: + case 236: case 245: case 246: case 247: case 248: case 249: + case 250: return aarch64_ext_simple_index (self, info, code, inst, errors); - case 238: case 239: case 240: - return aarch64_ext_sme_za_array (self, info, code, inst, errors); case 241: - return aarch64_ext_sme_addr_ri_u4xvl (self, info, code, inst, errors); + return aarch64_ext_sme_za_array (self, info, code, inst, errors); case 242: - return aarch64_ext_sme_sm_za (self, info, code, inst, errors); + return aarch64_ext_sme_addr_ri_u4xvl (self, info, code, inst, errors); case 243: + return aarch64_ext_sme_sm_za (self, info, code, inst, errors); + case 244: return aarch64_ext_sme_pred_reg_with_index (self, info, code, inst, errors); - case 257: case 258: case 259: + case 260: return aarch64_ext_x0_to_x30 (self, info, code, inst, errors); default: assert (0); abort (); } diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c index 0475adbc31d..1148f2e952a 100644 --- a/opcodes/aarch64-dis.c +++ b/opcodes/aarch64-dis.c @@ -3169,6 +3169,8 @@ aarch64_decode_variant_using_iclass (aarch64_inst *inst) variant = i - 1; break; + case sme_fp_sd: + case sme_int_sd: case sve_size_bh: case sve_size_sd: variant = extract_field (FLD_SVE_sz, inst->value, 0); diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c index 21e06e6114f..8658d07bf39 100644 --- a/opcodes/aarch64-opc-2.c +++ b/opcodes/aarch64-opc-2.c @@ -240,6 +240,7 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_SVE_REGLIST, "SVE_ZtxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "a list of SVE vector registers"}, {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zdnx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zdn2}, "a list of SVE vector registers"}, {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zdnx4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zdn4}, "a list of SVE vector registers"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm}, "an SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zmx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm2}, "a list of SVE vector registers"}, {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zmx4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm4}, "a list of SVE vector registers"}, {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Znx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zn2}, "a list of SVE vector registers"}, diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index cd185b8af29..d9cc0544e82 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -241,6 +241,7 @@ const aarch64_field fields[] = { 0, 3 }, /* SME_ZAda_3b: tile ZA0-ZA7. */ { 1, 4 }, /* SME_Zdn2: Z0-Z31, multiple of 2, bits [4:1]. */ { 2, 3 }, /* SME_Zdn4: Z0-Z31, multiple of 4, bits [4:2]. */ + { 16, 4 }, /* SME_Zm: Z0-Z15, bits [19:16]. */ { 17, 4 }, /* SME_Zm2: Z0-Z31, multiple of 2, bits [20:17]. */ { 18, 3 }, /* SME_Zm4: Z0-Z31, multiple of 4, bits [20:18]. */ { 6, 4 }, /* SME_Zn2: Z0-Z31, multiple of 2, bits [9:6]. */ @@ -1764,6 +1765,14 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, return 0; break; + case AARCH64_OPND_SME_Zm: + if (opnd->reg.regno > 15) + { + set_invalid_regno_error (mismatch_detail, idx, "z", 0, 15); + return 0; + } + break; + case AARCH64_OPND_SME_PnT_Wm_imm: size = aarch64_get_qualifier_esize (opnd->qualifier); max_value = 16 / size - 1; @@ -3101,23 +3110,38 @@ aarch64_match_operands_constraint (aarch64_inst *inst, break; default: - /* Check for cases where a source register needs to be the same as the - destination register. Do this before matching qualifiers since if - an instruction has both invalid tying and invalid qualifiers, - the error about qualifiers would suggest several alternative - instructions that also have invalid tying. */ - if (inst->operands[0].reg.regno - != inst->operands[i].reg.regno) - { - if (mismatch_detail) - { - mismatch_detail->kind = AARCH64_OPDE_UNTIED_OPERAND; - mismatch_detail->index = i; - mismatch_detail->error = NULL; - } - return 0; - } - break; + { + /* Check for cases where a source register needs to be the + same as the destination register. Do this before + matching qualifiers since if an instruction has both + invalid tying and invalid qualifiers, the error about + qualifiers would suggest several alternative instructions + that also have invalid tying. */ + enum aarch64_operand_class op_class1 + = aarch64_get_operand_class (inst->operands[0].type); + enum aarch64_operand_class op_class2 + = aarch64_get_operand_class (inst->operands[i].type); + assert (op_class1 == op_class2); + if (op_class1 == AARCH64_OPND_CLASS_SVE_REGLIST + ? ((inst->operands[0].reglist.first_regno + != inst->operands[i].reglist.first_regno) + || (inst->operands[0].reglist.num_regs + != inst->operands[i].reglist.num_regs) + || (inst->operands[0].reglist.stride + != inst->operands[i].reglist.stride)) + : (inst->operands[0].reg.regno + != inst->operands[i].reg.regno)) + { + if (mismatch_detail) + { + mismatch_detail->kind = AARCH64_OPDE_UNTIED_OPERAND; + mismatch_detail->index = i; + mismatch_detail->error = NULL; + } + return 0; + } + break; + } } } @@ -3874,6 +3898,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, case AARCH64_OPND_SVE_Zm_16: case AARCH64_OPND_SVE_Zn: case AARCH64_OPND_SVE_Zt: + case AARCH64_OPND_SME_Zm: if (opnd->qualifier == AARCH64_OPND_QLF_NIL) snprintf (buf, size, "%s", style_reg (styler, "z%d", opnd->reg.regno)); else @@ -6501,6 +6526,18 @@ aarch64_cpu_supports_inst_p (uint64_t cpu_variant, aarch64_inst *inst) || !AARCH64_CPU_HAS_ALL_FEATURES (cpu_variant, *inst->opcode->avariant)) return false; + if (inst->opcode->iclass == sme_fp_sd + && inst->operands[0].qualifier == AARCH64_OPND_QLF_S_D + && !AARCH64_CPU_HAS_ALL_FEATURES (cpu_variant, + AARCH64_FEATURE_SME_F64F64)) + return false; + + if (inst->opcode->iclass == sme_int_sd + && inst->operands[0].qualifier == AARCH64_OPND_QLF_S_D + && !AARCH64_CPU_HAS_ALL_FEATURES (cpu_variant, + AARCH64_FEATURE_SME_I16I64)) + return false; + return true; } diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h index 8422be4c9db..1284dd47d4d 100644 --- a/opcodes/aarch64-opc.h +++ b/opcodes/aarch64-opc.h @@ -62,6 +62,7 @@ enum aarch64_field_kind FLD_SME_ZAda_3b, FLD_SME_Zdn2, FLD_SME_Zdn4, + FLD_SME_Zm, FLD_SME_Zm2, FLD_SME_Zm4, FLD_SME_Zn2, diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 0f881681aab..b97e375c1f0 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -5325,7 +5325,19 @@ const struct aarch64_opcode aarch64_opcode_table[] = SME2_INSN ("whilelt", 0x25205410, 0xff20fc11, sme_size_22, 0, OP3 (SME_Pdx2, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0), /* SME2 extensions to SME. */ + SME2_INSN ("add", 0xc1a01c10, 0xffbf9c38, sme_int_sd, 0, OP2 (SME_ZA_array_off3_0, SME_Znx2), OP_SVE_VVV_SD, F_OD (2), 0), + SME2_INSN ("add", 0xc1a11c10, 0xffbf9c78, sme_int_sd, 0, OP2 (SME_ZA_array_off3_0, SME_Znx4), OP_SVE_VVV_SD, F_OD (4), 0), + SME2_INSN ("add", 0xc1201810, 0xffb09c18, sme_int_sd, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_VVV_SD, F_OD (2), 0), + SME2_INSN ("add", 0xc1301810, 0xffb09c18, sme_int_sd, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_VVV_SD, F_OD (4), 0), + SME2_INSN ("add", 0xc1a01810, 0xffa19c38, sme_int_sd, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zmx2), OP_SVE_VVV_SD, F_OD (2), 0), + SME2_INSN ("add", 0xc1a11810, 0xffa39c78, sme_int_sd, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zmx4), OP_SVE_VVV_SD, F_OD (4), 0), + SME2_INSN ("add", 0xc120a300, 0xff30ffe1, sme_size_22, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zm), OP_SVE_VVV_BHSD, 0, 1), + SME2_INSN ("add", 0xc120ab00, 0xff30ffe3, sme_size_22, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zm), OP_SVE_VVV_BHSD, 0, 1), SME2_INSN ("cntp", 0x25208200, 0xff3ffa00, sme_size_22, 0, OP3 (Rd, SME_PNn, SME_VLxN_10), OP_SVE_XV_BHSD, 0, 0), + SME2_INSN ("fadd", 0xc1a01c00, 0xffbf9c38, sme_fp_sd, 0, OP2 (SME_ZA_array_off3_0, SME_Znx2), OP_SVE_VVV_SD, F_OD (2), 0), + SME2_INSN ("fadd", 0xc1a11c00, 0xffbf9c78, sme_fp_sd, 0, OP2 (SME_ZA_array_off3_0, SME_Znx4), OP_SVE_VVV_SD, F_OD (4), 0), + SME2_INSN ("fsub", 0xc1a01c08, 0xffbf9c38, sme_fp_sd, 0, OP2 (SME_ZA_array_off3_0, SME_Znx2), OP_SVE_VVV_SD, F_OD (2), 0), + SME2_INSN ("fsub", 0xc1a11c08, 0xffbf9c78, sme_fp_sd, 0, OP2 (SME_ZA_array_off3_0, SME_Znx4), OP_SVE_VVV_SD, F_OD (4), 0), SME2_INSN ("ld1b", 0xa0400000, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_BZU, 0, 0), SME2_INSN ("ld1b", 0xa0408000, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_BZU, 0, 0), SME2_INSN ("ld1b", 0xa1400000, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_BZU, 0, 0), @@ -5485,6 +5497,12 @@ const struct aarch64_opcode aarch64_opcode_table[] = SME2_INSN ("stnt1w", 0xa1204008, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SUU, 0, 0), SME2_INSN ("stnt1w", 0xa120c008, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SUU, 0, 0), SME2_INSN ("str", 0xe13f8000, 0xfffffc1f, sme_misc, 0, OP2 (SME_ZT0, SIMD_ADDR_SIMPLE), {}, 0, 0), + SME2_INSN ("sub", 0xc1a01c18, 0xffbf9c38, sme_int_sd, 0, OP2 (SME_ZA_array_off3_0, SME_Znx2), OP_SVE_VVV_SD, F_OD (2), 0), + SME2_INSN ("sub", 0xc1a11c18, 0xffbf9c78, sme_int_sd, 0, OP2 (SME_ZA_array_off3_0, SME_Znx4), OP_SVE_VVV_SD, F_OD (4), 0), + SME2_INSN ("sub", 0xc1201818, 0xffb09c18, sme_int_sd, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_VVV_SD, F_OD (2), 0), + SME2_INSN ("sub", 0xc1301818, 0xffb09c18, sme_int_sd, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_VVV_SD, F_OD (4), 0), + SME2_INSN ("sub", 0xc1a01818, 0xffa19c38, sme_int_sd, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zmx2), OP_SVE_VVV_SD, F_OD (2), 0), + SME2_INSN ("sub", 0xc1a11818, 0xffa39c78, sme_int_sd, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zmx4), OP_SVE_VVV_SD, F_OD (4), 0), SME2_INSN ("whilege", 0x25204010, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0), SME2_INSN ("whilegt", 0x25204018, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0), SME2_INSN ("whilehi", 0x25204818, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0), @@ -6138,6 +6156,8 @@ const struct aarch64_opcode aarch64_opcode_table[] = F(FLD_SME_Zdn2), "a list of SVE vector registers") \ Y(SVE_REGLIST, sve_aligned_reglist, "SME_Zdnx4", 4 << OPD_F_OD_LSB, \ F(FLD_SME_Zdn4), "a list of SVE vector registers") \ + Y(SVE_REG, regno, "SME_Zm", 0, F(FLD_SME_Zm), \ + "an SVE vector register") \ Y(SVE_REGLIST, sve_aligned_reglist, "SME_Zmx2", 2 << OPD_F_OD_LSB, \ F(FLD_SME_Zm2), "a list of SVE vector registers") \ Y(SVE_REGLIST, sve_aligned_reglist, "SME_Zmx4", 4 << OPD_F_OD_LSB, \ From patchwork Thu Mar 30 10:26:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 77087 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1037760vqo; Thu, 30 Mar 2023 04:01:29 -0700 (PDT) X-Google-Smtp-Source: AKy350b0f8wVHRfFTiQmt+gAuyArcT2liNJcbxoRsGT/hrz69+I+c/VtKglSqac23LxykBF5LJfH X-Received: by 2002:a17:907:b60e:b0:93e:9fb9:183b with SMTP id vl14-20020a170907b60e00b0093e9fb9183bmr22876534ejc.73.1680174089249; Thu, 30 Mar 2023 04:01:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680174089; cv=none; d=google.com; s=arc-20160816; b=Nff80y4HYGmGVU+f/Hzt4QVpUA5253NKqnmZ8+2o2UrzgbG1tpLK3+oWF/xw1zVgJP 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OpenDKIM Filter v2.11.0 sourceware.org 52389388D328 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1680172941; bh=Bwx1zSRjh2pxmRraBoNZH67g+LCH77eRzCS37L/v3FY=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=BZQDUBarXvIEZ6V65fGOz8Naexxh9v6lEpRZvmecar6G/c07ckdJpIUAjgrJPewc/ dlKVFOBKPd7XjapT7oqzdMwwftxFduziT0Rwj02i4jX3rJTTekVkRbyxEnBdgTiVmQ Oit6TA4jC0GCNZkQ5HzNwDbYfcanb21j5HXbxuiU= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id C3799385B52A for ; Thu, 30 Mar 2023 10:27:03 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org C3799385B52A Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DC7861682; Thu, 30 Mar 2023 03:27:47 -0700 (PDT) Received: from e121540-lin.manchester.arm.com (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1EE433F663; Thu, 30 Mar 2023 03:27:03 -0700 (PDT) To: binutils@sourceware.org Cc: Richard Sandiford Subject: [PATCH 13/31] aarch64: Add the SME2 FMLA and FMLS instructions Date: Thu, 30 Mar 2023 11:26:28 +0100 Message-Id: <20230330102646.3327818-14-richard.sandiford@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230330102646.3327818-1-richard.sandiford@arm.com> References: <20230330102646.3327818-1-richard.sandiford@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-31.3 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, SCC_10_SHORT_WORD_LINES, SCC_5_SHORT_WORD_LINES, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Richard Sandiford via Binutils From: Richard Sandiford Reply-To: Richard Sandiford Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761790225854077591?= X-GMAIL-MSGID: =?utf-8?q?1761790225854077591?= --- gas/config/tc-aarch64.c | 2 + gas/testsuite/gas/aarch64/sme2-11-invalid.d | 3 + gas/testsuite/gas/aarch64/sme2-11-invalid.l | 101 ++ gas/testsuite/gas/aarch64/sme2-11-invalid.s | 91 ++ gas/testsuite/gas/aarch64/sme2-11-noarch.d | 3 + gas/testsuite/gas/aarch64/sme2-11-noarch.l | 117 ++ gas/testsuite/gas/aarch64/sme2-11.d | 125 ++ gas/testsuite/gas/aarch64/sme2-11.s | 127 ++ .../gas/aarch64/sme2-f64f64-2-invalid.d | 3 + .../gas/aarch64/sme2-f64f64-2-invalid.l | 98 ++ .../gas/aarch64/sme2-f64f64-2-invalid.s | 87 ++ .../gas/aarch64/sme2-f64f64-2-noarch.d | 3 + .../gas/aarch64/sme2-f64f64-2-noarch.l | 117 ++ gas/testsuite/gas/aarch64/sme2-f64f64-2.d | 125 ++ gas/testsuite/gas/aarch64/sme2-f64f64-2.s | 127 ++ include/opcode/aarch64.h | 2 + opcodes/aarch64-asm-2.c | 18 +- opcodes/aarch64-dis-2.c | 1220 ++++++++++------- opcodes/aarch64-opc-2.c | 2 + opcodes/aarch64-opc.c | 12 + opcodes/aarch64-opc.h | 2 + opcodes/aarch64-tbl.h | 28 + 22 files changed, 1884 insertions(+), 529 deletions(-) create mode 100644 gas/testsuite/gas/aarch64/sme2-11-invalid.d create mode 100644 gas/testsuite/gas/aarch64/sme2-11-invalid.l create mode 100644 gas/testsuite/gas/aarch64/sme2-11-invalid.s create mode 100644 gas/testsuite/gas/aarch64/sme2-11-noarch.d create mode 100644 gas/testsuite/gas/aarch64/sme2-11-noarch.l create mode 100644 gas/testsuite/gas/aarch64/sme2-11.d create mode 100644 gas/testsuite/gas/aarch64/sme2-11.s create mode 100644 gas/testsuite/gas/aarch64/sme2-f64f64-2-invalid.d create mode 100644 gas/testsuite/gas/aarch64/sme2-f64f64-2-invalid.l create mode 100644 gas/testsuite/gas/aarch64/sme2-f64f64-2-invalid.s create mode 100644 gas/testsuite/gas/aarch64/sme2-f64f64-2-noarch.d create mode 100644 gas/testsuite/gas/aarch64/sme2-f64f64-2-noarch.l create mode 100644 gas/testsuite/gas/aarch64/sme2-f64f64-2.d create mode 100644 gas/testsuite/gas/aarch64/sme2-f64f64-2.s diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 5e023152c17..47ad7048372 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -6727,6 +6727,8 @@ parse_operands (char *str, const aarch64_opcode *opcode) case AARCH64_OPND_SVE_Zm4_11_INDEX: case AARCH64_OPND_SVE_Zm4_INDEX: case AARCH64_OPND_SVE_Zn_INDEX: + case AARCH64_OPND_SME_Zm_INDEX1: + case AARCH64_OPND_SME_Zm_INDEX2: case AARCH64_OPND_SME_Zn_INDEX1_16: case AARCH64_OPND_SME_Zn_INDEX2_15: case AARCH64_OPND_SME_Zn_INDEX2_16: diff --git a/gas/testsuite/gas/aarch64/sme2-11-invalid.d b/gas/testsuite/gas/aarch64/sme2-11-invalid.d new file mode 100644 index 00000000000..1bc250965dd --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-11-invalid.d @@ -0,0 +1,3 @@ +#as: -march=armv8-a +#source: sme2-11-invalid.s +#error_output: sme2-11-invalid.l diff --git a/gas/testsuite/gas/aarch64/sme2-11-invalid.l b/gas/testsuite/gas/aarch64/sme2-11-invalid.l new file mode 100644 index 00000000000..8044d265750 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-11-invalid.l @@ -0,0 +1,101 @@ +[^ :]+: Assembler messages: +[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `fmla 0,{z0\.s-z1\.s},z0\.s\[0\]' +[^ :]+:[0-9]+: Error: expected '{' at operand 2 -- `fmla za\.s\[w8,0\],0,z0\.s\[0\]' +[^ :]+:[0-9]+: Error: expected a register or register list at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z1\.s},0' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.s\[w7,0\],{z0\.s-z1\.s},z0\.s\[0\]' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.s\[w12,0\],{z0\.s-z1\.s},z0\.s\[0\]' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.s\[w8,-1\],{z0\.s-z1\.s},z0\.s\[0\]' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.s\[w8,8\],{z0\.s-z1\.s},z0\.s\[0\]' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `fmla za\.s\[w8,0,vgx4\],{z0\.s-z1\.s},z0\.s\[0\]' +[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `fmla za\.s\[w8,0\],{z0\.s-z2\.s},z0\.s\[0\]' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\.s\[w8,0\],{z1\.s-z2\.s},z0\.s\[0\]' +[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z1\.s},z16\.s\[0\]' +[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z1\.s},z0\.s\[-1\]' +[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z1\.s},z0\.s\[4\]' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.s\[w7,0\],{z0\.s-z3\.s},z0\.s\[0\]' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.s\[w12,0\],{z0\.s-z3\.s},z0\.s\[0\]' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.s\[w8,-1\],{z0\.s-z3\.s},z0\.s\[0\]' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.s\[w8,8\],{z0\.s-z3\.s},z0\.s\[0\]' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `fmla za\.s\[w8,0,vgx2\],{z0\.s-z3\.s},z0\.s\[0\]' +[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 2 -- `fmla za\.s\[w8,0\],{z0\.s-z4\.s},z0\.s\[0\]' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\.s\[w8,0\],{z1\.s-z4\.s},z0\.s\[0\]' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\.s\[w8,0\],{z2\.s-z5\.s},z0\.s\[0\]' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\.s\[w8,0\],{z3\.s-z6\.s},z0\.s\[0\]' +[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z3\.s},z16\.s\[0\]' +[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z3\.s},z0\.s\[-1\]' +[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z3\.s},z0\.s\[4\]' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.s\[w0,0\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: expected a 32-bit selection register at operand 1 -- `fmla za\.s\[w31,0\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.s\[w8,1<<63\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z1\.s},z31\.s' +[^ :]+:[0-9]+: Error: the last offset is equal to the first offset at operand 1 -- `fmla za\.s\[w8,0:0\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: the last offset is less than the first offset at operand 1 -- `fmla za\.s\[w8,0:-1\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: expected a single offset rather than a range at operand 1 -- `fmla za\.s\[w8,0:1\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: expected a single offset rather than a range at operand 1 -- `fmla za\.s\[w8,0:100\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.s\[w7,0\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.s\[w12,0\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.s\[w8,-1\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.s\[w8,8\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z1\.s},z16\.s' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.s\[w7,0\],{z0\.s-z3\.s},z0\.s' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.s\[w12,0\],{z0\.s-z3\.s},z0\.s' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.s\[w8,-1\],{z0\.s-z3\.s},z0\.s' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.s\[w8,8\],{z0\.s-z3\.s},z0\.s' +[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z3\.s},z16\.s' +[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `fmla za\.s\[w8,0\],{z0\.s-z2\.s},z0\.s' +[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 2 -- `fmla za\.s\[w8,0\],{z0\.s-z4\.s},z0\.s' +[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `fmla za\.s\[w8,0\],{z0\.s,z1\.s,z2\.s},z0\.s' +[^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `fmla za\.s\[w8,0\],{z0\.s,z1\.s,z5\.s},z0\.s' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `fmla za\.s\[w8,0,vgx4\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `fmla za\.s\[w8,0,vgx2\],{z0\.s-z3\.s},z0\.s' +[^ :]+:[0-9]+: Error: operand mismatch -- `fmla za\[w8,0\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: fmla za\.s\[w8, 0\], {z0\.s-z1\.s}, z0\.s +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: fmla za\.d\[w8, 0\], {z0\.d-z1\.d}, z0\.d +[^ :]+:[0-9]+: Error: missing type suffix at operand 2 -- `fmla za\.s\[w8,0\],{z0-z1},z0\.s' +[^ :]+:[0-9]+: Error: operand mismatch -- `fmla za\.s\[w8,0\],{z0\.s-z1\.s},z0' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: fmla za\.s\[w8, 0\], {z0\.s-z1\.s}, z0\.s +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: fmla za\.d\[w8, 0\], {z0\.d-z1\.d}, z0\.d +[^ :]+:[0-9]+: Error: operand mismatch -- `fmla za\[w8,0\],{z0\.s-z1\.s},z0' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: fmla za\.s\[w8, 0\], {z0\.s-z1\.s}, z0\.s +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: fmla za\.d\[w8, 0\], {z0\.d-z1\.d}, z0\.d +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.s\[w7,0\],{z0\.s-z1\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.s\[w12,0\],{z0\.s-z1\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.s\[w8,-1\],{z0\.s-z1\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.s\[w8,8\],{z0\.s-z1\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\.s\[w8,0\],{z1\.s-z2\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z1\.s},{z15\.s-z16\.s}' +[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z1\.s},{z31\.s,z0\.s}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.s\[w7,0\],{z0\.s-z3\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.s\[w12,0\],{z0\.s-z3\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.s\[w8,-1\],{z0\.s-z3\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.s\[w8,8\],{z0\.s-z3\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\.s\[w8,0\],{z1\.s-z4\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\.s\[w8,0\],{z2\.s-z5\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\.s\[w8,0\],{z3\.s-z6\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z3\.s},{z15\.s-z18\.s}' +[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z3\.s},{z29\.s,z30\.s,z31\.s,z0\.s}' +[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `fmla za\.s\[w8,0\],{z0\.s-z2\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z3\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z1\.s},{z0\.s-z2\.s}' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z1\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z1\.s},{z0\.s-z4\.s}' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `fmla za\.s\[w8,0,vgx4\],{z0\.s-z1\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 3 -- `fmla za\.s\[w8,0,vgx4\],{z0\.s-z3\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `fmla za\.s\[w8,0,vgx2\],{z0\.s-z1\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `fmla za\.s\[w8,0,vgx2\],{z0\.s-z3\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: operand mismatch -- `fmla za\[w8,0\],{z0\.s-z1\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: fmla za\.s\[w8, 0\], {z0\.s-z1\.s}, {z0\.s-z1\.s} +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: fmla za\.d\[w8, 0\], {z0\.d-z1\.d}, {z0\.d-z1\.d} +[^ :]+:[0-9]+: Error: operand mismatch -- `fmla za\[w8,0\],{z0\.s-z3\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: fmla za\.s\[w8, 0\], {z0\.s-z3\.s}, {z0\.s-z3\.s} +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: fmla za\.d\[w8, 0\], {z0\.d-z3\.d}, {z0\.d-z3\.d} diff --git a/gas/testsuite/gas/aarch64/sme2-11-invalid.s b/gas/testsuite/gas/aarch64/sme2-11-invalid.s new file mode 100644 index 00000000000..70ab0c42e36 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-11-invalid.s @@ -0,0 +1,91 @@ + fmla 0, { z0.s - z1.s }, z0.s[0] + fmla za.s[w8, 0], 0, z0.s[0] + fmla za.s[w8, 0], { z0.s - z1.s }, 0 + + fmla za.s[w7, 0], { z0.s - z1.s }, z0.s[0] + fmla za.s[w12, 0], { z0.s - z1.s }, z0.s[0] + fmla za.s[w8, -1], { z0.s - z1.s }, z0.s[0] + fmla za.s[w8, 8], { z0.s - z1.s }, z0.s[0] + fmla za.s[w8, 0, vgx4], { z0.s - z1.s }, z0.s[0] + fmla za.s[w8, 0], { z0.s - z2.s }, z0.s[0] + fmla za.s[w8, 0], { z1.s - z2.s }, z0.s[0] + fmla za.s[w8, 0], { z0.s - z1.s }, z16.s[0] + fmla za.s[w8, 0], { z0.s - z1.s }, z0.s[-1] + fmla za.s[w8, 0], { z0.s - z1.s }, z0.s[4] + + fmla za.s[w7, 0], { z0.s - z3.s }, z0.s[0] + fmla za.s[w12, 0], { z0.s - z3.s }, z0.s[0] + fmla za.s[w8, -1], { z0.s - z3.s }, z0.s[0] + fmla za.s[w8, 8], { z0.s - z3.s }, z0.s[0] + fmla za.s[w8, 0, vgx2], { z0.s - z3.s }, z0.s[0] + fmla za.s[w8, 0], { z0.s - z4.s }, z0.s[0] + fmla za.s[w8, 0], { z1.s - z4.s }, z0.s[0] + fmla za.s[w8, 0], { z2.s - z5.s }, z0.s[0] + fmla za.s[w8, 0], { z3.s - z6.s }, z0.s[0] + fmla za.s[w8, 0], { z0.s - z3.s }, z16.s[0] + fmla za.s[w8, 0], { z0.s - z3.s }, z0.s[-1] + fmla za.s[w8, 0], { z0.s - z3.s }, z0.s[4] + + fmla za.s[w0, 0], { z0.s - z1.s }, z0.s + fmla za.s[w31, 0], { z0.s - z1.s }, z0.s + fmla za.s[w8, 1<<63], { z0.s - z1.s }, z0.s + fmla za.s[w8, 0], { z0.s - z1.s }, z31.s + fmla za.s[w8, 0:0], { z0.s - z1.s }, z0.s + fmla za.s[w8, 0:-1], { z0.s - z1.s }, z0.s + fmla za.s[w8, 0:1], { z0.s - z1.s }, z0.s + fmla za.s[w8, 0:100], { z0.s - z1.s }, z0.s + + fmla za.s[w7, 0], { z0.s - z1.s }, z0.s + fmla za.s[w12, 0], { z0.s - z1.s }, z0.s + fmla za.s[w8, -1], { z0.s - z1.s }, z0.s + fmla za.s[w8, 8], { z0.s - z1.s }, z0.s + fmla za.s[w8, 0], { z0.s - z1.s }, z16.s + + fmla za.s[w7, 0], { z0.s - z3.s }, z0.s + fmla za.s[w12, 0], { z0.s - z3.s }, z0.s + fmla za.s[w8, -1], { z0.s - z3.s }, z0.s + fmla za.s[w8, 8], { z0.s - z3.s }, z0.s + fmla za.s[w8, 0], { z0.s - z3.s }, z16.s + + fmla za.s[w8, 0], { z0.s - z2.s }, z0.s + fmla za.s[w8, 0], { z0.s - z4.s }, z0.s + fmla za.s[w8, 0], { z0.s, z1.s, z2.s }, z0.s + fmla za.s[w8, 0], { z0.s, z1.s, z5.s }, z0.s + + fmla za.s[w8, 0, vgx4], { z0.s - z1.s }, z0.s + fmla za.s[w8, 0, vgx2], { z0.s - z3.s }, z0.s + fmla za[w8, 0], { z0.s - z1.s }, z0.s + fmla za.s[w8, 0], { z0 - z1 }, z0.s + fmla za.s[w8, 0], { z0.s - z1.s }, z0 + fmla za[w8, 0], { z0.s - z1.s }, z0 + + fmla za.s[w7, 0], { z0.s - z1.s }, { z0.s - z1.s } + fmla za.s[w12, 0], { z0.s - z1.s }, { z0.s - z1.s } + fmla za.s[w8, -1], { z0.s - z1.s }, { z0.s - z1.s } + fmla za.s[w8, 8], { z0.s - z1.s }, { z0.s - z1.s } + fmla za.s[w8, 0], { z1.s - z2.s }, { z0.s - z1.s } + fmla za.s[w8, 0], { z0.s - z1.s }, { z15.s - z16.s } + fmla za.s[w8, 0], { z0.s - z1.s }, { z31.s, z0.s } + + fmla za.s[w7, 0], { z0.s - z3.s }, { z0.s - z3.s } + fmla za.s[w12, 0], { z0.s - z3.s }, { z0.s - z3.s } + fmla za.s[w8, -1], { z0.s - z3.s }, { z0.s - z3.s } + fmla za.s[w8, 8], { z0.s - z3.s }, { z0.s - z3.s } + fmla za.s[w8, 0], { z1.s - z4.s }, { z0.s - z3.s } + fmla za.s[w8, 0], { z2.s - z5.s }, { z0.s - z3.s } + fmla za.s[w8, 0], { z3.s - z6.s }, { z0.s - z3.s } + fmla za.s[w8, 0], { z0.s - z3.s }, { z15.s - z18.s } + fmla za.s[w8, 0], { z0.s - z3.s }, { z29.s, z30.s, z31.s, z0.s } + + fmla za.s[w8, 0], { z0.s - z2.s }, { z0.s - z1.s } + fmla za.s[w8, 0], { z0.s - z3.s }, { z0.s - z1.s } + fmla za.s[w8, 0], { z0.s - z1.s }, { z0.s - z2.s } + fmla za.s[w8, 0], { z0.s - z1.s }, { z0.s - z3.s } + fmla za.s[w8, 0], { z0.s - z1.s }, { z0.s - z4.s } + + fmla za.s[w8, 0, vgx4], { z0.s - z1.s }, { z0.s - z3.s } + fmla za.s[w8, 0, vgx4], { z0.s - z3.s }, { z0.s - z1.s } + fmla za.s[w8, 0, vgx2], { z0.s - z1.s }, { z0.s - z3.s } + fmla za.s[w8, 0, vgx2], { z0.s - z3.s }, { z0.s - z1.s } + fmla za[w8, 0], { z0.s - z1.s }, { z0.s - z1.s } + fmla za[w8, 0], { z0.s - z3.s }, { z0.s - z3.s } diff --git a/gas/testsuite/gas/aarch64/sme2-11-noarch.d b/gas/testsuite/gas/aarch64/sme2-11-noarch.d new file mode 100644 index 00000000000..7dcb6a04885 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-11-noarch.d @@ -0,0 +1,3 @@ +#as: -march=armv8-a+sme +#source: sme2-11.s +#error_output: sme2-11-noarch.l diff --git a/gas/testsuite/gas/aarch64/sme2-11-noarch.l b/gas/testsuite/gas/aarch64/sme2-11-noarch.l new file mode 100644 index 00000000000..05c3139f3b7 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-11-noarch.l @@ -0,0 +1,117 @@ +[^ :]+: Assembler messages: +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z0\.s-z1\.s},z0\.s\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0,vgx2\],{z0\.s-z1\.s},z0\.s\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.S\[W8,0,VGx2\],{Z0\.S-Z1\.S},Z0\.S\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w11,0\],{z0\.s-z1\.s},z0\.s\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,7\],{z0\.s-z1\.s},z0\.s\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z30\.s-z31\.s},z0\.s\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z0\.s-z1\.s},z15\.s\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z0\.s-z1\.s},z0\.s\[3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w9,6\],{z12\.s-z13\.s},z1\.s\[2\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z0\.s-z3\.s},z0\.s\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0,vgx4\],{z0\.s-z3\.s},z0\.s\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.S\[W8,0,VGX4\],{Z0\.S-Z3\.S},Z0\.S\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w11,0\],{z0\.s-z3\.s},z0\.s\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,7\],{z0\.s-z3\.s},z0\.s\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z28\.s-z31\.s},z0\.s\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z0\.s-z3\.s},z15\.s\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z0\.s-z3\.s},z0\.s\[3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w10,4\],{z4\.s-z7\.s},z9\.s\[1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0,vgx2\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.s\[W8,0,VGx2\],{Z0\.s-Z1\.s},Z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.S\[W8,0,VGX2\],{Z0\.S-Z1\.S},Z0\.S' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w11,0\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,7\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z30\.s-z31\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z31\.s,z0\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z31\.s-z0\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z0\.s-z1\.s},z15\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w9,5\],{z9\.s-z10\.s},z6\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z0\.s-z3\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0,vgx4\],{z0\.s-z3\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.s\[W8,0,VGx4\],{Z0\.s-Z3\.s},Z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.S\[W8,0,VGX4\],{Z0\.S-Z3\.S},Z0\.S' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w11,0\],{z0\.s-z3\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,7\],{z0\.s-z3\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z28\.s-z31\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z31\.s,z0\.s,z1\.s,z2\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z31\.s-z2\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z0\.s-z3\.s},z15\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w11,2\],{z23\.s-z26\.s},z13\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z0\.s-z1\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0,vgx2\],{z0\.s-z1\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.s\[W8,0,VGx2\],{Z0\.s-Z1\.s},{Z0\.s-Z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.S\[W8,0,VGX2\],{Z0\.S-Z1\.S},{Z0\.S-Z1\.S}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w11,0\],{z0\.s-z1\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,7\],{z0\.s-z1\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z30\.s-z31\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z0\.s-z1\.s},{z30\.s-z31\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w10,1\],{z22\.s-z23\.s},{z18\.s-z19\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z0\.s-z3\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0,vgx4\],{z0\.s-z3\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.s\[W8,0,VGx4\],{Z0\.s-Z3\.s},{Z0\.s-Z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.S\[W8,0,VGX4\],{Z0\.S-Z3\.S},{Z0\.S-Z3\.S}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w11,0\],{z0\.s-z3\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,7\],{z0\.s-z3\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z28\.s-z31\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z0\.s-z3\.s},{z28\.s-z31\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w11,3\],{z16\.s-z19\.s},{z24\.s-z27\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z0\.s-z1\.s},z0\.s\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0,vgx2\],{z0\.s-z1\.s},z0\.s\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.S\[W8,0,VGx2\],{Z0\.S-Z1\.S},Z0\.S\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w11,0\],{z0\.s-z1\.s},z0\.s\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,7\],{z0\.s-z1\.s},z0\.s\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z30\.s-z31\.s},z0\.s\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z0\.s-z1\.s},z15\.s\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z0\.s-z1\.s},z0\.s\[3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w9,6\],{z12\.s-z13\.s},z1\.s\[2\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z0\.s-z3\.s},z0\.s\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0,vgx4\],{z0\.s-z3\.s},z0\.s\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.S\[W8,0,VGX4\],{Z0\.S-Z3\.S},Z0\.S\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w11,0\],{z0\.s-z3\.s},z0\.s\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,7\],{z0\.s-z3\.s},z0\.s\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z28\.s-z31\.s},z0\.s\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z0\.s-z3\.s},z15\.s\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z0\.s-z3\.s},z0\.s\[3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w10,4\],{z4\.s-z7\.s},z9\.s\[1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0,vgx2\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.s\[W8,0,VGx2\],{Z0\.s-Z1\.s},Z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.S\[W8,0,VGX2\],{Z0\.S-Z1\.S},Z0\.S' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w11,0\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,7\],{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z30\.s-z31\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z31\.s,z0\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z31\.s-z0\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z0\.s-z1\.s},z15\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w9,5\],{z9\.s-z10\.s},z6\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z0\.s-z3\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0,vgx4\],{z0\.s-z3\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.s\[W8,0,VGx4\],{Z0\.s-Z3\.s},Z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.S\[W8,0,VGX4\],{Z0\.S-Z3\.S},Z0\.S' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w11,0\],{z0\.s-z3\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,7\],{z0\.s-z3\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z28\.s-z31\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z31\.s,z0\.s,z1\.s,z2\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z31\.s-z2\.s},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z0\.s-z3\.s},z15\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w11,2\],{z23\.s-z26\.s},z13\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z0\.s-z1\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0,vgx2\],{z0\.s-z1\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.s\[W8,0,VGx2\],{Z0\.s-Z1\.s},{Z0\.s-Z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.S\[W8,0,VGX2\],{Z0\.S-Z1\.S},{Z0\.S-Z1\.S}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w11,0\],{z0\.s-z1\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,7\],{z0\.s-z1\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z30\.s-z31\.s},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z0\.s-z1\.s},{z30\.s-z31\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w10,1\],{z22\.s-z23\.s},{z18\.s-z19\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z0\.s-z3\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0,vgx4\],{z0\.s-z3\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.s\[W8,0,VGx4\],{Z0\.s-Z3\.s},{Z0\.s-Z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.S\[W8,0,VGX4\],{Z0\.S-Z3\.S},{Z0\.S-Z3\.S}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w11,0\],{z0\.s-z3\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,7\],{z0\.s-z3\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z28\.s-z31\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z0\.s-z3\.s},{z28\.s-z31\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w11,3\],{z16\.s-z19\.s},{z24\.s-z27\.s}' diff --git a/gas/testsuite/gas/aarch64/sme2-11.d b/gas/testsuite/gas/aarch64/sme2-11.d new file mode 100644 index 00000000000..7f077e3a614 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-11.d @@ -0,0 +1,125 @@ +#as: -march=armv8-a+sme2 +#objdump: -dr + +[^:]+: file format .* + + +[^:]+: + +[^:]+: +[^:]+: c1500000 fmla za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s\[0\] +[^:]+: c1500000 fmla za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s\[0\] +[^:]+: c1500000 fmla za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s\[0\] +[^:]+: c1506000 fmla za\.s\[w11, 0, vgx2\], {z0\.s-z1\.s}, z0\.s\[0\] +[^:]+: c1500007 fmla za\.s\[w8, 7, vgx2\], {z0\.s-z1\.s}, z0\.s\[0\] +[^:]+: c15003c0 fmla za\.s\[w8, 0, vgx2\], {z30\.s-z31\.s}, z0\.s\[0\] +[^:]+: c15f0000 fmla za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z15\.s\[0\] +[^:]+: c1500c00 fmla za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s\[3\] +[^:]+: c1512986 fmla za\.s\[w9, 6, vgx2\], {z12\.s-z13\.s}, z1\.s\[2\] +[^:]+: c1508000 fmla za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s\[0\] +[^:]+: c1508000 fmla za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s\[0\] +[^:]+: c1508000 fmla za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s\[0\] +[^:]+: c150e000 fmla za\.s\[w11, 0, vgx4\], {z0\.s-z3\.s}, z0\.s\[0\] +[^:]+: c1508007 fmla za\.s\[w8, 7, vgx4\], {z0\.s-z3\.s}, z0\.s\[0\] +[^:]+: c1508380 fmla za\.s\[w8, 0, vgx4\], {z28\.s-z31\.s}, z0\.s\[0\] +[^:]+: c15f8000 fmla za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z15\.s\[0\] +[^:]+: c1508c00 fmla za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s\[3\] +[^:]+: c159c484 fmla za\.s\[w10, 4, vgx4\], {z4\.s-z7\.s}, z9\.s\[1\] +[^:]+: c1201800 fmla za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s +[^:]+: c1201800 fmla za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s +[^:]+: c1201800 fmla za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s +[^:]+: c1201800 fmla za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s +[^:]+: c1207800 fmla za\.s\[w11, 0, vgx2\], {z0\.s-z1\.s}, z0\.s +[^:]+: c1201807 fmla za\.s\[w8, 7, vgx2\], {z0\.s-z1\.s}, z0\.s +[^:]+: c1201bc0 fmla za\.s\[w8, 0, vgx2\], {z30\.s-z31\.s}, z0\.s +[^:]+: c1201be0 fmla za\.s\[w8, 0, vgx2\], {z31\.s-z0\.s}, z0\.s +[^:]+: c1201be0 fmla za\.s\[w8, 0, vgx2\], {z31\.s-z0\.s}, z0\.s +[^:]+: c12f1800 fmla za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z15\.s +[^:]+: c1263925 fmla za\.s\[w9, 5, vgx2\], {z9\.s-z10\.s}, z6\.s +[^:]+: c1301800 fmla za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s +[^:]+: c1301800 fmla za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s +[^:]+: c1301800 fmla za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s +[^:]+: c1301800 fmla za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s +[^:]+: c1307800 fmla za\.s\[w11, 0, vgx4\], {z0\.s-z3\.s}, z0\.s +[^:]+: c1301807 fmla za\.s\[w8, 7, vgx4\], {z0\.s-z3\.s}, z0\.s +[^:]+: c1301b80 fmla za\.s\[w8, 0, vgx4\], {z28\.s-z31\.s}, z0\.s +[^:]+: c1301be0 fmla za\.s\[w8, 0, vgx4\], {z31\.s-z2\.s}, z0\.s +[^:]+: c1301be0 fmla za\.s\[w8, 0, vgx4\], {z31\.s-z2\.s}, z0\.s +[^:]+: c13f1800 fmla za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z15\.s +[^:]+: c13d7ae2 fmla za\.s\[w11, 2, vgx4\], {z23\.s-z26\.s}, z13\.s +[^:]+: c1a01800 fmla za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s} +[^:]+: c1a01800 fmla za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s} +[^:]+: c1a01800 fmla za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s} +[^:]+: c1a01800 fmla za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s} +[^:]+: c1a07800 fmla za\.s\[w11, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s} +[^:]+: c1a01807 fmla za\.s\[w8, 7, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s} +[^:]+: c1a01bc0 fmla za\.s\[w8, 0, vgx2\], {z30\.s-z31\.s}, {z0\.s-z1\.s} +[^:]+: c1be1800 fmla za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z30\.s-z31\.s} +[^:]+: c1b25ac1 fmla za\.s\[w10, 1, vgx2\], {z22\.s-z23\.s}, {z18\.s-z19\.s} +[^:]+: c1a11800 fmla za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s} +[^:]+: c1a11800 fmla za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s} +[^:]+: c1a11800 fmla za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s} +[^:]+: c1a11800 fmla za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s} +[^:]+: c1a17800 fmla za\.s\[w11, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s} +[^:]+: c1a11807 fmla za\.s\[w8, 7, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s} +[^:]+: c1a11b80 fmla za\.s\[w8, 0, vgx4\], {z28\.s-z31\.s}, {z0\.s-z3\.s} +[^:]+: c1bd1800 fmla za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z28\.s-z31\.s} +[^:]+: c1b97a03 fmla za\.s\[w11, 3, vgx4\], {z16\.s-z19\.s}, {z24\.s-z27\.s} +[^:]+: c1500010 fmls za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s\[0\] +[^:]+: c1500010 fmls za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s\[0\] +[^:]+: c1500010 fmls za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s\[0\] +[^:]+: c1506010 fmls za\.s\[w11, 0, vgx2\], {z0\.s-z1\.s}, z0\.s\[0\] +[^:]+: c1500017 fmls za\.s\[w8, 7, vgx2\], {z0\.s-z1\.s}, z0\.s\[0\] +[^:]+: c15003d0 fmls za\.s\[w8, 0, vgx2\], {z30\.s-z31\.s}, z0\.s\[0\] +[^:]+: c15f0010 fmls za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z15\.s\[0\] +[^:]+: c1500c10 fmls za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s\[3\] +[^:]+: c1512996 fmls za\.s\[w9, 6, vgx2\], {z12\.s-z13\.s}, z1\.s\[2\] +[^:]+: c1508010 fmls za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s\[0\] +[^:]+: c1508010 fmls za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s\[0\] +[^:]+: c1508010 fmls za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s\[0\] +[^:]+: c150e010 fmls za\.s\[w11, 0, vgx4\], {z0\.s-z3\.s}, z0\.s\[0\] +[^:]+: c1508017 fmls za\.s\[w8, 7, vgx4\], {z0\.s-z3\.s}, z0\.s\[0\] +[^:]+: c1508390 fmls za\.s\[w8, 0, vgx4\], {z28\.s-z31\.s}, z0\.s\[0\] +[^:]+: c15f8010 fmls za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z15\.s\[0\] +[^:]+: c1508c10 fmls za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s\[3\] +[^:]+: c159c494 fmls za\.s\[w10, 4, vgx4\], {z4\.s-z7\.s}, z9\.s\[1\] +[^:]+: c1201808 fmls za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s +[^:]+: c1201808 fmls za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s +[^:]+: c1201808 fmls za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s +[^:]+: c1201808 fmls za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s +[^:]+: c1207808 fmls za\.s\[w11, 0, vgx2\], {z0\.s-z1\.s}, z0\.s +[^:]+: c120180f fmls za\.s\[w8, 7, vgx2\], {z0\.s-z1\.s}, z0\.s +[^:]+: c1201bc8 fmls za\.s\[w8, 0, vgx2\], {z30\.s-z31\.s}, z0\.s +[^:]+: c1201be8 fmls za\.s\[w8, 0, vgx2\], {z31\.s-z0\.s}, z0\.s +[^:]+: c1201be8 fmls za\.s\[w8, 0, vgx2\], {z31\.s-z0\.s}, z0\.s +[^:]+: c12f1808 fmls za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z15\.s +[^:]+: c126392d fmls za\.s\[w9, 5, vgx2\], {z9\.s-z10\.s}, z6\.s +[^:]+: c1301808 fmls za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s +[^:]+: c1301808 fmls za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s +[^:]+: c1301808 fmls za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s +[^:]+: c1301808 fmls za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s +[^:]+: c1307808 fmls za\.s\[w11, 0, vgx4\], {z0\.s-z3\.s}, z0\.s +[^:]+: c130180f fmls za\.s\[w8, 7, vgx4\], {z0\.s-z3\.s}, z0\.s +[^:]+: c1301b88 fmls za\.s\[w8, 0, vgx4\], {z28\.s-z31\.s}, z0\.s +[^:]+: c1301be8 fmls za\.s\[w8, 0, vgx4\], {z31\.s-z2\.s}, z0\.s +[^:]+: c1301be8 fmls za\.s\[w8, 0, vgx4\], {z31\.s-z2\.s}, z0\.s +[^:]+: c13f1808 fmls za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z15\.s +[^:]+: c13d7aea fmls za\.s\[w11, 2, vgx4\], {z23\.s-z26\.s}, z13\.s +[^:]+: c1a01808 fmls za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s} +[^:]+: c1a01808 fmls za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s} +[^:]+: c1a01808 fmls za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s} +[^:]+: c1a01808 fmls za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s} +[^:]+: c1a07808 fmls za\.s\[w11, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s} +[^:]+: c1a0180f fmls za\.s\[w8, 7, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s} +[^:]+: c1a01bc8 fmls za\.s\[w8, 0, vgx2\], {z30\.s-z31\.s}, {z0\.s-z1\.s} +[^:]+: c1be1808 fmls za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z30\.s-z31\.s} +[^:]+: c1b25ac9 fmls za\.s\[w10, 1, vgx2\], {z22\.s-z23\.s}, {z18\.s-z19\.s} +[^:]+: c1a11808 fmls za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s} +[^:]+: c1a11808 fmls za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s} +[^:]+: c1a11808 fmls za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s} +[^:]+: c1a11808 fmls za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s} +[^:]+: c1a17808 fmls za\.s\[w11, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s} +[^:]+: c1a1180f fmls za\.s\[w8, 7, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s} +[^:]+: c1a11b88 fmls za\.s\[w8, 0, vgx4\], {z28\.s-z31\.s}, {z0\.s-z3\.s} +[^:]+: c1bd1808 fmls za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z28\.s-z31\.s} +[^:]+: c1b97a0b fmls za\.s\[w11, 3, vgx4\], {z16\.s-z19\.s}, {z24\.s-z27\.s} diff --git a/gas/testsuite/gas/aarch64/sme2-11.s b/gas/testsuite/gas/aarch64/sme2-11.s new file mode 100644 index 00000000000..fbefe0dca5f --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-11.s @@ -0,0 +1,127 @@ + fmla za.s[w8, 0], { z0.s - z1.s }, z0.s[0] + fmla za.s[w8, 0, vgx2], { z0.s - z1.s }, z0.s[0] + FMLA ZA.S[W8, 0, VGx2], { Z0.S - Z1.S }, Z0.S[0] + fmla za.s[w11, 0], { z0.s - z1.s }, z0.s[0] + fmla za.s[w8, 7], { z0.s - z1.s }, z0.s[0] + fmla za.s[w8, 0], { z30.s - z31.s }, z0.s[0] + fmla za.s[w8, 0], { z0.s - z1.s }, z15.s[0] + fmla za.s[w8, 0], { z0.s - z1.s }, z0.s[3] + fmla za.s[w9, 6], { z12.s - z13.s }, z1.s[2] + + fmla za.s[w8, 0], { z0.s - z3.s }, z0.s[0] + fmla za.s[w8, 0, vgx4], { z0.s - z3.s }, z0.s[0] + FMLA ZA.S[W8, 0, VGX4], { Z0.S - Z3.S }, Z0.S[0] + fmla za.s[w11, 0], { z0.s - z3.s }, z0.s[0] + fmla za.s[w8, 7], { z0.s - z3.s }, z0.s[0] + fmla za.s[w8, 0], { z28.s - z31.s }, z0.s[0] + fmla za.s[w8, 0], { z0.s - z3.s }, z15.s[0] + fmla za.s[w8, 0], { z0.s - z3.s }, z0.s[3] + fmla za.s[w10, 4], { z4.s - z7.s }, z9.s[1] + + fmla za.s[w8, 0], { z0.s - z1.s }, z0.s + fmla za.s[w8, 0, vgx2], { z0.s - z1.s }, z0.s + FMLA ZA.s[W8, 0, VGx2], { Z0.s - Z1.s }, Z0.s + FMLA ZA.S[W8, 0, VGX2], { Z0.S - Z1.S }, Z0.S + fmla za.s[w11, 0], { z0.s - z1.s }, z0.s + fmla za.s[w8, 7], { z0.s - z1.s }, z0.s + fmla za.s[w8, 0], { z30.s - z31.s }, z0.s + fmla za.s[w8, 0], { z31.s, z0.s }, z0.s + fmla za.s[w8, 0], { z31.s - z0.s }, z0.s + fmla za.s[w8, 0], { z0.s - z1.s }, z15.s + fmla za.s[w9, 5], { z9.s - z10.s }, z6.s + + fmla za.s[w8, 0], { z0.s - z3.s }, z0.s + fmla za.s[w8, 0, vgx4], { z0.s - z3.s }, z0.s + FMLA ZA.s[W8, 0, VGx4], { Z0.s - Z3.s }, Z0.s + FMLA ZA.S[W8, 0, VGX4], { Z0.S - Z3.S }, Z0.S + fmla za.s[w11, 0], { z0.s - z3.s }, z0.s + fmla za.s[w8, 7], { z0.s - z3.s }, z0.s + fmla za.s[w8, 0], { z28.s - z31.s }, z0.s + fmla za.s[w8, 0], { z31.s, z0.s, z1.s, z2.s }, z0.s + fmla za.s[w8, 0], { z31.s - z2.s }, z0.s + fmla za.s[w8, 0], { z0.s - z3.s }, z15.s + fmla za.s[w11, 2], { z23.s - z26.s }, z13.s + + fmla za.s[w8, 0], { z0.s - z1.s }, { z0.s - z1.s } + fmla za.s[w8, 0, vgx2], { z0.s - z1.s }, { z0.s - z1.s } + FMLA ZA.s[W8, 0, VGx2], { Z0.s - Z1.s }, { Z0.s - Z1.s } + FMLA ZA.S[W8, 0, VGX2], { Z0.S - Z1.S }, { Z0.S - Z1.S } + fmla za.s[w11, 0], { z0.s - z1.s }, { z0.s - z1.s } + fmla za.s[w8, 7], { z0.s - z1.s }, { z0.s - z1.s } + fmla za.s[w8, 0], { z30.s - z31.s }, { z0.s - z1.s } + fmla za.s[w8, 0], { z0.s - z1.s }, { z30.s - z31.s } + fmla za.s[w10, 1], { z22.s - z23.s }, { z18.s - z19.s } + + fmla za.s[w8, 0], { z0.s - z3.s }, { z0.s - z3.s } + fmla za.s[w8, 0, vgx4], { z0.s - z3.s }, { z0.s - z3.s } + FMLA ZA.s[W8, 0, VGx4], { Z0.s - Z3.s }, { Z0.s - Z3.s } + FMLA ZA.S[W8, 0, VGX4], { Z0.S - Z3.S }, { Z0.S - Z3.S } + fmla za.s[w11, 0], { z0.s - z3.s }, { z0.s - z3.s } + fmla za.s[w8, 7], { z0.s - z3.s }, { z0.s - z3.s } + fmla za.s[w8, 0], { z28.s - z31.s }, { z0.s - z3.s } + fmla za.s[w8, 0], { z0.s - z3.s }, { z28.s - z31.s } + fmla za.s[w11, 3], { z16.s - z19.s }, { z24.s - z27.s } + + fmls za.s[w8, 0], { z0.s - z1.s }, z0.s[0] + fmls za.s[w8, 0, vgx2], { z0.s - z1.s }, z0.s[0] + FMLS ZA.S[W8, 0, VGx2], { Z0.S - Z1.S }, Z0.S[0] + fmls za.s[w11, 0], { z0.s - z1.s }, z0.s[0] + fmls za.s[w8, 7], { z0.s - z1.s }, z0.s[0] + fmls za.s[w8, 0], { z30.s - z31.s }, z0.s[0] + fmls za.s[w8, 0], { z0.s - z1.s }, z15.s[0] + fmls za.s[w8, 0], { z0.s - z1.s }, z0.s[3] + fmls za.s[w9, 6], { z12.s - z13.s }, z1.s[2] + + fmls za.s[w8, 0], { z0.s - z3.s }, z0.s[0] + fmls za.s[w8, 0, vgx4], { z0.s - z3.s }, z0.s[0] + FMLS ZA.S[W8, 0, VGX4], { Z0.S - Z3.S }, Z0.S[0] + fmls za.s[w11, 0], { z0.s - z3.s }, z0.s[0] + fmls za.s[w8, 7], { z0.s - z3.s }, z0.s[0] + fmls za.s[w8, 0], { z28.s - z31.s }, z0.s[0] + fmls za.s[w8, 0], { z0.s - z3.s }, z15.s[0] + fmls za.s[w8, 0], { z0.s - z3.s }, z0.s[3] + fmls za.s[w10, 4], { z4.s - z7.s }, z9.s[1] + + fmls za.s[w8, 0], { z0.s - z1.s }, z0.s + fmls za.s[w8, 0, vgx2], { z0.s - z1.s }, z0.s + FMLS ZA.s[W8, 0, VGx2], { Z0.s - Z1.s }, Z0.s + FMLS ZA.S[W8, 0, VGX2], { Z0.S - Z1.S }, Z0.S + fmls za.s[w11, 0], { z0.s - z1.s }, z0.s + fmls za.s[w8, 7], { z0.s - z1.s }, z0.s + fmls za.s[w8, 0], { z30.s - z31.s }, z0.s + fmls za.s[w8, 0], { z31.s, z0.s }, z0.s + fmls za.s[w8, 0], { z31.s - z0.s }, z0.s + fmls za.s[w8, 0], { z0.s - z1.s }, z15.s + fmls za.s[w9, 5], { z9.s - z10.s }, z6.s + + fmls za.s[w8, 0], { z0.s - z3.s }, z0.s + fmls za.s[w8, 0, vgx4], { z0.s - z3.s }, z0.s + FMLS ZA.s[W8, 0, VGx4], { Z0.s - Z3.s }, Z0.s + FMLS ZA.S[W8, 0, VGX4], { Z0.S - Z3.S }, Z0.S + fmls za.s[w11, 0], { z0.s - z3.s }, z0.s + fmls za.s[w8, 7], { z0.s - z3.s }, z0.s + fmls za.s[w8, 0], { z28.s - z31.s }, z0.s + fmls za.s[w8, 0], { z31.s, z0.s, z1.s, z2.s }, z0.s + fmls za.s[w8, 0], { z31.s - z2.s }, z0.s + fmls za.s[w8, 0], { z0.s - z3.s }, z15.s + fmls za.s[w11, 2], { z23.s - z26.s }, z13.s + + fmls za.s[w8, 0], { z0.s - z1.s }, { z0.s - z1.s } + fmls za.s[w8, 0, vgx2], { z0.s - z1.s }, { z0.s - z1.s } + FMLS ZA.s[W8, 0, VGx2], { Z0.s - Z1.s }, { Z0.s - Z1.s } + FMLS ZA.S[W8, 0, VGX2], { Z0.S - Z1.S }, { Z0.S - Z1.S } + fmls za.s[w11, 0], { z0.s - z1.s }, { z0.s - z1.s } + fmls za.s[w8, 7], { z0.s - z1.s }, { z0.s - z1.s } + fmls za.s[w8, 0], { z30.s - z31.s }, { z0.s - z1.s } + fmls za.s[w8, 0], { z0.s - z1.s }, { z30.s - z31.s } + fmls za.s[w10, 1], { z22.s - z23.s }, { z18.s - z19.s } + + fmls za.s[w8, 0], { z0.s - z3.s }, { z0.s - z3.s } + fmls za.s[w8, 0, vgx4], { z0.s - z3.s }, { z0.s - z3.s } + FMLS ZA.s[W8, 0, VGx4], { Z0.s - Z3.s }, { Z0.s - Z3.s } + FMLS ZA.S[W8, 0, VGX4], { Z0.S - Z3.S }, { Z0.S - Z3.S } + fmls za.s[w11, 0], { z0.s - z3.s }, { z0.s - z3.s } + fmls za.s[w8, 7], { z0.s - z3.s }, { z0.s - z3.s } + fmls za.s[w8, 0], { z28.s - z31.s }, { z0.s - z3.s } + fmls za.s[w8, 0], { z0.s - z3.s }, { z28.s - z31.s } + fmls za.s[w11, 3], { z16.s - z19.s }, { z24.s - z27.s } diff --git a/gas/testsuite/gas/aarch64/sme2-f64f64-2-invalid.d b/gas/testsuite/gas/aarch64/sme2-f64f64-2-invalid.d new file mode 100644 index 00000000000..e2e4a7a7607 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-f64f64-2-invalid.d @@ -0,0 +1,3 @@ +#as: -march=armv8-a +#source: sme2-f64f64-2-invalid.s +#error_output: sme2-f64f64-2-invalid.l diff --git a/gas/testsuite/gas/aarch64/sme2-f64f64-2-invalid.l b/gas/testsuite/gas/aarch64/sme2-f64f64-2-invalid.l new file mode 100644 index 00000000000..97b0db12d6c --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-f64f64-2-invalid.l @@ -0,0 +1,98 @@ +[^ :]+: Assembler messages: +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.d\[w7,0\],{z0\.d-z1\.d},z0\.d\[0\]' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.d\[w12,0\],{z0\.d-z1\.d},z0\.d\[0\]' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.d\[w8,-1\],{z0\.d-z1\.d},z0\.d\[0\]' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.d\[w8,8\],{z0\.d-z1\.d},z0\.d\[0\]' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `fmla za\.d\[w8,0,vgx4\],{z0\.d-z1\.d},z0\.d\[0\]' +[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `fmla za\.d\[w8,0\],{z0\.d-z2\.d},z0\.d\[0\]' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\.d\[w8,0\],{z1\.d-z2\.d},z0\.d\[0\]' +[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z1\.d},z16\.d\[0\]' +[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z1\.d},z0\.d\[-1\]' +[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z1\.d},z0\.d\[2\]' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.d\[w7,0\],{z0\.d-z3\.d},z0\.d\[0\]' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.d\[w12,0\],{z0\.d-z3\.d},z0\.d\[0\]' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.d\[w8,-1\],{z0\.d-z3\.d},z0\.d\[0\]' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.d\[w8,8\],{z0\.d-z3\.d},z0\.d\[0\]' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `fmla za\.d\[w8,0,vgx2\],{z0\.d-z3\.d},z0\.d\[0\]' +[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 2 -- `fmla za\.d\[w8,0\],{z0\.d-z4\.d},z0\.d\[0\]' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\.d\[w8,0\],{z1\.d-z4\.d},z0\.d\[0\]' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\.d\[w8,0\],{z2\.d-z5\.d},z0\.d\[0\]' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\.d\[w8,0\],{z3\.d-z6\.d},z0\.d\[0\]' +[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z3\.d},z16\.d\[0\]' +[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z3\.d},z0\.d\[-1\]' +[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z3\.d},z0\.d\[2\]' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.d\[w0,0\],{z0\.d-z1\.d},z0\.d' +[^ :]+:[0-9]+: Error: expected a 32-bit selection register at operand 1 -- `fmla za\.d\[w31,0\],{z0\.d-z1\.d},z0\.d' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.d\[w8,1<<63\],{z0\.d-z1\.d},z0\.d' +[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z1\.d},z31\.d' +[^ :]+:[0-9]+: Error: the last offset is equal to the first offset at operand 1 -- `fmla za\.d\[w8,0:0\],{z0\.d-z1\.d},z0\.d' +[^ :]+:[0-9]+: Error: the last offset is less than the first offset at operand 1 -- `fmla za\.d\[w8,0:-1\],{z0\.d-z1\.d},z0\.d' +[^ :]+:[0-9]+: Error: expected a single offset rather than a range at operand 1 -- `fmla za\.d\[w8,0:1\],{z0\.d-z1\.d},z0\.d' +[^ :]+:[0-9]+: Error: expected a single offset rather than a range at operand 1 -- `fmla za\.d\[w8,0:100\],{z0\.d-z1\.d},z0\.d' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.d\[w7,0\],{z0\.d-z1\.d},z0\.d' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.d\[w12,0\],{z0\.d-z1\.d},z0\.d' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.d\[w8,-1\],{z0\.d-z1\.d},z0\.d' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.d\[w8,8\],{z0\.d-z1\.d},z0\.d' +[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z1\.d},z16\.d' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.d\[w7,0\],{z0\.d-z3\.d},z0\.d' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.d\[w12,0\],{z0\.d-z3\.d},z0\.d' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.d\[w8,-1\],{z0\.d-z3\.d},z0\.d' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.d\[w8,8\],{z0\.d-z3\.d},z0\.d' +[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z3\.d},z16\.d' +[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `fmla za\.d\[w8,0\],{z0\.d-z2\.d},z0\.d' +[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 2 -- `fmla za\.d\[w8,0\],{z0\.d-z4\.d},z0\.d' +[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `fmla za\.d\[w8,0\],{z0\.d,z1\.d,z2\.d},z0\.d' +[^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `fmla za\.d\[w8,0\],{z0\.d,z1\.d,z5\.d},z0\.d' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `fmla za\.d\[w8,0,vgx4\],{z0\.d-z1\.d},z0\.d' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `fmla za\.d\[w8,0,vgx2\],{z0\.d-z3\.d},z0\.d' +[^ :]+:[0-9]+: Error: operand mismatch -- `fmla za\[w8,0\],{z0\.d-z1\.d},z0\.d' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: fmla za\.d\[w8, 0\], {z0\.d-z1\.d}, z0\.d +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: fmla za\.s\[w8, 0\], {z0\.s-z1\.s}, z0\.s +[^ :]+:[0-9]+: Error: missing type suffix at operand 2 -- `fmla za\.d\[w8,0\],{z0-z1},z0\.d' +[^ :]+:[0-9]+: Error: operand mismatch -- `fmla za\.d\[w8,0\],{z0\.d-z1\.d},z0' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: fmla za\.d\[w8, 0\], {z0\.d-z1\.d}, z0\.d +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: fmla za\.s\[w8, 0\], {z0\.s-z1\.s}, z0\.s +[^ :]+:[0-9]+: Error: operand mismatch -- `fmla za\[w8,0\],{z0\.d-z1\.d},z0' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: fmla za\.d\[w8, 0\], {z0\.d-z1\.d}, z0\.d +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: fmla za\.s\[w8, 0\], {z0\.s-z1\.s}, z0\.s +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.d\[w7,0\],{z0\.d-z1\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.d\[w12,0\],{z0\.d-z1\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.d\[w8,-1\],{z0\.d-z1\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.d\[w8,8\],{z0\.d-z1\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\.d\[w8,0\],{z1\.d-z2\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z1\.d},{z15\.d-z16\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z1\.d},{z31\.d,z0\.d}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.d\[w7,0\],{z0\.d-z3\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.d\[w12,0\],{z0\.d-z3\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.d\[w8,-1\],{z0\.d-z3\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.d\[w8,8\],{z0\.d-z3\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\.d\[w8,0\],{z1\.d-z4\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\.d\[w8,0\],{z2\.d-z5\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\.d\[w8,0\],{z3\.d-z6\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z3\.d},{z15\.d-z18\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z3\.d},{z29\.d,z30\.d,z31\.d,z0\.d}' +[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `fmla za\.d\[w8,0\],{z0\.d-z2\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z3\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z1\.d},{z0\.d-z2\.d}' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z1\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z1\.d},{z0\.d-z4\.d}' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `fmla za\.d\[w8,0,vgx4\],{z0\.d-z1\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 3 -- `fmla za\.d\[w8,0,vgx4\],{z0\.d-z3\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `fmla za\.d\[w8,0,vgx2\],{z0\.d-z1\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `fmla za\.d\[w8,0,vgx2\],{z0\.d-z3\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: operand mismatch -- `fmla za\[w8,0\],{z0\.d-z1\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: fmla za\.d\[w8, 0\], {z0\.d-z1\.d}, {z0\.d-z1\.d} +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: fmla za\.s\[w8, 0\], {z0\.s-z1\.s}, {z0\.s-z1\.s} +[^ :]+:[0-9]+: Error: operand mismatch -- `fmla za\[w8,0\],{z0\.d-z3\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: fmla za\.d\[w8, 0\], {z0\.d-z3\.d}, {z0\.d-z3\.d} +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: fmla za\.s\[w8, 0\], {z0\.s-z3\.s}, {z0\.s-z3\.s} diff --git a/gas/testsuite/gas/aarch64/sme2-f64f64-2-invalid.s b/gas/testsuite/gas/aarch64/sme2-f64f64-2-invalid.s new file mode 100644 index 00000000000..9839bfe8011 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-f64f64-2-invalid.s @@ -0,0 +1,87 @@ + fmla za.d[w7, 0], { z0.d - z1.d }, z0.d[0] + fmla za.d[w12, 0], { z0.d - z1.d }, z0.d[0] + fmla za.d[w8, -1], { z0.d - z1.d }, z0.d[0] + fmla za.d[w8, 8], { z0.d - z1.d }, z0.d[0] + fmla za.d[w8, 0, vgx4], { z0.d - z1.d }, z0.d[0] + fmla za.d[w8, 0], { z0.d - z2.d }, z0.d[0] + fmla za.d[w8, 0], { z1.d - z2.d }, z0.d[0] + fmla za.d[w8, 0], { z0.d - z1.d }, z16.d[0] + fmla za.d[w8, 0], { z0.d - z1.d }, z0.d[-1] + fmla za.d[w8, 0], { z0.d - z1.d }, z0.d[2] + + fmla za.d[w7, 0], { z0.d - z3.d }, z0.d[0] + fmla za.d[w12, 0], { z0.d - z3.d }, z0.d[0] + fmla za.d[w8, -1], { z0.d - z3.d }, z0.d[0] + fmla za.d[w8, 8], { z0.d - z3.d }, z0.d[0] + fmla za.d[w8, 0, vgx2], { z0.d - z3.d }, z0.d[0] + fmla za.d[w8, 0], { z0.d - z4.d }, z0.d[0] + fmla za.d[w8, 0], { z1.d - z4.d }, z0.d[0] + fmla za.d[w8, 0], { z2.d - z5.d }, z0.d[0] + fmla za.d[w8, 0], { z3.d - z6.d }, z0.d[0] + fmla za.d[w8, 0], { z0.d - z3.d }, z16.d[0] + fmla za.d[w8, 0], { z0.d - z3.d }, z0.d[-1] + fmla za.d[w8, 0], { z0.d - z3.d }, z0.d[2] + + fmla za.d[w0, 0], { z0.d - z1.d }, z0.d + fmla za.d[w31, 0], { z0.d - z1.d }, z0.d + fmla za.d[w8, 1<<63], { z0.d - z1.d }, z0.d + fmla za.d[w8, 0], { z0.d - z1.d }, z31.d + fmla za.d[w8, 0:0], { z0.d - z1.d }, z0.d + fmla za.d[w8, 0:-1], { z0.d - z1.d }, z0.d + fmla za.d[w8, 0:1], { z0.d - z1.d }, z0.d + fmla za.d[w8, 0:100], { z0.d - z1.d }, z0.d + + fmla za.d[w7, 0], { z0.d - z1.d }, z0.d + fmla za.d[w12, 0], { z0.d - z1.d }, z0.d + fmla za.d[w8, -1], { z0.d - z1.d }, z0.d + fmla za.d[w8, 8], { z0.d - z1.d }, z0.d + fmla za.d[w8, 0], { z0.d - z1.d }, z16.d + + fmla za.d[w7, 0], { z0.d - z3.d }, z0.d + fmla za.d[w12, 0], { z0.d - z3.d }, z0.d + fmla za.d[w8, -1], { z0.d - z3.d }, z0.d + fmla za.d[w8, 8], { z0.d - z3.d }, z0.d + fmla za.d[w8, 0], { z0.d - z3.d }, z16.d + + fmla za.d[w8, 0], { z0.d - z2.d }, z0.d + fmla za.d[w8, 0], { z0.d - z4.d }, z0.d + fmla za.d[w8, 0], { z0.d, z1.d, z2.d }, z0.d + fmla za.d[w8, 0], { z0.d, z1.d, z5.d }, z0.d + + fmla za.d[w8, 0, vgx4], { z0.d - z1.d }, z0.d + fmla za.d[w8, 0, vgx2], { z0.d - z3.d }, z0.d + fmla za[w8, 0], { z0.d - z1.d }, z0.d + fmla za.d[w8, 0], { z0 - z1 }, z0.d + fmla za.d[w8, 0], { z0.d - z1.d }, z0 + fmla za[w8, 0], { z0.d - z1.d }, z0 + + fmla za.d[w7, 0], { z0.d - z1.d }, { z0.d - z1.d } + fmla za.d[w12, 0], { z0.d - z1.d }, { z0.d - z1.d } + fmla za.d[w8, -1], { z0.d - z1.d }, { z0.d - z1.d } + fmla za.d[w8, 8], { z0.d - z1.d }, { z0.d - z1.d } + fmla za.d[w8, 0], { z1.d - z2.d }, { z0.d - z1.d } + fmla za.d[w8, 0], { z0.d - z1.d }, { z15.d - z16.d } + fmla za.d[w8, 0], { z0.d - z1.d }, { z31.d, z0.d } + + fmla za.d[w7, 0], { z0.d - z3.d }, { z0.d - z3.d } + fmla za.d[w12, 0], { z0.d - z3.d }, { z0.d - z3.d } + fmla za.d[w8, -1], { z0.d - z3.d }, { z0.d - z3.d } + fmla za.d[w8, 8], { z0.d - z3.d }, { z0.d - z3.d } + fmla za.d[w8, 0], { z1.d - z4.d }, { z0.d - z3.d } + fmla za.d[w8, 0], { z2.d - z5.d }, { z0.d - z3.d } + fmla za.d[w8, 0], { z3.d - z6.d }, { z0.d - z3.d } + fmla za.d[w8, 0], { z0.d - z3.d }, { z15.d - z18.d } + fmla za.d[w8, 0], { z0.d - z3.d }, { z29.d, z30.d, z31.d, z0.d } + + fmla za.d[w8, 0], { z0.d - z2.d }, { z0.d - z1.d } + fmla za.d[w8, 0], { z0.d - z3.d }, { z0.d - z1.d } + fmla za.d[w8, 0], { z0.d - z1.d }, { z0.d - z2.d } + fmla za.d[w8, 0], { z0.d - z1.d }, { z0.d - z3.d } + fmla za.d[w8, 0], { z0.d - z1.d }, { z0.d - z4.d } + + fmla za.d[w8, 0, vgx4], { z0.d - z1.d }, { z0.d - z3.d } + fmla za.d[w8, 0, vgx4], { z0.d - z3.d }, { z0.d - z1.d } + fmla za.d[w8, 0, vgx2], { z0.d - z1.d }, { z0.d - z3.d } + fmla za.d[w8, 0, vgx2], { z0.d - z3.d }, { z0.d - z1.d } + fmla za[w8, 0], { z0.d - z1.d }, { z0.d - z1.d } + fmla za[w8, 0], { z0.d - z3.d }, { z0.d - z3.d } diff --git a/gas/testsuite/gas/aarch64/sme2-f64f64-2-noarch.d b/gas/testsuite/gas/aarch64/sme2-f64f64-2-noarch.d new file mode 100644 index 00000000000..23c66a9aaee --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-f64f64-2-noarch.d @@ -0,0 +1,3 @@ +#as: -march=armv8-a+sme2 +#source: sme2-f64f64-2.s +#error_output: sme2-f64f64-2-noarch.l diff --git a/gas/testsuite/gas/aarch64/sme2-f64f64-2-noarch.l b/gas/testsuite/gas/aarch64/sme2-f64f64-2-noarch.l new file mode 100644 index 00000000000..5ab290d4080 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-f64f64-2-noarch.l @@ -0,0 +1,117 @@ +[^ :]+: Assembler messages: +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z0\.d-z1\.d},z0\.d\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0,vgx2\],{z0\.d-z1\.d},z0\.d\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.d\[W8,0,VGx2\],{Z0\.d-Z1\.d},Z0\.d\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w11,0\],{z0\.d-z1\.d},z0\.d\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,7\],{z0\.d-z1\.d},z0\.d\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z30\.d-z31\.d},z0\.d\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z0\.d-z1\.d},z15\.d\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z0\.d-z1\.d},z0\.d\[1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w10,2\],{z6\.d-z7\.d},z5\.d\[1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z0\.d-z3\.d},z0\.d\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0,vgx4\],{z0\.d-z3\.d},z0\.d\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.D\[W8,0,VGX4\],{Z0\.D-Z3\.D},Z0\.D\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w11,0\],{z0\.d-z3\.d},z0\.d\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,7\],{z0\.d-z3\.d},z0\.d\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z28\.d-z31\.d},z0\.d\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z0\.d-z3\.d},z15\.d\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z0\.d-z3\.d},z0\.d\[1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w9,3\],{z8\.d-z11\.d},z14\.d\[1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z0\.d-z1\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0,vgx2\],{z0\.d-z1\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.d\[W8,0,VGx2\],{Z0\.d-Z1\.d},Z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.D\[W8,0,VGX2\],{Z0\.D-Z1\.D},Z0\.D' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w11,0\],{z0\.d-z1\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,7\],{z0\.d-z1\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z30\.d-z31\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z31\.d,z0\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z31\.d-z0\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z0\.d-z1\.d},z15\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w9,5\],{z9\.d-z10\.d},z6\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z0\.d-z3\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0,vgx4\],{z0\.d-z3\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.d\[W8,0,VGx4\],{Z0\.d-Z3\.d},Z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.D\[W8,0,VGX4\],{Z0\.D-Z3\.D},Z0\.D' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w11,0\],{z0\.d-z3\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,7\],{z0\.d-z3\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z28\.d-z31\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z31\.d,z0\.d,z1\.d,z2\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z31\.d-z2\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z0\.d-z3\.d},z15\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w11,2\],{z23\.d-z26\.d},z13\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z0\.d-z1\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0,vgx2\],{z0\.d-z1\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.d\[W8,0,VGx2\],{Z0\.d-Z1\.d},{Z0\.d-Z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.D\[W8,0,VGX2\],{Z0\.D-Z1\.D},{Z0\.D-Z1\.D}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w11,0\],{z0\.d-z1\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,7\],{z0\.d-z1\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z30\.d-z31\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z0\.d-z1\.d},{z30\.d-z31\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w10,1\],{z22\.d-z23\.d},{z18\.d-z19\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z0\.d-z3\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0,vgx4\],{z0\.d-z3\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.d\[W8,0,VGx4\],{Z0\.d-Z3\.d},{Z0\.d-Z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.D\[W8,0,VGX4\],{Z0\.D-Z3\.D},{Z0\.D-Z3\.D}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w11,0\],{z0\.d-z3\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,7\],{z0\.d-z3\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z28\.d-z31\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z0\.d-z3\.d},{z28\.d-z31\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w11,3\],{z16\.d-z19\.d},{z24\.d-z27\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z0\.d-z1\.d},z0\.d\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0,vgx2\],{z0\.d-z1\.d},z0\.d\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.d\[W8,0,VGx2\],{Z0\.d-Z1\.d},Z0\.d\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w11,0\],{z0\.d-z1\.d},z0\.d\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,7\],{z0\.d-z1\.d},z0\.d\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z30\.d-z31\.d},z0\.d\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z0\.d-z1\.d},z15\.d\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z0\.d-z1\.d},z0\.d\[1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w10,2\],{z6\.d-z7\.d},z5\.d\[1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z0\.d-z3\.d},z0\.d\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0,vgx4\],{z0\.d-z3\.d},z0\.d\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.D\[W8,0,VGX4\],{Z0\.D-Z3\.D},Z0\.D\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w11,0\],{z0\.d-z3\.d},z0\.d\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,7\],{z0\.d-z3\.d},z0\.d\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z28\.d-z31\.d},z0\.d\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z0\.d-z3\.d},z15\.d\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z0\.d-z3\.d},z0\.d\[1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w9,3\],{z8\.d-z11\.d},z14\.d\[1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z0\.d-z1\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0,vgx2\],{z0\.d-z1\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.d\[W8,0,VGx2\],{Z0\.d-Z1\.d},Z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.D\[W8,0,VGX2\],{Z0\.D-Z1\.D},Z0\.D' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w11,0\],{z0\.d-z1\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,7\],{z0\.d-z1\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z30\.d-z31\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z31\.d,z0\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z31\.d-z0\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z0\.d-z1\.d},z15\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w9,5\],{z9\.d-z10\.d},z6\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z0\.d-z3\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0,vgx4\],{z0\.d-z3\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.d\[W8,0,VGx4\],{Z0\.d-Z3\.d},Z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.D\[W8,0,VGX4\],{Z0\.D-Z3\.D},Z0\.D' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w11,0\],{z0\.d-z3\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,7\],{z0\.d-z3\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z28\.d-z31\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z31\.d,z0\.d,z1\.d,z2\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z31\.d-z2\.d},z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z0\.d-z3\.d},z15\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w11,2\],{z23\.d-z26\.d},z13\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z0\.d-z1\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0,vgx2\],{z0\.d-z1\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.d\[W8,0,VGx2\],{Z0\.d-Z1\.d},{Z0\.d-Z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.D\[W8,0,VGX2\],{Z0\.D-Z1\.D},{Z0\.D-Z1\.D}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w11,0\],{z0\.d-z1\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,7\],{z0\.d-z1\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z30\.d-z31\.d},{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z0\.d-z1\.d},{z30\.d-z31\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w10,1\],{z22\.d-z23\.d},{z18\.d-z19\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z0\.d-z3\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0,vgx4\],{z0\.d-z3\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.d\[W8,0,VGx4\],{Z0\.d-Z3\.d},{Z0\.d-Z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.D\[W8,0,VGX4\],{Z0\.D-Z3\.D},{Z0\.D-Z3\.D}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w11,0\],{z0\.d-z3\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,7\],{z0\.d-z3\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z28\.d-z31\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z0\.d-z3\.d},{z28\.d-z31\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w11,3\],{z16\.d-z19\.d},{z24\.d-z27\.d}' diff --git a/gas/testsuite/gas/aarch64/sme2-f64f64-2.d b/gas/testsuite/gas/aarch64/sme2-f64f64-2.d new file mode 100644 index 00000000000..dbc8d65d2c9 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-f64f64-2.d @@ -0,0 +1,125 @@ +#as: -march=armv8-a+sme2+sme-f64f64 +#objdump: -dr + +[^:]+: file format .* + + +[^:]+: + +[^:]+: +[^:]+: c1d00000 fmla za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d\[0\] +[^:]+: c1d00000 fmla za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d\[0\] +[^:]+: c1d00000 fmla za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d\[0\] +[^:]+: c1d06000 fmla za\.d\[w11, 0, vgx2\], {z0\.d-z1\.d}, z0\.d\[0\] +[^:]+: c1d00007 fmla za\.d\[w8, 7, vgx2\], {z0\.d-z1\.d}, z0\.d\[0\] +[^:]+: c1d003c0 fmla za\.d\[w8, 0, vgx2\], {z30\.d-z31\.d}, z0\.d\[0\] +[^:]+: c1df0000 fmla za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z15\.d\[0\] +[^:]+: c1d00400 fmla za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d\[1\] +[^:]+: c1d544c2 fmla za\.d\[w10, 2, vgx2\], {z6\.d-z7\.d}, z5\.d\[1\] +[^:]+: c1d08000 fmla za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d\[0\] +[^:]+: c1d08000 fmla za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d\[0\] +[^:]+: c1d08000 fmla za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d\[0\] +[^:]+: c1d0e000 fmla za\.d\[w11, 0, vgx4\], {z0\.d-z3\.d}, z0\.d\[0\] +[^:]+: c1d08007 fmla za\.d\[w8, 7, vgx4\], {z0\.d-z3\.d}, z0\.d\[0\] +[^:]+: c1d08380 fmla za\.d\[w8, 0, vgx4\], {z28\.d-z31\.d}, z0\.d\[0\] +[^:]+: c1df8000 fmla za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z15\.d\[0\] +[^:]+: c1d08400 fmla za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d\[1\] +[^:]+: c1dea503 fmla za\.d\[w9, 3, vgx4\], {z8\.d-z11\.d}, z14\.d\[1\] +[^:]+: c1601800 fmla za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d +[^:]+: c1601800 fmla za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d +[^:]+: c1601800 fmla za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d +[^:]+: c1601800 fmla za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d +[^:]+: c1607800 fmla za\.d\[w11, 0, vgx2\], {z0\.d-z1\.d}, z0\.d +[^:]+: c1601807 fmla za\.d\[w8, 7, vgx2\], {z0\.d-z1\.d}, z0\.d +[^:]+: c1601bc0 fmla za\.d\[w8, 0, vgx2\], {z30\.d-z31\.d}, z0\.d +[^:]+: c1601be0 fmla za\.d\[w8, 0, vgx2\], {z31\.d-z0\.d}, z0\.d +[^:]+: c1601be0 fmla za\.d\[w8, 0, vgx2\], {z31\.d-z0\.d}, z0\.d +[^:]+: c16f1800 fmla za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z15\.d +[^:]+: c1663925 fmla za\.d\[w9, 5, vgx2\], {z9\.d-z10\.d}, z6\.d +[^:]+: c1701800 fmla za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d +[^:]+: c1701800 fmla za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d +[^:]+: c1701800 fmla za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d +[^:]+: c1701800 fmla za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d +[^:]+: c1707800 fmla za\.d\[w11, 0, vgx4\], {z0\.d-z3\.d}, z0\.d +[^:]+: c1701807 fmla za\.d\[w8, 7, vgx4\], {z0\.d-z3\.d}, z0\.d +[^:]+: c1701b80 fmla za\.d\[w8, 0, vgx4\], {z28\.d-z31\.d}, z0\.d +[^:]+: c1701be0 fmla za\.d\[w8, 0, vgx4\], {z31\.d-z2\.d}, z0\.d +[^:]+: c1701be0 fmla za\.d\[w8, 0, vgx4\], {z31\.d-z2\.d}, z0\.d +[^:]+: c17f1800 fmla za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z15\.d +[^:]+: c17d7ae2 fmla za\.d\[w11, 2, vgx4\], {z23\.d-z26\.d}, z13\.d +[^:]+: c1e01800 fmla za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d} +[^:]+: c1e01800 fmla za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d} +[^:]+: c1e01800 fmla za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d} +[^:]+: c1e01800 fmla za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d} +[^:]+: c1e07800 fmla za\.d\[w11, 0, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d} +[^:]+: c1e01807 fmla za\.d\[w8, 7, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d} +[^:]+: c1e01bc0 fmla za\.d\[w8, 0, vgx2\], {z30\.d-z31\.d}, {z0\.d-z1\.d} +[^:]+: c1fe1800 fmla za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, {z30\.d-z31\.d} +[^:]+: c1f25ac1 fmla za\.d\[w10, 1, vgx2\], {z22\.d-z23\.d}, {z18\.d-z19\.d} +[^:]+: c1e11800 fmla za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d} +[^:]+: c1e11800 fmla za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d} +[^:]+: c1e11800 fmla za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d} +[^:]+: c1e11800 fmla za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d} +[^:]+: c1e17800 fmla za\.d\[w11, 0, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d} +[^:]+: c1e11807 fmla za\.d\[w8, 7, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d} +[^:]+: c1e11b80 fmla za\.d\[w8, 0, vgx4\], {z28\.d-z31\.d}, {z0\.d-z3\.d} +[^:]+: c1fd1800 fmla za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, {z28\.d-z31\.d} +[^:]+: c1f97a03 fmla za\.d\[w11, 3, vgx4\], {z16\.d-z19\.d}, {z24\.d-z27\.d} +[^:]+: c1d00010 fmls za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d\[0\] +[^:]+: c1d00010 fmls za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d\[0\] +[^:]+: c1d00010 fmls za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d\[0\] +[^:]+: c1d06010 fmls za\.d\[w11, 0, vgx2\], {z0\.d-z1\.d}, z0\.d\[0\] +[^:]+: c1d00017 fmls za\.d\[w8, 7, vgx2\], {z0\.d-z1\.d}, z0\.d\[0\] +[^:]+: c1d003d0 fmls za\.d\[w8, 0, vgx2\], {z30\.d-z31\.d}, z0\.d\[0\] +[^:]+: c1df0010 fmls za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z15\.d\[0\] +[^:]+: c1d00410 fmls za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d\[1\] +[^:]+: c1d544d2 fmls za\.d\[w10, 2, vgx2\], {z6\.d-z7\.d}, z5\.d\[1\] +[^:]+: c1d08010 fmls za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d\[0\] +[^:]+: c1d08010 fmls za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d\[0\] +[^:]+: c1d08010 fmls za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d\[0\] +[^:]+: c1d0e010 fmls za\.d\[w11, 0, vgx4\], {z0\.d-z3\.d}, z0\.d\[0\] +[^:]+: c1d08017 fmls za\.d\[w8, 7, vgx4\], {z0\.d-z3\.d}, z0\.d\[0\] +[^:]+: c1d08390 fmls za\.d\[w8, 0, vgx4\], {z28\.d-z31\.d}, z0\.d\[0\] +[^:]+: c1df8010 fmls za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z15\.d\[0\] +[^:]+: c1d08410 fmls za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d\[1\] +[^:]+: c1dea513 fmls za\.d\[w9, 3, vgx4\], {z8\.d-z11\.d}, z14\.d\[1\] +[^:]+: c1601808 fmls za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d +[^:]+: c1601808 fmls za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d +[^:]+: c1601808 fmls za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d +[^:]+: c1601808 fmls za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d +[^:]+: c1607808 fmls za\.d\[w11, 0, vgx2\], {z0\.d-z1\.d}, z0\.d +[^:]+: c160180f fmls za\.d\[w8, 7, vgx2\], {z0\.d-z1\.d}, z0\.d +[^:]+: c1601bc8 fmls za\.d\[w8, 0, vgx2\], {z30\.d-z31\.d}, z0\.d +[^:]+: c1601be8 fmls za\.d\[w8, 0, vgx2\], {z31\.d-z0\.d}, z0\.d +[^:]+: c1601be8 fmls za\.d\[w8, 0, vgx2\], {z31\.d-z0\.d}, z0\.d +[^:]+: c16f1808 fmls za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z15\.d +[^:]+: c166392d fmls za\.d\[w9, 5, vgx2\], {z9\.d-z10\.d}, z6\.d +[^:]+: c1701808 fmls za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d +[^:]+: c1701808 fmls za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d +[^:]+: c1701808 fmls za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d +[^:]+: c1701808 fmls za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d +[^:]+: c1707808 fmls za\.d\[w11, 0, vgx4\], {z0\.d-z3\.d}, z0\.d +[^:]+: c170180f fmls za\.d\[w8, 7, vgx4\], {z0\.d-z3\.d}, z0\.d +[^:]+: c1701b88 fmls za\.d\[w8, 0, vgx4\], {z28\.d-z31\.d}, z0\.d +[^:]+: c1701be8 fmls za\.d\[w8, 0, vgx4\], {z31\.d-z2\.d}, z0\.d +[^:]+: c1701be8 fmls za\.d\[w8, 0, vgx4\], {z31\.d-z2\.d}, z0\.d +[^:]+: c17f1808 fmls za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z15\.d +[^:]+: c17d7aea fmls za\.d\[w11, 2, vgx4\], {z23\.d-z26\.d}, z13\.d +[^:]+: c1e01808 fmls za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d} +[^:]+: c1e01808 fmls za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d} +[^:]+: c1e01808 fmls za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d} +[^:]+: c1e01808 fmls za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d} +[^:]+: c1e07808 fmls za\.d\[w11, 0, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d} +[^:]+: c1e0180f fmls za\.d\[w8, 7, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d} +[^:]+: c1e01bc8 fmls za\.d\[w8, 0, vgx2\], {z30\.d-z31\.d}, {z0\.d-z1\.d} +[^:]+: c1fe1808 fmls za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, {z30\.d-z31\.d} +[^:]+: c1f25ac9 fmls za\.d\[w10, 1, vgx2\], {z22\.d-z23\.d}, {z18\.d-z19\.d} +[^:]+: c1e11808 fmls za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d} +[^:]+: c1e11808 fmls za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d} +[^:]+: c1e11808 fmls za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d} +[^:]+: c1e11808 fmls za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d} +[^:]+: c1e17808 fmls za\.d\[w11, 0, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d} +[^:]+: c1e1180f fmls za\.d\[w8, 7, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d} +[^:]+: c1e11b88 fmls za\.d\[w8, 0, vgx4\], {z28\.d-z31\.d}, {z0\.d-z3\.d} +[^:]+: c1fd1808 fmls za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, {z28\.d-z31\.d} +[^:]+: c1f97a0b fmls za\.d\[w11, 3, vgx4\], {z16\.d-z19\.d}, {z24\.d-z27\.d} diff --git a/gas/testsuite/gas/aarch64/sme2-f64f64-2.s b/gas/testsuite/gas/aarch64/sme2-f64f64-2.s new file mode 100644 index 00000000000..005db427db7 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-f64f64-2.s @@ -0,0 +1,127 @@ + fmla za.d[w8, 0], { z0.d - z1.d }, z0.d[0] + fmla za.d[w8, 0, vgx2], { z0.d - z1.d }, z0.d[0] + FMLA ZA.d[W8, 0, VGx2], { Z0.d - Z1.d }, Z0.d[0] + fmla za.d[w11, 0], { z0.d - z1.d }, z0.d[0] + fmla za.d[w8, 7], { z0.d - z1.d }, z0.d[0] + fmla za.d[w8, 0], { z30.d - z31.d }, z0.d[0] + fmla za.d[w8, 0], { z0.d - z1.d }, z15.d[0] + fmla za.d[w8, 0], { z0.d - z1.d }, z0.d[1] + fmla za.d[w10, 2], { z6.d - z7.d }, z5.d[1] + + fmla za.d[w8, 0], { z0.d - z3.d }, z0.d[0] + fmla za.d[w8, 0, vgx4], { z0.d - z3.d }, z0.d[0] + FMLA ZA.D[W8, 0, VGX4], { Z0.D - Z3.D }, Z0.D[0] + fmla za.d[w11, 0], { z0.d - z3.d }, z0.d[0] + fmla za.d[w8, 7], { z0.d - z3.d }, z0.d[0] + fmla za.d[w8, 0], { z28.d - z31.d }, z0.d[0] + fmla za.d[w8, 0], { z0.d - z3.d }, z15.d[0] + fmla za.d[w8, 0], { z0.d - z3.d }, z0.d[1] + fmla za.d[w9, 3], { z8.d - z11.d }, z14.d[1] + + fmla za.d[w8, 0], { z0.d - z1.d }, z0.d + fmla za.d[w8, 0, vgx2], { z0.d - z1.d }, z0.d + FMLA ZA.d[W8, 0, VGx2], { Z0.d - Z1.d }, Z0.d + FMLA ZA.D[W8, 0, VGX2], { Z0.D - Z1.D }, Z0.D + fmla za.d[w11, 0], { z0.d - z1.d }, z0.d + fmla za.d[w8, 7], { z0.d - z1.d }, z0.d + fmla za.d[w8, 0], { z30.d - z31.d }, z0.d + fmla za.d[w8, 0], { z31.d, z0.d }, z0.d + fmla za.d[w8, 0], { z31.d - z0.d }, z0.d + fmla za.d[w8, 0], { z0.d - z1.d }, z15.d + fmla za.d[w9, 5], { z9.d - z10.d }, z6.d + + fmla za.d[w8, 0], { z0.d - z3.d }, z0.d + fmla za.d[w8, 0, vgx4], { z0.d - z3.d }, z0.d + FMLA ZA.d[W8, 0, VGx4], { Z0.d - Z3.d }, Z0.d + FMLA ZA.D[W8, 0, VGX4], { Z0.D - Z3.D }, Z0.D + fmla za.d[w11, 0], { z0.d - z3.d }, z0.d + fmla za.d[w8, 7], { z0.d - z3.d }, z0.d + fmla za.d[w8, 0], { z28.d - z31.d }, z0.d + fmla za.d[w8, 0], { z31.d, z0.d, z1.d, z2.d }, z0.d + fmla za.d[w8, 0], { z31.d - z2.d }, z0.d + fmla za.d[w8, 0], { z0.d - z3.d }, z15.d + fmla za.d[w11, 2], { z23.d - z26.d }, z13.d + + fmla za.d[w8, 0], { z0.d - z1.d }, { z0.d - z1.d } + fmla za.d[w8, 0, vgx2], { z0.d - z1.d }, { z0.d - z1.d } + FMLA ZA.d[W8, 0, VGx2], { Z0.d - Z1.d }, { Z0.d - Z1.d } + FMLA ZA.D[W8, 0, VGX2], { Z0.D - Z1.D }, { Z0.D - Z1.D } + fmla za.d[w11, 0], { z0.d - z1.d }, { z0.d - z1.d } + fmla za.d[w8, 7], { z0.d - z1.d }, { z0.d - z1.d } + fmla za.d[w8, 0], { z30.d - z31.d }, { z0.d - z1.d } + fmla za.d[w8, 0], { z0.d - z1.d }, { z30.d - z31.d } + fmla za.d[w10, 1], { z22.d - z23.d }, { z18.d - z19.d } + + fmla za.d[w8, 0], { z0.d - z3.d }, { z0.d - z3.d } + fmla za.d[w8, 0, vgx4], { z0.d - z3.d }, { z0.d - z3.d } + FMLA ZA.d[W8, 0, VGx4], { Z0.d - Z3.d }, { Z0.d - Z3.d } + FMLA ZA.D[W8, 0, VGX4], { Z0.D - Z3.D }, { Z0.D - Z3.D } + fmla za.d[w11, 0], { z0.d - z3.d }, { z0.d - z3.d } + fmla za.d[w8, 7], { z0.d - z3.d }, { z0.d - z3.d } + fmla za.d[w8, 0], { z28.d - z31.d }, { z0.d - z3.d } + fmla za.d[w8, 0], { z0.d - z3.d }, { z28.d - z31.d } + fmla za.d[w11, 3], { z16.d - z19.d }, { z24.d - z27.d } + + fmls za.d[w8, 0], { z0.d - z1.d }, z0.d[0] + fmls za.d[w8, 0, vgx2], { z0.d - z1.d }, z0.d[0] + FMLS ZA.d[W8, 0, VGx2], { Z0.d - Z1.d }, Z0.d[0] + fmls za.d[w11, 0], { z0.d - z1.d }, z0.d[0] + fmls za.d[w8, 7], { z0.d - z1.d }, z0.d[0] + fmls za.d[w8, 0], { z30.d - z31.d }, z0.d[0] + fmls za.d[w8, 0], { z0.d - z1.d }, z15.d[0] + fmls za.d[w8, 0], { z0.d - z1.d }, z0.d[1] + fmls za.d[w10, 2], { z6.d - z7.d }, z5.d[1] + + fmls za.d[w8, 0], { z0.d - z3.d }, z0.d[0] + fmls za.d[w8, 0, vgx4], { z0.d - z3.d }, z0.d[0] + FMLS ZA.D[W8, 0, VGX4], { Z0.D - Z3.D }, Z0.D[0] + fmls za.d[w11, 0], { z0.d - z3.d }, z0.d[0] + fmls za.d[w8, 7], { z0.d - z3.d }, z0.d[0] + fmls za.d[w8, 0], { z28.d - z31.d }, z0.d[0] + fmls za.d[w8, 0], { z0.d - z3.d }, z15.d[0] + fmls za.d[w8, 0], { z0.d - z3.d }, z0.d[1] + fmls za.d[w9, 3], { z8.d - z11.d }, z14.d[1] + + fmls za.d[w8, 0], { z0.d - z1.d }, z0.d + fmls za.d[w8, 0, vgx2], { z0.d - z1.d }, z0.d + FMLS ZA.d[W8, 0, VGx2], { Z0.d - Z1.d }, Z0.d + FMLS ZA.D[W8, 0, VGX2], { Z0.D - Z1.D }, Z0.D + fmls za.d[w11, 0], { z0.d - z1.d }, z0.d + fmls za.d[w8, 7], { z0.d - z1.d }, z0.d + fmls za.d[w8, 0], { z30.d - z31.d }, z0.d + fmls za.d[w8, 0], { z31.d, z0.d }, z0.d + fmls za.d[w8, 0], { z31.d - z0.d }, z0.d + fmls za.d[w8, 0], { z0.d - z1.d }, z15.d + fmls za.d[w9, 5], { z9.d - z10.d }, z6.d + + fmls za.d[w8, 0], { z0.d - z3.d }, z0.d + fmls za.d[w8, 0, vgx4], { z0.d - z3.d }, z0.d + FMLS ZA.d[W8, 0, VGx4], { Z0.d - Z3.d }, Z0.d + FMLS ZA.D[W8, 0, VGX4], { Z0.D - Z3.D }, Z0.D + fmls za.d[w11, 0], { z0.d - z3.d }, z0.d + fmls za.d[w8, 7], { z0.d - z3.d }, z0.d + fmls za.d[w8, 0], { z28.d - z31.d }, z0.d + fmls za.d[w8, 0], { z31.d, z0.d, z1.d, z2.d }, z0.d + fmls za.d[w8, 0], { z31.d - z2.d }, z0.d + fmls za.d[w8, 0], { z0.d - z3.d }, z15.d + fmls za.d[w11, 2], { z23.d - z26.d }, z13.d + + fmls za.d[w8, 0], { z0.d - z1.d }, { z0.d - z1.d } + fmls za.d[w8, 0, vgx2], { z0.d - z1.d }, { z0.d - z1.d } + FMLS ZA.d[W8, 0, VGx2], { Z0.d - Z1.d }, { Z0.d - Z1.d } + FMLS ZA.D[W8, 0, VGX2], { Z0.D - Z1.D }, { Z0.D - Z1.D } + fmls za.d[w11, 0], { z0.d - z1.d }, { z0.d - z1.d } + fmls za.d[w8, 7], { z0.d - z1.d }, { z0.d - z1.d } + fmls za.d[w8, 0], { z30.d - z31.d }, { z0.d - z1.d } + fmls za.d[w8, 0], { z0.d - z1.d }, { z30.d - z31.d } + fmls za.d[w10, 1], { z22.d - z23.d }, { z18.d - z19.d } + + fmls za.d[w8, 0], { z0.d - z3.d }, { z0.d - z3.d } + fmls za.d[w8, 0, vgx4], { z0.d - z3.d }, { z0.d - z3.d } + FMLS ZA.d[W8, 0, VGx4], { Z0.d - Z3.d }, { Z0.d - Z3.d } + FMLS ZA.D[W8, 0, VGX4], { Z0.D - Z3.D }, { Z0.D - Z3.D } + fmls za.d[w11, 0], { z0.d - z3.d }, { z0.d - z3.d } + fmls za.d[w8, 7], { z0.d - z3.d }, { z0.d - z3.d } + fmls za.d[w8, 0], { z28.d - z31.d }, { z0.d - z3.d } + fmls za.d[w8, 0], { z0.d - z3.d }, { z28.d - z31.d } + fmls za.d[w11, 3], { z16.d - z19.d }, { z24.d - z27.d } diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index ff5367aedd7..8c7646a0ce3 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -516,6 +516,8 @@ enum aarch64_opnd AARCH64_OPND_SME_ADDR_RI_U4xVL, /* SME [{, #, MUL VL}]. */ AARCH64_OPND_SME_SM_ZA, /* SME {SM | ZA}. */ AARCH64_OPND_SME_PnT_Wm_imm, /* SME .[, #]. */ + AARCH64_OPND_SME_Zm_INDEX1, /* Zn.T[index], bits [19:16,10]. */ + AARCH64_OPND_SME_Zm_INDEX2, /* Zn.T[index], bits [19:16,11:10]. */ AARCH64_OPND_SME_Zn_INDEX1_16, /* Zn[index], bits [9:5] and [16:16]. */ AARCH64_OPND_SME_Zn_INDEX2_15, /* Zn[index], bits [9:5] and [16:15]. */ AARCH64_OPND_SME_Zn_INDEX2_16, /* Zn[index], bits [9:5] and [17:16]. */ diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c index 5dba041483c..b4ce19d8194 100644 --- a/opcodes/aarch64-asm-2.c +++ b/opcodes/aarch64-asm-2.c @@ -685,7 +685,7 @@ aarch64_insert_operand (const aarch64_operand *self, case 33: case 34: case 35: - case 257: + case 259: return aarch64_ins_reglane (self, info, code, inst, errors); case 36: return aarch64_ins_reglist (self, info, code, inst, errors); @@ -731,12 +731,12 @@ aarch64_insert_operand (const aarch64_operand *self, case 193: case 194: case 237: - case 251: - case 252: + case 253: case 254: case 256: - case 261: - case 262: + case 258: + case 263: + case 264: return aarch64_ins_imm (self, info, code, inst, errors); case 44: case 45: @@ -805,8 +805,8 @@ aarch64_insert_operand (const aarch64_operand *self, case 107: return aarch64_ins_prfop (self, info, code, inst, errors); case 108: - case 253: case 255: + case 257: return aarch64_ins_none (self, info, code, inst, errors); case 109: return aarch64_ins_hint (self, info, code, inst, errors); @@ -925,6 +925,8 @@ aarch64_insert_operand (const aarch64_operand *self, case 248: case 249: case 250: + case 251: + case 252: return aarch64_ins_simple_index (self, info, code, inst, errors); case 239: case 240: @@ -936,9 +938,9 @@ aarch64_insert_operand (const aarch64_operand *self, return aarch64_ins_sme_sm_za (self, info, code, inst, errors); case 244: return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors); - case 258: - case 259: case 260: + case 261: + case 262: return aarch64_ins_x0_to_x30 (self, info, code, inst, errors); default: assert (0); abort (); } diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c index 36e30f752b7..bfe2bc25e9d 100644 --- a/opcodes/aarch64-dis-2.c +++ b/opcodes/aarch64-dis-2.c @@ -166,7 +166,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000x10x100xxxxxxxxxxxxxxxxx zero. */ - return 2658; + return 2670; } } } @@ -190,7 +190,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000x00x101xx0xxxxxxxxxxxxxx luti4. */ - return 2527; + return 2539; } else { @@ -198,7 +198,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000x00x101xx1xxxxxxxxxxxxxx luti4. */ - return 2526; + return 2538; } } else @@ -207,7 +207,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000x10x101xxxxxxxxxxxxxxxxx luti4. */ - return 2525; + return 2537; } } } @@ -226,7 +226,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000xx0x010xxxxx00xxxxxxxxxx mov. */ - return 2534; + return 2546; } else { @@ -234,7 +234,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000xx0x011xxxxx00xxxxxxxxxx mov. */ - return 2530; + return 2542; } } else @@ -247,7 +247,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000x00x11xxx0xx00xxxxxxxxxx luti2. */ - return 2524; + return 2536; } else { @@ -255,7 +255,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000x00x11xxx1xx00xxxxxxxxxx luti2. */ - return 2523; + return 2535; } } else @@ -268,7 +268,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000010x110xxxxx00xxxxxxxxxx movt. */ - return 2545; + return 2557; } else { @@ -276,7 +276,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000010x111xxxxx00xxxxxxxxxx movt. */ - return 2544; + return 2556; } } else @@ -285,7 +285,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000110x11xxxxxx00xxxxxxxxxx luti2. */ - return 2522; + return 2534; } } } @@ -298,7 +298,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000xx0xx10xxxxx10xxxxxxxxxx mov. */ - return 2532; + return 2544; } else { @@ -306,7 +306,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000xx0xx11xxxxx10xxxxxxxxxx mov. */ - return 2528; + return 2540; } } } @@ -320,7 +320,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000xx0xx10xxxxx01xxxxxxxxxx mov. */ - return 2535; + return 2547; } else { @@ -328,7 +328,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000xx0xx11xxxxx01xxxxxxxxxx mov. */ - return 2531; + return 2543; } } else @@ -339,7 +339,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000xx0xx10xxxxx11xxxxxxxxxx mov. */ - return 2533; + return 2545; } else { @@ -347,7 +347,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000xx0xx11xxxxx11xxxxxxxxxx mov. */ - return 2529; + return 2541; } } } @@ -374,7 +374,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx000xxxxxxxxxxxx0 ld1b. */ - return 2461; + return 2473; } else { @@ -382,7 +382,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx100xxxxxxxxxxxx0 ld1b. */ - return 2462; + return 2474; } } else @@ -393,7 +393,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx010xxxxxxxxxxxx0 ld1w. */ - return 2485; + return 2497; } else { @@ -401,7 +401,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx110xxxxxxxxxxxx0 ld1w. */ - return 2486; + return 2498; } } } @@ -415,7 +415,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx001xxxxxxxxxxxx0 ld1h. */ - return 2477; + return 2489; } else { @@ -423,7 +423,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx101xxxxxxxxxxxx0 ld1h. */ - return 2478; + return 2490; } } else @@ -434,7 +434,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx011xxxxxxxxxxxx0 ld1d. */ - return 2469; + return 2481; } else { @@ -442,7 +442,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx111xxxxxxxxxxxx0 ld1d. */ - return 2470; + return 2482; } } } @@ -459,7 +459,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx000xxxxxxxxxxxx1 ldnt1b. */ - return 2493; + return 2505; } else { @@ -467,7 +467,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx100xxxxxxxxxxxx1 ldnt1b. */ - return 2494; + return 2506; } } else @@ -478,7 +478,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx010xxxxxxxxxxxx1 ldnt1w. */ - return 2517; + return 2529; } else { @@ -486,7 +486,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx110xxxxxxxxxxxx1 ldnt1w. */ - return 2518; + return 2530; } } } @@ -500,7 +500,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx001xxxxxxxxxxxx1 ldnt1h. */ - return 2509; + return 2521; } else { @@ -508,7 +508,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx101xxxxxxxxxxxx1 ldnt1h. */ - return 2510; + return 2522; } } else @@ -519,7 +519,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx011xxxxxxxxxxxx1 ldnt1d. */ - return 2501; + return 2513; } else { @@ -527,7 +527,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000000xxxxx111xxxxxxxxxxxx1 ldnt1d. */ - return 2502; + return 2514; } } } @@ -591,7 +591,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx000xxxxxxxxxxxx0 ld1b. */ - return 2457; + return 2469; } else { @@ -599,7 +599,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx100xxxxxxxxxxxx0 ld1b. */ - return 2458; + return 2470; } } else @@ -610,7 +610,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx010xxxxxxxxxxxx0 ld1w. */ - return 2481; + return 2493; } else { @@ -618,7 +618,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx110xxxxxxxxxxxx0 ld1w. */ - return 2482; + return 2494; } } } @@ -632,7 +632,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx001xxxxxxxxxxxx0 ld1h. */ - return 2473; + return 2485; } else { @@ -640,7 +640,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx101xxxxxxxxxxxx0 ld1h. */ - return 2474; + return 2486; } } else @@ -651,7 +651,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx011xxxxxxxxxxxx0 ld1d. */ - return 2465; + return 2477; } else { @@ -659,7 +659,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx111xxxxxxxxxxxx0 ld1d. */ - return 2466; + return 2478; } } } @@ -676,7 +676,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx000xxxxxxxxxxxx1 ldnt1b. */ - return 2489; + return 2501; } else { @@ -684,7 +684,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx100xxxxxxxxxxxx1 ldnt1b. */ - return 2490; + return 2502; } } else @@ -695,7 +695,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx010xxxxxxxxxxxx1 ldnt1w. */ - return 2513; + return 2525; } else { @@ -703,7 +703,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx110xxxxxxxxxxxx1 ldnt1w. */ - return 2514; + return 2526; } } } @@ -717,7 +717,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx001xxxxxxxxxxxx1 ldnt1h. */ - return 2505; + return 2517; } else { @@ -725,7 +725,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx101xxxxxxxxxxxx1 ldnt1h. */ - return 2506; + return 2518; } } else @@ -736,7 +736,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx011xxxxxxxxxxxx1 ldnt1d. */ - return 2497; + return 2509; } else { @@ -744,7 +744,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100000010xxxxx111xxxxxxxxxxxx1 ldnt1d. */ - return 2498; + return 2510; } } } @@ -812,7 +812,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx000xxxxxxxxxxxx0 st1b. */ - return 2571; + return 2583; } else { @@ -820,7 +820,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx100xxxxxxxxxxxx0 st1b. */ - return 2572; + return 2584; } } else @@ -831,7 +831,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx010xxxxxxxxxxxx0 st1w. */ - return 2595; + return 2607; } else { @@ -839,7 +839,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx110xxxxxxxxxxxx0 st1w. */ - return 2596; + return 2608; } } } @@ -853,7 +853,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx001xxxxxxxxxxxx0 st1h. */ - return 2587; + return 2599; } else { @@ -861,7 +861,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx101xxxxxxxxxxxx0 st1h. */ - return 2588; + return 2600; } } else @@ -872,7 +872,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx011xxxxxxxxxxxx0 st1d. */ - return 2579; + return 2591; } else { @@ -880,7 +880,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx111xxxxxxxxxxxx0 st1d. */ - return 2580; + return 2592; } } } @@ -897,7 +897,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx000xxxxxxxxxxxx1 stnt1b. */ - return 2603; + return 2615; } else { @@ -905,7 +905,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx100xxxxxxxxxxxx1 stnt1b. */ - return 2604; + return 2616; } } else @@ -916,7 +916,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx010xxxxxxxxxxxx1 stnt1w. */ - return 2627; + return 2639; } else { @@ -924,7 +924,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx110xxxxxxxxxxxx1 stnt1w. */ - return 2628; + return 2640; } } } @@ -938,7 +938,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx001xxxxxxxxxxxx1 stnt1h. */ - return 2619; + return 2631; } else { @@ -946,7 +946,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx101xxxxxxxxxxxx1 stnt1h. */ - return 2620; + return 2632; } } else @@ -957,7 +957,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx011xxxxxxxxxxxx1 stnt1d. */ - return 2611; + return 2623; } else { @@ -965,7 +965,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx111xxxxxxxxxxxx1 stnt1d. */ - return 2612; + return 2624; } } } @@ -1029,7 +1029,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx000xxxxxxxxxxxx0 st1b. */ - return 2567; + return 2579; } else { @@ -1037,7 +1037,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx100xxxxxxxxxxxx0 st1b. */ - return 2568; + return 2580; } } else @@ -1048,7 +1048,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx010xxxxxxxxxxxx0 st1w. */ - return 2591; + return 2603; } else { @@ -1056,7 +1056,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx110xxxxxxxxxxxx0 st1w. */ - return 2592; + return 2604; } } } @@ -1070,7 +1070,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx001xxxxxxxxxxxx0 st1h. */ - return 2583; + return 2595; } else { @@ -1078,7 +1078,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx101xxxxxxxxxxxx0 st1h. */ - return 2584; + return 2596; } } else @@ -1089,7 +1089,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx011xxxxxxxxxxxx0 st1d. */ - return 2575; + return 2587; } else { @@ -1097,7 +1097,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx111xxxxxxxxxxxx0 st1d. */ - return 2576; + return 2588; } } } @@ -1114,7 +1114,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx000xxxxxxxxxxxx1 stnt1b. */ - return 2599; + return 2611; } else { @@ -1122,7 +1122,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx100xxxxxxxxxxxx1 stnt1b. */ - return 2600; + return 2612; } } else @@ -1133,7 +1133,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx010xxxxxxxxxxxx1 stnt1w. */ - return 2623; + return 2635; } else { @@ -1141,7 +1141,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx110xxxxxxxxxxxx1 stnt1w. */ - return 2624; + return 2636; } } } @@ -1155,7 +1155,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx001xxxxxxxxxxxx1 stnt1h. */ - return 2615; + return 2627; } else { @@ -1163,7 +1163,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx101xxxxxxxxxxxx1 stnt1h. */ - return 2616; + return 2628; } } else @@ -1174,7 +1174,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx011xxxxxxxxxxxx1 stnt1d. */ - return 2607; + return 2619; } else { @@ -1182,7 +1182,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx111xxxxxxxxxxxx1 stnt1d. */ - return 2608; + return 2620; } } } @@ -1274,7 +1274,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00001000xxxxx000xxxxxxxxx0xxx ld1b. */ - return 2463; + return 2475; } else { @@ -1282,7 +1282,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00001000xxxxx010xxxxxxxxx0xxx ld1w. */ - return 2487; + return 2499; } } else @@ -1293,7 +1293,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00001000xxxxx001xxxxxxxxx0xxx ld1h. */ - return 2479; + return 2491; } else { @@ -1301,7 +1301,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00001000xxxxx011xxxxxxxxx0xxx ld1d. */ - return 2471; + return 2483; } } } @@ -1315,7 +1315,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00001000xxxxx000xxxxxxxxx1xxx ldnt1b. */ - return 2495; + return 2507; } else { @@ -1323,7 +1323,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00001000xxxxx010xxxxxxxxx1xxx ldnt1w. */ - return 2519; + return 2531; } } else @@ -1334,7 +1334,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00001000xxxxx001xxxxxxxxx1xxx ldnt1h. */ - return 2511; + return 2523; } else { @@ -1342,7 +1342,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00001000xxxxx011xxxxxxxxx1xxx ldnt1d. */ - return 2503; + return 2515; } } } @@ -1370,7 +1370,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00001000xxxxx100xxxxxxxxx0xxx ld1b. */ - return 2464; + return 2476; } else { @@ -1378,7 +1378,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1x00001000xxxxx100xxxxxxxxx0xxx ldr. */ - return 2521; + return 2533; } } else @@ -1387,7 +1387,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001000xxxxx110xxxxxxxxx0xxx ld1w. */ - return 2488; + return 2500; } } else @@ -1398,7 +1398,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001000xxxxx101xxxxxxxxx0xxx ld1h. */ - return 2480; + return 2492; } else { @@ -1406,7 +1406,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001000xxxxx111xxxxxxxxx0xxx ld1d. */ - return 2472; + return 2484; } } } @@ -1420,7 +1420,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001000xxxxx100xxxxxxxxx1xxx ldnt1b. */ - return 2496; + return 2508; } else { @@ -1428,7 +1428,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001000xxxxx110xxxxxxxxx1xxx ldnt1w. */ - return 2520; + return 2532; } } else @@ -1439,7 +1439,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001000xxxxx101xxxxxxxxx1xxx ldnt1h. */ - return 2512; + return 2524; } else { @@ -1447,7 +1447,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001000xxxxx111xxxxxxxxx1xxx ldnt1d. */ - return 2504; + return 2516; } } } @@ -1501,85 +1501,129 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 3) & 0x1) == 0) { - if (((word >> 13) & 0x1) == 0) + if (((word >> 15) & 0x1) == 0) { - if (((word >> 14) & 0x1) == 0) + if (((word >> 20) & 0x1) == 0) { - if (((word >> 15) & 0x1) == 0) + if (((word >> 13) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx00001010xxxxx000xxxxxxxxx0xxx - ld1b. */ - return 2459; + if (((word >> 14) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xxx000010100xxxx000xxxxxxxxx0xxx + ld1b. */ + return 2471; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xxx000010100xxxx010xxxxxxxxx0xxx + ld1w. */ + return 2495; + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx00001010xxxxx100xxxxxxxxx0xxx - ld1b. */ - return 2460; + if (((word >> 14) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xxx000010100xxxx001xxxxxxxxx0xxx + ld1h. */ + return 2487; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xxx000010100xxxx011xxxxxxxxx0xxx + ld1d. */ + return 2479; + } } } else { - if (((word >> 15) & 0x1) == 0) + if (((word >> 4) & 0x1) == 0) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - xxx00001010xxxxx010xxxxxxxxx0xxx - ld1w. */ - return 2483; + xxx000010101xxxx0xxxxxxxxxx00xxx + fmla. */ + return 2455; } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - xxx00001010xxxxx110xxxxxxxxx0xxx - ld1w. */ - return 2484; + xxx000010101xxxx0xxxxxxxxxx10xxx + fmls. */ + return 2461; } } } else { - if (((word >> 14) & 0x1) == 0) + if (((word >> 20) & 0x1) == 0) { - if (((word >> 15) & 0x1) == 0) + if (((word >> 13) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx00001010xxxxx001xxxxxxxxx0xxx - ld1h. */ - return 2475; + if (((word >> 14) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xxx000010100xxxx100xxxxxxxxx0xxx + ld1b. */ + return 2472; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xxx000010100xxxx110xxxxxxxxx0xxx + ld1w. */ + return 2496; + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx00001010xxxxx101xxxxxxxxx0xxx - ld1h. */ - return 2476; + if (((word >> 14) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xxx000010100xxxx101xxxxxxxxx0xxx + ld1h. */ + return 2488; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xxx000010100xxxx111xxxxxxxxx0xxx + ld1d. */ + return 2480; + } } } else { - if (((word >> 15) & 0x1) == 0) + if (((word >> 4) & 0x1) == 0) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - xxx00001010xxxxx011xxxxxxxxx0xxx - ld1d. */ - return 2467; + xxx000010101xxxx1xxxxxxxxxx00xxx + fmla. */ + return 2456; } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - xxx00001010xxxxx111xxxxxxxxx0xxx - ld1d. */ - return 2468; + xxx000010101xxxx1xxxxxxxxxx10xxx + fmls. */ + return 2462; } } } @@ -1596,7 +1640,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001010xxxxx000xxxxxxxxx1xxx ldnt1b. */ - return 2491; + return 2503; } else { @@ -1604,7 +1648,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001010xxxxx100xxxxxxxxx1xxx ldnt1b. */ - return 2492; + return 2504; } } else @@ -1615,7 +1659,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001010xxxxx010xxxxxxxxx1xxx ldnt1w. */ - return 2515; + return 2527; } else { @@ -1623,7 +1667,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001010xxxxx110xxxxxxxxx1xxx ldnt1w. */ - return 2516; + return 2528; } } } @@ -1637,7 +1681,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001010xxxxx001xxxxxxxxx1xxx ldnt1h. */ - return 2507; + return 2519; } else { @@ -1645,7 +1689,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001010xxxxx101xxxxxxxxx1xxx ldnt1h. */ - return 2508; + return 2520; } } else @@ -1656,7 +1700,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001010xxxxx011xxxxxxxxx1xxx ldnt1d. */ - return 2499; + return 2511; } else { @@ -1664,7 +1708,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001010xxxxx111xxxxxxxxx1xxx ldnt1d. */ - return 2500; + return 2512; } } } @@ -1674,30 +1718,74 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 4) & 0x1) == 0) { - if (((word >> 30) & 0x1) == 0) + if (((word >> 29) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x0x00001110xxxxxxxxxxxxxxxx0xxxx - usmopa. */ - return 2385; + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx000001110xxxxx0xxxxxxxxxx0xxxx + fmla. */ + return 2671; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx000001110xxxxx1xxxxxxxxxx0xxxx + fmla. */ + return 2672; + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1x00001110xxxxxxxxxxxxxxxx0xxxx - ld1q. */ - return 2397; + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0100001110xxxxxxxxxxxxxxxx0xxxx + usmopa. */ + return 2385; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1100001110xxxxxxxxxxxxxxxx0xxxx + ld1q. */ + return 2397; + } } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx00001110xxxxxxxxxxxxxxxx1xxxx - usmops. */ - return 2387; + if (((word >> 29) & 0x1) == 0) + { + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx000001110xxxxx0xxxxxxxxxx1xxxx + fmls. */ + return 2673; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx000001110xxxxx1xxxxxxxxxx1xxxx + fmls. */ + return 2674; + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx100001110xxxxxxxxxxxxxxxx1xxxx + usmops. */ + return 2387; + } } } } @@ -1733,21 +1821,65 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 4) & 0x1) == 0) { - if (((word >> 16) & 0x1) == 0) + if (((word >> 10) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx1xxxx00xxxxxxxxxx00xxx - fadd. */ - return 2437; + if (((word >> 23) & 0x1) == 0) + { + if (((word >> 20) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000010x10xxxx0xxxx0xxxxx00xxx + fmla. */ + return 2457; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000010x11xxxx0xxxx0xxxxx00xxx + fmla. */ + return 2458; + } + } + else + { + if (((word >> 16) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000011x1xxxx00xxxx0xxxxx00xxx + fmla. */ + return 2459; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000011x1xxxx10xxxx0xxxxx00xxx + fmla. */ + return 2460; + } + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx1xxxx10xxxxxxxxxx00xxx - fadd. */ - return 2438; + if (((word >> 16) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xxxx00xxxx1xxxxx00xxx + fadd. */ + return 2437; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xxxx10xxxx1xxxxx00xxx + fadd. */ + return 2438; + } } } else @@ -1818,21 +1950,65 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 4) & 0x1) == 0) { - if (((word >> 16) & 0x1) == 0) + if (((word >> 10) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx1xxxx00xxxxxxxxxx01xxx - fsub. */ - return 2455; + if (((word >> 23) & 0x1) == 0) + { + if (((word >> 20) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000010x10xxxx0xxxx0xxxxx01xxx + fmls. */ + return 2463; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000010x11xxxx0xxxx0xxxxx01xxx + fmls. */ + return 2464; + } + } + else + { + if (((word >> 16) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000011x1xxxx00xxxx0xxxxx01xxx + fmls. */ + return 2465; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10000011x1xxxx10xxxx0xxxxx01xxx + fmls. */ + return 2466; + } + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx1xxxx10xxxxxxxxxx01xxx - fsub. */ - return 2456; + if (((word >> 16) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xxxx00xxxx1xxxxx01xxx + fsub. */ + return 2467; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xxxx10xxxx1xxxxx01xxx + fsub. */ + return 2468; + } } } else @@ -1847,7 +2023,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000010x10xxxx0xxxx0xxxxx11xxx sub. */ - return 2634; + return 2646; } else { @@ -1855,7 +2031,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000010x11xxxx0xxxx0xxxxx11xxx sub. */ - return 2635; + return 2647; } } else @@ -1866,7 +2042,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011x1xxxx00xxxx0xxxxx11xxx sub. */ - return 2636; + return 2648; } else { @@ -1874,7 +2050,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011x1xxxx10xxxx0xxxxx11xxx sub. */ - return 2637; + return 2649; } } } @@ -1886,7 +2062,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxx00xxxx1xxxxx11xxx sub. */ - return 2632; + return 2644; } else { @@ -1894,7 +2070,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxx10xxxx1xxxxx11xxx sub. */ - return 2633; + return 2645; } } } @@ -1914,7 +2090,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxx01x0xxxxxxx0xxxx0 sel. */ - return 2549; + return 2561; } else { @@ -1922,7 +2098,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxx11x0xxxxxxx0xxxx0 sel. */ - return 2550; + return 2562; } } else @@ -1939,7 +2115,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1x1000x0xx0xxxx0 smax. */ - return 2551; + return 2563; } else { @@ -1947,7 +2123,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1x1100x0xx0xxxx0 smax. */ - return 2553; + return 2565; } } else @@ -1958,7 +2134,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1x1010x0xx0xxxx0 smax. */ - return 2552; + return 2564; } else { @@ -1966,7 +2142,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1x1110x0xx0xxxx0 smax. */ - return 2554; + return 2566; } } } @@ -1980,7 +2156,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1x1001x0xx0xxxx0 sqdmulh. */ - return 2559; + return 2571; } else { @@ -1988,7 +2164,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1x1101x0xx0xxxx0 sqdmulh. */ - return 2561; + return 2573; } } else @@ -1999,7 +2175,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1x1011x0xx0xxxx0 sqdmulh. */ - return 2560; + return 2572; } else { @@ -2007,7 +2183,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1x1111x0xx0xxxx0 sqdmulh. */ - return 2562; + return 2574; } } } @@ -2091,7 +2267,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1xx00x00xx1xxxx0 smin. */ - return 2555; + return 2567; } else { @@ -2099,7 +2275,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1xx10x00xx1xxxx0 smin. */ - return 2557; + return 2569; } } else @@ -2110,7 +2286,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1xx01x00xx1xxxx0 smin. */ - return 2556; + return 2568; } else { @@ -2118,7 +2294,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1xx11x00xx1xxxx0 smin. */ - return 2558; + return 2570; } } } @@ -2132,7 +2308,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1xx00x10xx1xxxx0 srshl. */ - return 2563; + return 2575; } else { @@ -2140,7 +2316,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1xx10x10xx1xxxx0 srshl. */ - return 2565; + return 2577; } } else @@ -2151,7 +2327,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1xx01x10xx1xxxx0 srshl. */ - return 2564; + return 2576; } else { @@ -2159,7 +2335,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1xx11x10xx1xxxx0 srshl. */ - return 2566; + return 2578; } } } @@ -2221,7 +2397,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1xx00xx0xx0xxxx1 umax. */ - return 2638; + return 2650; } else { @@ -2229,7 +2405,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1xx10xx0xx0xxxx1 umax. */ - return 2640; + return 2652; } } else @@ -2240,7 +2416,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1xx01xx0xx0xxxx1 umax. */ - return 2639; + return 2651; } else { @@ -2248,7 +2424,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1xx11xx0xx0xxxx1 umax. */ - return 2641; + return 2653; } } } @@ -2308,7 +2484,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1xx00x00xx1xxxx1 umin. */ - return 2642; + return 2654; } else { @@ -2316,7 +2492,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1xx10x00xx1xxxx1 umin. */ - return 2644; + return 2656; } } else @@ -2327,7 +2503,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1xx01x00xx1xxxx1 umin. */ - return 2643; + return 2655; } else { @@ -2335,7 +2511,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1xx11x00xx1xxxx1 umin. */ - return 2645; + return 2657; } } } @@ -2349,7 +2525,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1xx00x10xx1xxxx1 urshl. */ - return 2646; + return 2658; } else { @@ -2357,7 +2533,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1xx10x10xx1xxxx1 urshl. */ - return 2648; + return 2660; } } else @@ -2368,7 +2544,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1xx01x10xx1xxxx1 urshl. */ - return 2647; + return 2659; } else { @@ -2376,7 +2552,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1xx11x10xx1xxxx1 urshl. */ - return 2649; + return 2661; } } } @@ -2447,7 +2623,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx000xxxxxxxxx0xxx st1b. */ - return 2573; + return 2585; } else { @@ -2455,7 +2631,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx010xxxxxxxxx0xxx st1w. */ - return 2597; + return 2609; } } else @@ -2466,7 +2642,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx001xxxxxxxxx0xxx st1h. */ - return 2589; + return 2601; } else { @@ -2474,7 +2650,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx011xxxxxxxxx0xxx st1d. */ - return 2581; + return 2593; } } } @@ -2488,7 +2664,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx000xxxxxxxxx1xxx stnt1b. */ - return 2605; + return 2617; } else { @@ -2496,7 +2672,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx010xxxxxxxxx1xxx stnt1w. */ - return 2629; + return 2641; } } else @@ -2507,7 +2683,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx001xxxxxxxxx1xxx stnt1h. */ - return 2621; + return 2633; } else { @@ -2515,7 +2691,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx011xxxxxxxxx1xxx stnt1d. */ - return 2613; + return 2625; } } } @@ -2543,7 +2719,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx100xxxxxxxxx0xxx st1b. */ - return 2574; + return 2586; } else { @@ -2551,7 +2727,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1100001001xxxxx100xxxxxxxxx0xxx str. */ - return 2631; + return 2643; } } else @@ -2560,7 +2736,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001001xxxxx110xxxxxxxxx0xxx st1w. */ - return 2598; + return 2610; } } else @@ -2571,7 +2747,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001001xxxxx101xxxxxxxxx0xxx st1h. */ - return 2590; + return 2602; } else { @@ -2579,7 +2755,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001001xxxxx111xxxxxxxxx0xxx st1d. */ - return 2582; + return 2594; } } } @@ -2593,7 +2769,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001001xxxxx100xxxxxxxxx1xxx stnt1b. */ - return 2606; + return 2618; } else { @@ -2601,7 +2777,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001001xxxxx110xxxxxxxxx1xxx stnt1w. */ - return 2630; + return 2642; } } else @@ -2612,7 +2788,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001001xxxxx101xxxxxxxxx1xxx stnt1h. */ - return 2622; + return 2634; } else { @@ -2620,7 +2796,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001001xxxxx111xxxxxxxxx1xxx stnt1d. */ - return 2614; + return 2626; } } } @@ -2662,7 +2838,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx000xxxxxxxxx0xxx st1b. */ - return 2569; + return 2581; } else { @@ -2670,7 +2846,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx100xxxxxxxxx0xxx st1b. */ - return 2570; + return 2582; } } else @@ -2681,7 +2857,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx010xxxxxxxxx0xxx st1w. */ - return 2593; + return 2605; } else { @@ -2689,7 +2865,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx110xxxxxxxxx0xxx st1w. */ - return 2594; + return 2606; } } } @@ -2703,7 +2879,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx001xxxxxxxxx0xxx st1h. */ - return 2585; + return 2597; } else { @@ -2711,7 +2887,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx101xxxxxxxxx0xxx st1h. */ - return 2586; + return 2598; } } else @@ -2722,7 +2898,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx011xxxxxxxxx0xxx st1d. */ - return 2577; + return 2589; } else { @@ -2730,7 +2906,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx111xxxxxxxxx0xxx st1d. */ - return 2578; + return 2590; } } } @@ -2747,7 +2923,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx000xxxxxxxxx1xxx stnt1b. */ - return 2601; + return 2613; } else { @@ -2755,7 +2931,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx100xxxxxxxxx1xxx stnt1b. */ - return 2602; + return 2614; } } else @@ -2766,7 +2942,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx010xxxxxxxxx1xxx stnt1w. */ - return 2625; + return 2637; } else { @@ -2774,7 +2950,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx110xxxxxxxxx1xxx stnt1w. */ - return 2626; + return 2638; } } } @@ -2788,7 +2964,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx001xxxxxxxxx1xxx stnt1h. */ - return 2617; + return 2629; } else { @@ -2796,7 +2972,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx101xxxxxxxxx1xxx stnt1h. */ - return 2618; + return 2630; } } else @@ -2807,7 +2983,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx011xxxxxxxxx1xxx stnt1d. */ - return 2609; + return 2621; } else { @@ -2815,7 +2991,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx111xxxxxxxxx1xxx stnt1d. */ - return 2610; + return 2622; } } } @@ -5217,7 +5393,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 00011001000xxxxxxxxx00xxxxxxxxxx stlurb. */ - return 2699; + return 2715; } else { @@ -5225,7 +5401,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 10011001000xxxxxxxxx00xxxxxxxxxx stlur. */ - return 2707; + return 2723; } } else @@ -5236,7 +5412,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 01011001000xxxxxxxxx00xxxxxxxxxx stlurh. */ - return 2703; + return 2719; } else { @@ -5244,7 +5420,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 11011001000xxxxxxxxx00xxxxxxxxxx stlur. */ - return 2710; + return 2726; } } } @@ -5282,7 +5458,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0000x1xxxxxxxxxx cpyfp. */ - return 2759; + return 2775; } else { @@ -5290,7 +5466,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1000x1xxxxxxxxxx cpyfprn. */ - return 2765; + return 2781; } } else @@ -5301,7 +5477,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0100x1xxxxxxxxxx cpyfpwn. */ - return 2762; + return 2778; } else { @@ -5309,7 +5485,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1100x1xxxxxxxxxx cpyfpn. */ - return 2768; + return 2784; } } } @@ -5323,7 +5499,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0010x1xxxxxxxxxx cpyfprt. */ - return 2783; + return 2799; } else { @@ -5331,7 +5507,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1010x1xxxxxxxxxx cpyfprtrn. */ - return 2789; + return 2805; } } else @@ -5342,7 +5518,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0110x1xxxxxxxxxx cpyfprtwn. */ - return 2786; + return 2802; } else { @@ -5350,7 +5526,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1110x1xxxxxxxxxx cpyfprtn. */ - return 2792; + return 2808; } } } @@ -5367,7 +5543,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0001x1xxxxxxxxxx cpyfpwt. */ - return 2771; + return 2787; } else { @@ -5375,7 +5551,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1001x1xxxxxxxxxx cpyfpwtrn. */ - return 2777; + return 2793; } } else @@ -5386,7 +5562,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0101x1xxxxxxxxxx cpyfpwtwn. */ - return 2774; + return 2790; } else { @@ -5394,7 +5570,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1101x1xxxxxxxxxx cpyfpwtn. */ - return 2780; + return 2796; } } } @@ -5408,7 +5584,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0011x1xxxxxxxxxx cpyfpt. */ - return 2795; + return 2811; } else { @@ -5416,7 +5592,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1011x1xxxxxxxxxx cpyfptrn. */ - return 2801; + return 2817; } } else @@ -5427,7 +5603,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0111x1xxxxxxxxxx cpyfptwn. */ - return 2798; + return 2814; } else { @@ -5435,7 +5611,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1111x1xxxxxxxxxx cpyfptn. */ - return 2804; + return 2820; } } } @@ -5500,7 +5676,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 00011001010xxxxxxxxx00xxxxxxxxxx ldapurb. */ - return 2700; + return 2716; } else { @@ -5508,7 +5684,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 10011001010xxxxxxxxx00xxxxxxxxxx ldapur. */ - return 2708; + return 2724; } } else @@ -5519,7 +5695,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 01011001010xxxxxxxxx00xxxxxxxxxx ldapurh. */ - return 2704; + return 2720; } else { @@ -5527,7 +5703,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 11011001010xxxxxxxxx00xxxxxxxxxx ldapur. */ - return 2711; + return 2727; } } } @@ -5565,7 +5741,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0000x1xxxxxxxxxx cpyfm. */ - return 2760; + return 2776; } else { @@ -5573,7 +5749,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1000x1xxxxxxxxxx cpyfmrn. */ - return 2766; + return 2782; } } else @@ -5584,7 +5760,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0100x1xxxxxxxxxx cpyfmwn. */ - return 2763; + return 2779; } else { @@ -5592,7 +5768,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1100x1xxxxxxxxxx cpyfmn. */ - return 2769; + return 2785; } } } @@ -5606,7 +5782,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0010x1xxxxxxxxxx cpyfmrt. */ - return 2784; + return 2800; } else { @@ -5614,7 +5790,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1010x1xxxxxxxxxx cpyfmrtrn. */ - return 2790; + return 2806; } } else @@ -5625,7 +5801,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0110x1xxxxxxxxxx cpyfmrtwn. */ - return 2787; + return 2803; } else { @@ -5633,7 +5809,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1110x1xxxxxxxxxx cpyfmrtn. */ - return 2793; + return 2809; } } } @@ -5650,7 +5826,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0001x1xxxxxxxxxx cpyfmwt. */ - return 2772; + return 2788; } else { @@ -5658,7 +5834,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1001x1xxxxxxxxxx cpyfmwtrn. */ - return 2778; + return 2794; } } else @@ -5669,7 +5845,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0101x1xxxxxxxxxx cpyfmwtwn. */ - return 2775; + return 2791; } else { @@ -5677,7 +5853,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1101x1xxxxxxxxxx cpyfmwtn. */ - return 2781; + return 2797; } } } @@ -5691,7 +5867,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0011x1xxxxxxxxxx cpyfmt. */ - return 2796; + return 2812; } else { @@ -5699,7 +5875,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1011x1xxxxxxxxxx cpyfmtrn. */ - return 2802; + return 2818; } } else @@ -5710,7 +5886,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0111x1xxxxxxxxxx cpyfmtwn. */ - return 2799; + return 2815; } else { @@ -5718,7 +5894,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1111x1xxxxxxxxxx cpyfmtn. */ - return 2805; + return 2821; } } } @@ -5786,7 +5962,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 00011001100xxxxxxxxx00xxxxxxxxxx ldapursb. */ - return 2702; + return 2718; } else { @@ -5794,7 +5970,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 10011001100xxxxxxxxx00xxxxxxxxxx ldapursw. */ - return 2709; + return 2725; } } else @@ -5803,7 +5979,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1011001100xxxxxxxxx00xxxxxxxxxx ldapursh. */ - return 2706; + return 2722; } } else @@ -5814,7 +5990,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0011001110xxxxxxxxx00xxxxxxxxxx ldapursb. */ - return 2701; + return 2717; } else { @@ -5822,7 +5998,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1011001110xxxxxxxxx00xxxxxxxxxx ldapursh. */ - return 2705; + return 2721; } } } @@ -5884,7 +6060,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0000x1xxxxxxxxxx cpyfe. */ - return 2761; + return 2777; } else { @@ -5892,7 +6068,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0000x1xxxxxxxxxx setp. */ - return 2855; + return 2871; } } else @@ -5903,7 +6079,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx1000x1xxxxxxxxxx cpyfern. */ - return 2767; + return 2783; } else { @@ -5911,7 +6087,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx1000x1xxxxxxxxxx sete. */ - return 2857; + return 2873; } } } @@ -5925,7 +6101,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0100x1xxxxxxxxxx cpyfewn. */ - return 2764; + return 2780; } else { @@ -5933,7 +6109,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0100x1xxxxxxxxxx setm. */ - return 2856; + return 2872; } } else @@ -5942,7 +6118,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0110011x0xxxxx1100x1xxxxxxxxxx cpyfen. */ - return 2770; + return 2786; } } } @@ -5958,7 +6134,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0010x1xxxxxxxxxx cpyfert. */ - return 2785; + return 2801; } else { @@ -5966,7 +6142,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0010x1xxxxxxxxxx setpn. */ - return 2861; + return 2877; } } else @@ -5977,7 +6153,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx1010x1xxxxxxxxxx cpyfertrn. */ - return 2791; + return 2807; } else { @@ -5985,7 +6161,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx1010x1xxxxxxxxxx seten. */ - return 2863; + return 2879; } } } @@ -5999,7 +6175,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0110x1xxxxxxxxxx cpyfertwn. */ - return 2788; + return 2804; } else { @@ -6007,7 +6183,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0110x1xxxxxxxxxx setmn. */ - return 2862; + return 2878; } } else @@ -6016,7 +6192,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0110011x0xxxxx1110x1xxxxxxxxxx cpyfertn. */ - return 2794; + return 2810; } } } @@ -6035,7 +6211,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0001x1xxxxxxxxxx cpyfewt. */ - return 2773; + return 2789; } else { @@ -6043,7 +6219,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0001x1xxxxxxxxxx setpt. */ - return 2858; + return 2874; } } else @@ -6054,7 +6230,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx1001x1xxxxxxxxxx cpyfewtrn. */ - return 2779; + return 2795; } else { @@ -6062,7 +6238,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx1001x1xxxxxxxxxx setet. */ - return 2860; + return 2876; } } } @@ -6076,7 +6252,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0101x1xxxxxxxxxx cpyfewtwn. */ - return 2776; + return 2792; } else { @@ -6084,7 +6260,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0101x1xxxxxxxxxx setmt. */ - return 2859; + return 2875; } } else @@ -6093,7 +6269,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0110011x0xxxxx1101x1xxxxxxxxxx cpyfewtn. */ - return 2782; + return 2798; } } } @@ -6109,7 +6285,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0011x1xxxxxxxxxx cpyfet. */ - return 2797; + return 2813; } else { @@ -6117,7 +6293,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0011x1xxxxxxxxxx setptn. */ - return 2864; + return 2880; } } else @@ -6128,7 +6304,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx1011x1xxxxxxxxxx cpyfetrn. */ - return 2803; + return 2819; } else { @@ -6136,7 +6312,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx1011x1xxxxxxxxxx setetn. */ - return 2866; + return 2882; } } } @@ -6150,7 +6326,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0111x1xxxxxxxxxx cpyfetwn. */ - return 2800; + return 2816; } else { @@ -6158,7 +6334,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0111x1xxxxxxxxxx setmtn. */ - return 2865; + return 2881; } } else @@ -6167,7 +6343,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0110011x0xxxxx1111x1xxxxxxxxxx cpyfetn. */ - return 2806; + return 2822; } } } @@ -6540,7 +6716,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1x11010110xxxx0x01000xxxxxxxxxx abs. */ - return 2884; + return 2900; } else { @@ -6558,7 +6734,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010110xxxxxx11000xxxxxxxxxx smax. */ - return 2887; + return 2903; } } } @@ -6638,7 +6814,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010x00xxxxxx0xx10xxxxxxxxxx setf8. */ - return 2697; + return 2713; } else { @@ -6646,7 +6822,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010x00xxxxxx1xx10xxxxxxxxxx setf16. */ - return 2698; + return 2714; } } else @@ -6753,7 +6929,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010110xxxxxx11010xxxxxxxxxx smin. */ - return 2889; + return 2905; } } } @@ -6769,7 +6945,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010110xxxx0x00110xxxxxxxxxx ctz. */ - return 2886; + return 2902; } else { @@ -6814,7 +6990,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010000xxxxxxxxx01xxxxxxxxxx rmif. */ - return 2696; + return 2712; } else { @@ -6908,7 +7084,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010x10xxxxxx11001xxxxxxxxxx umax. */ - return 2888; + return 2904; } } } @@ -7038,7 +7214,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010xx0xxxxxx11011xxxxxxxxxx umin. */ - return 2890; + return 2906; } } } @@ -7054,7 +7230,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010xx0xxxx0x00111xxxxxxxxxx cnt. */ - return 2885; + return 2901; } else { @@ -7896,7 +8072,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x01x1xxxxx000110xxxxxxxxxx usdot. */ - return 2716; + return 2732; } } } @@ -7970,7 +8146,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x01x1xxxxx000111xxxxxxxxxx sudot. */ - return 2717; + return 2733; } } } @@ -10644,7 +10820,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x0xx0xxxxx011110xxxxxxxxxx usdot. */ - return 2715; + return 2731; } } } @@ -12348,7 +12524,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0100xxx10101xxxxxxxxxxxxx bfcvtnt. */ - return 2744; + return 2760; } } else @@ -12591,7 +12767,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x00x1xxxxxx00xxxxxxxxxxxxx ld1rob. */ - return 2720; + return 2736; } else { @@ -12599,7 +12775,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x01x1xxxxxx00xxxxxxxxxxxxx ld1roh. */ - return 2721; + return 2737; } } else @@ -12831,7 +13007,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0011xxxxx010xxxxxxxxxxxxx bfdot. */ - return 2741; + return 2757; } else { @@ -12852,7 +13028,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx010xx0xxxxxxxxxx bfmlalb. */ - return 2748; + return 2764; } else { @@ -12860,7 +13036,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx010xx1xxxxxxxxxx bfmlalt. */ - return 2747; + return 2763; } } else @@ -12915,7 +13091,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11001x0011xxxxx1x0xxxxxxxxxxxxx bfdot. */ - return 2740; + return 2756; } else { @@ -12927,7 +13103,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx1x0xx0xxxxxxxxxx bfmlalb. */ - return 2746; + return 2762; } else { @@ -12935,7 +13111,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx1x0xx1xxxxxxxxxx bfmlalt. */ - return 2745; + return 2761; } } else @@ -12986,7 +13162,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x00x1xxxxx001xxxxxxxxxxxxx ld1rob. */ - return 2724; + return 2740; } else { @@ -12994,7 +13170,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x01x1xxxxx001xxxxxxxxxxxxx ld1roh. */ - return 2725; + return 2741; } } else @@ -13353,7 +13529,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0101xxxxx111xxxxxxxxxxxxx fmmla. */ - return 2718; + return 2734; } else { @@ -13386,7 +13562,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0011xxxxx111xxxxxxxxxxxxx bfmmla. */ - return 2742; + return 2758; } else { @@ -13416,7 +13592,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx111xxxxxxxxxxxxx fmmla. */ - return 2719; + return 2735; } else { @@ -13545,7 +13721,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000x00xxxxxxxxxx zip1. */ - return 2728; + return 2744; } else { @@ -13555,7 +13731,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000010xxxxxxxxxx uzp1. */ - return 2730; + return 2746; } else { @@ -13563,7 +13739,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000110xxxxxxxxxx trn1. */ - return 2732; + return 2748; } } } @@ -13575,7 +13751,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000x01xxxxxxxxxx zip2. */ - return 2729; + return 2745; } else { @@ -13585,7 +13761,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000011xxxxxxxxxx uzp2. */ - return 2731; + return 2747; } else { @@ -13593,7 +13769,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000111xxxxxxxxxx trn2. */ - return 2733; + return 2749; } } } @@ -14652,7 +14828,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x1000xxxxx100110xxxxxxxxxx smmla. */ - return 2712; + return 2728; } else { @@ -14660,7 +14836,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x1100xxxxx100110xxxxxxxxxx usmmla. */ - return 2714; + return 2730; } } else @@ -14669,7 +14845,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x1x10xxxxx100110xxxxxxxxxx ummla. */ - return 2713; + return 2729; } } } @@ -16165,7 +16341,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x10x1xxxxx000xxxxxxxxxxxxx ld1row. */ - return 2722; + return 2738; } else { @@ -16173,7 +16349,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x11x1xxxxx000xxxxxxxxxxxxx ld1rod. */ - return 2723; + return 2739; } } } @@ -16547,7 +16723,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x10x1xxxxx001xxxxxxxxxxxxx ld1row. */ - return 2726; + return 2742; } else { @@ -16555,7 +16731,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x11x1xxxxx001xxxxxxxxxxxxx ld1rod. */ - return 2727; + return 2743; } } } @@ -16916,7 +17092,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x000xxxxx10xxx whilege. */ - return 2650; + return 2662; } else { @@ -16924,7 +17100,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x000xxxxx11xxx whilegt. */ - return 2651; + return 2663; } } else @@ -16954,7 +17130,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx011100xxxxx1xxxx pext. */ - return 2546; + return 2558; } } } @@ -16968,7 +17144,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x010xxxxx10xxx whilehs. */ - return 2653; + return 2665; } else { @@ -16976,7 +17152,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x010xxxxx11xxx whilehi. */ - return 2652; + return 2664; } } else @@ -17006,7 +17182,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx011110xxxxx1xxxx ptrue. */ - return 2548; + return 2560; } } } @@ -17023,7 +17199,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x001xxxxx10xxx whilelt. */ - return 2657; + return 2669; } else { @@ -17031,7 +17207,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x001xxxxx11xxx whilele. */ - return 2654; + return 2666; } } else @@ -17061,7 +17237,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx011101xxxxx1xxxx pext. */ - return 2547; + return 2559; } } } @@ -17075,7 +17251,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x011xxxxx10xxx whilelo. */ - return 2655; + return 2667; } else { @@ -17083,7 +17259,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x011xxxxx11xxx whilels. */ - return 2656; + return 2668; } } else @@ -18209,7 +18385,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x110001x10101xxxxxxxxxxxxx bfcvt. */ - return 2743; + return 2759; } } else @@ -19570,7 +19746,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1010100xxxxxxxxxxxxxxxxxxx1xxxx bc.c. */ - return 2879; + return 2895; } else { @@ -20150,7 +20326,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0000xxxxxxxxxxxx cpyp. */ - return 2807; + return 2823; } else { @@ -20158,7 +20334,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0000xxxxxxxxxxxx cpye. */ - return 2809; + return 2825; } } else @@ -20169,7 +20345,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1000xxxxxxxxxxxx cpyprn. */ - return 2813; + return 2829; } else { @@ -20177,7 +20353,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1000xxxxxxxxxxxx cpyern. */ - return 2815; + return 2831; } } } @@ -20191,7 +20367,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0100xxxxxxxxxxxx cpypwn. */ - return 2810; + return 2826; } else { @@ -20199,7 +20375,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0100xxxxxxxxxxxx cpyewn. */ - return 2812; + return 2828; } } else @@ -20210,7 +20386,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1100xxxxxxxxxxxx cpypn. */ - return 2816; + return 2832; } else { @@ -20218,7 +20394,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1100xxxxxxxxxxxx cpyen. */ - return 2818; + return 2834; } } } @@ -20235,7 +20411,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0010xxxxxxxxxxxx cpyprt. */ - return 2831; + return 2847; } else { @@ -20243,7 +20419,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0010xxxxxxxxxxxx cpyert. */ - return 2833; + return 2849; } } else @@ -20254,7 +20430,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1010xxxxxxxxxxxx cpyprtrn. */ - return 2837; + return 2853; } else { @@ -20262,7 +20438,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1010xxxxxxxxxxxx cpyertrn. */ - return 2839; + return 2855; } } } @@ -20276,7 +20452,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0110xxxxxxxxxxxx cpyprtwn. */ - return 2834; + return 2850; } else { @@ -20284,7 +20460,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0110xxxxxxxxxxxx cpyertwn. */ - return 2836; + return 2852; } } else @@ -20295,7 +20471,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1110xxxxxxxxxxxx cpyprtn. */ - return 2840; + return 2856; } else { @@ -20303,7 +20479,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1110xxxxxxxxxxxx cpyertn. */ - return 2842; + return 2858; } } } @@ -20323,7 +20499,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0001xxxxxxxxxxxx cpypwt. */ - return 2819; + return 2835; } else { @@ -20331,7 +20507,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0001xxxxxxxxxxxx cpyewt. */ - return 2821; + return 2837; } } else @@ -20342,7 +20518,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1001xxxxxxxxxxxx cpypwtrn. */ - return 2825; + return 2841; } else { @@ -20350,7 +20526,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1001xxxxxxxxxxxx cpyewtrn. */ - return 2827; + return 2843; } } } @@ -20364,7 +20540,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0101xxxxxxxxxxxx cpypwtwn. */ - return 2822; + return 2838; } else { @@ -20372,7 +20548,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0101xxxxxxxxxxxx cpyewtwn. */ - return 2824; + return 2840; } } else @@ -20383,7 +20559,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1101xxxxxxxxxxxx cpypwtn. */ - return 2828; + return 2844; } else { @@ -20391,7 +20567,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1101xxxxxxxxxxxx cpyewtn. */ - return 2830; + return 2846; } } } @@ -20408,7 +20584,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0011xxxxxxxxxxxx cpypt. */ - return 2843; + return 2859; } else { @@ -20416,7 +20592,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0011xxxxxxxxxxxx cpyet. */ - return 2845; + return 2861; } } else @@ -20427,7 +20603,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1011xxxxxxxxxxxx cpyptrn. */ - return 2849; + return 2865; } else { @@ -20435,7 +20611,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1011xxxxxxxxxxxx cpyetrn. */ - return 2851; + return 2867; } } } @@ -20449,7 +20625,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0111xxxxxxxxxxxx cpyptwn. */ - return 2846; + return 2862; } else { @@ -20457,7 +20633,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0111xxxxxxxxxxxx cpyetwn. */ - return 2848; + return 2864; } } else @@ -20468,7 +20644,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1111xxxxxxxxxxxx cpyptn. */ - return 2852; + return 2868; } else { @@ -20476,7 +20652,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1111xxxxxxxxxxxx cpyetn. */ - return 2854; + return 2870; } } } @@ -20510,7 +20686,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0000xxxxxxxxxxxx cpym. */ - return 2808; + return 2824; } else { @@ -20518,7 +20694,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0000xxxxxxxxxxxx setgp. */ - return 2867; + return 2883; } } else @@ -20529,7 +20705,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx1000xxxxxxxxxxxx cpymrn. */ - return 2814; + return 2830; } else { @@ -20537,7 +20713,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx1000xxxxxxxxxxxx setge. */ - return 2869; + return 2885; } } } @@ -20551,7 +20727,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0100xxxxxxxxxxxx cpymwn. */ - return 2811; + return 2827; } else { @@ -20559,7 +20735,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0100xxxxxxxxxxxx setgm. */ - return 2868; + return 2884; } } else @@ -20568,7 +20744,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011101x1xxxxxx1100xxxxxxxxxxxx cpymn. */ - return 2817; + return 2833; } } } @@ -20584,7 +20760,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0010xxxxxxxxxxxx cpymrt. */ - return 2832; + return 2848; } else { @@ -20592,7 +20768,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0010xxxxxxxxxxxx setgpn. */ - return 2873; + return 2889; } } else @@ -20603,7 +20779,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx1010xxxxxxxxxxxx cpymrtrn. */ - return 2838; + return 2854; } else { @@ -20611,7 +20787,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx1010xxxxxxxxxxxx setgen. */ - return 2875; + return 2891; } } } @@ -20625,7 +20801,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0110xxxxxxxxxxxx cpymrtwn. */ - return 2835; + return 2851; } else { @@ -20633,7 +20809,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0110xxxxxxxxxxxx setgmn. */ - return 2874; + return 2890; } } else @@ -20642,7 +20818,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011101x1xxxxxx1110xxxxxxxxxxxx cpymrtn. */ - return 2841; + return 2857; } } } @@ -20661,7 +20837,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0001xxxxxxxxxxxx cpymwt. */ - return 2820; + return 2836; } else { @@ -20669,7 +20845,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0001xxxxxxxxxxxx setgpt. */ - return 2870; + return 2886; } } else @@ -20680,7 +20856,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx1001xxxxxxxxxxxx cpymwtrn. */ - return 2826; + return 2842; } else { @@ -20688,7 +20864,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx1001xxxxxxxxxxxx setget. */ - return 2872; + return 2888; } } } @@ -20702,7 +20878,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0101xxxxxxxxxxxx cpymwtwn. */ - return 2823; + return 2839; } else { @@ -20710,7 +20886,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0101xxxxxxxxxxxx setgmt. */ - return 2871; + return 2887; } } else @@ -20719,7 +20895,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011101x1xxxxxx1101xxxxxxxxxxxx cpymwtn. */ - return 2829; + return 2845; } } } @@ -20735,7 +20911,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0011xxxxxxxxxxxx cpymt. */ - return 2844; + return 2860; } else { @@ -20743,7 +20919,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0011xxxxxxxxxxxx setgptn. */ - return 2876; + return 2892; } } else @@ -20754,7 +20930,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx1011xxxxxxxxxxxx cpymtrn. */ - return 2850; + return 2866; } else { @@ -20762,7 +20938,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx1011xxxxxxxxxxxx setgetn. */ - return 2878; + return 2894; } } } @@ -20776,7 +20952,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0111xxxxxxxxxxxx cpymtwn. */ - return 2847; + return 2863; } else { @@ -20784,7 +20960,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0111xxxxxxxxxxxx setgmtn. */ - return 2877; + return 2893; } } else @@ -20793,7 +20969,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011101x1xxxxxx1111xxxxxxxxxxxx cpymtn. */ - return 2853; + return 2869; } } } @@ -20960,7 +21136,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110xx0xxxxx1x1001xxxxxxxxxx smmla. */ - return 2734; + return 2750; } } } @@ -20993,7 +21169,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110xx0xxxxx1x0101xxxxxxxxxx sdot. */ - return 2660; + return 2676; } } else @@ -21067,7 +21243,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110xx0xxxxx1x1011xxxxxxxxxx usmmla. */ - return 2736; + return 2752; } } } @@ -21100,7 +21276,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110xx0xxxxx1x0111xxxxxxxxxx usdot. */ - return 2737; + return 2753; } } else @@ -21147,7 +21323,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110000xxxxxxxxxxxxxxxxxxxxx eor3. */ - return 2667; + return 2683; } else { @@ -21155,7 +21331,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110100xxxxxxxxxxxxxxxxxxxxx xar. */ - return 2669; + return 2685; } } else @@ -21166,7 +21342,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110x10xxxxx0xxxxxxxxxxxxxxx sm3ss1. */ - return 2671; + return 2687; } else { @@ -21180,7 +21356,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110010xxxxx1xxx00xxxxxxxxxx sm3tt1a. */ - return 2672; + return 2688; } else { @@ -21188,7 +21364,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110110xxxxx1xxx00xxxxxxxxxx sha512su0. */ - return 2665; + return 2681; } } else @@ -21197,7 +21373,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110x10xxxxx1xxx10xxxxxxxxxx sm3tt2a. */ - return 2674; + return 2690; } } else @@ -21210,7 +21386,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110010xxxxx1xxx01xxxxxxxxxx sm3tt1b. */ - return 2673; + return 2689; } else { @@ -21218,7 +21394,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110110xxxxx1xxx01xxxxxxxxxx sm4e. */ - return 2678; + return 2694; } } else @@ -21227,7 +21403,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110x10xxxxx1xxx11xxxxxxxxxx sm3tt2b. */ - return 2675; + return 2691; } } } @@ -21408,7 +21584,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx101110xx0xxxxx100101xxxxxxxxxx udot. */ - return 2659; + return 2675; } } else @@ -21439,7 +21615,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx101110xx0xxxxx101x01xxxxxxxxxx ummla. */ - return 2735; + return 2751; } else { @@ -21458,7 +21634,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx101110xx0xxxxx1x1011xxxxxxxxxx bfmmla. */ - return 2751; + return 2767; } else { @@ -21468,7 +21644,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx1011100x0xxxxx1x1111xxxxxxxxxx bfdot. */ - return 2749; + return 2765; } else { @@ -21478,7 +21654,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x01011101x0xxxxx1x1111xxxxxxxxxx bfmlalb. */ - return 2756; + return 2772; } else { @@ -21486,7 +21662,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11011101x0xxxxx1x1111xxxxxxxxxx bfmlalt. */ - return 2755; + return 2771; } } } @@ -22070,7 +22246,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000011101x1xxxx1011010xxxxxxxxxx bfcvtn. */ - return 2752; + return 2768; } else { @@ -22078,7 +22254,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010011101x1xxxx1011010xxxxxxxxxx bfcvtn2. */ - return 2753; + return 2769; } } } @@ -22396,7 +22572,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110xx1xxxxx0xxxxxxxxxxxxxxx bcax. */ - return 2670; + return 2686; } } else @@ -23007,7 +23183,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 11001110xx1xxxxx100000xxxxxxxxxx sha512h. */ - return 2663; + return 2679; } } } @@ -23059,7 +23235,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 11001110xx1xxxxx110000xxxxxxxxxx sm3partw1. */ - return 2676; + return 2692; } } } @@ -23302,7 +23478,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110xx1xxxxx100010xxxxxxxxxx sha512su1. */ - return 2666; + return 2682; } } else @@ -23378,7 +23554,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x0011100x1xxxxx110010xxxxxxxxxx sm4ekey. */ - return 2679; + return 2695; } } else @@ -24204,7 +24380,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110xx1xxxxx100001xxxxxxxxxx sha512h2. */ - return 2664; + return 2680; } } else @@ -24236,7 +24412,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x0011100x1xxxxx110001xxxxxxxxxx sm3partw2. */ - return 2677; + return 2693; } } else @@ -24476,7 +24652,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110xx1xxxxx100011xxxxxxxxxx rax1. */ - return 2668; + return 2684; } } else @@ -24508,7 +24684,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x01011100x1xxxxx110011xxxxxxxxxx fmlal2. */ - return 2682; + return 2698; } else { @@ -24516,7 +24692,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11011100x1xxxxx110011xxxxxxxxxx fmlal2. */ - return 2686; + return 2702; } } } @@ -24538,7 +24714,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x01011101x1xxxxx110011xxxxxxxxxx fmlsl2. */ - return 2683; + return 2699; } else { @@ -24546,7 +24722,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11011101x1xxxxx110011xxxxxxxxxx fmlsl2. */ - return 2687; + return 2703; } } } @@ -24585,7 +24761,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x00011100x1xxxxx111011xxxxxxxxxx fmlal. */ - return 2680; + return 2696; } else { @@ -24593,7 +24769,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10011100x1xxxxx111011xxxxxxxxxx fmlal. */ - return 2684; + return 2700; } } else @@ -24615,7 +24791,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x00011101x1xxxxx111011xxxxxxxxxx fmlsl. */ - return 2681; + return 2697; } else { @@ -24623,7 +24799,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10011101x1xxxxx111011xxxxxxxxxx fmlsl. */ - return 2685; + return 2701; } } else @@ -26431,7 +26607,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0001111xxxxxxxx0000x0xxxxxxxxxx fmlal. */ - return 2688; + return 2704; } else { @@ -26439,7 +26615,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1001111xxxxxxxx0000x0xxxxxxxxxx fmlal. */ - return 2692; + return 2708; } } else @@ -26461,7 +26637,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0001111xxxxxxxx0100x0xxxxxxxxxx fmlsl. */ - return 2689; + return 2705; } else { @@ -26469,7 +26645,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1001111xxxxxxxx0100x0xxxxxxxxxx fmlsl. */ - return 2693; + return 2709; } } else @@ -26975,7 +27151,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0101111xxxxxxxx1000x0xxxxxxxxxx fmlal2. */ - return 2690; + return 2706; } else { @@ -26983,7 +27159,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1101111xxxxxxxx1000x0xxxxxxxxxx fmlal2. */ - return 2694; + return 2710; } } } @@ -27005,7 +27181,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0101111xxxxxxxx1100x0xxxxxxxxxx fmlsl2. */ - return 2691; + return 2707; } else { @@ -27013,7 +27189,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1101111xxxxxxxx1100x0xxxxxxxxxx fmlsl2. */ - return 2695; + return 2711; } } } @@ -27069,7 +27245,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx001111xxxxxxxx1110x0xxxxxxxxxx sdot. */ - return 2662; + return 2678; } else { @@ -27077,7 +27253,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx101111xxxxxxxx1110x0xxxxxxxxxx udot. */ - return 2661; + return 2677; } } } @@ -27180,7 +27356,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx00111100xxxxxx1111x0xxxxxxxxxx sudot. */ - return 2739; + return 2755; } else { @@ -27188,7 +27364,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx00111110xxxxxx1111x0xxxxxxxxxx usdot. */ - return 2738; + return 2754; } } else @@ -27199,7 +27375,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx00111101xxxxxx1111x0xxxxxxxxxx bfdot. */ - return 2750; + return 2766; } else { @@ -27209,7 +27385,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x000111111xxxxxx1111x0xxxxxxxxxx bfmlalb. */ - return 2758; + return 2774; } else { @@ -27217,7 +27393,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x100111111xxxxxx1111x0xxxxxxxxxx bfmlalt. */ - return 2757; + return 2773; } } } @@ -27708,22 +27884,22 @@ aarch64_find_next_opcode (const aarch64_opcode *opcode) case 2391: return NULL; /* mova --> NULL. */ case 2388: value = 2390; break; /* mov --> mova. */ case 2390: return NULL; /* mova --> NULL. */ - case 2534: value = 2542; break; /* mov --> mova. */ - case 2542: return NULL; /* mova --> NULL. */ - case 2530: value = 2538; break; /* mov --> mova. */ - case 2538: return NULL; /* mova --> NULL. */ - case 2532: value = 2540; break; /* mov --> mova. */ - case 2540: return NULL; /* mova --> NULL. */ - case 2528: value = 2536; break; /* mov --> mova. */ - case 2536: return NULL; /* mova --> NULL. */ - case 2535: value = 2543; break; /* mov --> mova. */ - case 2543: return NULL; /* mova --> NULL. */ - case 2531: value = 2539; break; /* mov --> mova. */ - case 2539: return NULL; /* mova --> NULL. */ - case 2533: value = 2541; break; /* mov --> mova. */ - case 2541: return NULL; /* mova --> NULL. */ - case 2529: value = 2537; break; /* mov --> mova. */ - case 2537: return NULL; /* mova --> NULL. */ + case 2546: value = 2554; break; /* mov --> mova. */ + case 2554: return NULL; /* mova --> NULL. */ + case 2542: value = 2550; break; /* mov --> mova. */ + case 2550: return NULL; /* mova --> NULL. */ + case 2544: value = 2552; break; /* mov --> mova. */ + case 2552: return NULL; /* mova --> NULL. */ + case 2540: value = 2548; break; /* mov --> mova. */ + case 2548: return NULL; /* mova --> NULL. */ + case 2547: value = 2555; break; /* mov --> mova. */ + case 2555: return NULL; /* mova --> NULL. */ + case 2543: value = 2551; break; /* mov --> mova. */ + case 2551: return NULL; /* mova --> NULL. */ + case 2545: value = 2553; break; /* mov --> mova. */ + case 2553: return NULL; /* mova --> NULL. */ + case 2541: value = 2549; break; /* mov --> mova. */ + case 2549: return NULL; /* mova --> NULL. */ case 2393: value = 2398; break; /* ld1b --> ld1b. */ case 2398: return NULL; /* ld1b --> NULL. */ case 2395: value = 2400; break; /* ld1w --> ld1w. */ @@ -27745,11 +27921,11 @@ aarch64_find_next_opcode (const aarch64_opcode *opcode) case 2407: value = 2412; break; /* st1q --> st1q. */ case 2412: return NULL; /* st1q --> NULL. */ case 12: value = 19; break; /* add --> addg. */ - case 19: value = 2880; break; /* addg --> smax. */ - case 2880: value = 2881; break; /* smax --> umax. */ - case 2881: value = 2882; break; /* umax --> smin. */ - case 2882: value = 2883; break; /* smin --> umin. */ - case 2883: return NULL; /* umin --> NULL. */ + case 19: value = 2896; break; /* addg --> smax. */ + case 2896: value = 2897; break; /* smax --> umax. */ + case 2897: value = 2898; break; /* umax --> smin. */ + case 2898: value = 2899; break; /* smin --> umin. */ + case 2899: return NULL; /* umin --> NULL. */ case 16: value = 20; break; /* sub --> subg. */ case 20: return NULL; /* subg --> NULL. */ case 971: value = 975; break; /* stnp --> stp. */ @@ -27907,8 +28083,8 @@ aarch64_find_next_opcode (const aarch64_opcode *opcode) case 824: return NULL; /* fsqrt --> NULL. */ case 832: value = 833; break; /* frintz --> frintz. */ case 833: return NULL; /* frintz --> NULL. */ - case 825: value = 2754; break; /* fcvt --> bfcvt. */ - case 2754: return NULL; /* bfcvt --> NULL. */ + case 825: value = 2770; break; /* fcvt --> bfcvt. */ + case 2770: return NULL; /* bfcvt --> NULL. */ case 834: value = 835; break; /* frinta --> frinta. */ case 835: return NULL; /* frinta --> NULL. */ case 836: value = 837; break; /* frintx --> frintx. */ @@ -28437,7 +28613,7 @@ aarch64_extract_operand (const aarch64_operand *self, case 33: case 34: case 35: - case 257: + case 259: return aarch64_ext_reglane (self, info, code, inst, errors); case 36: return aarch64_ext_reglist (self, info, code, inst, errors); @@ -28484,12 +28660,12 @@ aarch64_extract_operand (const aarch64_operand *self, case 193: case 194: case 237: - case 251: - case 252: + case 253: case 254: case 256: - case 261: - case 262: + case 258: + case 263: + case 264: return aarch64_ext_imm (self, info, code, inst, errors); case 44: case 45: @@ -28560,8 +28736,8 @@ aarch64_extract_operand (const aarch64_operand *self, case 107: return aarch64_ext_prfop (self, info, code, inst, errors); case 108: - case 253: case 255: + case 257: return aarch64_ext_none (self, info, code, inst, errors); case 109: return aarch64_ext_hint (self, info, code, inst, errors); @@ -28680,6 +28856,8 @@ aarch64_extract_operand (const aarch64_operand *self, case 248: case 249: case 250: + case 251: + case 252: return aarch64_ext_simple_index (self, info, code, inst, errors); case 239: case 240: @@ -28691,9 +28869,9 @@ aarch64_extract_operand (const aarch64_operand *self, return aarch64_ext_sme_sm_za (self, info, code, inst, errors); case 244: return aarch64_ext_sme_pred_reg_with_index (self, info, code, inst, errors); - case 258: - case 259: case 260: + case 261: + case 262: return aarch64_ext_x0_to_x30 (self, info, code, inst, errors); default: assert (0); abort (); } diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c index 8658d07bf39..51415ceb033 100644 --- a/opcodes/aarch64-opc-2.c +++ b/opcodes/aarch64-opc-2.c @@ -269,6 +269,8 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_ADDRESS, "SME_ADDR_RI_U4xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_imm4_0}, "memory offset"}, {AARCH64_OPND_CLASS_ADDRESS, "SME_SM_ZA", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm}, "streaming mode"}, {AARCH64_OPND_CLASS_SVE_REG, "SME_PnT_Wm_imm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rm,FLD_SVE_Pn,FLD_SME_i1,FLD_SME_tszh,FLD_SME_tszl}, "Source scalable predicate register with index "}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm, FLD_imm1_10}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm, FLD_imm2_10}, "an indexed SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX1_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm1_16}, "an indexed SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX2_15", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm2_15}, "an indexed SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX2_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm2_16}, "an indexed SVE vector register"}, diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index d9cc0544e82..cd37f8ac910 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -320,8 +320,10 @@ const aarch64_field fields[] = { 5, 5 }, /* defgh: d:e:f:g:h bits in AdvSIMD modified immediate. */ { 21, 2 }, /* hw: in move wide constant instructions. */ { 8, 1 }, /* imm1_8: general immediate in bits [8]. */ + { 10, 1 }, /* imm1_10: general immediate in bits [10]. */ { 16, 1 }, /* imm1_16: general immediate in bits [16]. */ { 8, 2 }, /* imm2_8: general immediate in bits [9:8]. */ + { 10, 2 }, /* imm2_10: 2-bit immediate, bits [11:10] */ { 15, 2 }, /* imm2_15: 2-bit immediate, bits [16:15] */ { 16, 2 }, /* imm2_16: 2-bit immediate, bits [17:16] */ { 0, 3 }, /* imm3_0: general immediate in bits [2:0]. */ @@ -1765,6 +1767,14 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, return 0; break; + case AARCH64_OPND_SME_Zm_INDEX1: + case AARCH64_OPND_SME_Zm_INDEX2: + size = get_operand_fields_width (get_operand_from_code (type)) - 4; + if (!check_reglane (opnd, mismatch_detail, idx, "z", 0, 15, + 0, (1 << size) - 1)) + return 0; + break; + case AARCH64_OPND_SME_Zm: if (opnd->reg.regno > 15) { @@ -3926,6 +3936,8 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, case AARCH64_OPND_SVE_Zm4_11_INDEX: case AARCH64_OPND_SVE_Zm4_INDEX: case AARCH64_OPND_SVE_Zn_INDEX: + case AARCH64_OPND_SME_Zm_INDEX1: + case AARCH64_OPND_SME_Zm_INDEX2: case AARCH64_OPND_SME_Zn_INDEX1_16: case AARCH64_OPND_SME_Zn_INDEX2_15: case AARCH64_OPND_SME_Zn_INDEX2_16: diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h index 1284dd47d4d..b0084257a94 100644 --- a/opcodes/aarch64-opc.h +++ b/opcodes/aarch64-opc.h @@ -141,8 +141,10 @@ enum aarch64_field_kind FLD_defgh, FLD_hw, FLD_imm1_8, + FLD_imm1_10, FLD_imm1_16, FLD_imm2_8, + FLD_imm2_10, FLD_imm2_15, FLD_imm2_16, FLD_imm3_0, diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 9bcec954d53..434b76c010c 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -2509,6 +2509,8 @@ static const aarch64_feature_set aarch64_feature_sme_i16i64 = static const aarch64_feature_set aarch64_feature_sme2 = AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | AARCH64_FEATURE_SME | AARCH64_FEATURE_SME2, 0); +static const aarch64_feature_set aarch64_feature_sme2_f64f64 = + AARCH64_FEATURE (AARCH64_FEATURE_SME2 | AARCH64_FEATURE_SME_F64F64, 0); static const aarch64_feature_set aarch64_feature_v8_6 = AARCH64_FEATURE (AARCH64_FEATURE_V8_6, 0); static const aarch64_feature_set aarch64_feature_v8_7 = @@ -2578,6 +2580,7 @@ static const aarch64_feature_set aarch64_feature_cssc = #define SME_F64F64 &aarch64_feature_sme_f64f64 #define SME_I16I64 &aarch64_feature_sme_i16i64 #define SME2 &aarch64_feature_sme2 +#define SME2_F64F64 &aarch64_feature_sme2_f64f64 #define ARMV8_6 &aarch64_feature_v8_6 #define ARMV8_6_SVE &aarch64_feature_v8_6 #define BFLOAT16_SVE &aarch64_feature_bfloat16_sve @@ -2692,6 +2695,9 @@ static const aarch64_feature_set aarch64_feature_cssc = #define SME2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SME2, OPS, QUALS, \ F_STRICT | FLAGS, 0, TIED, NULL } +#define SME2_F64F64_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ + { NAME, OPCODE, MASK, CLASS, OP, SME2_F64F64, OPS, QUALS, \ + F_STRICT | FLAGS, 0, TIED, NULL } #define SVE2BITPERM_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SVE2_BITPERM, OPS, QUALS, \ FLAGS | F_STRICT, 0, TIED, NULL } @@ -5352,6 +5358,18 @@ const struct aarch64_opcode aarch64_opcode_table[] = SME2_INSN ("fminnm", 0xc120a921, 0xff30ffe3, sme_size_22_hsd, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zm), OP_SVE_VVV_HSD, 0, 1), SME2_INSN ("fminnm", 0xc120b121, 0xff21ffe1, sme_size_22_hsd, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zmx2), OP_SVE_VVV_HSD, 0, 1), SME2_INSN ("fminnm", 0xc120b921, 0xff23ffe3, sme_size_22_hsd, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zmx4), OP_SVE_VVV_HSD, 0, 1), + SME2_INSN ("fmla", 0xc1500000, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX2), OP_SVE_SSS, F_OD (2), 0), + SME2_INSN ("fmla", 0xc1508000, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX2), OP_SVE_SSS, F_OD (4), 0), + SME2_INSN ("fmla", 0xc1201800, 0xffb09c18, sme_fp_sd, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_VVV_SD, F_OD (2), 0), + SME2_INSN ("fmla", 0xc1301800, 0xffb09c18, sme_fp_sd, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_VVV_SD, F_OD (4), 0), + SME2_INSN ("fmla", 0xc1a01800, 0xffa19c38, sme_fp_sd, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zmx2), OP_SVE_VVV_SD, F_OD (2), 0), + SME2_INSN ("fmla", 0xc1a11800, 0xffa39c78, sme_fp_sd, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zmx4), OP_SVE_VVV_SD, F_OD (4), 0), + SME2_INSN ("fmls", 0xc1500010, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX2), OP_SVE_SSS, F_OD (2), 0), + SME2_INSN ("fmls", 0xc1508010, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX2), OP_SVE_SSS, F_OD (4), 0), + SME2_INSN ("fmls", 0xc1201808, 0xffb09c18, sme_fp_sd, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_VVV_SD, F_OD (2), 0), + SME2_INSN ("fmls", 0xc1301808, 0xffb09c18, sme_fp_sd, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_VVV_SD, F_OD (4), 0), + SME2_INSN ("fmls", 0xc1a01808, 0xffa19c38, sme_fp_sd, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zmx2), OP_SVE_VVV_SD, F_OD (2), 0), + SME2_INSN ("fmls", 0xc1a11808, 0xffa39c78, sme_fp_sd, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zmx4), OP_SVE_VVV_SD, F_OD (4), 0), SME2_INSN ("fsub", 0xc1a01c08, 0xffbf9c38, sme_fp_sd, 0, OP2 (SME_ZA_array_off3_0, SME_Znx2), OP_SVE_VVV_SD, F_OD (2), 0), SME2_INSN ("fsub", 0xc1a11c08, 0xffbf9c78, sme_fp_sd, 0, OP2 (SME_ZA_array_off3_0, SME_Znx4), OP_SVE_VVV_SD, F_OD (4), 0), SME2_INSN ("ld1b", 0xa0400000, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_BZU, 0, 0), @@ -5557,6 +5575,12 @@ const struct aarch64_opcode aarch64_opcode_table[] = SME2_INSN ("whilelt", 0x25204410, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0), SME2_INSN ("zero", 0xc0480001, 0xffffffff, sme_misc, 0, OP1 (SME_ZT0_LIST), {}, 0, 0), + /* SME2 F64F64 instructions. */ + SME2_F64F64_INSN ("fmla", 0xc1d00000, 0xfff09838, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX1), OP_SVE_DDD, F_OD (2), 0), + SME2_F64F64_INSN ("fmla", 0xc1d08000, 0xfff09878, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX1), OP_SVE_DDD, F_OD (4), 0), + SME2_F64F64_INSN ("fmls", 0xc1d00010, 0xfff09838, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX1), OP_SVE_DDD, F_OD (2), 0), + SME2_F64F64_INSN ("fmls", 0xc1d08010, 0xfff09878, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX1), OP_SVE_DDD, F_OD (4), 0), + /* SIMD Dot Product (optional in v8.2-A). */ DOT_INSN ("udot", 0x2e009400, 0xbf20fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ), DOT_INSN ("sdot", 0xe009400, 0xbf20fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ), @@ -6268,6 +6292,10 @@ const struct aarch64_opcode aarch64_opcode_table[] = Y(SVE_REG, sme_pred_reg_with_index, "SME_PnT_Wm_imm", 0, \ F(FLD_SME_Rm,FLD_SVE_Pn,FLD_SME_i1,FLD_SME_tszh,FLD_SME_tszl), \ "Source scalable predicate register with index ") \ + Y(SVE_REG, simple_index, "SME_Zm_INDEX1", 0, \ + F(FLD_SME_Zm, FLD_imm1_10), "an indexed SVE vector register") \ + Y(SVE_REG, simple_index, "SME_Zm_INDEX2", 0, \ + F(FLD_SME_Zm, FLD_imm2_10), "an indexed SVE vector register") \ Y(SVE_REG, simple_index, "SME_Zn_INDEX1_16", 0, \ F(FLD_SVE_Zn, FLD_imm1_16), "an indexed SVE vector register") \ Y(SVE_REG, simple_index, "SME_Zn_INDEX2_15", 0, \ From patchwork Thu Mar 30 10:26:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 77093 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1040509vqo; Thu, 30 Mar 2023 04:05:22 -0700 (PDT) X-Google-Smtp-Source: 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OpenDKIM Filter v2.11.0 sourceware.org B94D93836B92 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1680173113; bh=9nIk8XGb1N1LXfDAonsn4NR0NQvb+j50cDh2/cVKG+s=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=n5ghBarHSeem4EhCz9D85FxKpjfFVhUag6CwTxq/HR0ez4QuqqdiQUKunuFpiNF5e ftg18xkQoI1QQbtQvpWfAeQXMuUmTK+yhwUZg69hZDrJu0em1Bi73BVaHw4mfyR58l LNif/wwWyuJsrF1UoBO+0sxJm7YwJ9QKfqVrWiYA= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 90544389901C for ; Thu, 30 Mar 2023 10:27:10 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 90544389901C Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BCF031650; Thu, 30 Mar 2023 03:27:54 -0700 (PDT) Received: from e121540-lin.manchester.arm.com (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id F39013F663; Thu, 30 Mar 2023 03:27:09 -0700 (PDT) To: binutils@sourceware.org Cc: Richard Sandiford Subject: [PATCH 22/31] aarch64: Add the SME2 saturating conversion instructions Date: Thu, 30 Mar 2023 11:26:37 +0100 Message-Id: <20230330102646.3327818-23-richard.sandiford@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230330102646.3327818-1-richard.sandiford@arm.com> References: <20230330102646.3327818-1-richard.sandiford@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-32.0 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KAM_LOTSOFHASH, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Richard Sandiford via Binutils From: Richard Sandiford Reply-To: Richard Sandiford Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761790470165553988?= X-GMAIL-MSGID: =?utf-8?q?1761790470165553988?= There are two instruction formats here: - SQCVT, SQCVTU and UQCVT, which operate on lists of two or four registers. - SQCVTN, SQCVTUN and UQCVTN, which operate on lists of four registers. --- gas/testsuite/gas/aarch64/sme2-25-invalid.d | 3 + gas/testsuite/gas/aarch64/sme2-25-invalid.l | 48 + gas/testsuite/gas/aarch64/sme2-25-invalid.s | 28 + gas/testsuite/gas/aarch64/sme2-25-noarch.d | 3 + gas/testsuite/gas/aarch64/sme2-25-noarch.l | 37 + gas/testsuite/gas/aarch64/sme2-25.d | 45 + gas/testsuite/gas/aarch64/sme2-25.s | 44 + gas/testsuite/gas/aarch64/sme2-26-invalid.d | 3 + gas/testsuite/gas/aarch64/sme2-26-invalid.l | 13 + gas/testsuite/gas/aarch64/sme2-26-invalid.s | 14 + gas/testsuite/gas/aarch64/sme2-26-noarch.d | 3 + gas/testsuite/gas/aarch64/sme2-26-noarch.l | 25 + gas/testsuite/gas/aarch64/sme2-26.d | 33 + gas/testsuite/gas/aarch64/sme2-26.s | 29 + include/opcode/aarch64.h | 1 + opcodes/aarch64-asm.c | 5 + opcodes/aarch64-dis-2.c | 1035 ++++++++++--------- opcodes/aarch64-dis.c | 4 + opcodes/aarch64-opc.c | 1 + opcodes/aarch64-opc.h | 1 + opcodes/aarch64-tbl.h | 14 + 21 files changed, 921 insertions(+), 468 deletions(-) create mode 100644 gas/testsuite/gas/aarch64/sme2-25-invalid.d create mode 100644 gas/testsuite/gas/aarch64/sme2-25-invalid.l create mode 100644 gas/testsuite/gas/aarch64/sme2-25-invalid.s create mode 100644 gas/testsuite/gas/aarch64/sme2-25-noarch.d create mode 100644 gas/testsuite/gas/aarch64/sme2-25-noarch.l create mode 100644 gas/testsuite/gas/aarch64/sme2-25.d create mode 100644 gas/testsuite/gas/aarch64/sme2-25.s create mode 100644 gas/testsuite/gas/aarch64/sme2-26-invalid.d create mode 100644 gas/testsuite/gas/aarch64/sme2-26-invalid.l create mode 100644 gas/testsuite/gas/aarch64/sme2-26-invalid.s create mode 100644 gas/testsuite/gas/aarch64/sme2-26-noarch.d create mode 100644 gas/testsuite/gas/aarch64/sme2-26-noarch.l create mode 100644 gas/testsuite/gas/aarch64/sme2-26.d create mode 100644 gas/testsuite/gas/aarch64/sme2-26.s diff --git a/gas/testsuite/gas/aarch64/sme2-25-invalid.d b/gas/testsuite/gas/aarch64/sme2-25-invalid.d new file mode 100644 index 00000000000..62b23cd19a7 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-25-invalid.d @@ -0,0 +1,3 @@ +#as: -march=armv8-a +#source: sme2-25-invalid.s +#error_output: sme2-25-invalid.l diff --git a/gas/testsuite/gas/aarch64/sme2-25-invalid.l b/gas/testsuite/gas/aarch64/sme2-25-invalid.l new file mode 100644 index 00000000000..5b18a2ac99c --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-25-invalid.l @@ -0,0 +1,48 @@ +[^ :]+: Assembler messages: +[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqcvt 0,{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: expected '{' at operand 2 -- `sqcvt z0\.h,0' +[^ :]+:[0-9]+: Error: operand mismatch -- `sqcvt z0\.s,{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: sqcvt z0\.b, {z0\.s-z1\.s} +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: sqcvt z0\.h, {z0\.d-z1\.d} +[^ :]+:[0-9]+: Error: operand mismatch -- `sqcvt z0\.b,{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: sqcvt z0\.b, {z0\.s-z1\.s} +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: sqcvt z0\.h, {z0\.d-z1\.d} +[^ :]+:[0-9]+: Error: operand mismatch -- `sqcvt z0\.s,{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: sqcvt z0\.h, {z0\.d-z1\.d} +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: sqcvt z0\.b, {z0\.s-z1\.s} +[^ :]+:[0-9]+: Error: operand mismatch -- `sqcvt z0\.s,{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: sqcvt z0\.b, {z0\.s-z3\.s} +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: sqcvt z0\.h, {z0\.d-z3\.d} +[^ :]+:[0-9]+: Error: operand mismatch -- `sqcvt z0\.b,{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: sqcvt z0\.b, {z0\.s-z3\.s} +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: sqcvt z0\.h, {z0\.d-z3\.d} +[^ :]+:[0-9]+: Error: operand mismatch -- `sqcvt z0\.s,{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: sqcvt z0\.h, {z0\.d-z3\.d} +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: sqcvt z0\.b, {z0\.s-z3\.s} +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `sqcvt z0\.h,{z0\.s-z2\.s}' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `sqcvt z0\.h,{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: the register list must have a stride of 1 at operand 2 -- `sqcvt z0\.h,{z0\.s,z8\.s}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqcvt z0\.h,{z1\.s-z2\.s}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqcvt z0\.h,{z31\.s,z0\.s}' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `sqcvt z0\.b,{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `sqcvt z0\.b,{z0\.s-z2\.s}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqcvt z0\.b,{z1\.s-z4\.s}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqcvt z0\.b,{z2\.s-z5\.s}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqcvt z0\.b,{z3\.s-z6\.s}' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `sqcvt z0\.h,{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `sqcvt z0\.h,{z0\.d-z2\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqcvt z0\.h,{z1\.d-z4\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqcvt z0\.h,{z2\.d-z5\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqcvt z0\.h,{z3\.d-z6\.d}' diff --git a/gas/testsuite/gas/aarch64/sme2-25-invalid.s b/gas/testsuite/gas/aarch64/sme2-25-invalid.s new file mode 100644 index 00000000000..10395f75c40 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-25-invalid.s @@ -0,0 +1,28 @@ + sqcvt 0, { z0.s - z1.s } + sqcvt z0.h, 0 + + sqcvt z0.s, { z0.s - z1.s } + sqcvt z0.b, { z0.d - z1.d } + sqcvt z0.s, { z0.d - z1.d } + + sqcvt z0.s, { z0.s - z3.s } + sqcvt z0.b, { z0.d - z3.d } + sqcvt z0.s, { z0.d - z3.d } + + sqcvt z0.h, { z0.s - z2.s } + sqcvt z0.h, { z0.s - z3.s } + sqcvt z0.h, { z0.s, z8.s } + sqcvt z0.h, { z1.s - z2.s } + sqcvt z0.h, { z31.s, z0.s } + + sqcvt z0.b, { z0.s - z1.s } + sqcvt z0.b, { z0.s - z2.s } + sqcvt z0.b, { z1.s - z4.s } + sqcvt z0.b, { z2.s - z5.s } + sqcvt z0.b, { z3.s - z6.s } + + sqcvt z0.h, { z0.d - z1.d } + sqcvt z0.h, { z0.d - z2.d } + sqcvt z0.h, { z1.d - z4.d } + sqcvt z0.h, { z2.d - z5.d } + sqcvt z0.h, { z3.d - z6.d } diff --git a/gas/testsuite/gas/aarch64/sme2-25-noarch.d b/gas/testsuite/gas/aarch64/sme2-25-noarch.d new file mode 100644 index 00000000000..e1e9d3968c8 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-25-noarch.d @@ -0,0 +1,3 @@ +#as: -march=armv8-a+sme +#source: sme2-25.s +#error_output: sme2-25-noarch.l diff --git a/gas/testsuite/gas/aarch64/sme2-25-noarch.l b/gas/testsuite/gas/aarch64/sme2-25-noarch.l new file mode 100644 index 00000000000..66998fffd32 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-25-noarch.l @@ -0,0 +1,37 @@ +[^ :]+: Assembler messages: +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvt z0\.h,{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvt z31\.h,{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvt z0\.h,{z30\.s-z31\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvt z19\.h,{z14\.s-z15\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvt z0\.b,{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvt z31\.b,{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvt z0\.b,{z28\.s-z31\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvt z11\.b,{z20\.s-z23\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvt z0\.h,{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvt z31\.h,{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvt z0\.h,{z28\.d-z31\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvt z22\.h,{z4\.d-z7\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtu z0\.h,{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtu z31\.h,{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtu z0\.h,{z30\.s-z31\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtu z19\.h,{z14\.s-z15\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtu z0\.b,{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtu z31\.b,{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtu z0\.b,{z28\.s-z31\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtu z11\.b,{z20\.s-z23\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtu z0\.h,{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtu z31\.h,{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtu z0\.h,{z28\.d-z31\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtu z22\.h,{z4\.d-z7\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `uqcvt z0\.h,{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `uqcvt z31\.h,{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `uqcvt z0\.h,{z30\.s-z31\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `uqcvt z19\.h,{z14\.s-z15\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `uqcvt z0\.b,{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `uqcvt z31\.b,{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `uqcvt z0\.b,{z28\.s-z31\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `uqcvt z11\.b,{z20\.s-z23\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `uqcvt z0\.h,{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `uqcvt z31\.h,{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `uqcvt z0\.h,{z28\.d-z31\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `uqcvt z22\.h,{z4\.d-z7\.d}' diff --git a/gas/testsuite/gas/aarch64/sme2-25.d b/gas/testsuite/gas/aarch64/sme2-25.d new file mode 100644 index 00000000000..b2fdce756c3 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-25.d @@ -0,0 +1,45 @@ +#as: -march=armv8-a+sme2 +#objdump: -dr + +[^:]+: file format .* + + +[^:]+: + +[^:]+: +[^:]+: c123e000 sqcvt z0\.h, {z0\.s-z1\.s} +[^:]+: c123e01f sqcvt z31\.h, {z0\.s-z1\.s} +[^:]+: c123e3c0 sqcvt z0\.h, {z30\.s-z31\.s} +[^:]+: c123e1d3 sqcvt z19\.h, {z14\.s-z15\.s} +[^:]+: c133e000 sqcvt z0\.b, {z0\.s-z3\.s} +[^:]+: c133e01f sqcvt z31\.b, {z0\.s-z3\.s} +[^:]+: c133e380 sqcvt z0\.b, {z28\.s-z31\.s} +[^:]+: c133e28b sqcvt z11\.b, {z20\.s-z23\.s} +[^:]+: c1b3e000 sqcvt z0\.h, {z0\.d-z3\.d} +[^:]+: c1b3e01f sqcvt z31\.h, {z0\.d-z3\.d} +[^:]+: c1b3e380 sqcvt z0\.h, {z28\.d-z31\.d} +[^:]+: c1b3e096 sqcvt z22\.h, {z4\.d-z7\.d} +[^:]+: c163e000 sqcvtu z0\.h, {z0\.s-z1\.s} +[^:]+: c163e01f sqcvtu z31\.h, {z0\.s-z1\.s} +[^:]+: c163e3c0 sqcvtu z0\.h, {z30\.s-z31\.s} +[^:]+: c163e1d3 sqcvtu z19\.h, {z14\.s-z15\.s} +[^:]+: c173e000 sqcvtu z0\.b, {z0\.s-z3\.s} +[^:]+: c173e01f sqcvtu z31\.b, {z0\.s-z3\.s} +[^:]+: c173e380 sqcvtu z0\.b, {z28\.s-z31\.s} +[^:]+: c173e28b sqcvtu z11\.b, {z20\.s-z23\.s} +[^:]+: c1f3e000 sqcvtu z0\.h, {z0\.d-z3\.d} +[^:]+: c1f3e01f sqcvtu z31\.h, {z0\.d-z3\.d} +[^:]+: c1f3e380 sqcvtu z0\.h, {z28\.d-z31\.d} +[^:]+: c1f3e096 sqcvtu z22\.h, {z4\.d-z7\.d} +[^:]+: c123e020 uqcvt z0\.h, {z0\.s-z1\.s} +[^:]+: c123e03f uqcvt z31\.h, {z0\.s-z1\.s} +[^:]+: c123e3e0 uqcvt z0\.h, {z30\.s-z31\.s} +[^:]+: c123e1f3 uqcvt z19\.h, {z14\.s-z15\.s} +[^:]+: c133e020 uqcvt z0\.b, {z0\.s-z3\.s} +[^:]+: c133e03f uqcvt z31\.b, {z0\.s-z3\.s} +[^:]+: c133e3a0 uqcvt z0\.b, {z28\.s-z31\.s} +[^:]+: c133e2ab uqcvt z11\.b, {z20\.s-z23\.s} +[^:]+: c1b3e020 uqcvt z0\.h, {z0\.d-z3\.d} +[^:]+: c1b3e03f uqcvt z31\.h, {z0\.d-z3\.d} +[^:]+: c1b3e3a0 uqcvt z0\.h, {z28\.d-z31\.d} +[^:]+: c1b3e0b6 uqcvt z22\.h, {z4\.d-z7\.d} diff --git a/gas/testsuite/gas/aarch64/sme2-25.s b/gas/testsuite/gas/aarch64/sme2-25.s new file mode 100644 index 00000000000..45a2a70b021 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-25.s @@ -0,0 +1,44 @@ + sqcvt z0.h, { z0.s - z1.s } + sqcvt z31.h, { z0.s - z1.s } + sqcvt z0.h, { z30.s - z31.s } + sqcvt z19.h, { z14.s - z15.s } + + sqcvt z0.b, { z0.s - z3.s } + sqcvt z31.b, { z0.s - z3.s } + sqcvt z0.b, { z28.s - z31.s } + sqcvt z11.b, { z20.s - z23.s } + + sqcvt z0.h, { z0.d - z3.d } + sqcvt z31.h, { z0.d - z3.d } + sqcvt z0.h, { z28.d - z31.d } + sqcvt z22.h, { z4.d - z7.d } + + sqcvtu z0.h, { z0.s - z1.s } + sqcvtu z31.h, { z0.s - z1.s } + sqcvtu z0.h, { z30.s - z31.s } + sqcvtu z19.h, { z14.s - z15.s } + + sqcvtu z0.b, { z0.s - z3.s } + sqcvtu z31.b, { z0.s - z3.s } + sqcvtu z0.b, { z28.s - z31.s } + sqcvtu z11.b, { z20.s - z23.s } + + sqcvtu z0.h, { z0.d - z3.d } + sqcvtu z31.h, { z0.d - z3.d } + sqcvtu z0.h, { z28.d - z31.d } + sqcvtu z22.h, { z4.d - z7.d } + + uqcvt z0.h, { z0.s - z1.s } + uqcvt z31.h, { z0.s - z1.s } + uqcvt z0.h, { z30.s - z31.s } + uqcvt z19.h, { z14.s - z15.s } + + uqcvt z0.b, { z0.s - z3.s } + uqcvt z31.b, { z0.s - z3.s } + uqcvt z0.b, { z28.s - z31.s } + uqcvt z11.b, { z20.s - z23.s } + + uqcvt z0.h, { z0.d - z3.d } + uqcvt z31.h, { z0.d - z3.d } + uqcvt z0.h, { z28.d - z31.d } + uqcvt z22.h, { z4.d - z7.d } diff --git a/gas/testsuite/gas/aarch64/sme2-26-invalid.d b/gas/testsuite/gas/aarch64/sme2-26-invalid.d new file mode 100644 index 00000000000..5e336bf0905 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-26-invalid.d @@ -0,0 +1,3 @@ +#as: -march=armv8-a +#source: sme2-26-invalid.s +#error_output: sme2-26-invalid.l diff --git a/gas/testsuite/gas/aarch64/sme2-26-invalid.l b/gas/testsuite/gas/aarch64/sme2-26-invalid.l new file mode 100644 index 00000000000..08c2f7fc7af --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-26-invalid.l @@ -0,0 +1,13 @@ +[^ :]+: Assembler messages: +[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqcvtn 0,{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: expected '{' at operand 2 -- `sqcvtn z0\.b,0' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `sqcvtn z0\.b,{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `sqcvtn z0\.b,{z0\.s-z2\.s}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqcvtn z0\.b,{z1\.s-z4\.s}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqcvtn z0\.b,{z2\.s-z5\.s}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqcvtn z0\.b,{z3\.s-z6\.s}' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `sqcvtn z0\.h,{z0\.d-z1\.d}' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `sqcvtn z0\.h,{z0\.d-z2\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqcvtn z0\.h,{z1\.d-z4\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqcvtn z0\.h,{z2\.d-z5\.d}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqcvtn z0\.h,{z3\.d-z6\.d}' diff --git a/gas/testsuite/gas/aarch64/sme2-26-invalid.s b/gas/testsuite/gas/aarch64/sme2-26-invalid.s new file mode 100644 index 00000000000..2eddec902b2 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-26-invalid.s @@ -0,0 +1,14 @@ + sqcvtn 0, { z0.s - z3.s } + sqcvtn z0.b, 0 + + sqcvtn z0.b, { z0.s - z1.s } + sqcvtn z0.b, { z0.s - z2.s } + sqcvtn z0.b, { z1.s - z4.s } + sqcvtn z0.b, { z2.s - z5.s } + sqcvtn z0.b, { z3.s - z6.s } + + sqcvtn z0.h, { z0.d - z1.d } + sqcvtn z0.h, { z0.d - z2.d } + sqcvtn z0.h, { z1.d - z4.d } + sqcvtn z0.h, { z2.d - z5.d } + sqcvtn z0.h, { z3.d - z6.d } diff --git a/gas/testsuite/gas/aarch64/sme2-26-noarch.d b/gas/testsuite/gas/aarch64/sme2-26-noarch.d new file mode 100644 index 00000000000..e9af412a1e0 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-26-noarch.d @@ -0,0 +1,3 @@ +#as: -march=armv8-a+sme +#source: sme2-26.s +#error_output: sme2-26-noarch.l diff --git a/gas/testsuite/gas/aarch64/sme2-26-noarch.l b/gas/testsuite/gas/aarch64/sme2-26-noarch.l new file mode 100644 index 00000000000..b1bd4899d5e --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-26-noarch.l @@ -0,0 +1,25 @@ +[^ :]+: Assembler messages: +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtn z0\.b,{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtn z31\.b,{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtn z0\.b,{z28\.s-z31\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtn z11\.b,{z20\.s-z23\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtn z0\.h,{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtn z31\.h,{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtn z0\.h,{z28\.d-z31\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtn z22\.h,{z4\.d-z7\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtun z0\.b,{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtun z31\.b,{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtun z0\.b,{z28\.s-z31\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtun z11\.b,{z20\.s-z23\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtun z0\.h,{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtun z31\.h,{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtun z0\.h,{z28\.d-z31\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtun z22\.h,{z4\.d-z7\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `uqcvtn z0\.b,{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `uqcvtn z31\.b,{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `uqcvtn z0\.b,{z28\.s-z31\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `uqcvtn z11\.b,{z20\.s-z23\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `uqcvtn z0\.h,{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `uqcvtn z31\.h,{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `uqcvtn z0\.h,{z28\.d-z31\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `uqcvtn z22\.h,{z4\.d-z7\.d}' diff --git a/gas/testsuite/gas/aarch64/sme2-26.d b/gas/testsuite/gas/aarch64/sme2-26.d new file mode 100644 index 00000000000..96e0ca990f6 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-26.d @@ -0,0 +1,33 @@ +#as: -march=armv8-a+sme2 +#objdump: -dr + +[^:]+: file format .* + + +[^:]+: + +[^:]+: +[^:]+: c133e040 sqcvtn z0\.b, {z0\.s-z3\.s} +[^:]+: c133e05f sqcvtn z31\.b, {z0\.s-z3\.s} +[^:]+: c133e3c0 sqcvtn z0\.b, {z28\.s-z31\.s} +[^:]+: c133e2cb sqcvtn z11\.b, {z20\.s-z23\.s} +[^:]+: c1b3e040 sqcvtn z0\.h, {z0\.d-z3\.d} +[^:]+: c1b3e05f sqcvtn z31\.h, {z0\.d-z3\.d} +[^:]+: c1b3e3c0 sqcvtn z0\.h, {z28\.d-z31\.d} +[^:]+: c1b3e0d6 sqcvtn z22\.h, {z4\.d-z7\.d} +[^:]+: c173e040 sqcvtun z0\.b, {z0\.s-z3\.s} +[^:]+: c173e05f sqcvtun z31\.b, {z0\.s-z3\.s} +[^:]+: c173e3c0 sqcvtun z0\.b, {z28\.s-z31\.s} +[^:]+: c173e2cb sqcvtun z11\.b, {z20\.s-z23\.s} +[^:]+: c1f3e040 sqcvtun z0\.h, {z0\.d-z3\.d} +[^:]+: c1f3e05f sqcvtun z31\.h, {z0\.d-z3\.d} +[^:]+: c1f3e3c0 sqcvtun z0\.h, {z28\.d-z31\.d} +[^:]+: c1f3e0d6 sqcvtun z22\.h, {z4\.d-z7\.d} +[^:]+: c133e060 uqcvtn z0\.b, {z0\.s-z3\.s} +[^:]+: c133e07f uqcvtn z31\.b, {z0\.s-z3\.s} +[^:]+: c133e3e0 uqcvtn z0\.b, {z28\.s-z31\.s} +[^:]+: c133e2eb uqcvtn z11\.b, {z20\.s-z23\.s} +[^:]+: c1b3e060 uqcvtn z0\.h, {z0\.d-z3\.d} +[^:]+: c1b3e07f uqcvtn z31\.h, {z0\.d-z3\.d} +[^:]+: c1b3e3e0 uqcvtn z0\.h, {z28\.d-z31\.d} +[^:]+: c1b3e0f6 uqcvtn z22\.h, {z4\.d-z7\.d} diff --git a/gas/testsuite/gas/aarch64/sme2-26.s b/gas/testsuite/gas/aarch64/sme2-26.s new file mode 100644 index 00000000000..72bdbf68676 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-26.s @@ -0,0 +1,29 @@ + sqcvtn z0.b, { z0.s - z3.s } + sqcvtn z31.b, { z0.s - z3.s } + sqcvtn z0.b, { z28.s - z31.s } + sqcvtn z11.b, { z20.s - z23.s } + + sqcvtn z0.h, { z0.d - z3.d } + sqcvtn z31.h, { z0.d - z3.d } + sqcvtn z0.h, { z28.d - z31.d } + sqcvtn z22.h, { z4.d - z7.d } + + sqcvtun z0.b, { z0.s - z3.s } + sqcvtun z31.b, { z0.s - z3.s } + sqcvtun z0.b, { z28.s - z31.s } + sqcvtun z11.b, { z20.s - z23.s } + + sqcvtun z0.h, { z0.d - z3.d } + sqcvtun z31.h, { z0.d - z3.d } + sqcvtun z0.h, { z28.d - z31.d } + sqcvtun z22.h, { z4.d - z7.d } + + uqcvtn z0.b, { z0.s - z3.s } + uqcvtn z31.b, { z0.s - z3.s } + uqcvtn z0.b, { z28.s - z31.s } + uqcvtn z11.b, { z20.s - z23.s } + + uqcvtn z0.h, { z0.d - z3.d } + uqcvtn z31.h, { z0.d - z3.d } + uqcvtn z0.h, { z28.d - z31.d } + uqcvtn z22.h, { z4.d - z7.d } diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index f18f383a711..b445bf758fc 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -717,6 +717,7 @@ enum aarch64_insn_class sme_size_12_hs, sme_size_22, sme_size_22_hsd, + sme_sz_23, sme_str, sme_start, sme_stop, diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c index b1d2d589a13..5f2e51044ce 100644 --- a/opcodes/aarch64-asm.c +++ b/opcodes/aarch64-asm.c @@ -1970,6 +1970,11 @@ aarch64_encode_variant_using_iclass (struct aarch64_inst *inst) aarch64_get_variant (inst) + 1, 0); break; + case sme_sz_23: + insert_field (FLD_SME_sz_23, &inst->value, + aarch64_get_variant (inst), 0); + break; + case sve_cpy: insert_fields (&inst->value, aarch64_get_variant (inst), 0, 2, FLD_SVE_M_14, FLD_size); diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c index 759f6ab3611..55a01e6e593 100644 --- a/opcodes/aarch64-dis-2.c +++ b/opcodes/aarch64-dis-2.c @@ -188,7 +188,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000x10x100xxxxxxxxxxxxxxxxx zero. */ - return 2865; + return 2874; } } } @@ -856,7 +856,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx000xxxxxxxxxxxx0 st1b. */ - return 2699; + return 2705; } else { @@ -864,7 +864,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx100xxxxxxxxxxxx0 st1b. */ - return 2700; + return 2706; } } else @@ -875,7 +875,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx010xxxxxxxxxxxx0 st1w. */ - return 2723; + return 2729; } else { @@ -883,7 +883,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx110xxxxxxxxxxxx0 st1w. */ - return 2724; + return 2730; } } } @@ -897,7 +897,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx001xxxxxxxxxxxx0 st1h. */ - return 2715; + return 2721; } else { @@ -905,7 +905,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx101xxxxxxxxxxxx0 st1h. */ - return 2716; + return 2722; } } else @@ -916,7 +916,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx011xxxxxxxxxxxx0 st1d. */ - return 2707; + return 2713; } else { @@ -924,7 +924,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx111xxxxxxxxxxxx0 st1d. */ - return 2708; + return 2714; } } } @@ -941,7 +941,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx000xxxxxxxxxxxx1 stnt1b. */ - return 2731; + return 2737; } else { @@ -949,7 +949,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx100xxxxxxxxxxxx1 stnt1b. */ - return 2732; + return 2738; } } else @@ -960,7 +960,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx010xxxxxxxxxxxx1 stnt1w. */ - return 2755; + return 2761; } else { @@ -968,7 +968,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx110xxxxxxxxxxxx1 stnt1w. */ - return 2756; + return 2762; } } } @@ -982,7 +982,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx001xxxxxxxxxxxx1 stnt1h. */ - return 2747; + return 2753; } else { @@ -990,7 +990,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx101xxxxxxxxxxxx1 stnt1h. */ - return 2748; + return 2754; } } else @@ -1001,7 +1001,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx011xxxxxxxxxxxx1 stnt1d. */ - return 2739; + return 2745; } else { @@ -1009,7 +1009,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx111xxxxxxxxxxxx1 stnt1d. */ - return 2740; + return 2746; } } } @@ -1073,7 +1073,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx000xxxxxxxxxxxx0 st1b. */ - return 2695; + return 2701; } else { @@ -1081,7 +1081,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx100xxxxxxxxxxxx0 st1b. */ - return 2696; + return 2702; } } else @@ -1092,7 +1092,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx010xxxxxxxxxxxx0 st1w. */ - return 2719; + return 2725; } else { @@ -1100,7 +1100,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx110xxxxxxxxxxxx0 st1w. */ - return 2720; + return 2726; } } } @@ -1114,7 +1114,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx001xxxxxxxxxxxx0 st1h. */ - return 2711; + return 2717; } else { @@ -1122,7 +1122,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx101xxxxxxxxxxxx0 st1h. */ - return 2712; + return 2718; } } else @@ -1133,7 +1133,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx011xxxxxxxxxxxx0 st1d. */ - return 2703; + return 2709; } else { @@ -1141,7 +1141,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx111xxxxxxxxxxxx0 st1d. */ - return 2704; + return 2710; } } } @@ -1158,7 +1158,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx000xxxxxxxxxxxx1 stnt1b. */ - return 2727; + return 2733; } else { @@ -1166,7 +1166,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx100xxxxxxxxxxxx1 stnt1b. */ - return 2728; + return 2734; } } else @@ -1177,7 +1177,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx010xxxxxxxxxxxx1 stnt1w. */ - return 2751; + return 2757; } else { @@ -1185,7 +1185,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx110xxxxxxxxxxxx1 stnt1w. */ - return 2752; + return 2758; } } } @@ -1199,7 +1199,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx001xxxxxxxxxxxx1 stnt1h. */ - return 2743; + return 2749; } else { @@ -1207,7 +1207,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx101xxxxxxxxxxxx1 stnt1h. */ - return 2744; + return 2750; } } else @@ -1218,7 +1218,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx011xxxxxxxxxxxx1 stnt1d. */ - return 2735; + return 2741; } else { @@ -1226,7 +1226,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx111xxxxxxxxxxxx1 stnt1d. */ - return 2736; + return 2742; } } } @@ -1326,7 +1326,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000010000xxxxxxxxxxxxxxx001xx usmlall. */ - return 2846; + return 2855; } } else @@ -1358,7 +1358,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000010001xxxx0xxxxxxxxx100xxx usmlall. */ - return 2847; + return 2856; } else { @@ -1366,7 +1366,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000010001xxxx1xxxxxxxxx100xxx usmlall. */ - return 2848; + return 2857; } } } @@ -1381,7 +1381,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000010000xxxxxxxxxxxxxxx100xx umlall. */ - return 2810; + return 2816; } else { @@ -1389,7 +1389,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000010000xxxxxxxxxxxxxxx101xx sumlall. */ - return 2770; + return 2776; } } else @@ -1402,7 +1402,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000010001xxxx0xxxxxxxxx010xxx umlall. */ - return 2811; + return 2817; } else { @@ -1410,7 +1410,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000010001xxxx1xxxxxxxxx010xxx umlall. */ - return 2812; + return 2818; } } else @@ -1421,7 +1421,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000010001xxxx0xxxxxxxxx110xxx sumlall. */ - return 2771; + return 2777; } else { @@ -1429,7 +1429,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000010001xxxx1xxxxxxxxx110xxx sumlall. */ - return 2772; + return 2778; } } } @@ -1475,7 +1475,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000010000xxxxxxxxxxxxxxx11xxx umlsll. */ - return 2826; + return 2832; } else { @@ -1485,7 +1485,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000010001xxxx0xxxxxxxxxx11xxx umlsll. */ - return 2827; + return 2833; } else { @@ -1493,7 +1493,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000010001xxxx1xxxxxxxxxx11xxx umlsll. */ - return 2828; + return 2834; } } } @@ -1721,7 +1721,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011000xxxxxxx0xxxxxxx00xxx smlall. */ - return 2868; + return 2877; } else { @@ -1731,7 +1731,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011001xxxx0xx0xxxxxxx00xxx smlall. */ - return 2869; + return 2878; } else { @@ -1739,7 +1739,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011001xxxx1xx0xxxxxxx00xxx smlall. */ - return 2870; + return 2879; } } } @@ -1806,7 +1806,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011000xxxxxxx0xxxxxxx10xxx umlall. */ - return 2877; + return 2886; } else { @@ -1816,7 +1816,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011001xxxx0xx0xxxxxxx10xxx umlall. */ - return 2878; + return 2887; } else { @@ -1824,7 +1824,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011001xxxx1xx0xxxxxxx10xxx umlall. */ - return 2879; + return 2888; } } } @@ -1884,7 +1884,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000011000xxxxxxx0xxxxxxx01xxx smlsll. */ - return 2871; + return 2880; } else { @@ -1894,7 +1894,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000011001xxxx0xx0xxxxxxx01xxx smlsll. */ - return 2872; + return 2881; } else { @@ -1902,7 +1902,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000011001xxxx1xx0xxxxxxx01xxx smlsll. */ - return 2873; + return 2882; } } } @@ -1943,7 +1943,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001100xxxxxxxxxxxxxxxx01xxx umopa. */ - return 2834; + return 2840; } } else @@ -1958,7 +1958,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000011000xxxxxxx0xxxxxxx11xxx umlsll. */ - return 2880; + return 2889; } else { @@ -1968,7 +1968,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000011001xxxx0xx0xxxxxxx11xxx umlsll. */ - return 2881; + return 2890; } else { @@ -1976,7 +1976,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000011001xxxx1xx0xxxxxxx11xxx umlsll. */ - return 2882; + return 2891; } } } @@ -2017,7 +2017,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001100xxxxxxxxxxxxxxxx11xxx umops. */ - return 2835; + return 2841; } } } @@ -2103,7 +2103,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000010101xxxx0xx0xxxxxx100xxx svdot. */ - return 2776; + return 2782; } else { @@ -2133,7 +2133,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000010101xxxx0xx1xxxxxx010xxx udot. */ - return 2782; + return 2788; } } else @@ -2144,7 +2144,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000010101xxxx0xx0xxxxxx110xxx uvdot. */ - return 2855; + return 2864; } else { @@ -2152,7 +2152,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000010101xxxx0xx1xxxxxx110xxx udot. */ - return 2788; + return 2794; } } } @@ -2232,7 +2232,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000010101xxxx1xx0xxxxxx100xxx svdot. */ - return 2777; + return 2783; } else { @@ -2262,7 +2262,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000010101xxxx1xx1xxxxxx010xxx udot. */ - return 2783; + return 2789; } } else @@ -2273,7 +2273,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000010101xxxx1xx0xxxxxx110xxx uvdot. */ - return 2856; + return 2865; } else { @@ -2281,7 +2281,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000010101xxxx1xx1xxxxxx110xxx udot. */ - return 2789; + return 2795; } } } @@ -2362,7 +2362,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000010101xxxx0xxxxxxxxx101xxx usdot. */ - return 2840; + return 2849; } } else @@ -2392,7 +2392,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000010101xxxx0xxxxxxxxx111xxx sudot. */ - return 2766; + return 2772; } } } @@ -2460,7 +2460,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000010101xxxx1xx0xxxxxx101xxx usvdot. */ - return 2854; + return 2863; } else { @@ -2468,7 +2468,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000010101xxxx1xx1xxxxxx101xxx usdot. */ - return 2841; + return 2850; } } } @@ -2490,7 +2490,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000010101xxxx1xx0xxxxxx111xxx suvdot. */ - return 2775; + return 2781; } else { @@ -2498,7 +2498,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000010101xxxx1xx1xxxxxx111xxx sudot. */ - return 2767; + return 2773; } } } @@ -2522,7 +2522,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx000001110xxxxx0xx0xxxxxxx00xxx fmla. */ - return 2884; + return 2893; } else { @@ -2530,7 +2530,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx000001110xxxxx1xx0xxxxxxx00xxx fmla. */ - return 2885; + return 2894; } } else @@ -2576,7 +2576,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx000001110xxxxx0xx00xxxxxx01xxx sdot. */ - return 2866; + return 2875; } else { @@ -2584,7 +2584,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx000001110xxxxx1xx00xxxxxx01xxx sdot. */ - return 2867; + return 2876; } } else @@ -2593,7 +2593,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx000001110xxxxxxxx01xxxxxx01xxx svdot. */ - return 2874; + return 2883; } } else @@ -2662,7 +2662,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx000001110xxxxx0xx0xxxxxxx10xxx fmls. */ - return 2886; + return 2895; } else { @@ -2670,7 +2670,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx000001110xxxxx1xx0xxxxxxx10xxx fmls. */ - return 2887; + return 2896; } } else @@ -2681,7 +2681,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000011100xxxxxxx1xxxxxxx10xxx umlal. */ - return 2802; + return 2808; } else { @@ -2691,7 +2691,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000011101xxxx0xx1xxxxxxx10xxx umlal. */ - return 2803; + return 2809; } else { @@ -2699,7 +2699,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000011101xxxx1xx1xxxxxxx10xxx umlal. */ - return 2804; + return 2810; } } } @@ -2725,7 +2725,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001110xxxxx0xx00xxxxxx11xxx udot. */ - return 2875; + return 2884; } else { @@ -2733,7 +2733,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001110xxxxx1xx00xxxxxx11xxx udot. */ - return 2876; + return 2885; } } else @@ -2742,7 +2742,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001110xxxxxxxx01xxxxxx11xxx uvdot. */ - return 2883; + return 2892; } } else @@ -2753,7 +2753,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000011100xxxxxxx1xxxxxxx11xxx umlsl. */ - return 2818; + return 2824; } else { @@ -2763,7 +2763,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000011101xxxx0xx1xxxxxxx11xxx umlsl. */ - return 2819; + return 2825; } else { @@ -2771,7 +2771,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000011101xxxx1xx1xxxxxxx11xxx umlsl. */ - return 2820; + return 2826; } } } @@ -2868,7 +2868,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000010x10xxxx0xx000xxxxx001xx usmlall. */ - return 2850; + return 2859; } else { @@ -2876,7 +2876,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000010x11xxxx0xx000xxxxx001xx usmlall. */ - return 2851; + return 2860; } } else @@ -2887,7 +2887,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011x1xxxx00xx000xxxxx001xx usmlall. */ - return 2852; + return 2861; } else { @@ -2895,7 +2895,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011x1xxxx10xx000xxxxx001xx usmlall. */ - return 2853; + return 2862; } } } @@ -3092,7 +3092,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx0xx001xxxxx001xx usmlall. */ - return 2849; + return 2858; } } else @@ -3198,7 +3198,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000010x10xxxx0xx000xxxxx100xx umlall. */ - return 2814; + return 2820; } else { @@ -3206,7 +3206,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000010x11xxxx0xx000xxxxx100xx umlall. */ - return 2815; + return 2821; } } else @@ -3217,7 +3217,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011x1xxxx00xx000xxxxx100xx umlall. */ - return 2816; + return 2822; } else { @@ -3225,7 +3225,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011x1xxxx10xx000xxxxx100xx umlall. */ - return 2817; + return 2823; } } } @@ -3237,7 +3237,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx10xxxx0xx000xxxxx101xx sumlall. */ - return 2773; + return 2779; } else { @@ -3245,7 +3245,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx11xxxx0xx000xxxxx101xx sumlall. */ - return 2774; + return 2780; } } } @@ -3346,7 +3346,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000010110xxxx0xx010xxxxx10xxx umlal. */ - return 2806; + return 2812; } else { @@ -3354,7 +3354,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000010111xxxx0xx010xxxxx10xxx umlal. */ - return 2807; + return 2813; } } else @@ -3365,7 +3365,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001111xxxx00xx010xxxxx10xxx umlal. */ - return 2808; + return 2814; } else { @@ -3373,7 +3373,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001111xxxx10xx010xxxxx10xxx umlal. */ - return 2809; + return 2815; } } } @@ -3431,7 +3431,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx0xx001xxxxx10xxx umlall. */ - return 2813; + return 2819; } else { @@ -3443,7 +3443,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000010x10xxxx0xx101xxxxx10xxx udot. */ - return 2790; + return 2796; } else { @@ -3451,7 +3451,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000010x11xxxx0xx101xxxxx10xxx udot. */ - return 2791; + return 2797; } } else @@ -3462,7 +3462,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011x1xxxx00xx101xxxxx10xxx udot. */ - return 2792; + return 2798; } else { @@ -3470,7 +3470,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011x1xxxx10xx101xxxxx10xxx udot. */ - return 2793; + return 2799; } } } @@ -3493,7 +3493,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001x11xxxxx0xx011xxxxx10xxx umlal. */ - return 2805; + return 2811; } } else @@ -3720,7 +3720,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000010010xxxx0xx101xxxxx01xxx usdot. */ - return 2842; + return 2851; } else { @@ -3728,7 +3728,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000010011xxxx0xx101xxxxx01xxx usdot. */ - return 2843; + return 2852; } } else @@ -3739,7 +3739,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001101xxxx00xx101xxxxx01xxx usdot. */ - return 2844; + return 2853; } else { @@ -3747,7 +3747,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001101xxxx10xx101xxxxx01xxx usdot. */ - return 2845; + return 2854; } } } @@ -3851,7 +3851,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000010x10xxxx0xxx00xxxxx11xxx umlsll. */ - return 2830; + return 2836; } else { @@ -3859,7 +3859,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000010x11xxxx0xxx00xxxxx11xxx umlsll. */ - return 2831; + return 2837; } } else @@ -3870,7 +3870,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011x1xxxx00xxx00xxxxx11xxx umlsll. */ - return 2832; + return 2838; } else { @@ -3878,7 +3878,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011x1xxxx10xxx00xxxxx11xxx umlsll. */ - return 2833; + return 2839; } } } @@ -3937,7 +3937,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000010110xxxx0xx010xxxxx11xxx umlsl. */ - return 2822; + return 2828; } else { @@ -3945,7 +3945,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000010111xxxx0xx010xxxxx11xxx umlsl. */ - return 2823; + return 2829; } } else @@ -3956,7 +3956,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001111xxxx00xx010xxxxx11xxx umlsl. */ - return 2824; + return 2830; } else { @@ -3964,7 +3964,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001111xxxx10xx010xxxxx11xxx umlsl. */ - return 2825; + return 2831; } } } @@ -3979,7 +3979,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000010x10xxxx0xx110xxxxx11xxx sub. */ - return 2762; + return 2768; } else { @@ -3987,7 +3987,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000010x11xxxx0xx110xxxxx11xxx sub. */ - return 2763; + return 2769; } } else @@ -3998,7 +3998,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011x1xxxx00xx110xxxxx11xxx sub. */ - return 2764; + return 2770; } else { @@ -4006,7 +4006,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011x1xxxx10xx110xxxxx11xxx sub. */ - return 2765; + return 2771; } } } @@ -4022,7 +4022,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx0xx001xxxxx11xxx umlsll. */ - return 2829; + return 2835; } else { @@ -4034,7 +4034,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001x010xxxx0xx101xxxxx11xxx sudot. */ - return 2768; + return 2774; } else { @@ -4042,7 +4042,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001x011xxxx0xx101xxxxx11xxx sudot. */ - return 2769; + return 2775; } } else @@ -4055,7 +4055,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000010110xxxx0xx101xxxxx11xxx udot. */ - return 2784; + return 2790; } else { @@ -4063,7 +4063,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000010111xxxx0xx101xxxxx11xxx udot. */ - return 2785; + return 2791; } } else @@ -4074,7 +4074,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001111xxxx00xx101xxxxx11xxx udot. */ - return 2786; + return 2792; } else { @@ -4082,7 +4082,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001111xxxx10xx101xxxxx11xxx udot. */ - return 2787; + return 2793; } } } @@ -4106,7 +4106,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001x11xxxxx0xx011xxxxx11xxx umlsl. */ - return 2821; + return 2827; } } else @@ -4117,7 +4117,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxx00xx111xxxxx11xxx sub. */ - return 2760; + return 2766; } else { @@ -4125,7 +4125,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxx10xx111xxxxx11xxx sub. */ - return 2761; + return 2767; } } } @@ -4208,7 +4208,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1x0x0xxxxxxxxxx1 uclamp. */ - return 2778; + return 2784; } else { @@ -4216,7 +4216,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1x0x1xxxxxxxxxx1 uclamp. */ - return 2779; + return 2785; } } } @@ -4270,7 +4270,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx101000x0xx0xxxx1 umax. */ - return 2794; + return 2800; } else { @@ -4393,42 +4393,108 @@ aarch64_opcode_lookup_1 (uint32_t word) } else { - if (((word >> 19) & 0x1) == 0) + if (((word >> 17) & 0x1) == 0) { - if (((word >> 20) & 0x1) == 0) + if (((word >> 19) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx100xx1111000xxxx0xxxxx - fcvtzs. */ - return 2470; + if (((word >> 20) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx100x01111000xxxx0xxxxx + fcvtzs. */ + return 2470; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx110x01111000xxxx0xxxxx + fcvtzs. */ + return 2471; + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx110xx1111000xxxx0xxxxx - fcvtzs. */ - return 2471; + if (((word >> 20) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx101x01111000xxxx0xxxxx + frintp. */ + return 2530; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx111x01111000xxxx0xxxxx + frintp. */ + return 2531; + } } } else { if (((word >> 20) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx101xx1111000xxxx0xxxxx - frintp. */ - return 2530; + if (((word >> 22) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001x010xx11111000xxxx0xxxxx + sqcvt. */ + return 2687; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001x110xx11111000xxxx0xxxxx + sqcvtu. */ + return 2690; + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx111xx1111000xxxx0xxxxx - frintp. */ - return 2531; + if (((word >> 6) & 0x1) == 0) + { + if (((word >> 22) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001x011xx11111000xxx00xxxxx + sqcvt. */ + return 2688; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001x111xx11111000xxx00xxxxx + sqcvtu. */ + return 2691; + } + } + else + { + if (((word >> 22) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001x011xx11111000xxx10xxxxx + sqcvtn. */ + return 2689; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001x111xx11111000xxx10xxxxx + sqcvtun. */ + return 2692; + } + } } } } @@ -4463,7 +4529,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1x1100x0xx0xxxx1 umax. */ - return 2796; + return 2802; } else { @@ -4540,7 +4606,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1x1010x0xx0xxxx1 umax. */ - return 2795; + return 2801; } else { @@ -4548,7 +4614,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1x1110x0xx0xxxx1 umax. */ - return 2797; + return 2803; } } else @@ -4583,7 +4649,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1x1001xxxx0xxxxx sqdmulh. */ - return 2687; + return 2693; } else { @@ -4591,7 +4657,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1x1101xxxx0xxxxx sqdmulh. */ - return 2689; + return 2695; } } else @@ -4602,7 +4668,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1x1011xxxx0xxxxx sqdmulh. */ - return 2688; + return 2694; } else { @@ -4610,7 +4676,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1x1111xxxx0xxxxx sqdmulh. */ - return 2690; + return 2696; } } } @@ -4641,7 +4707,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx10100x10xx1xxxx0 srshl. */ - return 2691; + return 2697; } } else @@ -4663,7 +4729,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx10100x00xx1xxxx1 umin. */ - return 2798; + return 2804; } else { @@ -4671,7 +4737,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx10100x10xx1xxxx1 urshl. */ - return 2836; + return 2845; } } else @@ -4715,7 +4781,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx10xx1011100xxxxx1xxxxx ucvtf. */ - return 2780; + return 2786; } else { @@ -4723,27 +4789,60 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx11xx1011100xxxxx1xxxxx ucvtf. */ - return 2781; + return 2787; } } } else { - if (((word >> 20) & 0x1) == 0) + if (((word >> 17) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx10xxx111100xxxxx1xxxxx - fcvtzu. */ - return 2472; + if (((word >> 20) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx10xx0111100xxxxx1xxxxx + fcvtzu. */ + return 2472; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx11xx0111100xxxxx1xxxxx + fcvtzu. */ + return 2473; + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx11xxx111100xxxxx1xxxxx - fcvtzu. */ - return 2473; + if (((word >> 20) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx10xx1111100xxxxx1xxxxx + uqcvt. */ + return 2842; + } + else + { + if (((word >> 6) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx11xx1111100xxxx01xxxxx + uqcvt. */ + return 2843; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx11xx1111100xxxx11xxxxx + uqcvtn. */ + return 2844; + } + } } } } @@ -4768,7 +4867,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1x110x10xx1xxxx0 srshl. */ - return 2693; + return 2699; } } else @@ -4790,7 +4889,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1x110x00xx1xxxx1 umin. */ - return 2800; + return 2806; } else { @@ -4798,7 +4897,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1x110x10xx1xxxx1 urshl. */ - return 2838; + return 2847; } } else @@ -4845,7 +4944,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1x101x10xx1xxxx0 srshl. */ - return 2692; + return 2698; } else { @@ -4853,7 +4952,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1x111x10xx1xxxx0 srshl. */ - return 2694; + return 2700; } } } @@ -4889,7 +4988,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1x101x00xx1xxxx1 umin. */ - return 2799; + return 2805; } else { @@ -4897,7 +4996,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1x111x00xx1xxxx1 umin. */ - return 2801; + return 2807; } } else @@ -4908,7 +5007,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1x101x10xx1xxxx1 urshl. */ - return 2837; + return 2846; } else { @@ -4916,7 +5015,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1x111x10xx1xxxx1 urshl. */ - return 2839; + return 2848; } } } @@ -4966,7 +5065,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx000xxxxxxxxx0xxx st1b. */ - return 2701; + return 2707; } else { @@ -4974,7 +5073,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx010xxxxxxxxx0xxx st1w. */ - return 2725; + return 2731; } } else @@ -4985,7 +5084,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx001xxxxxxxxx0xxx st1h. */ - return 2717; + return 2723; } else { @@ -4993,7 +5092,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx011xxxxxxxxx0xxx st1d. */ - return 2709; + return 2715; } } } @@ -5007,7 +5106,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx000xxxxxxxxx1xxx stnt1b. */ - return 2733; + return 2739; } else { @@ -5015,7 +5114,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx010xxxxxxxxx1xxx stnt1w. */ - return 2757; + return 2763; } } else @@ -5026,7 +5125,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx001xxxxxxxxx1xxx stnt1h. */ - return 2749; + return 2755; } else { @@ -5034,7 +5133,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx011xxxxxxxxx1xxx stnt1d. */ - return 2741; + return 2747; } } } @@ -5062,7 +5161,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx100xxxxxxxxx0xxx st1b. */ - return 2702; + return 2708; } else { @@ -5070,7 +5169,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1100001001xxxxx100xxxxxxxxx0xxx str. */ - return 2759; + return 2765; } } else @@ -5079,7 +5178,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001001xxxxx110xxxxxxxxx0xxx st1w. */ - return 2726; + return 2732; } } else @@ -5090,7 +5189,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001001xxxxx101xxxxxxxxx0xxx st1h. */ - return 2718; + return 2724; } else { @@ -5098,7 +5197,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001001xxxxx111xxxxxxxxx0xxx st1d. */ - return 2710; + return 2716; } } } @@ -5112,7 +5211,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001001xxxxx100xxxxxxxxx1xxx stnt1b. */ - return 2734; + return 2740; } else { @@ -5120,7 +5219,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001001xxxxx110xxxxxxxxx1xxx stnt1w. */ - return 2758; + return 2764; } } else @@ -5131,7 +5230,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001001xxxxx101xxxxxxxxx1xxx stnt1h. */ - return 2750; + return 2756; } else { @@ -5139,7 +5238,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001001xxxxx111xxxxxxxxx1xxx stnt1d. */ - return 2742; + return 2748; } } } @@ -5181,7 +5280,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx000xxxxxxxxx0xxx st1b. */ - return 2697; + return 2703; } else { @@ -5189,7 +5288,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx100xxxxxxxxx0xxx st1b. */ - return 2698; + return 2704; } } else @@ -5200,7 +5299,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx010xxxxxxxxx0xxx st1w. */ - return 2721; + return 2727; } else { @@ -5208,7 +5307,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx110xxxxxxxxx0xxx st1w. */ - return 2722; + return 2728; } } } @@ -5222,7 +5321,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx001xxxxxxxxx0xxx st1h. */ - return 2713; + return 2719; } else { @@ -5230,7 +5329,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx101xxxxxxxxx0xxx st1h. */ - return 2714; + return 2720; } } else @@ -5241,7 +5340,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx011xxxxxxxxx0xxx st1d. */ - return 2705; + return 2711; } else { @@ -5249,7 +5348,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx111xxxxxxxxx0xxx st1d. */ - return 2706; + return 2712; } } } @@ -5266,7 +5365,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx000xxxxxxxxx1xxx stnt1b. */ - return 2729; + return 2735; } else { @@ -5274,7 +5373,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx100xxxxxxxxx1xxx stnt1b. */ - return 2730; + return 2736; } } else @@ -5285,7 +5384,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx010xxxxxxxxx1xxx stnt1w. */ - return 2753; + return 2759; } else { @@ -5293,7 +5392,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx110xxxxxxxxx1xxx stnt1w. */ - return 2754; + return 2760; } } } @@ -5307,7 +5406,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx001xxxxxxxxx1xxx stnt1h. */ - return 2745; + return 2751; } else { @@ -5315,7 +5414,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx101xxxxxxxxx1xxx stnt1h. */ - return 2746; + return 2752; } } else @@ -5326,7 +5425,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx011xxxxxxxxx1xxx stnt1d. */ - return 2737; + return 2743; } else { @@ -5334,7 +5433,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx111xxxxxxxxx1xxx stnt1d. */ - return 2738; + return 2744; } } } @@ -7736,7 +7835,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 00011001000xxxxxxxxx00xxxxxxxxxx stlurb. */ - return 2928; + return 2937; } else { @@ -7744,7 +7843,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 10011001000xxxxxxxxx00xxxxxxxxxx stlur. */ - return 2936; + return 2945; } } else @@ -7755,7 +7854,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 01011001000xxxxxxxxx00xxxxxxxxxx stlurh. */ - return 2932; + return 2941; } else { @@ -7763,7 +7862,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 11011001000xxxxxxxxx00xxxxxxxxxx stlur. */ - return 2939; + return 2948; } } } @@ -7801,7 +7900,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0000x1xxxxxxxxxx cpyfp. */ - return 2988; + return 2997; } else { @@ -7809,7 +7908,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1000x1xxxxxxxxxx cpyfprn. */ - return 2994; + return 3003; } } else @@ -7820,7 +7919,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0100x1xxxxxxxxxx cpyfpwn. */ - return 2991; + return 3000; } else { @@ -7828,7 +7927,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1100x1xxxxxxxxxx cpyfpn. */ - return 2997; + return 3006; } } } @@ -7842,7 +7941,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0010x1xxxxxxxxxx cpyfprt. */ - return 3012; + return 3021; } else { @@ -7850,7 +7949,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1010x1xxxxxxxxxx cpyfprtrn. */ - return 3018; + return 3027; } } else @@ -7861,7 +7960,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0110x1xxxxxxxxxx cpyfprtwn. */ - return 3015; + return 3024; } else { @@ -7869,7 +7968,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1110x1xxxxxxxxxx cpyfprtn. */ - return 3021; + return 3030; } } } @@ -7886,7 +7985,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0001x1xxxxxxxxxx cpyfpwt. */ - return 3000; + return 3009; } else { @@ -7894,7 +7993,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1001x1xxxxxxxxxx cpyfpwtrn. */ - return 3006; + return 3015; } } else @@ -7905,7 +8004,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0101x1xxxxxxxxxx cpyfpwtwn. */ - return 3003; + return 3012; } else { @@ -7913,7 +8012,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1101x1xxxxxxxxxx cpyfpwtn. */ - return 3009; + return 3018; } } } @@ -7927,7 +8026,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0011x1xxxxxxxxxx cpyfpt. */ - return 3024; + return 3033; } else { @@ -7935,7 +8034,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1011x1xxxxxxxxxx cpyfptrn. */ - return 3030; + return 3039; } } else @@ -7946,7 +8045,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0111x1xxxxxxxxxx cpyfptwn. */ - return 3027; + return 3036; } else { @@ -7954,7 +8053,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1111x1xxxxxxxxxx cpyfptn. */ - return 3033; + return 3042; } } } @@ -8019,7 +8118,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 00011001010xxxxxxxxx00xxxxxxxxxx ldapurb. */ - return 2929; + return 2938; } else { @@ -8027,7 +8126,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 10011001010xxxxxxxxx00xxxxxxxxxx ldapur. */ - return 2937; + return 2946; } } else @@ -8038,7 +8137,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 01011001010xxxxxxxxx00xxxxxxxxxx ldapurh. */ - return 2933; + return 2942; } else { @@ -8046,7 +8145,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 11011001010xxxxxxxxx00xxxxxxxxxx ldapur. */ - return 2940; + return 2949; } } } @@ -8084,7 +8183,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0000x1xxxxxxxxxx cpyfm. */ - return 2989; + return 2998; } else { @@ -8092,7 +8191,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1000x1xxxxxxxxxx cpyfmrn. */ - return 2995; + return 3004; } } else @@ -8103,7 +8202,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0100x1xxxxxxxxxx cpyfmwn. */ - return 2992; + return 3001; } else { @@ -8111,7 +8210,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1100x1xxxxxxxxxx cpyfmn. */ - return 2998; + return 3007; } } } @@ -8125,7 +8224,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0010x1xxxxxxxxxx cpyfmrt. */ - return 3013; + return 3022; } else { @@ -8133,7 +8232,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1010x1xxxxxxxxxx cpyfmrtrn. */ - return 3019; + return 3028; } } else @@ -8144,7 +8243,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0110x1xxxxxxxxxx cpyfmrtwn. */ - return 3016; + return 3025; } else { @@ -8152,7 +8251,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1110x1xxxxxxxxxx cpyfmrtn. */ - return 3022; + return 3031; } } } @@ -8169,7 +8268,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0001x1xxxxxxxxxx cpyfmwt. */ - return 3001; + return 3010; } else { @@ -8177,7 +8276,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1001x1xxxxxxxxxx cpyfmwtrn. */ - return 3007; + return 3016; } } else @@ -8188,7 +8287,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0101x1xxxxxxxxxx cpyfmwtwn. */ - return 3004; + return 3013; } else { @@ -8196,7 +8295,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1101x1xxxxxxxxxx cpyfmwtn. */ - return 3010; + return 3019; } } } @@ -8210,7 +8309,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0011x1xxxxxxxxxx cpyfmt. */ - return 3025; + return 3034; } else { @@ -8218,7 +8317,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1011x1xxxxxxxxxx cpyfmtrn. */ - return 3031; + return 3040; } } else @@ -8229,7 +8328,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0111x1xxxxxxxxxx cpyfmtwn. */ - return 3028; + return 3037; } else { @@ -8237,7 +8336,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1111x1xxxxxxxxxx cpyfmtn. */ - return 3034; + return 3043; } } } @@ -8305,7 +8404,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 00011001100xxxxxxxxx00xxxxxxxxxx ldapursb. */ - return 2931; + return 2940; } else { @@ -8313,7 +8412,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 10011001100xxxxxxxxx00xxxxxxxxxx ldapursw. */ - return 2938; + return 2947; } } else @@ -8322,7 +8421,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1011001100xxxxxxxxx00xxxxxxxxxx ldapursh. */ - return 2935; + return 2944; } } else @@ -8333,7 +8432,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0011001110xxxxxxxxx00xxxxxxxxxx ldapursb. */ - return 2930; + return 2939; } else { @@ -8341,7 +8440,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1011001110xxxxxxxxx00xxxxxxxxxx ldapursh. */ - return 2934; + return 2943; } } } @@ -8403,7 +8502,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0000x1xxxxxxxxxx cpyfe. */ - return 2990; + return 2999; } else { @@ -8411,7 +8510,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0000x1xxxxxxxxxx setp. */ - return 3084; + return 3093; } } else @@ -8422,7 +8521,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx1000x1xxxxxxxxxx cpyfern. */ - return 2996; + return 3005; } else { @@ -8430,7 +8529,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx1000x1xxxxxxxxxx sete. */ - return 3086; + return 3095; } } } @@ -8444,7 +8543,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0100x1xxxxxxxxxx cpyfewn. */ - return 2993; + return 3002; } else { @@ -8452,7 +8551,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0100x1xxxxxxxxxx setm. */ - return 3085; + return 3094; } } else @@ -8461,7 +8560,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0110011x0xxxxx1100x1xxxxxxxxxx cpyfen. */ - return 2999; + return 3008; } } } @@ -8477,7 +8576,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0010x1xxxxxxxxxx cpyfert. */ - return 3014; + return 3023; } else { @@ -8485,7 +8584,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0010x1xxxxxxxxxx setpn. */ - return 3090; + return 3099; } } else @@ -8496,7 +8595,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx1010x1xxxxxxxxxx cpyfertrn. */ - return 3020; + return 3029; } else { @@ -8504,7 +8603,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx1010x1xxxxxxxxxx seten. */ - return 3092; + return 3101; } } } @@ -8518,7 +8617,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0110x1xxxxxxxxxx cpyfertwn. */ - return 3017; + return 3026; } else { @@ -8526,7 +8625,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0110x1xxxxxxxxxx setmn. */ - return 3091; + return 3100; } } else @@ -8535,7 +8634,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0110011x0xxxxx1110x1xxxxxxxxxx cpyfertn. */ - return 3023; + return 3032; } } } @@ -8554,7 +8653,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0001x1xxxxxxxxxx cpyfewt. */ - return 3002; + return 3011; } else { @@ -8562,7 +8661,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0001x1xxxxxxxxxx setpt. */ - return 3087; + return 3096; } } else @@ -8573,7 +8672,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx1001x1xxxxxxxxxx cpyfewtrn. */ - return 3008; + return 3017; } else { @@ -8581,7 +8680,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx1001x1xxxxxxxxxx setet. */ - return 3089; + return 3098; } } } @@ -8595,7 +8694,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0101x1xxxxxxxxxx cpyfewtwn. */ - return 3005; + return 3014; } else { @@ -8603,7 +8702,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0101x1xxxxxxxxxx setmt. */ - return 3088; + return 3097; } } else @@ -8612,7 +8711,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0110011x0xxxxx1101x1xxxxxxxxxx cpyfewtn. */ - return 3011; + return 3020; } } } @@ -8628,7 +8727,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0011x1xxxxxxxxxx cpyfet. */ - return 3026; + return 3035; } else { @@ -8636,7 +8735,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0011x1xxxxxxxxxx setptn. */ - return 3093; + return 3102; } } else @@ -8647,7 +8746,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx1011x1xxxxxxxxxx cpyfetrn. */ - return 3032; + return 3041; } else { @@ -8655,7 +8754,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx1011x1xxxxxxxxxx setetn. */ - return 3095; + return 3104; } } } @@ -8669,7 +8768,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0111x1xxxxxxxxxx cpyfetwn. */ - return 3029; + return 3038; } else { @@ -8677,7 +8776,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0111x1xxxxxxxxxx setmtn. */ - return 3094; + return 3103; } } else @@ -8686,7 +8785,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0110011x0xxxxx1111x1xxxxxxxxxx cpyfetn. */ - return 3035; + return 3044; } } } @@ -9059,7 +9158,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1x11010110xxxx0x01000xxxxxxxxxx abs. */ - return 3113; + return 3122; } else { @@ -9077,7 +9176,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010110xxxxxx11000xxxxxxxxxx smax. */ - return 3116; + return 3125; } } } @@ -9157,7 +9256,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010x00xxxxxx0xx10xxxxxxxxxx setf8. */ - return 2926; + return 2935; } else { @@ -9165,7 +9264,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010x00xxxxxx1xx10xxxxxxxxxx setf16. */ - return 2927; + return 2936; } } else @@ -9272,7 +9371,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010110xxxxxx11010xxxxxxxxxx smin. */ - return 3118; + return 3127; } } } @@ -9288,7 +9387,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010110xxxx0x00110xxxxxxxxxx ctz. */ - return 3115; + return 3124; } else { @@ -9333,7 +9432,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010000xxxxxxxxx01xxxxxxxxxx rmif. */ - return 2925; + return 2934; } else { @@ -9427,7 +9526,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010x10xxxxxx11001xxxxxxxxxx umax. */ - return 3117; + return 3126; } } } @@ -9557,7 +9656,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010xx0xxxxxx11011xxxxxxxxxx umin. */ - return 3119; + return 3128; } } } @@ -9573,7 +9672,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010xx0xxxx0x00111xxxxxxxxxx cnt. */ - return 3114; + return 3123; } else { @@ -10415,7 +10514,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x01x1xxxxx000110xxxxxxxxxx usdot. */ - return 2945; + return 2954; } } } @@ -10489,7 +10588,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x01x1xxxxx000111xxxxxxxxxx sudot. */ - return 2946; + return 2955; } } } @@ -13163,7 +13262,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x0xx0xxxxx011110xxxxxxxxxx usdot. */ - return 2944; + return 2953; } } } @@ -14867,7 +14966,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0100xxx10101xxxxxxxxxxxxx bfcvtnt. */ - return 2973; + return 2982; } } else @@ -15110,7 +15209,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x00x1xxxxxx00xxxxxxxxxxxxx ld1rob. */ - return 2949; + return 2958; } else { @@ -15118,7 +15217,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x01x1xxxxxx00xxxxxxxxxxxxx ld1roh. */ - return 2950; + return 2959; } } else @@ -15350,7 +15449,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0011xxxxx010xxxxxxxxxxxxx bfdot. */ - return 2970; + return 2979; } else { @@ -15371,7 +15470,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx010xx0xxxxxxxxxx bfmlalb. */ - return 2977; + return 2986; } else { @@ -15379,7 +15478,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx010xx1xxxxxxxxxx bfmlalt. */ - return 2976; + return 2985; } } else @@ -15434,7 +15533,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11001x0011xxxxx1x0xxxxxxxxxxxxx bfdot. */ - return 2969; + return 2978; } else { @@ -15446,7 +15545,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx1x0xx0xxxxxxxxxx bfmlalb. */ - return 2975; + return 2984; } else { @@ -15454,7 +15553,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx1x0xx1xxxxxxxxxx bfmlalt. */ - return 2974; + return 2983; } } else @@ -15505,7 +15604,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x00x1xxxxx001xxxxxxxxxxxxx ld1rob. */ - return 2953; + return 2962; } else { @@ -15513,7 +15612,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x01x1xxxxx001xxxxxxxxxxxxx ld1roh. */ - return 2954; + return 2963; } } else @@ -15872,7 +15971,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0101xxxxx111xxxxxxxxxxxxx fmmla. */ - return 2947; + return 2956; } else { @@ -15905,7 +16004,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0011xxxxx111xxxxxxxxxxxxx bfmmla. */ - return 2971; + return 2980; } else { @@ -15935,7 +16034,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx111xxxxxxxxxxxxx fmmla. */ - return 2948; + return 2957; } else { @@ -16064,7 +16163,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000x00xxxxxxxxxx zip1. */ - return 2957; + return 2966; } else { @@ -16074,7 +16173,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000010xxxxxxxxxx uzp1. */ - return 2959; + return 2968; } else { @@ -16082,7 +16181,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000110xxxxxxxxxx trn1. */ - return 2961; + return 2970; } } } @@ -16094,7 +16193,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000x01xxxxxxxxxx zip2. */ - return 2958; + return 2967; } else { @@ -16104,7 +16203,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000011xxxxxxxxxx uzp2. */ - return 2960; + return 2969; } else { @@ -16112,7 +16211,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000111xxxxxxxxxx trn2. */ - return 2962; + return 2971; } } } @@ -17171,7 +17270,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x1000xxxxx100110xxxxxxxxxx smmla. */ - return 2941; + return 2950; } else { @@ -17179,7 +17278,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x1100xxxxx100110xxxxxxxxxx usmmla. */ - return 2943; + return 2952; } } else @@ -17188,7 +17287,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x1x10xxxxx100110xxxxxxxxxx ummla. */ - return 2942; + return 2951; } } } @@ -18684,7 +18783,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x10x1xxxxx000xxxxxxxxxxxxx ld1row. */ - return 2951; + return 2960; } else { @@ -18692,7 +18791,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x11x1xxxxx000xxxxxxxxxxxxx ld1rod. */ - return 2952; + return 2961; } } } @@ -19066,7 +19165,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x10x1xxxxx001xxxxxxxxxxxxx ld1row. */ - return 2955; + return 2964; } else { @@ -19074,7 +19173,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x11x1xxxxx001xxxxxxxxxxxxx ld1rod. */ - return 2956; + return 2965; } } } @@ -19435,7 +19534,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x000xxxxx10xxx whilege. */ - return 2857; + return 2866; } else { @@ -19443,7 +19542,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x000xxxxx11xxx whilegt. */ - return 2858; + return 2867; } } else @@ -19487,7 +19586,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x010xxxxx10xxx whilehs. */ - return 2860; + return 2869; } else { @@ -19495,7 +19594,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x010xxxxx11xxx whilehi. */ - return 2859; + return 2868; } } else @@ -19542,7 +19641,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x001xxxxx10xxx whilelt. */ - return 2864; + return 2873; } else { @@ -19550,7 +19649,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x001xxxxx11xxx whilele. */ - return 2861; + return 2870; } } else @@ -19594,7 +19693,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x011xxxxx10xxx whilelo. */ - return 2862; + return 2871; } else { @@ -19602,7 +19701,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x011xxxxx11xxx whilels. */ - return 2863; + return 2872; } } else @@ -20728,7 +20827,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x110001x10101xxxxxxxxxxxxx bfcvt. */ - return 2972; + return 2981; } } else @@ -22089,7 +22188,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1010100xxxxxxxxxxxxxxxxxxx1xxxx bc.c. */ - return 3108; + return 3117; } else { @@ -22669,7 +22768,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0000xxxxxxxxxxxx cpyp. */ - return 3036; + return 3045; } else { @@ -22677,7 +22776,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0000xxxxxxxxxxxx cpye. */ - return 3038; + return 3047; } } else @@ -22688,7 +22787,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1000xxxxxxxxxxxx cpyprn. */ - return 3042; + return 3051; } else { @@ -22696,7 +22795,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1000xxxxxxxxxxxx cpyern. */ - return 3044; + return 3053; } } } @@ -22710,7 +22809,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0100xxxxxxxxxxxx cpypwn. */ - return 3039; + return 3048; } else { @@ -22718,7 +22817,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0100xxxxxxxxxxxx cpyewn. */ - return 3041; + return 3050; } } else @@ -22729,7 +22828,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1100xxxxxxxxxxxx cpypn. */ - return 3045; + return 3054; } else { @@ -22737,7 +22836,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1100xxxxxxxxxxxx cpyen. */ - return 3047; + return 3056; } } } @@ -22754,7 +22853,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0010xxxxxxxxxxxx cpyprt. */ - return 3060; + return 3069; } else { @@ -22762,7 +22861,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0010xxxxxxxxxxxx cpyert. */ - return 3062; + return 3071; } } else @@ -22773,7 +22872,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1010xxxxxxxxxxxx cpyprtrn. */ - return 3066; + return 3075; } else { @@ -22781,7 +22880,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1010xxxxxxxxxxxx cpyertrn. */ - return 3068; + return 3077; } } } @@ -22795,7 +22894,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0110xxxxxxxxxxxx cpyprtwn. */ - return 3063; + return 3072; } else { @@ -22803,7 +22902,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0110xxxxxxxxxxxx cpyertwn. */ - return 3065; + return 3074; } } else @@ -22814,7 +22913,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1110xxxxxxxxxxxx cpyprtn. */ - return 3069; + return 3078; } else { @@ -22822,7 +22921,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1110xxxxxxxxxxxx cpyertn. */ - return 3071; + return 3080; } } } @@ -22842,7 +22941,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0001xxxxxxxxxxxx cpypwt. */ - return 3048; + return 3057; } else { @@ -22850,7 +22949,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0001xxxxxxxxxxxx cpyewt. */ - return 3050; + return 3059; } } else @@ -22861,7 +22960,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1001xxxxxxxxxxxx cpypwtrn. */ - return 3054; + return 3063; } else { @@ -22869,7 +22968,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1001xxxxxxxxxxxx cpyewtrn. */ - return 3056; + return 3065; } } } @@ -22883,7 +22982,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0101xxxxxxxxxxxx cpypwtwn. */ - return 3051; + return 3060; } else { @@ -22891,7 +22990,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0101xxxxxxxxxxxx cpyewtwn. */ - return 3053; + return 3062; } } else @@ -22902,7 +23001,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1101xxxxxxxxxxxx cpypwtn. */ - return 3057; + return 3066; } else { @@ -22910,7 +23009,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1101xxxxxxxxxxxx cpyewtn. */ - return 3059; + return 3068; } } } @@ -22927,7 +23026,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0011xxxxxxxxxxxx cpypt. */ - return 3072; + return 3081; } else { @@ -22935,7 +23034,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0011xxxxxxxxxxxx cpyet. */ - return 3074; + return 3083; } } else @@ -22946,7 +23045,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1011xxxxxxxxxxxx cpyptrn. */ - return 3078; + return 3087; } else { @@ -22954,7 +23053,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1011xxxxxxxxxxxx cpyetrn. */ - return 3080; + return 3089; } } } @@ -22968,7 +23067,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0111xxxxxxxxxxxx cpyptwn. */ - return 3075; + return 3084; } else { @@ -22976,7 +23075,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0111xxxxxxxxxxxx cpyetwn. */ - return 3077; + return 3086; } } else @@ -22987,7 +23086,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1111xxxxxxxxxxxx cpyptn. */ - return 3081; + return 3090; } else { @@ -22995,7 +23094,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1111xxxxxxxxxxxx cpyetn. */ - return 3083; + return 3092; } } } @@ -23029,7 +23128,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0000xxxxxxxxxxxx cpym. */ - return 3037; + return 3046; } else { @@ -23037,7 +23136,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0000xxxxxxxxxxxx setgp. */ - return 3096; + return 3105; } } else @@ -23048,7 +23147,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx1000xxxxxxxxxxxx cpymrn. */ - return 3043; + return 3052; } else { @@ -23056,7 +23155,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx1000xxxxxxxxxxxx setge. */ - return 3098; + return 3107; } } } @@ -23070,7 +23169,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0100xxxxxxxxxxxx cpymwn. */ - return 3040; + return 3049; } else { @@ -23078,7 +23177,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0100xxxxxxxxxxxx setgm. */ - return 3097; + return 3106; } } else @@ -23087,7 +23186,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011101x1xxxxxx1100xxxxxxxxxxxx cpymn. */ - return 3046; + return 3055; } } } @@ -23103,7 +23202,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0010xxxxxxxxxxxx cpymrt. */ - return 3061; + return 3070; } else { @@ -23111,7 +23210,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0010xxxxxxxxxxxx setgpn. */ - return 3102; + return 3111; } } else @@ -23122,7 +23221,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx1010xxxxxxxxxxxx cpymrtrn. */ - return 3067; + return 3076; } else { @@ -23130,7 +23229,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx1010xxxxxxxxxxxx setgen. */ - return 3104; + return 3113; } } } @@ -23144,7 +23243,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0110xxxxxxxxxxxx cpymrtwn. */ - return 3064; + return 3073; } else { @@ -23152,7 +23251,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0110xxxxxxxxxxxx setgmn. */ - return 3103; + return 3112; } } else @@ -23161,7 +23260,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011101x1xxxxxx1110xxxxxxxxxxxx cpymrtn. */ - return 3070; + return 3079; } } } @@ -23180,7 +23279,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0001xxxxxxxxxxxx cpymwt. */ - return 3049; + return 3058; } else { @@ -23188,7 +23287,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0001xxxxxxxxxxxx setgpt. */ - return 3099; + return 3108; } } else @@ -23199,7 +23298,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx1001xxxxxxxxxxxx cpymwtrn. */ - return 3055; + return 3064; } else { @@ -23207,7 +23306,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx1001xxxxxxxxxxxx setget. */ - return 3101; + return 3110; } } } @@ -23221,7 +23320,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0101xxxxxxxxxxxx cpymwtwn. */ - return 3052; + return 3061; } else { @@ -23229,7 +23328,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0101xxxxxxxxxxxx setgmt. */ - return 3100; + return 3109; } } else @@ -23238,7 +23337,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011101x1xxxxxx1101xxxxxxxxxxxx cpymwtn. */ - return 3058; + return 3067; } } } @@ -23254,7 +23353,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0011xxxxxxxxxxxx cpymt. */ - return 3073; + return 3082; } else { @@ -23262,7 +23361,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0011xxxxxxxxxxxx setgptn. */ - return 3105; + return 3114; } } else @@ -23273,7 +23372,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx1011xxxxxxxxxxxx cpymtrn. */ - return 3079; + return 3088; } else { @@ -23281,7 +23380,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx1011xxxxxxxxxxxx setgetn. */ - return 3107; + return 3116; } } } @@ -23295,7 +23394,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0111xxxxxxxxxxxx cpymtwn. */ - return 3076; + return 3085; } else { @@ -23303,7 +23402,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0111xxxxxxxxxxxx setgmtn. */ - return 3106; + return 3115; } } else @@ -23312,7 +23411,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011101x1xxxxxx1111xxxxxxxxxxxx cpymtn. */ - return 3082; + return 3091; } } } @@ -23479,7 +23578,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110xx0xxxxx1x1001xxxxxxxxxx smmla. */ - return 2963; + return 2972; } } } @@ -23512,7 +23611,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110xx0xxxxx1x0101xxxxxxxxxx sdot. */ - return 2889; + return 2898; } } else @@ -23586,7 +23685,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110xx0xxxxx1x1011xxxxxxxxxx usmmla. */ - return 2965; + return 2974; } } } @@ -23619,7 +23718,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110xx0xxxxx1x0111xxxxxxxxxx usdot. */ - return 2966; + return 2975; } } else @@ -23666,7 +23765,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110000xxxxxxxxxxxxxxxxxxxxx eor3. */ - return 2896; + return 2905; } else { @@ -23674,7 +23773,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110100xxxxxxxxxxxxxxxxxxxxx xar. */ - return 2898; + return 2907; } } else @@ -23685,7 +23784,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110x10xxxxx0xxxxxxxxxxxxxxx sm3ss1. */ - return 2900; + return 2909; } else { @@ -23699,7 +23798,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110010xxxxx1xxx00xxxxxxxxxx sm3tt1a. */ - return 2901; + return 2910; } else { @@ -23707,7 +23806,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110110xxxxx1xxx00xxxxxxxxxx sha512su0. */ - return 2894; + return 2903; } } else @@ -23716,7 +23815,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110x10xxxxx1xxx10xxxxxxxxxx sm3tt2a. */ - return 2903; + return 2912; } } else @@ -23729,7 +23828,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110010xxxxx1xxx01xxxxxxxxxx sm3tt1b. */ - return 2902; + return 2911; } else { @@ -23737,7 +23836,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110110xxxxx1xxx01xxxxxxxxxx sm4e. */ - return 2907; + return 2916; } } else @@ -23746,7 +23845,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110x10xxxxx1xxx11xxxxxxxxxx sm3tt2b. */ - return 2904; + return 2913; } } } @@ -23927,7 +24026,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx101110xx0xxxxx100101xxxxxxxxxx udot. */ - return 2888; + return 2897; } } else @@ -23958,7 +24057,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx101110xx0xxxxx101x01xxxxxxxxxx ummla. */ - return 2964; + return 2973; } else { @@ -23977,7 +24076,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx101110xx0xxxxx1x1011xxxxxxxxxx bfmmla. */ - return 2980; + return 2989; } else { @@ -23987,7 +24086,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx1011100x0xxxxx1x1111xxxxxxxxxx bfdot. */ - return 2978; + return 2987; } else { @@ -23997,7 +24096,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x01011101x0xxxxx1x1111xxxxxxxxxx bfmlalb. */ - return 2985; + return 2994; } else { @@ -24005,7 +24104,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11011101x0xxxxx1x1111xxxxxxxxxx bfmlalt. */ - return 2984; + return 2993; } } } @@ -24589,7 +24688,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000011101x1xxxx1011010xxxxxxxxxx bfcvtn. */ - return 2981; + return 2990; } else { @@ -24597,7 +24696,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010011101x1xxxx1011010xxxxxxxxxx bfcvtn2. */ - return 2982; + return 2991; } } } @@ -24915,7 +25014,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110xx1xxxxx0xxxxxxxxxxxxxxx bcax. */ - return 2899; + return 2908; } } else @@ -25526,7 +25625,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 11001110xx1xxxxx100000xxxxxxxxxx sha512h. */ - return 2892; + return 2901; } } } @@ -25578,7 +25677,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 11001110xx1xxxxx110000xxxxxxxxxx sm3partw1. */ - return 2905; + return 2914; } } } @@ -25821,7 +25920,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110xx1xxxxx100010xxxxxxxxxx sha512su1. */ - return 2895; + return 2904; } } else @@ -25897,7 +25996,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x0011100x1xxxxx110010xxxxxxxxxx sm4ekey. */ - return 2908; + return 2917; } } else @@ -26723,7 +26822,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110xx1xxxxx100001xxxxxxxxxx sha512h2. */ - return 2893; + return 2902; } } else @@ -26755,7 +26854,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x0011100x1xxxxx110001xxxxxxxxxx sm3partw2. */ - return 2906; + return 2915; } } else @@ -26995,7 +27094,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110xx1xxxxx100011xxxxxxxxxx rax1. */ - return 2897; + return 2906; } } else @@ -27027,7 +27126,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x01011100x1xxxxx110011xxxxxxxxxx fmlal2. */ - return 2911; + return 2920; } else { @@ -27035,7 +27134,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11011100x1xxxxx110011xxxxxxxxxx fmlal2. */ - return 2915; + return 2924; } } } @@ -27057,7 +27156,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x01011101x1xxxxx110011xxxxxxxxxx fmlsl2. */ - return 2912; + return 2921; } else { @@ -27065,7 +27164,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11011101x1xxxxx110011xxxxxxxxxx fmlsl2. */ - return 2916; + return 2925; } } } @@ -27104,7 +27203,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x00011100x1xxxxx111011xxxxxxxxxx fmlal. */ - return 2909; + return 2918; } else { @@ -27112,7 +27211,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10011100x1xxxxx111011xxxxxxxxxx fmlal. */ - return 2913; + return 2922; } } else @@ -27134,7 +27233,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x00011101x1xxxxx111011xxxxxxxxxx fmlsl. */ - return 2910; + return 2919; } else { @@ -27142,7 +27241,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10011101x1xxxxx111011xxxxxxxxxx fmlsl. */ - return 2914; + return 2923; } } else @@ -28950,7 +29049,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0001111xxxxxxxx0000x0xxxxxxxxxx fmlal. */ - return 2917; + return 2926; } else { @@ -28958,7 +29057,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1001111xxxxxxxx0000x0xxxxxxxxxx fmlal. */ - return 2921; + return 2930; } } else @@ -28980,7 +29079,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0001111xxxxxxxx0100x0xxxxxxxxxx fmlsl. */ - return 2918; + return 2927; } else { @@ -28988,7 +29087,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1001111xxxxxxxx0100x0xxxxxxxxxx fmlsl. */ - return 2922; + return 2931; } } else @@ -29494,7 +29593,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0101111xxxxxxxx1000x0xxxxxxxxxx fmlal2. */ - return 2919; + return 2928; } else { @@ -29502,7 +29601,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1101111xxxxxxxx1000x0xxxxxxxxxx fmlal2. */ - return 2923; + return 2932; } } } @@ -29524,7 +29623,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0101111xxxxxxxx1100x0xxxxxxxxxx fmlsl2. */ - return 2920; + return 2929; } else { @@ -29532,7 +29631,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1101111xxxxxxxx1100x0xxxxxxxxxx fmlsl2. */ - return 2924; + return 2933; } } } @@ -29588,7 +29687,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx001111xxxxxxxx1110x0xxxxxxxxxx sdot. */ - return 2891; + return 2900; } else { @@ -29596,7 +29695,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx101111xxxxxxxx1110x0xxxxxxxxxx udot. */ - return 2890; + return 2899; } } } @@ -29699,7 +29798,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx00111100xxxxxx1111x0xxxxxxxxxx sudot. */ - return 2968; + return 2977; } else { @@ -29707,7 +29806,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx00111110xxxxxx1111x0xxxxxxxxxx usdot. */ - return 2967; + return 2976; } } else @@ -29718,7 +29817,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx00111101xxxxxx1111x0xxxxxxxxxx bfdot. */ - return 2979; + return 2988; } else { @@ -29728,7 +29827,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x000111111xxxxxx1111x0xxxxxxxxxx bfmlalb. */ - return 2987; + return 2996; } else { @@ -29736,7 +29835,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x100111111xxxxxx1111x0xxxxxxxxxx bfmlalt. */ - return 2986; + return 2995; } } } @@ -30264,11 +30363,11 @@ aarch64_find_next_opcode (const aarch64_opcode *opcode) case 2407: value = 2412; break; /* st1q --> st1q. */ case 2412: return NULL; /* st1q --> NULL. */ case 12: value = 19; break; /* add --> addg. */ - case 19: value = 3109; break; /* addg --> smax. */ - case 3109: value = 3110; break; /* smax --> umax. */ - case 3110: value = 3111; break; /* umax --> smin. */ - case 3111: value = 3112; break; /* smin --> umin. */ - case 3112: return NULL; /* umin --> NULL. */ + case 19: value = 3118; break; /* addg --> smax. */ + case 3118: value = 3119; break; /* smax --> umax. */ + case 3119: value = 3120; break; /* umax --> smin. */ + case 3120: value = 3121; break; /* smin --> umin. */ + case 3121: return NULL; /* umin --> NULL. */ case 16: value = 20; break; /* sub --> subg. */ case 20: return NULL; /* subg --> NULL. */ case 971: value = 975; break; /* stnp --> stp. */ @@ -30426,8 +30525,8 @@ aarch64_find_next_opcode (const aarch64_opcode *opcode) case 824: return NULL; /* fsqrt --> NULL. */ case 832: value = 833; break; /* frintz --> frintz. */ case 833: return NULL; /* frintz --> NULL. */ - case 825: value = 2983; break; /* fcvt --> bfcvt. */ - case 2983: return NULL; /* bfcvt --> NULL. */ + case 825: value = 2992; break; /* fcvt --> bfcvt. */ + case 2992: return NULL; /* bfcvt --> NULL. */ case 834: value = 835; break; /* frinta --> frinta. */ case 835: return NULL; /* frinta --> NULL. */ case 836: value = 837; break; /* frintx --> frintx. */ diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c index 7271231eb3f..fd13c924804 100644 --- a/opcodes/aarch64-dis.c +++ b/opcodes/aarch64-dis.c @@ -3102,6 +3102,10 @@ aarch64_decode_variant_using_iclass (aarch64_inst *inst) variant -= 1; break; + case sme_sz_23: + variant = extract_field (FLD_SME_sz_23, inst->value, 0); + break; + case sve_cpy: variant = extract_fields (inst->value, 0, 2, FLD_size, FLD_SVE_M_14); break; diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index ac54bf7811a..0418a21b295 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -252,6 +252,7 @@ const aarch64_field fields[] = { 23, 1 }, /* SME_i1: immediate field, bit 23. */ { 12, 2 }, /* SME_size_12: bits [13:12]. */ { 22, 2 }, /* SME_size_22: size<1>, size<0> class field, [23:22]. */ + { 23, 1 }, /* SME_sz_23: bit [23]. */ { 22, 1 }, /* SME_tszh: immediate and qualifier field, bit 22. */ { 18, 3 }, /* SME_tszl: immediate and qualifier field, bits [20:18]. */ { 0, 8 }, /* SME_zero_mask: list of up to 8 tile names separated by commas [7:0]. */ diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h index f8051c9b2da..698b00d7805 100644 --- a/opcodes/aarch64-opc.h +++ b/opcodes/aarch64-opc.h @@ -73,6 +73,7 @@ enum aarch64_field_kind FLD_SME_i1, FLD_SME_size_12, FLD_SME_size_22, + FLD_SME_sz_23, FLD_SME_tszh, FLD_SME_tszl, FLD_SME_zero_mask, diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index eae843b593c..b0c5bb54ae4 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -2128,6 +2128,11 @@ QLF2(S_D,S_D), \ QLF2(S_Q,S_Q), \ } +#define OP_SVE_VV_BH_SD \ +{ \ + QLF2(S_B,S_S), \ + QLF2(S_H,S_D), \ +} #define OP_SVE_VV_HSD \ { \ QLF2(S_H,S_H), \ @@ -5608,6 +5613,12 @@ const struct aarch64_opcode aarch64_opcode_table[] = SME2_INSN ("smlsll", 0xc1a10008, 0xffa39c7e, sme_int_sd, 0, OP3 (SME_ZA_array_off1x4, SME_Znx4, SME_Zmx4), OP_SVE_VVV_SD_BH, F_OD (4), 0), SME2_INSN ("smopa", 0xa0800008, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_SMMHH, 0, 0), SME2_INSN ("smops", 0xa0800018, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_SMMHH, 0, 0), + SME2_INSN ("sqcvt", 0xc123e000, 0xfffffc20, sme_misc, 0, OP2 (SVE_Zd, SME_Znx2), OP_SVE_HS, 0, 0), + SME2_INSN ("sqcvt", 0xc133e000, 0xff7ffc60, sme_sz_23, 0, OP2 (SVE_Zd, SME_Znx4), OP_SVE_VV_BH_SD, 0, 0), + SME2_INSN ("sqcvtn", 0xc133e040, 0xff7ffc60, sme_sz_23, 0, OP2 (SVE_Zd, SME_Znx4), OP_SVE_VV_BH_SD, 0, 0), + SME2_INSN ("sqcvtu", 0xc163e000, 0xfffffc20, sme_misc, 0, OP2 (SVE_Zd, SME_Znx2), OP_SVE_HS, 0, 0), + SME2_INSN ("sqcvtu", 0xc173e000, 0xff7ffc60, sme_sz_23, 0, OP2 (SVE_Zd, SME_Znx4), OP_SVE_VV_BH_SD, 0, 0), + SME2_INSN ("sqcvtun", 0xc173e040, 0xff7ffc60, sme_sz_23, 0, OP2 (SVE_Zd, SME_Znx4), OP_SVE_VV_BH_SD, 0, 0), SME2_INSN ("sqdmulh", 0xc120a400, 0xff30ffe1, sme_size_22, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zm), OP_SVE_VVV_BHSD, 0, 1), SME2_INSN ("sqdmulh", 0xc120ac00, 0xff30ffe3, sme_size_22, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zm), OP_SVE_VVV_BHSD, 0, 1), SME2_INSN ("sqdmulh", 0xc120b400, 0xff21ffe1, sme_size_22, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zmx2), OP_SVE_VVV_BHSD, 0, 1), @@ -5757,6 +5768,9 @@ const struct aarch64_opcode aarch64_opcode_table[] = SME2_INSN ("umlsll", 0xc1a10018, 0xffa39c7e, sme_int_sd, 0, OP3 (SME_ZA_array_off1x4, SME_Znx4, SME_Zmx4), OP_SVE_VVV_SD_BH, F_OD (4), 0), SME2_INSN ("umopa", 0xa1800008, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_SMMHH, 0, 0), SME2_INSN ("umops", 0xa1800018, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_SMMHH, 0, 0), + SME2_INSN ("uqcvt", 0xc123e020, 0xfffffc20, sme_misc, 0, OP2 (SVE_Zd, SME_Znx2), OP_SVE_HS, 0, 0), + SME2_INSN ("uqcvt", 0xc133e020, 0xff7ffc60, sme_sz_23, 0, OP2 (SVE_Zd, SME_Znx4), OP_SVE_VV_BH_SD, 0, 0), + SME2_INSN ("uqcvtn", 0xc133e060, 0xff7ffc60, sme_sz_23, 0, OP2 (SVE_Zd, SME_Znx4), OP_SVE_VV_BH_SD, 0, 0), SME2_INSN ("urshl", 0xc120a221, 0xff30ffe1, sme_size_22, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zm), OP_SVE_VVV_BHSD, 0, 1), SME2_INSN ("urshl", 0xc120aa21, 0xff30ffe3, sme_size_22, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zm), OP_SVE_VVV_BHSD, 0, 1), SME2_INSN ("urshl", 0xc120b221, 0xff21ffe1, sme_size_22, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zmx2), 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[8.43.85.97]) by mx.google.com with ESMTPS id d22-20020aa7c1d6000000b004ab4f62171asi36876005edp.279.2023.03.30.04.04.36 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Mar 2023 04:04:36 -0700 (PDT) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=M+342cyx; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 227493836BAC for ; Thu, 30 Mar 2023 10:44:35 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 227493836BAC DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1680173075; bh=plu54jA+va9kUx0E54loAckloj7itOPHt+HGLKcwg5A=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=M+342cyxhp+zoja0UtSP+lB2BxFR3I1kZWgPPGSOxJqn9gqnUWOaaJ8rZCAd5oq7x nfVYbEbZlYV7Z3UvpvPjAkADHpnbX4RwVIolnFenq5/i2jWkOnbomPmTneINwCRCgi 38srpqaIw9ONxtzCDxcIkvJvR9Cr37xq13tG2onc= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 56FF43899424 for ; Thu, 30 Mar 2023 10:27:11 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 56FF43899424 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 781CA16F2; Thu, 30 Mar 2023 03:27:55 -0700 (PDT) Received: from e121540-lin.manchester.arm.com (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id AEC093F663; Thu, 30 Mar 2023 03:27:10 -0700 (PDT) To: binutils@sourceware.org Cc: Richard Sandiford Subject: [PATCH 23/31] aarch64: Add the SME2 shift instructions Date: Thu, 30 Mar 2023 11:26:38 +0100 Message-Id: <20230330102646.3327818-24-richard.sandiford@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230330102646.3327818-1-richard.sandiford@arm.com> References: <20230330102646.3327818-1-richard.sandiford@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-31.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KAM_LOTSOFHASH, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Richard Sandiford via Binutils From: Richard Sandiford Reply-To: Richard Sandiford Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761790422716105468?= X-GMAIL-MSGID: =?utf-8?q?1761790422716105468?= There are two instruction formats here: - SQRSHR, SQRSHRU and UQRSHR, which operate on lists of two or four registers. - SQRSHRN, SQRSHRUN and UQRSHRN, which operate on lists of four registers. These are the first SME2 instructions to have immediate operands. The patch makes sure that, when parsing SME2 instructions with immediate operands, the new predicate-as-counter registers are parsed as registers rather than as #-less immediates. --- gas/config/tc-aarch64.c | 17 +- gas/testsuite/gas/aarch64/sme2-27-invalid.d | 3 + gas/testsuite/gas/aarch64/sme2-27-invalid.l | 31 + gas/testsuite/gas/aarch64/sme2-27-invalid.s | 25 + gas/testsuite/gas/aarch64/sme2-27-noarch.d | 3 + gas/testsuite/gas/aarch64/sme2-27-noarch.l | 50 + gas/testsuite/gas/aarch64/sme2-27.d | 62 ++ gas/testsuite/gas/aarch64/sme2-27.s | 71 ++ gas/testsuite/gas/aarch64/sme2-28-invalid.d | 3 + gas/testsuite/gas/aarch64/sme2-28-invalid.l | 19 + gas/testsuite/gas/aarch64/sme2-28-invalid.s | 11 + gas/testsuite/gas/aarch64/sme2-28-noarch.d | 3 + gas/testsuite/gas/aarch64/sme2-28-noarch.l | 26 + gas/testsuite/gas/aarch64/sme2-28.d | 34 + gas/testsuite/gas/aarch64/sme2-28.s | 29 + include/opcode/aarch64.h | 3 + opcodes/aarch64-asm-2.c | 23 +- opcodes/aarch64-asm.c | 14 + opcodes/aarch64-asm.h | 1 + opcodes/aarch64-dis-2.c | 1092 ++++++++++--------- opcodes/aarch64-dis.c | 17 + opcodes/aarch64-dis.h | 1 + opcodes/aarch64-opc-2.c | 2 + opcodes/aarch64-opc.c | 12 + opcodes/aarch64-tbl.h | 22 + 25 files changed, 1066 insertions(+), 508 deletions(-) create mode 100644 gas/testsuite/gas/aarch64/sme2-27-invalid.d create mode 100644 gas/testsuite/gas/aarch64/sme2-27-invalid.l create mode 100644 gas/testsuite/gas/aarch64/sme2-27-invalid.s create mode 100644 gas/testsuite/gas/aarch64/sme2-27-noarch.d create mode 100644 gas/testsuite/gas/aarch64/sme2-27-noarch.l create mode 100644 gas/testsuite/gas/aarch64/sme2-27.d create mode 100644 gas/testsuite/gas/aarch64/sme2-27.s create mode 100644 gas/testsuite/gas/aarch64/sme2-28-invalid.d create mode 100644 gas/testsuite/gas/aarch64/sme2-28-invalid.l create mode 100644 gas/testsuite/gas/aarch64/sme2-28-invalid.s create mode 100644 gas/testsuite/gas/aarch64/sme2-28-noarch.d create mode 100644 gas/testsuite/gas/aarch64/sme2-28-noarch.l create mode 100644 gas/testsuite/gas/aarch64/sme2-28.d create mode 100644 gas/testsuite/gas/aarch64/sme2-28.s diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 2c8d5916182..781c87bbc41 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -349,6 +349,13 @@ struct reloc_entry | REG_TYPE(FP_B) | REG_TYPE(FP_H) \ | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q) \ | REG_TYPE(Z) | REG_TYPE(P)) \ + /* Likewise, but with predicate-as-counter registers added. */ \ + MULTI_REG_TYPE(R_ZR_SP_BHSDQ_VZP_PN, REG_TYPE(R_32) | REG_TYPE(R_64) \ + | REG_TYPE(SP_32) | REG_TYPE(SP_64) \ + | REG_TYPE(ZR_32) | REG_TYPE(ZR_64) | REG_TYPE(V) \ + | REG_TYPE(FP_B) | REG_TYPE(FP_H) \ + | REG_TYPE(FP_S) | REG_TYPE(FP_D) | REG_TYPE(FP_Q) \ + | REG_TYPE(Z) | REG_TYPE(P) | REG_TYPE(PN)) \ /* Any integer register; used for error messages only. */ \ MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64) \ | REG_TYPE(SP_32) | REG_TYPE(SP_64) \ @@ -6527,9 +6534,11 @@ parse_operands (char *str, const aarch64_opcode *opcode) clear_error (); skip_whitespace (str); - if (AARCH64_CPU_HAS_ANY_FEATURES (*opcode->avariant, - AARCH64_FEATURE_SVE - | AARCH64_FEATURE_SVE2)) + if (AARCH64_CPU_HAS_FEATURE (*opcode->avariant, AARCH64_FEATURE_SME2)) + imm_reg_type = REG_TYPE_R_ZR_SP_BHSDQ_VZP_PN; + else if (AARCH64_CPU_HAS_ANY_FEATURES (*opcode->avariant, + AARCH64_FEATURE_SVE + | AARCH64_FEATURE_SVE2)) imm_reg_type = REG_TYPE_R_ZR_SP_BHSDQ_VZP; else imm_reg_type = REG_TYPE_R_ZR_BHSDQ_V; @@ -6892,6 +6901,8 @@ parse_operands (char *str, const aarch64_opcode *opcode) case AARCH64_OPND_SVE_SHLIMM_PRED: case AARCH64_OPND_SVE_SHLIMM_UNPRED: case AARCH64_OPND_SVE_SHLIMM_UNPRED_22: + case AARCH64_OPND_SME_SHRIMM4: + case AARCH64_OPND_SME_SHRIMM5: case AARCH64_OPND_SVE_SHRIMM_PRED: case AARCH64_OPND_SVE_SHRIMM_UNPRED: case AARCH64_OPND_SVE_SHRIMM_UNPRED_22: diff --git a/gas/testsuite/gas/aarch64/sme2-27-invalid.d b/gas/testsuite/gas/aarch64/sme2-27-invalid.d new file mode 100644 index 00000000000..7b34ec4ce67 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-27-invalid.d @@ -0,0 +1,3 @@ +#as: -march=armv8-a +#source: sme2-27-invalid.s +#error_output: sme2-27-invalid.l diff --git a/gas/testsuite/gas/aarch64/sme2-27-invalid.l b/gas/testsuite/gas/aarch64/sme2-27-invalid.l new file mode 100644 index 00000000000..9efaa04ca90 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-27-invalid.l @@ -0,0 +1,31 @@ +[^ :]+: Assembler messages: +[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqrshr 0,{z0\.s-z1\.s},#1' +[^ :]+:[0-9]+: Error: expected '{' at operand 2 -- `sqrshr z0\.h,0,#1' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqrshr z0\.h,{z1\.s-z2\.s},#1' +[^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `sqrshr z0\.h,{z0\.s-z1\.s},#0' +[^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `sqrshr z0\.h,{z0\.s-z1\.s},#17' +[^ :]+:[0-9]+: Error: operand mismatch -- `sqrshr z0\.s,{z0\.d-z1\.d},#1' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: sqrshr z0\.h, {z0\.d-z1\.d}, #1 +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: sqrshr z0\.b, {z0\.s-z1\.s}, #1 +[^ :]+:[0-9]+: Error: immediate operand required at operand 3 -- `sqrshr z0\.h,{z0\.s-z1\.s},x0' +[^ :]+:[0-9]+: Error: immediate operand required at operand 3 -- `sqrshr z0\.h,{z0\.s-z1\.s},z0\.s' +[^ :]+:[0-9]+: Error: immediate operand required at operand 3 -- `sqrshr z0\.h,{z0\.s-z1\.s},p0' +[^ :]+:[0-9]+: Error: immediate operand required at operand 3 -- `sqrshr z0\.h,{z0\.s-z1\.s},pn0' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqrshr z0\.b,{z1\.s-z4\.s},#1' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqrshr z0\.b,{z2\.s-z5\.s},#1' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqrshr z0\.b,{z3\.s-z6\.s},#1' +[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqrshr z0\.b,{z0\.s-z3\.s},#-1' +[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqrshr z0\.b,{z0\.s-z3\.s},#0' +[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqrshr z0\.b,{z0\.s-z3\.s},#33' +[^ :]+:[0-9]+: Error: operand mismatch -- `sqrshr z0\.b,{z0\.d-z3\.d},#1' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: sqrshr z0\.b, {z0\.s-z3\.s}, #1 +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: sqrshr z0\.h, {z0\.d-z3\.d}, #1 +[^ :]+:[0-9]+: Error: operand mismatch -- `sqrshr z0\.b,{z0\.d-z3\.d},#65' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: sqrshr z0\.b, {z0\.s-z3\.s}, #65 +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: sqrshr z0\.h, {z0\.d-z3\.d}, #65 diff --git a/gas/testsuite/gas/aarch64/sme2-27-invalid.s b/gas/testsuite/gas/aarch64/sme2-27-invalid.s new file mode 100644 index 00000000000..3a613af9a8d --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-27-invalid.s @@ -0,0 +1,25 @@ + .equ x0, 1 + .equ z0.s, 2 + .equ p0, 3 + .equ pn0, 4 + + sqrshr 0, { z0.s - z1.s }, #1 + sqrshr z0.h, 0, #1 + + sqrshr z0.h, { z1.s - z2.s }, #1 + sqrshr z0.h, { z0.s - z1.s }, #0 + sqrshr z0.h, { z0.s - z1.s }, #17 + sqrshr z0.s, { z0.d - z1.d }, #1 + sqrshr z0.h, { z0.s - z1.s }, x0 + sqrshr z0.h, { z0.s - z1.s }, z0.s + sqrshr z0.h, { z0.s - z1.s }, p0 + sqrshr z0.h, { z0.s - z1.s }, pn0 + + sqrshr z0.b, { z1.s - z4.s }, #1 + sqrshr z0.b, { z2.s - z5.s }, #1 + sqrshr z0.b, { z3.s - z6.s }, #1 + sqrshr z0.b, { z0.s - z3.s }, #-1 + sqrshr z0.b, { z0.s - z3.s }, #0 + sqrshr z0.b, { z0.s - z3.s }, #33 + sqrshr z0.b, { z0.d - z3.d }, #1 + sqrshr z0.b, { z0.d - z3.d }, #65 // Double error diff --git a/gas/testsuite/gas/aarch64/sme2-27-noarch.d b/gas/testsuite/gas/aarch64/sme2-27-noarch.d new file mode 100644 index 00000000000..f0e735db033 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-27-noarch.d @@ -0,0 +1,3 @@ +#as: -march=armv8-a+sme +#source: sme2-27.s +#error_output: sme2-27-noarch.l diff --git a/gas/testsuite/gas/aarch64/sme2-27-noarch.l b/gas/testsuite/gas/aarch64/sme2-27-noarch.l new file mode 100644 index 00000000000..72213e0c281 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-27-noarch.l @@ -0,0 +1,50 @@ +[^ :]+: Assembler messages: +[^ :]+:[0-9]+: Error: selected processor does not support `sqrshr z0\.h,{z0\.s-z1\.s},#1' +[^ :]+:[0-9]+: Error: selected processor does not support `sqrshr z31\.h,{z0\.s-z1\.s},#1' +[^ :]+:[0-9]+: Error: selected processor does not support `sqrshr z0\.h,{z30\.s-z31\.s},#1' +[^ :]+:[0-9]+: Error: selected processor does not support `sqrshr z0\.h,{z0\.s-z1\.s},#16' +[^ :]+:[0-9]+: Error: selected processor does not support `sqrshr z14\.h,{z22\.s-z23\.s},#7' +[^ :]+:[0-9]+: Error: selected processor does not support `sqrshr z0\.h,{z0\.s-z1\.s},#x0' +[^ :]+:[0-9]+: Error: selected processor does not support `sqrshr z0\.h,{z0\.s-z1\.s},#z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `sqrshr z0\.h,{z0\.s-z1\.s},#p0' +[^ :]+:[0-9]+: Error: selected processor does not support `sqrshr z0\.h,{z0\.s-z1\.s},#pn0' +[^ :]+:[0-9]+: Error: selected processor does not support `sqrshr z0\.b,{z0\.s-z3\.s},#1' +[^ :]+:[0-9]+: Error: selected processor does not support `sqrshr z31\.b,{z0\.s-z3\.s},#1' +[^ :]+:[0-9]+: Error: selected processor does not support `sqrshr z0\.b,{z28\.s-z31\.s},#1' +[^ :]+:[0-9]+: Error: selected processor does not support `sqrshr z0\.b,{z0\.s-z3\.s},#32' +[^ :]+:[0-9]+: Error: selected processor does not support `sqrshr z6\.b,{z12\.s-z15\.s},#25' +[^ :]+:[0-9]+: Error: selected processor does not support `sqrshr z0\.h,{z0\.d-z3\.d},#1' +[^ :]+:[0-9]+: Error: selected processor does not support `sqrshr z31\.h,{z0\.d-z3\.d},#1' +[^ :]+:[0-9]+: Error: selected processor does not support `sqrshr z0\.h,{z28\.d-z31\.d},#1' +[^ :]+:[0-9]+: Error: selected processor does not support `sqrshr z0\.h,{z0\.d-z3\.d},#64' +[^ :]+:[0-9]+: Error: selected processor does not support `sqrshr z25\.h,{z20\.d-z23\.d},#50' +[^ :]+:[0-9]+: Error: selected processor does not support `sqrshru z0\.h,{z0\.s-z1\.s},#1' +[^ :]+:[0-9]+: Error: selected processor does not support `sqrshru z31\.h,{z0\.s-z1\.s},#1' +[^ :]+:[0-9]+: Error: selected processor does not support `sqrshru z0\.h,{z30\.s-z31\.s},#1' +[^ :]+:[0-9]+: Error: selected processor does not support `sqrshru z0\.h,{z0\.s-z1\.s},#16' +[^ :]+:[0-9]+: Error: selected processor does not support `sqrshru z14\.h,{z22\.s-z23\.s},#7' +[^ :]+:[0-9]+: Error: selected processor does not support `sqrshru z0\.b,{z0\.s-z3\.s},#1' +[^ :]+:[0-9]+: Error: selected processor does not support `sqrshru z31\.b,{z0\.s-z3\.s},#1' +[^ :]+:[0-9]+: Error: selected processor does not support `sqrshru z0\.b,{z28\.s-z31\.s},#1' +[^ :]+:[0-9]+: Error: selected processor does not support `sqrshru z0\.b,{z0\.s-z3\.s},#32' +[^ :]+:[0-9]+: Error: selected processor does not support `sqrshru z6\.b,{z12\.s-z15\.s},#25' +[^ :]+:[0-9]+: Error: selected processor does not support `sqrshru z0\.h,{z0\.d-z3\.d},#1' +[^ :]+:[0-9]+: Error: selected processor does not support `sqrshru z31\.h,{z0\.d-z3\.d},#1' +[^ :]+:[0-9]+: Error: selected processor does not support `sqrshru z0\.h,{z28\.d-z31\.d},#1' +[^ :]+:[0-9]+: Error: selected processor does not support `sqrshru z0\.h,{z0\.d-z3\.d},#64' +[^ :]+:[0-9]+: Error: selected processor does not support `sqrshru z25\.h,{z20\.d-z23\.d},#50' +[^ :]+:[0-9]+: Error: selected processor does not support `uqrshr z0\.h,{z0\.s-z1\.s},#1' +[^ :]+:[0-9]+: Error: selected processor does not support `uqrshr z31\.h,{z0\.s-z1\.s},#1' +[^ :]+:[0-9]+: Error: selected processor does not support `uqrshr z0\.h,{z30\.s-z31\.s},#1' +[^ :]+:[0-9]+: Error: selected processor does not support `uqrshr z0\.h,{z0\.s-z1\.s},#16' +[^ :]+:[0-9]+: Error: selected processor does not support `uqrshr z14\.h,{z22\.s-z23\.s},#7' +[^ :]+:[0-9]+: Error: selected processor does not support `uqrshr z0\.b,{z0\.s-z3\.s},#1' +[^ :]+:[0-9]+: Error: selected processor does not support `uqrshr z31\.b,{z0\.s-z3\.s},#1' +[^ :]+:[0-9]+: Error: selected processor does not support `uqrshr z0\.b,{z28\.s-z31\.s},#1' +[^ :]+:[0-9]+: Error: selected processor does not support `uqrshr z0\.b,{z0\.s-z3\.s},#32' +[^ :]+:[0-9]+: Error: selected processor does not support `uqrshr z6\.b,{z12\.s-z15\.s},#25' +[^ :]+:[0-9]+: Error: selected processor does not support `uqrshr z0\.h,{z0\.d-z3\.d},#1' +[^ :]+:[0-9]+: Error: selected processor does not support `uqrshr z31\.h,{z0\.d-z3\.d},#1' +[^ :]+:[0-9]+: Error: selected processor does not support `uqrshr z0\.h,{z28\.d-z31\.d},#1' +[^ :]+:[0-9]+: Error: selected processor does not support `uqrshr z0\.h,{z0\.d-z3\.d},#64' +[^ :]+:[0-9]+: Error: selected processor does not support `uqrshr z25\.h,{z20\.d-z23\.d},#50' diff --git a/gas/testsuite/gas/aarch64/sme2-27.d b/gas/testsuite/gas/aarch64/sme2-27.d new file mode 100644 index 00000000000..e217715489e --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-27.d @@ -0,0 +1,62 @@ +#as: -march=armv8-a+sme2 +#objdump: -dr + +[^:]+: file format .* + + +[^:]+: + +[^:]+: +[^:]+: c1efd400 sqrshr z0\.h, {z0\.s-z1\.s}, #1 +[^:]+: c1efd41f sqrshr z31\.h, {z0\.s-z1\.s}, #1 +[^:]+: c1efd7c0 sqrshr z0\.h, {z30\.s-z31\.s}, #1 +[^:]+: c1e0d400 sqrshr z0\.h, {z0\.s-z1\.s}, #16 +[^:]+: c1e9d6ce sqrshr z14\.h, {z22\.s-z23\.s}, #7 +[^:]+: c1efd400 sqrshr z0\.h, {z0\.s-z1\.s}, #1 +[^:]+: c1eed400 sqrshr z0\.h, {z0\.s-z1\.s}, #2 +[^:]+: c1edd400 sqrshr z0\.h, {z0\.s-z1\.s}, #3 +[^:]+: c1ecd400 sqrshr z0\.h, {z0\.s-z1\.s}, #4 +[^:]+: c17fd800 sqrshr z0\.b, {z0\.s-z3\.s}, #1 +[^:]+: c17fd81f sqrshr z31\.b, {z0\.s-z3\.s}, #1 +[^:]+: c17fdb80 sqrshr z0\.b, {z28\.s-z31\.s}, #1 +[^:]+: c160d800 sqrshr z0\.b, {z0\.s-z3\.s}, #32 +[^:]+: c167d986 sqrshr z6\.b, {z12\.s-z15\.s}, #25 +[^:]+: c1ffd800 sqrshr z0\.h, {z0\.d-z3\.d}, #1 +[^:]+: c1ffd81f sqrshr z31\.h, {z0\.d-z3\.d}, #1 +[^:]+: c1ffdb80 sqrshr z0\.h, {z28\.d-z31\.d}, #1 +[^:]+: c1a0d800 sqrshr z0\.h, {z0\.d-z3\.d}, #64 +[^:]+: c1aeda99 sqrshr z25\.h, {z20\.d-z23\.d}, #50 +[^:]+: c13fd800 \.inst 0xc13fd800 ; undefined +[^:]+: c120d800 \.inst 0xc120d800 ; undefined +[^:]+: c1ffd400 sqrshru z0\.h, {z0\.s-z1\.s}, #1 +[^:]+: c1ffd41f sqrshru z31\.h, {z0\.s-z1\.s}, #1 +[^:]+: c1ffd7c0 sqrshru z0\.h, {z30\.s-z31\.s}, #1 +[^:]+: c1f0d400 sqrshru z0\.h, {z0\.s-z1\.s}, #16 +[^:]+: c1f9d6ce sqrshru z14\.h, {z22\.s-z23\.s}, #7 +[^:]+: c17fd840 sqrshru z0\.b, {z0\.s-z3\.s}, #1 +[^:]+: c17fd85f sqrshru z31\.b, {z0\.s-z3\.s}, #1 +[^:]+: c17fdbc0 sqrshru z0\.b, {z28\.s-z31\.s}, #1 +[^:]+: c160d840 sqrshru z0\.b, {z0\.s-z3\.s}, #32 +[^:]+: c167d9c6 sqrshru z6\.b, {z12\.s-z15\.s}, #25 +[^:]+: c1ffd840 sqrshru z0\.h, {z0\.d-z3\.d}, #1 +[^:]+: c1ffd85f sqrshru z31\.h, {z0\.d-z3\.d}, #1 +[^:]+: c1ffdbc0 sqrshru z0\.h, {z28\.d-z31\.d}, #1 +[^:]+: c1a0d840 sqrshru z0\.h, {z0\.d-z3\.d}, #64 +[^:]+: c1aedad9 sqrshru z25\.h, {z20\.d-z23\.d}, #50 +[^:]+: c1efd420 uqrshr z0\.h, {z0\.s-z1\.s}, #1 +[^:]+: c1efd43f uqrshr z31\.h, {z0\.s-z1\.s}, #1 +[^:]+: c1efd7e0 uqrshr z0\.h, {z30\.s-z31\.s}, #1 +[^:]+: c1e0d420 uqrshr z0\.h, {z0\.s-z1\.s}, #16 +[^:]+: c1e9d6ee uqrshr z14\.h, {z22\.s-z23\.s}, #7 +[^:]+: c17fd820 uqrshr z0\.b, {z0\.s-z3\.s}, #1 +[^:]+: c17fd83f uqrshr z31\.b, {z0\.s-z3\.s}, #1 +[^:]+: c17fdba0 uqrshr z0\.b, {z28\.s-z31\.s}, #1 +[^:]+: c160d820 uqrshr z0\.b, {z0\.s-z3\.s}, #32 +[^:]+: c167d9a6 uqrshr z6\.b, {z12\.s-z15\.s}, #25 +[^:]+: c1ffd820 uqrshr z0\.h, {z0\.d-z3\.d}, #1 +[^:]+: c1ffd83f uqrshr z31\.h, {z0\.d-z3\.d}, #1 +[^:]+: c1ffdba0 uqrshr z0\.h, {z28\.d-z31\.d}, #1 +[^:]+: c1a0d820 uqrshr z0\.h, {z0\.d-z3\.d}, #64 +[^:]+: c1aedab9 uqrshr z25\.h, {z20\.d-z23\.d}, #50 +[^:]+: c13fd820 \.inst 0xc13fd820 ; undefined +[^:]+: c120d820 \.inst 0xc120d820 ; undefined diff --git a/gas/testsuite/gas/aarch64/sme2-27.s b/gas/testsuite/gas/aarch64/sme2-27.s new file mode 100644 index 00000000000..e7e04ba68c9 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-27.s @@ -0,0 +1,71 @@ + .equ x0, 1 + .equ z0.s, 2 + .equ p0, 3 + .equ pn0, 4 + + sqrshr z0.h, { z0.s - z1.s }, #1 + sqrshr z31.h, { z0.s - z1.s }, #1 + sqrshr z0.h, { z30.s - z31.s }, #1 + sqrshr z0.h, { z0.s - z1.s }, #16 + sqrshr z14.h, { z22.s - z23.s }, #7 + + sqrshr z0.h, { z0.s - z1.s }, #x0 + sqrshr z0.h, { z0.s - z1.s }, #z0.s + sqrshr z0.h, { z0.s - z1.s }, #p0 + sqrshr z0.h, { z0.s - z1.s }, #pn0 + + sqrshr z0.b, { z0.s - z3.s }, #1 + sqrshr z31.b, { z0.s - z3.s }, #1 + sqrshr z0.b, { z28.s - z31.s }, #1 + sqrshr z0.b, { z0.s - z3.s }, #32 + sqrshr z6.b, { z12.s - z15.s }, #25 + + sqrshr z0.h, { z0.d - z3.d }, #1 + sqrshr z31.h, { z0.d - z3.d }, #1 + sqrshr z0.h, { z28.d - z31.d }, #1 + sqrshr z0.h, { z0.d - z3.d }, #64 + sqrshr z25.h, { z20.d - z23.d }, #50 + + // Invalid SQRSHR + .inst 0xc13fd800 + .inst 0xc120d800 + + sqrshru z0.h, { z0.s - z1.s }, #1 + sqrshru z31.h, { z0.s - z1.s }, #1 + sqrshru z0.h, { z30.s - z31.s }, #1 + sqrshru z0.h, { z0.s - z1.s }, #16 + sqrshru z14.h, { z22.s - z23.s }, #7 + + sqrshru z0.b, { z0.s - z3.s }, #1 + sqrshru z31.b, { z0.s - z3.s }, #1 + sqrshru z0.b, { z28.s - z31.s }, #1 + sqrshru z0.b, { z0.s - z3.s }, #32 + sqrshru z6.b, { z12.s - z15.s }, #25 + + sqrshru z0.h, { z0.d - z3.d }, #1 + sqrshru z31.h, { z0.d - z3.d }, #1 + sqrshru z0.h, { z28.d - z31.d }, #1 + sqrshru z0.h, { z0.d - z3.d }, #64 + sqrshru z25.h, { z20.d - z23.d }, #50 + + uqrshr z0.h, { z0.s - z1.s }, #1 + uqrshr z31.h, { z0.s - z1.s }, #1 + uqrshr z0.h, { z30.s - z31.s }, #1 + uqrshr z0.h, { z0.s - z1.s }, #16 + uqrshr z14.h, { z22.s - z23.s }, #7 + + uqrshr z0.b, { z0.s - z3.s }, #1 + uqrshr z31.b, { z0.s - z3.s }, #1 + uqrshr z0.b, { z28.s - z31.s }, #1 + uqrshr z0.b, { z0.s - z3.s }, #32 + uqrshr z6.b, { z12.s - z15.s }, #25 + + uqrshr z0.h, { z0.d - z3.d }, #1 + uqrshr z31.h, { z0.d - z3.d }, #1 + uqrshr z0.h, { z28.d - z31.d }, #1 + uqrshr z0.h, { z0.d - z3.d }, #64 + uqrshr z25.h, { z20.d - z23.d }, #50 + + // Invalid UQRSHR + .inst 0xc13fd820 + .inst 0xc120d820 diff --git a/gas/testsuite/gas/aarch64/sme2-28-invalid.d b/gas/testsuite/gas/aarch64/sme2-28-invalid.d new file mode 100644 index 00000000000..dbe03ce0a7c --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-28-invalid.d @@ -0,0 +1,3 @@ +#as: -march=armv8-a +#source: sme2-28-invalid.s +#error_output: sme2-28-invalid.l diff --git a/gas/testsuite/gas/aarch64/sme2-28-invalid.l b/gas/testsuite/gas/aarch64/sme2-28-invalid.l new file mode 100644 index 00000000000..615f8c35039 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-28-invalid.l @@ -0,0 +1,19 @@ +[^ :]+: Assembler messages: +[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sqrshrn 0,{z0\.s-z3\.s},#1' +[^ :]+:[0-9]+: Error: expected '{' at operand 2 -- `sqrshrn z0\.b,0,#1' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqrshrn z0\.b,{z1\.s-z4\.s},#1' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqrshrn z0\.b,{z2\.s-z5\.s},#1' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqrshrn z0\.b,{z3\.s-z6\.s},#1' +[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqrshrn z0\.b,{z0\.s-z3\.s},#-1' +[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqrshrn z0\.b,{z0\.s-z3\.s},#0' +[^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqrshrn z0\.b,{z0\.s-z3\.s},#33' +[^ :]+:[0-9]+: Error: operand mismatch -- `sqrshrn z0\.b,{z0\.d-z3\.d},#1' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: sqrshrn z0\.b, {z0\.s-z3\.s}, #1 +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: sqrshrn z0\.h, {z0\.d-z3\.d}, #1 +[^ :]+:[0-9]+: Error: operand mismatch -- `sqrshrn z0\.b,{z0\.d-z3\.d},#65' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: sqrshrn z0\.b, {z0\.s-z3\.s}, #65 +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: sqrshrn z0\.h, {z0\.d-z3\.d}, #65 diff --git a/gas/testsuite/gas/aarch64/sme2-28-invalid.s b/gas/testsuite/gas/aarch64/sme2-28-invalid.s new file mode 100644 index 00000000000..f587049967e --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-28-invalid.s @@ -0,0 +1,11 @@ + sqrshrn 0, { z0.s - z3.s }, #1 + sqrshrn z0.b, 0, #1 + + sqrshrn z0.b, { z1.s - z4.s }, #1 + sqrshrn z0.b, { z2.s - z5.s }, #1 + sqrshrn z0.b, { z3.s - z6.s }, #1 + sqrshrn z0.b, { z0.s - z3.s }, #-1 + sqrshrn z0.b, { z0.s - z3.s }, #0 + sqrshrn z0.b, { z0.s - z3.s }, #33 + sqrshrn z0.b, { z0.d - z3.d }, #1 + sqrshrn z0.b, { z0.d - z3.d }, #65 // Double error diff --git a/gas/testsuite/gas/aarch64/sme2-28-noarch.d b/gas/testsuite/gas/aarch64/sme2-28-noarch.d new file mode 100644 index 00000000000..de378eb1998 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-28-noarch.d @@ -0,0 +1,3 @@ +#as: -march=armv8-a+sme +#source: sme2-28.s +#error_output: sme2-28-noarch.l diff --git a/gas/testsuite/gas/aarch64/sme2-28-noarch.l b/gas/testsuite/gas/aarch64/sme2-28-noarch.l new file mode 100644 index 00000000000..a3762f1b9a9 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-28-noarch.l @@ -0,0 +1,26 @@ +[^ :]+: Assembler messages: +[^ :]+:[0-9]+: Error: selected processor does not support `sqrshrn z0\.b,{z0\.s-z3\.s},#1' +[^ :]+:[0-9]+: Error: selected processor does not support `sqrshrn z31\.b,{z0\.s-z3\.s},#1' +[^ :]+:[0-9]+: Error: selected processor does not support `sqrshrn z0\.b,{z28\.s-z31\.s},#1' +[^ :]+:[0-9]+: Error: selected processor does not support `sqrshrn z0\.b,{z0\.s-z3\.s},#32' +[^ :]+:[0-9]+: Error: selected processor does not support `sqrshrn z6\.b,{z12\.s-z15\.s},#25' +[^ :]+:[0-9]+: Error: selected processor does not support `sqrshrn z0\.h,{z0\.d-z3\.d},#1' +[^ :]+:[0-9]+: Error: selected processor does not support `sqrshrn z31\.h,{z0\.d-z3\.d},#1' +[^ :]+:[0-9]+: Error: selected processor does not support `sqrshrn z0\.h,{z28\.d-z31\.d},#1' +[^ :]+:[0-9]+: Error: selected processor does not support `sqrshrn z0\.h,{z0\.d-z3\.d},#64' +[^ :]+:[0-9]+: Error: selected processor does not support `sqrshrn z25\.h,{z20\.d-z23\.d},#50' +[^ :]+:[0-9]+: Error: selected processor does not support `sqrshrun z0\.b,{z0\.s-z3\.s},#1' +[^ :]+:[0-9]+: Error: selected processor does not support `sqrshrun z31\.b,{z0\.s-z3\.s},#1' +[^ :]+:[0-9]+: Error: selected processor does not support `sqrshrun z0\.b,{z28\.s-z31\.s},#1' +[^ :]+:[0-9]+: Error: selected processor does not support `sqrshrun z0\.b,{z0\.s-z3\.s},#32' +[^ :]+:[0-9]+: Error: selected processor does not support `sqrshrun z6\.b,{z12\.s-z15\.s},#25' +[^ :]+:[0-9]+: Error: selected processor does not support `uqrshrn z0\.b,{z0\.s-z3\.s},#1' +[^ :]+:[0-9]+: Error: selected processor does not support `uqrshrn z31\.b,{z0\.s-z3\.s},#1' +[^ :]+:[0-9]+: Error: selected processor does not support `uqrshrn z0\.b,{z28\.s-z31\.s},#1' +[^ :]+:[0-9]+: Error: selected processor does not support `uqrshrn z0\.b,{z0\.s-z3\.s},#32' +[^ :]+:[0-9]+: Error: selected processor does not support `uqrshrn z6\.b,{z12\.s-z15\.s},#25' +[^ :]+:[0-9]+: Error: selected processor does not support `uqrshrn z0\.h,{z0\.d-z3\.d},#1' +[^ :]+:[0-9]+: Error: selected processor does not support `uqrshrn z31\.h,{z0\.d-z3\.d},#1' +[^ :]+:[0-9]+: Error: selected processor does not support `uqrshrn z0\.h,{z28\.d-z31\.d},#1' +[^ :]+:[0-9]+: Error: selected processor does not support `uqrshrn z0\.h,{z0\.d-z3\.d},#64' +[^ :]+:[0-9]+: Error: selected processor does not support `uqrshrn z25\.h,{z20\.d-z23\.d},#50' diff --git a/gas/testsuite/gas/aarch64/sme2-28.d b/gas/testsuite/gas/aarch64/sme2-28.d new file mode 100644 index 00000000000..b72273dd548 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-28.d @@ -0,0 +1,34 @@ +#as: -march=armv8-a+sme2 +#objdump: -dr + +[^:]+: file format .* + + +[^:]+: + +[^:]+: +[^:]+: c17fdc00 sqrshrn z0\.b, {z0\.s-z3\.s}, #1 +[^:]+: c17fdc1f sqrshrn z31\.b, {z0\.s-z3\.s}, #1 +[^:]+: c17fdf80 sqrshrn z0\.b, {z28\.s-z31\.s}, #1 +[^:]+: c160dc00 sqrshrn z0\.b, {z0\.s-z3\.s}, #32 +[^:]+: c167dd86 sqrshrn z6\.b, {z12\.s-z15\.s}, #25 +[^:]+: c1ffdc00 sqrshrn z0\.h, {z0\.d-z3\.d}, #1 +[^:]+: c1ffdc1f sqrshrn z31\.h, {z0\.d-z3\.d}, #1 +[^:]+: c1ffdf80 sqrshrn z0\.h, {z28\.d-z31\.d}, #1 +[^:]+: c1a0dc00 sqrshrn z0\.h, {z0\.d-z3\.d}, #64 +[^:]+: c1aede99 sqrshrn z25\.h, {z20\.d-z23\.d}, #50 +[^:]+: c17fdc40 sqrshrun z0\.b, {z0\.s-z3\.s}, #1 +[^:]+: c17fdc5f sqrshrun z31\.b, {z0\.s-z3\.s}, #1 +[^:]+: c17fdfc0 sqrshrun z0\.b, {z28\.s-z31\.s}, #1 +[^:]+: c160dc40 sqrshrun z0\.b, {z0\.s-z3\.s}, #32 +[^:]+: c167ddc6 sqrshrun z6\.b, {z12\.s-z15\.s}, #25 +[^:]+: c17fdc20 uqrshrn z0\.b, {z0\.s-z3\.s}, #1 +[^:]+: c17fdc3f uqrshrn z31\.b, {z0\.s-z3\.s}, #1 +[^:]+: c17fdfa0 uqrshrn z0\.b, {z28\.s-z31\.s}, #1 +[^:]+: c160dc20 uqrshrn z0\.b, {z0\.s-z3\.s}, #32 +[^:]+: c167dda6 uqrshrn z6\.b, {z12\.s-z15\.s}, #25 +[^:]+: c1ffdc20 uqrshrn z0\.h, {z0\.d-z3\.d}, #1 +[^:]+: c1ffdc3f uqrshrn z31\.h, {z0\.d-z3\.d}, #1 +[^:]+: c1ffdfa0 uqrshrn z0\.h, {z28\.d-z31\.d}, #1 +[^:]+: c1a0dc20 uqrshrn z0\.h, {z0\.d-z3\.d}, #64 +[^:]+: c1aedeb9 uqrshrn z25\.h, {z20\.d-z23\.d}, #50 diff --git a/gas/testsuite/gas/aarch64/sme2-28.s b/gas/testsuite/gas/aarch64/sme2-28.s new file mode 100644 index 00000000000..3b51448288e --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-28.s @@ -0,0 +1,29 @@ + sqrshrn z0.b, { z0.s - z3.s }, #1 + sqrshrn z31.b, { z0.s - z3.s }, #1 + sqrshrn z0.b, { z28.s - z31.s }, #1 + sqrshrn z0.b, { z0.s - z3.s }, #32 + sqrshrn z6.b, { z12.s - z15.s }, #25 + + sqrshrn z0.h, { z0.d - z3.d }, #1 + sqrshrn z31.h, { z0.d - z3.d }, #1 + sqrshrn z0.h, { z28.d - z31.d }, #1 + sqrshrn z0.h, { z0.d - z3.d }, #64 + sqrshrn z25.h, { z20.d - z23.d }, #50 + + sqrshrun z0.b, { z0.s - z3.s }, #1 + sqrshrun z31.b, { z0.s - z3.s }, #1 + sqrshrun z0.b, { z28.s - z31.s }, #1 + sqrshrun z0.b, { z0.s - z3.s }, #32 + sqrshrun z6.b, { z12.s - z15.s }, #25 + + uqrshrn z0.b, { z0.s - z3.s }, #1 + uqrshrn z31.b, { z0.s - z3.s }, #1 + uqrshrn z0.b, { z28.s - z31.s }, #1 + uqrshrn z0.b, { z0.s - z3.s }, #32 + uqrshrn z6.b, { z12.s - z15.s }, #25 + + uqrshrn z0.h, { z0.d - z3.d }, #1 + uqrshrn z31.h, { z0.d - z3.d }, #1 + uqrshrn z0.h, { z28.d - z31.d }, #1 + uqrshrn z0.h, { z0.d - z3.d }, #64 + uqrshrn z25.h, { z20.d - z23.d }, #50 diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index b445bf758fc..a4f1623d4ca 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -520,6 +520,8 @@ enum aarch64_opnd AARCH64_OPND_SME_ADDR_RI_U4xVL, /* SME [{, #, MUL VL}]. */ AARCH64_OPND_SME_SM_ZA, /* SME {SM | ZA}. */ AARCH64_OPND_SME_PnT_Wm_imm, /* SME .[, #]. */ + AARCH64_OPND_SME_SHRIMM4, /* 4-bit right shift, bits [19:16]. */ + AARCH64_OPND_SME_SHRIMM5, /* size + 5-bit right shift, bits [23:22,20:16]. */ AARCH64_OPND_SME_Zm_INDEX1, /* Zn.T[index], bits [19:16,10]. */ AARCH64_OPND_SME_Zm_INDEX2, /* Zn.T[index], bits [19:16,11:10]. */ AARCH64_OPND_SME_Zm_INDEX3_1, /* Zn.T[index], bits [19:16,10,2:1]. */ @@ -713,6 +715,7 @@ enum aarch64_insn_class sme_mov, sme_ldr, sme_psel, + sme_shift, sme_size_12_bhs, sme_size_12_hs, sme_size_22, diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c index 3d439d4e688..03d1c0e1221 100644 --- a/opcodes/aarch64-asm-2.c +++ b/opcodes/aarch64-asm-2.c @@ -685,7 +685,7 @@ aarch64_insert_operand (const aarch64_operand *self, case 33: case 34: case 35: - case 268: + case 270: return aarch64_ins_reglane (self, info, code, inst, errors); case 36: return aarch64_ins_reglist (self, info, code, inst, errors); @@ -731,12 +731,12 @@ aarch64_insert_operand (const aarch64_operand *self, case 193: case 194: case 237: - case 262: - case 263: + case 264: case 265: case 267: - case 272: - case 273: + case 269: + case 274: + case 275: return aarch64_ins_imm (self, info, code, inst, errors); case 44: case 45: @@ -805,8 +805,8 @@ aarch64_insert_operand (const aarch64_operand *self, case 107: return aarch64_ins_prfop (self, info, code, inst, errors); case 108: - case 264: case 266: + case 268: return aarch64_ins_none (self, info, code, inst, errors); case 109: return aarch64_ins_hint (self, info, code, inst, errors); @@ -886,6 +886,7 @@ aarch64_insert_operand (const aarch64_operand *self, case 184: case 185: case 186: + case 250: return aarch64_ins_sve_shrimm (self, info, code, inst, errors); case 204: case 205: @@ -919,8 +920,6 @@ aarch64_insert_operand (const aarch64_operand *self, return aarch64_ins_sme_za_hv_tiles_range (self, info, code, inst, errors); case 235: case 236: - case 249: - case 250: case 251: case 252: case 253: @@ -932,6 +931,8 @@ aarch64_insert_operand (const aarch64_operand *self, case 259: case 260: case 261: + case 262: + case 263: return aarch64_ins_simple_index (self, info, code, inst, errors); case 239: case 240: @@ -947,9 +948,11 @@ aarch64_insert_operand (const aarch64_operand *self, return aarch64_ins_sme_sm_za (self, info, code, inst, errors); case 248: return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors); - case 269: - case 270: + case 249: + return aarch64_ins_plain_shrimm (self, info, code, inst, errors); case 271: + case 272: + case 273: return aarch64_ins_x0_to_x30 (self, info, code, inst, errors); default: assert (0); abort (); } diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c index 5f2e51044ce..0025cb6f80c 100644 --- a/opcodes/aarch64-asm.c +++ b/opcodes/aarch64-asm.c @@ -1624,6 +1624,19 @@ aarch64_ins_simple_index (const aarch64_operand *self, return true; } +/* Insert a plain shift-right immediate, when there is only a single + element size. */ +bool +aarch64_ins_plain_shrimm (const aarch64_operand *self, + const aarch64_opnd_info *info, aarch64_insn *code, + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) +{ + unsigned int base = 1 << get_operand_field_width (self, 0); + insert_field (self->fields[0], code, base - info->imm.value, 0); + return true; +} + /* Miscellaneous encoding functions. */ /* Encode size[0], i.e. bit 22, for @@ -1980,6 +1993,7 @@ aarch64_encode_variant_using_iclass (struct aarch64_inst *inst) 0, 2, FLD_SVE_M_14, FLD_size); break; + case sme_shift: case sve_index: case sve_shift_pred: case sve_shift_unpred: diff --git a/opcodes/aarch64-asm.h b/opcodes/aarch64-asm.h index 4cc48dfdcb6..0028e8bbaed 100644 --- a/opcodes/aarch64-asm.h +++ b/opcodes/aarch64-asm.h @@ -111,6 +111,7 @@ AARCH64_DECL_OPD_INSERTER (ins_imm_rotate1); AARCH64_DECL_OPD_INSERTER (ins_imm_rotate2); AARCH64_DECL_OPD_INSERTER (ins_x0_to_x30); AARCH64_DECL_OPD_INSERTER (ins_simple_index); +AARCH64_DECL_OPD_INSERTER (ins_plain_shrimm); #undef AARCH64_DECL_OPD_INSERTER diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c index 55a01e6e593..d82c37498e7 100644 --- a/opcodes/aarch64-dis-2.c +++ b/opcodes/aarch64-dis-2.c @@ -188,7 +188,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000x10x100xxxxxxxxxxxxxxxxx zero. */ - return 2874; + return 2883; } } } @@ -856,7 +856,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx000xxxxxxxxxxxx0 st1b. */ - return 2705; + return 2711; } else { @@ -864,7 +864,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx100xxxxxxxxxxxx0 st1b. */ - return 2706; + return 2712; } } else @@ -875,7 +875,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx010xxxxxxxxxxxx0 st1w. */ - return 2729; + return 2735; } else { @@ -883,7 +883,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx110xxxxxxxxxxxx0 st1w. */ - return 2730; + return 2736; } } } @@ -897,7 +897,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx001xxxxxxxxxxxx0 st1h. */ - return 2721; + return 2727; } else { @@ -905,7 +905,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx101xxxxxxxxxxxx0 st1h. */ - return 2722; + return 2728; } } else @@ -916,7 +916,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx011xxxxxxxxxxxx0 st1d. */ - return 2713; + return 2719; } else { @@ -924,7 +924,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx111xxxxxxxxxxxx0 st1d. */ - return 2714; + return 2720; } } } @@ -941,7 +941,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx000xxxxxxxxxxxx1 stnt1b. */ - return 2737; + return 2743; } else { @@ -949,7 +949,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx100xxxxxxxxxxxx1 stnt1b. */ - return 2738; + return 2744; } } else @@ -960,7 +960,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx010xxxxxxxxxxxx1 stnt1w. */ - return 2761; + return 2767; } else { @@ -968,7 +968,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx110xxxxxxxxxxxx1 stnt1w. */ - return 2762; + return 2768; } } } @@ -982,7 +982,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx001xxxxxxxxxxxx1 stnt1h. */ - return 2753; + return 2759; } else { @@ -990,7 +990,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx101xxxxxxxxxxxx1 stnt1h. */ - return 2754; + return 2760; } } else @@ -1001,7 +1001,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx011xxxxxxxxxxxx1 stnt1d. */ - return 2745; + return 2751; } else { @@ -1009,7 +1009,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx111xxxxxxxxxxxx1 stnt1d. */ - return 2746; + return 2752; } } } @@ -1073,7 +1073,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx000xxxxxxxxxxxx0 st1b. */ - return 2701; + return 2707; } else { @@ -1081,7 +1081,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx100xxxxxxxxxxxx0 st1b. */ - return 2702; + return 2708; } } else @@ -1092,7 +1092,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx010xxxxxxxxxxxx0 st1w. */ - return 2725; + return 2731; } else { @@ -1100,7 +1100,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx110xxxxxxxxxxxx0 st1w. */ - return 2726; + return 2732; } } } @@ -1114,7 +1114,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx001xxxxxxxxxxxx0 st1h. */ - return 2717; + return 2723; } else { @@ -1122,7 +1122,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx101xxxxxxxxxxxx0 st1h. */ - return 2718; + return 2724; } } else @@ -1133,7 +1133,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx011xxxxxxxxxxxx0 st1d. */ - return 2709; + return 2715; } else { @@ -1141,7 +1141,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx111xxxxxxxxxxxx0 st1d. */ - return 2710; + return 2716; } } } @@ -1158,7 +1158,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx000xxxxxxxxxxxx1 stnt1b. */ - return 2733; + return 2739; } else { @@ -1166,7 +1166,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx100xxxxxxxxxxxx1 stnt1b. */ - return 2734; + return 2740; } } else @@ -1177,7 +1177,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx010xxxxxxxxxxxx1 stnt1w. */ - return 2757; + return 2763; } else { @@ -1185,7 +1185,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx110xxxxxxxxxxxx1 stnt1w. */ - return 2758; + return 2764; } } } @@ -1199,7 +1199,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx001xxxxxxxxxxxx1 stnt1h. */ - return 2749; + return 2755; } else { @@ -1207,7 +1207,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx101xxxxxxxxxxxx1 stnt1h. */ - return 2750; + return 2756; } } else @@ -1218,7 +1218,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx011xxxxxxxxxxxx1 stnt1d. */ - return 2741; + return 2747; } else { @@ -1226,7 +1226,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx111xxxxxxxxxxxx1 stnt1d. */ - return 2742; + return 2748; } } } @@ -1326,7 +1326,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000010000xxxxxxxxxxxxxxx001xx usmlall. */ - return 2855; + return 2864; } } else @@ -1358,7 +1358,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000010001xxxx0xxxxxxxxx100xxx usmlall. */ - return 2856; + return 2865; } else { @@ -1366,7 +1366,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000010001xxxx1xxxxxxxxx100xxx usmlall. */ - return 2857; + return 2866; } } } @@ -1381,7 +1381,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000010000xxxxxxxxxxxxxxx100xx umlall. */ - return 2816; + return 2822; } else { @@ -1389,7 +1389,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000010000xxxxxxxxxxxxxxx101xx sumlall. */ - return 2776; + return 2782; } } else @@ -1402,7 +1402,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000010001xxxx0xxxxxxxxx010xxx umlall. */ - return 2817; + return 2823; } else { @@ -1410,7 +1410,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000010001xxxx1xxxxxxxxx010xxx umlall. */ - return 2818; + return 2824; } } else @@ -1421,7 +1421,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000010001xxxx0xxxxxxxxx110xxx sumlall. */ - return 2777; + return 2783; } else { @@ -1429,7 +1429,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000010001xxxx1xxxxxxxxx110xxx sumlall. */ - return 2778; + return 2784; } } } @@ -1475,7 +1475,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000010000xxxxxxxxxxxxxxx11xxx umlsll. */ - return 2832; + return 2838; } else { @@ -1485,7 +1485,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000010001xxxx0xxxxxxxxxx11xxx umlsll. */ - return 2833; + return 2839; } else { @@ -1493,7 +1493,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000010001xxxx1xxxxxxxxxx11xxx umlsll. */ - return 2834; + return 2840; } } } @@ -1721,7 +1721,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011000xxxxxxx0xxxxxxx00xxx smlall. */ - return 2877; + return 2886; } else { @@ -1731,7 +1731,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011001xxxx0xx0xxxxxxx00xxx smlall. */ - return 2878; + return 2887; } else { @@ -1739,7 +1739,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011001xxxx1xx0xxxxxxx00xxx smlall. */ - return 2879; + return 2888; } } } @@ -1806,7 +1806,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011000xxxxxxx0xxxxxxx10xxx umlall. */ - return 2886; + return 2895; } else { @@ -1816,7 +1816,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011001xxxx0xx0xxxxxxx10xxx umlall. */ - return 2887; + return 2896; } else { @@ -1824,7 +1824,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011001xxxx1xx0xxxxxxx10xxx umlall. */ - return 2888; + return 2897; } } } @@ -1884,7 +1884,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000011000xxxxxxx0xxxxxxx01xxx smlsll. */ - return 2880; + return 2889; } else { @@ -1894,7 +1894,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000011001xxxx0xx0xxxxxxx01xxx smlsll. */ - return 2881; + return 2890; } else { @@ -1902,7 +1902,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000011001xxxx1xx0xxxxxxx01xxx smlsll. */ - return 2882; + return 2891; } } } @@ -1943,7 +1943,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001100xxxxxxxxxxxxxxxx01xxx umopa. */ - return 2840; + return 2846; } } else @@ -1958,7 +1958,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000011000xxxxxxx0xxxxxxx11xxx umlsll. */ - return 2889; + return 2898; } else { @@ -1968,7 +1968,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000011001xxxx0xx0xxxxxxx11xxx umlsll. */ - return 2890; + return 2899; } else { @@ -1976,7 +1976,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000011001xxxx1xx0xxxxxxx11xxx umlsll. */ - return 2891; + return 2900; } } } @@ -2017,7 +2017,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001100xxxxxxxxxxxxxxxx11xxx umops. */ - return 2841; + return 2847; } } } @@ -2103,7 +2103,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000010101xxxx0xx0xxxxxx100xxx svdot. */ - return 2782; + return 2788; } else { @@ -2133,7 +2133,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000010101xxxx0xx1xxxxxx010xxx udot. */ - return 2788; + return 2794; } } else @@ -2144,7 +2144,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000010101xxxx0xx0xxxxxx110xxx uvdot. */ - return 2864; + return 2873; } else { @@ -2152,7 +2152,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000010101xxxx0xx1xxxxxx110xxx udot. */ - return 2794; + return 2800; } } } @@ -2232,7 +2232,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000010101xxxx1xx0xxxxxx100xxx svdot. */ - return 2783; + return 2789; } else { @@ -2262,7 +2262,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000010101xxxx1xx1xxxxxx010xxx udot. */ - return 2789; + return 2795; } } else @@ -2273,7 +2273,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000010101xxxx1xx0xxxxxx110xxx uvdot. */ - return 2865; + return 2874; } else { @@ -2281,7 +2281,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000010101xxxx1xx1xxxxxx110xxx udot. */ - return 2795; + return 2801; } } } @@ -2362,7 +2362,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000010101xxxx0xxxxxxxxx101xxx usdot. */ - return 2849; + return 2858; } } else @@ -2392,7 +2392,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000010101xxxx0xxxxxxxxx111xxx sudot. */ - return 2772; + return 2778; } } } @@ -2460,7 +2460,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000010101xxxx1xx0xxxxxx101xxx usvdot. */ - return 2863; + return 2872; } else { @@ -2468,7 +2468,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000010101xxxx1xx1xxxxxx101xxx usdot. */ - return 2850; + return 2859; } } } @@ -2490,7 +2490,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000010101xxxx1xx0xxxxxx111xxx suvdot. */ - return 2781; + return 2787; } else { @@ -2498,7 +2498,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000010101xxxx1xx1xxxxxx111xxx sudot. */ - return 2773; + return 2779; } } } @@ -2522,7 +2522,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx000001110xxxxx0xx0xxxxxxx00xxx fmla. */ - return 2893; + return 2902; } else { @@ -2530,7 +2530,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx000001110xxxxx1xx0xxxxxxx00xxx fmla. */ - return 2894; + return 2903; } } else @@ -2576,7 +2576,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx000001110xxxxx0xx00xxxxxx01xxx sdot. */ - return 2875; + return 2884; } else { @@ -2584,7 +2584,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx000001110xxxxx1xx00xxxxxx01xxx sdot. */ - return 2876; + return 2885; } } else @@ -2593,7 +2593,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx000001110xxxxxxxx01xxxxxx01xxx svdot. */ - return 2883; + return 2892; } } else @@ -2662,7 +2662,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx000001110xxxxx0xx0xxxxxxx10xxx fmls. */ - return 2895; + return 2904; } else { @@ -2670,7 +2670,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx000001110xxxxx1xx0xxxxxxx10xxx fmls. */ - return 2896; + return 2905; } } else @@ -2681,7 +2681,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000011100xxxxxxx1xxxxxxx10xxx umlal. */ - return 2808; + return 2814; } else { @@ -2691,7 +2691,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000011101xxxx0xx1xxxxxxx10xxx umlal. */ - return 2809; + return 2815; } else { @@ -2699,7 +2699,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000011101xxxx1xx1xxxxxxx10xxx umlal. */ - return 2810; + return 2816; } } } @@ -2725,7 +2725,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001110xxxxx0xx00xxxxxx11xxx udot. */ - return 2884; + return 2893; } else { @@ -2733,7 +2733,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001110xxxxx1xx00xxxxxx11xxx udot. */ - return 2885; + return 2894; } } else @@ -2742,7 +2742,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001110xxxxxxxx01xxxxxx11xxx uvdot. */ - return 2892; + return 2901; } } else @@ -2753,7 +2753,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000011100xxxxxxx1xxxxxxx11xxx umlsl. */ - return 2824; + return 2830; } else { @@ -2763,7 +2763,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000011101xxxx0xx1xxxxxxx11xxx umlsl. */ - return 2825; + return 2831; } else { @@ -2771,7 +2771,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000011101xxxx1xx1xxxxxxx11xxx umlsl. */ - return 2826; + return 2832; } } } @@ -2868,7 +2868,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000010x10xxxx0xx000xxxxx001xx usmlall. */ - return 2859; + return 2868; } else { @@ -2876,7 +2876,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000010x11xxxx0xx000xxxxx001xx usmlall. */ - return 2860; + return 2869; } } else @@ -2887,7 +2887,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011x1xxxx00xx000xxxxx001xx usmlall. */ - return 2861; + return 2870; } else { @@ -2895,7 +2895,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011x1xxxx10xx000xxxxx001xx usmlall. */ - return 2862; + return 2871; } } } @@ -3092,7 +3092,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx0xx001xxxxx001xx usmlall. */ - return 2858; + return 2867; } } else @@ -3198,7 +3198,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000010x10xxxx0xx000xxxxx100xx umlall. */ - return 2820; + return 2826; } else { @@ -3206,7 +3206,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000010x11xxxx0xx000xxxxx100xx umlall. */ - return 2821; + return 2827; } } else @@ -3217,7 +3217,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011x1xxxx00xx000xxxxx100xx umlall. */ - return 2822; + return 2828; } else { @@ -3225,7 +3225,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011x1xxxx10xx000xxxxx100xx umlall. */ - return 2823; + return 2829; } } } @@ -3237,7 +3237,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx10xxxx0xx000xxxxx101xx sumlall. */ - return 2779; + return 2785; } else { @@ -3245,7 +3245,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx11xxxx0xx000xxxxx101xx sumlall. */ - return 2780; + return 2786; } } } @@ -3346,7 +3346,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000010110xxxx0xx010xxxxx10xxx umlal. */ - return 2812; + return 2818; } else { @@ -3354,7 +3354,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000010111xxxx0xx010xxxxx10xxx umlal. */ - return 2813; + return 2819; } } else @@ -3365,7 +3365,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001111xxxx00xx010xxxxx10xxx umlal. */ - return 2814; + return 2820; } else { @@ -3373,7 +3373,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001111xxxx10xx010xxxxx10xxx umlal. */ - return 2815; + return 2821; } } } @@ -3431,7 +3431,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx0xx001xxxxx10xxx umlall. */ - return 2819; + return 2825; } else { @@ -3443,7 +3443,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000010x10xxxx0xx101xxxxx10xxx udot. */ - return 2796; + return 2802; } else { @@ -3451,7 +3451,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000010x11xxxx0xx101xxxxx10xxx udot. */ - return 2797; + return 2803; } } else @@ -3462,7 +3462,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011x1xxxx00xx101xxxxx10xxx udot. */ - return 2798; + return 2804; } else { @@ -3470,7 +3470,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011x1xxxx10xx101xxxxx10xxx udot. */ - return 2799; + return 2805; } } } @@ -3493,7 +3493,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001x11xxxxx0xx011xxxxx10xxx umlal. */ - return 2811; + return 2817; } } else @@ -3720,7 +3720,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000010010xxxx0xx101xxxxx01xxx usdot. */ - return 2851; + return 2860; } else { @@ -3728,7 +3728,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000010011xxxx0xx101xxxxx01xxx usdot. */ - return 2852; + return 2861; } } else @@ -3739,7 +3739,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001101xxxx00xx101xxxxx01xxx usdot. */ - return 2853; + return 2862; } else { @@ -3747,7 +3747,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001101xxxx10xx101xxxxx01xxx usdot. */ - return 2854; + return 2863; } } } @@ -3851,7 +3851,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000010x10xxxx0xxx00xxxxx11xxx umlsll. */ - return 2836; + return 2842; } else { @@ -3859,7 +3859,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000010x11xxxx0xxx00xxxxx11xxx umlsll. */ - return 2837; + return 2843; } } else @@ -3870,7 +3870,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011x1xxxx00xxx00xxxxx11xxx umlsll. */ - return 2838; + return 2844; } else { @@ -3878,7 +3878,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011x1xxxx10xxx00xxxxx11xxx umlsll. */ - return 2839; + return 2845; } } } @@ -3937,7 +3937,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000010110xxxx0xx010xxxxx11xxx umlsl. */ - return 2828; + return 2834; } else { @@ -3945,7 +3945,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000010111xxxx0xx010xxxxx11xxx umlsl. */ - return 2829; + return 2835; } } else @@ -3956,7 +3956,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001111xxxx00xx010xxxxx11xxx umlsl. */ - return 2830; + return 2836; } else { @@ -3964,7 +3964,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001111xxxx10xx010xxxxx11xxx umlsl. */ - return 2831; + return 2837; } } } @@ -3979,7 +3979,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000010x10xxxx0xx110xxxxx11xxx sub. */ - return 2768; + return 2774; } else { @@ -3987,7 +3987,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000010x11xxxx0xx110xxxxx11xxx sub. */ - return 2769; + return 2775; } } else @@ -3998,7 +3998,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011x1xxxx00xx110xxxxx11xxx sub. */ - return 2770; + return 2776; } else { @@ -4006,7 +4006,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011x1xxxx10xx110xxxxx11xxx sub. */ - return 2771; + return 2777; } } } @@ -4022,7 +4022,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx0xx001xxxxx11xxx umlsll. */ - return 2835; + return 2841; } else { @@ -4034,7 +4034,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001x010xxxx0xx101xxxxx11xxx sudot. */ - return 2774; + return 2780; } else { @@ -4042,7 +4042,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001x011xxxx0xx101xxxxx11xxx sudot. */ - return 2775; + return 2781; } } else @@ -4055,7 +4055,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000010110xxxx0xx101xxxxx11xxx udot. */ - return 2790; + return 2796; } else { @@ -4063,7 +4063,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000010111xxxx0xx101xxxxx11xxx udot. */ - return 2791; + return 2797; } } else @@ -4074,7 +4074,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001111xxxx00xx101xxxxx11xxx udot. */ - return 2792; + return 2798; } else { @@ -4082,7 +4082,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001111xxxx10xx101xxxxx11xxx udot. */ - return 2793; + return 2799; } } } @@ -4106,7 +4106,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001x11xxxxx0xx011xxxxx11xxx umlsl. */ - return 2827; + return 2833; } } else @@ -4117,7 +4117,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxx00xx111xxxxx11xxx sub. */ - return 2766; + return 2772; } else { @@ -4125,7 +4125,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxx10xx111xxxxx11xxx sub. */ - return 2767; + return 2773; } } } @@ -4137,88 +4137,187 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 13) & 0x1) == 0) { - if (((word >> 0) & 0x1) == 0) + if (((word >> 14) & 0x1) == 0) { - if (((word >> 14) & 0x1) == 0) + if (((word >> 16) & 0x1) == 0) { - if (((word >> 16) & 0x1) == 0) + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xxxx0100xxxxxxxxxxxxx + sel. */ + return 2643; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xxxx1100xxxxxxxxxxxxx + sel. */ + return 2644; + } + } + else + { + if (((word >> 10) & 0x1) == 0) + { + if (((word >> 11) & 0x1) == 0) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x1000001xx1xxxx0100xxxxxxxxxxxx0 - sel. */ - return 2643; + x1000001xx1xxxxx110x00xxxxxxxxxx + fclamp. */ + return 2466; } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx1xxxx1100xxxxxxxxxxxx0 - sel. */ - return 2644; + if (((word >> 12) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xxxxx110010xxxxxxxxxx + fclamp. */ + return 2467; + } + else + { + if (((word >> 5) & 0x1) == 0) + { + if (((word >> 6) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xxxxx110110xxx00xxxxx + sqrshr. */ + return 2698; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xxxxx110110xxx10xxxxx + sqrshru. */ + return 2701; + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xxxxx110110xxxx1xxxxx + uqrshr. */ + return 2852; + } + } } } else { - if (((word >> 10) & 0x1) == 0) + if (((word >> 11) & 0x1) == 0) { - if (((word >> 11) & 0x1) == 0) + if (((word >> 12) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx1xxxxx110x00xxxxxxxxx0 - fclamp. */ - return 2466; + if (((word >> 0) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xxxxx110001xxxxxxxxx0 + sclamp. */ + return 2627; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xxxxx110001xxxxxxxxx1 + uclamp. */ + return 2790; + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx1xxxxx110x10xxxxxxxxx0 - fclamp. */ - return 2467; + if (((word >> 5) & 0x1) == 0) + { + if (((word >> 20) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx10xxxx110101xxxx0xxxxx + sqrshr. */ + return 2697; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx11xxxx110101xxxx0xxxxx + sqrshru. */ + return 2700; + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xxxxx110101xxxx1xxxxx + uqrshr. */ + return 2851; + } } } else { - if (((word >> 11) & 0x1) == 0) + if (((word >> 12) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx1xxxxx110x01xxxxxxxxx0 - sclamp. */ - return 2627; + if (((word >> 0) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xxxxx110011xxxxxxxxx0 + sclamp. */ + return 2628; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xxxxx110011xxxxxxxxx1 + uclamp. */ + return 2791; + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx1xxxxx110x11xxxxxxxxx0 - sclamp. */ - return 2628; + if (((word >> 5) & 0x1) == 0) + { + if (((word >> 6) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xxxxx110111xxx00xxxxx + sqrshrn. */ + return 2699; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xxxxx110111xxx10xxxxx + sqrshrun. */ + return 2702; + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xxxxx110111xxxx1xxxxx + uqrshrn. */ + return 2853; + } } } } } - else - { - if (((word >> 11) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx1xxxxx1x0x0xxxxxxxxxx1 - uclamp. */ - return 2784; - } - else - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx1xxxxx1x0x1xxxxxxxxxx1 - uclamp. */ - return 2785; - } - } } else { @@ -4270,7 +4369,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx101000x0xx0xxxx1 umax. */ - return 2800; + return 2806; } else { @@ -4529,7 +4628,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1x1100x0xx0xxxx1 umax. */ - return 2802; + return 2808; } else { @@ -4606,7 +4705,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1x1010x0xx0xxxx1 umax. */ - return 2801; + return 2807; } else { @@ -4614,7 +4713,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1x1110x0xx0xxxx1 umax. */ - return 2803; + return 2809; } } else @@ -4707,7 +4806,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx10100x10xx1xxxx0 srshl. */ - return 2697; + return 2703; } } else @@ -4729,7 +4828,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx10100x00xx1xxxx1 umin. */ - return 2804; + return 2810; } else { @@ -4737,7 +4836,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx10100x10xx1xxxx1 urshl. */ - return 2845; + return 2854; } } else @@ -4781,7 +4880,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx10xx1011100xxxxx1xxxxx ucvtf. */ - return 2786; + return 2792; } else { @@ -4789,7 +4888,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx11xx1011100xxxxx1xxxxx ucvtf. */ - return 2787; + return 2793; } } } @@ -4822,7 +4921,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx10xx1111100xxxxx1xxxxx uqcvt. */ - return 2842; + return 2848; } else { @@ -4832,7 +4931,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx11xx1111100xxxx01xxxxx uqcvt. */ - return 2843; + return 2849; } else { @@ -4840,7 +4939,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx11xx1111100xxxx11xxxxx uqcvtn. */ - return 2844; + return 2850; } } } @@ -4867,7 +4966,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1x110x10xx1xxxx0 srshl. */ - return 2699; + return 2705; } } else @@ -4889,7 +4988,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1x110x00xx1xxxx1 umin. */ - return 2806; + return 2812; } else { @@ -4897,7 +4996,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1x110x10xx1xxxx1 urshl. */ - return 2847; + return 2856; } } else @@ -4944,7 +5043,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1x101x10xx1xxxx0 srshl. */ - return 2698; + return 2704; } else { @@ -4952,7 +5051,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1x111x10xx1xxxx0 srshl. */ - return 2700; + return 2706; } } } @@ -4988,7 +5087,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1x101x00xx1xxxx1 umin. */ - return 2805; + return 2811; } else { @@ -4996,7 +5095,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1x111x00xx1xxxx1 umin. */ - return 2807; + return 2813; } } else @@ -5007,7 +5106,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1x101x10xx1xxxx1 urshl. */ - return 2846; + return 2855; } else { @@ -5015,7 +5114,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx1x111x10xx1xxxx1 urshl. */ - return 2848; + return 2857; } } } @@ -5065,7 +5164,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx000xxxxxxxxx0xxx st1b. */ - return 2707; + return 2713; } else { @@ -5073,7 +5172,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx010xxxxxxxxx0xxx st1w. */ - return 2731; + return 2737; } } else @@ -5084,7 +5183,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx001xxxxxxxxx0xxx st1h. */ - return 2723; + return 2729; } else { @@ -5092,7 +5191,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx011xxxxxxxxx0xxx st1d. */ - return 2715; + return 2721; } } } @@ -5106,7 +5205,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx000xxxxxxxxx1xxx stnt1b. */ - return 2739; + return 2745; } else { @@ -5114,7 +5213,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx010xxxxxxxxx1xxx stnt1w. */ - return 2763; + return 2769; } } else @@ -5125,7 +5224,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx001xxxxxxxxx1xxx stnt1h. */ - return 2755; + return 2761; } else { @@ -5133,7 +5232,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx011xxxxxxxxx1xxx stnt1d. */ - return 2747; + return 2753; } } } @@ -5161,7 +5260,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx100xxxxxxxxx0xxx st1b. */ - return 2708; + return 2714; } else { @@ -5169,7 +5268,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1100001001xxxxx100xxxxxxxxx0xxx str. */ - return 2765; + return 2771; } } else @@ -5178,7 +5277,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001001xxxxx110xxxxxxxxx0xxx st1w. */ - return 2732; + return 2738; } } else @@ -5189,7 +5288,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001001xxxxx101xxxxxxxxx0xxx st1h. */ - return 2724; + return 2730; } else { @@ -5197,7 +5296,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001001xxxxx111xxxxxxxxx0xxx st1d. */ - return 2716; + return 2722; } } } @@ -5211,7 +5310,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001001xxxxx100xxxxxxxxx1xxx stnt1b. */ - return 2740; + return 2746; } else { @@ -5219,7 +5318,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001001xxxxx110xxxxxxxxx1xxx stnt1w. */ - return 2764; + return 2770; } } else @@ -5230,7 +5329,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001001xxxxx101xxxxxxxxx1xxx stnt1h. */ - return 2756; + return 2762; } else { @@ -5238,7 +5337,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001001xxxxx111xxxxxxxxx1xxx stnt1d. */ - return 2748; + return 2754; } } } @@ -5280,7 +5379,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx000xxxxxxxxx0xxx st1b. */ - return 2703; + return 2709; } else { @@ -5288,7 +5387,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx100xxxxxxxxx0xxx st1b. */ - return 2704; + return 2710; } } else @@ -5299,7 +5398,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx010xxxxxxxxx0xxx st1w. */ - return 2727; + return 2733; } else { @@ -5307,7 +5406,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx110xxxxxxxxx0xxx st1w. */ - return 2728; + return 2734; } } } @@ -5321,7 +5420,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx001xxxxxxxxx0xxx st1h. */ - return 2719; + return 2725; } else { @@ -5329,7 +5428,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx101xxxxxxxxx0xxx st1h. */ - return 2720; + return 2726; } } else @@ -5340,7 +5439,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx011xxxxxxxxx0xxx st1d. */ - return 2711; + return 2717; } else { @@ -5348,7 +5447,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx111xxxxxxxxx0xxx st1d. */ - return 2712; + return 2718; } } } @@ -5365,7 +5464,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx000xxxxxxxxx1xxx stnt1b. */ - return 2735; + return 2741; } else { @@ -5373,7 +5472,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx100xxxxxxxxx1xxx stnt1b. */ - return 2736; + return 2742; } } else @@ -5384,7 +5483,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx010xxxxxxxxx1xxx stnt1w. */ - return 2759; + return 2765; } else { @@ -5392,7 +5491,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx110xxxxxxxxx1xxx stnt1w. */ - return 2760; + return 2766; } } } @@ -5406,7 +5505,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx001xxxxxxxxx1xxx stnt1h. */ - return 2751; + return 2757; } else { @@ -5414,7 +5513,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx101xxxxxxxxx1xxx stnt1h. */ - return 2752; + return 2758; } } else @@ -5425,7 +5524,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx011xxxxxxxxx1xxx stnt1d. */ - return 2743; + return 2749; } else { @@ -5433,7 +5532,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx111xxxxxxxxx1xxx stnt1d. */ - return 2744; + return 2750; } } } @@ -7835,7 +7934,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 00011001000xxxxxxxxx00xxxxxxxxxx stlurb. */ - return 2937; + return 2946; } else { @@ -7843,7 +7942,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 10011001000xxxxxxxxx00xxxxxxxxxx stlur. */ - return 2945; + return 2954; } } else @@ -7854,7 +7953,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 01011001000xxxxxxxxx00xxxxxxxxxx stlurh. */ - return 2941; + return 2950; } else { @@ -7862,7 +7961,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 11011001000xxxxxxxxx00xxxxxxxxxx stlur. */ - return 2948; + return 2957; } } } @@ -7900,7 +7999,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0000x1xxxxxxxxxx cpyfp. */ - return 2997; + return 3006; } else { @@ -7908,7 +8007,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1000x1xxxxxxxxxx cpyfprn. */ - return 3003; + return 3012; } } else @@ -7919,7 +8018,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0100x1xxxxxxxxxx cpyfpwn. */ - return 3000; + return 3009; } else { @@ -7927,7 +8026,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1100x1xxxxxxxxxx cpyfpn. */ - return 3006; + return 3015; } } } @@ -7941,7 +8040,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0010x1xxxxxxxxxx cpyfprt. */ - return 3021; + return 3030; } else { @@ -7949,7 +8048,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1010x1xxxxxxxxxx cpyfprtrn. */ - return 3027; + return 3036; } } else @@ -7960,7 +8059,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0110x1xxxxxxxxxx cpyfprtwn. */ - return 3024; + return 3033; } else { @@ -7968,7 +8067,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1110x1xxxxxxxxxx cpyfprtn. */ - return 3030; + return 3039; } } } @@ -7985,7 +8084,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0001x1xxxxxxxxxx cpyfpwt. */ - return 3009; + return 3018; } else { @@ -7993,7 +8092,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1001x1xxxxxxxxxx cpyfpwtrn. */ - return 3015; + return 3024; } } else @@ -8004,7 +8103,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0101x1xxxxxxxxxx cpyfpwtwn. */ - return 3012; + return 3021; } else { @@ -8012,7 +8111,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1101x1xxxxxxxxxx cpyfpwtn. */ - return 3018; + return 3027; } } } @@ -8026,7 +8125,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0011x1xxxxxxxxxx cpyfpt. */ - return 3033; + return 3042; } else { @@ -8034,7 +8133,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1011x1xxxxxxxxxx cpyfptrn. */ - return 3039; + return 3048; } } else @@ -8045,7 +8144,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0111x1xxxxxxxxxx cpyfptwn. */ - return 3036; + return 3045; } else { @@ -8053,7 +8152,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1111x1xxxxxxxxxx cpyfptn. */ - return 3042; + return 3051; } } } @@ -8118,7 +8217,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 00011001010xxxxxxxxx00xxxxxxxxxx ldapurb. */ - return 2938; + return 2947; } else { @@ -8126,7 +8225,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 10011001010xxxxxxxxx00xxxxxxxxxx ldapur. */ - return 2946; + return 2955; } } else @@ -8137,7 +8236,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 01011001010xxxxxxxxx00xxxxxxxxxx ldapurh. */ - return 2942; + return 2951; } else { @@ -8145,7 +8244,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 11011001010xxxxxxxxx00xxxxxxxxxx ldapur. */ - return 2949; + return 2958; } } } @@ -8183,7 +8282,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0000x1xxxxxxxxxx cpyfm. */ - return 2998; + return 3007; } else { @@ -8191,7 +8290,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1000x1xxxxxxxxxx cpyfmrn. */ - return 3004; + return 3013; } } else @@ -8202,7 +8301,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0100x1xxxxxxxxxx cpyfmwn. */ - return 3001; + return 3010; } else { @@ -8210,7 +8309,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1100x1xxxxxxxxxx cpyfmn. */ - return 3007; + return 3016; } } } @@ -8224,7 +8323,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0010x1xxxxxxxxxx cpyfmrt. */ - return 3022; + return 3031; } else { @@ -8232,7 +8331,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1010x1xxxxxxxxxx cpyfmrtrn. */ - return 3028; + return 3037; } } else @@ -8243,7 +8342,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0110x1xxxxxxxxxx cpyfmrtwn. */ - return 3025; + return 3034; } else { @@ -8251,7 +8350,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1110x1xxxxxxxxxx cpyfmrtn. */ - return 3031; + return 3040; } } } @@ -8268,7 +8367,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0001x1xxxxxxxxxx cpyfmwt. */ - return 3010; + return 3019; } else { @@ -8276,7 +8375,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1001x1xxxxxxxxxx cpyfmwtrn. */ - return 3016; + return 3025; } } else @@ -8287,7 +8386,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0101x1xxxxxxxxxx cpyfmwtwn. */ - return 3013; + return 3022; } else { @@ -8295,7 +8394,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1101x1xxxxxxxxxx cpyfmwtn. */ - return 3019; + return 3028; } } } @@ -8309,7 +8408,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0011x1xxxxxxxxxx cpyfmt. */ - return 3034; + return 3043; } else { @@ -8317,7 +8416,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1011x1xxxxxxxxxx cpyfmtrn. */ - return 3040; + return 3049; } } else @@ -8328,7 +8427,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0111x1xxxxxxxxxx cpyfmtwn. */ - return 3037; + return 3046; } else { @@ -8336,7 +8435,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1111x1xxxxxxxxxx cpyfmtn. */ - return 3043; + return 3052; } } } @@ -8404,7 +8503,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 00011001100xxxxxxxxx00xxxxxxxxxx ldapursb. */ - return 2940; + return 2949; } else { @@ -8412,7 +8511,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 10011001100xxxxxxxxx00xxxxxxxxxx ldapursw. */ - return 2947; + return 2956; } } else @@ -8421,7 +8520,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1011001100xxxxxxxxx00xxxxxxxxxx ldapursh. */ - return 2944; + return 2953; } } else @@ -8432,7 +8531,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0011001110xxxxxxxxx00xxxxxxxxxx ldapursb. */ - return 2939; + return 2948; } else { @@ -8440,7 +8539,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1011001110xxxxxxxxx00xxxxxxxxxx ldapursh. */ - return 2943; + return 2952; } } } @@ -8502,7 +8601,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0000x1xxxxxxxxxx cpyfe. */ - return 2999; + return 3008; } else { @@ -8510,7 +8609,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0000x1xxxxxxxxxx setp. */ - return 3093; + return 3102; } } else @@ -8521,7 +8620,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx1000x1xxxxxxxxxx cpyfern. */ - return 3005; + return 3014; } else { @@ -8529,7 +8628,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx1000x1xxxxxxxxxx sete. */ - return 3095; + return 3104; } } } @@ -8543,7 +8642,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0100x1xxxxxxxxxx cpyfewn. */ - return 3002; + return 3011; } else { @@ -8551,7 +8650,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0100x1xxxxxxxxxx setm. */ - return 3094; + return 3103; } } else @@ -8560,7 +8659,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0110011x0xxxxx1100x1xxxxxxxxxx cpyfen. */ - return 3008; + return 3017; } } } @@ -8576,7 +8675,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0010x1xxxxxxxxxx cpyfert. */ - return 3023; + return 3032; } else { @@ -8584,7 +8683,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0010x1xxxxxxxxxx setpn. */ - return 3099; + return 3108; } } else @@ -8595,7 +8694,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx1010x1xxxxxxxxxx cpyfertrn. */ - return 3029; + return 3038; } else { @@ -8603,7 +8702,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx1010x1xxxxxxxxxx seten. */ - return 3101; + return 3110; } } } @@ -8617,7 +8716,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0110x1xxxxxxxxxx cpyfertwn. */ - return 3026; + return 3035; } else { @@ -8625,7 +8724,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0110x1xxxxxxxxxx setmn. */ - return 3100; + return 3109; } } else @@ -8634,7 +8733,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0110011x0xxxxx1110x1xxxxxxxxxx cpyfertn. */ - return 3032; + return 3041; } } } @@ -8653,7 +8752,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0001x1xxxxxxxxxx cpyfewt. */ - return 3011; + return 3020; } else { @@ -8661,7 +8760,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0001x1xxxxxxxxxx setpt. */ - return 3096; + return 3105; } } else @@ -8672,7 +8771,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx1001x1xxxxxxxxxx cpyfewtrn. */ - return 3017; + return 3026; } else { @@ -8680,7 +8779,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx1001x1xxxxxxxxxx setet. */ - return 3098; + return 3107; } } } @@ -8694,7 +8793,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0101x1xxxxxxxxxx cpyfewtwn. */ - return 3014; + return 3023; } else { @@ -8702,7 +8801,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0101x1xxxxxxxxxx setmt. */ - return 3097; + return 3106; } } else @@ -8711,7 +8810,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0110011x0xxxxx1101x1xxxxxxxxxx cpyfewtn. */ - return 3020; + return 3029; } } } @@ -8727,7 +8826,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0011x1xxxxxxxxxx cpyfet. */ - return 3035; + return 3044; } else { @@ -8735,7 +8834,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0011x1xxxxxxxxxx setptn. */ - return 3102; + return 3111; } } else @@ -8746,7 +8845,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx1011x1xxxxxxxxxx cpyfetrn. */ - return 3041; + return 3050; } else { @@ -8754,7 +8853,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx1011x1xxxxxxxxxx setetn. */ - return 3104; + return 3113; } } } @@ -8768,7 +8867,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0111x1xxxxxxxxxx cpyfetwn. */ - return 3038; + return 3047; } else { @@ -8776,7 +8875,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0111x1xxxxxxxxxx setmtn. */ - return 3103; + return 3112; } } else @@ -8785,7 +8884,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0110011x0xxxxx1111x1xxxxxxxxxx cpyfetn. */ - return 3044; + return 3053; } } } @@ -9158,7 +9257,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1x11010110xxxx0x01000xxxxxxxxxx abs. */ - return 3122; + return 3131; } else { @@ -9176,7 +9275,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010110xxxxxx11000xxxxxxxxxx smax. */ - return 3125; + return 3134; } } } @@ -9256,7 +9355,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010x00xxxxxx0xx10xxxxxxxxxx setf8. */ - return 2935; + return 2944; } else { @@ -9264,7 +9363,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010x00xxxxxx1xx10xxxxxxxxxx setf16. */ - return 2936; + return 2945; } } else @@ -9371,7 +9470,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010110xxxxxx11010xxxxxxxxxx smin. */ - return 3127; + return 3136; } } } @@ -9387,7 +9486,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010110xxxx0x00110xxxxxxxxxx ctz. */ - return 3124; + return 3133; } else { @@ -9432,7 +9531,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010000xxxxxxxxx01xxxxxxxxxx rmif. */ - return 2934; + return 2943; } else { @@ -9526,7 +9625,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010x10xxxxxx11001xxxxxxxxxx umax. */ - return 3126; + return 3135; } } } @@ -9656,7 +9755,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010xx0xxxxxx11011xxxxxxxxxx umin. */ - return 3128; + return 3137; } } } @@ -9672,7 +9771,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010xx0xxxx0x00111xxxxxxxxxx cnt. */ - return 3123; + return 3132; } else { @@ -10514,7 +10613,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x01x1xxxxx000110xxxxxxxxxx usdot. */ - return 2954; + return 2963; } } } @@ -10588,7 +10687,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x01x1xxxxx000111xxxxxxxxxx sudot. */ - return 2955; + return 2964; } } } @@ -13262,7 +13361,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x0xx0xxxxx011110xxxxxxxxxx usdot. */ - return 2953; + return 2962; } } } @@ -14966,7 +15065,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0100xxx10101xxxxxxxxxxxxx bfcvtnt. */ - return 2982; + return 2991; } } else @@ -15209,7 +15308,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x00x1xxxxxx00xxxxxxxxxxxxx ld1rob. */ - return 2958; + return 2967; } else { @@ -15217,7 +15316,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x01x1xxxxxx00xxxxxxxxxxxxx ld1roh. */ - return 2959; + return 2968; } } else @@ -15449,7 +15548,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0011xxxxx010xxxxxxxxxxxxx bfdot. */ - return 2979; + return 2988; } else { @@ -15470,7 +15569,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx010xx0xxxxxxxxxx bfmlalb. */ - return 2986; + return 2995; } else { @@ -15478,7 +15577,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx010xx1xxxxxxxxxx bfmlalt. */ - return 2985; + return 2994; } } else @@ -15533,7 +15632,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11001x0011xxxxx1x0xxxxxxxxxxxxx bfdot. */ - return 2978; + return 2987; } else { @@ -15545,7 +15644,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx1x0xx0xxxxxxxxxx bfmlalb. */ - return 2984; + return 2993; } else { @@ -15553,7 +15652,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx1x0xx1xxxxxxxxxx bfmlalt. */ - return 2983; + return 2992; } } else @@ -15604,7 +15703,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x00x1xxxxx001xxxxxxxxxxxxx ld1rob. */ - return 2962; + return 2971; } else { @@ -15612,7 +15711,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x01x1xxxxx001xxxxxxxxxxxxx ld1roh. */ - return 2963; + return 2972; } } else @@ -15971,7 +16070,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0101xxxxx111xxxxxxxxxxxxx fmmla. */ - return 2956; + return 2965; } else { @@ -16004,7 +16103,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0011xxxxx111xxxxxxxxxxxxx bfmmla. */ - return 2980; + return 2989; } else { @@ -16034,7 +16133,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx111xxxxxxxxxxxxx fmmla. */ - return 2957; + return 2966; } else { @@ -16163,7 +16262,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000x00xxxxxxxxxx zip1. */ - return 2966; + return 2975; } else { @@ -16173,7 +16272,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000010xxxxxxxxxx uzp1. */ - return 2968; + return 2977; } else { @@ -16181,7 +16280,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000110xxxxxxxxxx trn1. */ - return 2970; + return 2979; } } } @@ -16193,7 +16292,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000x01xxxxxxxxxx zip2. */ - return 2967; + return 2976; } else { @@ -16203,7 +16302,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000011xxxxxxxxxx uzp2. */ - return 2969; + return 2978; } else { @@ -16211,7 +16310,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000111xxxxxxxxxx trn2. */ - return 2971; + return 2980; } } } @@ -17270,7 +17369,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x1000xxxxx100110xxxxxxxxxx smmla. */ - return 2950; + return 2959; } else { @@ -17278,7 +17377,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x1100xxxxx100110xxxxxxxxxx usmmla. */ - return 2952; + return 2961; } } else @@ -17287,7 +17386,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x1x10xxxxx100110xxxxxxxxxx ummla. */ - return 2951; + return 2960; } } } @@ -18783,7 +18882,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x10x1xxxxx000xxxxxxxxxxxxx ld1row. */ - return 2960; + return 2969; } else { @@ -18791,7 +18890,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x11x1xxxxx000xxxxxxxxxxxxx ld1rod. */ - return 2961; + return 2970; } } } @@ -19165,7 +19264,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x10x1xxxxx001xxxxxxxxxxxxx ld1row. */ - return 2964; + return 2973; } else { @@ -19173,7 +19272,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x11x1xxxxx001xxxxxxxxxxxxx ld1rod. */ - return 2965; + return 2974; } } } @@ -19534,7 +19633,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x000xxxxx10xxx whilege. */ - return 2866; + return 2875; } else { @@ -19542,7 +19641,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x000xxxxx11xxx whilegt. */ - return 2867; + return 2876; } } else @@ -19586,7 +19685,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x010xxxxx10xxx whilehs. */ - return 2869; + return 2878; } else { @@ -19594,7 +19693,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x010xxxxx11xxx whilehi. */ - return 2868; + return 2877; } } else @@ -19641,7 +19740,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x001xxxxx10xxx whilelt. */ - return 2873; + return 2882; } else { @@ -19649,7 +19748,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x001xxxxx11xxx whilele. */ - return 2870; + return 2879; } } else @@ -19693,7 +19792,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x011xxxxx10xxx whilelo. */ - return 2871; + return 2880; } else { @@ -19701,7 +19800,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x011xxxxx11xxx whilels. */ - return 2872; + return 2881; } } else @@ -20827,7 +20926,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x110001x10101xxxxxxxxxxxxx bfcvt. */ - return 2981; + return 2990; } } else @@ -22188,7 +22287,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1010100xxxxxxxxxxxxxxxxxxx1xxxx bc.c. */ - return 3117; + return 3126; } else { @@ -22768,7 +22867,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0000xxxxxxxxxxxx cpyp. */ - return 3045; + return 3054; } else { @@ -22776,7 +22875,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0000xxxxxxxxxxxx cpye. */ - return 3047; + return 3056; } } else @@ -22787,7 +22886,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1000xxxxxxxxxxxx cpyprn. */ - return 3051; + return 3060; } else { @@ -22795,7 +22894,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1000xxxxxxxxxxxx cpyern. */ - return 3053; + return 3062; } } } @@ -22809,7 +22908,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0100xxxxxxxxxxxx cpypwn. */ - return 3048; + return 3057; } else { @@ -22817,7 +22916,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0100xxxxxxxxxxxx cpyewn. */ - return 3050; + return 3059; } } else @@ -22828,7 +22927,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1100xxxxxxxxxxxx cpypn. */ - return 3054; + return 3063; } else { @@ -22836,7 +22935,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1100xxxxxxxxxxxx cpyen. */ - return 3056; + return 3065; } } } @@ -22853,7 +22952,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0010xxxxxxxxxxxx cpyprt. */ - return 3069; + return 3078; } else { @@ -22861,7 +22960,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0010xxxxxxxxxxxx cpyert. */ - return 3071; + return 3080; } } else @@ -22872,7 +22971,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1010xxxxxxxxxxxx cpyprtrn. */ - return 3075; + return 3084; } else { @@ -22880,7 +22979,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1010xxxxxxxxxxxx cpyertrn. */ - return 3077; + return 3086; } } } @@ -22894,7 +22993,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0110xxxxxxxxxxxx cpyprtwn. */ - return 3072; + return 3081; } else { @@ -22902,7 +23001,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0110xxxxxxxxxxxx cpyertwn. */ - return 3074; + return 3083; } } else @@ -22913,7 +23012,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1110xxxxxxxxxxxx cpyprtn. */ - return 3078; + return 3087; } else { @@ -22921,7 +23020,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1110xxxxxxxxxxxx cpyertn. */ - return 3080; + return 3089; } } } @@ -22941,7 +23040,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0001xxxxxxxxxxxx cpypwt. */ - return 3057; + return 3066; } else { @@ -22949,7 +23048,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0001xxxxxxxxxxxx cpyewt. */ - return 3059; + return 3068; } } else @@ -22960,7 +23059,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1001xxxxxxxxxxxx cpypwtrn. */ - return 3063; + return 3072; } else { @@ -22968,7 +23067,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1001xxxxxxxxxxxx cpyewtrn. */ - return 3065; + return 3074; } } } @@ -22982,7 +23081,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0101xxxxxxxxxxxx cpypwtwn. */ - return 3060; + return 3069; } else { @@ -22990,7 +23089,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0101xxxxxxxxxxxx cpyewtwn. */ - return 3062; + return 3071; } } else @@ -23001,7 +23100,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1101xxxxxxxxxxxx cpypwtn. */ - return 3066; + return 3075; } else { @@ -23009,7 +23108,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1101xxxxxxxxxxxx cpyewtn. */ - return 3068; + return 3077; } } } @@ -23026,7 +23125,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0011xxxxxxxxxxxx cpypt. */ - return 3081; + return 3090; } else { @@ -23034,7 +23133,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0011xxxxxxxxxxxx cpyet. */ - return 3083; + return 3092; } } else @@ -23045,7 +23144,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1011xxxxxxxxxxxx cpyptrn. */ - return 3087; + return 3096; } else { @@ -23053,7 +23152,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1011xxxxxxxxxxxx cpyetrn. */ - return 3089; + return 3098; } } } @@ -23067,7 +23166,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0111xxxxxxxxxxxx cpyptwn. */ - return 3084; + return 3093; } else { @@ -23075,7 +23174,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0111xxxxxxxxxxxx cpyetwn. */ - return 3086; + return 3095; } } else @@ -23086,7 +23185,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1111xxxxxxxxxxxx cpyptn. */ - return 3090; + return 3099; } else { @@ -23094,7 +23193,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1111xxxxxxxxxxxx cpyetn. */ - return 3092; + return 3101; } } } @@ -23128,7 +23227,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0000xxxxxxxxxxxx cpym. */ - return 3046; + return 3055; } else { @@ -23136,7 +23235,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0000xxxxxxxxxxxx setgp. */ - return 3105; + return 3114; } } else @@ -23147,7 +23246,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx1000xxxxxxxxxxxx cpymrn. */ - return 3052; + return 3061; } else { @@ -23155,7 +23254,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx1000xxxxxxxxxxxx setge. */ - return 3107; + return 3116; } } } @@ -23169,7 +23268,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0100xxxxxxxxxxxx cpymwn. */ - return 3049; + return 3058; } else { @@ -23177,7 +23276,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0100xxxxxxxxxxxx setgm. */ - return 3106; + return 3115; } } else @@ -23186,7 +23285,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011101x1xxxxxx1100xxxxxxxxxxxx cpymn. */ - return 3055; + return 3064; } } } @@ -23202,7 +23301,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0010xxxxxxxxxxxx cpymrt. */ - return 3070; + return 3079; } else { @@ -23210,7 +23309,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0010xxxxxxxxxxxx setgpn. */ - return 3111; + return 3120; } } else @@ -23221,7 +23320,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx1010xxxxxxxxxxxx cpymrtrn. */ - return 3076; + return 3085; } else { @@ -23229,7 +23328,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx1010xxxxxxxxxxxx setgen. */ - return 3113; + return 3122; } } } @@ -23243,7 +23342,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0110xxxxxxxxxxxx cpymrtwn. */ - return 3073; + return 3082; } else { @@ -23251,7 +23350,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0110xxxxxxxxxxxx setgmn. */ - return 3112; + return 3121; } } else @@ -23260,7 +23359,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011101x1xxxxxx1110xxxxxxxxxxxx cpymrtn. */ - return 3079; + return 3088; } } } @@ -23279,7 +23378,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0001xxxxxxxxxxxx cpymwt. */ - return 3058; + return 3067; } else { @@ -23287,7 +23386,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0001xxxxxxxxxxxx setgpt. */ - return 3108; + return 3117; } } else @@ -23298,7 +23397,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx1001xxxxxxxxxxxx cpymwtrn. */ - return 3064; + return 3073; } else { @@ -23306,7 +23405,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx1001xxxxxxxxxxxx setget. */ - return 3110; + return 3119; } } } @@ -23320,7 +23419,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0101xxxxxxxxxxxx cpymwtwn. */ - return 3061; + return 3070; } else { @@ -23328,7 +23427,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0101xxxxxxxxxxxx setgmt. */ - return 3109; + return 3118; } } else @@ -23337,7 +23436,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011101x1xxxxxx1101xxxxxxxxxxxx cpymwtn. */ - return 3067; + return 3076; } } } @@ -23353,7 +23452,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0011xxxxxxxxxxxx cpymt. */ - return 3082; + return 3091; } else { @@ -23361,7 +23460,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0011xxxxxxxxxxxx setgptn. */ - return 3114; + return 3123; } } else @@ -23372,7 +23471,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx1011xxxxxxxxxxxx cpymtrn. */ - return 3088; + return 3097; } else { @@ -23380,7 +23479,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx1011xxxxxxxxxxxx setgetn. */ - return 3116; + return 3125; } } } @@ -23394,7 +23493,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0111xxxxxxxxxxxx cpymtwn. */ - return 3085; + return 3094; } else { @@ -23402,7 +23501,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0111xxxxxxxxxxxx setgmtn. */ - return 3115; + return 3124; } } else @@ -23411,7 +23510,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011101x1xxxxxx1111xxxxxxxxxxxx cpymtn. */ - return 3091; + return 3100; } } } @@ -23578,7 +23677,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110xx0xxxxx1x1001xxxxxxxxxx smmla. */ - return 2972; + return 2981; } } } @@ -23611,7 +23710,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110xx0xxxxx1x0101xxxxxxxxxx sdot. */ - return 2898; + return 2907; } } else @@ -23685,7 +23784,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110xx0xxxxx1x1011xxxxxxxxxx usmmla. */ - return 2974; + return 2983; } } } @@ -23718,7 +23817,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110xx0xxxxx1x0111xxxxxxxxxx usdot. */ - return 2975; + return 2984; } } else @@ -23765,7 +23864,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110000xxxxxxxxxxxxxxxxxxxxx eor3. */ - return 2905; + return 2914; } else { @@ -23773,7 +23872,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110100xxxxxxxxxxxxxxxxxxxxx xar. */ - return 2907; + return 2916; } } else @@ -23784,7 +23883,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110x10xxxxx0xxxxxxxxxxxxxxx sm3ss1. */ - return 2909; + return 2918; } else { @@ -23798,7 +23897,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110010xxxxx1xxx00xxxxxxxxxx sm3tt1a. */ - return 2910; + return 2919; } else { @@ -23806,7 +23905,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110110xxxxx1xxx00xxxxxxxxxx sha512su0. */ - return 2903; + return 2912; } } else @@ -23815,7 +23914,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110x10xxxxx1xxx10xxxxxxxxxx sm3tt2a. */ - return 2912; + return 2921; } } else @@ -23828,7 +23927,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110010xxxxx1xxx01xxxxxxxxxx sm3tt1b. */ - return 2911; + return 2920; } else { @@ -23836,7 +23935,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110110xxxxx1xxx01xxxxxxxxxx sm4e. */ - return 2916; + return 2925; } } else @@ -23845,7 +23944,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110x10xxxxx1xxx11xxxxxxxxxx sm3tt2b. */ - return 2913; + return 2922; } } } @@ -24026,7 +24125,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx101110xx0xxxxx100101xxxxxxxxxx udot. */ - return 2897; + return 2906; } } else @@ -24057,7 +24156,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx101110xx0xxxxx101x01xxxxxxxxxx ummla. */ - return 2973; + return 2982; } else { @@ -24076,7 +24175,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx101110xx0xxxxx1x1011xxxxxxxxxx bfmmla. */ - return 2989; + return 2998; } else { @@ -24086,7 +24185,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx1011100x0xxxxx1x1111xxxxxxxxxx bfdot. */ - return 2987; + return 2996; } else { @@ -24096,7 +24195,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x01011101x0xxxxx1x1111xxxxxxxxxx bfmlalb. */ - return 2994; + return 3003; } else { @@ -24104,7 +24203,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11011101x0xxxxx1x1111xxxxxxxxxx bfmlalt. */ - return 2993; + return 3002; } } } @@ -24688,7 +24787,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000011101x1xxxx1011010xxxxxxxxxx bfcvtn. */ - return 2990; + return 2999; } else { @@ -24696,7 +24795,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010011101x1xxxx1011010xxxxxxxxxx bfcvtn2. */ - return 2991; + return 3000; } } } @@ -25014,7 +25113,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110xx1xxxxx0xxxxxxxxxxxxxxx bcax. */ - return 2908; + return 2917; } } else @@ -25625,7 +25724,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 11001110xx1xxxxx100000xxxxxxxxxx sha512h. */ - return 2901; + return 2910; } } } @@ -25677,7 +25776,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 11001110xx1xxxxx110000xxxxxxxxxx sm3partw1. */ - return 2914; + return 2923; } } } @@ -25920,7 +26019,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110xx1xxxxx100010xxxxxxxxxx sha512su1. */ - return 2904; + return 2913; } } else @@ -25996,7 +26095,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x0011100x1xxxxx110010xxxxxxxxxx sm4ekey. */ - return 2917; + return 2926; } } else @@ -26822,7 +26921,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110xx1xxxxx100001xxxxxxxxxx sha512h2. */ - return 2902; + return 2911; } } else @@ -26854,7 +26953,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x0011100x1xxxxx110001xxxxxxxxxx sm3partw2. */ - return 2915; + return 2924; } } else @@ -27094,7 +27193,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110xx1xxxxx100011xxxxxxxxxx rax1. */ - return 2906; + return 2915; } } else @@ -27126,7 +27225,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x01011100x1xxxxx110011xxxxxxxxxx fmlal2. */ - return 2920; + return 2929; } else { @@ -27134,7 +27233,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11011100x1xxxxx110011xxxxxxxxxx fmlal2. */ - return 2924; + return 2933; } } } @@ -27156,7 +27255,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x01011101x1xxxxx110011xxxxxxxxxx fmlsl2. */ - return 2921; + return 2930; } else { @@ -27164,7 +27263,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11011101x1xxxxx110011xxxxxxxxxx fmlsl2. */ - return 2925; + return 2934; } } } @@ -27203,7 +27302,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x00011100x1xxxxx111011xxxxxxxxxx fmlal. */ - return 2918; + return 2927; } else { @@ -27211,7 +27310,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10011100x1xxxxx111011xxxxxxxxxx fmlal. */ - return 2922; + return 2931; } } else @@ -27233,7 +27332,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x00011101x1xxxxx111011xxxxxxxxxx fmlsl. */ - return 2919; + return 2928; } else { @@ -27241,7 +27340,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10011101x1xxxxx111011xxxxxxxxxx fmlsl. */ - return 2923; + return 2932; } } else @@ -29049,7 +29148,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0001111xxxxxxxx0000x0xxxxxxxxxx fmlal. */ - return 2926; + return 2935; } else { @@ -29057,7 +29156,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1001111xxxxxxxx0000x0xxxxxxxxxx fmlal. */ - return 2930; + return 2939; } } else @@ -29079,7 +29178,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0001111xxxxxxxx0100x0xxxxxxxxxx fmlsl. */ - return 2927; + return 2936; } else { @@ -29087,7 +29186,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1001111xxxxxxxx0100x0xxxxxxxxxx fmlsl. */ - return 2931; + return 2940; } } else @@ -29593,7 +29692,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0101111xxxxxxxx1000x0xxxxxxxxxx fmlal2. */ - return 2928; + return 2937; } else { @@ -29601,7 +29700,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1101111xxxxxxxx1000x0xxxxxxxxxx fmlal2. */ - return 2932; + return 2941; } } } @@ -29623,7 +29722,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0101111xxxxxxxx1100x0xxxxxxxxxx fmlsl2. */ - return 2929; + return 2938; } else { @@ -29631,7 +29730,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1101111xxxxxxxx1100x0xxxxxxxxxx fmlsl2. */ - return 2933; + return 2942; } } } @@ -29687,7 +29786,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx001111xxxxxxxx1110x0xxxxxxxxxx sdot. */ - return 2900; + return 2909; } else { @@ -29695,7 +29794,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx101111xxxxxxxx1110x0xxxxxxxxxx udot. */ - return 2899; + return 2908; } } } @@ -29798,7 +29897,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx00111100xxxxxx1111x0xxxxxxxxxx sudot. */ - return 2977; + return 2986; } else { @@ -29806,7 +29905,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx00111110xxxxxx1111x0xxxxxxxxxx usdot. */ - return 2976; + return 2985; } } else @@ -29817,7 +29916,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx00111101xxxxxx1111x0xxxxxxxxxx bfdot. */ - return 2988; + return 2997; } else { @@ -29827,7 +29926,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x000111111xxxxxx1111x0xxxxxxxxxx bfmlalb. */ - return 2996; + return 3005; } else { @@ -29835,7 +29934,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x100111111xxxxxx1111x0xxxxxxxxxx bfmlalt. */ - return 2995; + return 3004; } } } @@ -30363,11 +30462,11 @@ aarch64_find_next_opcode (const aarch64_opcode *opcode) case 2407: value = 2412; break; /* st1q --> st1q. */ case 2412: return NULL; /* st1q --> NULL. */ case 12: value = 19; break; /* add --> addg. */ - case 19: value = 3118; break; /* addg --> smax. */ - case 3118: value = 3119; break; /* smax --> umax. */ - case 3119: value = 3120; break; /* umax --> smin. */ - case 3120: value = 3121; break; /* smin --> umin. */ - case 3121: return NULL; /* umin --> NULL. */ + case 19: value = 3127; break; /* addg --> smax. */ + case 3127: value = 3128; break; /* smax --> umax. */ + case 3128: value = 3129; break; /* umax --> smin. */ + case 3129: value = 3130; break; /* smin --> umin. */ + case 3130: return NULL; /* umin --> NULL. */ case 16: value = 20; break; /* sub --> subg. */ case 20: return NULL; /* subg --> NULL. */ case 971: value = 975; break; /* stnp --> stp. */ @@ -30525,8 +30624,8 @@ aarch64_find_next_opcode (const aarch64_opcode *opcode) case 824: return NULL; /* fsqrt --> NULL. */ case 832: value = 833; break; /* frintz --> frintz. */ case 833: return NULL; /* frintz --> NULL. */ - case 825: value = 2992; break; /* fcvt --> bfcvt. */ - case 2992: return NULL; /* bfcvt --> NULL. */ + case 825: value = 3001; break; /* fcvt --> bfcvt. */ + case 3001: return NULL; /* bfcvt --> NULL. */ case 834: value = 835; break; /* frinta --> frinta. */ case 835: return NULL; /* frinta --> NULL. */ case 836: value = 837; break; /* frintx --> frintx. */ @@ -31055,7 +31154,7 @@ aarch64_extract_operand (const aarch64_operand *self, case 33: case 34: case 35: - case 268: + case 270: return aarch64_ext_reglane (self, info, code, inst, errors); case 36: return aarch64_ext_reglist (self, info, code, inst, errors); @@ -31102,12 +31201,12 @@ aarch64_extract_operand (const aarch64_operand *self, case 193: case 194: case 237: - case 262: - case 263: + case 264: case 265: case 267: - case 272: - case 273: + case 269: + case 274: + case 275: return aarch64_ext_imm (self, info, code, inst, errors); case 44: case 45: @@ -31178,8 +31277,8 @@ aarch64_extract_operand (const aarch64_operand *self, case 107: return aarch64_ext_prfop (self, info, code, inst, errors); case 108: - case 264: case 266: + case 268: return aarch64_ext_none (self, info, code, inst, errors); case 109: return aarch64_ext_hint (self, info, code, inst, errors); @@ -31259,6 +31358,7 @@ aarch64_extract_operand (const aarch64_operand *self, case 184: case 185: case 186: + case 250: return aarch64_ext_sve_shrimm (self, info, code, inst, errors); case 204: case 205: @@ -31292,8 +31392,6 @@ aarch64_extract_operand (const aarch64_operand *self, return aarch64_ext_sme_za_hv_tiles_range (self, info, code, inst, errors); case 235: case 236: - case 249: - case 250: case 251: case 252: case 253: @@ -31305,6 +31403,8 @@ aarch64_extract_operand (const aarch64_operand *self, case 259: case 260: case 261: + case 262: + case 263: return aarch64_ext_simple_index (self, info, code, inst, errors); case 239: case 240: @@ -31320,9 +31420,11 @@ aarch64_extract_operand (const aarch64_operand *self, return aarch64_ext_sme_sm_za (self, info, code, inst, errors); case 248: return aarch64_ext_sme_pred_reg_with_index (self, info, code, inst, errors); - case 269: - case 270: + case 249: + return aarch64_ext_plain_shrimm (self, info, code, inst, errors); case 271: + case 272: + case 273: return aarch64_ext_x0_to_x30 (self, info, code, inst, errors); default: assert (0); abort (); } diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c index fd13c924804..019ee8b0b81 100644 --- a/opcodes/aarch64-dis.c +++ b/opcodes/aarch64-dis.c @@ -2157,6 +2157,19 @@ aarch64_ext_simple_index (const aarch64_operand *self, aarch64_opnd_info *info, info->reglane.index = extract_all_fields_after (self, 1, code); return true; } + +/* Decode a plain shift-right immediate, when there is only a single + element size. */ +bool +aarch64_ext_plain_shrimm (const aarch64_operand *self, aarch64_opnd_info *info, + const aarch64_insn code, + const aarch64_inst *inst ATTRIBUTE_UNUSED, + aarch64_operand_error *errors ATTRIBUTE_UNUSED) +{ + unsigned int base = 1 << get_operand_field_width (self, 0); + info->imm.value = base - extract_field (self->fields[0], code, 0); + return true; +} /* Bitfields that are commonly used to encode certain operands' information may be partially used as part of the base opcode in some instructions. @@ -3078,6 +3091,10 @@ aarch64_decode_variant_using_iclass (aarch64_inst *inst) } break; + case sme_shift: + i = extract_field (FLD_SVE_tszh, inst->value, 0); + goto sve_shift; + case sme_size_12_bhs: variant = extract_field (FLD_SME_size_12, inst->value, 0); if (variant >= 3) diff --git a/opcodes/aarch64-dis.h b/opcodes/aarch64-dis.h index 6e6c00b1de2..3be382fe5fd 100644 --- a/opcodes/aarch64-dis.h +++ b/opcodes/aarch64-dis.h @@ -135,6 +135,7 @@ AARCH64_DECL_OPD_EXTRACTOR (ext_imm_rotate1); AARCH64_DECL_OPD_EXTRACTOR (ext_imm_rotate2); AARCH64_DECL_OPD_EXTRACTOR (ext_x0_to_x30); AARCH64_DECL_OPD_EXTRACTOR (ext_simple_index); +AARCH64_DECL_OPD_EXTRACTOR (ext_plain_shrimm); #undef AARCH64_DECL_OPD_EXTRACTOR diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c index a2ef94536ff..ae707ef82c9 100644 --- a/opcodes/aarch64-opc-2.c +++ b/opcodes/aarch64-opc-2.c @@ -273,6 +273,8 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_ADDRESS, "SME_ADDR_RI_U4xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_imm4_0}, "memory offset"}, {AARCH64_OPND_CLASS_ADDRESS, "SME_SM_ZA", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm}, "streaming mode"}, {AARCH64_OPND_CLASS_SVE_REG, "SME_PnT_Wm_imm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rm,FLD_SVE_Pn,FLD_SME_i1,FLD_SME_tszh,FLD_SME_tszl}, "Source scalable predicate register with index "}, + {AARCH64_OPND_CLASS_IMMEDIATE, "SME_SHRIMM4", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm4}, "a shift-right immediate operand"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "SME_SHRIMM5", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_SVE_imm5b}, "a shift-right immediate operand"}, {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm, FLD_imm1_10}, "an indexed SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm, FLD_imm2_10}, "an indexed SVE vector register"}, {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX3_1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm, FLD_imm1_10, FLD_imm2_1}, "an indexed SVE vector register"}, diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 0418a21b295..810548a93bd 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -2924,6 +2924,16 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, } break; + case AARCH64_OPND_SME_SHRIMM4: + size = 1 << get_operand_fields_width (get_operand_from_code (type)); + if (!value_in_range_p (opnd->imm.value, 1, size)) + { + set_imm_out_of_range_error (mismatch_detail, idx, 1, size); + return 0; + } + break; + + case AARCH64_OPND_SME_SHRIMM5: case AARCH64_OPND_SVE_SHRIMM_PRED: case AARCH64_OPND_SVE_SHRIMM_UNPRED: case AARCH64_OPND_SVE_SHRIMM_UNPRED_22: @@ -4103,6 +4113,8 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, case AARCH64_OPND_FBITS: case AARCH64_OPND_TME_UIMM16: case AARCH64_OPND_SIMM5: + case AARCH64_OPND_SME_SHRIMM4: + case AARCH64_OPND_SME_SHRIMM5: case AARCH64_OPND_SVE_SHLIMM_PRED: case AARCH64_OPND_SVE_SHLIMM_UNPRED: case AARCH64_OPND_SVE_SHLIMM_UNPRED_22: diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index b0c5bb54ae4..a6f5747c417 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -1628,6 +1628,10 @@ { \ QLF2(S_H,S_S), \ } +#define OP_SVE_HSU \ +{ \ + QLF3(S_H,S_S,NIL), \ +} #define OP_SVE_HU \ { \ QLF2(S_H,NIL), \ @@ -1854,6 +1858,11 @@ QLF3(S_S,P_M,S_H), \ QLF3(S_D,P_M,S_S), \ } +#define OP_SVE_VVU_BH_SD \ +{ \ + QLF3(S_B,S_S,NIL), \ + QLF3(S_H,S_D,NIL), \ +} #define OP_SVE_VVU_HSD_BHS \ { \ QLF3(S_H,S_B,NIL), \ @@ -5623,6 +5632,12 @@ const struct aarch64_opcode aarch64_opcode_table[] = SME2_INSN ("sqdmulh", 0xc120ac00, 0xff30ffe3, sme_size_22, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zm), OP_SVE_VVV_BHSD, 0, 1), SME2_INSN ("sqdmulh", 0xc120b400, 0xff21ffe1, sme_size_22, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zmx2), OP_SVE_VVV_BHSD, 0, 1), SME2_INSN ("sqdmulh", 0xc120bc00, 0xff23ffe3, sme_size_22, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zmx4), OP_SVE_VVV_BHSD, 0, 1), + SME2_INSN ("sqrshr", 0xc1e0d400, 0xfff0fc20, sme_misc, 0, OP3 (SVE_Zd, SME_Znx2, SME_SHRIMM4), OP_SVE_HSU, 0, 0), + SME2_INSN ("sqrshr", 0xc120d800, 0xff20fc60, sme_shift, 0, OP3 (SVE_Zd, SME_Znx4, SME_SHRIMM5), OP_SVE_VVU_BH_SD, 0, 0), + SME2_INSN ("sqrshrn", 0xc120dc00, 0xff20fc60, sme_shift, 0, OP3 (SVE_Zd, SME_Znx4, SME_SHRIMM5), OP_SVE_VVU_BH_SD, 0, 0), + SME2_INSN ("sqrshru", 0xc1f0d400, 0xfff0fc20, sme_misc, 0, OP3 (SVE_Zd, SME_Znx2, SME_SHRIMM4), OP_SVE_HSU, 0, 0), + SME2_INSN ("sqrshru", 0xc120d840, 0xff20fc60, sme_shift, 0, OP3 (SVE_Zd, SME_Znx4, SME_SHRIMM5), OP_SVE_VVU_BH_SD, 0, 0), + SME2_INSN ("sqrshrun", 0xc120dc40, 0xff20fc60, sme_shift, 0, OP3 (SVE_Zd, SME_Znx4, SME_SHRIMM5), OP_SVE_VVU_BH_SD, 0, 0), SME2_INSN ("srshl", 0xc120a220, 0xff30ffe1, sme_size_22, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zm), OP_SVE_VVV_BHSD, 0, 1), SME2_INSN ("srshl", 0xc120aa20, 0xff30ffe3, sme_size_22, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zm), OP_SVE_VVV_BHSD, 0, 1), SME2_INSN ("srshl", 0xc120b220, 0xff21ffe1, sme_size_22, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zmx2), OP_SVE_VVV_BHSD, 0, 1), @@ -5771,6 +5786,9 @@ const struct aarch64_opcode aarch64_opcode_table[] = SME2_INSN ("uqcvt", 0xc123e020, 0xfffffc20, sme_misc, 0, OP2 (SVE_Zd, SME_Znx2), OP_SVE_HS, 0, 0), SME2_INSN ("uqcvt", 0xc133e020, 0xff7ffc60, sme_sz_23, 0, OP2 (SVE_Zd, SME_Znx4), OP_SVE_VV_BH_SD, 0, 0), SME2_INSN ("uqcvtn", 0xc133e060, 0xff7ffc60, sme_sz_23, 0, OP2 (SVE_Zd, SME_Znx4), OP_SVE_VV_BH_SD, 0, 0), + SME2_INSN ("uqrshr", 0xc1e0d420, 0xfff0fc20, sme_misc, 0, OP3 (SVE_Zd, SME_Znx2, SME_SHRIMM4), OP_SVE_HSU, 0, 0), + SME2_INSN ("uqrshr", 0xc120d820, 0xff20fc60, sme_shift, 0, OP3 (SVE_Zd, SME_Znx4, SME_SHRIMM5), OP_SVE_VVU_BH_SD, 0, 0), + SME2_INSN ("uqrshrn", 0xc120dc20, 0xff20fc60, sme_shift, 0, OP3 (SVE_Zd, SME_Znx4, SME_SHRIMM5), OP_SVE_VVU_BH_SD, 0, 0), SME2_INSN ("urshl", 0xc120a221, 0xff30ffe1, sme_size_22, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zm), OP_SVE_VVV_BHSD, 0, 1), SME2_INSN ("urshl", 0xc120aa21, 0xff30ffe3, sme_size_22, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zm), OP_SVE_VVV_BHSD, 0, 1), SME2_INSN ("urshl", 0xc120b221, 0xff21ffe1, sme_size_22, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zmx2), OP_SVE_VVV_BHSD, 0, 1), @@ -6547,6 +6565,10 @@ const struct aarch64_opcode aarch64_opcode_table[] = Y(SVE_REG, sme_pred_reg_with_index, "SME_PnT_Wm_imm", 0, \ F(FLD_SME_Rm,FLD_SVE_Pn,FLD_SME_i1,FLD_SME_tszh,FLD_SME_tszl), \ "Source scalable predicate register with index ") \ + Y(IMMEDIATE, plain_shrimm, "SME_SHRIMM4", 0, F(FLD_SVE_imm4), \ + "a shift-right immediate operand") \ + Y(IMMEDIATE, sve_shrimm, "SME_SHRIMM5", 1 << OPD_F_OD_LSB, \ + F(FLD_SVE_tszh,FLD_SVE_imm5b), "a shift-right immediate operand") \ Y(SVE_REG, simple_index, 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Received: from e121540-lin.manchester.arm.com (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 696B33F663; Thu, 30 Mar 2023 03:27:11 -0700 (PDT) To: binutils@sourceware.org Cc: Richard Sandiford Subject: [PATCH 24/31] aarch64: Add the SME2 UNPK instructions Date: Thu, 30 Mar 2023 11:26:39 +0100 Message-Id: <20230330102646.3327818-25-richard.sandiford@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230330102646.3327818-1-richard.sandiford@arm.com> References: <20230330102646.3327818-1-richard.sandiford@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-32.0 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KAM_LOTSOFHASH, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Richard Sandiford via Binutils From: Richard Sandiford Reply-To: Richard Sandiford Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761790641905211916?= X-GMAIL-MSGID: =?utf-8?q?1761790641905211916?= This patch adds SUNPK and UUNPK, which unpack one register's worth of elements to two registers' worth, or two registers' worth to four registers' worth. --- gas/testsuite/gas/aarch64/sme2-29-invalid.d | 3 + gas/testsuite/gas/aarch64/sme2-29-invalid.l | 39 + gas/testsuite/gas/aarch64/sme2-29-invalid.s | 14 + gas/testsuite/gas/aarch64/sme2-29-noarch.d | 3 + gas/testsuite/gas/aarch64/sme2-29-noarch.l | 37 + gas/testsuite/gas/aarch64/sme2-29.d | 45 + gas/testsuite/gas/aarch64/sme2-29.s | 47 + opcodes/aarch64-dis-2.c | 1462 ++++++++++--------- opcodes/aarch64-tbl.h | 4 + 9 files changed, 945 insertions(+), 709 deletions(-) create mode 100644 gas/testsuite/gas/aarch64/sme2-29-invalid.d create mode 100644 gas/testsuite/gas/aarch64/sme2-29-invalid.l create mode 100644 gas/testsuite/gas/aarch64/sme2-29-invalid.s create mode 100644 gas/testsuite/gas/aarch64/sme2-29-noarch.d create mode 100644 gas/testsuite/gas/aarch64/sme2-29-noarch.l create mode 100644 gas/testsuite/gas/aarch64/sme2-29.d create mode 100644 gas/testsuite/gas/aarch64/sme2-29.s diff --git a/gas/testsuite/gas/aarch64/sme2-29-invalid.d b/gas/testsuite/gas/aarch64/sme2-29-invalid.d new file mode 100644 index 00000000000..ad85e2d6ffa --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-29-invalid.d @@ -0,0 +1,3 @@ +#as: -march=armv8-a +#source: sme2-29-invalid.s +#error_output: sme2-29-invalid.l diff --git a/gas/testsuite/gas/aarch64/sme2-29-invalid.l b/gas/testsuite/gas/aarch64/sme2-29-invalid.l new file mode 100644 index 00000000000..893866c114f --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-29-invalid.l @@ -0,0 +1,39 @@ +[^ :]+: Assembler messages: +[^ :]+:[0-9]+: Error: expected '{' at operand 1 -- `sunpk 0,z0\.b' +[^ :]+:[0-9]+: Error: expected a register or register list at operand 2 -- `sunpk {z0\.h,z1\.h},0' +[^ :]+:[0-9]+: Error: missing braces at operand 1 -- `sunpk z0\.b,z0\.b' +[^ :]+:[0-9]+: Error: operand mismatch -- `sunpk {z0\.b,z1\.b},z0\.b' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: sunpk {z0\.h-z1\.h}, z0\.b +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: sunpk {z0\.s-z1\.s}, z0\.h +[^ :]+:[0-9]+: Info: sunpk {z0\.d-z1\.d}, z0\.s +[^ :]+:[0-9]+: Error: operand mismatch -- `sunpk {z0\.h,z1\.h},z0\.h' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: sunpk {z0\.h-z1\.h}, z0\.b +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: sunpk {z0\.s-z1\.s}, z0\.h +[^ :]+:[0-9]+: Info: sunpk {z0\.d-z1\.d}, z0\.s +[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `sunpk {z1\.h,z2\.h},z0\.b' +[^ :]+:[0-9]+: Error: operand mismatch -- `sunpk {z0\.b,z2\.b},z0\.b' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: sunpk {z0\.h, z2\.h}, z0\.b +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: sunpk {z0\.s, z2\.s}, z0\.h +[^ :]+:[0-9]+: Info: sunpk {z0\.d, z2\.d}, z0\.s +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 1 -- `sunpk {z1\.h-z3\.h},{z0\.b-z1\.b}' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 1 -- `sunpk {z2\.h-z4\.h},{z0\.b-z1\.b}' +[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 1 -- `sunpk {z3\.h-z5\.h},{z0\.b-z1\.b}' +[^ :]+:[0-9]+: Error: operand mismatch -- `sunpk {z0\.s-z3\.s},z0\.b' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: sunpk {z0\.h-z3\.h}, z0\.b +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: sunpk {z0\.s-z3\.s}, z0\.h +[^ :]+:[0-9]+: Info: sunpk {z0\.d-z3\.d}, z0\.s +[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sunpk {z0\.s-z3\.s},{x0\.s-x1\.s}' +[^ :]+:[0-9]+: Error: operand mismatch -- `sunpk {z0\.s-z3\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: sunpk {z0\.s-z3\.s}, {z0\.h-z3\.h} +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: sunpk {z0\.h-z3\.h}, {z0\.b-z3\.b} +[^ :]+:[0-9]+: Info: sunpk {z0\.d-z3\.d}, {z0\.s-z3\.s} diff --git a/gas/testsuite/gas/aarch64/sme2-29-invalid.s b/gas/testsuite/gas/aarch64/sme2-29-invalid.s new file mode 100644 index 00000000000..2282dd214f4 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-29-invalid.s @@ -0,0 +1,14 @@ + sunpk 0, z0.b + sunpk { z0.h, z1.h }, 0 + + sunpk z0.b, z0.b + sunpk { z0.b, z1.b }, z0.b + sunpk { z0.h, z1.h }, z0.h + sunpk { z1.h, z2.h }, z0.b + sunpk { z0.b, z2.b }, z0.b + sunpk { z1.h - z3.h }, { z0.b - z1.b } + sunpk { z2.h - z4.h }, { z0.b - z1.b } + sunpk { z3.h - z5.h }, { z0.b - z1.b } + sunpk { z0.s - z3.s }, z0.b + sunpk { z0.s - z3.s }, { x0.s - x1.s } + sunpk { z0.s - z3.s }, { z0.s - z3.s } diff --git a/gas/testsuite/gas/aarch64/sme2-29-noarch.d b/gas/testsuite/gas/aarch64/sme2-29-noarch.d new file mode 100644 index 00000000000..73c02c50997 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-29-noarch.d @@ -0,0 +1,3 @@ +#as: -march=armv8-a+sme +#source: sme2-29.s +#error_output: sme2-29-noarch.l diff --git a/gas/testsuite/gas/aarch64/sme2-29-noarch.l b/gas/testsuite/gas/aarch64/sme2-29-noarch.l new file mode 100644 index 00000000000..2777e1672b3 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-29-noarch.l @@ -0,0 +1,37 @@ +[^ :]+: Assembler messages: +[^ :]+:[0-9]+: Error: selected processor does not support `sunpk {z0\.h,z1\.h},z0\.b' +[^ :]+:[0-9]+: Error: selected processor does not support `sunpk {z30\.h,z31\.h},z0\.b' +[^ :]+:[0-9]+: Error: selected processor does not support `sunpk {z0\.h,z1\.h},z31\.b' +[^ :]+:[0-9]+: Error: selected processor does not support `sunpk {z0\.h-z3\.h},{z0\.b-z1\.b}' +[^ :]+:[0-9]+: Error: selected processor does not support `sunpk {z28\.h-z31\.h},{z0\.b-z1\.b}' +[^ :]+:[0-9]+: Error: selected processor does not support `sunpk {z0\.h-z3\.h},{z30\.b-z31\.b}' +[^ :]+:[0-9]+: Error: selected processor does not support `sunpk {z0\.s,z1\.s},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `sunpk {z30\.s,z31\.s},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `sunpk {z0\.s,z1\.s},z31\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `sunpk {z0\.s-z3\.s},{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `sunpk {z28\.s-z31\.s},{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `sunpk {z0\.s-z3\.s},{z30\.h-z31\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `sunpk {z0\.d,z1\.d},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `sunpk {z30\.d,z31\.d},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `sunpk {z0\.d,z1\.d},z31\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `sunpk {z0\.d-z3\.d},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sunpk {z28\.d-z31\.d},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `sunpk {z0\.d-z3\.d},{z30\.s-z31\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `uunpk {z0\.h,z1\.h},z0\.b' +[^ :]+:[0-9]+: Error: selected processor does not support `uunpk {z30\.h,z31\.h},z0\.b' +[^ :]+:[0-9]+: Error: selected processor does not support `uunpk {z0\.h,z1\.h},z31\.b' +[^ :]+:[0-9]+: Error: selected processor does not support `uunpk {z0\.h-z3\.h},{z0\.b-z1\.b}' +[^ :]+:[0-9]+: Error: selected processor does not support `uunpk {z28\.h-z31\.h},{z0\.b-z1\.b}' +[^ :]+:[0-9]+: Error: selected processor does not support `uunpk {z0\.h-z3\.h},{z30\.b-z31\.b}' +[^ :]+:[0-9]+: Error: selected processor does not support `uunpk {z0\.s,z1\.s},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `uunpk {z30\.s,z31\.s},z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `uunpk {z0\.s,z1\.s},z31\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `uunpk {z0\.s-z3\.s},{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `uunpk {z28\.s-z31\.s},{z0\.h-z1\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `uunpk {z0\.s-z3\.s},{z30\.h-z31\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `uunpk {z0\.d,z1\.d},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `uunpk {z30\.d,z31\.d},z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `uunpk {z0\.d,z1\.d},z31\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `uunpk {z0\.d-z3\.d},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `uunpk {z28\.d-z31\.d},{z0\.s-z1\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `uunpk {z0\.d-z3\.d},{z30\.s-z31\.s}' diff --git a/gas/testsuite/gas/aarch64/sme2-29.d b/gas/testsuite/gas/aarch64/sme2-29.d new file mode 100644 index 00000000000..235b0554b8f --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-29.d @@ -0,0 +1,45 @@ +#as: -march=armv8-a+sme2 +#objdump: -dr + +[^:]+: file format .* + + +[^:]+: + +[^:]+: +[^:]+: c165e000 sunpk {z0\.h-z1\.h}, z0\.b +[^:]+: c165e01e sunpk {z30\.h-z31\.h}, z0\.b +[^:]+: c165e3e0 sunpk {z0\.h-z1\.h}, z31\.b +[^:]+: c175e000 sunpk {z0\.h-z3\.h}, {z0\.b-z1\.b} +[^:]+: c175e01c sunpk {z28\.h-z31\.h}, {z0\.b-z1\.b} +[^:]+: c175e3c0 sunpk {z0\.h-z3\.h}, {z30\.b-z31\.b} +[^:]+: c1a5e000 sunpk {z0\.s-z1\.s}, z0\.h +[^:]+: c1a5e01e sunpk {z30\.s-z31\.s}, z0\.h +[^:]+: c1a5e3e0 sunpk {z0\.s-z1\.s}, z31\.h +[^:]+: c1b5e000 sunpk {z0\.s-z3\.s}, {z0\.h-z1\.h} +[^:]+: c1b5e01c sunpk {z28\.s-z31\.s}, {z0\.h-z1\.h} +[^:]+: c1b5e3c0 sunpk {z0\.s-z3\.s}, {z30\.h-z31\.h} +[^:]+: c1e5e000 sunpk {z0\.d-z1\.d}, z0\.s +[^:]+: c1e5e01e sunpk {z30\.d-z31\.d}, z0\.s +[^:]+: c1e5e3e0 sunpk {z0\.d-z1\.d}, z31\.s +[^:]+: c1f5e000 sunpk {z0\.d-z3\.d}, {z0\.s-z1\.s} +[^:]+: c1f5e01c sunpk {z28\.d-z31\.d}, {z0\.s-z1\.s} +[^:]+: c1f5e3c0 sunpk {z0\.d-z3\.d}, {z30\.s-z31\.s} +[^:]+: c165e001 uunpk {z0\.h-z1\.h}, z0\.b +[^:]+: c165e01f uunpk {z30\.h-z31\.h}, z0\.b +[^:]+: c165e3e1 uunpk {z0\.h-z1\.h}, z31\.b +[^:]+: c175e001 uunpk {z0\.h-z3\.h}, {z0\.b-z1\.b} +[^:]+: c175e01d uunpk {z28\.h-z31\.h}, {z0\.b-z1\.b} +[^:]+: c175e3c1 uunpk {z0\.h-z3\.h}, {z30\.b-z31\.b} +[^:]+: c1a5e001 uunpk {z0\.s-z1\.s}, z0\.h +[^:]+: c1a5e01f uunpk {z30\.s-z31\.s}, z0\.h +[^:]+: c1a5e3e1 uunpk {z0\.s-z1\.s}, z31\.h +[^:]+: c1b5e001 uunpk {z0\.s-z3\.s}, {z0\.h-z1\.h} +[^:]+: c1b5e01d uunpk {z28\.s-z31\.s}, {z0\.h-z1\.h} +[^:]+: c1b5e3c1 uunpk {z0\.s-z3\.s}, {z30\.h-z31\.h} +[^:]+: c1e5e001 uunpk {z0\.d-z1\.d}, z0\.s +[^:]+: c1e5e01f uunpk {z30\.d-z31\.d}, z0\.s +[^:]+: c1e5e3e1 uunpk {z0\.d-z1\.d}, z31\.s +[^:]+: c1f5e001 uunpk {z0\.d-z3\.d}, {z0\.s-z1\.s} +[^:]+: c1f5e01d uunpk {z28\.d-z31\.d}, {z0\.s-z1\.s} +[^:]+: c1f5e3c1 uunpk {z0\.d-z3\.d}, {z30\.s-z31\.s} diff --git a/gas/testsuite/gas/aarch64/sme2-29.s b/gas/testsuite/gas/aarch64/sme2-29.s new file mode 100644 index 00000000000..1cf1a3f239b --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-29.s @@ -0,0 +1,47 @@ + sunpk { z0.h, z1.h }, z0.b + sunpk { z30.h, z31.h }, z0.b + sunpk { z0.h, z1.h }, z31.b + + sunpk { z0.h - z3.h }, { z0.b - z1.b } + sunpk { z28.h - z31.h }, { z0.b - z1.b } + sunpk { z0.h - z3.h }, { z30.b - z31.b } + + sunpk { z0.s, z1.s }, z0.h + sunpk { z30.s, z31.s }, z0.h + sunpk { z0.s, z1.s }, z31.h + + sunpk { z0.s - z3.s }, { z0.h - z1.h } + sunpk { z28.s - z31.s }, { z0.h - z1.h } + sunpk { z0.s - z3.s }, { z30.h - z31.h } + + sunpk { z0.d, z1.d }, z0.s + sunpk { z30.d, z31.d }, z0.s + sunpk { z0.d, z1.d }, z31.s + + sunpk { z0.d - z3.d }, { z0.s - z1.s } + sunpk { z28.d - z31.d }, { z0.s - z1.s } + sunpk { z0.d - z3.d }, { z30.s - z31.s } + + uunpk { z0.h, z1.h }, z0.b + uunpk { z30.h, z31.h }, z0.b + uunpk { z0.h, z1.h }, z31.b + + uunpk { z0.h - z3.h }, { z0.b - z1.b } + uunpk { z28.h - z31.h }, { z0.b - z1.b } + uunpk { z0.h - z3.h }, { z30.b - z31.b } + + uunpk { z0.s, z1.s }, z0.h + uunpk { z30.s, z31.s }, z0.h + uunpk { z0.s, z1.s }, z31.h + + uunpk { z0.s - z3.s }, { z0.h - z1.h } + uunpk { z28.s - z31.s }, { z0.h - z1.h } + uunpk { z0.s - z3.s }, { z30.h - z31.h } + + uunpk { z0.d, z1.d }, z0.s + uunpk { z30.d, z31.d }, z0.s + uunpk { z0.d, z1.d }, z31.s + + uunpk { z0.d - z3.d }, { z0.s - z1.s } + uunpk { z28.d - z31.d }, { z0.s - z1.s } + uunpk { z0.d - z3.d }, { z30.s - z31.s } diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c index d82c37498e7..e514becb5fd 100644 --- a/opcodes/aarch64-dis-2.c +++ b/opcodes/aarch64-dis-2.c @@ -188,7 +188,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000x10x100xxxxxxxxxxxxxxxxx zero. */ - return 2883; + return 2887; } } } @@ -1326,7 +1326,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000010000xxxxxxxxxxxxxxx001xx usmlall. */ - return 2864; + return 2866; } } else @@ -1358,7 +1358,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000010001xxxx0xxxxxxxxx100xxx usmlall. */ - return 2865; + return 2867; } else { @@ -1366,7 +1366,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000010001xxxx1xxxxxxxxx100xxx usmlall. */ - return 2866; + return 2868; } } } @@ -1381,7 +1381,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000010000xxxxxxxxxxxxxxx100xx umlall. */ - return 2822; + return 2824; } else { @@ -1402,7 +1402,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000010001xxxx0xxxxxxxxx010xxx umlall. */ - return 2823; + return 2825; } else { @@ -1410,7 +1410,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000010001xxxx1xxxxxxxxx010xxx umlall. */ - return 2824; + return 2826; } } else @@ -1475,7 +1475,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000010000xxxxxxxxxxxxxxx11xxx umlsll. */ - return 2838; + return 2840; } else { @@ -1485,7 +1485,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000010001xxxx0xxxxxxxxxx11xxx umlsll. */ - return 2839; + return 2841; } else { @@ -1493,7 +1493,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000010001xxxx1xxxxxxxxxx11xxx umlsll. */ - return 2840; + return 2842; } } } @@ -1721,7 +1721,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011000xxxxxxx0xxxxxxx00xxx smlall. */ - return 2886; + return 2890; } else { @@ -1731,7 +1731,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011001xxxx0xx0xxxxxxx00xxx smlall. */ - return 2887; + return 2891; } else { @@ -1739,7 +1739,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011001xxxx1xx0xxxxxxx00xxx smlall. */ - return 2888; + return 2892; } } } @@ -1806,7 +1806,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011000xxxxxxx0xxxxxxx10xxx umlall. */ - return 2895; + return 2899; } else { @@ -1816,7 +1816,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011001xxxx0xx0xxxxxxx10xxx umlall. */ - return 2896; + return 2900; } else { @@ -1824,7 +1824,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011001xxxx1xx0xxxxxxx10xxx umlall. */ - return 2897; + return 2901; } } } @@ -1884,7 +1884,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000011000xxxxxxx0xxxxxxx01xxx smlsll. */ - return 2889; + return 2893; } else { @@ -1894,7 +1894,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000011001xxxx0xx0xxxxxxx01xxx smlsll. */ - return 2890; + return 2894; } else { @@ -1902,7 +1902,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000011001xxxx1xx0xxxxxxx01xxx smlsll. */ - return 2891; + return 2895; } } } @@ -1943,7 +1943,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001100xxxxxxxxxxxxxxxx01xxx umopa. */ - return 2846; + return 2848; } } else @@ -1958,7 +1958,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000011000xxxxxxx0xxxxxxx11xxx umlsll. */ - return 2898; + return 2902; } else { @@ -1968,7 +1968,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000011001xxxx0xx0xxxxxxx11xxx umlsll. */ - return 2899; + return 2903; } else { @@ -1976,7 +1976,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000011001xxxx1xx0xxxxxxx11xxx umlsll. */ - return 2900; + return 2904; } } } @@ -2017,7 +2017,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001100xxxxxxxxxxxxxxxx11xxx umops. */ - return 2847; + return 2849; } } } @@ -2103,7 +2103,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000010101xxxx0xx0xxxxxx100xxx svdot. */ - return 2788; + return 2790; } else { @@ -2133,7 +2133,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000010101xxxx0xx1xxxxxx010xxx udot. */ - return 2794; + return 2796; } } else @@ -2144,7 +2144,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000010101xxxx0xx0xxxxxx110xxx uvdot. */ - return 2873; + return 2877; } else { @@ -2152,7 +2152,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000010101xxxx0xx1xxxxxx110xxx udot. */ - return 2800; + return 2802; } } } @@ -2232,7 +2232,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000010101xxxx1xx0xxxxxx100xxx svdot. */ - return 2789; + return 2791; } else { @@ -2262,7 +2262,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000010101xxxx1xx1xxxxxx010xxx udot. */ - return 2795; + return 2797; } } else @@ -2273,7 +2273,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000010101xxxx1xx0xxxxxx110xxx uvdot. */ - return 2874; + return 2878; } else { @@ -2281,7 +2281,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000010101xxxx1xx1xxxxxx110xxx udot. */ - return 2801; + return 2803; } } } @@ -2362,7 +2362,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000010101xxxx0xxxxxxxxx101xxx usdot. */ - return 2858; + return 2860; } } else @@ -2460,7 +2460,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000010101xxxx1xx0xxxxxx101xxx usvdot. */ - return 2872; + return 2874; } else { @@ -2468,7 +2468,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000010101xxxx1xx1xxxxxx101xxx usdot. */ - return 2859; + return 2861; } } } @@ -2490,7 +2490,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000010101xxxx1xx0xxxxxx111xxx suvdot. */ - return 2787; + return 2789; } else { @@ -2522,7 +2522,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx000001110xxxxx0xx0xxxxxxx00xxx fmla. */ - return 2902; + return 2906; } else { @@ -2530,7 +2530,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx000001110xxxxx1xx0xxxxxxx00xxx fmla. */ - return 2903; + return 2907; } } else @@ -2576,7 +2576,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx000001110xxxxx0xx00xxxxxx01xxx sdot. */ - return 2884; + return 2888; } else { @@ -2584,7 +2584,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx000001110xxxxx1xx00xxxxxx01xxx sdot. */ - return 2885; + return 2889; } } else @@ -2593,7 +2593,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx000001110xxxxxxxx01xxxxxx01xxx svdot. */ - return 2892; + return 2896; } } else @@ -2662,7 +2662,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx000001110xxxxx0xx0xxxxxxx10xxx fmls. */ - return 2904; + return 2908; } else { @@ -2670,7 +2670,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx000001110xxxxx1xx0xxxxxxx10xxx fmls. */ - return 2905; + return 2909; } } else @@ -2681,7 +2681,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000011100xxxxxxx1xxxxxxx10xxx umlal. */ - return 2814; + return 2816; } else { @@ -2691,7 +2691,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000011101xxxx0xx1xxxxxxx10xxx umlal. */ - return 2815; + return 2817; } else { @@ -2699,7 +2699,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000011101xxxx1xx1xxxxxxx10xxx umlal. */ - return 2816; + return 2818; } } } @@ -2725,7 +2725,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001110xxxxx0xx00xxxxxx11xxx udot. */ - return 2893; + return 2897; } else { @@ -2733,7 +2733,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001110xxxxx1xx00xxxxxx11xxx udot. */ - return 2894; + return 2898; } } else @@ -2742,7 +2742,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001110xxxxxxxx01xxxxxx11xxx uvdot. */ - return 2901; + return 2905; } } else @@ -2753,7 +2753,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000011100xxxxxxx1xxxxxxx11xxx umlsl. */ - return 2830; + return 2832; } else { @@ -2763,7 +2763,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000011101xxxx0xx1xxxxxxx11xxx umlsl. */ - return 2831; + return 2833; } else { @@ -2771,7 +2771,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx000011101xxxx1xx1xxxxxxx11xxx umlsl. */ - return 2832; + return 2834; } } } @@ -2868,7 +2868,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000010x10xxxx0xx000xxxxx001xx usmlall. */ - return 2868; + return 2870; } else { @@ -2876,7 +2876,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000010x11xxxx0xx000xxxxx001xx usmlall. */ - return 2869; + return 2871; } } else @@ -2887,7 +2887,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011x1xxxx00xx000xxxxx001xx usmlall. */ - return 2870; + return 2872; } else { @@ -2895,7 +2895,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011x1xxxx10xx000xxxxx001xx usmlall. */ - return 2871; + return 2873; } } } @@ -3092,7 +3092,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx0xx001xxxxx001xx usmlall. */ - return 2867; + return 2869; } } else @@ -3198,7 +3198,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000010x10xxxx0xx000xxxxx100xx umlall. */ - return 2826; + return 2828; } else { @@ -3206,7 +3206,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000010x11xxxx0xx000xxxxx100xx umlall. */ - return 2827; + return 2829; } } else @@ -3217,7 +3217,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011x1xxxx00xx000xxxxx100xx umlall. */ - return 2828; + return 2830; } else { @@ -3225,7 +3225,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011x1xxxx10xx000xxxxx100xx umlall. */ - return 2829; + return 2831; } } } @@ -3346,7 +3346,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000010110xxxx0xx010xxxxx10xxx umlal. */ - return 2818; + return 2820; } else { @@ -3354,7 +3354,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000010111xxxx0xx010xxxxx10xxx umlal. */ - return 2819; + return 2821; } } else @@ -3365,7 +3365,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001111xxxx00xx010xxxxx10xxx umlal. */ - return 2820; + return 2822; } else { @@ -3373,7 +3373,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001111xxxx10xx010xxxxx10xxx umlal. */ - return 2821; + return 2823; } } } @@ -3431,7 +3431,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx0xx001xxxxx10xxx umlall. */ - return 2825; + return 2827; } else { @@ -3443,7 +3443,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000010x10xxxx0xx101xxxxx10xxx udot. */ - return 2802; + return 2804; } else { @@ -3451,7 +3451,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000010x11xxxx0xx101xxxxx10xxx udot. */ - return 2803; + return 2805; } } else @@ -3462,7 +3462,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011x1xxxx00xx101xxxxx10xxx udot. */ - return 2804; + return 2806; } else { @@ -3470,7 +3470,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011x1xxxx10xx101xxxxx10xxx udot. */ - return 2805; + return 2807; } } } @@ -3493,7 +3493,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001x11xxxxx0xx011xxxxx10xxx umlal. */ - return 2817; + return 2819; } } else @@ -3720,7 +3720,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000010010xxxx0xx101xxxxx01xxx usdot. */ - return 2860; + return 2862; } else { @@ -3728,7 +3728,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000010011xxxx0xx101xxxxx01xxx usdot. */ - return 2861; + return 2863; } } else @@ -3739,7 +3739,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001101xxxx00xx101xxxxx01xxx usdot. */ - return 2862; + return 2864; } else { @@ -3747,7 +3747,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001101xxxx10xx101xxxxx01xxx usdot. */ - return 2863; + return 2865; } } } @@ -3851,7 +3851,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000010x10xxxx0xxx00xxxxx11xxx umlsll. */ - return 2842; + return 2844; } else { @@ -3859,7 +3859,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000010x11xxxx0xxx00xxxxx11xxx umlsll. */ - return 2843; + return 2845; } } else @@ -3870,7 +3870,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011x1xxxx00xxx00xxxxx11xxx umlsll. */ - return 2844; + return 2846; } else { @@ -3878,7 +3878,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011x1xxxx10xxx00xxxxx11xxx umlsll. */ - return 2845; + return 2847; } } } @@ -3937,7 +3937,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000010110xxxx0xx010xxxxx11xxx umlsl. */ - return 2834; + return 2836; } else { @@ -3945,7 +3945,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000010111xxxx0xx010xxxxx11xxx umlsl. */ - return 2835; + return 2837; } } else @@ -3956,7 +3956,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001111xxxx00xx010xxxxx11xxx umlsl. */ - return 2836; + return 2838; } else { @@ -3964,7 +3964,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001111xxxx10xx010xxxxx11xxx umlsl. */ - return 2837; + return 2839; } } } @@ -4022,7 +4022,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx0xx001xxxxx11xxx umlsll. */ - return 2841; + return 2843; } else { @@ -4055,7 +4055,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000010110xxxx0xx101xxxxx11xxx udot. */ - return 2796; + return 2798; } else { @@ -4063,7 +4063,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000010111xxxx0xx101xxxxx11xxx udot. */ - return 2797; + return 2799; } } else @@ -4074,7 +4074,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001111xxxx00xx101xxxxx11xxx udot. */ - return 2798; + return 2800; } else { @@ -4082,7 +4082,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001111xxxx10xx101xxxxx11xxx udot. */ - return 2799; + return 2801; } } } @@ -4106,7 +4106,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001x11xxxxx0xx011xxxxx11xxx umlsl. */ - return 2833; + return 2835; } } else @@ -4205,7 +4205,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx110110xxxx1xxxxx uqrshr. */ - return 2852; + return 2854; } } } @@ -4230,7 +4230,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx110001xxxxxxxxx1 uclamp. */ - return 2790; + return 2792; } } else @@ -4260,7 +4260,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx110101xxxx1xxxxx uqrshr. */ - return 2851; + return 2853; } } } @@ -4282,7 +4282,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx110011xxxxxxxxx1 uclamp. */ - return 2791; + return 2793; } } else @@ -4312,7 +4312,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx110111xxxx1xxxxx uqrshrn. */ - return 2853; + return 2855; } } } @@ -4321,17 +4321,17 @@ aarch64_opcode_lookup_1 (uint32_t word) } else { - if (((word >> 5) & 0x1) == 0) + if (((word >> 10) & 0x1) == 0) { - if (((word >> 10) & 0x1) == 0) + if (((word >> 11) & 0x1) == 0) { - if (((word >> 11) & 0x1) == 0) + if (((word >> 12) & 0x1) == 0) { - if (((word >> 12) & 0x1) == 0) + if (((word >> 14) & 0x1) == 0) { - if (((word >> 14) & 0x1) == 0) + if (((word >> 0) & 0x1) == 0) { - if (((word >> 0) & 0x1) == 0) + if (((word >> 5) & 0x1) == 0) { if (((word >> 8) & 0x1) == 0) { @@ -4362,6 +4362,39 @@ aarch64_opcode_lookup_1 (uint32_t word) } } else + { + if (((word >> 8) & 0x1) == 0) + { + if (((word >> 9) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xxxxx10100000xx1xxxx0 + smin. */ + return 2649; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xxxxx10100010xx1xxxx0 + srshl. */ + return 2703; + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xxxxx101000x1xx1xxxx0 + fmaxnm. */ + return 2484; + } + } + } + else + { + if (((word >> 5) & 0x1) == 0) { if (((word >> 8) & 0x1) == 0) { @@ -4369,7 +4402,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxxx101000x0xx0xxxx1 umax. */ - return 2806; + return 2808; } else { @@ -4380,10 +4413,43 @@ aarch64_opcode_lookup_1 (uint32_t word) return 2488; } } + else + { + if (((word >> 8) & 0x1) == 0) + { + if (((word >> 9) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xxxxx10100000xx1xxxx1 + umin. */ + return 2812; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xxxxx10100010xx1xxxx1 + urshl. */ + return 2856; + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xxxxx101000x1xx1xxxx1 + fminnm. */ + return 2492; + } + } } - else + } + else + { + if (((word >> 16) & 0x1) == 0) { - if (((word >> 16) & 0x1) == 0) + if (((word >> 5) & 0x1) == 0) { if (((word >> 17) & 0x1) == 0) { @@ -4494,23 +4560,111 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 17) & 0x1) == 0) { - if (((word >> 19) & 0x1) == 0) + if (((word >> 22) & 0x1) == 0) { - if (((word >> 20) & 0x1) == 0) + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001x01xxx00111000xxxx1xxxxx + fcvtn. */ + return 2469; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001x11xxx00111000xxxx1xxxxx + bfcvtn. */ + return 2437; + } + } + else + { + if (((word >> 20) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx10xx10111000xxxx1xxxxx + ucvtf. */ + return 2794; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx11xx10111000xxxx1xxxxx + ucvtf. */ + return 2795; + } + } + } + } + else + { + if (((word >> 17) & 0x1) == 0) + { + if (((word >> 0) & 0x1) == 0) + { + if (((word >> 18) & 0x1) == 0) + { + if (((word >> 5) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx100x01111000xxxx0xxxxx - fcvtzs. */ - return 2470; + if (((word >> 19) & 0x1) == 0) + { + if (((word >> 20) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx100001111000xxxx0xxxx0 + fcvtzs. */ + return 2470; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx110001111000xxxx0xxxx0 + fcvtzs. */ + return 2471; + } + } + else + { + if (((word >> 20) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx101001111000xxxx0xxxx0 + frintp. */ + return 2530; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx111001111000xxxx0xxxx0 + frintp. */ + return 2531; + } + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx110x01111000xxxx0xxxxx - fcvtzs. */ - return 2471; + if (((word >> 20) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx10x001111000xxxx1xxxx0 + fcvtzu. */ + return 2472; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx11x001111000xxxx1xxxx0 + fcvtzu. */ + return 2473; + } } } else @@ -4519,21 +4673,43 @@ aarch64_opcode_lookup_1 (uint32_t word) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x1000001xx101x01111000xxxx0xxxxx - frintp. */ - return 2530; + x1000001xx10x101111000xxxxxxxxx0 + sunpk. */ + return 2787; } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x1000001xx111x01111000xxxx0xxxxx - frintp. */ - return 2531; + x1000001xx11x101111000xxxxxxxxx0 + sunpk. */ + return 2788; } } } else + { + if (((word >> 20) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx10xx01111000xxxxxxxxx1 + uunpk. */ + return 2875; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx11xx01111000xxxxxxxxx1 + uunpk. */ + return 2876; + } + } + } + else + { + if (((word >> 5) & 0x1) == 0) { if (((word >> 20) & 0x1) == 0) { @@ -4596,12 +4772,45 @@ aarch64_opcode_lookup_1 (uint32_t word) } } } + else + { + if (((word >> 20) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx10xx11111000xxxx1xxxxx + uqcvt. */ + return 2850; + } + else + { + if (((word >> 6) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx11xx11111000xxx01xxxxx + uqcvt. */ + return 2851; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx11xx11111000xxx11xxxxx + uqcvtn. */ + return 2852; + } + } + } } } } - else + } + else + { + if (((word >> 0) & 0x1) == 0) { - if (((word >> 0) & 0x1) == 0) + if (((word >> 5) & 0x1) == 0) { if (((word >> 8) & 0x1) == 0) { @@ -4624,115 +4833,82 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 8) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx1xxxxx1x1100x0xx0xxxx1 - umax. */ - return 2808; - } - else - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx1xxxxx1x1100x1xx0xxxx1 - fmin. */ - return 2490; - } - } - } - } - else - { - if (((word >> 0) & 0x1) == 0) - { - if (((word >> 8) & 0x1) == 0) - { - if (((word >> 12) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx1xxxxx1x1010x0xx0xxxx0 - smax. */ - return 2646; - } - else - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx1xxxxx1x1110x0xx0xxxx0 - smax. */ - return 2648; - } - } - else - { - if (((word >> 9) & 0x1) == 0) - { - if (((word >> 12) & 0x1) == 0) + if (((word >> 9) & 0x1) == 0) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x1000001xx1xxxxx1x101001xx0xxxx0 - fmax. */ - return 2481; + x1000001xx1xxxxx1x110000xx1xxxx0 + smin. */ + return 2651; } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x1000001xx1xxxxx1x111001xx0xxxx0 - fmax. */ - return 2483; + x1000001xx1xxxxx1x110010xx1xxxx0 + srshl. */ + return 2705; } } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x1000001xx1xxxxx1x1x1011xx0xxxx0 - add. */ - return 2435; + x1000001xx1xxxxx1x1100x1xx1xxxx0 + fmaxnm. */ + return 2486; } } } else { - if (((word >> 8) & 0x1) == 0) + if (((word >> 5) & 0x1) == 0) { - if (((word >> 12) & 0x1) == 0) + if (((word >> 8) & 0x1) == 0) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x1000001xx1xxxxx1x1010x0xx0xxxx1 + x1000001xx1xxxxx1x1100x0xx0xxxx1 umax. */ - return 2807; + return 2810; } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x1000001xx1xxxxx1x1110x0xx0xxxx1 - umax. */ - return 2809; + x1000001xx1xxxxx1x1100x1xx0xxxx1 + fmin. */ + return 2490; } } else { - if (((word >> 12) & 0x1) == 0) + if (((word >> 8) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx1xxxxx1x1010x1xx0xxxx1 - fmin. */ - return 2489; + if (((word >> 9) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xxxxx1x110000xx1xxxx1 + umin. */ + return 2814; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xxxxx1x110010xx1xxxx1 + urshl. */ + return 2858; + } } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x1000001xx1xxxxx1x1110x1xx0xxxx1 - fmin. */ - return 2491; + x1000001xx1xxxxx1x1100x1xx1xxxx1 + fminnm. */ + return 2494; } } } @@ -4740,299 +4916,145 @@ aarch64_opcode_lookup_1 (uint32_t word) } else { - if (((word >> 11) & 0x1) == 0) - { - if (((word >> 12) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx1xxxxx1x1001xxxx0xxxxx - sqdmulh. */ - return 2693; - } - else - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx1xxxxx1x1101xxxx0xxxxx - sqdmulh. */ - return 2695; - } - } - else - { - if (((word >> 12) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx1xxxxx1x1011xxxx0xxxxx - sqdmulh. */ - return 2694; - } - else - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx1xxxxx1x1111xxxx0xxxxx - sqdmulh. */ - return 2696; - } - } - } - } - else - { - if (((word >> 11) & 0x1) == 0) - { - if (((word >> 12) & 0x1) == 0) + if (((word >> 0) & 0x1) == 0) { - if (((word >> 14) & 0x1) == 0) + if (((word >> 5) & 0x1) == 0) { - if (((word >> 0) & 0x1) == 0) + if (((word >> 8) & 0x1) == 0) { - if (((word >> 8) & 0x1) == 0) + if (((word >> 12) & 0x1) == 0) { - if (((word >> 9) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx1xxxxx10100x00xx1xxxx0 - smin. */ - return 2649; - } - else - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx1xxxxx10100x10xx1xxxx0 - srshl. */ - return 2703; - } + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xxxxx1x1010x0xx0xxxx0 + smax. */ + return 2646; } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x1000001xx1xxxxx10100xx1xx1xxxx0 - fmaxnm. */ - return 2484; + x1000001xx1xxxxx1x1110x0xx0xxxx0 + smax. */ + return 2648; } } else { - if (((word >> 8) & 0x1) == 0) + if (((word >> 9) & 0x1) == 0) { - if (((word >> 9) & 0x1) == 0) + if (((word >> 12) & 0x1) == 0) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x1000001xx1xxxxx10100x00xx1xxxx1 - umin. */ - return 2810; + x1000001xx1xxxxx1x101001xx0xxxx0 + fmax. */ + return 2481; } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x1000001xx1xxxxx10100x10xx1xxxx1 - urshl. */ - return 2854; + x1000001xx1xxxxx1x111001xx0xxxx0 + fmax. */ + return 2483; } } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x1000001xx1xxxxx10100xx1xx1xxxx1 - fminnm. */ - return 2492; + x1000001xx1xxxxx1x1x1011xx0xxxx0 + add. */ + return 2435; } } } else { - if (((word >> 16) & 0x1) == 0) + if (((word >> 8) & 0x1) == 0) { - if (((word >> 17) & 0x1) == 0) + if (((word >> 9) & 0x1) == 0) { - if (((word >> 22) & 0x1) == 0) + if (((word >> 12) & 0x1) == 0) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x1000001x01xxx0011100xxxxx1xxxxx - fcvtn. */ - return 2469; + x1000001xx1xxxxx1x101000xx1xxxx0 + smin. */ + return 2650; } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x1000001x11xxx0011100xxxxx1xxxxx - bfcvtn. */ - return 2437; + x1000001xx1xxxxx1x111000xx1xxxx0 + smin. */ + return 2652; } } else { - if (((word >> 20) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx10xx1011100xxxxx1xxxxx - ucvtf. */ - return 2792; - } - else - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx11xx1011100xxxxx1xxxxx - ucvtf. */ - return 2793; - } - } - } - else - { - if (((word >> 17) & 0x1) == 0) - { - if (((word >> 20) & 0x1) == 0) + if (((word >> 12) & 0x1) == 0) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x1000001xx10xx0111100xxxxx1xxxxx - fcvtzu. */ - return 2472; + x1000001xx1xxxxx1x101010xx1xxxx0 + srshl. */ + return 2704; } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x1000001xx11xx0111100xxxxx1xxxxx - fcvtzu. */ - return 2473; - } - } - else - { - if (((word >> 20) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx10xx1111100xxxxx1xxxxx - uqcvt. */ - return 2848; - } - else - { - if (((word >> 6) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx11xx1111100xxxx01xxxxx - uqcvt. */ - return 2849; - } - else - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx11xx1111100xxxx11xxxxx - uqcvtn. */ - return 2850; - } + x1000001xx1xxxxx1x111010xx1xxxx0 + srshl. */ + return 2706; } } } - } - } - else - { - if (((word >> 0) & 0x1) == 0) - { - if (((word >> 8) & 0x1) == 0) - { - if (((word >> 9) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx1xxxxx1x110x00xx1xxxx0 - smin. */ - return 2651; - } - else - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx1xxxxx1x110x10xx1xxxx0 - srshl. */ - return 2705; - } - } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx1xxxxx1x110xx1xx1xxxx0 - fmaxnm. */ - return 2486; - } - } - else - { - if (((word >> 8) & 0x1) == 0) - { - if (((word >> 9) & 0x1) == 0) + if (((word >> 12) & 0x1) == 0) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x1000001xx1xxxxx1x110x00xx1xxxx1 - umin. */ - return 2812; + x1000001xx1xxxxx1x1010x1xx1xxxx0 + fmaxnm. */ + return 2485; } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x1000001xx1xxxxx1x110x10xx1xxxx1 - urshl. */ - return 2856; + x1000001xx1xxxxx1x1110x1xx1xxxx0 + fmaxnm. */ + return 2487; } } - else - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx1xxxxx1x110xx1xx1xxxx1 - fminnm. */ - return 2494; - } } } - } - else - { - if (((word >> 0) & 0x1) == 0) + else { - if (((word >> 8) & 0x1) == 0) + if (((word >> 5) & 0x1) == 0) { - if (((word >> 9) & 0x1) == 0) + if (((word >> 8) & 0x1) == 0) { if (((word >> 12) & 0x1) == 0) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x1000001xx1xxxxx1x101x00xx1xxxx0 - smin. */ - return 2650; + x1000001xx1xxxxx1x1010x0xx0xxxx1 + umax. */ + return 2809; } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x1000001xx1xxxxx1x111x00xx1xxxx0 - smin. */ - return 2652; + x1000001xx1xxxxx1x1110x0xx0xxxx1 + umax. */ + return 2811; } } else @@ -5041,61 +5063,61 @@ aarch64_opcode_lookup_1 (uint32_t word) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x1000001xx1xxxxx1x101x10xx1xxxx0 - srshl. */ - return 2704; + x1000001xx1xxxxx1x1010x1xx0xxxx1 + fmin. */ + return 2489; } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x1000001xx1xxxxx1x111x10xx1xxxx0 - srshl. */ - return 2706; + x1000001xx1xxxxx1x1110x1xx0xxxx1 + fmin. */ + return 2491; } } } else { - if (((word >> 12) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx1xxxxx1x101xx1xx1xxxx0 - fmaxnm. */ - return 2485; - } - else - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx1xxxxx1x111xx1xx1xxxx0 - fmaxnm. */ - return 2487; - } - } - } - else - { - if (((word >> 8) & 0x1) == 0) - { - if (((word >> 9) & 0x1) == 0) + if (((word >> 8) & 0x1) == 0) { - if (((word >> 12) & 0x1) == 0) + if (((word >> 9) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx1xxxxx1x101x00xx1xxxx1 - umin. */ - return 2811; + if (((word >> 12) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xxxxx1x101000xx1xxxx1 + umin. */ + return 2813; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xxxxx1x111000xx1xxxx1 + umin. */ + return 2815; + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx1xxxxx1x111x00xx1xxxx1 - umin. */ - return 2813; + if (((word >> 12) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xxxxx1x101010xx1xxxx1 + urshl. */ + return 2857; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xxxxx1x111010xx1xxxx1 + urshl. */ + return 2859; + } } } else @@ -5104,39 +5126,61 @@ aarch64_opcode_lookup_1 (uint32_t word) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x1000001xx1xxxxx1x101x10xx1xxxx1 - urshl. */ - return 2855; + x1000001xx1xxxxx1x1010x1xx1xxxx1 + fminnm. */ + return 2493; } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x1000001xx1xxxxx1x111x10xx1xxxx1 - urshl. */ - return 2857; + x1000001xx1xxxxx1x1110x1xx1xxxx1 + fminnm. */ + return 2495; } } } - else - { - if (((word >> 12) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx1xxxxx1x101xx1xx1xxxx1 - fminnm. */ - return 2493; - } - else - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx1xxxxx1x111xx1xx1xxxx1 - fminnm. */ - return 2495; - } - } + } + } + } + else + { + if (((word >> 11) & 0x1) == 0) + { + if (((word >> 12) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xxxxx1x1001xxxxxxxxxx + sqdmulh. */ + return 2693; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xxxxx1x1101xxxxxxxxxx + sqdmulh. */ + return 2695; + } + } + else + { + if (((word >> 12) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xxxxx1x1011xxxxxxxxxx + sqdmulh. */ + return 2694; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xxxxx1x1111xxxxxxxxxx + sqdmulh. */ + return 2696; } } } @@ -7934,7 +7978,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 00011001000xxxxxxxxx00xxxxxxxxxx stlurb. */ - return 2946; + return 2950; } else { @@ -7942,7 +7986,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 10011001000xxxxxxxxx00xxxxxxxxxx stlur. */ - return 2954; + return 2958; } } else @@ -7953,7 +7997,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 01011001000xxxxxxxxx00xxxxxxxxxx stlurh. */ - return 2950; + return 2954; } else { @@ -7961,7 +8005,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 11011001000xxxxxxxxx00xxxxxxxxxx stlur. */ - return 2957; + return 2961; } } } @@ -7999,7 +8043,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0000x1xxxxxxxxxx cpyfp. */ - return 3006; + return 3010; } else { @@ -8007,7 +8051,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1000x1xxxxxxxxxx cpyfprn. */ - return 3012; + return 3016; } } else @@ -8018,7 +8062,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0100x1xxxxxxxxxx cpyfpwn. */ - return 3009; + return 3013; } else { @@ -8026,7 +8070,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1100x1xxxxxxxxxx cpyfpn. */ - return 3015; + return 3019; } } } @@ -8040,7 +8084,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0010x1xxxxxxxxxx cpyfprt. */ - return 3030; + return 3034; } else { @@ -8048,7 +8092,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1010x1xxxxxxxxxx cpyfprtrn. */ - return 3036; + return 3040; } } else @@ -8059,7 +8103,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0110x1xxxxxxxxxx cpyfprtwn. */ - return 3033; + return 3037; } else { @@ -8067,7 +8111,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1110x1xxxxxxxxxx cpyfprtn. */ - return 3039; + return 3043; } } } @@ -8084,7 +8128,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0001x1xxxxxxxxxx cpyfpwt. */ - return 3018; + return 3022; } else { @@ -8092,7 +8136,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1001x1xxxxxxxxxx cpyfpwtrn. */ - return 3024; + return 3028; } } else @@ -8103,7 +8147,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0101x1xxxxxxxxxx cpyfpwtwn. */ - return 3021; + return 3025; } else { @@ -8111,7 +8155,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1101x1xxxxxxxxxx cpyfpwtn. */ - return 3027; + return 3031; } } } @@ -8125,7 +8169,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0011x1xxxxxxxxxx cpyfpt. */ - return 3042; + return 3046; } else { @@ -8133,7 +8177,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1011x1xxxxxxxxxx cpyfptrn. */ - return 3048; + return 3052; } } else @@ -8144,7 +8188,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0111x1xxxxxxxxxx cpyfptwn. */ - return 3045; + return 3049; } else { @@ -8152,7 +8196,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1111x1xxxxxxxxxx cpyfptn. */ - return 3051; + return 3055; } } } @@ -8217,7 +8261,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 00011001010xxxxxxxxx00xxxxxxxxxx ldapurb. */ - return 2947; + return 2951; } else { @@ -8225,7 +8269,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 10011001010xxxxxxxxx00xxxxxxxxxx ldapur. */ - return 2955; + return 2959; } } else @@ -8236,7 +8280,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 01011001010xxxxxxxxx00xxxxxxxxxx ldapurh. */ - return 2951; + return 2955; } else { @@ -8244,7 +8288,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 11011001010xxxxxxxxx00xxxxxxxxxx ldapur. */ - return 2958; + return 2962; } } } @@ -8282,7 +8326,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0000x1xxxxxxxxxx cpyfm. */ - return 3007; + return 3011; } else { @@ -8290,7 +8334,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1000x1xxxxxxxxxx cpyfmrn. */ - return 3013; + return 3017; } } else @@ -8301,7 +8345,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0100x1xxxxxxxxxx cpyfmwn. */ - return 3010; + return 3014; } else { @@ -8309,7 +8353,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1100x1xxxxxxxxxx cpyfmn. */ - return 3016; + return 3020; } } } @@ -8323,7 +8367,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0010x1xxxxxxxxxx cpyfmrt. */ - return 3031; + return 3035; } else { @@ -8331,7 +8375,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1010x1xxxxxxxxxx cpyfmrtrn. */ - return 3037; + return 3041; } } else @@ -8342,7 +8386,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0110x1xxxxxxxxxx cpyfmrtwn. */ - return 3034; + return 3038; } else { @@ -8350,7 +8394,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1110x1xxxxxxxxxx cpyfmrtn. */ - return 3040; + return 3044; } } } @@ -8367,7 +8411,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0001x1xxxxxxxxxx cpyfmwt. */ - return 3019; + return 3023; } else { @@ -8375,7 +8419,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1001x1xxxxxxxxxx cpyfmwtrn. */ - return 3025; + return 3029; } } else @@ -8386,7 +8430,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0101x1xxxxxxxxxx cpyfmwtwn. */ - return 3022; + return 3026; } else { @@ -8394,7 +8438,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1101x1xxxxxxxxxx cpyfmwtn. */ - return 3028; + return 3032; } } } @@ -8408,7 +8452,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0011x1xxxxxxxxxx cpyfmt. */ - return 3043; + return 3047; } else { @@ -8416,7 +8460,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1011x1xxxxxxxxxx cpyfmtrn. */ - return 3049; + return 3053; } } else @@ -8427,7 +8471,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0111x1xxxxxxxxxx cpyfmtwn. */ - return 3046; + return 3050; } else { @@ -8435,7 +8479,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1111x1xxxxxxxxxx cpyfmtn. */ - return 3052; + return 3056; } } } @@ -8503,7 +8547,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 00011001100xxxxxxxxx00xxxxxxxxxx ldapursb. */ - return 2949; + return 2953; } else { @@ -8511,7 +8555,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 10011001100xxxxxxxxx00xxxxxxxxxx ldapursw. */ - return 2956; + return 2960; } } else @@ -8520,7 +8564,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1011001100xxxxxxxxx00xxxxxxxxxx ldapursh. */ - return 2953; + return 2957; } } else @@ -8531,7 +8575,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0011001110xxxxxxxxx00xxxxxxxxxx ldapursb. */ - return 2948; + return 2952; } else { @@ -8539,7 +8583,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1011001110xxxxxxxxx00xxxxxxxxxx ldapursh. */ - return 2952; + return 2956; } } } @@ -8601,7 +8645,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0000x1xxxxxxxxxx cpyfe. */ - return 3008; + return 3012; } else { @@ -8609,7 +8653,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0000x1xxxxxxxxxx setp. */ - return 3102; + return 3106; } } else @@ -8620,7 +8664,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx1000x1xxxxxxxxxx cpyfern. */ - return 3014; + return 3018; } else { @@ -8628,7 +8672,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx1000x1xxxxxxxxxx sete. */ - return 3104; + return 3108; } } } @@ -8642,7 +8686,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0100x1xxxxxxxxxx cpyfewn. */ - return 3011; + return 3015; } else { @@ -8650,7 +8694,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0100x1xxxxxxxxxx setm. */ - return 3103; + return 3107; } } else @@ -8659,7 +8703,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0110011x0xxxxx1100x1xxxxxxxxxx cpyfen. */ - return 3017; + return 3021; } } } @@ -8675,7 +8719,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0010x1xxxxxxxxxx cpyfert. */ - return 3032; + return 3036; } else { @@ -8683,7 +8727,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0010x1xxxxxxxxxx setpn. */ - return 3108; + return 3112; } } else @@ -8694,7 +8738,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx1010x1xxxxxxxxxx cpyfertrn. */ - return 3038; + return 3042; } else { @@ -8702,7 +8746,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx1010x1xxxxxxxxxx seten. */ - return 3110; + return 3114; } } } @@ -8716,7 +8760,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0110x1xxxxxxxxxx cpyfertwn. */ - return 3035; + return 3039; } else { @@ -8724,7 +8768,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0110x1xxxxxxxxxx setmn. */ - return 3109; + return 3113; } } else @@ -8733,7 +8777,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0110011x0xxxxx1110x1xxxxxxxxxx cpyfertn. */ - return 3041; + return 3045; } } } @@ -8752,7 +8796,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0001x1xxxxxxxxxx cpyfewt. */ - return 3020; + return 3024; } else { @@ -8760,7 +8804,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0001x1xxxxxxxxxx setpt. */ - return 3105; + return 3109; } } else @@ -8771,7 +8815,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx1001x1xxxxxxxxxx cpyfewtrn. */ - return 3026; + return 3030; } else { @@ -8779,7 +8823,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx1001x1xxxxxxxxxx setet. */ - return 3107; + return 3111; } } } @@ -8793,7 +8837,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0101x1xxxxxxxxxx cpyfewtwn. */ - return 3023; + return 3027; } else { @@ -8801,7 +8845,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0101x1xxxxxxxxxx setmt. */ - return 3106; + return 3110; } } else @@ -8810,7 +8854,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0110011x0xxxxx1101x1xxxxxxxxxx cpyfewtn. */ - return 3029; + return 3033; } } } @@ -8826,7 +8870,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0011x1xxxxxxxxxx cpyfet. */ - return 3044; + return 3048; } else { @@ -8834,7 +8878,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0011x1xxxxxxxxxx setptn. */ - return 3111; + return 3115; } } else @@ -8845,7 +8889,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx1011x1xxxxxxxxxx cpyfetrn. */ - return 3050; + return 3054; } else { @@ -8853,7 +8897,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx1011x1xxxxxxxxxx setetn. */ - return 3113; + return 3117; } } } @@ -8867,7 +8911,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0111x1xxxxxxxxxx cpyfetwn. */ - return 3047; + return 3051; } else { @@ -8875,7 +8919,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0111x1xxxxxxxxxx setmtn. */ - return 3112; + return 3116; } } else @@ -8884,7 +8928,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0110011x0xxxxx1111x1xxxxxxxxxx cpyfetn. */ - return 3053; + return 3057; } } } @@ -9257,7 +9301,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1x11010110xxxx0x01000xxxxxxxxxx abs. */ - return 3131; + return 3135; } else { @@ -9275,7 +9319,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010110xxxxxx11000xxxxxxxxxx smax. */ - return 3134; + return 3138; } } } @@ -9355,7 +9399,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010x00xxxxxx0xx10xxxxxxxxxx setf8. */ - return 2944; + return 2948; } else { @@ -9363,7 +9407,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010x00xxxxxx1xx10xxxxxxxxxx setf16. */ - return 2945; + return 2949; } } else @@ -9470,7 +9514,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010110xxxxxx11010xxxxxxxxxx smin. */ - return 3136; + return 3140; } } } @@ -9486,7 +9530,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010110xxxx0x00110xxxxxxxxxx ctz. */ - return 3133; + return 3137; } else { @@ -9531,7 +9575,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010000xxxxxxxxx01xxxxxxxxxx rmif. */ - return 2943; + return 2947; } else { @@ -9625,7 +9669,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010x10xxxxxx11001xxxxxxxxxx umax. */ - return 3135; + return 3139; } } } @@ -9755,7 +9799,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010xx0xxxxxx11011xxxxxxxxxx umin. */ - return 3137; + return 3141; } } } @@ -9771,7 +9815,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010xx0xxxx0x00111xxxxxxxxxx cnt. */ - return 3132; + return 3136; } else { @@ -10613,7 +10657,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x01x1xxxxx000110xxxxxxxxxx usdot. */ - return 2963; + return 2967; } } } @@ -10687,7 +10731,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x01x1xxxxx000111xxxxxxxxxx sudot. */ - return 2964; + return 2968; } } } @@ -13361,7 +13405,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x0xx0xxxxx011110xxxxxxxxxx usdot. */ - return 2962; + return 2966; } } } @@ -15065,7 +15109,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0100xxx10101xxxxxxxxxxxxx bfcvtnt. */ - return 2991; + return 2995; } } else @@ -15308,7 +15352,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x00x1xxxxxx00xxxxxxxxxxxxx ld1rob. */ - return 2967; + return 2971; } else { @@ -15316,7 +15360,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x01x1xxxxxx00xxxxxxxxxxxxx ld1roh. */ - return 2968; + return 2972; } } else @@ -15548,7 +15592,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0011xxxxx010xxxxxxxxxxxxx bfdot. */ - return 2988; + return 2992; } else { @@ -15569,7 +15613,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx010xx0xxxxxxxxxx bfmlalb. */ - return 2995; + return 2999; } else { @@ -15577,7 +15621,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx010xx1xxxxxxxxxx bfmlalt. */ - return 2994; + return 2998; } } else @@ -15632,7 +15676,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11001x0011xxxxx1x0xxxxxxxxxxxxx bfdot. */ - return 2987; + return 2991; } else { @@ -15644,7 +15688,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx1x0xx0xxxxxxxxxx bfmlalb. */ - return 2993; + return 2997; } else { @@ -15652,7 +15696,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx1x0xx1xxxxxxxxxx bfmlalt. */ - return 2992; + return 2996; } } else @@ -15703,7 +15747,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x00x1xxxxx001xxxxxxxxxxxxx ld1rob. */ - return 2971; + return 2975; } else { @@ -15711,7 +15755,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x01x1xxxxx001xxxxxxxxxxxxx ld1roh. */ - return 2972; + return 2976; } } else @@ -16070,7 +16114,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0101xxxxx111xxxxxxxxxxxxx fmmla. */ - return 2965; + return 2969; } else { @@ -16103,7 +16147,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0011xxxxx111xxxxxxxxxxxxx bfmmla. */ - return 2989; + return 2993; } else { @@ -16133,7 +16177,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx111xxxxxxxxxxxxx fmmla. */ - return 2966; + return 2970; } else { @@ -16262,7 +16306,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000x00xxxxxxxxxx zip1. */ - return 2975; + return 2979; } else { @@ -16272,7 +16316,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000010xxxxxxxxxx uzp1. */ - return 2977; + return 2981; } else { @@ -16280,7 +16324,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000110xxxxxxxxxx trn1. */ - return 2979; + return 2983; } } } @@ -16292,7 +16336,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000x01xxxxxxxxxx zip2. */ - return 2976; + return 2980; } else { @@ -16302,7 +16346,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000011xxxxxxxxxx uzp2. */ - return 2978; + return 2982; } else { @@ -16310,7 +16354,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000111xxxxxxxxxx trn2. */ - return 2980; + return 2984; } } } @@ -17369,7 +17413,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x1000xxxxx100110xxxxxxxxxx smmla. */ - return 2959; + return 2963; } else { @@ -17377,7 +17421,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x1100xxxxx100110xxxxxxxxxx usmmla. */ - return 2961; + return 2965; } } else @@ -17386,7 +17430,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x1x10xxxxx100110xxxxxxxxxx ummla. */ - return 2960; + return 2964; } } } @@ -18882,7 +18926,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x10x1xxxxx000xxxxxxxxxxxxx ld1row. */ - return 2969; + return 2973; } else { @@ -18890,7 +18934,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x11x1xxxxx000xxxxxxxxxxxxx ld1rod. */ - return 2970; + return 2974; } } } @@ -19264,7 +19308,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x10x1xxxxx001xxxxxxxxxxxxx ld1row. */ - return 2973; + return 2977; } else { @@ -19272,7 +19316,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x11x1xxxxx001xxxxxxxxxxxxx ld1rod. */ - return 2974; + return 2978; } } } @@ -19633,7 +19677,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x000xxxxx10xxx whilege. */ - return 2875; + return 2879; } else { @@ -19641,7 +19685,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x000xxxxx11xxx whilegt. */ - return 2876; + return 2880; } } else @@ -19685,7 +19729,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x010xxxxx10xxx whilehs. */ - return 2878; + return 2882; } else { @@ -19693,7 +19737,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x010xxxxx11xxx whilehi. */ - return 2877; + return 2881; } } else @@ -19740,7 +19784,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x001xxxxx10xxx whilelt. */ - return 2882; + return 2886; } else { @@ -19748,7 +19792,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x001xxxxx11xxx whilele. */ - return 2879; + return 2883; } } else @@ -19792,7 +19836,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x011xxxxx10xxx whilelo. */ - return 2880; + return 2884; } else { @@ -19800,7 +19844,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x011xxxxx11xxx whilels. */ - return 2881; + return 2885; } } else @@ -20926,7 +20970,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x110001x10101xxxxxxxxxxxxx bfcvt. */ - return 2990; + return 2994; } } else @@ -22287,7 +22331,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1010100xxxxxxxxxxxxxxxxxxx1xxxx bc.c. */ - return 3126; + return 3130; } else { @@ -22867,7 +22911,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0000xxxxxxxxxxxx cpyp. */ - return 3054; + return 3058; } else { @@ -22875,7 +22919,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0000xxxxxxxxxxxx cpye. */ - return 3056; + return 3060; } } else @@ -22886,7 +22930,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1000xxxxxxxxxxxx cpyprn. */ - return 3060; + return 3064; } else { @@ -22894,7 +22938,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1000xxxxxxxxxxxx cpyern. */ - return 3062; + return 3066; } } } @@ -22908,7 +22952,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0100xxxxxxxxxxxx cpypwn. */ - return 3057; + return 3061; } else { @@ -22916,7 +22960,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0100xxxxxxxxxxxx cpyewn. */ - return 3059; + return 3063; } } else @@ -22927,7 +22971,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1100xxxxxxxxxxxx cpypn. */ - return 3063; + return 3067; } else { @@ -22935,7 +22979,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1100xxxxxxxxxxxx cpyen. */ - return 3065; + return 3069; } } } @@ -22952,7 +22996,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0010xxxxxxxxxxxx cpyprt. */ - return 3078; + return 3082; } else { @@ -22960,7 +23004,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0010xxxxxxxxxxxx cpyert. */ - return 3080; + return 3084; } } else @@ -22971,7 +23015,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1010xxxxxxxxxxxx cpyprtrn. */ - return 3084; + return 3088; } else { @@ -22979,7 +23023,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1010xxxxxxxxxxxx cpyertrn. */ - return 3086; + return 3090; } } } @@ -22993,7 +23037,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0110xxxxxxxxxxxx cpyprtwn. */ - return 3081; + return 3085; } else { @@ -23001,7 +23045,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0110xxxxxxxxxxxx cpyertwn. */ - return 3083; + return 3087; } } else @@ -23012,7 +23056,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1110xxxxxxxxxxxx cpyprtn. */ - return 3087; + return 3091; } else { @@ -23020,7 +23064,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1110xxxxxxxxxxxx cpyertn. */ - return 3089; + return 3093; } } } @@ -23040,7 +23084,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0001xxxxxxxxxxxx cpypwt. */ - return 3066; + return 3070; } else { @@ -23048,7 +23092,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0001xxxxxxxxxxxx cpyewt. */ - return 3068; + return 3072; } } else @@ -23059,7 +23103,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1001xxxxxxxxxxxx cpypwtrn. */ - return 3072; + return 3076; } else { @@ -23067,7 +23111,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1001xxxxxxxxxxxx cpyewtrn. */ - return 3074; + return 3078; } } } @@ -23081,7 +23125,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0101xxxxxxxxxxxx cpypwtwn. */ - return 3069; + return 3073; } else { @@ -23089,7 +23133,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0101xxxxxxxxxxxx cpyewtwn. */ - return 3071; + return 3075; } } else @@ -23100,7 +23144,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1101xxxxxxxxxxxx cpypwtn. */ - return 3075; + return 3079; } else { @@ -23108,7 +23152,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1101xxxxxxxxxxxx cpyewtn. */ - return 3077; + return 3081; } } } @@ -23125,7 +23169,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0011xxxxxxxxxxxx cpypt. */ - return 3090; + return 3094; } else { @@ -23133,7 +23177,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0011xxxxxxxxxxxx cpyet. */ - return 3092; + return 3096; } } else @@ -23144,7 +23188,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1011xxxxxxxxxxxx cpyptrn. */ - return 3096; + return 3100; } else { @@ -23152,7 +23196,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1011xxxxxxxxxxxx cpyetrn. */ - return 3098; + return 3102; } } } @@ -23166,7 +23210,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0111xxxxxxxxxxxx cpyptwn. */ - return 3093; + return 3097; } else { @@ -23174,7 +23218,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0111xxxxxxxxxxxx cpyetwn. */ - return 3095; + return 3099; } } else @@ -23185,7 +23229,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1111xxxxxxxxxxxx cpyptn. */ - return 3099; + return 3103; } else { @@ -23193,7 +23237,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1111xxxxxxxxxxxx cpyetn. */ - return 3101; + return 3105; } } } @@ -23227,7 +23271,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0000xxxxxxxxxxxx cpym. */ - return 3055; + return 3059; } else { @@ -23235,7 +23279,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0000xxxxxxxxxxxx setgp. */ - return 3114; + return 3118; } } else @@ -23246,7 +23290,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx1000xxxxxxxxxxxx cpymrn. */ - return 3061; + return 3065; } else { @@ -23254,7 +23298,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx1000xxxxxxxxxxxx setge. */ - return 3116; + return 3120; } } } @@ -23268,7 +23312,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0100xxxxxxxxxxxx cpymwn. */ - return 3058; + return 3062; } else { @@ -23276,7 +23320,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0100xxxxxxxxxxxx setgm. */ - return 3115; + return 3119; } } else @@ -23285,7 +23329,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011101x1xxxxxx1100xxxxxxxxxxxx cpymn. */ - return 3064; + return 3068; } } } @@ -23301,7 +23345,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0010xxxxxxxxxxxx cpymrt. */ - return 3079; + return 3083; } else { @@ -23309,7 +23353,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0010xxxxxxxxxxxx setgpn. */ - return 3120; + return 3124; } } else @@ -23320,7 +23364,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx1010xxxxxxxxxxxx cpymrtrn. */ - return 3085; + return 3089; } else { @@ -23328,7 +23372,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx1010xxxxxxxxxxxx setgen. */ - return 3122; + return 3126; } } } @@ -23342,7 +23386,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0110xxxxxxxxxxxx cpymrtwn. */ - return 3082; + return 3086; } else { @@ -23350,7 +23394,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0110xxxxxxxxxxxx setgmn. */ - return 3121; + return 3125; } } else @@ -23359,7 +23403,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011101x1xxxxxx1110xxxxxxxxxxxx cpymrtn. */ - return 3088; + return 3092; } } } @@ -23378,7 +23422,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0001xxxxxxxxxxxx cpymwt. */ - return 3067; + return 3071; } else { @@ -23386,7 +23430,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0001xxxxxxxxxxxx setgpt. */ - return 3117; + return 3121; } } else @@ -23397,7 +23441,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx1001xxxxxxxxxxxx cpymwtrn. */ - return 3073; + return 3077; } else { @@ -23405,7 +23449,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx1001xxxxxxxxxxxx setget. */ - return 3119; + return 3123; } } } @@ -23419,7 +23463,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0101xxxxxxxxxxxx cpymwtwn. */ - return 3070; + return 3074; } else { @@ -23427,7 +23471,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0101xxxxxxxxxxxx setgmt. */ - return 3118; + return 3122; } } else @@ -23436,7 +23480,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011101x1xxxxxx1101xxxxxxxxxxxx cpymwtn. */ - return 3076; + return 3080; } } } @@ -23452,7 +23496,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0011xxxxxxxxxxxx cpymt. */ - return 3091; + return 3095; } else { @@ -23460,7 +23504,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0011xxxxxxxxxxxx setgptn. */ - return 3123; + return 3127; } } else @@ -23471,7 +23515,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx1011xxxxxxxxxxxx cpymtrn. */ - return 3097; + return 3101; } else { @@ -23479,7 +23523,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx1011xxxxxxxxxxxx setgetn. */ - return 3125; + return 3129; } } } @@ -23493,7 +23537,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0111xxxxxxxxxxxx cpymtwn. */ - return 3094; + return 3098; } else { @@ -23501,7 +23545,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0111xxxxxxxxxxxx setgmtn. */ - return 3124; + return 3128; } } else @@ -23510,7 +23554,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011101x1xxxxxx1111xxxxxxxxxxxx cpymtn. */ - return 3100; + return 3104; } } } @@ -23677,7 +23721,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110xx0xxxxx1x1001xxxxxxxxxx smmla. */ - return 2981; + return 2985; } } } @@ -23710,7 +23754,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110xx0xxxxx1x0101xxxxxxxxxx sdot. */ - return 2907; + return 2911; } } else @@ -23784,7 +23828,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110xx0xxxxx1x1011xxxxxxxxxx usmmla. */ - return 2983; + return 2987; } } } @@ -23817,7 +23861,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110xx0xxxxx1x0111xxxxxxxxxx usdot. */ - return 2984; + return 2988; } } else @@ -23864,7 +23908,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110000xxxxxxxxxxxxxxxxxxxxx eor3. */ - return 2914; + return 2918; } else { @@ -23872,7 +23916,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110100xxxxxxxxxxxxxxxxxxxxx xar. */ - return 2916; + return 2920; } } else @@ -23883,7 +23927,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110x10xxxxx0xxxxxxxxxxxxxxx sm3ss1. */ - return 2918; + return 2922; } else { @@ -23897,7 +23941,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110010xxxxx1xxx00xxxxxxxxxx sm3tt1a. */ - return 2919; + return 2923; } else { @@ -23905,7 +23949,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110110xxxxx1xxx00xxxxxxxxxx sha512su0. */ - return 2912; + return 2916; } } else @@ -23914,7 +23958,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110x10xxxxx1xxx10xxxxxxxxxx sm3tt2a. */ - return 2921; + return 2925; } } else @@ -23927,7 +23971,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110010xxxxx1xxx01xxxxxxxxxx sm3tt1b. */ - return 2920; + return 2924; } else { @@ -23935,7 +23979,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110110xxxxx1xxx01xxxxxxxxxx sm4e. */ - return 2925; + return 2929; } } else @@ -23944,7 +23988,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110x10xxxxx1xxx11xxxxxxxxxx sm3tt2b. */ - return 2922; + return 2926; } } } @@ -24125,7 +24169,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx101110xx0xxxxx100101xxxxxxxxxx udot. */ - return 2906; + return 2910; } } else @@ -24156,7 +24200,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx101110xx0xxxxx101x01xxxxxxxxxx ummla. */ - return 2982; + return 2986; } else { @@ -24175,7 +24219,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx101110xx0xxxxx1x1011xxxxxxxxxx bfmmla. */ - return 2998; + return 3002; } else { @@ -24185,7 +24229,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx1011100x0xxxxx1x1111xxxxxxxxxx bfdot. */ - return 2996; + return 3000; } else { @@ -24195,7 +24239,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x01011101x0xxxxx1x1111xxxxxxxxxx bfmlalb. */ - return 3003; + return 3007; } else { @@ -24203,7 +24247,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11011101x0xxxxx1x1111xxxxxxxxxx bfmlalt. */ - return 3002; + return 3006; } } } @@ -24787,7 +24831,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000011101x1xxxx1011010xxxxxxxxxx bfcvtn. */ - return 2999; + return 3003; } else { @@ -24795,7 +24839,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010011101x1xxxx1011010xxxxxxxxxx bfcvtn2. */ - return 3000; + return 3004; } } } @@ -25113,7 +25157,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110xx1xxxxx0xxxxxxxxxxxxxxx bcax. */ - return 2917; + return 2921; } } else @@ -25724,7 +25768,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 11001110xx1xxxxx100000xxxxxxxxxx sha512h. */ - return 2910; + return 2914; } } } @@ -25776,7 +25820,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 11001110xx1xxxxx110000xxxxxxxxxx sm3partw1. */ - return 2923; + return 2927; } } } @@ -26019,7 +26063,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110xx1xxxxx100010xxxxxxxxxx sha512su1. */ - return 2913; + return 2917; } } else @@ -26095,7 +26139,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x0011100x1xxxxx110010xxxxxxxxxx sm4ekey. */ - return 2926; + return 2930; } } else @@ -26921,7 +26965,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110xx1xxxxx100001xxxxxxxxxx sha512h2. */ - return 2911; + return 2915; } } else @@ -26953,7 +26997,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x0011100x1xxxxx110001xxxxxxxxxx sm3partw2. */ - return 2924; + return 2928; } } else @@ -27193,7 +27237,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110xx1xxxxx100011xxxxxxxxxx rax1. */ - return 2915; + return 2919; } } else @@ -27225,7 +27269,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x01011100x1xxxxx110011xxxxxxxxxx fmlal2. */ - return 2929; + return 2933; } else { @@ -27233,7 +27277,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11011100x1xxxxx110011xxxxxxxxxx fmlal2. */ - return 2933; + return 2937; } } } @@ -27255,7 +27299,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x01011101x1xxxxx110011xxxxxxxxxx fmlsl2. */ - return 2930; + return 2934; } else { @@ -27263,7 +27307,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11011101x1xxxxx110011xxxxxxxxxx fmlsl2. */ - return 2934; + return 2938; } } } @@ -27302,7 +27346,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x00011100x1xxxxx111011xxxxxxxxxx fmlal. */ - return 2927; + return 2931; } else { @@ -27310,7 +27354,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10011100x1xxxxx111011xxxxxxxxxx fmlal. */ - return 2931; + return 2935; } } else @@ -27332,7 +27376,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x00011101x1xxxxx111011xxxxxxxxxx fmlsl. */ - return 2928; + return 2932; } else { @@ -27340,7 +27384,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10011101x1xxxxx111011xxxxxxxxxx fmlsl. */ - return 2932; + return 2936; } } else @@ -29148,7 +29192,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0001111xxxxxxxx0000x0xxxxxxxxxx fmlal. */ - return 2935; + return 2939; } else { @@ -29156,7 +29200,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1001111xxxxxxxx0000x0xxxxxxxxxx fmlal. */ - return 2939; + return 2943; } } else @@ -29178,7 +29222,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0001111xxxxxxxx0100x0xxxxxxxxxx fmlsl. */ - return 2936; + return 2940; } else { @@ -29186,7 +29230,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1001111xxxxxxxx0100x0xxxxxxxxxx fmlsl. */ - return 2940; + return 2944; } } else @@ -29692,7 +29736,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0101111xxxxxxxx1000x0xxxxxxxxxx fmlal2. */ - return 2937; + return 2941; } else { @@ -29700,7 +29744,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1101111xxxxxxxx1000x0xxxxxxxxxx fmlal2. */ - return 2941; + return 2945; } } } @@ -29722,7 +29766,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0101111xxxxxxxx1100x0xxxxxxxxxx fmlsl2. */ - return 2938; + return 2942; } else { @@ -29730,7 +29774,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1101111xxxxxxxx1100x0xxxxxxxxxx fmlsl2. */ - return 2942; + return 2946; } } } @@ -29786,7 +29830,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx001111xxxxxxxx1110x0xxxxxxxxxx sdot. */ - return 2909; + return 2913; } else { @@ -29794,7 +29838,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx101111xxxxxxxx1110x0xxxxxxxxxx udot. */ - return 2908; + return 2912; } } } @@ -29897,7 +29941,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx00111100xxxxxx1111x0xxxxxxxxxx sudot. */ - return 2986; + return 2990; } else { @@ -29905,7 +29949,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx00111110xxxxxx1111x0xxxxxxxxxx usdot. */ - return 2985; + return 2989; } } else @@ -29916,7 +29960,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx00111101xxxxxx1111x0xxxxxxxxxx bfdot. */ - return 2997; + return 3001; } else { @@ -29926,7 +29970,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x000111111xxxxxx1111x0xxxxxxxxxx bfmlalb. */ - return 3005; + return 3009; } else { @@ -29934,7 +29978,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x100111111xxxxxx1111x0xxxxxxxxxx bfmlalt. */ - return 3004; + return 3008; } } } @@ -30462,11 +30506,11 @@ aarch64_find_next_opcode (const aarch64_opcode *opcode) case 2407: value = 2412; break; /* st1q --> st1q. */ case 2412: return NULL; /* st1q --> NULL. */ case 12: value = 19; break; /* add --> addg. */ - case 19: value = 3127; break; /* addg --> smax. */ - case 3127: value = 3128; break; /* smax --> umax. */ - case 3128: value = 3129; break; /* umax --> smin. */ - case 3129: value = 3130; break; /* smin --> umin. */ - case 3130: return NULL; /* umin --> NULL. */ + case 19: value = 3131; break; /* addg --> smax. */ + case 3131: value = 3132; break; /* smax --> umax. */ + case 3132: value = 3133; break; /* umax --> smin. */ + case 3133: value = 3134; break; /* smin --> umin. */ + case 3134: return NULL; /* umin --> NULL. */ case 16: value = 20; break; /* sub --> subg. */ case 20: return NULL; /* subg --> NULL. */ case 971: value = 975; break; /* stnp --> stp. */ @@ -30624,8 +30668,8 @@ aarch64_find_next_opcode (const aarch64_opcode *opcode) case 824: return NULL; /* fsqrt --> NULL. */ case 832: value = 833; break; /* frintz --> frintz. */ case 833: return NULL; /* frintz --> NULL. */ - case 825: value = 3001; break; /* fcvt --> bfcvt. */ - case 3001: return NULL; /* bfcvt --> NULL. */ + case 825: value = 3005; break; /* fcvt --> bfcvt. */ + case 3005: return NULL; /* bfcvt --> NULL. */ case 834: value = 835; break; /* frinta --> frinta. */ case 835: return NULL; /* frinta --> NULL. */ case 836: value = 837; break; /* frintx --> frintx. */ diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index a6f5747c417..e44ad1622c8 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -5722,6 +5722,8 @@ const struct aarch64_opcode aarch64_opcode_table[] = SME2_INSN ("sumlall", 0xc1108030, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off1x4, SME_Znx4, SME_Zm_INDEX4_1), OP_SVE_SBB, F_OD (4), 0), SME2_INSN ("sumlall", 0xc1200014, 0xfff09c1e, sme_misc, 0, OP3 (SME_ZA_array_off1x4, SVE_ZnxN, SME_Zm), OP_SVE_SBB, F_OD (2), 0), SME2_INSN ("sumlall", 0xc1300014, 0xfff09c1e, sme_misc, 0, OP3 (SME_ZA_array_off1x4, SVE_ZnxN, SME_Zm), OP_SVE_SBB, F_OD (4), 0), + SME2_INSN ("sunpk", 0xc125e000, 0xff3ffc01, sme_size_22_hsd, 0, OP2 (SME_Zdnx2, SVE_Zn), OP_SVE_VV_HSD_BHS, 0, 0), + SME2_INSN ("sunpk", 0xc135e000, 0xff3ffc23, sme_size_22_hsd, 0, OP2 (SME_Zdnx4, SME_Znx2), OP_SVE_VV_HSD_BHS, 0, 0), SME2_INSN ("suvdot", 0xc1508038, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX2), OP_SVE_SBB, F_OD (4), 0), SME2_INSN ("svdot", 0xc1500020, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX2), OP_SVE_SHH, F_OD (2), 0), SME2_INSN ("svdot", 0xc1508020, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX2), OP_SVE_SBB, F_OD (4), 0), @@ -5808,6 +5810,8 @@ const struct aarch64_opcode aarch64_opcode_table[] = SME2_INSN ("usmlall", 0xc1a00004, 0xffe19c3e, sme_misc, 0, OP3 (SME_ZA_array_off1x4, SME_Znx2, SME_Zmx2), OP_SVE_SBB, F_OD (2), 0), SME2_INSN ("usmlall", 0xc1a10004, 0xffe39c7e, sme_misc, 0, OP3 (SME_ZA_array_off1x4, SME_Znx4, SME_Zmx4), OP_SVE_SBB, F_OD (4), 0), SME2_INSN ("usvdot", 0xc1508028, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX2), OP_SVE_SBB, F_OD (4), 0), + SME2_INSN ("uunpk", 0xc125e001, 0xff3ffc01, sme_size_22_hsd, 0, OP2 (SME_Zdnx2, SVE_Zn), OP_SVE_VV_HSD_BHS, 0, 0), + SME2_INSN ("uunpk", 0xc135e001, 0xff3ffc23, sme_size_22_hsd, 0, OP2 (SME_Zdnx4, SME_Znx2), OP_SVE_VV_HSD_BHS, 0, 0), SME2_INSN ("uvdot", 0xc1500030, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX2), OP_SVE_SHH, F_OD (2), 0), SME2_INSN ("uvdot", 0xc1508030, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX2), OP_SVE_SBB, F_OD (4), 0), SME2_INSN ("whilege", 0x25204010, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0), From patchwork Thu Mar 30 10:26:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 77092 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1040417vqo; Thu, 30 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Received: from e121540-lin.manchester.arm.com (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 227CA3F663; Thu, 30 Mar 2023 03:27:12 -0700 (PDT) To: binutils@sourceware.org Cc: Richard Sandiford Subject: [PATCH 25/31] aarch64: Add the SME2 UZP and ZIP instructions Date: Thu, 30 Mar 2023 11:26:40 +0100 Message-Id: <20230330102646.3327818-26-richard.sandiford@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230330102646.3327818-1-richard.sandiford@arm.com> References: <20230330102646.3327818-1-richard.sandiford@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-31.5 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KAM_LOTSOFHASH, SCC_5_SHORT_WORD_LINES, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Richard Sandiford via Binutils From: Richard Sandiford Reply-To: Richard Sandiford Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761790460621821350?= X-GMAIL-MSGID: =?utf-8?q?1761790460621821350?= This patch adds UZP and ZIP, which combine UZP{1,2} and ZIP{1,2} into single instructions. --- gas/testsuite/gas/aarch64/sme2-30-invalid.d | 3 + gas/testsuite/gas/aarch64/sme2-30-invalid.l | 29 + gas/testsuite/gas/aarch64/sme2-30-invalid.s | 18 + gas/testsuite/gas/aarch64/sme2-30-noarch.d | 3 + gas/testsuite/gas/aarch64/sme2-30-noarch.l | 91 +++ gas/testsuite/gas/aarch64/sme2-30.d | 99 +++ gas/testsuite/gas/aarch64/sme2-30.s | 109 +++ opcodes/aarch64-dis-2.c | 764 +++++++++++--------- opcodes/aarch64-tbl.h | 12 + 9 files changed, 790 insertions(+), 338 deletions(-) create mode 100644 gas/testsuite/gas/aarch64/sme2-30-invalid.d create mode 100644 gas/testsuite/gas/aarch64/sme2-30-invalid.l create mode 100644 gas/testsuite/gas/aarch64/sme2-30-invalid.s create mode 100644 gas/testsuite/gas/aarch64/sme2-30-noarch.d create mode 100644 gas/testsuite/gas/aarch64/sme2-30-noarch.l create mode 100644 gas/testsuite/gas/aarch64/sme2-30.d create mode 100644 gas/testsuite/gas/aarch64/sme2-30.s diff --git a/gas/testsuite/gas/aarch64/sme2-30-invalid.d b/gas/testsuite/gas/aarch64/sme2-30-invalid.d new file mode 100644 index 00000000000..535abe3f490 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-30-invalid.d @@ -0,0 +1,3 @@ +#as: -march=armv8-a +#source: sme2-30-invalid.s +#error_output: sme2-30-invalid.l diff --git a/gas/testsuite/gas/aarch64/sme2-30-invalid.l b/gas/testsuite/gas/aarch64/sme2-30-invalid.l new file mode 100644 index 00000000000..6805ddba39c --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-30-invalid.l @@ -0,0 +1,29 @@ +[^ :]+: Assembler messages: +[^ :]+:[0-9]+: Error: expected '{' at operand 1 -- `uzp 0,z0\.b,z0\.b' +[^ :]+:[0-9]+: Error: expected a register or register list at operand 2 -- `uzp {z0\.b-z1\.b},0,z0\.b' +[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `uzp {z0\.b-z1\.b},z0\.b,0' +[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `uzp {z1\.b-z2\.b},z0\.b,z0\.b' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 1 -- `uzp {z0\.b-z2\.b},z0\.b,z0\.b' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 1 -- `uzp {z0\.b-z3\.b},z0\.b,z0\.b' +[^ :]+:[0-9]+: Error: unexpected characters following instruction at operand 2 -- `uzp {z0\.b-z1\.b},{z0\.b-z1\.b},{z0\.b,z1\.b}' +[^ :]+:[0-9]+: Error: operand mismatch -- `uzp {z0\.h-z1\.h},z0\.b,z0\.b' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: uzp {z0\.b-z1\.b}, z0\.b, z0\.b +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: uzp {z0\.h-z1\.h}, z0\.h, z0\.h +[^ :]+:[0-9]+: Info: uzp {z0\.s-z1\.s}, z0\.s, z0\.s +[^ :]+:[0-9]+: Info: uzp {z0\.d-z1\.d}, z0\.d, z0\.d +[^ :]+:[0-9]+: Error: operand mismatch -- `uzp {z0\.q-z3\.q},z0\.b,z0\.b' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: uzp {z0\.b-z3\.b}, z0\.b, z0\.b +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: uzp {z0\.h-z3\.h}, z0\.h, z0\.h +[^ :]+:[0-9]+: Info: uzp {z0\.s-z3\.s}, z0\.s, z0\.s +[^ :]+:[0-9]+: Info: uzp {z0\.d-z3\.d}, z0\.d, z0\.d +[^ :]+:[0-9]+: Error: unexpected characters following instruction at operand 2 -- `uzp {z0\.b-z3\.b},{z0\.b-z1\.b},{z2\.b-z3\.b}' +[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `uzp {z1\.b-z4\.b},{z0\.b-z3\.b}' +[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `uzp {z2\.b-z5\.b},{z0\.b-z3\.b}' +[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `uzp {z3\.b-z6\.b},{z0\.b-z3\.b}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `uzp {z0\.b-z3\.b},{z1\.b-z4\.b}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `uzp {z0\.b-z3\.b},{z2\.b-z5\.b}' +[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `uzp {z0\.b-z3\.b},{z3\.b-z6\.b}' diff --git a/gas/testsuite/gas/aarch64/sme2-30-invalid.s b/gas/testsuite/gas/aarch64/sme2-30-invalid.s new file mode 100644 index 00000000000..2d3dd1b2604 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-30-invalid.s @@ -0,0 +1,18 @@ + uzp 0, z0.b, z0.b + uzp { z0.b - z1.b }, 0, z0.b + uzp { z0.b - z1.b }, z0.b, 0 + + uzp { z1.b - z2.b }, z0.b, z0.b + uzp { z0.b - z2.b }, z0.b, z0.b + uzp { z0.b - z3.b }, z0.b, z0.b + uzp { z0.b - z1.b }, { z0.b - z1.b }, { z0.b, z1.b } + uzp { z0.h - z1.h }, z0.b, z0.b + uzp { z0.q - z3.q }, z0.b, z0.b + + uzp { z0.b - z3.b }, { z0.b - z1.b }, { z2.b - z3.b } + uzp { z1.b - z4.b }, { z0.b - z3.b } + uzp { z2.b - z5.b }, { z0.b - z3.b } + uzp { z3.b - z6.b }, { z0.b - z3.b } + uzp { z0.b - z3.b }, { z1.b - z4.b } + uzp { z0.b - z3.b }, { z2.b - z5.b } + uzp { z0.b - z3.b }, { z3.b - z6.b } diff --git a/gas/testsuite/gas/aarch64/sme2-30-noarch.d b/gas/testsuite/gas/aarch64/sme2-30-noarch.d new file mode 100644 index 00000000000..c58d102b75b --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-30-noarch.d @@ -0,0 +1,3 @@ +#as: -march=armv8-a+sme +#source: sme2-30.s +#error_output: sme2-30-noarch.l diff --git a/gas/testsuite/gas/aarch64/sme2-30-noarch.l b/gas/testsuite/gas/aarch64/sme2-30-noarch.l new file mode 100644 index 00000000000..e3ddd704860 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-30-noarch.l @@ -0,0 +1,91 @@ +[^ :]+: Assembler messages: +[^ :]+:[0-9]+: Error: selected processor does not support `uzp {z0\.b-z1\.b},z0\.b,z0\.b' +[^ :]+:[0-9]+: Error: selected processor does not support `uzp {z30\.b-z31\.b},z0\.b,z0\.b' +[^ :]+:[0-9]+: Error: selected processor does not support `uzp {z0\.b-z1\.b},z31\.b,z0\.b' +[^ :]+:[0-9]+: Error: selected processor does not support `uzp {z0\.b-z1\.b},z0\.b,z31\.b' +[^ :]+:[0-9]+: Error: selected processor does not support `uzp {z18\.b-z19\.b},z11\.b,z25\.b' +[^ :]+:[0-9]+: Error: selected processor does not support `uzp {z0\.h-z1\.h},z0\.h,z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `uzp {z30\.h-z31\.h},z0\.h,z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `uzp {z0\.h-z1\.h},z31\.h,z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `uzp {z0\.h-z1\.h},z0\.h,z31\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `uzp {z6\.h-z7\.h},z8\.h,z22\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `uzp {z0\.s-z1\.s},z0\.s,z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `uzp {z30\.s-z31\.s},z0\.s,z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `uzp {z0\.s-z1\.s},z31\.s,z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `uzp {z0\.s-z1\.s},z0\.s,z31\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `uzp {z24\.s-z25\.s},z19\.s,z2\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `uzp {z0\.d-z1\.d},z0\.d,z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `uzp {z30\.d-z31\.d},z0\.d,z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `uzp {z0\.d-z1\.d},z31\.d,z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `uzp {z0\.d-z1\.d},z0\.d,z31\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `uzp {z2\.d-z3\.d},z29\.d,z5\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `uzp {z0\.q-z1\.q},z0\.q,z0\.q' +[^ :]+:[0-9]+: Error: selected processor does not support `uzp {z30\.q-z31\.q},z0\.q,z0\.q' +[^ :]+:[0-9]+: Error: selected processor does not support `uzp {z0\.q-z1\.q},z31\.q,z0\.q' +[^ :]+:[0-9]+: Error: selected processor does not support `uzp {z0\.q-z1\.q},z0\.q,z31\.q' +[^ :]+:[0-9]+: Error: selected processor does not support `uzp {z14\.q-z15\.q},z24\.q,z9\.q' +[^ :]+:[0-9]+: Error: selected processor does not support `uzp {z0\.b-z3\.b},{z0\.b-z3\.b}' +[^ :]+:[0-9]+: Error: selected processor does not support `uzp {z28\.b-z31\.b},{z0\.b-z3\.b}' +[^ :]+:[0-9]+: Error: selected processor does not support `uzp {z0\.b-z3\.b},{z28\.b-z31\.b}' +[^ :]+:[0-9]+: Error: selected processor does not support `uzp {z4\.b-z7\.b},{z24\.b-z27\.b}' +[^ :]+:[0-9]+: Error: selected processor does not support `uzp {z0\.h-z3\.h},{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `uzp {z28\.h-z31\.h},{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `uzp {z0\.h-z3\.h},{z28\.h-z31\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `uzp {z16\.h-z19\.h},{z8\.h-z11\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `uzp {z0\.s-z3\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `uzp {z28\.s-z31\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `uzp {z0\.s-z3\.s},{z28\.s-z31\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `uzp {z20\.s-z23\.s},{z12\.s-z15\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `uzp {z0\.d-z3\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `uzp {z28\.d-z31\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `uzp {z0\.d-z3\.d},{z28\.d-z31\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `uzp {z8\.d-z11\.d},{z16\.d-z19\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `uzp {z0\.q-z3\.q},{z0\.q-z3\.q}' +[^ :]+:[0-9]+: Error: selected processor does not support `uzp {z28\.q-z31\.q},{z0\.q-z3\.q}' +[^ :]+:[0-9]+: Error: selected processor does not support `uzp {z0\.q-z3\.q},{z28\.q-z31\.q}' +[^ :]+:[0-9]+: Error: selected processor does not support `uzp {z12\.q-z15\.q},{z4\.q-z7\.q}' +[^ :]+:[0-9]+: Error: selected processor does not support `zip {z0\.b-z1\.b},z0\.b,z0\.b' +[^ :]+:[0-9]+: Error: selected processor does not support `zip {z30\.b-z31\.b},z0\.b,z0\.b' +[^ :]+:[0-9]+: Error: selected processor does not support `zip {z0\.b-z1\.b},z31\.b,z0\.b' +[^ :]+:[0-9]+: Error: selected processor does not support `zip {z0\.b-z1\.b},z0\.b,z31\.b' +[^ :]+:[0-9]+: Error: selected processor does not support `zip {z18\.b-z19\.b},z11\.b,z25\.b' +[^ :]+:[0-9]+: Error: selected processor does not support `zip {z0\.h-z1\.h},z0\.h,z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `zip {z30\.h-z31\.h},z0\.h,z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `zip {z0\.h-z1\.h},z31\.h,z0\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `zip {z0\.h-z1\.h},z0\.h,z31\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `zip {z6\.h-z7\.h},z8\.h,z22\.h' +[^ :]+:[0-9]+: Error: selected processor does not support `zip {z0\.s-z1\.s},z0\.s,z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `zip {z30\.s-z31\.s},z0\.s,z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `zip {z0\.s-z1\.s},z31\.s,z0\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `zip {z0\.s-z1\.s},z0\.s,z31\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `zip {z24\.s-z25\.s},z19\.s,z2\.s' +[^ :]+:[0-9]+: Error: selected processor does not support `zip {z0\.d-z1\.d},z0\.d,z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `zip {z30\.d-z31\.d},z0\.d,z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `zip {z0\.d-z1\.d},z31\.d,z0\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `zip {z0\.d-z1\.d},z0\.d,z31\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `zip {z2\.d-z3\.d},z29\.d,z5\.d' +[^ :]+:[0-9]+: Error: selected processor does not support `zip {z0\.q-z1\.q},z0\.q,z0\.q' +[^ :]+:[0-9]+: Error: selected processor does not support `zip {z30\.q-z31\.q},z0\.q,z0\.q' +[^ :]+:[0-9]+: Error: selected processor does not support `zip {z0\.q-z1\.q},z31\.q,z0\.q' +[^ :]+:[0-9]+: Error: selected processor does not support `zip {z0\.q-z1\.q},z0\.q,z31\.q' +[^ :]+:[0-9]+: Error: selected processor does not support `zip {z14\.q-z15\.q},z24\.q,z9\.q' +[^ :]+:[0-9]+: Error: selected processor does not support `zip {z0\.b-z3\.b},{z0\.b-z3\.b}' +[^ :]+:[0-9]+: Error: selected processor does not support `zip {z28\.b-z31\.b},{z0\.b-z3\.b}' +[^ :]+:[0-9]+: Error: selected processor does not support `zip {z0\.b-z3\.b},{z28\.b-z31\.b}' +[^ :]+:[0-9]+: Error: selected processor does not support `zip {z4\.b-z7\.b},{z24\.b-z27\.b}' +[^ :]+:[0-9]+: Error: selected processor does not support `zip {z0\.h-z3\.h},{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `zip {z28\.h-z31\.h},{z0\.h-z3\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `zip {z0\.h-z3\.h},{z28\.h-z31\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `zip {z16\.h-z19\.h},{z8\.h-z11\.h}' +[^ :]+:[0-9]+: Error: selected processor does not support `zip {z0\.s-z3\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `zip {z28\.s-z31\.s},{z0\.s-z3\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `zip {z0\.s-z3\.s},{z28\.s-z31\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `zip {z20\.s-z23\.s},{z12\.s-z15\.s}' +[^ :]+:[0-9]+: Error: selected processor does not support `zip {z0\.d-z3\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `zip {z28\.d-z31\.d},{z0\.d-z3\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `zip {z0\.d-z3\.d},{z28\.d-z31\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `zip {z8\.d-z11\.d},{z16\.d-z19\.d}' +[^ :]+:[0-9]+: Error: selected processor does not support `zip {z0\.q-z3\.q},{z0\.q-z3\.q}' +[^ :]+:[0-9]+: Error: selected processor does not support `zip {z28\.q-z31\.q},{z0\.q-z3\.q}' +[^ :]+:[0-9]+: Error: selected processor does not support `zip {z0\.q-z3\.q},{z28\.q-z31\.q}' +[^ :]+:[0-9]+: Error: selected processor does not support `zip {z12\.q-z15\.q},{z4\.q-z7\.q}' diff --git a/gas/testsuite/gas/aarch64/sme2-30.d b/gas/testsuite/gas/aarch64/sme2-30.d new file mode 100644 index 00000000000..2db95e0a83a --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-30.d @@ -0,0 +1,99 @@ +#as: -march=armv8-a+sme2 +#objdump: -dr + +[^:]+: file format .* + + +[^:]+: + +[^:]+: +[^:]+: c120d001 uzp {z0\.b-z1\.b}, z0\.b, z0\.b +[^:]+: c120d01f uzp {z30\.b-z31\.b}, z0\.b, z0\.b +[^:]+: c120d3e1 uzp {z0\.b-z1\.b}, z31\.b, z0\.b +[^:]+: c13fd001 uzp {z0\.b-z1\.b}, z0\.b, z31\.b +[^:]+: c139d173 uzp {z18\.b-z19\.b}, z11\.b, z25\.b +[^:]+: c160d001 uzp {z0\.h-z1\.h}, z0\.h, z0\.h +[^:]+: c160d01f uzp {z30\.h-z31\.h}, z0\.h, z0\.h +[^:]+: c160d3e1 uzp {z0\.h-z1\.h}, z31\.h, z0\.h +[^:]+: c17fd001 uzp {z0\.h-z1\.h}, z0\.h, z31\.h +[^:]+: c176d107 uzp {z6\.h-z7\.h}, z8\.h, z22\.h +[^:]+: c1a0d001 uzp {z0\.s-z1\.s}, z0\.s, z0\.s +[^:]+: c1a0d01f uzp {z30\.s-z31\.s}, z0\.s, z0\.s +[^:]+: c1a0d3e1 uzp {z0\.s-z1\.s}, z31\.s, z0\.s +[^:]+: c1bfd001 uzp {z0\.s-z1\.s}, z0\.s, z31\.s +[^:]+: c1a2d279 uzp {z24\.s-z25\.s}, z19\.s, z2\.s +[^:]+: c1e0d001 uzp {z0\.d-z1\.d}, z0\.d, z0\.d +[^:]+: c1e0d01f uzp {z30\.d-z31\.d}, z0\.d, z0\.d +[^:]+: c1e0d3e1 uzp {z0\.d-z1\.d}, z31\.d, z0\.d +[^:]+: c1ffd001 uzp {z0\.d-z1\.d}, z0\.d, z31\.d +[^:]+: c1e5d3a3 uzp {z2\.d-z3\.d}, z29\.d, z5\.d +[^:]+: c120d401 uzp {z0\.q-z1\.q}, z0\.q, z0\.q +[^:]+: c120d41f uzp {z30\.q-z31\.q}, z0\.q, z0\.q +[^:]+: c120d7e1 uzp {z0\.q-z1\.q}, z31\.q, z0\.q +[^:]+: c13fd401 uzp {z0\.q-z1\.q}, z0\.q, z31\.q +[^:]+: c129d70f uzp {z14\.q-z15\.q}, z24\.q, z9\.q +[^:]+: c136e002 uzp {z0\.b-z3\.b}, {z0\.b-z3\.b} +[^:]+: c136e01e uzp {z28\.b-z31\.b}, {z0\.b-z3\.b} +[^:]+: c136e382 uzp {z0\.b-z3\.b}, {z28\.b-z31\.b} +[^:]+: c136e306 uzp {z4\.b-z7\.b}, {z24\.b-z27\.b} +[^:]+: c176e002 uzp {z0\.h-z3\.h}, {z0\.h-z3\.h} +[^:]+: c176e01e uzp {z28\.h-z31\.h}, {z0\.h-z3\.h} +[^:]+: c176e382 uzp {z0\.h-z3\.h}, {z28\.h-z31\.h} +[^:]+: c176e112 uzp {z16\.h-z19\.h}, {z8\.h-z11\.h} +[^:]+: c1b6e002 uzp {z0\.s-z3\.s}, {z0\.s-z3\.s} +[^:]+: c1b6e01e uzp {z28\.s-z31\.s}, {z0\.s-z3\.s} +[^:]+: c1b6e382 uzp {z0\.s-z3\.s}, {z28\.s-z31\.s} +[^:]+: c1b6e196 uzp {z20\.s-z23\.s}, {z12\.s-z15\.s} +[^:]+: c1f6e002 uzp {z0\.d-z3\.d}, {z0\.d-z3\.d} +[^:]+: c1f6e01e uzp {z28\.d-z31\.d}, {z0\.d-z3\.d} +[^:]+: c1f6e382 uzp {z0\.d-z3\.d}, {z28\.d-z31\.d} +[^:]+: c1f6e20a uzp {z8\.d-z11\.d}, {z16\.d-z19\.d} +[^:]+: c137e002 uzp {z0\.q-z3\.q}, {z0\.q-z3\.q} +[^:]+: c137e01e uzp {z28\.q-z31\.q}, {z0\.q-z3\.q} +[^:]+: c137e382 uzp {z0\.q-z3\.q}, {z28\.q-z31\.q} +[^:]+: c137e08e uzp {z12\.q-z15\.q}, {z4\.q-z7\.q} +[^:]+: c120d000 zip {z0\.b-z1\.b}, z0\.b, z0\.b +[^:]+: c120d01e zip {z30\.b-z31\.b}, z0\.b, z0\.b +[^:]+: c120d3e0 zip {z0\.b-z1\.b}, z31\.b, z0\.b +[^:]+: c13fd000 zip {z0\.b-z1\.b}, z0\.b, z31\.b +[^:]+: c139d172 zip {z18\.b-z19\.b}, z11\.b, z25\.b +[^:]+: c160d000 zip {z0\.h-z1\.h}, z0\.h, z0\.h +[^:]+: c160d01e zip {z30\.h-z31\.h}, z0\.h, z0\.h +[^:]+: c160d3e0 zip {z0\.h-z1\.h}, z31\.h, z0\.h +[^:]+: c17fd000 zip {z0\.h-z1\.h}, z0\.h, z31\.h +[^:]+: c176d106 zip {z6\.h-z7\.h}, z8\.h, z22\.h +[^:]+: c1a0d000 zip {z0\.s-z1\.s}, z0\.s, z0\.s +[^:]+: c1a0d01e zip {z30\.s-z31\.s}, z0\.s, z0\.s +[^:]+: c1a0d3e0 zip {z0\.s-z1\.s}, z31\.s, z0\.s +[^:]+: c1bfd000 zip {z0\.s-z1\.s}, z0\.s, z31\.s +[^:]+: c1a2d278 zip {z24\.s-z25\.s}, z19\.s, z2\.s +[^:]+: c1e0d000 zip {z0\.d-z1\.d}, z0\.d, z0\.d +[^:]+: c1e0d01e zip {z30\.d-z31\.d}, z0\.d, z0\.d +[^:]+: c1e0d3e0 zip {z0\.d-z1\.d}, z31\.d, z0\.d +[^:]+: c1ffd000 zip {z0\.d-z1\.d}, z0\.d, z31\.d +[^:]+: c1e5d3a2 zip {z2\.d-z3\.d}, z29\.d, z5\.d +[^:]+: c120d400 zip {z0\.q-z1\.q}, z0\.q, z0\.q +[^:]+: c120d41e zip {z30\.q-z31\.q}, z0\.q, z0\.q +[^:]+: c120d7e0 zip {z0\.q-z1\.q}, z31\.q, z0\.q +[^:]+: c13fd400 zip {z0\.q-z1\.q}, z0\.q, z31\.q +[^:]+: c129d70e zip {z14\.q-z15\.q}, z24\.q, z9\.q +[^:]+: c136e000 zip {z0\.b-z3\.b}, {z0\.b-z3\.b} +[^:]+: c136e01c zip {z28\.b-z31\.b}, {z0\.b-z3\.b} +[^:]+: c136e380 zip {z0\.b-z3\.b}, {z28\.b-z31\.b} +[^:]+: c136e304 zip {z4\.b-z7\.b}, {z24\.b-z27\.b} +[^:]+: c176e000 zip {z0\.h-z3\.h}, {z0\.h-z3\.h} +[^:]+: c176e01c zip {z28\.h-z31\.h}, {z0\.h-z3\.h} +[^:]+: c176e380 zip {z0\.h-z3\.h}, {z28\.h-z31\.h} +[^:]+: c176e110 zip {z16\.h-z19\.h}, {z8\.h-z11\.h} +[^:]+: c1b6e000 zip {z0\.s-z3\.s}, {z0\.s-z3\.s} +[^:]+: c1b6e01c zip {z28\.s-z31\.s}, {z0\.s-z3\.s} +[^:]+: c1b6e380 zip {z0\.s-z3\.s}, {z28\.s-z31\.s} +[^:]+: c1b6e194 zip {z20\.s-z23\.s}, {z12\.s-z15\.s} +[^:]+: c1f6e000 zip {z0\.d-z3\.d}, {z0\.d-z3\.d} +[^:]+: c1f6e01c zip {z28\.d-z31\.d}, {z0\.d-z3\.d} +[^:]+: c1f6e380 zip {z0\.d-z3\.d}, {z28\.d-z31\.d} +[^:]+: c1f6e208 zip {z8\.d-z11\.d}, {z16\.d-z19\.d} +[^:]+: c137e000 zip {z0\.q-z3\.q}, {z0\.q-z3\.q} +[^:]+: c137e01c zip {z28\.q-z31\.q}, {z0\.q-z3\.q} +[^:]+: c137e380 zip {z0\.q-z3\.q}, {z28\.q-z31\.q} +[^:]+: c137e08c zip {z12\.q-z15\.q}, {z4\.q-z7\.q} diff --git a/gas/testsuite/gas/aarch64/sme2-30.s b/gas/testsuite/gas/aarch64/sme2-30.s new file mode 100644 index 00000000000..ade5fc1a0bd --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-30.s @@ -0,0 +1,109 @@ + uzp { z0.b - z1.b }, z0.b, z0.b + uzp { z30.b - z31.b }, z0.b, z0.b + uzp { z0.b - z1.b }, z31.b, z0.b + uzp { z0.b - z1.b }, z0.b, z31.b + uzp { z18.b - z19.b }, z11.b, z25.b + + uzp { z0.h - z1.h }, z0.h, z0.h + uzp { z30.h - z31.h }, z0.h, z0.h + uzp { z0.h - z1.h }, z31.h, z0.h + uzp { z0.h - z1.h }, z0.h, z31.h + uzp { z6.h - z7.h }, z8.h, z22.h + + uzp { z0.s - z1.s }, z0.s, z0.s + uzp { z30.s - z31.s }, z0.s, z0.s + uzp { z0.s - z1.s }, z31.s, z0.s + uzp { z0.s - z1.s }, z0.s, z31.s + uzp { z24.s - z25.s }, z19.s, z2.s + + uzp { z0.d - z1.d }, z0.d, z0.d + uzp { z30.d - z31.d }, z0.d, z0.d + uzp { z0.d - z1.d }, z31.d, z0.d + uzp { z0.d - z1.d }, z0.d, z31.d + uzp { z2.d - z3.d }, z29.d, z5.d + + uzp { z0.q - z1.q }, z0.q, z0.q + uzp { z30.q - z31.q }, z0.q, z0.q + uzp { z0.q - z1.q }, z31.q, z0.q + uzp { z0.q - z1.q }, z0.q, z31.q + uzp { z14.q - z15.q }, z24.q, z9.q + + uzp { z0.b - z3.b }, { z0.b - z3.b } + uzp { z28.b - z31.b }, { z0.b - z3.b } + uzp { z0.b - z3.b }, { z28.b - z31.b } + uzp { z4.b - z7.b }, { z24.b - z27.b } + + uzp { z0.h - z3.h }, { z0.h - z3.h } + uzp { z28.h - z31.h }, { z0.h - z3.h } + uzp { z0.h - z3.h }, { z28.h - z31.h } + uzp { z16.h - z19.h }, { z8.h - z11.h } + + uzp { z0.s - z3.s }, { z0.s - z3.s } + uzp { z28.s - z31.s }, { z0.s - z3.s } + uzp { z0.s - z3.s }, { z28.s - z31.s } + uzp { z20.s - z23.s }, { z12.s - z15.s } + + uzp { z0.d - z3.d }, { z0.d - z3.d } + uzp { z28.d - z31.d }, { z0.d - z3.d } + uzp { z0.d - z3.d }, { z28.d - z31.d } + uzp { z8.d - z11.d }, { z16.d - z19.d } + + uzp { z0.q - z3.q }, { z0.q - z3.q } + uzp { z28.q - z31.q }, { z0.q - z3.q } + uzp { z0.q - z3.q }, { z28.q - z31.q } + uzp { z12.q - z15.q }, { z4.q - z7.q } + + zip { z0.b - z1.b }, z0.b, z0.b + zip { z30.b - z31.b }, z0.b, z0.b + zip { z0.b - z1.b }, z31.b, z0.b + zip { z0.b - z1.b }, z0.b, z31.b + zip { z18.b - z19.b }, z11.b, z25.b + + zip { z0.h - z1.h }, z0.h, z0.h + zip { z30.h - z31.h }, z0.h, z0.h + zip { z0.h - z1.h }, z31.h, z0.h + zip { z0.h - z1.h }, z0.h, z31.h + zip { z6.h - z7.h }, z8.h, z22.h + + zip { z0.s - z1.s }, z0.s, z0.s + zip { z30.s - z31.s }, z0.s, z0.s + zip { z0.s - z1.s }, z31.s, z0.s + zip { z0.s - z1.s }, z0.s, z31.s + zip { z24.s - z25.s }, z19.s, z2.s + + zip { z0.d - z1.d }, z0.d, z0.d + zip { z30.d - z31.d }, z0.d, z0.d + zip { z0.d - z1.d }, z31.d, z0.d + zip { z0.d - z1.d }, z0.d, z31.d + zip { z2.d - z3.d }, z29.d, z5.d + + zip { z0.q - z1.q }, z0.q, z0.q + zip { z30.q - z31.q }, z0.q, z0.q + zip { z0.q - z1.q }, z31.q, z0.q + zip { z0.q - z1.q }, z0.q, z31.q + zip { z14.q - z15.q }, z24.q, z9.q + + zip { z0.b - z3.b }, { z0.b - z3.b } + zip { z28.b - z31.b }, { z0.b - z3.b } + zip { z0.b - z3.b }, { z28.b - z31.b } + zip { z4.b - z7.b }, { z24.b - z27.b } + + zip { z0.h - z3.h }, { z0.h - z3.h } + zip { z28.h - z31.h }, { z0.h - z3.h } + zip { z0.h - z3.h }, { z28.h - z31.h } + zip { z16.h - z19.h }, { z8.h - z11.h } + + zip { z0.s - z3.s }, { z0.s - z3.s } + zip { z28.s - z31.s }, { z0.s - z3.s } + zip { z0.s - z3.s }, { z28.s - z31.s } + zip { z20.s - z23.s }, { z12.s - z15.s } + + zip { z0.d - z3.d }, { z0.d - z3.d } + zip { z28.d - z31.d }, { z0.d - z3.d } + zip { z0.d - z3.d }, { z28.d - z31.d } + zip { z8.d - z11.d }, { z16.d - z19.d } + + zip { z0.q - z3.q }, { z0.q - z3.q } + zip { z28.q - z31.q }, { z0.q - z3.q } + zip { z0.q - z3.q }, { z28.q - z31.q } + zip { z12.q - z15.q }, { z4.q - z7.q } diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c index e514becb5fd..bf04e3fcb0b 100644 --- a/opcodes/aarch64-dis-2.c +++ b/opcodes/aarch64-dis-2.c @@ -188,7 +188,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000x10x100xxxxxxxxxxxxxxxxx zero. */ - return 2887; + return 2891; } } } @@ -1721,7 +1721,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011000xxxxxxx0xxxxxxx00xxx smlall. */ - return 2890; + return 2898; } else { @@ -1731,7 +1731,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011001xxxx0xx0xxxxxxx00xxx smlall. */ - return 2891; + return 2899; } else { @@ -1739,7 +1739,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011001xxxx1xx0xxxxxxx00xxx smlall. */ - return 2892; + return 2900; } } } @@ -1806,7 +1806,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011000xxxxxxx0xxxxxxx10xxx umlall. */ - return 2899; + return 2907; } else { @@ -1816,7 +1816,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011001xxxx0xx0xxxxxxx10xxx umlall. */ - return 2900; + return 2908; } else { @@ -1824,7 +1824,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10000011001xxxx1xx0xxxxxxx10xxx umlall. */ - return 2901; + return 2909; } } } @@ -1884,7 +1884,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000011000xxxxxxx0xxxxxxx01xxx smlsll. */ - return 2893; + return 2901; } else { @@ -1894,7 +1894,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000011001xxxx0xx0xxxxxxx01xxx smlsll. */ - return 2894; + return 2902; } else { @@ -1902,7 +1902,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000011001xxxx1xx0xxxxxxx01xxx smlsll. */ - return 2895; + return 2903; } } } @@ -1958,7 +1958,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000011000xxxxxxx0xxxxxxx11xxx umlsll. */ - return 2902; + return 2910; } else { @@ -1968,7 +1968,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000011001xxxx0xx0xxxxxxx11xxx umlsll. */ - return 2903; + return 2911; } else { @@ -1976,7 +1976,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0000011001xxxx1xx0xxxxxxx11xxx umlsll. */ - return 2904; + return 2912; } } } @@ -2522,7 +2522,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx000001110xxxxx0xx0xxxxxxx00xxx fmla. */ - return 2906; + return 2914; } else { @@ -2530,7 +2530,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx000001110xxxxx1xx0xxxxxxx00xxx fmla. */ - return 2907; + return 2915; } } else @@ -2576,7 +2576,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx000001110xxxxx0xx00xxxxxx01xxx sdot. */ - return 2888; + return 2896; } else { @@ -2584,7 +2584,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx000001110xxxxx1xx00xxxxxx01xxx sdot. */ - return 2889; + return 2897; } } else @@ -2593,7 +2593,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx000001110xxxxxxxx01xxxxxx01xxx svdot. */ - return 2896; + return 2904; } } else @@ -2662,7 +2662,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx000001110xxxxx0xx0xxxxxxx10xxx fmls. */ - return 2908; + return 2916; } else { @@ -2670,7 +2670,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx000001110xxxxx1xx0xxxxxxx10xxx fmls. */ - return 2909; + return 2917; } } else @@ -2725,7 +2725,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001110xxxxx0xx00xxxxxx11xxx udot. */ - return 2897; + return 2905; } else { @@ -2733,7 +2733,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001110xxxxx1xx00xxxxxx11xxx udot. */ - return 2898; + return 2906; } } else @@ -2742,7 +2742,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx00001110xxxxxxxx01xxxxxx11xxx uvdot. */ - return 2905; + return 2913; } } else @@ -4162,11 +4162,33 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 11) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx1xxxxx110x00xxxxxxxxxx - fclamp. */ - return 2466; + if (((word >> 0) & 0x1) == 0) + { + if (((word >> 12) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xxxxx110000xxxxxxxxx0 + fclamp. */ + return 2466; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xxxxx110100xxxxxxxxx0 + zip. */ + return 2892; + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xxxxx110x00xxxxxxxxx1 + uzp. */ + return 2879; + } } else { @@ -4235,32 +4257,54 @@ aarch64_opcode_lookup_1 (uint32_t word) } else { - if (((word >> 5) & 0x1) == 0) + if (((word >> 22) & 0x1) == 0) { - if (((word >> 20) & 0x1) == 0) + if (((word >> 0) & 0x1) == 0) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x1000001xx10xxxx110101xxxx0xxxxx - sqrshr. */ - return 2697; + x1000001x01xxxxx110101xxxxxxxxx0 + zip. */ + return 2893; } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x1000001xx11xxxx110101xxxx0xxxxx - sqrshru. */ - return 2700; + x1000001x01xxxxx110101xxxxxxxxx1 + uzp. */ + return 2880; } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx1xxxxx110101xxxx1xxxxx - uqrshr. */ - return 2853; + if (((word >> 5) & 0x1) == 0) + { + if (((word >> 20) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001x110xxxx110101xxxx0xxxxx + sqrshr. */ + return 2697; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001x111xxxx110101xxxx0xxxxx + sqrshru. */ + return 2700; + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001x11xxxxx110101xxxx1xxxxx + uqrshr. */ + return 2853; + } } } } @@ -4516,42 +4560,64 @@ aarch64_opcode_lookup_1 (uint32_t word) } else { - if (((word >> 19) & 0x1) == 0) + if (((word >> 18) & 0x1) == 0) { - if (((word >> 20) & 0x1) == 0) + if (((word >> 19) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx100x10111000xxxx0xxxxx - scvtf. */ - return 2629; + if (((word >> 20) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx100010111000xxxx0xxxxx + scvtf. */ + return 2629; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx110010111000xxxx0xxxxx + scvtf. */ + return 2630; + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001xx110x10111000xxxx0xxxxx - scvtf. */ - return 2630; + if (((word >> 20) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx101010111000xxxx0xxxxx + frintm. */ + return 2526; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx111010111000xxxx0xxxxx + frintm. */ + return 2527; + } } } else { - if (((word >> 20) & 0x1) == 0) + if (((word >> 1) & 0x1) == 0) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x1000001xx101x10111000xxxx0xxxxx - frintm. */ - return 2526; + x1000001xx1xx110111000xxxx0xxx0x + zip. */ + return 2894; } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x1000001xx111x10111000xxxx0xxxxx - frintm. */ - return 2527; + x1000001xx1xx110111000xxxx0xxx1x + uzp. */ + return 2881; } } } @@ -4711,66 +4777,88 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 5) & 0x1) == 0) { - if (((word >> 20) & 0x1) == 0) - { - if (((word >> 22) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001x010xx11111000xxxx0xxxxx - sqcvt. */ - return 2687; - } - else - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001x110xx11111000xxxx0xxxxx - sqcvtu. */ - return 2690; - } - } - else + if (((word >> 18) & 0x1) == 0) { - if (((word >> 6) & 0x1) == 0) + if (((word >> 20) & 0x1) == 0) { if (((word >> 22) & 0x1) == 0) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x1000001x011xx11111000xxx00xxxxx + x1000001x010x011111000xxxx0xxxxx sqcvt. */ - return 2688; + return 2687; } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x1000001x111xx11111000xxx00xxxxx + x1000001x110x011111000xxxx0xxxxx sqcvtu. */ - return 2691; + return 2690; } } else { - if (((word >> 22) & 0x1) == 0) + if (((word >> 6) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001x011xx11111000xxx10xxxxx - sqcvtn. */ - return 2689; + if (((word >> 22) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001x011x011111000xxx00xxxxx + sqcvt. */ + return 2688; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001x111x011111000xxx00xxxxx + sqcvtu. */ + return 2691; + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000001x111xx11111000xxx10xxxxx - sqcvtun. */ - return 2692; + if (((word >> 22) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001x011x011111000xxx10xxxxx + sqcvtn. */ + return 2689; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001x111x011111000xxx10xxxxx + sqcvtun. */ + return 2692; + } } } } + else + { + if (((word >> 1) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xx111111000xxxx0xxx0x + zip. */ + return 2895; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000001xx1xx111111000xxxx0xxx1x + uzp. */ + return 2882; + } + } } else { @@ -7978,7 +8066,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 00011001000xxxxxxxxx00xxxxxxxxxx stlurb. */ - return 2950; + return 2958; } else { @@ -7986,7 +8074,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 10011001000xxxxxxxxx00xxxxxxxxxx stlur. */ - return 2958; + return 2966; } } else @@ -7997,7 +8085,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 01011001000xxxxxxxxx00xxxxxxxxxx stlurh. */ - return 2954; + return 2962; } else { @@ -8005,7 +8093,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 11011001000xxxxxxxxx00xxxxxxxxxx stlur. */ - return 2961; + return 2969; } } } @@ -8043,7 +8131,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0000x1xxxxxxxxxx cpyfp. */ - return 3010; + return 3018; } else { @@ -8051,7 +8139,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1000x1xxxxxxxxxx cpyfprn. */ - return 3016; + return 3024; } } else @@ -8062,7 +8150,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0100x1xxxxxxxxxx cpyfpwn. */ - return 3013; + return 3021; } else { @@ -8070,7 +8158,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1100x1xxxxxxxxxx cpyfpn. */ - return 3019; + return 3027; } } } @@ -8084,7 +8172,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0010x1xxxxxxxxxx cpyfprt. */ - return 3034; + return 3042; } else { @@ -8092,7 +8180,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1010x1xxxxxxxxxx cpyfprtrn. */ - return 3040; + return 3048; } } else @@ -8103,7 +8191,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0110x1xxxxxxxxxx cpyfprtwn. */ - return 3037; + return 3045; } else { @@ -8111,7 +8199,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1110x1xxxxxxxxxx cpyfprtn. */ - return 3043; + return 3051; } } } @@ -8128,7 +8216,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0001x1xxxxxxxxxx cpyfpwt. */ - return 3022; + return 3030; } else { @@ -8136,7 +8224,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1001x1xxxxxxxxxx cpyfpwtrn. */ - return 3028; + return 3036; } } else @@ -8147,7 +8235,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0101x1xxxxxxxxxx cpyfpwtwn. */ - return 3025; + return 3033; } else { @@ -8155,7 +8243,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1101x1xxxxxxxxxx cpyfpwtn. */ - return 3031; + return 3039; } } } @@ -8169,7 +8257,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0011x1xxxxxxxxxx cpyfpt. */ - return 3046; + return 3054; } else { @@ -8177,7 +8265,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1011x1xxxxxxxxxx cpyfptrn. */ - return 3052; + return 3060; } } else @@ -8188,7 +8276,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0111x1xxxxxxxxxx cpyfptwn. */ - return 3049; + return 3057; } else { @@ -8196,7 +8284,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1111x1xxxxxxxxxx cpyfptn. */ - return 3055; + return 3063; } } } @@ -8261,7 +8349,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 00011001010xxxxxxxxx00xxxxxxxxxx ldapurb. */ - return 2951; + return 2959; } else { @@ -8269,7 +8357,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 10011001010xxxxxxxxx00xxxxxxxxxx ldapur. */ - return 2959; + return 2967; } } else @@ -8280,7 +8368,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 01011001010xxxxxxxxx00xxxxxxxxxx ldapurh. */ - return 2955; + return 2963; } else { @@ -8288,7 +8376,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 11011001010xxxxxxxxx00xxxxxxxxxx ldapur. */ - return 2962; + return 2970; } } } @@ -8326,7 +8414,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0000x1xxxxxxxxxx cpyfm. */ - return 3011; + return 3019; } else { @@ -8334,7 +8422,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1000x1xxxxxxxxxx cpyfmrn. */ - return 3017; + return 3025; } } else @@ -8345,7 +8433,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0100x1xxxxxxxxxx cpyfmwn. */ - return 3014; + return 3022; } else { @@ -8353,7 +8441,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1100x1xxxxxxxxxx cpyfmn. */ - return 3020; + return 3028; } } } @@ -8367,7 +8455,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0010x1xxxxxxxxxx cpyfmrt. */ - return 3035; + return 3043; } else { @@ -8375,7 +8463,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1010x1xxxxxxxxxx cpyfmrtrn. */ - return 3041; + return 3049; } } else @@ -8386,7 +8474,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0110x1xxxxxxxxxx cpyfmrtwn. */ - return 3038; + return 3046; } else { @@ -8394,7 +8482,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1110x1xxxxxxxxxx cpyfmrtn. */ - return 3044; + return 3052; } } } @@ -8411,7 +8499,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0001x1xxxxxxxxxx cpyfmwt. */ - return 3023; + return 3031; } else { @@ -8419,7 +8507,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1001x1xxxxxxxxxx cpyfmwtrn. */ - return 3029; + return 3037; } } else @@ -8430,7 +8518,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0101x1xxxxxxxxxx cpyfmwtwn. */ - return 3026; + return 3034; } else { @@ -8438,7 +8526,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1101x1xxxxxxxxxx cpyfmwtn. */ - return 3032; + return 3040; } } } @@ -8452,7 +8540,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0011x1xxxxxxxxxx cpyfmt. */ - return 3047; + return 3055; } else { @@ -8460,7 +8548,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1011x1xxxxxxxxxx cpyfmtrn. */ - return 3053; + return 3061; } } else @@ -8471,7 +8559,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0111x1xxxxxxxxxx cpyfmtwn. */ - return 3050; + return 3058; } else { @@ -8479,7 +8567,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1111x1xxxxxxxxxx cpyfmtn. */ - return 3056; + return 3064; } } } @@ -8547,7 +8635,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 00011001100xxxxxxxxx00xxxxxxxxxx ldapursb. */ - return 2953; + return 2961; } else { @@ -8555,7 +8643,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 10011001100xxxxxxxxx00xxxxxxxxxx ldapursw. */ - return 2960; + return 2968; } } else @@ -8564,7 +8652,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1011001100xxxxxxxxx00xxxxxxxxxx ldapursh. */ - return 2957; + return 2965; } } else @@ -8575,7 +8663,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0011001110xxxxxxxxx00xxxxxxxxxx ldapursb. */ - return 2952; + return 2960; } else { @@ -8583,7 +8671,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1011001110xxxxxxxxx00xxxxxxxxxx ldapursh. */ - return 2956; + return 2964; } } } @@ -8645,7 +8733,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0000x1xxxxxxxxxx cpyfe. */ - return 3012; + return 3020; } else { @@ -8653,7 +8741,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0000x1xxxxxxxxxx setp. */ - return 3106; + return 3114; } } else @@ -8664,7 +8752,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx1000x1xxxxxxxxxx cpyfern. */ - return 3018; + return 3026; } else { @@ -8672,7 +8760,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx1000x1xxxxxxxxxx sete. */ - return 3108; + return 3116; } } } @@ -8686,7 +8774,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0100x1xxxxxxxxxx cpyfewn. */ - return 3015; + return 3023; } else { @@ -8694,7 +8782,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0100x1xxxxxxxxxx setm. */ - return 3107; + return 3115; } } else @@ -8703,7 +8791,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0110011x0xxxxx1100x1xxxxxxxxxx cpyfen. */ - return 3021; + return 3029; } } } @@ -8719,7 +8807,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0010x1xxxxxxxxxx cpyfert. */ - return 3036; + return 3044; } else { @@ -8727,7 +8815,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0010x1xxxxxxxxxx setpn. */ - return 3112; + return 3120; } } else @@ -8738,7 +8826,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx1010x1xxxxxxxxxx cpyfertrn. */ - return 3042; + return 3050; } else { @@ -8746,7 +8834,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx1010x1xxxxxxxxxx seten. */ - return 3114; + return 3122; } } } @@ -8760,7 +8848,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0110x1xxxxxxxxxx cpyfertwn. */ - return 3039; + return 3047; } else { @@ -8768,7 +8856,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0110x1xxxxxxxxxx setmn. */ - return 3113; + return 3121; } } else @@ -8777,7 +8865,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0110011x0xxxxx1110x1xxxxxxxxxx cpyfertn. */ - return 3045; + return 3053; } } } @@ -8796,7 +8884,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0001x1xxxxxxxxxx cpyfewt. */ - return 3024; + return 3032; } else { @@ -8804,7 +8892,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0001x1xxxxxxxxxx setpt. */ - return 3109; + return 3117; } } else @@ -8815,7 +8903,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx1001x1xxxxxxxxxx cpyfewtrn. */ - return 3030; + return 3038; } else { @@ -8823,7 +8911,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx1001x1xxxxxxxxxx setet. */ - return 3111; + return 3119; } } } @@ -8837,7 +8925,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0101x1xxxxxxxxxx cpyfewtwn. */ - return 3027; + return 3035; } else { @@ -8845,7 +8933,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0101x1xxxxxxxxxx setmt. */ - return 3110; + return 3118; } } else @@ -8854,7 +8942,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0110011x0xxxxx1101x1xxxxxxxxxx cpyfewtn. */ - return 3033; + return 3041; } } } @@ -8870,7 +8958,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0011x1xxxxxxxxxx cpyfet. */ - return 3048; + return 3056; } else { @@ -8878,7 +8966,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0011x1xxxxxxxxxx setptn. */ - return 3115; + return 3123; } } else @@ -8889,7 +8977,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx1011x1xxxxxxxxxx cpyfetrn. */ - return 3054; + return 3062; } else { @@ -8897,7 +8985,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx1011x1xxxxxxxxxx setetn. */ - return 3117; + return 3125; } } } @@ -8911,7 +8999,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0111x1xxxxxxxxxx cpyfetwn. */ - return 3051; + return 3059; } else { @@ -8919,7 +9007,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0111x1xxxxxxxxxx setmtn. */ - return 3116; + return 3124; } } else @@ -8928,7 +9016,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0110011x0xxxxx1111x1xxxxxxxxxx cpyfetn. */ - return 3057; + return 3065; } } } @@ -9301,7 +9389,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1x11010110xxxx0x01000xxxxxxxxxx abs. */ - return 3135; + return 3143; } else { @@ -9319,7 +9407,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010110xxxxxx11000xxxxxxxxxx smax. */ - return 3138; + return 3146; } } } @@ -9399,7 +9487,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010x00xxxxxx0xx10xxxxxxxxxx setf8. */ - return 2948; + return 2956; } else { @@ -9407,7 +9495,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010x00xxxxxx1xx10xxxxxxxxxx setf16. */ - return 2949; + return 2957; } } else @@ -9514,7 +9602,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010110xxxxxx11010xxxxxxxxxx smin. */ - return 3140; + return 3148; } } } @@ -9530,7 +9618,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010110xxxx0x00110xxxxxxxxxx ctz. */ - return 3137; + return 3145; } else { @@ -9575,7 +9663,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010000xxxxxxxxx01xxxxxxxxxx rmif. */ - return 2947; + return 2955; } else { @@ -9669,7 +9757,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010x10xxxxxx11001xxxxxxxxxx umax. */ - return 3139; + return 3147; } } } @@ -9799,7 +9887,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010xx0xxxxxx11011xxxxxxxxxx umin. */ - return 3141; + return 3149; } } } @@ -9815,7 +9903,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010xx0xxxx0x00111xxxxxxxxxx cnt. */ - return 3136; + return 3144; } else { @@ -10657,7 +10745,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x01x1xxxxx000110xxxxxxxxxx usdot. */ - return 2967; + return 2975; } } } @@ -10731,7 +10819,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x01x1xxxxx000111xxxxxxxxxx sudot. */ - return 2968; + return 2976; } } } @@ -13405,7 +13493,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x0xx0xxxxx011110xxxxxxxxxx usdot. */ - return 2966; + return 2974; } } } @@ -15109,7 +15197,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0100xxx10101xxxxxxxxxxxxx bfcvtnt. */ - return 2995; + return 3003; } } else @@ -15352,7 +15440,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x00x1xxxxxx00xxxxxxxxxxxxx ld1rob. */ - return 2971; + return 2979; } else { @@ -15360,7 +15448,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x01x1xxxxxx00xxxxxxxxxxxxx ld1roh. */ - return 2972; + return 2980; } } else @@ -15592,7 +15680,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0011xxxxx010xxxxxxxxxxxxx bfdot. */ - return 2992; + return 3000; } else { @@ -15613,7 +15701,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx010xx0xxxxxxxxxx bfmlalb. */ - return 2999; + return 3007; } else { @@ -15621,7 +15709,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx010xx1xxxxxxxxxx bfmlalt. */ - return 2998; + return 3006; } } else @@ -15676,7 +15764,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11001x0011xxxxx1x0xxxxxxxxxxxxx bfdot. */ - return 2991; + return 2999; } else { @@ -15688,7 +15776,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx1x0xx0xxxxxxxxxx bfmlalb. */ - return 2997; + return 3005; } else { @@ -15696,7 +15784,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx1x0xx1xxxxxxxxxx bfmlalt. */ - return 2996; + return 3004; } } else @@ -15747,7 +15835,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x00x1xxxxx001xxxxxxxxxxxxx ld1rob. */ - return 2975; + return 2983; } else { @@ -15755,7 +15843,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x01x1xxxxx001xxxxxxxxxxxxx ld1roh. */ - return 2976; + return 2984; } } else @@ -16114,7 +16202,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0101xxxxx111xxxxxxxxxxxxx fmmla. */ - return 2969; + return 2977; } else { @@ -16147,7 +16235,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0011xxxxx111xxxxxxxxxxxxx bfmmla. */ - return 2993; + return 3001; } else { @@ -16177,7 +16265,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx111xxxxxxxxxxxxx fmmla. */ - return 2970; + return 2978; } else { @@ -16306,7 +16394,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000x00xxxxxxxxxx zip1. */ - return 2979; + return 2987; } else { @@ -16316,7 +16404,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000010xxxxxxxxxx uzp1. */ - return 2981; + return 2989; } else { @@ -16324,7 +16412,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000110xxxxxxxxxx trn1. */ - return 2983; + return 2991; } } } @@ -16336,7 +16424,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000x01xxxxxxxxxx zip2. */ - return 2980; + return 2988; } else { @@ -16346,7 +16434,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000011xxxxxxxxxx uzp2. */ - return 2982; + return 2990; } else { @@ -16354,7 +16442,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000111xxxxxxxxxx trn2. */ - return 2984; + return 2992; } } } @@ -17413,7 +17501,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x1000xxxxx100110xxxxxxxxxx smmla. */ - return 2963; + return 2971; } else { @@ -17421,7 +17509,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x1100xxxxx100110xxxxxxxxxx usmmla. */ - return 2965; + return 2973; } } else @@ -17430,7 +17518,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x1x10xxxxx100110xxxxxxxxxx ummla. */ - return 2964; + return 2972; } } } @@ -18926,7 +19014,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x10x1xxxxx000xxxxxxxxxxxxx ld1row. */ - return 2973; + return 2981; } else { @@ -18934,7 +19022,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x11x1xxxxx000xxxxxxxxxxxxx ld1rod. */ - return 2974; + return 2982; } } } @@ -19308,7 +19396,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x10x1xxxxx001xxxxxxxxxxxxx ld1row. */ - return 2977; + return 2985; } else { @@ -19316,7 +19404,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x11x1xxxxx001xxxxxxxxxxxxx ld1rod. */ - return 2978; + return 2986; } } } @@ -19677,7 +19765,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x000xxxxx10xxx whilege. */ - return 2879; + return 2883; } else { @@ -19685,7 +19773,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x000xxxxx11xxx whilegt. */ - return 2880; + return 2884; } } else @@ -19729,7 +19817,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x010xxxxx10xxx whilehs. */ - return 2882; + return 2886; } else { @@ -19737,7 +19825,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x010xxxxx11xxx whilehi. */ - return 2881; + return 2885; } } else @@ -19784,7 +19872,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x001xxxxx10xxx whilelt. */ - return 2886; + return 2890; } else { @@ -19792,7 +19880,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x001xxxxx11xxx whilele. */ - return 2883; + return 2887; } } else @@ -19836,7 +19924,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x011xxxxx10xxx whilelo. */ - return 2884; + return 2888; } else { @@ -19844,7 +19932,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x011xxxxx11xxx whilels. */ - return 2885; + return 2889; } } else @@ -20970,7 +21058,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x110001x10101xxxxxxxxxxxxx bfcvt. */ - return 2994; + return 3002; } } else @@ -22331,7 +22419,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1010100xxxxxxxxxxxxxxxxxxx1xxxx bc.c. */ - return 3130; + return 3138; } else { @@ -22911,7 +22999,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0000xxxxxxxxxxxx cpyp. */ - return 3058; + return 3066; } else { @@ -22919,7 +23007,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0000xxxxxxxxxxxx cpye. */ - return 3060; + return 3068; } } else @@ -22930,7 +23018,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1000xxxxxxxxxxxx cpyprn. */ - return 3064; + return 3072; } else { @@ -22938,7 +23026,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1000xxxxxxxxxxxx cpyern. */ - return 3066; + return 3074; } } } @@ -22952,7 +23040,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0100xxxxxxxxxxxx cpypwn. */ - return 3061; + return 3069; } else { @@ -22960,7 +23048,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0100xxxxxxxxxxxx cpyewn. */ - return 3063; + return 3071; } } else @@ -22971,7 +23059,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1100xxxxxxxxxxxx cpypn. */ - return 3067; + return 3075; } else { @@ -22979,7 +23067,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1100xxxxxxxxxxxx cpyen. */ - return 3069; + return 3077; } } } @@ -22996,7 +23084,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0010xxxxxxxxxxxx cpyprt. */ - return 3082; + return 3090; } else { @@ -23004,7 +23092,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0010xxxxxxxxxxxx cpyert. */ - return 3084; + return 3092; } } else @@ -23015,7 +23103,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1010xxxxxxxxxxxx cpyprtrn. */ - return 3088; + return 3096; } else { @@ -23023,7 +23111,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1010xxxxxxxxxxxx cpyertrn. */ - return 3090; + return 3098; } } } @@ -23037,7 +23125,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0110xxxxxxxxxxxx cpyprtwn. */ - return 3085; + return 3093; } else { @@ -23045,7 +23133,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0110xxxxxxxxxxxx cpyertwn. */ - return 3087; + return 3095; } } else @@ -23056,7 +23144,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1110xxxxxxxxxxxx cpyprtn. */ - return 3091; + return 3099; } else { @@ -23064,7 +23152,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1110xxxxxxxxxxxx cpyertn. */ - return 3093; + return 3101; } } } @@ -23084,7 +23172,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0001xxxxxxxxxxxx cpypwt. */ - return 3070; + return 3078; } else { @@ -23092,7 +23180,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0001xxxxxxxxxxxx cpyewt. */ - return 3072; + return 3080; } } else @@ -23103,7 +23191,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1001xxxxxxxxxxxx cpypwtrn. */ - return 3076; + return 3084; } else { @@ -23111,7 +23199,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1001xxxxxxxxxxxx cpyewtrn. */ - return 3078; + return 3086; } } } @@ -23125,7 +23213,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0101xxxxxxxxxxxx cpypwtwn. */ - return 3073; + return 3081; } else { @@ -23133,7 +23221,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0101xxxxxxxxxxxx cpyewtwn. */ - return 3075; + return 3083; } } else @@ -23144,7 +23232,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1101xxxxxxxxxxxx cpypwtn. */ - return 3079; + return 3087; } else { @@ -23152,7 +23240,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1101xxxxxxxxxxxx cpyewtn. */ - return 3081; + return 3089; } } } @@ -23169,7 +23257,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0011xxxxxxxxxxxx cpypt. */ - return 3094; + return 3102; } else { @@ -23177,7 +23265,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0011xxxxxxxxxxxx cpyet. */ - return 3096; + return 3104; } } else @@ -23188,7 +23276,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1011xxxxxxxxxxxx cpyptrn. */ - return 3100; + return 3108; } else { @@ -23196,7 +23284,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1011xxxxxxxxxxxx cpyetrn. */ - return 3102; + return 3110; } } } @@ -23210,7 +23298,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0111xxxxxxxxxxxx cpyptwn. */ - return 3097; + return 3105; } else { @@ -23218,7 +23306,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0111xxxxxxxxxxxx cpyetwn. */ - return 3099; + return 3107; } } else @@ -23229,7 +23317,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1111xxxxxxxxxxxx cpyptn. */ - return 3103; + return 3111; } else { @@ -23237,7 +23325,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1111xxxxxxxxxxxx cpyetn. */ - return 3105; + return 3113; } } } @@ -23271,7 +23359,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0000xxxxxxxxxxxx cpym. */ - return 3059; + return 3067; } else { @@ -23279,7 +23367,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0000xxxxxxxxxxxx setgp. */ - return 3118; + return 3126; } } else @@ -23290,7 +23378,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx1000xxxxxxxxxxxx cpymrn. */ - return 3065; + return 3073; } else { @@ -23298,7 +23386,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx1000xxxxxxxxxxxx setge. */ - return 3120; + return 3128; } } } @@ -23312,7 +23400,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0100xxxxxxxxxxxx cpymwn. */ - return 3062; + return 3070; } else { @@ -23320,7 +23408,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0100xxxxxxxxxxxx setgm. */ - return 3119; + return 3127; } } else @@ -23329,7 +23417,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011101x1xxxxxx1100xxxxxxxxxxxx cpymn. */ - return 3068; + return 3076; } } } @@ -23345,7 +23433,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0010xxxxxxxxxxxx cpymrt. */ - return 3083; + return 3091; } else { @@ -23353,7 +23441,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0010xxxxxxxxxxxx setgpn. */ - return 3124; + return 3132; } } else @@ -23364,7 +23452,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx1010xxxxxxxxxxxx cpymrtrn. */ - return 3089; + return 3097; } else { @@ -23372,7 +23460,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx1010xxxxxxxxxxxx setgen. */ - return 3126; + return 3134; } } } @@ -23386,7 +23474,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0110xxxxxxxxxxxx cpymrtwn. */ - return 3086; + return 3094; } else { @@ -23394,7 +23482,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0110xxxxxxxxxxxx setgmn. */ - return 3125; + return 3133; } } else @@ -23403,7 +23491,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011101x1xxxxxx1110xxxxxxxxxxxx cpymrtn. */ - return 3092; + return 3100; } } } @@ -23422,7 +23510,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0001xxxxxxxxxxxx cpymwt. */ - return 3071; + return 3079; } else { @@ -23430,7 +23518,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0001xxxxxxxxxxxx setgpt. */ - return 3121; + return 3129; } } else @@ -23441,7 +23529,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx1001xxxxxxxxxxxx cpymwtrn. */ - return 3077; + return 3085; } else { @@ -23449,7 +23537,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx1001xxxxxxxxxxxx setget. */ - return 3123; + return 3131; } } } @@ -23463,7 +23551,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0101xxxxxxxxxxxx cpymwtwn. */ - return 3074; + return 3082; } else { @@ -23471,7 +23559,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0101xxxxxxxxxxxx setgmt. */ - return 3122; + return 3130; } } else @@ -23480,7 +23568,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011101x1xxxxxx1101xxxxxxxxxxxx cpymwtn. */ - return 3080; + return 3088; } } } @@ -23496,7 +23584,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0011xxxxxxxxxxxx cpymt. */ - return 3095; + return 3103; } else { @@ -23504,7 +23592,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0011xxxxxxxxxxxx setgptn. */ - return 3127; + return 3135; } } else @@ -23515,7 +23603,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx1011xxxxxxxxxxxx cpymtrn. */ - return 3101; + return 3109; } else { @@ -23523,7 +23611,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx1011xxxxxxxxxxxx setgetn. */ - return 3129; + return 3137; } } } @@ -23537,7 +23625,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0111xxxxxxxxxxxx cpymtwn. */ - return 3098; + return 3106; } else { @@ -23545,7 +23633,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0111xxxxxxxxxxxx setgmtn. */ - return 3128; + return 3136; } } else @@ -23554,7 +23642,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011101x1xxxxxx1111xxxxxxxxxxxx cpymtn. */ - return 3104; + return 3112; } } } @@ -23721,7 +23809,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110xx0xxxxx1x1001xxxxxxxxxx smmla. */ - return 2985; + return 2993; } } } @@ -23754,7 +23842,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110xx0xxxxx1x0101xxxxxxxxxx sdot. */ - return 2911; + return 2919; } } else @@ -23828,7 +23916,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110xx0xxxxx1x1011xxxxxxxxxx usmmla. */ - return 2987; + return 2995; } } } @@ -23861,7 +23949,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110xx0xxxxx1x0111xxxxxxxxxx usdot. */ - return 2988; + return 2996; } } else @@ -23908,7 +23996,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110000xxxxxxxxxxxxxxxxxxxxx eor3. */ - return 2918; + return 2926; } else { @@ -23916,7 +24004,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110100xxxxxxxxxxxxxxxxxxxxx xar. */ - return 2920; + return 2928; } } else @@ -23927,7 +24015,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110x10xxxxx0xxxxxxxxxxxxxxx sm3ss1. */ - return 2922; + return 2930; } else { @@ -23941,7 +24029,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110010xxxxx1xxx00xxxxxxxxxx sm3tt1a. */ - return 2923; + return 2931; } else { @@ -23949,7 +24037,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110110xxxxx1xxx00xxxxxxxxxx sha512su0. */ - return 2916; + return 2924; } } else @@ -23958,7 +24046,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110x10xxxxx1xxx10xxxxxxxxxx sm3tt2a. */ - return 2925; + return 2933; } } else @@ -23971,7 +24059,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110010xxxxx1xxx01xxxxxxxxxx sm3tt1b. */ - return 2924; + return 2932; } else { @@ -23979,7 +24067,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110110xxxxx1xxx01xxxxxxxxxx sm4e. */ - return 2929; + return 2937; } } else @@ -23988,7 +24076,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110x10xxxxx1xxx11xxxxxxxxxx sm3tt2b. */ - return 2926; + return 2934; } } } @@ -24169,7 +24257,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx101110xx0xxxxx100101xxxxxxxxxx udot. */ - return 2910; + return 2918; } } else @@ -24200,7 +24288,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx101110xx0xxxxx101x01xxxxxxxxxx ummla. */ - return 2986; + return 2994; } else { @@ -24219,7 +24307,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx101110xx0xxxxx1x1011xxxxxxxxxx bfmmla. */ - return 3002; + return 3010; } else { @@ -24229,7 +24317,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx1011100x0xxxxx1x1111xxxxxxxxxx bfdot. */ - return 3000; + return 3008; } else { @@ -24239,7 +24327,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x01011101x0xxxxx1x1111xxxxxxxxxx bfmlalb. */ - return 3007; + return 3015; } else { @@ -24247,7 +24335,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11011101x0xxxxx1x1111xxxxxxxxxx bfmlalt. */ - return 3006; + return 3014; } } } @@ -24831,7 +24919,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000011101x1xxxx1011010xxxxxxxxxx bfcvtn. */ - return 3003; + return 3011; } else { @@ -24839,7 +24927,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010011101x1xxxx1011010xxxxxxxxxx bfcvtn2. */ - return 3004; + return 3012; } } } @@ -25157,7 +25245,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110xx1xxxxx0xxxxxxxxxxxxxxx bcax. */ - return 2921; + return 2929; } } else @@ -25768,7 +25856,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 11001110xx1xxxxx100000xxxxxxxxxx sha512h. */ - return 2914; + return 2922; } } } @@ -25820,7 +25908,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 11001110xx1xxxxx110000xxxxxxxxxx sm3partw1. */ - return 2927; + return 2935; } } } @@ -26063,7 +26151,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110xx1xxxxx100010xxxxxxxxxx sha512su1. */ - return 2917; + return 2925; } } else @@ -26139,7 +26227,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x0011100x1xxxxx110010xxxxxxxxxx sm4ekey. */ - return 2930; + return 2938; } } else @@ -26965,7 +27053,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110xx1xxxxx100001xxxxxxxxxx sha512h2. */ - return 2915; + return 2923; } } else @@ -26997,7 +27085,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x0011100x1xxxxx110001xxxxxxxxxx sm3partw2. */ - return 2928; + return 2936; } } else @@ -27237,7 +27325,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110xx1xxxxx100011xxxxxxxxxx rax1. */ - return 2919; + return 2927; } } else @@ -27269,7 +27357,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x01011100x1xxxxx110011xxxxxxxxxx fmlal2. */ - return 2933; + return 2941; } else { @@ -27277,7 +27365,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11011100x1xxxxx110011xxxxxxxxxx fmlal2. */ - return 2937; + return 2945; } } } @@ -27299,7 +27387,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x01011101x1xxxxx110011xxxxxxxxxx fmlsl2. */ - return 2934; + return 2942; } else { @@ -27307,7 +27395,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11011101x1xxxxx110011xxxxxxxxxx fmlsl2. */ - return 2938; + return 2946; } } } @@ -27346,7 +27434,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x00011100x1xxxxx111011xxxxxxxxxx fmlal. */ - return 2931; + return 2939; } else { @@ -27354,7 +27442,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10011100x1xxxxx111011xxxxxxxxxx fmlal. */ - return 2935; + return 2943; } } else @@ -27376,7 +27464,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x00011101x1xxxxx111011xxxxxxxxxx fmlsl. */ - return 2932; + return 2940; } else { @@ -27384,7 +27472,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10011101x1xxxxx111011xxxxxxxxxx fmlsl. */ - return 2936; + return 2944; } } else @@ -29192,7 +29280,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0001111xxxxxxxx0000x0xxxxxxxxxx fmlal. */ - return 2939; + return 2947; } else { @@ -29200,7 +29288,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1001111xxxxxxxx0000x0xxxxxxxxxx fmlal. */ - return 2943; + return 2951; } } else @@ -29222,7 +29310,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0001111xxxxxxxx0100x0xxxxxxxxxx fmlsl. */ - return 2940; + return 2948; } else { @@ -29230,7 +29318,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1001111xxxxxxxx0100x0xxxxxxxxxx fmlsl. */ - return 2944; + return 2952; } } else @@ -29736,7 +29824,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0101111xxxxxxxx1000x0xxxxxxxxxx fmlal2. */ - return 2941; + return 2949; } else { @@ -29744,7 +29832,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1101111xxxxxxxx1000x0xxxxxxxxxx fmlal2. */ - return 2945; + return 2953; } } } @@ -29766,7 +29854,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0101111xxxxxxxx1100x0xxxxxxxxxx fmlsl2. */ - return 2942; + return 2950; } else { @@ -29774,7 +29862,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1101111xxxxxxxx1100x0xxxxxxxxxx fmlsl2. */ - return 2946; + return 2954; } } } @@ -29830,7 +29918,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx001111xxxxxxxx1110x0xxxxxxxxxx sdot. */ - return 2913; + return 2921; } else { @@ -29838,7 +29926,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx101111xxxxxxxx1110x0xxxxxxxxxx udot. */ - return 2912; + return 2920; } } } @@ -29941,7 +30029,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx00111100xxxxxx1111x0xxxxxxxxxx sudot. */ - return 2990; + return 2998; } else { @@ -29949,7 +30037,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx00111110xxxxxx1111x0xxxxxxxxxx usdot. */ - return 2989; + return 2997; } } else @@ -29960,7 +30048,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx00111101xxxxxx1111x0xxxxxxxxxx bfdot. */ - return 3001; + return 3009; } else { @@ -29970,7 +30058,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x000111111xxxxxx1111x0xxxxxxxxxx bfmlalb. */ - return 3009; + return 3017; } else { @@ -29978,7 +30066,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x100111111xxxxxx1111x0xxxxxxxxxx bfmlalt. */ - return 3008; + return 3016; } } } @@ -30506,11 +30594,11 @@ aarch64_find_next_opcode (const aarch64_opcode *opcode) case 2407: value = 2412; break; /* st1q --> st1q. */ case 2412: return NULL; /* st1q --> NULL. */ case 12: value = 19; break; /* add --> addg. */ - case 19: value = 3131; break; /* addg --> smax. */ - case 3131: value = 3132; break; /* smax --> umax. */ - case 3132: value = 3133; break; /* umax --> smin. */ - case 3133: value = 3134; break; /* smin --> umin. */ - case 3134: return NULL; /* umin --> NULL. */ + case 19: value = 3139; break; /* addg --> smax. */ + case 3139: value = 3140; break; /* smax --> umax. */ + case 3140: value = 3141; break; /* umax --> smin. */ + case 3141: value = 3142; break; /* smin --> umin. */ + case 3142: return NULL; /* umin --> NULL. */ case 16: value = 20; break; /* sub --> subg. */ case 20: return NULL; /* subg --> NULL. */ case 971: value = 975; break; /* stnp --> stp. */ @@ -30668,8 +30756,8 @@ aarch64_find_next_opcode (const aarch64_opcode *opcode) case 824: return NULL; /* fsqrt --> NULL. */ case 832: value = 833; break; /* frintz --> frintz. */ case 833: return NULL; /* frintz --> NULL. */ - case 825: value = 3005; break; /* fcvt --> bfcvt. */ - case 3005: return NULL; /* bfcvt --> NULL. */ + case 825: value = 3013; break; /* fcvt --> bfcvt. */ + case 3013: return NULL; /* bfcvt --> NULL. */ case 834: value = 835; break; /* frinta --> frinta. */ case 835: return NULL; /* frinta --> NULL. */ case 836: value = 837; break; /* frintx --> frintx. */ diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index e44ad1622c8..a99d2a4a039 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -1648,6 +1648,10 @@ { \ QLF3(S_Q,P_M,S_Q), \ } +#define OP_SVE_QQ \ +{ \ + QLF2(S_Q,S_Q), \ +} #define OP_SVE_QQQ \ { \ QLF3(S_Q,S_Q,S_Q), \ @@ -5814,6 +5818,10 @@ const struct aarch64_opcode aarch64_opcode_table[] = SME2_INSN ("uunpk", 0xc135e001, 0xff3ffc23, sme_size_22_hsd, 0, OP2 (SME_Zdnx4, SME_Znx2), OP_SVE_VV_HSD_BHS, 0, 0), SME2_INSN ("uvdot", 0xc1500030, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX2), OP_SVE_SHH, F_OD (2), 0), SME2_INSN ("uvdot", 0xc1508030, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX2), OP_SVE_SBB, F_OD (4), 0), + SME2_INSN ("uzp", 0xc120d001, 0xff20fc01, sme_size_22, 0, OP3 (SME_Zdnx2, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), + SME2_INSN ("uzp", 0xc120d401, 0xffe0fc01, sme_misc, 0, OP3 (SME_Zdnx2, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0), + SME2_INSN ("uzp", 0xc136e002, 0xff3ffc63, sme_size_22, 0, OP2 (SME_Zdnx4, SME_Znx4), OP_SVE_VV_BHSD, 0, 0), + SME2_INSN ("uzp", 0xc137e002, 0xfffffc63, sme_misc, 0, OP2 (SME_Zdnx4, SME_Znx4), OP_SVE_QQ, 0, 0), SME2_INSN ("whilege", 0x25204010, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0), SME2_INSN ("whilegt", 0x25204018, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0), SME2_INSN ("whilehi", 0x25204818, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0), @@ -5823,6 +5831,10 @@ const struct aarch64_opcode aarch64_opcode_table[] = SME2_INSN ("whilels", 0x25204c18, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0), SME2_INSN ("whilelt", 0x25204410, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0), SME2_INSN ("zero", 0xc0480001, 0xffffffff, sme_misc, 0, OP1 (SME_ZT0_LIST), {}, 0, 0), + SME2_INSN ("zip", 0xc120d000, 0xff20fc01, sme_size_22, 0, OP3 (SME_Zdnx2, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0), + SME2_INSN ("zip", 0xc120d400, 0xffe0fc01, sme_misc, 0, OP3 (SME_Zdnx2, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0), + SME2_INSN ("zip", 0xc136e000, 0xff3ffc63, sme_size_22, 0, OP2 (SME_Zdnx4, SME_Znx4), OP_SVE_VV_BHSD, 0, 0), + SME2_INSN ("zip", 0xc137e000, 0xfffffc63, sme_misc, 0, OP2 (SME_Zdnx4, SME_Znx4), OP_SVE_QQ, 0, 0), /* SME2 I16I64 instructions. */ SME2_I16I64_INSN ("sdot", 0xc1d00008, 0xfff09838, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX1), OP_SVE_DHH, F_OD (2), 0),