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Signed-off-by: Ben Dooks Reviewed-by: Krzysztof Kozlowski Reviewed-by: Krzysztof Kozlowski Acked-by: Uwe Kleine-König --- v5: - fixed order of properties - corrected clock to two items v4: - fixed typos, added reg v3: - add description and example - merge the snps,pwm-number into this patch - rename snps,pwm to snps,dw-apb-timers-pwm2 v2: - fix #pwm-cells to be 3 - fix indentation and ordering issues --- .../bindings/pwm/snps,dw-apb-timers-pwm2.yaml | 68 +++++++++++++++++++ 1 file changed, 68 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml diff --git a/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml b/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml new file mode 100644 index 000000000000..9aabdb373afa --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2022 SiFive, Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/snps,dw-apb-timers-pwm2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synopsys DW-APB timers PWM controller + +maintainers: + - Ben Dooks + +description: + This describes the DesignWare APB timers module when used in the PWM + mode. The IP core can be generated with various options which can + control the functionality, the number of PWMs available and other + internal controls the designer requires. + + The IP block has a version register so this can be used for detection + instead of having to encode the IP version number in the device tree + comaptible. + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + const: snps,dw-apb-timers-pwm2 + + reg: + maxItems: 1 + + "#pwm-cells": + const: 3 + + clocks: + items: + - description: Interface bus clock + - description: PWM reference clock + + clock-names: + items: + - const: bus + - const: timer + + snps,pwm-number: + $ref: /schemas/types.yaml#/definitions/uint32 + description: The number of PWM channels configured for this instance + enum: [1, 2, 3, 4, 5, 6, 7, 8] + +required: + - compatible + - reg + - "#pwm-cells" + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + pwm: pwm@180000 { + compatible = "snps,dw-apb-timers-pwm2"; + reg = <0x180000 0x200>; + #pwm-cells = <3>; + clocks = <&bus>, <&timer>; + clock-names = "bus", "timer"; + }; From patchwork Thu Oct 20 15:16:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ben Dooks X-Patchwork-Id: 6243 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4242:0:0:0:0:0 with SMTP id s2csp169545wrr; Thu, 20 Oct 2022 08:20:25 -0700 (PDT) X-Google-Smtp-Source: AMsMyM53sP8OpSnaZQASZYiHYB7202t8u1boVVFCGML1Aexxp/F7hJMaGo/kVbWaabCUYqn9QLJV X-Received: by 2002:a63:ff55:0:b0:438:fa5d:af36 with SMTP id s21-20020a63ff55000000b00438fa5daf36mr12120491pgk.533.1666279225184; Thu, 20 Oct 2022 08:20:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666279225; cv=none; d=google.com; s=arc-20160816; b=yeaFmwZJgIfjQfCnc+Frvyi8t1mSQwLKrYDwEGa20GVSgOvaQqmHPLp/ILh5w+zVkV ok9DkkZYJVceP4EmZ6nk8KEgZrHMpjiQBh6Ul9qXF5e3wCnRQ3uPeb3bSfZTSzeap6th oC9c7QPysutLDwxSAXhs9a1r5TE7RYZE80TBUfkIzsw1Py+4ErjyhdQvPG+n6ev59ir/ aatSBMfTw+9hsUmelClADm5KC4vzWlQn22F62HyfHACQXFOlgcgCjTUDzUvu0nsaIS0s gwTRIhdJVsj4XaSiRN0akEoXhVpewPvhxN90ZcGEJKcvLCkvyvKcAW3NieLdsLtHf5xF 5KKg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=pOKidRu+yxajr1o110Z9rt8XpJh4zLytmd2a75/kdaY=; b=x3bm6P213/3BwOAkA3eJc/SXD9zS+Y0MVmW9w2lK3mYo+5aLRV77gwfDEjtrpmHTCW Uk1/cklc05rs+ye/pdShDdhrO3ZOEf7iHfv7qRqMrDWd0vOREUEgyBQ7gJwXL6NFZumb hqgK5W63oyokEm47pKXkHlG0zF+hewYh50Tzj2/lw29rfF3gVH8xD+OcD9aw7hNr6EAP VGkPXq12tUJ9Z8RE09cjd8YnJiNvr2pJLPHn/n/9CMTkfpNA4r+2Tts4P/+N8RPTKARb Z4s2SbbKy4V7RUfMwSeGDM55pBiVxX0rim2+FQsIZoyqGj9jLFw01ImJTHfaZ9azCTDD rB+Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sifive.com header.s=google header.b=kJeYraV+; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Ben Dooks Acked-by: Uwe Kleine-König --- v4: - moved to earlier in the series v3: - add HAS_IOMEM depdency for compile testing --- drivers/pwm/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 60d13a949bc5..3f3c53af4a56 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -176,7 +176,8 @@ config PWM_CROS_EC config PWM_DWC tristate "DesignWare PWM Controller" - depends on PCI + depends on PCI || COMPILE_TEST + depends on HAS_IOMEM help PWM driver for Synopsys DWC PWM Controller attached to a PCI bus. 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Change these all to the be 'dev' variable to make lines shorter. Signed-off-by: Ben Dooks Acked-by: Uwe Kleine-König --- drivers/pwm/pwm-dwc.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/pwm/pwm-dwc.c b/drivers/pwm/pwm-dwc.c index 7568300bb11e..c706ef9a7ba1 100644 --- a/drivers/pwm/pwm-dwc.c +++ b/drivers/pwm/pwm-dwc.c @@ -202,14 +202,13 @@ static int dwc_pwm_probe(struct pci_dev *pci, const struct pci_device_id *id) struct dwc_pwm *dwc; int ret; - dwc = devm_kzalloc(&pci->dev, sizeof(*dwc), GFP_KERNEL); + dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); if (!dwc) return -ENOMEM; ret = pcim_enable_device(pci); if (ret) { - dev_err(&pci->dev, - "Failed to enable device (%pe)\n", ERR_PTR(ret)); + dev_err(dev, "Failed to enable device (%pe)\n", ERR_PTR(ret)); return ret; } @@ -217,14 +216,13 @@ static int dwc_pwm_probe(struct pci_dev *pci, const struct pci_device_id *id) ret = pcim_iomap_regions(pci, BIT(0), pci_name(pci)); if (ret) { - dev_err(&pci->dev, - "Failed to iomap PCI BAR (%pe)\n", ERR_PTR(ret)); + dev_err(dev, "Failed to iomap PCI BAR (%pe)\n", ERR_PTR(ret)); return ret; } dwc->base = pcim_iomap_table(pci)[0]; if (!dwc->base) { - dev_err(&pci->dev, "Base address missing\n"); + dev_err(dev, "Base address missing\n"); return -ENOMEM; } From patchwork Thu Oct 20 15:16:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Dooks X-Patchwork-Id: 6244 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4242:0:0:0:0:0 with SMTP id s2csp169585wrr; Thu, 20 Oct 2022 08:20:30 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4DwDkEoYY8U7ClfTCI3g99AT1ToDcgwIdzabMW6Ed70FTvvrC9ikfCGYRtwg0qUjqm9ha+ X-Received: by 2002:a17:90b:1916:b0:212:c87e:d5cc with SMTP id mp22-20020a17090b191600b00212c87ed5ccmr1104pjb.45.1666279230530; Thu, 20 Oct 2022 08:20:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666279230; cv=none; d=google.com; s=arc-20160816; b=DnQQaGgOxWfukiGmezGygbgPCgerAj3SQUaPO9pv4BWvRDkQu452Zqc7nQ2XzlOoL3 T8sQ4f5c+vHTZ0nq1nSy7TGd62bT3CqAB/1A6mE9VE6nko7lKgs8w4Gf40CNNP4I3GQr cbqUBGW+0wbNGXHdk3TJTezfMnQFneu/yxreaIa+ViMgJwAtdIYq2xz+sj3YGbqj/Ea9 MAlWynOJ7yQ7ZsPTRElk63Vc+GrmoDPw6mZy3jKw+GKXbLdyKd0J3ec8ZqhhLpcR2q1U znwTbML5kYXQiDQuoEWOq29qFw64mTTScQMTdIniCQDTki5rqntI6YOyjB1UcXfU8Apv 8J/Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=3SdKoJam1KKdYl+ZS8hBn9qpHaB89KQkUoXzOnMw6QQ=; b=MKPHFwnLlZMhCHWtwViH2NIAmKhpwKx8XT+HfJU1UmmG9JlpLn8PU0vdP6ygxVK37t gDDXGP5Zi3TSIpY0E4YPbMmCEYvk1U1S+/ZxkKR4+FhMEp+xyhYv/enR70ca6VCnBea1 RBehmqAAvvZ+OmXsMzti8OTu2wyOyECaIw1kGpL/b0+hbu4mlovXC6Fc0eSulSdhvyWG 7DjfJ8nGirzdRwfDh672Ji7gvaEb0jfWr3kDGQaJbE6JPbgMpHSnBXpkZJow1h/G6S2l qyUAIk8KdJuuxgp0pZwWYZ6V0Yb70TW22KA88oGnrRPs/2nHS1YYgkXNgitjxUR1YHlE PP9Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sifive.com header.s=google header.b=RoVWDS+6; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Ben Dooks --- drivers/pwm/pwm-dwc.c | 24 +++++++++++++++++------- 1 file changed, 17 insertions(+), 7 deletions(-) diff --git a/drivers/pwm/pwm-dwc.c b/drivers/pwm/pwm-dwc.c index c706ef9a7ba1..61f11e0a9319 100644 --- a/drivers/pwm/pwm-dwc.c +++ b/drivers/pwm/pwm-dwc.c @@ -196,13 +196,29 @@ static const struct pwm_ops dwc_pwm_ops = { .owner = THIS_MODULE, }; +static struct dwc_pwm *dwc_pwm_alloc(struct device *dev) +{ + struct dwc_pwm *dwc; + + dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); + if (!dwc) + return NULL; + + dwc->chip.dev = dev; + dwc->chip.ops = &dwc_pwm_ops; + dwc->chip.npwm = DWC_TIMERS_TOTAL; + + dev_set_drvdata(dev, dwc); + return dwc; +} + static int dwc_pwm_probe(struct pci_dev *pci, const struct pci_device_id *id) { struct device *dev = &pci->dev; struct dwc_pwm *dwc; int ret; - dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); + dwc = dwc_pwm_alloc(dev); if (!dwc) return -ENOMEM; @@ -226,12 +242,6 @@ static int dwc_pwm_probe(struct pci_dev *pci, const struct pci_device_id *id) return -ENOMEM; } - pci_set_drvdata(pci, dwc); - - dwc->chip.dev = dev; - dwc->chip.ops = &dwc_pwm_ops; - dwc->chip.npwm = DWC_TIMERS_TOTAL; - ret = pwmchip_add(&dwc->chip); if (ret) return ret; From patchwork Thu Oct 20 15:16:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ben Dooks X-Patchwork-Id: 6239 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4242:0:0:0:0:0 with SMTP id s2csp168992wrr; Thu, 20 Oct 2022 08:19:19 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5kGRdPyG99bP3FQzqPnZBIQ7KII/1zPHqL3IcdXSYty+pFoZ0Sw0wUbjXvJbq7RWMc6dS+ X-Received: by 2002:a05:6402:4411:b0:437:b723:72 with SMTP id y17-20020a056402441100b00437b7230072mr12932923eda.38.1666279159181; Thu, 20 Oct 2022 08:19:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666279159; cv=none; d=google.com; s=arc-20160816; b=qib0O+L7qCOhxqzi4JVq7qzpekYySqpjGoYsGSjl2+0Az7XGUU+Gcr5UlDvdAQPDIU iiIsJmm8G5Gcj8mqm0ZdgZcnojP8HbfEVcteLQV53Gusq7l8VlOGngA7KzHqElC2H3fX EVzV4f9mBKgIibzwVcjlz2m2BhBs/rwe277WKJkFKddVDmkJ95o7fOkepTZ4NFTuaVDt odLIlWFMYmB5eL3T+N8v2MGXH8pHwfeADgNaPvzc7i3J63lgcLtA0zDDeI+djysmPrH0 8663gFUIAIm4bQmQI3roUYXm2w1BjLlPaPV+2dZ8lLGl6xIaqVuGEhyjUgQc/T8/QzxA ZMjw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=JVsjMt/QqWDQIkbN9ThQA44X6Q8M6+q3vjfLdgd5aDk=; b=mIaJO5Gk6J8iNDndHJjG6guEBRKdq5FnlwWyb2aRlG6DapUvXEuvl1dY8pHXaRUmxP F/VTiyngbGHh2BOiCI9O6U4aYk6rYndhB4kV1uGTgUwlIfr74PkCid9BjZN0wQLmQkL7 Ztf3C8FHkAkwhO+vV07N33sbkzRvHk3rNYpvbH363PMxM+hvxbJ0Zb24ZNG5GfHc1ucn XavJA7gZ4BIbpUC9yzHBPMnur2FlLMg8YTQOthpf5L9iiXWzkvx1xgjWPTt4d0+W46PS IxbTUJwXByr2GnPxjUG5N2IN6jWLPcbPaqQQg2RmelDP0tYlg2aQod1A1ulYnNtbcSFN EohQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sifive.com header.s=google header.b=iOxGAFmV; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Ben Dooks Reviewed-by: Uwe Kleine-König --- drivers/pwm/pwm-dwc.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/pwm/pwm-dwc.c b/drivers/pwm/pwm-dwc.c index 61f11e0a9319..56cde9da2c0e 100644 --- a/drivers/pwm/pwm-dwc.c +++ b/drivers/pwm/pwm-dwc.c @@ -242,7 +242,7 @@ static int dwc_pwm_probe(struct pci_dev *pci, const struct pci_device_id *id) return -ENOMEM; } - ret = pwmchip_add(&dwc->chip); + ret = devm_pwmchip_add(dev, &dwc->chip); if (ret) return ret; @@ -254,12 +254,8 @@ static int dwc_pwm_probe(struct pci_dev *pci, const struct pci_device_id *id) static void dwc_pwm_remove(struct pci_dev *pci) { - struct dwc_pwm *dwc = pci_get_drvdata(pci); - pm_runtime_forbid(&pci->dev); pm_runtime_get_noresume(&pci->dev); - - pwmchip_remove(&dwc->chip); } #ifdef CONFIG_PM_SLEEP From patchwork Thu Oct 20 15:16:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Dooks X-Patchwork-Id: 6250 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4242:0:0:0:0:0 with SMTP id s2csp170275wrr; Thu, 20 Oct 2022 08:22:00 -0700 (PDT) X-Google-Smtp-Source: AMsMyM61wy9IlrrfY4U3ljiz1LFh4dtP2QsZgU7ugExGZEV4cl+2UV45SwJGi+PzZ8SFm/UzCBBl X-Received: by 2002:a17:903:11cd:b0:170:cde8:18b7 with SMTP id q13-20020a17090311cd00b00170cde818b7mr14487479plh.165.1666279319955; Thu, 20 Oct 2022 08:21:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666279319; cv=none; d=google.com; s=arc-20160816; b=rJ3nvdj+qUV0XnwJ5cfrwuosYhlfFAljj6e/SzHH9OJ+1GMRg+AEC1O/5Xq9KaXcCr VhGDmaVcKZfoWrKSPTxy/PL+osqLwLHVg053WeEl1ztkn12EUF8sy7paaWozXMqn1mTP GcL8nQMSxauPijRSmBN5nnc91s2Fgw5R3WAJCI/phmuax5FBIKVcV+UkOHr17uk24ocg N1XdfuKbQ622waCDXUb3hRHJCH67PHrj92q46KcBpi5+V0m3IGONyyNb7clKAYVJNWcN INSr+K5D8e2mvq/xZUfMlu6owQR7rRwWkGIelO/rUMe79H8KjfpCD0FJ0lWZhn0yowF4 c6ww== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=CrCSKyIIPnCSoamHugpD/e3j+U8pl8ZSDgiJjEnZ55k=; b=LyrKYYA6KraDK+G1Stm1Rm7e+j/uWHphxCLEDnuW94OfvKBUCqQfVXV+FTpuOuofko v0pI1foGGXlVf2lKU7qWNZEPnCXCXMijoL/eQC1Q40hu/d8O+epQH/sZ/yhuNnLaRalG Owt1+DhzS7v+xNSEDajQWRTE6/vDZYXIEyfy1sEY9rjIuUJeo6U1WmAcx9RIemUcAx5l LqC4ITQMr17A8iABE965TYc2iMBashpWKom0lUnBD0d7RFaW6VzO2roO4uINW9BEjYtv Rb4KsKO1MCLJdrtViRl/MiN8Kda97dfPtdg6n3YXYCZhRrzrLFG4V2XtpKvbV52UspYq GSeA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sifive.com header.s=google header.b=RbDNo5ks; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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This is partly due to the module_driver() code only being allowed once in a module and also to avoid a number of #ifdef if we build a single file in a system without pci support. Signed-off-by: Ben Dooks --- v6: - put DWC_PERIOD_NS back to avoid bisect issues v4: - removed DWC_PERIOD_NS as not needed --- drivers/pwm/Kconfig | 14 +++- drivers/pwm/Makefile | 1 + drivers/pwm/pwm-dwc-pci.c | 133 ++++++++++++++++++++++++++++++++ drivers/pwm/pwm-dwc.c | 158 +------------------------------------- drivers/pwm/pwm-dwc.h | 58 ++++++++++++++ 5 files changed, 207 insertions(+), 157 deletions(-) create mode 100644 drivers/pwm/pwm-dwc-pci.c create mode 100644 drivers/pwm/pwm-dwc.h diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 3f3c53af4a56..a9f1c554db2b 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -175,15 +175,23 @@ config PWM_CROS_EC Controller. config PWM_DWC - tristate "DesignWare PWM Controller" - depends on PCI || COMPILE_TEST + tristate "DesignWare PWM Controller core" depends on HAS_IOMEM help - PWM driver for Synopsys DWC PWM Controller attached to a PCI bus. + PWM driver for Synopsys DWC PWM Controller. To compile this driver as a module, choose M here: the module will be called pwm-dwc. +config PWM_DWC_PCI + tristate "DesignWare PWM Controller core" + depends on PWM_DWC && HAS_IOMEM && PCI + help + PWM driver for Synopsys DWC PWM Controller attached to a PCI bus. + + To compile this driver as a module, choose M here: the module + will be called pwm-dwc-pci. + config PWM_EP93XX tristate "Cirrus Logic EP93xx PWM support" depends on ARCH_EP93XX || COMPILE_TEST diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 7bf1a29f02b8..a70d36623129 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_PWM_CLPS711X) += pwm-clps711x.o obj-$(CONFIG_PWM_CRC) += pwm-crc.o obj-$(CONFIG_PWM_CROS_EC) += pwm-cros-ec.o obj-$(CONFIG_PWM_DWC) += pwm-dwc.o +obj-$(CONFIG_PWM_DWC_PCI) += pwm-dwc-pci.o obj-$(CONFIG_PWM_EP93XX) += pwm-ep93xx.o obj-$(CONFIG_PWM_FSL_FTM) += pwm-fsl-ftm.o obj-$(CONFIG_PWM_HIBVT) += pwm-hibvt.o diff --git a/drivers/pwm/pwm-dwc-pci.c b/drivers/pwm/pwm-dwc-pci.c new file mode 100644 index 000000000000..2213d0e7f3c8 --- /dev/null +++ b/drivers/pwm/pwm-dwc-pci.c @@ -0,0 +1,133 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DesignWare PWM Controller driver (PCI part) + * + * Copyright (C) 2018-2020 Intel Corporation + * + * Author: Felipe Balbi (Intel) + * Author: Jarkko Nikula + * Author: Raymond Tan + * + * Limitations: + * - The hardware cannot generate a 0 % or 100 % duty cycle. Both high and low + * periods are one or more input clock periods long. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "pwm-dwc.h" + +static int dwc_pwm_probe(struct pci_dev *pci, const struct pci_device_id *id) +{ + struct device *dev = &pci->dev; + struct dwc_pwm *dwc; + int ret; + + dwc = dwc_pwm_alloc(dev); + if (!dwc) + return -ENOMEM; + + ret = pcim_enable_device(pci); + if (ret) { + dev_err(dev, "Failed to enable device (%pe)\n", ERR_PTR(ret)); + return ret; + } + + pci_set_master(pci); + + ret = pcim_iomap_regions(pci, BIT(0), pci_name(pci)); + if (ret) { + dev_err(dev, "Failed to iomap PCI BAR (%pe)\n", ERR_PTR(ret)); + return ret; + } + + dwc->base = pcim_iomap_table(pci)[0]; + if (!dwc->base) { + dev_err(dev, "Base address missing\n"); + return -ENOMEM; + } + + ret = devm_pwmchip_add(dev, &dwc->chip); + if (ret) + return ret; + + pm_runtime_put(dev); + pm_runtime_allow(dev); + + return 0; +} + +static void dwc_pwm_remove(struct pci_dev *pci) +{ + pm_runtime_forbid(&pci->dev); + pm_runtime_get_noresume(&pci->dev); +} + +#ifdef CONFIG_PM_SLEEP +static int dwc_pwm_suspend(struct device *dev) +{ + struct pci_dev *pdev = container_of(dev, struct pci_dev, dev); + struct dwc_pwm *dwc = pci_get_drvdata(pdev); + int i; + + for (i = 0; i < DWC_TIMERS_TOTAL; i++) { + if (dwc->chip.pwms[i].state.enabled) { + dev_err(dev, "PWM %u in use by consumer (%s)\n", + i, dwc->chip.pwms[i].label); + return -EBUSY; + } + dwc->ctx[i].cnt = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(i)); + dwc->ctx[i].cnt2 = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(i)); + dwc->ctx[i].ctrl = dwc_pwm_readl(dwc, DWC_TIM_CTRL(i)); + } + + return 0; +} + +static int dwc_pwm_resume(struct device *dev) +{ + struct pci_dev *pdev = container_of(dev, struct pci_dev, dev); + struct dwc_pwm *dwc = pci_get_drvdata(pdev); + int i; + + for (i = 0; i < DWC_TIMERS_TOTAL; i++) { + dwc_pwm_writel(dwc, dwc->ctx[i].cnt, DWC_TIM_LD_CNT(i)); + dwc_pwm_writel(dwc, dwc->ctx[i].cnt2, DWC_TIM_LD_CNT2(i)); + dwc_pwm_writel(dwc, dwc->ctx[i].ctrl, DWC_TIM_CTRL(i)); + } + + return 0; +} +#endif + +static SIMPLE_DEV_PM_OPS(dwc_pwm_pm_ops, dwc_pwm_suspend, dwc_pwm_resume); + +static const struct pci_device_id dwc_pwm_id_table[] = { + { PCI_VDEVICE(INTEL, 0x4bb7) }, /* Elkhart Lake */ + { } /* Terminating Entry */ +}; +MODULE_DEVICE_TABLE(pci, dwc_pwm_id_table); + +static struct pci_driver dwc_pwm_driver = { + .name = "pwm-dwc", + .probe = dwc_pwm_probe, + .remove = dwc_pwm_remove, + .id_table = dwc_pwm_id_table, + .driver = { + .pm = &dwc_pwm_pm_ops, + }, +}; + +module_pci_driver(dwc_pwm_driver); + +MODULE_AUTHOR("Felipe Balbi (Intel)"); +MODULE_AUTHOR("Jarkko Nikula "); +MODULE_AUTHOR("Raymond Tan "); +MODULE_DESCRIPTION("DesignWare PWM Controller"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pwm/pwm-dwc.c b/drivers/pwm/pwm-dwc.c index 56cde9da2c0e..90a8ae1252a1 100644 --- a/drivers/pwm/pwm-dwc.c +++ b/drivers/pwm/pwm-dwc.c @@ -1,16 +1,12 @@ // SPDX-License-Identifier: GPL-2.0 /* - * DesignWare PWM Controller driver + * DesignWare PWM Controller driver core * * Copyright (C) 2018-2020 Intel Corporation * * Author: Felipe Balbi (Intel) * Author: Jarkko Nikula * Author: Raymond Tan - * - * Limitations: - * - The hardware cannot generate a 0 % or 100 % duty cycle. Both high and low - * periods are one or more input clock periods long. */ #include @@ -21,51 +17,7 @@ #include #include -#define DWC_TIM_LD_CNT(n) ((n) * 0x14) -#define DWC_TIM_LD_CNT2(n) (((n) * 4) + 0xb0) -#define DWC_TIM_CUR_VAL(n) (((n) * 0x14) + 0x04) -#define DWC_TIM_CTRL(n) (((n) * 0x14) + 0x08) -#define DWC_TIM_EOI(n) (((n) * 0x14) + 0x0c) -#define DWC_TIM_INT_STS(n) (((n) * 0x14) + 0x10) - -#define DWC_TIMERS_INT_STS 0xa0 -#define DWC_TIMERS_EOI 0xa4 -#define DWC_TIMERS_RAW_INT_STS 0xa8 -#define DWC_TIMERS_COMP_VERSION 0xac - -#define DWC_TIMERS_TOTAL 8 -#define DWC_CLK_PERIOD_NS 10 - -/* Timer Control Register */ -#define DWC_TIM_CTRL_EN BIT(0) -#define DWC_TIM_CTRL_MODE BIT(1) -#define DWC_TIM_CTRL_MODE_FREE (0 << 1) -#define DWC_TIM_CTRL_MODE_USER (1 << 1) -#define DWC_TIM_CTRL_INT_MASK BIT(2) -#define DWC_TIM_CTRL_PWM BIT(3) - -struct dwc_pwm_ctx { - u32 cnt; - u32 cnt2; - u32 ctrl; -}; - -struct dwc_pwm { - struct pwm_chip chip; - void __iomem *base; - struct dwc_pwm_ctx ctx[DWC_TIMERS_TOTAL]; -}; -#define to_dwc_pwm(p) (container_of((p), struct dwc_pwm, chip)) - -static inline u32 dwc_pwm_readl(struct dwc_pwm *dwc, u32 offset) -{ - return readl(dwc->base + offset); -} - -static inline void dwc_pwm_writel(struct dwc_pwm *dwc, u32 value, u32 offset) -{ - writel(value, dwc->base + offset); -} +#include "pwm-dwc.h" static void __dwc_pwm_set_enable(struct dwc_pwm *dwc, int pwm, int enabled) { @@ -196,7 +148,7 @@ static const struct pwm_ops dwc_pwm_ops = { .owner = THIS_MODULE, }; -static struct dwc_pwm *dwc_pwm_alloc(struct device *dev) +struct dwc_pwm *dwc_pwm_alloc(struct device *dev) { struct dwc_pwm *dwc; @@ -211,109 +163,7 @@ static struct dwc_pwm *dwc_pwm_alloc(struct device *dev) dev_set_drvdata(dev, dwc); return dwc; } - -static int dwc_pwm_probe(struct pci_dev *pci, const struct pci_device_id *id) -{ - struct device *dev = &pci->dev; - struct dwc_pwm *dwc; - int ret; - - dwc = dwc_pwm_alloc(dev); - if (!dwc) - return -ENOMEM; - - ret = pcim_enable_device(pci); - if (ret) { - dev_err(dev, "Failed to enable device (%pe)\n", ERR_PTR(ret)); - return ret; - } - - pci_set_master(pci); - - ret = pcim_iomap_regions(pci, BIT(0), pci_name(pci)); - if (ret) { - dev_err(dev, "Failed to iomap PCI BAR (%pe)\n", ERR_PTR(ret)); - return ret; - } - - dwc->base = pcim_iomap_table(pci)[0]; - if (!dwc->base) { - dev_err(dev, "Base address missing\n"); - return -ENOMEM; - } - - ret = devm_pwmchip_add(dev, &dwc->chip); - if (ret) - return ret; - - pm_runtime_put(dev); - pm_runtime_allow(dev); - - return 0; -} - -static void dwc_pwm_remove(struct pci_dev *pci) -{ - pm_runtime_forbid(&pci->dev); - pm_runtime_get_noresume(&pci->dev); -} - -#ifdef CONFIG_PM_SLEEP -static int dwc_pwm_suspend(struct device *dev) -{ - struct pci_dev *pdev = container_of(dev, struct pci_dev, dev); - struct dwc_pwm *dwc = pci_get_drvdata(pdev); - int i; - - for (i = 0; i < DWC_TIMERS_TOTAL; i++) { - if (dwc->chip.pwms[i].state.enabled) { - dev_err(dev, "PWM %u in use by consumer (%s)\n", - i, dwc->chip.pwms[i].label); - return -EBUSY; - } - dwc->ctx[i].cnt = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(i)); - dwc->ctx[i].cnt2 = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(i)); - dwc->ctx[i].ctrl = dwc_pwm_readl(dwc, DWC_TIM_CTRL(i)); - } - - return 0; -} - -static int dwc_pwm_resume(struct device *dev) -{ - struct pci_dev *pdev = container_of(dev, struct pci_dev, dev); - struct dwc_pwm *dwc = pci_get_drvdata(pdev); - int i; - - for (i = 0; i < DWC_TIMERS_TOTAL; i++) { - dwc_pwm_writel(dwc, dwc->ctx[i].cnt, DWC_TIM_LD_CNT(i)); - dwc_pwm_writel(dwc, dwc->ctx[i].cnt2, DWC_TIM_LD_CNT2(i)); - dwc_pwm_writel(dwc, dwc->ctx[i].ctrl, DWC_TIM_CTRL(i)); - } - - return 0; -} -#endif - -static SIMPLE_DEV_PM_OPS(dwc_pwm_pm_ops, dwc_pwm_suspend, dwc_pwm_resume); - -static const struct pci_device_id dwc_pwm_id_table[] = { - { PCI_VDEVICE(INTEL, 0x4bb7) }, /* Elkhart Lake */ - { } /* Terminating Entry */ -}; -MODULE_DEVICE_TABLE(pci, dwc_pwm_id_table); - -static struct pci_driver dwc_pwm_driver = { - .name = "pwm-dwc", - .probe = dwc_pwm_probe, - .remove = dwc_pwm_remove, - .id_table = dwc_pwm_id_table, - .driver = { - .pm = &dwc_pwm_pm_ops, - }, -}; - -module_pci_driver(dwc_pwm_driver); +EXPORT_SYMBOL_GPL(dwc_pwm_alloc); MODULE_AUTHOR("Felipe Balbi (Intel)"); MODULE_AUTHOR("Jarkko Nikula "); diff --git a/drivers/pwm/pwm-dwc.h b/drivers/pwm/pwm-dwc.h new file mode 100644 index 000000000000..68f98eb76152 --- /dev/null +++ b/drivers/pwm/pwm-dwc.h @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DesignWare PWM Controller driver + * + * Copyright (C) 2018-2020 Intel Corporation + * + * Author: Felipe Balbi (Intel) + * Author: Jarkko Nikula + * Author: Raymond Tan + */ + +#define DWC_TIM_LD_CNT(n) ((n) * 0x14) +#define DWC_TIM_LD_CNT2(n) (((n) * 4) + 0xb0) +#define DWC_TIM_CUR_VAL(n) (((n) * 0x14) + 0x04) +#define DWC_TIM_CTRL(n) (((n) * 0x14) + 0x08) +#define DWC_TIM_EOI(n) (((n) * 0x14) + 0x0c) +#define DWC_TIM_INT_STS(n) (((n) * 0x14) + 0x10) + +#define DWC_TIMERS_INT_STS 0xa0 +#define DWC_TIMERS_EOI 0xa4 +#define DWC_TIMERS_RAW_INT_STS 0xa8 +#define DWC_TIMERS_COMP_VERSION 0xac + +#define DWC_TIMERS_TOTAL 8 +#define DWC_CLK_PERIOD_NS 10 + +/* Timer Control Register */ +#define DWC_TIM_CTRL_EN BIT(0) +#define DWC_TIM_CTRL_MODE BIT(1) +#define DWC_TIM_CTRL_MODE_FREE (0 << 1) +#define DWC_TIM_CTRL_MODE_USER (1 << 1) +#define DWC_TIM_CTRL_INT_MASK BIT(2) +#define DWC_TIM_CTRL_PWM BIT(3) + +struct dwc_pwm_ctx { + u32 cnt; + u32 cnt2; + u32 ctrl; +}; + +struct dwc_pwm { + struct pwm_chip chip; + void __iomem *base; + struct dwc_pwm_ctx ctx[DWC_TIMERS_TOTAL]; +}; +#define to_dwc_pwm(p) (container_of((p), struct dwc_pwm, chip)) + +static inline u32 dwc_pwm_readl(struct dwc_pwm *dwc, u32 offset) +{ + return readl(dwc->base + offset); +} + +static inline void dwc_pwm_writel(struct dwc_pwm *dwc, u32 value, u32 offset) +{ + writel(value, dwc->base + offset); +} + +extern struct dwc_pwm *dwc_pwm_alloc(struct device *dev); From patchwork Thu Oct 20 15:16:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Dooks X-Patchwork-Id: 6240 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4242:0:0:0:0:0 with SMTP id s2csp169122wrr; Thu, 20 Oct 2022 08:19:31 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6QgZZNjvehTKX2HLwSYUUtwF0ja4px/r+Wb0iYbM4YFemyfrWOq6Zz4GSLOEHmeASmNXkN X-Received: by 2002:a05:6a00:4c84:b0:562:ed08:599a with SMTP id eb4-20020a056a004c8400b00562ed08599amr14631434pfb.64.1666279171247; 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Signed-off-by: Ben Dooks --- v6: - removed DWC_CLK_PERIOD_NS as it is now not needed v4: - moved earlier before the of changes to make the of changes one patch v2: - removed the ifdef and merged the other clock patch in here --- drivers/pwm/pwm-dwc-pci.c | 1 + drivers/pwm/pwm-dwc.c | 10 ++++++---- drivers/pwm/pwm-dwc.h | 3 ++- 3 files changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/pwm/pwm-dwc-pci.c b/drivers/pwm/pwm-dwc-pci.c index 2213d0e7f3c8..949423e368f9 100644 --- a/drivers/pwm/pwm-dwc-pci.c +++ b/drivers/pwm/pwm-dwc-pci.c @@ -20,6 +20,7 @@ #include #include #include +#include #include "pwm-dwc.h" diff --git a/drivers/pwm/pwm-dwc.c b/drivers/pwm/pwm-dwc.c index 90a8ae1252a1..1251620ab771 100644 --- a/drivers/pwm/pwm-dwc.c +++ b/drivers/pwm/pwm-dwc.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include @@ -47,13 +48,13 @@ static int __dwc_pwm_configure_timer(struct dwc_pwm *dwc, * periods and check are the result within HW limits between 1 and * 2^32 periods. */ - tmp = DIV_ROUND_CLOSEST_ULL(state->duty_cycle, DWC_CLK_PERIOD_NS); + tmp = DIV_ROUND_CLOSEST_ULL(state->duty_cycle, dwc->clk_ns); if (tmp < 1 || tmp > (1ULL << 32)) return -ERANGE; low = tmp - 1; tmp = DIV_ROUND_CLOSEST_ULL(state->period - state->duty_cycle, - DWC_CLK_PERIOD_NS); + dwc->clk_ns); if (tmp < 1 || tmp > (1ULL << 32)) return -ERANGE; high = tmp - 1; @@ -128,12 +129,12 @@ static void dwc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, duty = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(pwm->hwpwm)); duty += 1; - duty *= DWC_CLK_PERIOD_NS; + duty *= dwc->clk_ns; state->duty_cycle = duty; period = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(pwm->hwpwm)); period += 1; - period *= DWC_CLK_PERIOD_NS; + period *= dwc->clk_ns; period += duty; state->period = period; @@ -156,6 +157,7 @@ struct dwc_pwm *dwc_pwm_alloc(struct device *dev) if (!dwc) return NULL; + dwc->clk_ns = 10; dwc->chip.dev = dev; dwc->chip.ops = &dwc_pwm_ops; dwc->chip.npwm = DWC_TIMERS_TOTAL; diff --git a/drivers/pwm/pwm-dwc.h b/drivers/pwm/pwm-dwc.h index 68f98eb76152..dc451cb2eff5 100644 --- a/drivers/pwm/pwm-dwc.h +++ b/drivers/pwm/pwm-dwc.h @@ -22,7 +22,6 @@ #define DWC_TIMERS_COMP_VERSION 0xac #define DWC_TIMERS_TOTAL 8 -#define DWC_CLK_PERIOD_NS 10 /* Timer Control Register */ #define DWC_TIM_CTRL_EN BIT(0) @@ -41,6 +40,8 @@ struct dwc_pwm_ctx { struct dwc_pwm { struct pwm_chip chip; void __iomem *base; + struct clk *clk; + unsigned int clk_ns; struct dwc_pwm_ctx ctx[DWC_TIMERS_TOTAL]; }; #define to_dwc_pwm(p) (container_of((p), struct dwc_pwm, chip)) From patchwork Thu Oct 20 15:16:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Dooks X-Patchwork-Id: 6241 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4242:0:0:0:0:0 with SMTP id s2csp169210wrr; Thu, 20 Oct 2022 08:19:43 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6LFekn0mPb2DfwvUIL2gQXq6FLk42GAEN1i4cBNgH2Emu2tDkiUQCkzQ+odNAYR6DRhZt5 X-Received: by 2002:a17:902:c952:b0:183:6e51:4fa with SMTP id i18-20020a170902c95200b001836e5104famr14842539pla.42.1666279183142; Thu, 20 Oct 2022 08:19:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666279183; cv=none; d=google.com; s=arc-20160816; b=NmLcV9owj3direoUF8/1A0+4Cxq3rNMpKn6cpHQKD0Stc4BOqwfKJ7f5cizD8Xoiny Yai5ZSg55ExlL5OuDveE6IRaztfvCUh3l5WjPi1r98cXPzNfSs1sQG6gTAczZgFV3lMi tPRskywt4WLtJp0bjIWq1ACwUnweio39m79np+/I9VCqXaSdXUJ7OnzVnnma0U0soE3x xvaxxcXivuUOWazAXwmG9ZrN7i+1ofWe1UeyaSRQg24unLZl/L19QmZ5qArLNRUjiZUT AcbNsuiOlVI931e6p4r3MsUkXusjzwo670lRcRVza9KNoiOb2rnNEq8Vs4r3Sqp6ImO4 k4gQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=bZarqMDc/6hKea1bOExuvbbOHo7DHkLG1khhfpxmIGM=; b=MY3AT0UW070dfjS2XjdIFqdHlAsbAJby4lG3g+Mu6w63dn1m3oAnB+7zsFqCrQjtzO qa2fzc+ag5KMb+nvTPbUXssGFike7ZxF53BB9ZD9T7vaoL1UFdQ9eGlF0JRjlG+dtMWQ 0I1keUxmWtJv3s16EkM0rHA/YkKaejiJb7AruZ3vZDi5+SyZ2mtexjO4PAxoTKcJaUI8 lR3B8H082lwa2kC/DLRwx74pRlWT+xSXJUFB8BuKZ3IDB+4pBE0tBO2ZkqqmqYD6MZsI 2CQOGWz//LEj8wnAKxrt/lQPtZbyc8yA3+P+u/yIRCDTo0bgTZ19M4DoCk7clnlKack7 PovA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sifive.com header.s=google header.b=kUl9Fn1q; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Ben Dooks --- v5: - fix missing " in kconfig - remove .remove method, devm already sorts this. - merge pwm-number code - split the of code out of the core - get bus clock v4: - moved the compile test code earlier - fixed review comments - used NS_PER_SEC - use devm_clk_get_enabled - ensure we get the bus clock v3: - changed compatible name fixup add pwm/Kconfig --- drivers/pwm/Kconfig | 9 +++++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-dwc-of.c | 76 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 86 insertions(+) create mode 100644 drivers/pwm/pwm-dwc-of.c diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index a9f1c554db2b..c734f58a8bfc 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -192,6 +192,15 @@ config PWM_DWC_PCI To compile this driver as a module, choose M here: the module will be called pwm-dwc-pci. +config PWM_DWC_OF + tristate "DesignWare PWM Controller (OF bus)" + depends on PWM_DWC && OF + help + PWM driver for Synopsys DWC PWM Controller on an OF bus. + + To compile this driver as a module, choose M here: the module + will be called pwm-dwc-of. + config PWM_EP93XX tristate "Cirrus Logic EP93xx PWM support" depends on ARCH_EP93XX || COMPILE_TEST diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index a70d36623129..d1fd1641f077 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_PWM_CLPS711X) += pwm-clps711x.o obj-$(CONFIG_PWM_CRC) += pwm-crc.o obj-$(CONFIG_PWM_CROS_EC) += pwm-cros-ec.o obj-$(CONFIG_PWM_DWC) += pwm-dwc.o +obj-$(CONFIG_PWM_DWC_OF) += pwm-dwc-of.o obj-$(CONFIG_PWM_DWC_PCI) += pwm-dwc-pci.o obj-$(CONFIG_PWM_EP93XX) += pwm-ep93xx.o obj-$(CONFIG_PWM_FSL_FTM) += pwm-fsl-ftm.o diff --git a/drivers/pwm/pwm-dwc-of.c b/drivers/pwm/pwm-dwc-of.c new file mode 100644 index 000000000000..c5b4351cc7b0 --- /dev/null +++ b/drivers/pwm/pwm-dwc-of.c @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DesignWare PWM Controller driver OF + * + * Copyright (C) 2022 SiFive, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pwm-dwc.h" + +static int dwc_pwm_plat_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct dwc_pwm *dwc; + struct clk *bus; + u32 nr_pwm; + + dwc = dwc_pwm_alloc(dev); + if (!dwc) + return -ENOMEM; + + if (!device_property_read_u32(dev, "snps,pwm-number", &nr_pwm)) { + if (nr_pwm > DWC_TIMERS_TOTAL) + dev_err(dev, "too many PWMs (%d) specified, capping at %d\n", + nr_pwm, dwc->chip.npwm); + else + dwc->chip.npwm = nr_pwm; + } + + dwc->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(dwc->base)) + return PTR_ERR(dwc->base); + + bus = devm_clk_get_enabled(dev, NULL); + if (IS_ERR(bus)) + return dev_err_probe(dev, PTR_ERR(bus), + "failed to get clock\n"); + + dwc->clk = devm_clk_get_enabled(dev, "timer"); + if (IS_ERR(dwc->clk)) + return dev_err_probe(dev, PTR_ERR(dwc->clk), + "failed to get timer clock\n"); + + dwc->clk_ns = NSEC_PER_SEC / clk_get_rate(dwc->clk); + return devm_pwmchip_add(dev, &dwc->chip); +} + +static const struct of_device_id dwc_pwm_dt_ids[] = { + { .compatible = "snps,dw-apb-timers-pwm2" }, + { }, +}; +MODULE_DEVICE_TABLE(of, dwc_pwm_dt_ids); + +static struct platform_driver dwc_pwm_plat_driver = { + .driver = { + .name = "dwc-pwm", + .of_match_table = dwc_pwm_dt_ids, + }, + .probe = dwc_pwm_plat_probe, +}; + +module_platform_driver(dwc_pwm_plat_driver); + +MODULE_ALIAS("platform:dwc-pwm-of"); +MODULE_AUTHOR("Ben Dooks "); +MODULE_DESCRIPTION("DesignWare PWM Controller"); +MODULE_LICENSE("GPL"); From patchwork Thu Oct 20 15:16:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Dooks X-Patchwork-Id: 6251 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4242:0:0:0:0:0 with SMTP id s2csp170526wrr; Thu, 20 Oct 2022 08:22:32 -0700 (PDT) X-Google-Smtp-Source: AMsMyM48s4LKNN1C6uMbmYXnNTEsPZbQfYR+yuSchx7uJVklXfRyroTRICsqqmtstEqZFWR/fKlp X-Received: by 2002:a17:90b:3755:b0:20d:9df4:be01 with SMTP id ne21-20020a17090b375500b0020d9df4be01mr16570643pjb.51.1666279352603; Thu, 20 Oct 2022 08:22:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666279352; 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Add a check for the PWM mode in dwc_pwm_get_state() and if DWC_TIM_CTRL_PWM is not set, then return a 50% cycle. This may only be an issue on initialisation, as the rest of the code currently assumes we're always going to have the extended PWM mode using two counters. Signed-off-by: Ben Dooks --- v4: - fixed review comment on mulit-line calculations --- drivers/pwm/pwm-dwc.c | 29 ++++++++++++++++++----------- 1 file changed, 18 insertions(+), 11 deletions(-) diff --git a/drivers/pwm/pwm-dwc.c b/drivers/pwm/pwm-dwc.c index 1251620ab771..5ef0fe7ea3e9 100644 --- a/drivers/pwm/pwm-dwc.c +++ b/drivers/pwm/pwm-dwc.c @@ -121,23 +121,30 @@ static void dwc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, { struct dwc_pwm *dwc = to_dwc_pwm(chip); u64 duty, period; + u32 ctrl, ld, ld2; pm_runtime_get_sync(chip->dev); - state->enabled = !!(dwc_pwm_readl(dwc, - DWC_TIM_CTRL(pwm->hwpwm)) & DWC_TIM_CTRL_EN); + ctrl = dwc_pwm_readl(dwc, DWC_TIM_CTRL(pwm->hwpwm)); + ld = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(pwm->hwpwm)); + ld2 = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(pwm->hwpwm)); - duty = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(pwm->hwpwm)); - duty += 1; - duty *= dwc->clk_ns; - state->duty_cycle = duty; + state->enabled = !!(ctrl & DWC_TIM_CTRL_EN); - period = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(pwm->hwpwm)); - period += 1; - period *= dwc->clk_ns; - period += duty; - state->period = period; + /* If we're not in PWM, technically the output is a 50-50 + * based on the timer load-count only. + */ + if (ctrl & DWC_TIM_CTRL_PWM) { + duty = (ld + 1) * dwc->clk_ns; + period = (ld2 + 1) * dwc->clk_ns; + period += duty; + } else { + duty = (ld + 1) * dwc->clk_ns; + period = duty * 2; + } + state->period = period; + state->duty_cycle = duty; state->polarity = PWM_POLARITY_INVERSED; pm_runtime_put_sync(chip->dev); From patchwork Thu Oct 20 15:16:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ben Dooks X-Patchwork-Id: 6245 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4242:0:0:0:0:0 with SMTP id s2csp169668wrr; Thu, 20 Oct 2022 08:20:41 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5DO/ZtlFsmbT6IZ/tEPMllO7NPwtmDiglchrkqRBuIAdEuDMesJQJQdtNWZRkR4aAZcBCM X-Received: by 2002:a17:907:6095:b0:78d:bb0b:c34d with SMTP id ht21-20020a170907609500b0078dbb0bc34dmr11320768ejc.662.1666279241626; Thu, 20 Oct 2022 08:20:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666279241; cv=none; d=google.com; s=arc-20160816; b=H8zuIl5kPdqTqBx2UTa+IZTeLWNDo02s/Asu5moLJW/HFBO4D3FzUpggVyXcLAWVP+ xqoYKt9JG0ZFh0Hw/we1lhK2oqzswoCZiSIpzF5SlsVTM0kovSxkniM3krhy2NuIiWxt hQ5C0tPyc4kb7VjOkacx9XdZJTvkrI1K39tbdGkReiTaxiDyJi6L8tkNE26FBhIm5i9S CZhk7QFX2g7B/A8k9W77V8hbVtUxyE+s18iEsPVKRDW/WtiTurxkQW/7vWo98G1dEM4y mhVOvF6c9CrCHCNOdb15YtmwzeOCr642m+xl7NpU5BzWAYuCGM+unkhxZKQGL/w9k+AI xMFQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=MuQJZUiYgsrv6ydPrE/ryH64TRoc2yWi4dM3ARWJNR4=; b=aeBVXkv5SURb6cu+XDCwhFLKiKuE+cWR39ZfOsbbiznhdORXmmD7eyAM8K6z+uKdGH 5QR3q+9mdNgGga9KMXtol1PSwO9SRrI4RhZm6/eT3c6304tKen7ntcNaK4ft8CgxWVXo dIhX+BRwlNT1Utw1ENH1oDfuOWEqRik/8Tq1fMP4rkfwrpPXRiwHLuOsQlFxTgTaEMan KuLTkFSke5JGuXEygvFDh3KIi+o6ngxvJRB2N1ekXMAJdFlrJ1+c4L9Iy0DjAp0IauO+ 9LYzT1rJrsDNF8R9zGbAxSZO+wA4BfujjLdd2/h70dYeuaoD0K9wffbyLEnYJJ005H7P sCfw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sifive.com header.s=google header.b=OpNhgpcg; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by; Ben Dooks Reported-by: Uwe Kleine-König --- drivers/pwm/pwm-dwc-of.c | 2 +- drivers/pwm/pwm-dwc.c | 29 ++++++++++++++++++++--------- drivers/pwm/pwm-dwc.h | 2 +- 3 files changed, 22 insertions(+), 11 deletions(-) diff --git a/drivers/pwm/pwm-dwc-of.c b/drivers/pwm/pwm-dwc-of.c index c5b4351cc7b0..5f7f066859d4 100644 --- a/drivers/pwm/pwm-dwc-of.c +++ b/drivers/pwm/pwm-dwc-of.c @@ -50,7 +50,7 @@ static int dwc_pwm_plat_probe(struct platform_device *pdev) return dev_err_probe(dev, PTR_ERR(dwc->clk), "failed to get timer clock\n"); - dwc->clk_ns = NSEC_PER_SEC / clk_get_rate(dwc->clk); + dwc->clk_rate = clk_get_rate(dwc->clk); return devm_pwmchip_add(dev, &dwc->chip); } diff --git a/drivers/pwm/pwm-dwc.c b/drivers/pwm/pwm-dwc.c index 5ef0fe7ea3e9..f48a6245a3b5 100644 --- a/drivers/pwm/pwm-dwc.c +++ b/drivers/pwm/pwm-dwc.c @@ -43,18 +43,22 @@ static int __dwc_pwm_configure_timer(struct dwc_pwm *dwc, u32 high; u32 low; + if (dwc->clk) + dwc->clk_rate = clk_get_rate(dwc->clk); + /* * Calculate width of low and high period in terms of input clock * periods and check are the result within HW limits between 1 and * 2^32 periods. */ - tmp = DIV_ROUND_CLOSEST_ULL(state->duty_cycle, dwc->clk_ns); + tmp = state->duty_cycle * dwc->clk_rate; + tmp = DIV_ROUND_CLOSEST_ULL(tmp, NSEC_PER_SEC); if (tmp < 1 || tmp > (1ULL << 32)) return -ERANGE; low = tmp - 1; - tmp = DIV_ROUND_CLOSEST_ULL(state->period - state->duty_cycle, - dwc->clk_ns); + tmp = (state->period - state->duty_cycle) * dwc->clk_rate; + tmp = DIV_ROUND_CLOSEST_ULL(tmp, NSEC_PER_SEC); if (tmp < 1 || tmp > (1ULL << 32)) return -ERANGE; high = tmp - 1; @@ -120,6 +124,7 @@ static void dwc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, struct pwm_state *state) { struct dwc_pwm *dwc = to_dwc_pwm(chip); + unsigned long clk_rate; u64 duty, period; u32 ctrl, ld, ld2; @@ -129,22 +134,28 @@ static void dwc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, ld = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(pwm->hwpwm)); ld2 = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(pwm->hwpwm)); + if (dwc->clk) + dwc->clk_rate = clk_get_rate(dwc->clk); + + clk_rate = dwc->clk_rate; state->enabled = !!(ctrl & DWC_TIM_CTRL_EN); /* If we're not in PWM, technically the output is a 50-50 * based on the timer load-count only. */ if (ctrl & DWC_TIM_CTRL_PWM) { - duty = (ld + 1) * dwc->clk_ns; - period = (ld2 + 1) * dwc->clk_ns; + duty = ld + 1; + period = ld2 + 1; period += duty; } else { - duty = (ld + 1) * dwc->clk_ns; + duty = ld + 1; period = duty * 2; } - state->period = period; - state->duty_cycle = duty; + duty *= NSEC_PER_SEC; + period *= NSEC_PER_SEC; + state->period = DIV_ROUND_CLOSEST_ULL(period, clk_rate); + state->duty_cycle = DIV_ROUND_CLOSEST_ULL(duty, clk_rate); state->polarity = PWM_POLARITY_INVERSED; pm_runtime_put_sync(chip->dev); @@ -164,7 +175,7 @@ struct dwc_pwm *dwc_pwm_alloc(struct device *dev) if (!dwc) return NULL; - dwc->clk_ns = 10; + dwc->clk_rate = NSEC_PER_SEC / 10; dwc->chip.dev = dev; dwc->chip.ops = &dwc_pwm_ops; dwc->chip.npwm = DWC_TIMERS_TOTAL; diff --git a/drivers/pwm/pwm-dwc.h b/drivers/pwm/pwm-dwc.h index dc451cb2eff5..19bdc2224690 100644 --- a/drivers/pwm/pwm-dwc.h +++ b/drivers/pwm/pwm-dwc.h @@ -41,7 +41,7 @@ struct dwc_pwm { struct pwm_chip chip; void __iomem *base; struct clk *clk; - unsigned int clk_ns; + unsigned long clk_rate; struct dwc_pwm_ctx ctx[DWC_TIMERS_TOTAL]; }; #define to_dwc_pwm(p) (container_of((p), struct dwc_pwm, chip))