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[83.9.3.225]) by smtp.gmail.com with ESMTPSA id f4-20020a2e3804000000b0029ad1fc89b3sm5189658lja.60.2023.03.29.12.17.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Mar 2023 12:17:37 -0700 (PDT) From: Konrad Dybcio Date: Wed, 29 Mar 2023 21:17:28 +0200 Subject: [PATCH 1/4] arm64: dts: qcom: msm8998: Improve GPU OPP table MIME-Version: 1.0 Message-Id: <20230329-topic-adreno_opp-v1-1-24d34ac6f007@linaro.org> References: <20230329-topic-adreno_opp-v1-0-24d34ac6f007@linaro.org> In-Reply-To: <20230329-topic-adreno_opp-v1-0-24d34ac6f007@linaro.org> To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , AngeloGioacchino Del Regno , Jordan Crouse , Srinivas Kandagatla , Vivek Gautam , Vinod Koul , Rob Clark , Stephen Boyd Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Andy Gross , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680117452; l=3231; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=BuTOgjCT81kJFbrqBabPtOTaRvqV7WCYi0kTMwbrGyM=; b=sIueiwaBv29WZYicIP/gR6f1I5FJrtIi4R/EoqLoj5R6f4Cpwk3nADWHqIKjdyJsZQNZ5nsG2rgH BOk3yWWuDdxPFGzt0xsYbCEE08QXV0aCsCc9Zw/ZrDReYpsf8AdS X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761731225011339907?= X-GMAIL-MSGID: =?utf-8?q?1761731225011339907?= Add a newline before the first OPP subnode, remove useless opp-supported-hw (there's only a single speed bin anyway) and replace opp-level with required-opps to make sure the power domain level is actually set, as opp-level is not the right property for this.. Furthermore, correct the levels that were incorrect before (confirmed against downstream). Round off frequencies that had uneven fluff on the last two digits. To top if off, leave a note that we should really be scaling the VDD GFX power domain coming from CPR4, which is not yet supported. Scaling MX is still very important though and can be considered valid for the time being - it's better if we scale at one of two voltage rails than if we scaled none.. Fixes: 87cd46d68aea ("arm64: dts: qcom: msm8998: Configure Adreno GPU and related IOMMU") Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 39 +++++++++++++++-------------------- 1 file changed, 17 insertions(+), 22 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 09b222f363c2..11952f9ed9ae 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -1396,51 +1396,46 @@ adreno_gpu: gpu@5000000 { interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; iommus = <&adreno_smmu 0>; operating-points-v2 = <&gpu_opp_table>; + /* TODO: also scale VDDGFX with CPR4 */ power-domains = <&rpmpd MSM8998_VDDMX>; status = "disabled"; gpu_opp_table: opp-table { compatible = "operating-points-v2"; - opp-710000097 { - opp-hz = /bits/ 64 <710000097>; - opp-level = ; - opp-supported-hw = <0xff>; + + opp-710000000 { + opp-hz = /bits/ 64 <710000000>; + required-opps = <&rpmpd_opp_turbo>; }; - opp-670000048 { - opp-hz = /bits/ 64 <670000048>; - opp-level = ; - opp-supported-hw = <0xff>; + opp-670000000 { + opp-hz = /bits/ 64 <670000000>; + required-opps = <&rpmpd_opp_turbo>; }; - opp-596000097 { - opp-hz = /bits/ 64 <596000097>; - opp-level = ; - opp-supported-hw = <0xff>; + opp-596000000 { + opp-hz = /bits/ 64 <596000000>; + required-opps = <&rpmpd_opp_nom>; }; - opp-515000097 { - opp-hz = /bits/ 64 <515000097>; - opp-level = ; - opp-supported-hw = <0xff>; + opp-515000000 { + opp-hz = /bits/ 64 <515000000>; + required-opps = <&rpmpd_opp_nom>; }; opp-414000000 { opp-hz = /bits/ 64 <414000000>; - opp-level = ; - opp-supported-hw = <0xff>; + required-opps = <&rpmpd_opp_svs>; }; opp-342000000 { opp-hz = /bits/ 64 <342000000>; - opp-level = ; - opp-supported-hw = <0xff>; + required-opps = <&rpmpd_opp_svs>; }; opp-257000000 { opp-hz = /bits/ 64 <257000000>; - opp-level = ; - opp-supported-hw = <0xff>; + required-opps = <&rpmpd_opp_svs>; }; }; }; From patchwork Wed Mar 29 19:17:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 76770 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp636356vqo; Wed, 29 Mar 2023 12:23:54 -0700 (PDT) X-Google-Smtp-Source: AKy350aRQpA5PwNETaFd+RCB5fnA1fo+PQE4fTTizWkfu2ItaArE3cfjvPcom9sV9ne1WaPnVpMx X-Received: by 2002:a17:902:e74e:b0:19e:6b50:e220 with SMTP id p14-20020a170902e74e00b0019e6b50e220mr22761199plf.53.1680117834677; Wed, 29 Mar 2023 12:23:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680117834; cv=none; d=google.com; s=arc-20160816; b=kk1o/UxEwf3XHY6+XXjZ6+g21KIs5uAz3G0tqXI3MkQOrcyXI/RARV/e0kuNtAcLvi vBJnroad6l/awEHWy3npxqR89zc6PL+7RFAKIZG6lfzsiH3WAspzIuvFRcnFSPxVWRhr hdofcqU/U3bTcnk8UoVP7ZLUbbrUFayU5UNYsIi+ObCY1/NJ9sfDVfaBrqJvHhlAsE/4 0MnokRRS9AN6ievTp/vvgMlW482lZ2/thVOPTNO8R4yfpfF80oiRELf2iQr3z5XfjxQw ksq3fYu5ZQmHlkkWiNUSk+K14hcg0eEP4VwjnpuHCZjSg9nB79WDrkneXx09lmig81yU E82A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=FkAai3XhfiUPRhW3jICgZ5p+Oa8ltVSaTnDmaflq7J0=; b=Cn/20x48qhv9aMHPXgWqmc0VAakGgJN4cXefhu0a7Ud/SfNjtTMuuOyL7vyHxIZZ23 b434i2KflkX5bd4DExPB3mYWGUUAETtlK+cxT2ykuadW8VGaz1dd51ugNq5+oncE6KlG 2oTOpDas/WKIOaswdYJTBpUkFU5c4+3qiIzxAYT4rK5BcKbkBj/ctQm6UMNT1WflbQDN 04gFnop3PzVys4TMuOw4dUknpsVLYrxmiKWONm3km1xtD2ug5L+c+AKTXyb3i2Bl4u3U 1O6i5QMDu4ityRBRajZoTeYYlAu5CI+4gFyGxZJAKKqw60RAefIOSEpCxaIjEj+N1BVM fNVw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=h2ZHVxfV; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[83.9.3.225]) by smtp.gmail.com with ESMTPSA id f4-20020a2e3804000000b0029ad1fc89b3sm5189658lja.60.2023.03.29.12.17.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Mar 2023 12:17:38 -0700 (PDT) From: Konrad Dybcio Date: Wed, 29 Mar 2023 21:17:29 +0200 Subject: [PATCH 2/4] arm64: dts: qcom: msm8996: Pass VDDMX to gpu in power-domains MIME-Version: 1.0 Message-Id: <20230329-topic-adreno_opp-v1-2-24d34ac6f007@linaro.org> References: <20230329-topic-adreno_opp-v1-0-24d34ac6f007@linaro.org> In-Reply-To: <20230329-topic-adreno_opp-v1-0-24d34ac6f007@linaro.org> To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , AngeloGioacchino Del Regno , Jordan Crouse , Srinivas Kandagatla , Vivek Gautam , Vinod Koul , Rob Clark , Stephen Boyd Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Andy Gross , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680117452; l=1874; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=B4c/XI1szXxzRjFxiQx3VjZCHnPxGxqsOILu9llcN2Y=; b=Zs9LksiWRztnXYtI4O3NfXHgKmEahbtvCpXjg3ZG98cB1u4HUyqw+s4VmKtPstHhnnUov1foxpUk RR4OCGrFDyd3G9norJZwh8qiAX82Ny9DXokCHV9hL/kqR5rGpXms X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761731238261718274?= X-GMAIL-MSGID: =?utf-8?q?1761731238261718274?= Since power-domains is used for perf_level pm_genpd scaling, it's only fitting that we pass a power domain that's actually supposed to be scaled (and not only turned on/off) to the GPU. While we don't quite support CPR3 yet, the next best thing we can do is pass VDDMX, so that we're at least guaranteed a reasonable vote on the memory side of things. Do so and leave a note mentioning CPR3 PD should be used here instead when support is added. Fixes: 69cc3114ab0f ("arm64: dts: Add Adreno GPU definitions") Fixes: 3f65d51e9e22 ("arm64: dts: qcom: msm8996: Make GPU node control GPU_GX GDSC") Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 4661a556772e..4dd37f72e018 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -1228,7 +1228,8 @@ gpu: gpu@b00000 { interconnects = <&bimc MASTER_GRAPHICS_3D &bimc SLAVE_EBI_CH0>; interconnect-names = "gfx-mem"; - power-domains = <&mmcc GPU_GX_GDSC>; + /* TODO: also scale VDDGFX with CPR3 */ + power-domains = <&rpmpd MSM8996_VDDMX>; iommus = <&adreno_smmu 0>; nvmem-cells = <&speedbin_efuse>; @@ -2254,7 +2255,13 @@ adreno_smmu: iommu@b40000 { <&mmcc GPU_AHB_CLK>; clock-names = "bus", "iface"; - power-domains = <&mmcc GPU_GDSC>; + /* + * We need both GPU_GDSC and GPU_GX_GDSC to be on, but the + * power-domains entry under gpu is occupied by the scaled + * voltage domain. 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[83.9.3.225]) by smtp.gmail.com with ESMTPSA id f4-20020a2e3804000000b0029ad1fc89b3sm5189658lja.60.2023.03.29.12.17.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Mar 2023 12:17:40 -0700 (PDT) From: Konrad Dybcio Date: Wed, 29 Mar 2023 21:17:30 +0200 Subject: [PATCH 3/4] arm64: dts: qcom: msm8996: Improve GPU OPP table MIME-Version: 1.0 Message-Id: <20230329-topic-adreno_opp-v1-3-24d34ac6f007@linaro.org> References: <20230329-topic-adreno_opp-v1-0-24d34ac6f007@linaro.org> In-Reply-To: <20230329-topic-adreno_opp-v1-0-24d34ac6f007@linaro.org> To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , AngeloGioacchino Del Regno , Jordan Crouse , Srinivas Kandagatla , Vivek Gautam , Vinod Koul , Rob Clark , Stephen Boyd Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Andy Gross , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680117452; l=2100; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=HHs9XUkau//fB7qwICGVh9A9wHhqzyRvVAVcwO4KDfs=; b=78jckBmXgNXovF2Ypqr1OD6fjvfwgaTJPmXe+Ex0iTBQcKoz9mv8K8UM4YxbtIL5EcHHQOAtW9iT FXeHmfBjATuEPj7/i+Ciw/ONUdUNPpV84+0+3EDe0sM4abfpIaOw X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761731297980132225?= X-GMAIL-MSGID: =?utf-8?q?1761731297980132225?= Remove the self-explanatory comment about opp-supported-hw contents, add required-opps to ensure reasonable power domain levels are voted for (currently we've been piggybacking off of miracles and MDP votes) and add newlines between each subnode. Fixes: 69cc3114ab0f ("arm64: dts: Add Adreno GPU definitions") Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 4dd37f72e018..62ad30e94f40 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -1244,37 +1244,45 @@ gpu: gpu@b00000 { gpu_opp_table: opp-table { compatible = "operating-points-v2"; - /* - * 624Mhz is only available on speed bins 0 and 3. - * 560Mhz is only available on speed bins 0, 2 and 3. - * All the rest are available on all bins of the hardware. - */ opp-624000000 { opp-hz = /bits/ 64 <624000000>; + required-opps = <&rpmpd_opp_turbo>; opp-supported-hw = <0x09>; }; + opp-560000000 { opp-hz = /bits/ 64 <560000000>; + required-opps = <&rpmpd_opp_turbo>; opp-supported-hw = <0x0d>; }; + opp-510000000 { opp-hz = /bits/ 64 <510000000>; + required-opps = <&rpmpd_opp_nom>; opp-supported-hw = <0xff>; }; + opp-401800000 { opp-hz = /bits/ 64 <401800000>; + required-opps = <&rpmpd_opp_nom>; opp-supported-hw = <0xff>; }; + opp-315000000 { opp-hz = /bits/ 64 <315000000>; + required-opps = <&rpmpd_opp_svs>; opp-supported-hw = <0xff>; }; + opp-214000000 { opp-hz = /bits/ 64 <214000000>; + required-opps = <&rpmpd_opp_svs>; opp-supported-hw = <0xff>; }; + opp-133000000 { opp-hz = /bits/ 64 <133000000>; + required-opps = <&rpmpd_opp_svs>; opp-supported-hw = <0xff>; }; }; From patchwork Wed Mar 29 19:17:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 76774 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp644462vqo; Wed, 29 Mar 2023 12:41:45 -0700 (PDT) X-Google-Smtp-Source: AKy350Zca4sopYLqILtrSEfQBceZ2BGimHVlaarHa06VFvc1xROSxsgXsk+xOPVjg/lrgLD4bGkz X-Received: by 2002:a17:907:3e21:b0:930:f953:9614 with SMTP id hp33-20020a1709073e2100b00930f9539614mr27906063ejc.1.1680118905662; Wed, 29 Mar 2023 12:41:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680118905; cv=none; d=google.com; s=arc-20160816; b=OWFcZLwoW7D8KHwBccpaZgCi5H609QBgsmkeo4ApBEz69tmo91ixGImV91KqsjE/f+ sNrJag1d8RfLJn+1IXHOr8NVRAvBXM76U0x6xjETJkqqCX7/MgaTLLXkXzp//R7oZJPu BEsThQdWI57CNmOXHQaZTJs4fTFRh6GxVlimgeAg7CAy2yUab9zXOeqJTHgbYm3cjjr+ iBhdzJ5X8CJH5Tx71ovNUwhgmNuNPTBf0325oOFTGWRDQnwTK+wOuMVljkvop3d+blqs UniAZnP4r3ML1cucYW6/epJPGiA2Aj7Wj9ABPgBM1GSD7kl0bO7K4Tk5Sjkb6quxAC8k qQjw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=PkKk7Qpt0miI3NiUcSnncqHdyr3DuNCBLMRDZMN+mTU=; b=PSyvLzVZexdDdGYXbWnf1zeb2IvcxHq9RSXH3cRFf67+fB1eLXARxtXiaUqBcu3WqA v2nNgqh8pVCdodWO8INYUkbzPxoCVtbjfOHGn3oUX+JOFkcWplHQIFrp6ANmDzyPodY6 VpmKnzlK7GfQVhvSaZyUHSrfGVtjwasGUtzRP2XIgtgbjgAWdMRMvFwCQS8ZXTlbyert fRbd4i6FR5NXcTBgEsT6BQQMKIjFO3rfy/87ccNSWZApE/ECvHOUNUarbX6Td/UTofec Xhfa44l6LOQLCNXQ8/y0TRmZxoqrcAbOGGFEf1w7ubBYq8LS3AetqSzh0+gJQsxZBQ0F SeHw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=enBcjGxx; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[83.9.3.225]) by smtp.gmail.com with ESMTPSA id f4-20020a2e3804000000b0029ad1fc89b3sm5189658lja.60.2023.03.29.12.17.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Mar 2023 12:17:41 -0700 (PDT) From: Konrad Dybcio Date: Wed, 29 Mar 2023 21:17:31 +0200 Subject: [PATCH 4/4] arm64: dts: qcom: msm8916: Improve GPU OPP table MIME-Version: 1.0 Message-Id: <20230329-topic-adreno_opp-v1-4-24d34ac6f007@linaro.org> References: <20230329-topic-adreno_opp-v1-0-24d34ac6f007@linaro.org> In-Reply-To: <20230329-topic-adreno_opp-v1-0-24d34ac6f007@linaro.org> To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , AngeloGioacchino Del Regno , Jordan Crouse , Srinivas Kandagatla , Vivek Gautam , Vinod Koul , Rob Clark , Stephen Boyd Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Andy Gross , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1680117452; l=1898; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=JPOS4C7Jq8MAmse1/02vKyaIWx2AGQSTrD2cYU4Vq9M=; b=lR/hlBWa2ERR2A1gCrnw36uoxaK8g9TG5iXuPzYclbj1Ce9GkiXJWntiYjP8oOqkHpGQkzk4jdjf xNIJmF5aCXtrCkWWqIkgo6zRBmnrYl36cNeRr/WMJC811dC8QWzk X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761732361607908847?= X-GMAIL-MSGID: =?utf-8?q?1761732361607908847?= Add required-opps to ensure reasonable power domain levels are voted for (currently we've been piggybacking off of miracles and MDP votes), add missing frequencies and add newlines between each subnode. Fixes: 61b83be9117c ("arm64: dts: qcom: msm8916: Add gpu support") Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 22 ++++++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 639b158b4fbe..13bd0c647c1d 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1287,18 +1287,31 @@ gpu@1c00000 { <&gcc GCC_BIMC_GFX_CLK>, <&gcc GCC_BIMC_GPU_CLK>, <&gcc GFX3D_CLK_SRC>; - power-domains = <&gcc OXILI_GDSC>; + power-domains = <&rpmpd MSM8916_VDDCX>; operating-points-v2 = <&gpu_opp_table>; iommus = <&gpu_iommu 1>, <&gpu_iommu 2>; gpu_opp_table: opp-table { compatible = "operating-points-v2"; + opp-27000000 { + opp-hz = /bits/ 64 <27000000>; + required-opps = <&rpmpd_opp_svs_krait>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmpd_opp_svs_soc>; + }; + + opp-310000000 { + opp-hz = /bits/ 64 <310000000>; + required-opps = <&rpmpd_opp_nom>; + }; + opp-400000000 { opp-hz = /bits/ 64 <400000000>; - }; - opp-19200000 { - opp-hz = /bits/ 64 <19200000>; + required-opps = <&rpmpd_opp_super_turbo>; }; }; }; @@ -1368,6 +1381,7 @@ gpu_iommu: iommu@1f08000 { clocks = <&gcc GCC_SMMU_CFG_CLK>, <&gcc GCC_GFX_TCU_CLK>; clock-names = "iface", "bus"; + power-domains = <&gcc OXILI_GDSC>; qcom,iommu-secure-id = <18>; /* GFX3D_USER */