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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id e19-20020a50ec93000000b004ad8bff8f1dsi31897578edr.204.2023.03.29.00.55.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Mar 2023 00:55:10 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=TcVSkYU6; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id ABF933858C2B for ; Wed, 29 Mar 2023 07:55:08 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org ABF933858C2B DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1680076508; bh=uVlbzYk1SYQixCfpcLmaZsAROgPjb4PfH0QGXw/DgvA=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=TcVSkYU6QqhMsLJFqeGFhxwm4pWJxHd4uy26I/Dtdox1amzMxYSgnYmIFY6n9JlLi DfYE4zAxSHISMX6uyrmCGjsir2EFRoEMUmA02ZQYLXEP6faiKaIAsoxHjOm9XXjUor 9Dih/wuh0W/dZkYPyMlHqMNIEDzaJAjWhIDMiHTg= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by sourceware.org (Postfix) with ESMTPS id 3523F3858D39 for ; Wed, 29 Mar 2023 07:54:24 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 3523F3858D39 X-IronPort-AV: E=McAfee;i="6600,9927,10663"; a="320461204" X-IronPort-AV: E=Sophos;i="5.98,300,1673942400"; d="scan'208";a="320461204" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Mar 2023 00:52:34 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10663"; a="748701415" X-IronPort-AV: E=Sophos;i="5.98,300,1673942400"; d="scan'208";a="748701415" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by fmsmga008.fm.intel.com with ESMTP; 29 Mar 2023 00:52:31 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.46.88]) by shvmail02.sh.intel.com (Postfix) with ESMTP id 187EC1010211; Wed, 29 Mar 2023 15:52:31 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@sifive.com, pan2.li@intel.com, rguenther@suse.de, yanzhang.wang@intel.com Subject: [PATCH] [RISC-V]: Bugfix for RVV vbool*_t vn_reference_equal. Date: Wed, 29 Mar 2023 15:52:22 +0800 Message-Id: <20230329075222.2888608-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-10.6 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SCC_5_SHORT_WORD_LINES, SPF_HELO_PASS, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Pan Li via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: pan2.li@intel.com Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761687906584824596?= X-GMAIL-MSGID: =?utf-8?q?1761687906584824596?= From: Pan Li In most architecture the precision_size of vbool*_t types are caculated like as the multiple of the type size. For example: precision_size = type_size * 8 (aka, bit count per bytes). Unfortunately, some architecture like RISC-V will adjust the precision_size for the vbool*_t in order to align the ISA. For example as below. type_size = [1, 1, 1, 1, 2, 4, 8] precision_size = [1, 2, 4, 8, 16, 32, 64] Then the precision_size of RISC-V vbool*_t will not be the multiple of the type_size. This PATCH try to enrich this case when comparing the vn_reference. Given we have the below code: void test_vbool8_then_vbool16(int8_t * restrict in, int8_t * restrict out) { vbool8_t v1 = *(vbool8_t*)in; vbool16_t v2 = *(vbool16_t*)in; *(vbool8_t*)(out + 100) = v1; *(vbool16_t*)(out + 200) = v2; } Before this PATCH: csrr t0,vlenb slli t1,t0,1 csrr a3,vlenb sub sp,sp,t1 slli a4,a3,1 add a4,a4,sp addi a2,a1,100 vsetvli a5,zero,e8,m1,ta,ma sub a3,a4,a3 vlm.v v24,0(a0) vsm.v v24,0(a2) vsm.v v24,0(a3) addi a1,a1,200 csrr t0,vlenb vsetvli a4,zero,e8,mf2,ta,ma slli t1,t0,1 vlm.v v24,0(a3) vsm.v v24,0(a1) add sp,sp,t1 jr ra After this PATCH: addi a3,a1,100 vsetvli a4,zero,e8,m1,ta,ma addi a1,a1,200 vlm.v v24,0(a0) vsm.v v24,0(a3) vsetvli a5,zero,e8,mf2,ta,ma vlm.v v24,0(a0) vsm.v v24,0(a1) ret PR 109272 gcc/ChangeLog: * tree-ssa-sccvn.cc (vn_reference_eq): gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pr108185-4.c: * gcc.target/riscv/rvv/base/pr108185-5.c: * gcc.target/riscv/rvv/base/pr108185-6.c: --- .../gcc.target/riscv/rvv/base/pr108185-4.c | 2 +- .../gcc.target/riscv/rvv/base/pr108185-5.c | 2 +- .../gcc.target/riscv/rvv/base/pr108185-6.c | 2 +- gcc/tree-ssa-sccvn.cc | 13 +++++++++++++ 4 files changed, 16 insertions(+), 3 deletions(-) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c index ea3c360d756..e70284fada8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c @@ -65,4 +65,4 @@ test_vbool8_then_vbool64(int8_t * restrict in, int8_t * restrict out) { /* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */ /* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */ /* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */ -/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 15 } } */ +/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c index 9fc659d2402..575a7842cdf 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c @@ -65,4 +65,4 @@ test_vbool16_then_vbool64(int8_t * restrict in, int8_t * restrict out) { /* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */ /* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */ /* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */ -/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 14 } } */ +/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c index 98275e5267d..95a11d37016 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c @@ -65,4 +65,4 @@ test_vbool32_then_vbool64(int8_t * restrict in, int8_t * restrict out) { /* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma} 1 } } */ /* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */ /* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */ -/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 13 } } */ +/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */ diff --git a/gcc/tree-ssa-sccvn.cc b/gcc/tree-ssa-sccvn.cc index 6b8d38b270c..c6dfa8fd9a3 100644 --- a/gcc/tree-ssa-sccvn.cc +++ b/gcc/tree-ssa-sccvn.cc @@ -799,6 +799,19 @@ vn_reference_eq (const_vn_reference_t const vr1, const_vn_reference_t const vr2) && (TYPE_PRECISION (vr2->type) != TREE_INT_CST_LOW (TYPE_SIZE (vr2->type)))) return false; + else if (VECTOR_BOOLEAN_TYPE_P (vr1->type) + && VECTOR_BOOLEAN_TYPE_P (vr2->type) + && expressions_equal_p (TYPE_SIZE (vr1->type), + TYPE_SIZE (vr2->type)) + && TYPE_PRECISION (vr1->type) != TYPE_PRECISION (vr2->type)) + /* For the vbool*_t types in most architectures, the precision size is + caculated as the multiple of the type size. For example, + precision_size = type_size * 8 (aka, bit count per bytes). + Unfortunately, some architecture like RISC-V will adjust the + precision for the vbool*_t in order to align the ISA and the + precision will not be the multiple of the type size. Thus, enrich + the type comparation for this case here. */ + return false; i = 0; j = 0;