From patchwork Wed Mar 29 00:43:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ChiYuan Huang X-Patchwork-Id: 76328 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp82905vqo; Tue, 28 Mar 2023 18:13:25 -0700 (PDT) X-Google-Smtp-Source: AKy350Zc+PdQM1ZMjHbVb2DY8V6P++wdtjD/0fUL93Srsg7ZRCJfgXKFlaE5CYv7ebKiN/hBwVvg X-Received: by 2002:a17:906:3c46:b0:92f:d1ec:a7d7 with SMTP id i6-20020a1709063c4600b0092fd1eca7d7mr430973ejg.15.1680052405033; Tue, 28 Mar 2023 18:13:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680052405; cv=none; d=google.com; s=arc-20160816; b=t9QIMJPE8dAE4jfkxjw/s5hdHVaeSWvrNHijcb4m169XQTlbYz+WhZQ34XZj1nPBSG hzRS1NMtqR5Pg1b0luv9r5538IDv9Y2T5AWVyITkxgu4EPdAkWUcJfQZpmIGhAKj6tIo C1cdjA5Knd2F8EBcbKPpgP+RBRwEpaewAd9mhiGG601J622BQum6DjiZFQmM8zD2Q9AD AepqfKhrreIqnLx2/R45c1s5jwSABuR+C91Etyc1jc731+YyfM9DbB1m5bIG6j9ccVN8 fL785YDBIxgY5hhpemPAU759AsWTbkn7aInLsD6tRxBHgNFgbp9kqrAWTJmdk5xNDuAh WE3Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:message-id:date:subject:cc:to:from; bh=mFVplKN3TlNshGWojE482FdqvDHsloDvZyMwC+qLk6A=; b=BVWAZW7wqG6t+Xhc8avn9pdIFelUa0vuFurtgDAtt9tdcvLAbztynRihFU3SJY68TT niFlVGYMjP6nqYy8QhA0ZwUZ7WoHOjL2qJvitIfgtMBa57N/YreMbO3dtmdaie3QNVSL 4c8MU0IC2zs657/iWFI8zt8u2a5JaOZjXHe28elAOW30XWUPt5J0casPoQPZqptEdBgr AGUskUSS4howLXv1w+opvFNU2kruYZmjW0TyflHpGxmHVGUcRwARzBam/DqlbaagK589 N9pVw1aOk7WrEb3QboJ4Lbe37bRYAjD7hAksVkeUI9GtC6QiPeAGGW9iecZ4fOisst7l ZYtw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id bk17-20020a170906b0d100b008e7916f1952si31439215ejb.822.2023.03.28.18.12.50; Tue, 28 Mar 2023 18:13:24 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229755AbjC2An7 (ORCPT + 99 others); Tue, 28 Mar 2023 20:43:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40468 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229456AbjC2Anz (ORCPT ); Tue, 28 Mar 2023 20:43:55 -0400 Received: from mg.richtek.com (mg.richtek.com [220.130.44.152]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 83B0B2109; Tue, 28 Mar 2023 17:43:49 -0700 (PDT) X-MailGates: (flag:4,DYNAMIC,BADHELO,RELAY,NOHOST:PASS)(compute_score:DE LIVER,40,3) Received: from 192.168.10.47 by mg.richtek.com with MailGates ESMTP Server V5.0(26679:0:AUTH_RELAY) (envelope-from ); Wed, 29 Mar 2023 08:43:28 +0800 (CST) Received: from ex4.rt.l (192.168.10.47) by ex4.rt.l (192.168.10.47) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.25; Wed, 29 Mar 2023 08:43:27 +0800 Received: from linuxcarl2.richtek.com (192.168.10.154) by ex4.rt.l (192.168.10.45) with Microsoft SMTP Server id 15.2.1118.25 via Frontend Transport; Wed, 29 Mar 2023 08:43:27 +0800 From: To: , , CC: , , , , Subject: [PATCH v2 1/2] regulator: dt-bindings: Add Richtek RT4803 Date: Wed, 29 Mar 2023 08:43:25 +0800 Message-ID: <1680050606-461-1-git-send-email-cy_huang@richtek.com> X-Mailer: git-send-email 1.8.3.1 MIME-Version: 1.0 X-Spam-Status: No, score=0.0 required=5.0 tests=SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761662630734395563?= X-GMAIL-MSGID: =?utf-8?q?1761662630734395563?= From: ChiYuan Huang Add the binding document for Richtek RT4803. Signed-off-by: ChiYuan Huang Reviewed-by: Krzysztof Kozlowski --- Since v2 - Subject prefix change to 'regulator: dt-bindings: .....' - Add Reviewed-by tag. --- .../bindings/regulator/richtek,rt4803.yaml | 68 ++++++++++++++++++++++ 1 file changed, 68 insertions(+) create mode 100644 Documentation/devicetree/bindings/regulator/richtek,rt4803.yaml diff --git a/Documentation/devicetree/bindings/regulator/richtek,rt4803.yaml b/Documentation/devicetree/bindings/regulator/richtek,rt4803.yaml new file mode 100644 index 00000000..6ceba02 --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/richtek,rt4803.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/richtek,rt4803.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Richtek RT4803 Boost Regulator + +maintainers: + - ChiYuan Huang + +description: | + RT4803 is a boost regulator that's designed to provide the minimum output + voltage, even if the input voltage is lower than the required voltage. It + supports boost and auto bypass mode that depends on the difference between the + input and output voltage. If the input is lower than the output, mode will + transform to boost mode. Otherwise, turn on bypass switch to enter bypass mode. + + Datasheet is available at + https://www.richtek.com/assets/product_file/RT4803/DS4803-03.pdf + https://www.richtek.com/assets/product_file/RT4803A/DS4803A-06.pdf + +allOf: + - $ref: regulator.yaml# + +properties: + compatible: + enum: + - richtek,rt4803 + + reg: + maxItems: 1 + + richtek,vsel-active-high: + type: boolean + description: Specify the VSEL register group is using when system is active + + regulator-allowed-modes: + description: | + Available operating mode + 1: Auto PFM/PWM + 2: Force PWM + items: + enum: [1, 2] + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + regulator@75 { + compatible = "richtek,rt4803"; + reg = <0x75>; + richtek,vsel-active-high; + regulator-name = "rt4803-regulator"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <4400000>; + regulator-allowed-modes = <1 2>; + regulator-always-on; + }; + }; From patchwork Wed Mar 29 00:43:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ChiYuan Huang X-Patchwork-Id: 76327 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp76904vqo; Tue, 28 Mar 2023 18:01:15 -0700 (PDT) X-Google-Smtp-Source: AKy350bj6/DX3ZI0sAt+7Zh2ELYZ/gCe8uVrUdgwsH5ho39Ru92iTPf/J5RC9G7WyrwvQV5g22FJ X-Received: by 2002:a17:902:ce8f:b0:1a1:efb8:599d with SMTP id f15-20020a170902ce8f00b001a1efb8599dmr580807plg.6.1680051675658; Tue, 28 Mar 2023 18:01:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680051675; cv=none; d=google.com; s=arc-20160816; b=GXninINBr3zCa84dOM8CVpEfhdlClJqiGVpF/KlVE64y7kkAgwwx5rsd+mcGqjfKBY eMgbxSw1cjNuQuHOyLRXb91tKweImieSlUrL3PIjscUe05LmrT/IFLtjLtIO4B58lCnR HwrvoRdb5cVVvZlXegaIJjdCDKT1JdhKccbi7c3jNhYLM06zdEWim8GI01ll+i622RzY +NloqLS4CQlkrDZwgZpesiFnXsrvt0k49EApa0sJGava8gquARCosA5P6vKKrrqV20TG eBTKlRqalz6Gy5RcC2snxqU/rEUxHQL7sEWZc5/Cg6zy0G2mjeMtfuH5vpOIzwAQBfqy gLxQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from; bh=RnswfrGcx6ugu5vfTzGkd0VlMgbGMAlqMx8SrWbr20M=; b=OdRMlIFILc98e9E4xmnIpeRFPGpdTXMt86tzS4FtLG5QFRXL/k0Ga8k2YQFOSt4p8M xQZbKqo1MxTlGW77WpKcRzfSXh5Vt8bDCUGTXTV75GwUzxK5SkkBAl0k1z+ur2PMZdkh lp1WqpGkkrKc6W8/6P3hG1+ZnKUt53RZWjqGFcsDn2H0Pt3P3LnUIB2fHbq8uJM1XyPa a2rDj8Rd3V0SNJjeIjlQPFP7ox0MV3sKY3y8+AF1atou/DTJsr0QFSpnvoqveyV1WSrx 5YrmWqOtkjs3TvZwOfGrY6U0/8LtLz4cXNRpU5dmTdN8MF75lzYxhJnwbbOIUOMpzUUm 0VsA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id ay9-20020a1709028b8900b0019ca7ed8931si29371800plb.279.2023.03.28.18.00.57; Tue, 28 Mar 2023 18:01:15 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229666AbjC2An4 (ORCPT + 99 others); Tue, 28 Mar 2023 20:43:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40470 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229452AbjC2Anz (ORCPT ); Tue, 28 Mar 2023 20:43:55 -0400 Received: from mg.richtek.com (mg.richtek.com [220.130.44.152]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 83C3E210D; Tue, 28 Mar 2023 17:43:49 -0700 (PDT) X-MailGates: (flag:4,DYNAMIC,BADHELO,RELAY,NOHOST:PASS)(compute_score:DE LIVER,40,3) Received: from 192.168.10.47 by mg.richtek.com with MailGates ESMTP Server V5.0(26679:0:AUTH_RELAY) (envelope-from ); Wed, 29 Mar 2023 08:43:28 +0800 (CST) Received: from ex4.rt.l (192.168.10.47) by ex4.rt.l (192.168.10.47) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.25; Wed, 29 Mar 2023 08:43:28 +0800 Received: from linuxcarl2.richtek.com (192.168.10.154) by ex4.rt.l (192.168.10.45) with Microsoft SMTP Server id 15.2.1118.25 via Frontend Transport; Wed, 29 Mar 2023 08:43:28 +0800 From: To: , , CC: , , , , Subject: [PATCH v2 2/2] regulator: Add Richtek RT4803 boost regulator Date: Wed, 29 Mar 2023 08:43:26 +0800 Message-ID: <1680050606-461-2-git-send-email-cy_huang@richtek.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1680050606-461-1-git-send-email-cy_huang@richtek.com> References: <1680050606-461-1-git-send-email-cy_huang@richtek.com> MIME-Version: 1.0 X-Spam-Status: No, score=0.0 required=5.0 tests=SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761661865742601882?= X-GMAIL-MSGID: =?utf-8?q?1761661865742601882?= From: ChiYuan Huang RT4803 is a boost converter that integrates an internal bypass FET. It will automatically transform the operation mode between bypass and boost based on the voltage difference of the input and output voltage. Signed-off-by: ChiYuan Huang --- drivers/regulator/Kconfig | 10 +++ drivers/regulator/Makefile | 1 + drivers/regulator/rt4803.c | 216 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 227 insertions(+) create mode 100644 drivers/regulator/rt4803.c diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig index aae28d0..fd9a29c 100644 --- a/drivers/regulator/Kconfig +++ b/drivers/regulator/Kconfig @@ -1082,6 +1082,16 @@ config REGULATOR_RT4801 This adds support for voltage regulators in Richtek RT4801 Display Bias IC. The device supports two regulators (DSVP/DSVN). +config REGULATOR_RT4803 + tristate "Richtek RT4803 boost regualtor" + depends on I2C + select REGMAP_I2C + help + This adds support for RT4803 boost converter that integrates the + bypass switch. If the input voltage is low than the required voltage, + RT4803 will enter boost mode. Otherwise, enable internal bypass + switch to enter bypass mode. + config REGULATOR_RT4831 tristate "Richtek RT4831 DSV Regulators" depends on MFD_RT4831 diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile index ee383d8..163b599 100644 --- a/drivers/regulator/Makefile +++ b/drivers/regulator/Makefile @@ -130,6 +130,7 @@ obj-$(CONFIG_REGULATOR_RK808) += rk808-regulator.o obj-$(CONFIG_REGULATOR_RN5T618) += rn5t618-regulator.o obj-$(CONFIG_REGULATOR_ROHM) += rohm-regulator.o obj-$(CONFIG_REGULATOR_RT4801) += rt4801-regulator.o +obj-$(CONFIG_REGULATOR_RT4803) += rt4803.o obj-$(CONFIG_REGULATOR_RT4831) += rt4831-regulator.o obj-$(CONFIG_REGULATOR_RT5033) += rt5033-regulator.o obj-$(CONFIG_REGULATOR_RT5120) += rt5120-regulator.o diff --git a/drivers/regulator/rt4803.c b/drivers/regulator/rt4803.c new file mode 100644 index 00000000..c96fb02 --- /dev/null +++ b/drivers/regulator/rt4803.c @@ -0,0 +1,216 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023 Richtek Technology Corp. + * + * Author: ChiYuan Huang + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define RT4803_AUTO_MODE 1 +#define RT4803_FPWM_MODE 2 + +#define RT4803_REG_CONFIG 0x01 +#define RT4803_REG_VSELL 0x02 +#define RT4803_REG_VSELH 0x03 +#define RT4803_REG_ILIM 0x04 +#define RT4803_REG_STAT 0x05 + +#define RT4803_MODE_MASK GENMASK(1, 0) +#define RT4803_VSEL_MASK GENMASK(4, 0) +#define RT4803_ILIM_MASK GENMASK(3, 0) +#define RT4803_TSD_MASK BIT(7) +#define RT4803_HOTDIE_MASK BIT(6) +#define RT4803_FAULT_MASK BIT(1) +#define RT4803_PGOOD_MASK BIT(0) + +#define RT4803_VOUT_MINUV 2850000 +#define RT4803_VOUT_STEPUV 50000 +#define RT4803_VOUT_NUM 32 + +static int rt4803_set_mode(struct regulator_dev *rdev, unsigned int mode) +{ + struct regmap *regmap = rdev_get_regmap(rdev); + unsigned int modeval; + + switch (mode) { + case REGULATOR_MODE_NORMAL: + modeval = RT4803_AUTO_MODE; + break; + case REGULATOR_MODE_FAST: + modeval = RT4803_FPWM_MODE; + break; + default: + return -EINVAL; + } + + modeval <<= ffs(RT4803_MODE_MASK) - 1; + + return regmap_update_bits(regmap, RT4803_REG_CONFIG, RT4803_MODE_MASK, modeval); +} + +static unsigned int rt4803_get_mode(struct regulator_dev *rdev) +{ + struct regmap *regmap = rdev_get_regmap(rdev); + unsigned int modeval; + int ret; + + ret = regmap_read(regmap, RT4803_REG_CONFIG, &modeval); + if (ret) + return REGULATOR_MODE_INVALID; + + modeval >>= ffs(RT4803_MODE_MASK) - 1; + + switch (modeval) { + case RT4803_AUTO_MODE: + return REGULATOR_MODE_NORMAL; + case RT4803_FPWM_MODE: + return REGULATOR_MODE_FAST; + default: + return REGULATOR_MODE_INVALID; + } +} + +static int rt4803_get_error_flags(struct regulator_dev *rdev, unsigned int *flags) +{ + struct regmap *regmap = rdev_get_regmap(rdev); + unsigned int state, events = 0; + int ret; + + ret = regmap_read(regmap, RT4803_REG_STAT, &state); + if (ret) + return ret; + + if (state & RT4803_PGOOD_MASK) + goto out_error_flag; + + if (state & RT4803_FAULT_MASK) + events |= REGULATOR_ERROR_FAIL; + + if (state & RT4803_HOTDIE_MASK) + events |= REGULATOR_ERROR_OVER_TEMP_WARN; + + if (state & RT4803_TSD_MASK) + events |= REGULATOR_ERROR_OVER_TEMP; + +out_error_flag: + *flags = events; + return 0; +} + +static int rt4803_set_suspend_voltage(struct regulator_dev *rdev, int uV) +{ + struct regmap *regmap = rdev_get_regmap(rdev); + unsigned int reg, vsel; + + if (rdev->desc->vsel_reg == RT4803_REG_VSELL) + reg = RT4803_REG_VSELH; + else + reg = RT4803_REG_VSELL; + + vsel = (uV - rdev->desc->min_uV) / rdev->desc->uV_step; + vsel <<= ffs(RT4803_VSEL_MASK) - 1; + + return regmap_update_bits(regmap, reg, RT4803_VSEL_MASK, vsel); +} + +static const struct regulator_ops rt4803_regulator_ops = { + .list_voltage = regulator_list_voltage_linear, + .set_voltage_sel = regulator_set_voltage_sel_regmap, + .get_voltage_sel = regulator_get_voltage_sel_regmap, + .set_mode = rt4803_set_mode, + .get_mode = rt4803_get_mode, + .get_error_flags = rt4803_get_error_flags, + .set_suspend_voltage = rt4803_set_suspend_voltage, +}; + +static unsigned int rt4803_of_map_mode(unsigned int mode) +{ + switch (mode) { + case RT4803_AUTO_MODE: + return REGULATOR_MODE_NORMAL; + case RT4803_FPWM_MODE: + return REGULATOR_MODE_FAST; + default: + return REGULATOR_MODE_INVALID; + } +} + +static const struct regmap_config rt4803_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + .max_register = RT4803_REG_STAT, +}; + +static int rt4803_probe(struct i2c_client *i2c) +{ + struct device *dev = &i2c->dev; + struct regmap *regmap; + struct regulator_desc *desc; + struct regulator_config cfg = {}; + struct regulator_dev *rdev; + bool vsel_act_high; + int ret; + + desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); + if (!desc) + return -ENOMEM; + + regmap = devm_regmap_init_i2c(i2c, &rt4803_regmap_config); + if (IS_ERR(regmap)) + return dev_err_probe(dev, PTR_ERR(regmap), "Failed to init regmap\n"); + + /* Always configure the input current limit to max 5A at initial */ + ret = regmap_update_bits(regmap, RT4803_REG_ILIM, RT4803_ILIM_MASK, 0xff); + if (ret) + return dev_err_probe(dev, ret, "Failed to config ILIM to max\n"); + + vsel_act_high = device_property_read_bool(dev, "richtek,vsel-active-high"); + + desc->name = "rt4803-regulator"; + desc->type = REGULATOR_VOLTAGE; + desc->owner = THIS_MODULE; + desc->ops = &rt4803_regulator_ops; + desc->min_uV = RT4803_VOUT_MINUV; + desc->uV_step = RT4803_VOUT_STEPUV; + desc->n_voltages = RT4803_VOUT_NUM; + desc->vsel_mask = RT4803_VSEL_MASK; + desc->of_map_mode = rt4803_of_map_mode; + if (vsel_act_high) + desc->vsel_reg = RT4803_REG_VSELH; + else + desc->vsel_reg = RT4803_REG_VSELL; + + cfg.dev = dev; + cfg.of_node = dev_of_node(dev); + cfg.init_data = of_get_regulator_init_data(dev, dev_of_node(dev), desc); + + rdev = devm_regulator_register(dev, desc, &cfg); + return PTR_ERR_OR_ZERO(rdev); +} + +static const struct of_device_id rt4803_device_match_table[] = { + { .compatible = "richtek,rt4803" }, + {} +}; +MODULE_DEVICE_TABLE(of, rt4803_device_match_table); + +static struct i2c_driver rt4803_driver = { + .driver = { + .name = "rt4803", + .of_match_table = rt4803_device_match_table, + }, + .probe = rt4803_probe, +}; +module_i2c_driver(rt4803_driver); + +MODULE_DESCRIPTION("Richtek RT4803 voltage regulator driver"); +MODULE_AUTHOR("ChiYuan Huang "); +MODULE_LICENSE("GPL");