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[2620:137:e000::1:20]) by mx.google.com with ESMTP id ay5-20020a056402202500b00501d7cdf513si16626674edb.126.2023.03.28.12.38.33; Tue, 28 Mar 2023 12:38:58 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@bgdev-pl.20210112.gappssmtp.com header.s=20210112 header.b=pXEpgibP; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229708AbjC1Tgu (ORCPT + 99 others); Tue, 28 Mar 2023 15:36:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50302 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229623AbjC1Tgp (ORCPT ); Tue, 28 Mar 2023 15:36:45 -0400 Received: from mail-wm1-x32e.google.com (mail-wm1-x32e.google.com [IPv6:2a00:1450:4864:20::32e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 29AE61980 for ; Tue, 28 Mar 2023 12:36:43 -0700 (PDT) Received: by mail-wm1-x32e.google.com with SMTP id j18-20020a05600c1c1200b003ee5157346cso10124610wms.1 for ; Tue, 28 Mar 2023 12:36:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bgdev-pl.20210112.gappssmtp.com; s=20210112; t=1680032201; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fz5lcSDpF7J02lC5C/+yg9eF6HsVD3HRWyB+OFxgdJs=; b=pXEpgibP9p3ABJt6Vkv481tXwtfDAEvMM0sFIWQF8Umsnsr5bwRnyP08xtVGXtjuSg +Bs8bMncyFdXfaE5mf0nR09vDVakWSFmrqpuxzykekA0lASc8POVN9tDL9aheKJ1Uso7 TtVzbkDK0q8Lm6ioPcvnbY7oHI3s5RQSFC2brP/3lCTUXtRzHFVuYc1CmDXWRIVgHmtz pBGLE8SjFsuAqHH0oLau96BCqs80JoRPmD+So1yviZdXClqu3jwp/uxLHXTjFp8jHgia WsLTvBqoDifWUAX9KC3yKtZiHbsSmmKNHuMmDhajwEnkSSQw2KXCnAgUfTOhU3DseeXr aTCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680032201; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fz5lcSDpF7J02lC5C/+yg9eF6HsVD3HRWyB+OFxgdJs=; b=SYCKYfOrbIiNT3hsrkGq8b/CKOdjSzrCpv/wDFGm2FLgnNZK8dq2EUIZtJdYEKf377 ZxhshPrFy2GaptuvoCfVUot/VNwGt26Bi+KHHO0QTaZYRQkFpnLkRZs/+u4F5AC1RSo5 at4tUndWIgUH5J/trcoIEfVAx1i/qRcmxeVMo953pWGiQ0liAYDloU4Fs1hA3aIT4WW5 tJKtR70YiOx+yFi/WBTjPw65eBk36IGiZ4v6w5HJ734sTk/ndtpcEm/Rt01gEc3tb48a dGs2ql9DJhXaiNayRfkQNWKnCMt8E0y4QbAzg51rgjbleGvhe4lZvZcm3trDdBZn0/T3 oKxA== X-Gm-Message-State: AO0yUKWJ1QMm5TSpMAiwpPDwBYCPbK0Jwj2KAEjqPZZ8THPd4n+tGmdi V+OaORU/J5TrC2JT0w8u4MdmNQ== X-Received: by 2002:a05:600c:2118:b0:3eb:39e0:3530 with SMTP id u24-20020a05600c211800b003eb39e03530mr12166851wml.41.1680032201623; Tue, 28 Mar 2023 12:36:41 -0700 (PDT) Received: from brgl-uxlite.home ([2a01:cb1d:334:ac00:7b39:552d:b2f1:d7e8]) by smtp.gmail.com with ESMTPSA id g23-20020a7bc4d7000000b003eb5ce1b734sm18060544wmk.7.2023.03.28.12.36.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Mar 2023 12:36:41 -0700 (PDT) From: Bartosz Golaszewski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Dmitry Baryshkov Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, Bartosz Golaszewski , Stephen Boyd , Michael Turquette Subject: [PATCH 1/7] dt-bindings: clock: qcom: describe the GPUCC clock for SA8775P Date: Tue, 28 Mar 2023 21:36:26 +0200 Message-Id: <20230328193632.226095-2-brgl@bgdev.pl> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230328193632.226095-1-brgl@bgdev.pl> References: <20230328193632.226095-1-brgl@bgdev.pl> MIME-Version: 1.0 X-Spam-Status: No, score=0.0 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761641588797817398?= X-GMAIL-MSGID: =?utf-8?q?1761641588797817398?= From: Bartosz Golaszewski Add bindings for the Qualcomm Graphics Clock control module present on sa8775p platforms. Cc: Stephen Boyd Cc: Michael Turquette Signed-off-by: Bartosz Golaszewski Reviewed-by: Krzysztof Kozlowski --- .../bindings/clock/qcom,sa8775p-gpucc.yaml | 61 +++++++++++++++++++ .../dt-bindings/clock/qcom,sa8775p-gpucc.h | 50 +++++++++++++++ 2 files changed, 111 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sa8775p-gpucc.yaml create mode 100644 include/dt-bindings/clock/qcom,sa8775p-gpucc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sa8775p-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sa8775p-gpucc.yaml new file mode 100644 index 000000000000..203802f81738 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sa8775p-gpucc.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sa8775p-gpucc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Clock & Reset Controller on SA8775P + +maintainers: + - Bjorn Andersson + - Bartosz Golaszewski + +description: | + Qualcomm graphics clock control module provides clocks, resets and power + domains on Qualcomm SoCs. + + See also:: include/dt-bindings/clock/qcom,sa8775p-gpucc.h + +properties: + compatible: + enum: + - qcom,sa8775p-gpucc + + clocks: + items: + - description: Board XO source + - description: GPLL0 main branch source + - description: GPLL0 div branch source + - description: SNoC DVM GFX source + +required: + - compatible + - clocks + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + clock-controller@3d90000 { + compatible = "qcom,sa8775p-gpucc"; + reg = <0x0 0x03d90000 0x0 0xa000>; + clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + }; +... diff --git a/include/dt-bindings/clock/qcom,sa8775p-gpucc.h b/include/dt-bindings/clock/qcom,sa8775p-gpucc.h new file mode 100644 index 000000000000..a5fd784b1ea2 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sa8775p-gpucc.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPUCC_SA8775P_H +#define _DT_BINDINGS_CLK_QCOM_GPUCC_SA8775P_H + +/* GPU_CC clocks */ +#define GPU_CC_PLL0 0 +#define GPU_CC_PLL1 1 +#define GPU_CC_AHB_CLK 2 +#define GPU_CC_CB_CLK 3 +#define GPU_CC_CRC_AHB_CLK 4 +#define GPU_CC_CX_FF_CLK 5 +#define GPU_CC_CX_GMU_CLK 6 +#define GPU_CC_CX_SNOC_DVM_CLK 7 +#define GPU_CC_CXO_AON_CLK 8 +#define GPU_CC_CXO_CLK 9 +#define GPU_CC_DEMET_CLK 10 +#define GPU_CC_DEMET_DIV_CLK_SRC 11 +#define GPU_CC_FF_CLK_SRC 12 +#define GPU_CC_GMU_CLK_SRC 13 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 14 +#define GPU_CC_HUB_AHB_DIV_CLK_SRC 15 +#define GPU_CC_HUB_AON_CLK 16 +#define GPU_CC_HUB_CLK_SRC 17 +#define GPU_CC_HUB_CX_INT_CLK 18 +#define GPU_CC_HUB_CX_INT_DIV_CLK_SRC 19 +#define GPU_CC_MEMNOC_GFX_CLK 20 +#define GPU_CC_SLEEP_CLK 21 +#define GPU_CC_XO_CLK_SRC 22 + +/* GPU_CC resets */ +#define GPUCC_GPU_CC_ACD_BCR 0 +#define GPUCC_GPU_CC_CB_BCR 1 +#define GPUCC_GPU_CC_CX_BCR 2 +#define GPUCC_GPU_CC_FAST_HUB_BCR 3 +#define GPUCC_GPU_CC_FF_BCR 4 +#define GPUCC_GPU_CC_GFX3D_AON_BCR 5 +#define GPUCC_GPU_CC_GMU_BCR 6 +#define GPUCC_GPU_CC_GX_BCR 7 +#define GPUCC_GPU_CC_XO_BCR 8 + +/* GPU_CC power domains */ +#define GPU_CC_CX_GDSC 0 +#define GPU_CC_GX_GDSC 1 + +#endif /* _DT_BINDINGS_CLK_QCOM_GPUCC_SA8775P_H */ From patchwork Tue Mar 28 19:36:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartosz Golaszewski X-Patchwork-Id: 76231 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2459540vqo; Tue, 28 Mar 2023 12:38:26 -0700 (PDT) X-Google-Smtp-Source: AK7set/0/EFsIjt2tmfhiYdEsdJzwHRW+U6QIz46sLWM6XJAWGE7UX1EiP/8EdnwjHosOSdhiCQZ X-Received: by 2002:a17:906:3710:b0:923:812c:a5d3 with SMTP id d16-20020a170906371000b00923812ca5d3mr22279939ejc.25.1680032306155; Tue, 28 Mar 2023 12:38:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680032306; cv=none; d=google.com; s=arc-20160816; b=0+axL1WCOlmzLvxk56R90deRTVtXhN/QixivKOA47T6zcTe2KfVEgnSH+yIA+j8CFA erF9jewFKwQI0lrZMn/XTe7g9yfo1QsItLlKUWnah+hD1AsOLAxfXn9E1u6B+QLZMOUQ 9XyXwYeixeIdtx6XRkePSSirYr9In6tO1ZxmMk48gd798gb8gqfBZSlJOi+ZzuxbECJi hf6lbtIgdDzYMdvvC4Ij3SzR3npLiSVvS3vJvoy36SkXGuM7aQb6ZnRO+25Qurrx6ZP6 Yp6cPzaaMPvVJ4wvCyv6VlRFcz1uqETG57vrvIOsAOOTixxqTKtMbMDvo/IUlq0NcabD WNzg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=KDnwPaVexo5B1g88nheOFvterzJspb//g6jFEqzt/ng=; b=Yn3lWDdMEzvIxg+t+B4OKePSmAG5byqJ9YtScu58iHP9mU6bRxDwWAWF4n2uICesJn 0QyB3vOfQzMc9VZ5ZL1x/w0ax5UFInschWJiux+dQa44vQq2RkO328ZGKNSV7AnZF5zl jucfn8kwshHnEhcwXrUfvLEM4mjo4KnWsM9uVdl9ZTNxqOV2pw9lYw1Q0WuIJ9fFMqeb hBJA0e9bZ9hTrhNlAWiTtmFKHXQmnq2NpS/ker8xHhlFg6bwArXSPvagLa+CkeQTgX8A p9++HqxRwSkxB34/Gz6MMK/DTN1VzuJVfEfS55XKvk3V+CGyiDrkCXKn8a1mTly8u05I WwoA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@bgdev-pl.20210112.gappssmtp.com header.s=20210112 header.b=wgyLqUJ6; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Cc: Stephen Boyd Cc: Michael Turquette Signed-off-by: Shazad Hussain [Bartosz: make ready for upstream] Co-authored-by: Bartosz Golaszewski Signed-off-by: Bartosz Golaszewski --- drivers/clk/qcom/Kconfig | 8 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gpucc-sa8775p.c | 633 +++++++++++++++++++++++++++++++ 3 files changed, 642 insertions(+) create mode 100644 drivers/clk/qcom/gpucc-sa8775p.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 449bc8314d21..5e1919738aeb 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -437,6 +437,14 @@ config SA_GCC_8775P Say Y if you want to use peripheral devices such as UART, SPI, I2C, USB, UFS, SDCC, etc. +config SA_GPUCC_8775P + tristate "SA8775P Graphics clock controller" + select SA_GCC_8775P + help + Support for the graphics clock controller on SA8775P devices. + Say Y if you want to support graphics controller devices and + functionality such as 3D graphics. + config SC_GCC_7180 tristate "SC7180 Global Clock Controller" select QCOM_GDSC diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index c1adb427d1ef..525e0172a1ef 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -71,6 +71,7 @@ obj-$(CONFIG_SC_DISPCC_7180) += dispcc-sc7180.o obj-$(CONFIG_SC_DISPCC_7280) += dispcc-sc7280.o obj-$(CONFIG_SC_DISPCC_8280XP) += dispcc-sc8280xp.o obj-$(CONFIG_SA_GCC_8775P) += gcc-sa8775p.o +obj-$(CONFIG_SA_GPUCC_8775P) += gpucc-sa8775p.o obj-$(CONFIG_SC_GCC_7180) += gcc-sc7180.o obj-$(CONFIG_SC_GCC_7280) += gcc-sc7280.o obj-$(CONFIG_SC_GCC_8180X) += gcc-sc8180x.o diff --git a/drivers/clk/qcom/gpucc-sa8775p.c b/drivers/clk/qcom/gpucc-sa8775p.c new file mode 100644 index 000000000000..46d73bd0199b --- /dev/null +++ b/drivers/clk/qcom/gpucc-sa8775p.c @@ -0,0 +1,633 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "common.h" +#include "reset.h" +#include "gdsc.h" + +/* Need to match the order of clocks in DT binding */ +enum { + DT_IFACE, + DT_BI_TCXO, + DT_GCC_GPU_GPLL0_CLK_SRC, + DT_GCC_GPU_GPLL0_DIV_CLK_SRC, +}; + +enum { + P_BI_TCXO, + P_GPLL0_OUT_MAIN, + P_GPLL0_OUT_MAIN_DIV, + P_GPU_CC_PLL0_OUT_MAIN, + P_GPU_CC_PLL1_OUT_MAIN, +}; + +static const struct clk_parent_data parent_data_tcxo = { .index = DT_BI_TCXO }; + +static const struct pll_vco lucid_evo_vco[] = { + { 249600000, 2020000000, 0 }, +}; + +/* 810MHz configuration */ +static struct alpha_pll_config gpu_cc_pll0_config = { + .l = 0x2a, + .alpha = 0x3000, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x32aa299c, + .user_ctl_val = 0x00000001, + .user_ctl_hi_val = 0x00400805, +}; + +static struct clk_alpha_pll gpu_cc_pll0 = { + .offset = 0x0, + .vco_table = lucid_evo_vco, + .num_vco = ARRAY_SIZE(lucid_evo_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr = { + .hw.init = &(const struct clk_init_data){ + .name = "gpu_cc_pll0", + .parent_data = &parent_data_tcxo, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +/* 1000MHz configuration */ +static struct alpha_pll_config gpu_cc_pll1_config = { + .l = 0x34, + .alpha = 0x1555, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x32aa299c, + .user_ctl_val = 0x00000001, + .user_ctl_hi_val = 0x00400805, +}; + +static struct clk_alpha_pll gpu_cc_pll1 = { + .offset = 0x1000, + .vco_table = lucid_evo_vco, + .num_vco = ARRAY_SIZE(lucid_evo_vco), + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], + .clkr = { + .hw.init = &(const struct clk_init_data){ + .name = "gpu_cc_pll1", + .parent_data = &parent_data_tcxo, + .num_parents = 1, + .ops = &clk_alpha_pll_lucid_evo_ops, + }, + }, +}; + +static const struct parent_map gpu_cc_parent_map_0[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_0[] = { + { .index = DT_BI_TCXO }, + { .index = DT_GCC_GPU_GPLL0_CLK_SRC }, + { .index = DT_GCC_GPU_GPLL0_DIV_CLK_SRC }, +}; + +static const struct parent_map gpu_cc_parent_map_1[] = { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL0_OUT_MAIN, 1 }, + { P_GPU_CC_PLL1_OUT_MAIN, 3 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_1[] = { + { .index = DT_BI_TCXO }, + { .hw = &gpu_cc_pll0.clkr.hw }, + { .hw = &gpu_cc_pll1.clkr.hw }, + { .index = DT_GCC_GPU_GPLL0_CLK_SRC }, + { .index = DT_GCC_GPU_GPLL0_DIV_CLK_SRC }, +}; + +static const struct parent_map gpu_cc_parent_map_2[] = { + { P_BI_TCXO, 0 }, + { P_GPU_CC_PLL1_OUT_MAIN, 3 }, + { P_GPLL0_OUT_MAIN, 5 }, + { P_GPLL0_OUT_MAIN_DIV, 6 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_2[] = { + { .index = DT_BI_TCXO }, + { .hw = &gpu_cc_pll1.clkr.hw }, + { .index = DT_GCC_GPU_GPLL0_CLK_SRC }, + { .index = DT_GCC_GPU_GPLL0_DIV_CLK_SRC }, +}; + +static const struct parent_map gpu_cc_parent_map_3[] = { + { P_BI_TCXO, 0 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_3[] = { + { .index = DT_BI_TCXO }, +}; + +static const struct freq_tbl ftbl_gpu_cc_ff_clk_src[] = { + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_ff_clk_src = { + .cmd_rcgr = 0x9474, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpu_cc_parent_map_0, + .freq_tbl = ftbl_gpu_cc_ff_clk_src, + .clkr.hw.init = &(const struct clk_init_data){ + .name = "gpu_cc_ff_clk_src", + .parent_data = gpu_cc_parent_data_0, + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = { + F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_gmu_clk_src = { + .cmd_rcgr = 0x9318, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpu_cc_parent_map_1, + .freq_tbl = ftbl_gpu_cc_gmu_clk_src, + .clkr.hw.init = &(const struct clk_init_data){ + .name = "gpu_cc_gmu_clk_src", + .parent_data = gpu_cc_parent_data_1, + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_1), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = { + F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_hub_clk_src = { + .cmd_rcgr = 0x93ec, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpu_cc_parent_map_2, + .freq_tbl = ftbl_gpu_cc_hub_clk_src, + .clkr.hw.init = &(const struct clk_init_data){ + .name = "gpu_cc_hub_clk_src", + .parent_data = gpu_cc_parent_data_2, + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_2), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gpu_cc_xo_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_xo_clk_src = { + .cmd_rcgr = 0x9010, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpu_cc_parent_map_3, + .freq_tbl = ftbl_gpu_cc_xo_clk_src, + .clkr.hw.init = &(const struct clk_init_data){ + .name = "gpu_cc_xo_clk_src", + .parent_data = gpu_cc_parent_data_3, + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_3), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_regmap_div gpu_cc_demet_div_clk_src = { + .reg = 0x9054, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_demet_div_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div gpu_cc_hub_ahb_div_clk_src = { + .reg = 0x9430, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_hub_ahb_div_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div gpu_cc_hub_cx_int_div_clk_src = { + .reg = 0x942c, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gpu_cc_hub_cx_int_div_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch gpu_cc_ahb_clk = { + .halt_reg = 0x911c, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x911c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gpu_cc_ahb_clk", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_hub_ahb_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cb_clk = { + .halt_reg = 0x93a4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x93a4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gpu_cc_cb_clk", + .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_crc_ahb_clk = { + .halt_reg = 0x9120, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x9120, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gpu_cc_crc_ahb_clk", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_hub_ahb_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_ff_clk = { + .halt_reg = 0x914c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x914c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gpu_cc_cx_ff_clk", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_ff_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_gmu_clk = { + .halt_reg = 0x913c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x913c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gpu_cc_cx_gmu_clk", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_gmu_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + .ops = &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_snoc_dvm_clk = { + .halt_reg = 0x9130, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x9130, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gpu_cc_cx_snoc_dvm_clk", + .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cxo_aon_clk = { + .halt_reg = 0x9004, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x9004, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gpu_cc_cxo_aon_clk", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cxo_clk = { + .halt_reg = 0x9144, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x9144, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gpu_cc_cxo_clk", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_xo_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_demet_clk = { + .halt_reg = 0x900c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x900c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gpu_cc_demet_clk", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_demet_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + .ops = &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = { + .halt_reg = 0x7000, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x7000, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gpu_cc_hlos1_vote_gpu_smmu_clk", + .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hub_aon_clk = { + .halt_reg = 0x93e8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x93e8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gpu_cc_hub_aon_clk", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_hub_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + .ops = &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_hub_cx_int_clk = { + .halt_reg = 0x9148, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x9148, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gpu_cc_hub_cx_int_clk", + .parent_hws = (const struct clk_hw*[]){ + &gpu_cc_hub_cx_int_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, + .ops = &clk_branch2_aon_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_memnoc_gfx_clk = { + .halt_reg = 0x9150, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x9150, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gpu_cc_memnoc_gfx_clk", + .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_sleep_clk = { + .halt_reg = 0x9134, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x9134, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "gpu_cc_sleep_clk", + .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap *gpu_cc_sa8775p_clocks[] = { + [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr, + [GPU_CC_CB_CLK] = &gpu_cc_cb_clk.clkr, + [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr, + [GPU_CC_CX_FF_CLK] = &gpu_cc_cx_ff_clk.clkr, + [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr, + [GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr, + [GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr, + [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr, + [GPU_CC_DEMET_CLK] = &gpu_cc_demet_clk.clkr, + [GPU_CC_DEMET_DIV_CLK_SRC] = &gpu_cc_demet_div_clk_src.clkr, + [GPU_CC_FF_CLK_SRC] = &gpu_cc_ff_clk_src.clkr, + [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr, + [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr, + [GPU_CC_HUB_AHB_DIV_CLK_SRC] = &gpu_cc_hub_ahb_div_clk_src.clkr, + [GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr, + [GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr, + [GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr, + [GPU_CC_HUB_CX_INT_DIV_CLK_SRC] = &gpu_cc_hub_cx_int_div_clk_src.clkr, + [GPU_CC_MEMNOC_GFX_CLK] = &gpu_cc_memnoc_gfx_clk.clkr, + [GPU_CC_PLL0] = &gpu_cc_pll0.clkr, + [GPU_CC_PLL1] = &gpu_cc_pll1.clkr, + [GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr, + [GPU_CC_XO_CLK_SRC] = &gpu_cc_xo_clk_src.clkr, +}; + +static struct gdsc cx_gdsc = { + .gdscr = 0x9108, + .gds_hw_ctrl = 0x953c, + .pd = { + .name = "cx_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = VOTABLE | RETAIN_FF_ENABLE | ALWAYS_ON, +}; + +static struct gdsc gx_gdsc = { + .gdscr = 0x905c, + .pd = { + .name = "gx_gdsc", + .power_on = gdsc_gx_do_nothing_enable, + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = AON_RESET | RETAIN_FF_ENABLE, +}; + +static struct gdsc *gpu_cc_sa8775p_gdscs[] = { + [GPU_CC_CX_GDSC] = &cx_gdsc, + [GPU_CC_GX_GDSC] = &gx_gdsc, +}; + +static const struct qcom_reset_map gpu_cc_sa8775p_resets[] = { + [GPUCC_GPU_CC_ACD_BCR] = { 0x9358 }, + [GPUCC_GPU_CC_CB_BCR] = { 0x93a0 }, + [GPUCC_GPU_CC_CX_BCR] = { 0x9104 }, + [GPUCC_GPU_CC_FAST_HUB_BCR] = { 0x93e4 }, + [GPUCC_GPU_CC_FF_BCR] = { 0x9470 }, + [GPUCC_GPU_CC_GFX3D_AON_BCR] = { 0x9198 }, + [GPUCC_GPU_CC_GMU_BCR] = { 0x9314 }, + [GPUCC_GPU_CC_GX_BCR] = { 0x9058 }, + [GPUCC_GPU_CC_XO_BCR] = { 0x9000 }, +}; + +static const struct regmap_config gpu_cc_sa8775p_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x9988, + .fast_io = true, +}; + +static const struct qcom_cc_desc gpu_cc_sa8775p_desc = { + .config = &gpu_cc_sa8775p_regmap_config, + .clks = gpu_cc_sa8775p_clocks, + .num_clks = ARRAY_SIZE(gpu_cc_sa8775p_clocks), + .resets = gpu_cc_sa8775p_resets, + .num_resets = ARRAY_SIZE(gpu_cc_sa8775p_resets), + .gdscs = gpu_cc_sa8775p_gdscs, + .num_gdscs = ARRAY_SIZE(gpu_cc_sa8775p_gdscs), +}; + +static const struct of_device_id gpu_cc_sa8775p_match_table[] = { + { .compatible = "qcom,sa8775p-gpucc" }, + { } +}; +MODULE_DEVICE_TABLE(of, gpu_cc_sa8775p_match_table); + +static int gpu_cc_sa8775p_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + + regmap = qcom_cc_map(pdev, &gpu_cc_sa8775p_desc); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + clk_lucid_evo_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); + clk_lucid_evo_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); + + /* + * Keep the clocks always-ON + * GPU_CC_CB_CLK + */ + regmap_update_bits(regmap, 0x93a4, BIT(0), BIT(0)); + + return qcom_cc_really_probe(pdev, &gpu_cc_sa8775p_desc, regmap); +} + +static struct platform_driver gpu_cc_sa8775p_driver = { + .probe = gpu_cc_sa8775p_probe, + .driver = { + .name = "gpu_cc-sa8775p", + .of_match_table = gpu_cc_sa8775p_match_table, + }, +}; + +static int __init gpu_cc_sa8775p_init(void) +{ + return platform_driver_register(&gpu_cc_sa8775p_driver); +} +subsys_initcall(gpu_cc_sa8775p_init); + +static void __exit gpu_cc_sa8775p_exit(void) +{ + platform_driver_unregister(&gpu_cc_sa8775p_driver); +} +module_exit(gpu_cc_sa8775p_exit); + +MODULE_DESCRIPTION("SA8775P GPUCC driver"); +MODULE_LICENSE("GPL"); From patchwork Tue Mar 28 19:36:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartosz Golaszewski X-Patchwork-Id: 76233 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2463828vqo; Tue, 28 Mar 2023 12:47:11 -0700 (PDT) X-Google-Smtp-Source: AK7set8AIxNBqhF0567w8LeIJ2X9wYUQ+zYL3S6wOyiKBO0QrxKVYxcUWVhbCRQdbQQFPfnWrTLz X-Received: by 2002:a05:6a20:b2f:b0:da:c40:8d6 with SMTP id x47-20020a056a200b2f00b000da0c4008d6mr14047787pzf.0.1680032831636; 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Cc: Arnd Bergmann Cc: Catalin Marinas Signed-off-by: Bartosz Golaszewski --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index d206a9120ee4..fa0a145defe2 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1161,6 +1161,7 @@ CONFIG_MSM_MMCC_8998=m CONFIG_MSM_GCC_8998=y CONFIG_QCS_GCC_404=y CONFIG_SA_GCC_8775P=y +CONFIG_SA_GPUCC_8775P=y CONFIG_SC_DISPCC_8280XP=m CONFIG_SC_GCC_7180=y CONFIG_SC_GCC_7280=y From patchwork Tue Mar 28 19:36:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartosz Golaszewski X-Patchwork-Id: 76236 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2464383vqo; Tue, 28 Mar 2023 12:48:17 -0700 (PDT) X-Google-Smtp-Source: AKy350aIj+XCUPATe+bEy7htXPa7bCq4LOXMZ5yRprc5io8rdDrZBm2Bh9L8YqHN4P56I7ucR40B X-Received: by 2002:a17:902:da82:b0:1a1:a996:feb3 with SMTP id j2-20020a170902da8200b001a1a996feb3mr22934043plx.26.1680032896912; Tue, 28 Mar 2023 12:48:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680032896; cv=none; d=google.com; s=arc-20160816; b=NqhoP8eFDpEozBCD4r8NjMdrjSEjB5Ya2J1CB1TubAGzr3C9aY6tccHLBgFWsNI5B0 jkQRYdjUa5TmAooxc3OGs4bA4ean14VngGgeeq3szBLnbir+IMbTBjmCJQ1Fk+T0xqsy qF9ShscbcPhjOBXvos1Juu9/Q6pererHjOVkBHH7xemCPjdxGFFS6rsDmxfsEcM5u0Ev Ozp7WAPfpE/ncHUhnzatNJzJz3azbXJiI3SmInNFdpy3yCaNbvd2pD5UswkdM0yc7xQX Y4viaC6Y9o9rumtgxpWS3UaH0f/hmw1k0zNk3P3scmXs0Sp5Ha4UiJAuBATA/nO1JPvU LC0Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=II92TSP623ZsHMmNH1N53jKIrTirkMn1oZIUlYAm+4I=; b=k7aeU0YNBlI4O9qgLq4pHRqZExQGSCfRtno3o3HlpRqqbr0cEA3HxCcL7C087EP0SP 9gXJ1zHq8zQJiWN72buDSIrnYwVJmmTqYAT91nSV2G/f09aCf4lIaYawxb4IYfkI+sk7 MvxpYputwnucqTnayEp+WlA81cehnAf2uruR2j/xiBCTQaC0nwkkLbIy9V/0+i3Db3PT MIxJsEhglbUEx+943FCpDaBp8NMraUhSCzgtdnZ4u2Di5S0XakW68JaYzQYu8LVUjeYY a2v/2YIwMFs0O8c2UDSqkNoMD989rcmbXtWlEU+Zu8l2bMCH+Y4MVobeP4aGCaWvkqs2 SueQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@bgdev-pl.20210112.gappssmtp.com header.s=20210112 header.b=UnBiVK6Y; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Enable it for sa8775p in the bindings. Cc: Will Deacon Cc: Robin Murphy Cc: Joerg Roedel Signed-off-by: Bartosz Golaszewski --- Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 1 - 1 file changed, 1 deletion(-) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index 807cb511fe18..74d5164ed1e8 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -375,7 +375,6 @@ allOf: - nvidia,smmu-500 - qcom,qcm2290-smmu-500 - qcom,qdu1000-smmu-500 - - qcom,sa8775p-smmu-500 - qcom,sc7180-smmu-500 - qcom,sc8180x-smmu-500 - qcom,sc8280xp-smmu-500 From patchwork Tue Mar 28 19:36:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartosz Golaszewski X-Patchwork-Id: 76234 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2463832vqo; Tue, 28 Mar 2023 12:47:12 -0700 (PDT) X-Google-Smtp-Source: AKy350ahqAn0bWxYynCDyMxf41YBx2Qs/75HMDgKsScq0ROrBZal+F/06rzPDQvUjDPHlSRNcHuQ X-Received: by 2002:a17:902:fb86:b0:1a2:17b1:70d with SMTP id lg6-20020a170902fb8600b001a217b1070dmr13898106plb.42.1680032831919; Tue, 28 Mar 2023 12:47:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680032831; cv=none; d=google.com; s=arc-20160816; b=zkC3jOkg7AUj80qRfclv+/CgXJ/9BmNdDcdAg6KVm6JYDrZrjiEewfHe/cHFXQj9yk B9OSS35h6EAOFBM+HtbqEjfVGaWGb7uTqo3eLRyOPygT049O9OjCr2Eb5h8lYcNXi3k5 s13upnO3rN34vKCcmoaYfSAJo6us+JNKENtkGYq6lv8YAfJq9LelQogTFteRY/pC6yZh ipq6DRdsONqMLyDZ7nrMf72t4CIy7NIzn0BVavBBDq6ylHJem3+es2Th7g+2GX4iL3il IstklGHFUeaKwMyJUGn4JtoP5i8fN9zOb3YIV6MSb+hl+EJou+W3tiiDINyzlUfy7NlG +4LQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=tXyJ56MXTgaGuaRJ30aQZ32hSfK274M12CnrDdVzkv0=; b=ITlAqPYktjim7wchQ7Eo3RKWh+lbU6/gcZ0L7W6IWrth5aG2bPRznKbq7wWvZxtleu zw62OGV1v8ejsVtq34sfwcnF2bVHgpXJrkbIshrSb8ofONiRQWgqMOPQzrWH9XkST+2Y nKDbt6op5iIXk/QPG50VMVbwnG5IRMegiuz4BtYd9YE/K75bW5EP5qvMMVEs3dHxrwm1 NYHqf6FJZQA1TvdkEe/zMZKn4KDAIMfG7RKxD0RajbvNBLnomJNxq3mfBv0qm5RfEMst w2/BiCnjeyyjSW13e1gAC/oMhwOF0XeSoJ8U1nEVblm1fyXc/FpYCIdCZbASpJwXhyhy rGbQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@bgdev-pl.20210112.gappssmtp.com header.s=20210112 header.b="7/ds7V0h"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 74 +++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 2343df7e0ea4..9ab630c7d81b 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -809,6 +809,80 @@ apps_smmu: iommu@15000000 { ; }; + pcie_smmu: iommu@15200000 { + compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x15200000 0x0 0x800000>; + #iommu-cells = <2>; + #global-interrupts = <2>; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + intc: interrupt-controller@17a00000 { compatible = "arm,gic-v3"; reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ From patchwork Tue Mar 28 19:36:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartosz Golaszewski X-Patchwork-Id: 76238 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2465976vqo; Tue, 28 Mar 2023 12:51:44 -0700 (PDT) X-Google-Smtp-Source: AKy350YmEMuRmtwtuEvkC7c5byBDozwL+OAv51Oeo/MKxBxSgIpun2UZJYIhFnG4bTiT6XDXeoGU X-Received: by 2002:aa7:9433:0:b0:5a0:c4b6:edd6 with SMTP id y19-20020aa79433000000b005a0c4b6edd6mr16482756pfo.0.1680033104501; Tue, 28 Mar 2023 12:51:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680033104; cv=none; d=google.com; s=arc-20160816; b=dgW+Mu9k8POH5/986qVHMplk+vT2CX24qeXD2x9JvBoUXWkla8YSZ13h1YuMq7r+Zu NDNAOnB6vebf3eL9mf/bDfq78fXbOFVIEUWkX0D7iGkOXZvnsM779pYRJLZ4MZwjqDTh /K6ok3ocuSYeY1K1hvPLVi3L+yCOL9csd8g5TgqcsMF1bFFbhWCbs6OA4SIV3gBjBf8T J5Sl0HYfak4tSpbbZD83Lpz1GWLn/lQSyVrHmr0xKHq1qSGFojPDXGhV5WsXUF3/c5/u 27R9RHkMzpdgfrYpJLqvINnR3lxZTWzvuBsQxXgfyBc4YN8NW5knWKHE1yBCuqYuZCbD 738Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=qPfw21v8gtigUsolrO+BT5/gzWDhSW7RBoQgHH2kESM=; b=cefH0WT6XvzRj9T01VnFh9+tjRY20e9EfsREVMXnDhnti11Zh3E5V/mqu7hNIm+wQ0 2Id5NAIjI49p4OL7RF9xHGuVP7A+fGdsu0BKNmdczb/h+TAKkZYf3MtAN2vgHo3K1lEQ vGYdlInhTWAAgKqnK2XGSJF9srhagnTcbYVoOHn225rco7YDeBJWB/K53vtNrbXyWCR+ 7xRbxIC74DFHgkeWb71urLrdaQ5i32IVvgt+DTyKdsjokOxRyB2DR5riTP2AHnG2Yvj0 WkzxaKlq9XypWd8BPYN7vyjxIXveXvuWezVo8iuATeKe/7LZG+c9wWqCz6Bfg+mBAtwl +sEw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@bgdev-pl.20210112.gappssmtp.com header.s=20210112 header.b="kF/rxL6H"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 9ab630c7d81b..4c45ad1cc7ff 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -591,6 +591,18 @@ tcsr_mutex: hwlock@1f40000 { #hwlock-cells = <1>; }; + gpucc: clock-controller@3d90000 { + compatible = "qcom,sa8775p-gpucc"; + reg = <0x0 0x03d90000 0x0 0xa000>; + clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sa8775p-pdc", "qcom,pdc"; reg = <0x0 0x0b220000 0x0 0x30000>, From patchwork Tue Mar 28 19:36:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartosz Golaszewski X-Patchwork-Id: 76237 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2464818vqo; Tue, 28 Mar 2023 12:49:15 -0700 (PDT) X-Google-Smtp-Source: AK7set/DwJZJ+FNPjirRK1/QZFwYtOTzW/nJZ0ZOrxnHILPlI1wucPBJj/nqLKfYXrCXnIBwFsjd X-Received: by 2002:a05:6a20:49a4:b0:da:834d:edd with SMTP id fs36-20020a056a2049a400b000da834d0eddmr15539147pzb.34.1680032955665; Tue, 28 Mar 2023 12:49:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680032955; cv=none; d=google.com; s=arc-20160816; b=NVHaNLVgsBFL8HGvgY1OygI9Bj+56GikcVCMQlPxVK49o5DILS4mXrdoPPuDisEbkj vSSSQFkBWy3VQ0dDfyDhImHIMKZ3mcgCjOMurHd/kuf6BUoYRHl8B6jYGhmZBOQ35XLY j4Rvqu2orvine1T5yQPncIuniWUHDUkZczU1esyYGHyNCPMpPi4qwwysiJMIJT0funuw R5MPXI+W+Fhs0f/QV6+NXhXHt/jYt1iuSMqacPJrh1Ap2Jgjydf4PbcpoyUdMwgr9scS h+VhE5vtB6UxqfyMSkPKDl5PHh/fgI3acVxw5VpkQGK+LMWigpRGSsLj2otQUasV7zh0 IfGQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=MnMzj7ZL79LUqbUVPGQil7x2FOJbb8kWmQlz9dfo7dA=; b=hUzQWrUItDIJP1qjKfm4VeGjZBqKf7CNb9ff3f+zHNHpfVP6J+NS8+e0kjowG1RPOD fqdpH5vgK1a5UILn/ycEigndgpsUhEF7doY0t68WkIbz1JCfknirCbAAc0zAWrxHnoDI 8pcy9onzslcytGiDDbcrPK2vo82GmIicqklX7JbSOJHqt8w7dVoXSpAKpBgX4/B21AWJ 06LQ4l2ikrR2sYC4z9BnPUVmL3pQs6Hm37vE/eI95nP5vMoxJC8w4brN9smIJDv3RS8e wAJrvciLmDYwvCt+7J+I8VhWbPqB5W8xzprwvXU87zYGoYystGRKGN4XJf5SqEXidE3F 1c2Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@bgdev-pl.20210112.gappssmtp.com header.s=20210112 header.b=xWi7Hv9N; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Bartosz Golaszewski --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 29 +++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 4c45ad1cc7ff..de5e8449397c 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -603,6 +604,34 @@ gpucc: clock-controller@3d90000 { #power-domain-cells = <1>; }; + kgsl_smmu: iommu@3da0000 { + compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x03da0000 0x0 0x20000>; + #iommu-cells = <2>; + #global-interrupts = <2>; + dma-coherent; + power-domains = <&gpucc GPU_CC_CX_GDSC>; + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_HUB_AON_CLK>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sa8775p-pdc", "qcom,pdc"; reg = <0x0 0x0b220000 0x0 0x30000>,