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[93.5.22.158]) by smtp.googlemail.com with ESMTPSA id j10-20020adff00a000000b002d1bfe3269esm27102109wro.59.2023.03.28.02.05.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Mar 2023 02:05:01 -0700 (PDT) From: Alexandre Mergnat Date: Tue, 28 Mar 2023 11:04:47 +0200 Subject: [PATCH v6 1/2] arm64: dts: mediatek: add i2c support for mt8365 SoC MIME-Version: 1.0 Message-Id: <20221122-mt8365-i2c-support-v6-1-e1009c8afd53@baylibre.com> References: <20221122-mt8365-i2c-support-v6-0-e1009c8afd53@baylibre.com> In-Reply-To: <20221122-mt8365-i2c-support-v6-0-e1009c8afd53@baylibre.com> To: Qii Wang , Rob Herring , Krzysztof Kozlowski , Matthias Brugger Cc: linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, Fabien Parent , Rob Herring , AngeloGioacchino Del Regno , Alexandre Mergnat X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2696; i=amergnat@baylibre.com; h=from:subject:message-id; bh=751COW4mlyt6NiZw3ZmEVilTCKVZTkOYnz6i1pHU/mc=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBkIq27A//D5eTADCDZW5waqfVl8NWE1cZPKo7QzgiC QRY+qwWJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCZCKtuwAKCRArRkmdfjHURdKcD/ 9dklIQyjq2bmzwRR1bmW/+ucAFmmdbP+ueL5/JvJgO2UYTKs0dAUjRvVeAlRUimE/+1PRxlG9vmw6R W2HSHcsx2m0stXGqwqLUeSGoO7VO61cHl3CD4ksm1sw8BIXkGee+9guQwuCpvm+G43Qik20amAVn4k 76j5WjfNGANer3cuTkBqFfcI2EpUy8G51UfKyfoBvHmy543aR0A8gccs4fptpVkcYqS7QF3q0xku9V Tb7icnO+irswsZGNe90mnAdzUPWf4cDlcLPH2AnddCHJ8F1jpeM804/cxzzi5zs51IL7hkg54TvkB8 4e+1jWeV64d5BxhUL+rcnRE0S9AsovOq+X+Nc7Vfr7sLnjTMCwojclLcQ9I03fRNJ5fAGs1x5uMzfR V8DSU3Xgzt5BcFjDbFjHIJf31Y9UgMWLexRz41gJcaiudvPPK0B9gjsEij78LnLoQD5O40Au45+hpv nDJOX7PHM5GrzSw0aowSIFZQVmmAb1I7JqHZqmUh4UijJf/czUMi95xVmQ6neBEAhwc0/2qy1g7f0J B5vqq34XX/Iyr08yVdl2oU/TW0V5AM6uA4gnsVQuBwMnCSc1QnDhuRbtf/7tdU5TDpvtaxomYodWa0 IE9TZtRb0iZR3iJBvgH+rRojySvGge/iZb2iWhmSnG8LnJfQRT3RZuD3Jniw== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 X-Spam-Status: No, score=0.0 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761601960789436533?= X-GMAIL-MSGID: =?utf-8?q?1761601960789436533?= There are four I2C master channels in MT8365 with a same HW architecture. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Alexandre Mergnat --- arch/arm64/boot/dts/mediatek/mt8365.dtsi | 48 ++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi index 15ac4c1f0966..b70f4d256f63 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -282,6 +282,42 @@ pwm: pwm@11006000 { clock-names = "top", "main", "pwm1", "pwm2", "pwm3"; }; + i2c0: i2c@11007000 { + compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; + reg = <0 0x11007000 0 0xa0>, <0 0x11000080 0 0x80>; + interrupts = ; + clock-div = <1>; + clocks = <&infracfg CLK_IFR_I2C0_AXI>, <&infracfg CLK_IFR_AP_DMA>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@11008000 { + compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; + reg = <0 0x11008000 0 0xa0>, <0 0x11000100 0 0x80>; + interrupts = ; + clock-div = <1>; + clocks = <&infracfg CLK_IFR_I2C1_AXI>, <&infracfg CLK_IFR_AP_DMA>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@11009000 { + compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; + reg = <0 0x11009000 0 0xa0>, <0 0x11000180 0 0x80>; + interrupts = ; + clock-div = <1>; + clocks = <&infracfg CLK_IFR_I2C2_AXI>, <&infracfg CLK_IFR_AP_DMA>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + spi: spi@1100a000 { compatible = "mediatek,mt8365-spi", "mediatek,mt7622-spi"; reg = <0 0x1100a000 0 0x100>; @@ -295,6 +331,18 @@ spi: spi@1100a000 { status = "disabled"; }; + i2c3: i2c@1100f000 { + compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; + reg = <0 0x1100f000 0 0xa0>, <0 0x11000200 0 0x80>; + interrupts = ; + clock-div = <1>; + clocks = <&infracfg CLK_IFR_I2C3_AXI>, <&infracfg CLK_IFR_AP_DMA>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + ssusb: usb@11201000 { compatible = "mediatek,mt8365-mtu3", "mediatek,mtu3"; reg = <0 0x11201000 0 0x2e00>, <0 0x11203e00 0 0x0100>; From patchwork Tue Mar 28 09:04:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Mergnat X-Patchwork-Id: 75916 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp2076316vqo; Tue, 28 Mar 2023 02:17:10 -0700 (PDT) X-Google-Smtp-Source: AK7set8nHxo6ZDjcdH//QKUD6SsGLt5ZEidGimDrb4p88xnju10aLApDTnQKGrhcLwW02OxBeK6g X-Received: by 2002:a05:6a20:8f0f:b0:cc:70df:ae20 with SMTP id b15-20020a056a208f0f00b000cc70dfae20mr19156513pzk.0.1679995029986; Tue, 28 Mar 2023 02:17:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1679995029; cv=none; d=google.com; s=arc-20160816; b=vgrQmH6u69VRVJn/oZFl+oOZYvYWiD33DP4wXpIuJ9+vRV8vEteXYRrHs4Ra9f0D1O wlOYevSUwdpYbk9fMRKoxq/NY7ZRLNrvXpPl+DZSa5NJR0H6880SvKlN0fd5dj7ufymL b+gvLAMqVEtsuTayyPRNMDoDt75dA9UOSjV7mWY+o60M+8XTOmNXt84Xhtd2Skt8MKxk RxcfuXNtWW8DG+P/7LB+MIgnvl3IrxQdgdbJSB3an88jMcYrUFFsTFWqo0zy4RJzO+VF zpOBlnTuQ3frzZ0Fu0ES/bnDMs9zgiJpUm0pAEyzLLp2BhhccpyIVItxNym2o4D8X7y1 jDPA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=uj5gr+4mPVvnfCNzOk8V4mj5Wru/QwptKiCL/eRZCmY=; b=NVbw3Ci/nqfFjQLoKGYN1KZWDfmlO9Q6HtNIkUCVQL5+PpdZkOF1rZ/XCCY4ZRpgmq P6EvYVyO7L/L3kXKodXyn9f4gTlWciyM5ffEi+4ylnLOax6PF6OBKdi0MZnEJWkitlnC G6cihCvIkzdMWYHvO7OOzQiZX+n13tqkyp6kmlm+jmxqh33LBVUi8w8XRVUNY4NC0mNN D2iEl9qbrF16224xuFAcddBVZ4HQB2gu4mufkX/DhgUFDc4GMLnNjt0hkwC7ZOlvgVZB LjIegU2iQnbYBmL6bZBxIOhR2LZk16dcl1hOPWQuQiLWqM+UKRaQVt71eFcVAAtoA516 2Vbw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20210112.gappssmtp.com header.s=20210112 header.b=qCkdQ2dq; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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[93.5.22.158]) by smtp.googlemail.com with ESMTPSA id j10-20020adff00a000000b002d1bfe3269esm27102109wro.59.2023.03.28.02.05.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Mar 2023 02:05:02 -0700 (PDT) From: Alexandre Mergnat Date: Tue, 28 Mar 2023 11:04:48 +0200 Subject: [PATCH v6 2/2] arm64: dts: mediatek: enable i2c0 for mt8365-evk board MIME-Version: 1.0 Message-Id: <20221122-mt8365-i2c-support-v6-2-e1009c8afd53@baylibre.com> References: <20221122-mt8365-i2c-support-v6-0-e1009c8afd53@baylibre.com> In-Reply-To: <20221122-mt8365-i2c-support-v6-0-e1009c8afd53@baylibre.com> To: Qii Wang , Rob Herring , Krzysztof Kozlowski , Matthias Brugger Cc: linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, Fabien Parent , Rob Herring , AngeloGioacchino Del Regno , Alexandre Mergnat X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1213; i=amergnat@baylibre.com; h=from:subject:message-id; bh=oenjaAD8yENugJ98bbechsKeee+bhy6mS/fPCtOzVTk=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBkIq27SlFTL8MC9k4ujZdwxuq3vNeLbQumhcib27er OgQI70uJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCZCKtuwAKCRArRkmdfjHURWz/D/ sFXI8s9TB/qi3jpFd/eIFHieqQczvcNbppzmtw2IaKeSYj4L5NQ2IHJq1BVTDqt4C+63+P6LudKs/o hurxwr/Gi7n7GxUIokB3Pqaiza0PmwZh/+ty8GmE25C2VrWXSXie6bwya9ciOcvzvRHjneZWzzwpNf 4GO+ZoXHAhS7HRzUxtrKUxuk1skldQszNlc+hPzcL9hzl+N+YNqxrFBbZaAjgqJ2RS/E49fp6r8vI8 0SaLRQHzOZOEDEioGdE/3MvytFVGEBiHuONio7h/O1+ae00ZHjcbfJ7Ns5kCQlUcjfWiTt4D5EIfe7 UhC6hGUtBOxjQzR5geXTtM8IjY4acENy2/MSpHEIWMLcGWF/IO2tmXzno/wdLPD2q4LPzSXYlCkrk+ ja8194zterVHQY9ecTD/KsDzfsgkAsnVB6cbCv2OxrihuzePBRZPoQhs3B/0a+nk9AqqTYt+DZviI4 trmjzAo3ykqHOxtdPdKRUpEsm/3ku8irhv9HQTCEgms7VHL4usqWTwE0MINlJePPNYTpgiIe4kOYDN UDIw3AWNImmYClwUcnX40Xas+gWTXU8UH5C47HH8aXmryu2Z3KEXqmItRiU9mu1askHaiJNLST3QyA etFbBfVE6NMlGxRUAbrHKkA1W1VLBKhkjh1h97cR9BcdwPBLg//URJnWqDBw== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 X-Spam-Status: No, score=0.0 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761602468248921743?= X-GMAIL-MSGID: =?utf-8?q?1761602468248921743?= Enable the I2C0 bus provides communication with: - The integrated RT9466 Switching Battery Charger. - The integrated MT6691 LP4X buck for VDDQ. - The integrated MT6691 LP4X buck for VDD2. - The pin header, to plug external I2C devices. Signed-off-by: Alexandre Mergnat Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts index 4683704ea235..adc79ba14b33 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts +++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts @@ -87,6 +87,13 @@ optee_reserved: optee@43200000 { }; }; +&i2c0 { + clock-frequency = <100000>; + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + &pio { gpio_keys: gpio-keys-pins { pins { @@ -96,6 +103,14 @@ pins { }; }; + i2c0_pins: i2c0-pins { + pins { + bias-pull-up; + pinmux = , + ; + }; + }; + uart0_pins: uart0-pins { pins { pinmux = ,