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[2620:137:e000::1:20]) by mx.google.com with ESMTP id x17-20020aa7dad1000000b004a18f2ffb81si29195348eds.321.2023.03.27.08.39.48; Mon, 27 Mar 2023 08:40:11 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=d1D9Hr7z; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232592AbjC0P2w (ORCPT + 99 others); Mon, 27 Mar 2023 11:28:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46406 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232621AbjC0P2s (ORCPT ); Mon, 27 Mar 2023 11:28:48 -0400 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 01FBC11D; Mon, 27 Mar 2023 08:28:41 -0700 (PDT) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 32RFSZ8K024960; Mon, 27 Mar 2023 10:28:35 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1679930915; bh=M/QhegHV0Q4kDE/iTuCWgzgOGM693VqyfQk/DupvKQI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=d1D9Hr7zsZMCGbvF8b62oooRexFEgvfpARIVyKUuz5Vi5zvSQK45VSCkIwqxbxI2Q QQW7doJxTs7cUUii24hP/bByYEHgqZvsmyKQdvsLKFrCdGUKS3ui+7xNuEtJxUGk1d eQHOty25u/2EvgDkMNiaupR48UnAjz+xJkMVjQ/g= Received: from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 32RFSZ26008974 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 27 Mar 2023 10:28:35 -0500 Received: from DFLE101.ent.ti.com (10.64.6.22) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Mon, 27 Mar 2023 10:28:35 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Mon, 27 Mar 2023 10:28:35 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 32RFSYWC004003; Mon, 27 Mar 2023 10:28:34 -0500 From: Devarsh Thakkar To: , , , , , , , , CC: , , , , , , , Subject: [PATCH v8 1/3] remoteproc: k3-r5: Simplify cluster mode setting usage Date: Mon, 27 Mar 2023 20:58:30 +0530 Message-ID: <20230327152832.923480-2-devarsht@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230327152832.923480-1-devarsht@ti.com> References: <20230327152832.923480-1-devarsht@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-2.5 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_PASS, SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761535969399329244?= X-GMAIL-MSGID: =?utf-8?q?1761535969399329244?= Check the validity of mode against SoC supported modes right at the probe to minimize the usage of same check further in the code. Set default value of cluster-mode only if cluster-mode device tree property is empty. In case devicetree provided cluster-mode property is invalid For e.g. using CLUSTER_MODE_SINGLECPU on any SoC other than am64x then return error. If firmware has set the PROC_BOOT_STATUS_FLAG_R5_SINGLECORE_ONLY flag then what it means is that only CLUSTER_MODE_SINGLECPU is possible to use [1] and hence there is no need to check for soc_data->single_cpu_mode first and then checking cluster mode. PROC_BOOT_CFG_FLAG_R5_SINGLE_CORE flag can be set directly for CLUSTER_MODE_SINGLECPU without checking for soc_data->single_cpu_mode since that check has already been done during probe. For IPC-only mode, directly override cluster mode as per config flag set by bootloader without checking for soc specific data. This because config flag would already have been validated by firmware when bootloader was setting it. Link: [1] https://software-dl.ti.com/tisci/esd/latest/2_tisci_msgs/security/PROC_BOOT.html?highlight=singlecore_only#arm-r5 Signed-off-by: Devarsh Thakkar --- V1->V6: No changelog (Patch introduced in V6) V6->V7: - Override to appropriate cluster mode per firmware status flag directly without checking for soc_data - Set appropriate mode as default if not provided in DT - Check mode validity against SoC data during probe - Rebase on top of 6.3 linux-next V7->V8: - Override cluster mode without using soc_data for IPC only mode as suggested in review --- drivers/remoteproc/ti_k3_r5_remoteproc.c | 76 +++++++++++++----------- 1 file changed, 40 insertions(+), 36 deletions(-) diff --git a/drivers/remoteproc/ti_k3_r5_remoteproc.c b/drivers/remoteproc/ti_k3_r5_remoteproc.c index 0481926c6975..fd035a83c816 100644 --- a/drivers/remoteproc/ti_k3_r5_remoteproc.c +++ b/drivers/remoteproc/ti_k3_r5_remoteproc.c @@ -852,38 +852,33 @@ static int k3_r5_rproc_configure(struct k3_r5_rproc *kproc) dev_dbg(dev, "boot_vector = 0x%llx, cfg = 0x%x ctrl = 0x%x stat = 0x%x\n", boot_vec, cfg, ctrl, stat); - /* check if only Single-CPU mode is supported on applicable SoCs */ - if (cluster->soc_data->single_cpu_mode) { - single_cpu = - !!(stat & PROC_BOOT_STATUS_FLAG_R5_SINGLECORE_ONLY); - if (single_cpu && cluster->mode == CLUSTER_MODE_SPLIT) { - dev_err(cluster->dev, "split-mode not permitted, force configuring for single-cpu mode\n"); - cluster->mode = CLUSTER_MODE_SINGLECPU; - } - goto config; + single_cpu = !!(stat & PROC_BOOT_STATUS_FLAG_R5_SINGLECORE_ONLY); + lockstep_en = !!(stat & PROC_BOOT_STATUS_FLAG_R5_LOCKSTEP_PERMITTED); + + /* Override to single CPU mode if set in status flag */ + if (single_cpu && cluster->mode == CLUSTER_MODE_SPLIT) { + dev_err(cluster->dev, "split-mode not permitted, force configuring for single-cpu mode\n"); + cluster->mode = CLUSTER_MODE_SINGLECPU; } - /* check conventional LockStep vs Split mode configuration */ - lockstep_en = !!(stat & PROC_BOOT_STATUS_FLAG_R5_LOCKSTEP_PERMITTED); + /* Override to split mode if lockstep enable bit is not set in status flag */ if (!lockstep_en && cluster->mode == CLUSTER_MODE_LOCKSTEP) { dev_err(cluster->dev, "lockstep mode not permitted, force configuring for split-mode\n"); cluster->mode = CLUSTER_MODE_SPLIT; } -config: /* always enable ARM mode and set boot vector to 0 */ boot_vec = 0x0; if (core == core0) { clr_cfg = PROC_BOOT_CFG_FLAG_R5_TEINIT; - if (cluster->soc_data->single_cpu_mode) { - /* - * Single-CPU configuration bit can only be configured - * on Core0 and system firmware will NACK any requests - * with the bit configured, so program it only on - * permitted cores - */ - if (cluster->mode == CLUSTER_MODE_SINGLECPU) - set_cfg = PROC_BOOT_CFG_FLAG_R5_SINGLE_CORE; + /* + * Single-CPU configuration bit can only be configured + * on Core0 and system firmware will NACK any requests + * with the bit configured, so program it only on + * permitted cores + */ + if (cluster->mode == CLUSTER_MODE_SINGLECPU) { + set_cfg = PROC_BOOT_CFG_FLAG_R5_SINGLE_CORE; } else { /* * LockStep configuration bit is Read-only on Split-mode @@ -1108,12 +1103,12 @@ static int k3_r5_rproc_configure_mode(struct k3_r5_rproc *kproc) struct k3_r5_cluster *cluster = kproc->cluster; struct k3_r5_core *core = kproc->core; struct device *cdev = core->dev; - bool r_state = false, c_state = false; + bool r_state = false, c_state = false, lockstep_en = false, single_cpu = false; u32 ctrl = 0, cfg = 0, stat = 0, halted = 0; u64 boot_vec = 0; u32 atcm_enable, btcm_enable, loczrama; struct k3_r5_core *core0; - enum cluster_mode mode; + enum cluster_mode mode = cluster->mode; int ret; core0 = list_first_entry(&cluster->cores, struct k3_r5_core, elem); @@ -1147,13 +1142,14 @@ static int k3_r5_rproc_configure_mode(struct k3_r5_rproc *kproc) atcm_enable = cfg & PROC_BOOT_CFG_FLAG_R5_ATCM_EN ? 1 : 0; btcm_enable = cfg & PROC_BOOT_CFG_FLAG_R5_BTCM_EN ? 1 : 0; loczrama = cfg & PROC_BOOT_CFG_FLAG_R5_TCM_RSTBASE ? 1 : 0; - if (cluster->soc_data->single_cpu_mode) { - mode = cfg & PROC_BOOT_CFG_FLAG_R5_SINGLE_CORE ? - CLUSTER_MODE_SINGLECPU : CLUSTER_MODE_SPLIT; - } else { - mode = cfg & PROC_BOOT_CFG_FLAG_R5_LOCKSTEP ? - CLUSTER_MODE_LOCKSTEP : CLUSTER_MODE_SPLIT; - } + single_cpu = cfg & PROC_BOOT_CFG_FLAG_R5_SINGLE_CORE ? 1 : 0; + lockstep_en = cfg & PROC_BOOT_CFG_FLAG_R5_LOCKSTEP ? 1 : 0; + + if (single_cpu) + mode = CLUSTER_MODE_SINGLECPU; + if (lockstep_en) + mode = CLUSTER_MODE_LOCKSTEP; + halted = ctrl & PROC_BOOT_CTRL_FLAG_R5_CORE_HALT; /* @@ -1700,12 +1696,6 @@ static int k3_r5_probe(struct platform_device *pdev) return -ENOMEM; cluster->dev = dev; - /* - * default to most common efuse configurations - Split-mode on AM64x - * and LockStep-mode on all others - */ - cluster->mode = data->single_cpu_mode ? - CLUSTER_MODE_SPLIT : CLUSTER_MODE_LOCKSTEP; cluster->soc_data = data; INIT_LIST_HEAD(&cluster->cores); @@ -1716,6 +1706,20 @@ static int k3_r5_probe(struct platform_device *pdev) return ret; } + if (ret == -EINVAL) { + /* + * default to most common efuse configurations - Split-mode on AM64x + * and LockStep-mode on all others + */ + cluster->mode = data->single_cpu_mode ? + CLUSTER_MODE_SPLIT : CLUSTER_MODE_LOCKSTEP; + } + + if (cluster->mode == CLUSTER_MODE_SINGLECPU && !data->single_cpu_mode) { + dev_err(dev, "Cluster mode = %d is not supported on this SoC\n", cluster->mode); + return -EINVAL; + } + num_cores = of_get_available_child_count(np); if (num_cores != 2) { dev_err(dev, "MCU cluster requires both R5F cores to be enabled, num_cores = %d\n", From patchwork Mon Mar 27 15:28:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Devarsh Thakkar X-Patchwork-Id: 75524 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1603584vqo; Mon, 27 Mar 2023 08:41:59 -0700 (PDT) X-Google-Smtp-Source: AKy350bq8+iafzSky6cHd54AQMG9Hg8EQhEzUNTdupp7GbO6/Q0ch18Qd+G/epZPjveydxesIHEB X-Received: by 2002:a17:906:641:b0:8b1:77bf:3bdd with SMTP id t1-20020a170906064100b008b177bf3bddmr13230522ejb.36.1679931719479; Mon, 27 Mar 2023 08:41:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1679931719; cv=none; d=google.com; s=arc-20160816; b=OmURF3umFGTfzA2nPFXHSVD0cBsmRIL/Rxfm0QJJDtlc3TtvZDCf7UtdH0UTn6LIOp Jdg8/kcaBo7Nqm25pElOKGmONTZyE6nKgWK+vOd+Zl4fgVAuzfkGFAbW9CwCMS0SV/tf NbzPadxm5+VIjrCFGqXFijZ/rseFjEfMnxTL2ixJfrzx41Hsw4lZ5ddEhqm8r2wzX1k5 lajityLQgjQz5asZpFDsSw3pwQWQEpMl0CMTbkUsIvBWX9Y/mMiozA5M1DqjGh5ORSA2 AcgUNPU78CWXo3Z1aXecXhxzboH2/3SrDujr+3B90Zdm/U3zP5h8TbaEJ+ijbCMJauq6 mGtA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=vjPmgr1P1Mrys6D8p7H2HqoMmj6Qy1uYR6ihimvAk8o=; b=CXRqzHgdXAddf8VAGYu4vWls41NP2fqWbvlt9ttW5P54n1fa7CDZ3n17rGD10e1Esd RZbNFOoLZdGFCgGUlW91cEjt/U9jzbNkA4mOhTe9TfAvyNZYYXSE4RoL0+Dn34WV+dLb an7w34En+Kg7hpwGSjQStcNecto+IZR1yBz+kGv0JdM3BuLptkBWtXNN+fSST2RUVEJF Xy+QiVl2lxFTNarAAKfO/ruUB4hCdk5Nseg4dcrVPV96zMIOxnZg60h0fJubSspmIi2Y 03vn+EfY0fPRz8CxpwBzkiZoF6ukZ3w0VAUumLLawCEjFHrusvk8b1K8NxdKRV7sBEWy 46sg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=MT47KrI4; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id r8-20020aa7da08000000b004c007c7905asi29283879eds.484.2023.03.27.08.41.35; Mon, 27 Mar 2023 08:41:59 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=MT47KrI4; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232628AbjC0P24 (ORCPT + 99 others); Mon, 27 Mar 2023 11:28:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46418 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232625AbjC0P2s (ORCPT ); Mon, 27 Mar 2023 11:28:48 -0400 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6891B2D69; Mon, 27 Mar 2023 08:28:43 -0700 (PDT) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 32RFSb5O120976; Mon, 27 Mar 2023 10:28:37 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1679930917; bh=vjPmgr1P1Mrys6D8p7H2HqoMmj6Qy1uYR6ihimvAk8o=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=MT47KrI44Sdl+iUToBkoLKEF/zOsjsO5dNlYyMsQE5W+bvDsDkWNYQSZocvmgr5oA FTbLhjPhqh0tdE/W5TmANIydOXSuz2M3mReunnrW+7Vfu+uvUTb6lJ0aCfrwAOX4i+ 7vDp5E95qYljlYPsViG3ukMZvlezfCWadp40VRJQ= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 32RFSaZv098690 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 27 Mar 2023 10:28:37 -0500 Received: from DFLE108.ent.ti.com (10.64.6.29) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Mon, 27 Mar 2023 10:28:36 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Mon, 27 Mar 2023 10:28:36 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 32RFSZML103666; Mon, 27 Mar 2023 10:28:36 -0500 From: Devarsh Thakkar To: , , , , , , , , CC: , , , , , , , Subject: [PATCH v8 2/3] dt-bindings: remoteproc: ti: Add new compatible for AM62 SoC family Date: Mon, 27 Mar 2023 20:58:31 +0530 Message-ID: <20230327152832.923480-3-devarsht@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230327152832.923480-1-devarsht@ti.com> References: <20230327152832.923480-1-devarsht@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-2.5 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_PASS, SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761536082668308642?= X-GMAIL-MSGID: =?utf-8?q?1761536082668308642?= AM62 family of devices don't have a R5F cluster, instead they have single core DM R5F. Add new compatible string ti,am62-r5fss to support this scenario. When this new compatible is used cluster-mode property can only be set to value 3 i.e. CLUSTER_MODE_SINGLECORE which is also the default value in case cluster-mode is not defined in device-tree. While at it, also sort the compatible lists in alphabetical order. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Devarsh Thakkar --- V2: Avoid acronyms, use "Device Manager" instead of "DM" V3: - Use separate if block for each compatible for ti,cluster-mode property - Rearrange compatibles as per alphabatical order V4: Place each enum in separate line in allOf V5: No change (fixing typo in email address) V6: Remove reviewed-by due to new modifications to Use cluster-mode=3 for am62x V7: No change V8: Add Reviewed-By --- .../bindings/remoteproc/ti,k3-r5f-rproc.yaml | 76 ++++++++++++++----- 1 file changed, 55 insertions(+), 21 deletions(-) diff --git a/Documentation/devicetree/bindings/remoteproc/ti,k3-r5f-rproc.yaml b/Documentation/devicetree/bindings/remoteproc/ti,k3-r5f-rproc.yaml index fb9605f0655b..fcc3db97fe8f 100644 --- a/Documentation/devicetree/bindings/remoteproc/ti,k3-r5f-rproc.yaml +++ b/Documentation/devicetree/bindings/remoteproc/ti,k3-r5f-rproc.yaml @@ -21,6 +21,9 @@ description: | called "Single-CPU" mode, where only Core0 is used, but with ability to use Core1's TCMs as well. + AM62 SoC family support a single R5F core only which runs Device Manager + firmware and can also be used as a remote processor with IPC communication. + Each Dual-Core R5F sub-system is represented as a single DTS node representing the cluster, with a pair of child DT nodes representing the individual R5F cores. Each node has a number of required or optional @@ -34,10 +37,11 @@ properties: compatible: enum: + - ti,am62-r5fss + - ti,am64-r5fss - ti,am654-r5fss - - ti,j721e-r5fss - ti,j7200-r5fss - - ti,am64-r5fss + - ti,j721e-r5fss - ti,j721s2-r5fss power-domains: @@ -64,10 +68,17 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32 description: | Configuration Mode for the Dual R5F cores within the R5F cluster. - Should be either a value of 1 (LockStep mode) or 0 (Split mode) on + For most SoCs (AM65x, J721E, J7200, J721s2), + It should be either a value of 1 (LockStep mode) or 0 (Split mode) on most SoCs (AM65x, J721E, J7200, J721s2), default is LockStep mode if - omitted; and should be either a value of 0 (Split mode) or 2 - (Single-CPU mode) on AM64x SoCs, default is Split mode if omitted. + omitted. + For AM64x SoCs, + It should be either a value of 0 (Split mode) or 2 (Single-CPU mode) and + default is Split mode if omitted. + For AM62x SoCs, + It should be set as 3 (Single-Core mode) which is also the default if + omitted. + # R5F Processor Child Nodes: # ========================== @@ -80,7 +91,9 @@ patternProperties: node representing a TI instantiation of the Arm Cortex R5F core. There are some specific integration differences for the IP like the usage of a Region Address Translator (RAT) for translating the larger SoC bus - addresses into a 32-bit address space for the processor. + addresses into a 32-bit address space for the processor. For AM62x, + the R5F Sub-System device node should only define one R5F child node + as it has only one core available. Each R5F core has an associated 64 KB of Tightly-Coupled Memory (TCM) internal memories split between two banks - TCMA and TCMB (further @@ -100,10 +113,11 @@ patternProperties: properties: compatible: enum: + - ti,am62-r5f + - ti,am64-r5f - ti,am654-r5f - - ti,j721e-r5f - ti,j7200-r5f - - ti,am64-r5f + - ti,j721e-r5f - ti,j721s2-r5f reg: @@ -208,19 +222,39 @@ patternProperties: unevaluatedProperties: false -if: - properties: - compatible: - enum: - - ti,am64-r5fss -then: - properties: - ti,cluster-mode: - enum: [0, 2] -else: - properties: - ti,cluster-mode: - enum: [0, 1] +allOf: + - if: + properties: + compatible: + enum: + - ti,am64-r5fss + then: + properties: + ti,cluster-mode: + enum: [0, 2] + + - if: + properties: + compatible: + enum: + - ti,am654-r5fss + - ti,j7200-r5fss + - ti,j721e-r5fss + - ti,j721s2-r5fss + then: + properties: + ti,cluster-mode: + enum: [0, 1] + + - if: + properties: + compatible: + enum: + - ti,am62-r5fss + then: + properties: + ti,cluster-mode: + enum: [3] required: - compatible From patchwork Mon Mar 27 15:28:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Devarsh Thakkar X-Patchwork-Id: 75521 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1602338vqo; Mon, 27 Mar 2023 08:39:38 -0700 (PDT) X-Google-Smtp-Source: AKy350buv7MtDdDUceE3v6nCGmYdQdSqT8X8eAO7PuqUyFLywXYIJ3/pDOe4PlpDFyESYe2HgRfZ X-Received: by 2002:a17:906:eb8e:b0:885:fee4:69ee with SMTP id mh14-20020a170906eb8e00b00885fee469eemr14140972ejb.59.1679931578247; Mon, 27 Mar 2023 08:39:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1679931578; cv=none; d=google.com; s=arc-20160816; b=D5Jm3dVmrxX/drUk4yNDtWHUchyerfnrDnmUrt8JXeeY80FKlBR9AdQVC/O1Gd71E+ wRYCfu0/h0bQJw7qYOpCTLU1YoT1YHw5ZdnkHJLVsmQ9fGZcmXjGGqkDA3oTqEEbPjf6 8NDXoTZQjG8xWjtzqx5inNnkdSdT/wb3G2TFWFiw3fgQc9RIMpeOXeKSD95nN3VzFr45 MUhlgbyemOARdGt6MAGHS13CkBzdCkQWUPhD+k3o7No0+yrBrVwSn9PviHGaM2GRPh8M 8Hgm8xdOfUtzLPR0oFdiimg2nv2AFTwxbOfbbwUbS5+OBhcy48h3tEkQU58aJxxxAA4a 0c6w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=zt3pOWn9K5Wouelw0ko0yLSeUY0SgQ9GcrAN3rMCXzU=; b=JKG7RBk3qpAuiN9YbkBaSF1zAPjLj5vueFMz8IWFo/0w4CKvunuGFFzaYX/2i8J3t4 BsbJVuhNDSOgvbohWJAUAC40b/1FtjlGp79OYiddqK9WkIYNQ2fVRddG2QoN6ocUUHJD LAoLub870jFv24inUiOhVOdX/uuyAWKAg0jluhgEoKwjdrO1v/4SMQltJcXXOcIp5uW5 vizc7Vii9+CPAyu5ngIkGMNgF901ozFmJhv163Ut5YIAQLYQ9ExvL24K5KqVkqGP0U+a OXZG7EB61jyiz2wRW6NZGnGPFyHc0uEpJsn6zXZU5InjBmG13sC8bXe7JkhddhRkIMQ7 WO9A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=tVHSk+Di; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from out1.vger.email (out1.vger.email. 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To support this single core scenario map it with newly defined CLUSTER_MODE_SINGLECORE and use it when compatible is set to ti,am62-r5fss. Also set PROC_BOOT_CFG_FLAG_R5_SINGLE_CORE config for CLUSTER_MODE_SINGLECORE too as it is required by R5 core when it is being as general purpose core instead of device manager. For IPC-only mode when config flag PROC_BOOT_CFG_FLAG_R5_SINGLE_CORE is set, skip overriding to CLUSTER_MODE_SINGLECPU when CLUSTER_MODE_SINGLECORE is set as same flag is applicable for single core configuration too. Signed-off-by: Devarsh Thakkar --- V2: - Fix indentation and ordering issues as per review comments V3: - Change CLUSTER_MODE_NONE value to -1 V4: - No change V5: - No change (fixing typo in email address) V6: - Use CLUSTER_MODE_SINGLECORE for AM62x - Set PROC_BOOT_CFG_FLAG_R5_SINGLE_CORE for single core. V7: - Simplify and rebase on top of base commit "[PATCH v7] remoteproc: k3-r5: Simplify cluster mode setting" V8: - Rebase on top of base commit "[PATCH v8] remoteproc: k3-r5: Simplify cluster mode setting" Signed-off-by: Devarsh Thakkar --- drivers/remoteproc/ti_k3_r5_remoteproc.c | 59 +++++++++++++++++++----- 1 file changed, 47 insertions(+), 12 deletions(-) diff --git a/drivers/remoteproc/ti_k3_r5_remoteproc.c b/drivers/remoteproc/ti_k3_r5_remoteproc.c index fd035a83c816..23fe44d4d7a5 100644 --- a/drivers/remoteproc/ti_k3_r5_remoteproc.c +++ b/drivers/remoteproc/ti_k3_r5_remoteproc.c @@ -71,14 +71,16 @@ struct k3_r5_mem { /* * All cluster mode values are not applicable on all SoCs. The following * are the modes supported on various SoCs: - * Split mode : AM65x, J721E, J7200 and AM64x SoCs - * LockStep mode : AM65x, J721E and J7200 SoCs - * Single-CPU mode : AM64x SoCs only + * Split mode : AM65x, J721E, J7200 and AM64x SoCs + * LockStep mode : AM65x, J721E and J7200 SoCs + * Single-CPU mode : AM64x SoCs only + * Single-Core mode : AM62x, AM62A SoCs */ enum cluster_mode { CLUSTER_MODE_SPLIT = 0, CLUSTER_MODE_LOCKSTEP, CLUSTER_MODE_SINGLECPU, + CLUSTER_MODE_SINGLECORE }; /** @@ -86,11 +88,13 @@ enum cluster_mode { * @tcm_is_double: flag to denote the larger unified TCMs in certain modes * @tcm_ecc_autoinit: flag to denote the auto-initialization of TCMs for ECC * @single_cpu_mode: flag to denote if SoC/IP supports Single-CPU mode + * @is_single_core: flag to denote if SoC/IP has only single core R5 */ struct k3_r5_soc_data { bool tcm_is_double; bool tcm_ecc_autoinit; bool single_cpu_mode; + bool is_single_core; }; /** @@ -838,7 +842,8 @@ static int k3_r5_rproc_configure(struct k3_r5_rproc *kproc) core0 = list_first_entry(&cluster->cores, struct k3_r5_core, elem); if (cluster->mode == CLUSTER_MODE_LOCKSTEP || - cluster->mode == CLUSTER_MODE_SINGLECPU) { + cluster->mode == CLUSTER_MODE_SINGLECPU || + cluster->mode == CLUSTER_MODE_SINGLECORE) { core = core0; } else { core = kproc->core; @@ -877,7 +882,8 @@ static int k3_r5_rproc_configure(struct k3_r5_rproc *kproc) * with the bit configured, so program it only on * permitted cores */ - if (cluster->mode == CLUSTER_MODE_SINGLECPU) { + if (cluster->mode == CLUSTER_MODE_SINGLECPU || + cluster->mode == CLUSTER_MODE_SINGLECORE) { set_cfg = PROC_BOOT_CFG_FLAG_R5_SINGLE_CORE; } else { /* @@ -1069,6 +1075,7 @@ static void k3_r5_adjust_tcm_sizes(struct k3_r5_rproc *kproc) if (cluster->mode == CLUSTER_MODE_LOCKSTEP || cluster->mode == CLUSTER_MODE_SINGLECPU || + cluster->mode == CLUSTER_MODE_SINGLECORE || !cluster->soc_data->tcm_is_double) return; @@ -1145,7 +1152,7 @@ static int k3_r5_rproc_configure_mode(struct k3_r5_rproc *kproc) single_cpu = cfg & PROC_BOOT_CFG_FLAG_R5_SINGLE_CORE ? 1 : 0; lockstep_en = cfg & PROC_BOOT_CFG_FLAG_R5_LOCKSTEP ? 1 : 0; - if (single_cpu) + if (single_cpu && mode != CLUSTER_MODE_SINGLECORE) mode = CLUSTER_MODE_SINGLECPU; if (lockstep_en) mode = CLUSTER_MODE_LOCKSTEP; @@ -1265,9 +1272,12 @@ static int k3_r5_cluster_rproc_init(struct platform_device *pdev) goto err_add; } - /* create only one rproc in lockstep mode or single-cpu mode */ + /* create only one rproc in lockstep, single-cpu or + * single core mode + */ if (cluster->mode == CLUSTER_MODE_LOCKSTEP || - cluster->mode == CLUSTER_MODE_SINGLECPU) + cluster->mode == CLUSTER_MODE_SINGLECPU || + cluster->mode == CLUSTER_MODE_SINGLECORE) break; } @@ -1710,19 +1720,33 @@ static int k3_r5_probe(struct platform_device *pdev) /* * default to most common efuse configurations - Split-mode on AM64x * and LockStep-mode on all others + * default to most common efuse configurations - + * Split-mode on AM64x + * Single core on AM62x + * LockStep-mode on all others */ - cluster->mode = data->single_cpu_mode ? + if (!data->is_single_core) + cluster->mode = data->single_cpu_mode ? CLUSTER_MODE_SPLIT : CLUSTER_MODE_LOCKSTEP; + else + cluster->mode = CLUSTER_MODE_SINGLECORE; } - if (cluster->mode == CLUSTER_MODE_SINGLECPU && !data->single_cpu_mode) { + if ((cluster->mode == CLUSTER_MODE_SINGLECPU && !data->single_cpu_mode) || + (cluster->mode == CLUSTER_MODE_SINGLECORE && !data->is_single_core)) { dev_err(dev, "Cluster mode = %d is not supported on this SoC\n", cluster->mode); return -EINVAL; } num_cores = of_get_available_child_count(np); - if (num_cores != 2) { - dev_err(dev, "MCU cluster requires both R5F cores to be enabled, num_cores = %d\n", + if (num_cores != 2 && !data->is_single_core) { + dev_err(dev, "MCU cluster requires both R5F cores to be enabled but num_cores is set to = %d\n", + num_cores); + return -ENODEV; + } + + if (num_cores != 1 && data->is_single_core) { + dev_err(dev, "SoC supports only single core R5 but num_cores is set to %d\n", num_cores); return -ENODEV; } @@ -1764,18 +1788,28 @@ static const struct k3_r5_soc_data am65_j721e_soc_data = { .tcm_is_double = false, .tcm_ecc_autoinit = false, .single_cpu_mode = false, + .is_single_core = false, }; static const struct k3_r5_soc_data j7200_j721s2_soc_data = { .tcm_is_double = true, .tcm_ecc_autoinit = true, .single_cpu_mode = false, + .is_single_core = false, }; static const struct k3_r5_soc_data am64_soc_data = { .tcm_is_double = true, .tcm_ecc_autoinit = true, .single_cpu_mode = true, + .is_single_core = false, +}; + +static const struct k3_r5_soc_data am62_soc_data = { + .tcm_is_double = false, + .tcm_ecc_autoinit = true, + .single_cpu_mode = false, + .is_single_core = true, }; static const struct of_device_id k3_r5_of_match[] = { @@ -1783,6 +1817,7 @@ static const struct of_device_id k3_r5_of_match[] = { { .compatible = "ti,j721e-r5fss", .data = &am65_j721e_soc_data, }, { .compatible = "ti,j7200-r5fss", .data = &j7200_j721s2_soc_data, }, { .compatible = "ti,am64-r5fss", .data = &am64_soc_data, }, + { .compatible = "ti,am62-r5fss", .data = &am62_soc_data, }, { .compatible = "ti,j721s2-r5fss", .data = &j7200_j721s2_soc_data, }, { /* sentinel */ }, };