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[2620:137:e000::1:20]) by mx.google.com with ESMTP id y63-20020a638a42000000b004588a5bd0bfsi19391766pgd.569.2022.10.20.01.58.01; Thu, 20 Oct 2022 01:58:14 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=Y60UZf9O; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230096AbiJTIwu (ORCPT + 99 others); Thu, 20 Oct 2022 04:52:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57636 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230190AbiJTIw1 (ORCPT ); Thu, 20 Oct 2022 04:52:27 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 600DD1929BB; Thu, 20 Oct 2022 01:52:15 -0700 (PDT) X-UUID: 0b8c80ff656e4f829ed817df65990b24-20221020 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=AJ2M5XJKl6SRTMP63loV//P+jxWoSU8S0YiLYNWgiqg=; b=Y60UZf9OQLJeGqBdI+wbaBzbsYecqrlemipSxVMVX6ILyTDs63+Tdbe0BbdGacWuF299E3bGrHBQsxsMNuZ+TiYDCAMph+tW5sVvAwVJrDiOCAepIC4w8EoAvfWOvQZRl/p7US/2rOwSHWku+VLbJpzVVSb1ByK4gsx58AVARWY=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.12,REQID:48c55b20-91a9-4b8d-b687-286e895148cc,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:62cd327,CLOUDID:4e75e3ee-314c-4293-acb8-ca4299dd021f,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 0b8c80ff656e4f829ed817df65990b24-20221020 Received: from mtkmbs11n2.mediatek.inc [(172.21.101.187)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 985525040; Thu, 20 Oct 2022 16:52:08 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Thu, 20 Oct 2022 16:52:07 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Thu, 20 Oct 2022 16:52:06 +0800 From: Biao Huang To: AngeloGioacchino Del Regno , "Rob Herring" , Krzysztof Kozlowski , Matthias Brugger CC: , , , , "Biao Huang" , Subject: [PATCH v4] arm64: dts: mt8195: Add Ethernet controller Date: Thu, 20 Oct 2022 16:52:03 +0800 Message-ID: <20221020085203.1974-2-biao.huang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221020085203.1974-1-biao.huang@mediatek.com> References: <20221020085203.1974-1-biao.huang@mediatek.com> MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS, SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1746928976263965778?= X-GMAIL-MSGID: =?utf-8?q?1747196360672447622?= Add Ethernet controller node for mt8195. Signed-off-by: Biao Huang Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8195-demo.dts | 88 ++++++++++++++++++++ arch/arm64/boot/dts/mediatek/mt8195.dtsi | 86 +++++++++++++++++++ 2 files changed, 174 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts index 4fbd99eb496a..0e8496d837ef 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts +++ b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts @@ -258,6 +258,72 @@ &mt6359_vsram_others_ldo_reg { }; &pio { + eth_default_pins: eth-default-pins { + pins-txd { + pinmux = , + , + , + ; + drive-strength = ; + }; + pins-cc { + pinmux = , + , + , + ; + drive-strength = ; + }; + pins-rxd { + pinmux = , + , + , + ; + }; + pins-mdio { + pinmux = , + ; + input-enable; + }; + pins-power { + pinmux = , + ; + output-high; + }; + }; + + eth_sleep_pins: eth-sleep-pins { + pins-txd { + pinmux = , + , + , + ; + }; + pins-cc { + pinmux = , + , + , + ; + }; + pins-rxd { + pinmux = , + , + , + ; + }; + pins-mdio { + pinmux = , + ; + input-disable; + bias-disable; + }; + pins-power { + pinmux = , + ; + input-disable; + bias-disable; + }; + }; + gpio_keys_pins: gpio-keys-pins { pins { pinmux = ; @@ -434,6 +500,28 @@ &xhci0 { status = "okay"; }; +ð { + phy-mode ="rgmii-rxid"; + phy-handle = <ðernet_phy0>; + snps,reset-gpio = <&pio 93 GPIO_ACTIVE_HIGH>; + snps,reset-delays-us = <0 10000 10000>; + mediatek,tx-delay-ps = <2030>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <ð_default_pins>; + pinctrl-1 = <ð_sleep_pins>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + ethernet_phy0: ethernet-phy@1 { + compatible = "ethernet-phy-id001c.c916"; + reg = <0x1>; + }; + }; +}; + &xhci1 { vusb33-supply = <&mt6359_vusb_ldo_reg>; status = "okay"; diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 905d1a90b406..0639ad9d261c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1042,6 +1042,92 @@ spis1: spi@1101e000 { status = "disabled"; }; + eth: ethernet@11021000 { + compatible = "mediatek,mt8195-gmac", "snps,dwmac-5.10a"; + reg = <0 0x11021000 0 0x4000>; + interrupts = ; + interrupt-names = "macirq"; + clock-names = "axi", + "apb", + "mac_cg", + "mac_main", + "ptp_ref", + "rmii_internal"; + clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET>, + <&pericfg_ao CLK_PERI_AO_ETHERNET_BUS>, + <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>, + <&topckgen CLK_TOP_SNPS_ETH_250M>, + <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>, + <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>; + assigned-clocks = <&topckgen CLK_TOP_SNPS_ETH_250M>, + <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>, + <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>; + assigned-clock-parents = <&topckgen CLK_TOP_ETHPLL_D2>, + <&topckgen CLK_TOP_ETHPLL_D8>, + <&topckgen CLK_TOP_ETHPLL_D10>; + power-domains = <&spm MT8195_POWER_DOMAIN_ETHER>; + mediatek,pericfg = <&infracfg_ao>; + snps,axi-config = <&stmmac_axi_setup>; + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + snps,txpbl = <16>; + snps,rxpbl = <16>; + snps,clk-csr = <0>; + status = "disabled"; + + stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <0x7>; + snps,rd_osr_lmt = <0x7>; + snps,blen = <0 0 0 0 16 8 4>; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <4>; + snps,rx-sched-sp; + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + }; + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + }; + queue2 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + }; + queue3 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <4>; + snps,tx-sched-wrr; + queue0 { + snps,weight = <0x10>; + snps,dcb-algorithm; + snps,priority = <0x0>; + }; + queue1 { + snps,weight = <0x11>; + snps,dcb-algorithm; + snps,priority = <0x1>; + }; + queue2 { + snps,weight = <0x12>; + snps,dcb-algorithm; + snps,priority = <0x2>; + }; + queue3 { + snps,weight = <0x13>; + snps,dcb-algorithm; + snps,priority = <0x3>; + }; + }; + }; + xhci0: usb@11200000 { compatible = "mediatek,mt8195-xhci", "mediatek,mtk-xhci";