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[8.43.85.97]) by mx.google.com with ESMTPS id kt22-20020a170906aad600b0092522b9937dsi20002170ejb.320.2023.03.23.04.48.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Mar 2023 04:48:18 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 4AE26385043E for ; Thu, 23 Mar 2023 11:48:13 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from esa4.mentor.iphmx.com (esa4.mentor.iphmx.com [68.232.137.252]) by sourceware.org (Postfix) with ESMTPS id E6E413858C20 for ; Thu, 23 Mar 2023 11:47:48 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org E6E413858C20 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=codesourcery.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=mentor.com X-IronPort-AV: E=Sophos;i="5.98,283,1673942400"; d="scan'208";a="96935" Received: from orw-gwy-02-in.mentorg.com ([192.94.38.167]) by esa4.mentor.iphmx.com with ESMTP; 23 Mar 2023 03:47:46 -0800 IronPort-SDR: haMIf+EIfiWp/oR1KsJ0JAI8rHRR5MXq25rrEOF9SWGpXzFObuKNXfjjFm0kADVwvCqpCK9pr3 24lPa7UAFu0xhDYPF3UGb3juFwA1EDhwWl9Jm1Md9pJzn7RVL3axcb1MQB8pgTChBdn562jncb TkYTjwFg6QPVDpOyR4arYJs1fofhvAq20qqGyrdzfOOvae0IJn4+PkbW+sgQSlv4JEiQoJTTfV MM5fXtin9mgLqBU829Kg+PJVYK4qLhQ4jydroAD8YLdojGTdP9+nwOUlPIxELMBqyh2g+V1zNM PXA= Message-ID: <3da64e3a-9067-77dd-374e-664445af3344@codesourcery.com> Date: Thu, 23 Mar 2023 11:47:41 +0000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.9.0 Content-Language: en-GB From: Andrew Stubbs Subject: [committed] amdgcn: Fix register size bug To: "gcc-patches@gcc.gnu.org" X-Originating-IP: [137.202.0.90] X-ClientProxiedBy: svr-ies-mbx-11.mgc.mentorg.com (139.181.222.11) To svr-ies-mbx-11.mgc.mentorg.com (139.181.222.11) X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, KAM_DMARC_STATUS, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761158993296033311?= X-GMAIL-MSGID: =?utf-8?q?1761158993296033311?= This patch fixes a bug in which the function prologue would save more registers to the stack than there was space allocated. This would cause data corruption when the epilogue restored the registers if a child function had overwritten that memory. The problem was caused by insn constraints that allow vectors to be placed in scalar registers. This isn't usually allowed without an explicit vec_duplicate in the pattern, but some post-reload splitters do it sometimes (hence the size calculation mismatch). A full fix would add vec_duplicate variants of all the instructions that support this, but that's a huge explosion of patterns, and this fix is enough for correctness, for now. This has already been committed to the OG12 branch. Andrew amdgcn: Fix register size bug Fix an issue in which "vectors" of duplicate entries placed in scalar registers caused the following 63 registers to be marked live, for the purpose of prologue generation, which resulted in stack corruption. gcc/ChangeLog: * config/gcn/gcn.cc (gcn_class_max_nregs): Handle vectors in SGPRs. (move_callee_saved_registers): Detect the bug condition early. diff --git a/gcc/config/gcn/gcn.cc b/gcc/config/gcn/gcn.cc index 5bf88e98083..a7d278cd2f8 100644 --- a/gcc/config/gcn/gcn.cc +++ b/gcc/config/gcn/gcn.cc @@ -492,6 +492,15 @@ gcn_class_max_nregs (reg_class_t rclass, machine_mode mode) } else if (rclass == VCC_CONDITIONAL_REG && mode == BImode) return 2; + + /* Vector modes in SGPRs are not supposed to happen (disallowed by + gcn_hard_regno_mode_ok), but there are some patterns that have an "Sv" + constraint and are used by splitters, post-reload. + This ensures that we don't accidentally mark the following 63 scalar + registers as "live". */ + if (rclass == SGPR_REGS && VECTOR_MODE_P (mode)) + return CEIL (GET_MODE_SIZE (GET_MODE_INNER (mode)), 4); + return CEIL (GET_MODE_SIZE (mode), 4); } @@ -3239,6 +3248,10 @@ move_callee_saved_registers (rtx sp, machine_function *offsets, emit_insn (move_vectors); emit_insn (move_scalars); } + + /* This happens when a new register becomes "live" after reload. + Check your splitters! */ + gcc_assert (offset <= offsets->callee_saves); } /* Generate prologue. Called from gen_prologue during pro_and_epilogue pass.