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[2620:137:e000::1:20]) by mx.google.com with ESMTP id d21-20020a50fb15000000b004c074367506si17423864edq.307.2023.03.23.00.35.39; Thu, 23 Mar 2023 00:36:02 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b="k25/JmpU"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231148AbjCWH1m (ORCPT + 99 others); Thu, 23 Mar 2023 03:27:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57210 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231127AbjCWH1k (ORCPT ); Thu, 23 Mar 2023 03:27:40 -0400 Received: from mail-pl1-x633.google.com (mail-pl1-x633.google.com [IPv6:2607:f8b0:4864:20::633]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6D8632A6D7; Thu, 23 Mar 2023 00:27:37 -0700 (PDT) Received: by mail-pl1-x633.google.com with SMTP id z19so11111062plo.2; Thu, 23 Mar 2023 00:27:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1679556457; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DHgR8WnUGtyQlzlXJoBF94+5SlpfH7HFwfB03S3iMjg=; b=k25/JmpULurq7a+KwS00111eD3hcJsdFkYd2R+WTM/eDcosEvnl/WTVZX/0pso7TM+ s77HTnChysFAL+H8QdiRZBcn9kmkI3pXVcAEXNveRPsOxAN94d/2FBG1XuhP1mriRDWP ck03f6B9q0AfQums0mckX79XZ+wzKGFxVSZ1QsJA7fKBW9Ujh99Bq+lyLdsJr166H7Df 3o2DpCcfyvA2ZOQQIogObdwIhu4g1b5/xTUN0z8V/ReVJ9BUwHPMkP4K6AyS0vMxr9ic d6MpLz5x47FVM8fG/vbW0zZB5nPCpsMbvoUk2EehRiUXHV988ujCaeYQrggr8q3Aa7R6 Sm7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679556457; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DHgR8WnUGtyQlzlXJoBF94+5SlpfH7HFwfB03S3iMjg=; b=zxbXxnyDR65mVks2BGu5FY5N1nZ9DgsOrkhx0afkbZeeByUqud812187pHfW1bWum9 Kf20nHQHB3DeXXZlkHpYTYFRySRTkbASmmfNpXUIl/feeWxRV6iNncpnNKZqF21nYl5w vOpOvwnP3mPgRTtX9Cqri6Iqba7bAM7ESQRvKlUiNPcdX8b/sIijp93f91IWFm/qmK11 i/J8+aVXW9Oo+HfY87zSBAEG9sWGB3pBGWT3V8RGSYDal2f/bzS2jPOkzVJs2+EDW8X4 2dWYllw8wXyVRVT535yQsbPoRGq+3a2HbiyQCLMqo/kAwTC0M6mzOH3wJHxx2PaiTuM2 jnRw== X-Gm-Message-State: AO0yUKV32cWEwPQuI0e+Irdo6o4frur7p8JI6tJtFifkl5/8JPH4g1mt NbH2LZjZFD6JiYc1NokFPRo= X-Received: by 2002:a17:903:2345:b0:19e:cfbf:f68d with SMTP id c5-20020a170903234500b0019ecfbff68dmr6564770plh.23.1679556456689; Thu, 23 Mar 2023 00:27:36 -0700 (PDT) Received: from localhost.localdomain ([103.7.29.32]) by smtp.gmail.com with ESMTPSA id 13-20020a170902c24d00b0017a032d7ae4sm11645447plg.104.2023.03.23.00.27.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Mar 2023 00:27:36 -0700 (PDT) From: Like Xu X-Google-Original-From: Like Xu To: Sean Christopherson Cc: Paolo Bonzini , Jinrong Liang , linux-kernel@vger.kernel.org, kvm@vger.kernel.org Subject: [PATCH 1/7] KVM: selftests: Test Intel PMU architectural events on gp counters Date: Thu, 23 Mar 2023 15:27:08 +0800 Message-Id: <20230323072714.82289-2-likexu@tencent.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230323072714.82289-1-likexu@tencent.com> References: <20230323072714.82289-1-likexu@tencent.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761143121839920210?= X-GMAIL-MSGID: =?utf-8?q?1761143121839920210?= From: Like Xu Add test cases to check if different Architectural events are available after it's marked as unavailable via CPUID. It covers vPMU event filtering logic based on Intel CPUID, which is a complement to pmu_event_filter. According to Intel SDM, the number of architectural events is reported through CPUID.0AH:EAX[31:24] and the architectural event x is supported if EBX[x]=0 && EAX[31:24]>x. Co-developed-by: Jinrong Liang Signed-off-by: Jinrong Liang Signed-off-by: Like Xu --- tools/testing/selftests/kvm/Makefile | 1 + .../selftests/kvm/x86_64/pmu_cpuid_test.c | 202 ++++++++++++++++++ 2 files changed, 203 insertions(+) create mode 100644 tools/testing/selftests/kvm/x86_64/pmu_cpuid_test.c diff --git a/tools/testing/selftests/kvm/Makefile b/tools/testing/selftests/kvm/Makefile index 84a627c43795..8aa63081b3e6 100644 --- a/tools/testing/selftests/kvm/Makefile +++ b/tools/testing/selftests/kvm/Makefile @@ -78,6 +78,7 @@ TEST_GEN_PROGS_x86_64 += x86_64/mmio_warning_test TEST_GEN_PROGS_x86_64 += x86_64/monitor_mwait_test TEST_GEN_PROGS_x86_64 += x86_64/nested_exceptions_test TEST_GEN_PROGS_x86_64 += x86_64/platform_info_test +TEST_GEN_PROGS_x86_64 += x86_64/pmu_cpuid_test TEST_GEN_PROGS_x86_64 += x86_64/pmu_event_filter_test TEST_GEN_PROGS_x86_64 += x86_64/set_boot_cpu_id TEST_GEN_PROGS_x86_64 += x86_64/set_sregs_test diff --git a/tools/testing/selftests/kvm/x86_64/pmu_cpuid_test.c b/tools/testing/selftests/kvm/x86_64/pmu_cpuid_test.c new file mode 100644 index 000000000000..faab0a91e191 --- /dev/null +++ b/tools/testing/selftests/kvm/x86_64/pmu_cpuid_test.c @@ -0,0 +1,202 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Test the consistency of the PMU's CPUID and its features + * + * Copyright (C) 2023, Tencent, Inc. + * + * Check that the VM's PMU behaviour is consistent with the + * VM CPUID definition. + */ + +#define _GNU_SOURCE /* for program_invocation_short_name */ +#include + +#include "processor.h" + +/* Guest payload for any performance counter counting */ +#define NUM_BRANCHES 10 + +#define EVENTSEL_OS BIT_ULL(17) +#define EVENTSEL_EN BIT_ULL(22) +#define PMU_CAP_FW_WRITES BIT_ULL(13) +#define EVENTS_MASK GENMASK_ULL(7, 0) +#define PMU_VERSION_MASK GENMASK_ULL(7, 0) +#define GP_CTR_NUM_OFS_BIT 8 +#define GP_CTR_NUM_MASK GENMASK_ULL(15, GP_CTR_NUM_OFS_BIT) +#define EVT_LEN_OFS_BIT 24 +#define EVT_LEN_MASK GENMASK_ULL(31, EVT_LEN_OFS_BIT) + +#define ARCH_EVENT(select, umask) (((select) & 0xff) | ((umask) & 0xff) << 8) + +/* + * Intel Pre-defined Architectural Performance Events. Note some events + * are skipped for testing due to difficulties in stable reproduction. + */ +static const uint64_t arch_events[] = { + [0] = ARCH_EVENT(0x3c, 0x0), + [1] = ARCH_EVENT(0xc0, 0x0), + [2] = ARCH_EVENT(0x3c, 0x1), + [3] = ARCH_EVENT(0x2e, 0x4f), /* LLC Reference */ + [4] = ARCH_EVENT(0x2e, 0x41), /* LLC Misses */ + [5] = ARCH_EVENT(0xc4, 0x0), + [6] = ARCH_EVENT(0xc5, 0x0), /* Branch Misses Retired */ + [7] = ARCH_EVENT(0xa4, 0x1), /* Topdown Slots */ +}; + +static struct kvm_vcpu *new_vcpu(void *guest_code) +{ + struct kvm_vm *vm; + struct kvm_vcpu *vcpu; + + vm = vm_create_with_one_vcpu(&vcpu, guest_code); + vm_init_descriptor_tables(vm); + vcpu_init_descriptor_tables(vcpu); + + return vcpu; +} + +static void free_vcpu(struct kvm_vcpu *vcpu) +{ + kvm_vm_free(vcpu->vm); +} + +static void run_vcpu(struct kvm_vcpu *vcpu, const char *msg, + bool (*check_ucall)(struct ucall *uc, void *data), + void *expect_args) +{ + struct ucall uc; + + for (;;) { + vcpu_run(vcpu); + switch (get_ucall(vcpu, &uc)) { + case UCALL_SYNC: + TEST_ASSERT(check_ucall(&uc, expect_args), "%s", msg); + continue; + case UCALL_DONE: + break; + default: + TEST_ASSERT(false, "Unexpected exit: %s", + exit_reason_str(vcpu->run->exit_reason)); + } + break; + } +} + +static bool first_uc_arg_non_zero(struct ucall *uc, void *data) +{ + return uc->args[1]; +} + +static void intel_guest_run_arch_event(uint8_t version, uint8_t max_gp_num, + bool supported, uint32_t ctr_base_msr, + uint64_t evt_code) +{ + uint32_t global_msr = MSR_CORE_PERF_GLOBAL_CTRL; + unsigned int i; + + for (i = 0; i < max_gp_num; i++) { + wrmsr(ctr_base_msr + i, 0); + wrmsr(MSR_P6_EVNTSEL0 + i, EVENTSEL_OS | EVENTSEL_EN | evt_code); + if (version > 1) + wrmsr(global_msr, BIT_ULL(i)); + + __asm__ __volatile__("loop ." : "+c"((int){NUM_BRANCHES})); + + if (version > 1) + wrmsr(global_msr, 0); + + GUEST_SYNC(supported == !!_rdpmc(i)); + } + + GUEST_DONE(); +} + +static void test_arch_events_setup(struct kvm_vcpu *vcpu, uint8_t evt_vector, + uint8_t unavl_mask, uint8_t idx) +{ + struct kvm_cpuid_entry2 *entry; + uint32_t ctr_msr = MSR_IA32_PERFCTR0; + bool is_supported; + + entry = vcpu_get_cpuid_entry(vcpu, 0xa); + entry->eax = (entry->eax & ~EVT_LEN_MASK) | + (evt_vector << EVT_LEN_OFS_BIT); + entry->ebx = (entry->ebx & ~EVENTS_MASK) | unavl_mask; + vcpu_set_cpuid(vcpu); + + if (vcpu_get_msr(vcpu, MSR_IA32_PERF_CAPABILITIES) & PMU_CAP_FW_WRITES) + ctr_msr = MSR_IA32_PMC0; + + /* Arch event x is supported if EBX[x]=0 && EAX[31:24]>x */ + is_supported = !(entry->ebx & BIT_ULL(idx)) && + (((entry->eax & EVT_LEN_MASK) >> EVT_LEN_OFS_BIT) > idx); + + vcpu_args_set(vcpu, 5, entry->eax & PMU_VERSION_MASK, + (entry->eax & GP_CTR_NUM_MASK) >> GP_CTR_NUM_OFS_BIT, + is_supported, ctr_msr, arch_events[idx]); +} + +static void intel_check_arch_event_is_unavl(uint8_t idx) +{ + const char *msg = "Unavailable arch event is counting."; + uint8_t eax_evt_vec, ebx_unavl_mask, i, j; + struct kvm_vcpu *vcpu; + + /* + * A brute force iteration of all combinations of values is likely to + * exhaust the limit of the single-threaded thread fd nums, so it's + * tested here by iterating through all valid values on a single bit. + */ + for (i = 0; i < ARRAY_SIZE(arch_events); i++) { + eax_evt_vec = BIT_ULL(i); + for (j = 0; j < ARRAY_SIZE(arch_events); j++) { + ebx_unavl_mask = BIT_ULL(j); + + vcpu = new_vcpu(intel_guest_run_arch_event); + test_arch_events_setup(vcpu, eax_evt_vec, + ebx_unavl_mask, idx); + run_vcpu(vcpu, msg, first_uc_arg_non_zero, NULL); + free_vcpu(vcpu); + } + } +} + +static void intel_test_arch_events(void) +{ + uint8_t idx; + + for (idx = 0; idx < ARRAY_SIZE(arch_events); idx++) { + /* + * Given the stability of performance event recurrence, + * only these arch events are currently being tested: + * - Core cycle event (idx = 0) + * - Instruction retired event (idx = 1) + * - Reference cycles event (idx = 2) + * - Branch instruction retired event (idx = 5) + */ + if (idx > 2 && idx != 5) + continue; + + intel_check_arch_event_is_unavl(idx); + } +} + +static void intel_test_pmu_cpuid(void) +{ + intel_test_arch_events(); +} + +int main(int argc, char *argv[]) +{ + TEST_REQUIRE(get_kvm_param_bool("enable_pmu")); + + if (host_cpu_is_intel) { + TEST_REQUIRE(kvm_cpu_has_p(X86_PROPERTY_PMU_VERSION)); + TEST_REQUIRE(kvm_cpu_property(X86_PROPERTY_PMU_VERSION) > 0); + TEST_REQUIRE(kvm_cpu_has(X86_FEATURE_PDCM)); + + intel_test_pmu_cpuid(); + } + + return 0; +} From patchwork Thu Mar 23 07:27:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Like Xu X-Patchwork-Id: 73866 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:604a:0:0:0:0:0 with SMTP id j10csp2768836wrt; Thu, 23 Mar 2023 00:32:55 -0700 (PDT) X-Google-Smtp-Source: AK7set//8nhUBjFGwJESzhzekQuI/vkk3Nikyj+tXfhlelLoMK/umZST8vhEHgqhL9YSwYdMWaLI X-Received: by 2002:a17:907:1b0b:b0:93a:6c59:4247 with SMTP id mp11-20020a1709071b0b00b0093a6c594247mr8625450ejc.13.1679556775771; Thu, 23 Mar 2023 00:32:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1679556775; cv=none; d=google.com; s=arc-20160816; b=PSq4V04SAnoechAGMz+aPBFbJrel63FVTItUEwveJSx3Nt7irCBGfYywn0jktKttla QxBmDNLWuEYbTrotbQ4YDKvVwNRYD9z7BFxrRUuoe57sKVO/BPqsjvh1wx8NkgCBP/ug LAfzc8Cgt6NUArTryfo8JJMad36V6WQiHjf9Zejx+wJ6qumCY3CJvK9Zz/xiDaZoziXk NDrKToQKFLYnZmEY/0bmC+G8VGYVx5VDUUMXBn4id4AXG+OUs686uaDtZ/+fb/U9jVVU 45wsktZ1Cc8r2jTQnnsDxRvtAI9pqDc7k+tFaIQrTbssFldxLGGsTD9yETek8HFaqZUb JxIQ== ARC-Message-Signature: i=1; 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Per Intel SDM, PMU users can also count architecture performance events on fixed counters (specifically, FIXED_CTR0 for the retired instructions and FIXED_CTR1 for cpu core cycles event). Therefore, if guest's CPUID indicates that an architecture event is not available, the corresponding fixed counter will also not count that event. Co-developed-by: Like Xu Signed-off-by: Like Xu Signed-off-by: Jinrong Liang --- .../selftests/kvm/x86_64/pmu_cpuid_test.c | 37 +++++++++++++++++-- 1 file changed, 33 insertions(+), 4 deletions(-) diff --git a/tools/testing/selftests/kvm/x86_64/pmu_cpuid_test.c b/tools/testing/selftests/kvm/x86_64/pmu_cpuid_test.c index faab0a91e191..75434aa2a0ec 100644 --- a/tools/testing/selftests/kvm/x86_64/pmu_cpuid_test.c +++ b/tools/testing/selftests/kvm/x86_64/pmu_cpuid_test.c @@ -25,6 +25,9 @@ #define GP_CTR_NUM_MASK GENMASK_ULL(15, GP_CTR_NUM_OFS_BIT) #define EVT_LEN_OFS_BIT 24 #define EVT_LEN_MASK GENMASK_ULL(31, EVT_LEN_OFS_BIT) +#define INTEL_PMC_IDX_FIXED 32 +#define RDPMC_FIXED_BASE BIT_ULL(30) +#define FIXED_CTR_NUM_MASK GENMASK_ULL(4, 0) #define ARCH_EVENT(select, umask) (((select) & 0xff) | ((umask) & 0xff) << 8) @@ -43,6 +46,14 @@ static const uint64_t arch_events[] = { [7] = ARCH_EVENT(0xa4, 0x1), /* Topdown Slots */ }; +/* Association of Fixed Counters with Architectural Performance Events */ +static int fixed_events[] = {1, 0, 7}; + +static uint64_t evt_code_for_fixed_ctr(uint8_t idx) +{ + return arch_events[fixed_events[idx]]; +} + static struct kvm_vcpu *new_vcpu(void *guest_code) { struct kvm_vm *vm; @@ -88,8 +99,8 @@ static bool first_uc_arg_non_zero(struct ucall *uc, void *data) } static void intel_guest_run_arch_event(uint8_t version, uint8_t max_gp_num, - bool supported, uint32_t ctr_base_msr, - uint64_t evt_code) + uint8_t max_fixed_num, bool supported, + uint32_t ctr_base_msr, uint64_t evt_code) { uint32_t global_msr = MSR_CORE_PERF_GLOBAL_CTRL; unsigned int i; @@ -108,6 +119,23 @@ static void intel_guest_run_arch_event(uint8_t version, uint8_t max_gp_num, GUEST_SYNC(supported == !!_rdpmc(i)); } + /* No need to test independent arch events on fixed counters. */ + if (version > 1 && max_fixed_num > 1 && + (evt_code == evt_code_for_fixed_ctr(0) || + evt_code == evt_code_for_fixed_ctr(1))) { + i = (evt_code == evt_code_for_fixed_ctr(0)) ? 0 : 1; + + wrmsr(MSR_CORE_PERF_FIXED_CTR0 + i, 0); + wrmsr(MSR_CORE_PERF_FIXED_CTR_CTRL, BIT_ULL(4 * i)); + wrmsr(global_msr, BIT_ULL(INTEL_PMC_IDX_FIXED + i)); + + __asm__ __volatile__("loop ." : "+c"((int){NUM_BRANCHES})); + + wrmsr(global_msr, 0); + + GUEST_SYNC(supported == !!_rdpmc(RDPMC_FIXED_BASE | i)); + } + GUEST_DONE(); } @@ -131,9 +159,10 @@ static void test_arch_events_setup(struct kvm_vcpu *vcpu, uint8_t evt_vector, is_supported = !(entry->ebx & BIT_ULL(idx)) && (((entry->eax & EVT_LEN_MASK) >> EVT_LEN_OFS_BIT) > idx); - vcpu_args_set(vcpu, 5, entry->eax & PMU_VERSION_MASK, + vcpu_args_set(vcpu, 6, entry->eax & PMU_VERSION_MASK, (entry->eax & GP_CTR_NUM_MASK) >> GP_CTR_NUM_OFS_BIT, - is_supported, ctr_msr, arch_events[idx]); + (entry->edx & FIXED_CTR_NUM_MASK), is_supported, + ctr_msr, arch_events[idx]); } static void intel_check_arch_event_is_unavl(uint8_t idx) From patchwork Thu Mar 23 07:27:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Like Xu X-Patchwork-Id: 73874 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:604a:0:0:0:0:0 with SMTP id j10csp2771972wrt; Thu, 23 Mar 2023 00:43:25 -0700 (PDT) X-Google-Smtp-Source: AK7set+N78cVQNqRjF58mfhOt5ZvY+opQd6knKQQOymZKKg1SnepdEDOkwagkkhG7glJQMDvdCVZ X-Received: by 2002:a17:907:7ba0:b0:93c:847d:a456 with SMTP id ne32-20020a1709077ba000b0093c847da456mr2604290ejc.22.1679557405143; Thu, 23 Mar 2023 00:43:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1679557405; cv=none; d=google.com; s=arc-20160816; b=0bO5HFli6l8sIjBPSUlj9yALXxihWVafgYSM5YVeNZpm7//cXCOvbMxpT3upzasQjs T/m5EUNCRCVdOoR2sKL1bP6V+YcOgH7vn9Dqk9vrD/0JV6rQ/lNu3NFEZhHkJTd+QJyd 0UppPh7NrvxwpW42zID8vM0+1jPYK2yrpG1U7GU3tlK2CRCvLPxmc+iOz9f32YG4qZ/k vpRn0rdwIiSjKqMdIQWMF+4MZkNaHEaardDcZYnLANeIHp2EJLe+NElitKiLmGTU/LK5 o/7Pf7rES5QmVGib/DqhRc66s2Egxu6gSFxQFrz8U60fjAIAR5BvS4oRDBW57UcJ8tRg CFcg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=GQ7Q1+dYjZORNI5EX6aTkzr9RtDccrkdusVCk0aMZNk=; b=TUUvxA8ixWH+p6Q+LdVdLCtUUb4JNc5aGhx0sduL327iiLJ8Fw5Gf9EHodf7HO0LiS FduKXsclKe+BEXs9ChMFYLDDHxs49QTt1hjFLWAhpdkcLjE7dFcJq8//zNcNvmex40mR JlL4j2yQ5d+WAp3sRL9Vd8+/zeK3OBypR2HTGu08l1JIQ5XFKvSNmBIjJBwqlBZj75R5 c1MoLhMyRtD3J5DBMesaRbrS+HD4fo58B6bRioYh2Zupehvhxb0OsYYeLOxrxDVnRX1c KQgjtborQfqo9O62wEYFZeZDFNQTwdPQtXPPOIQ2+I3I74ByyAw2WbcUl8daI4AlyC/j sbLQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=EenW2Hrr; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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When the num of counters is less than 3, KVM does not emulate #GP if a counter isn't present due to compatibility MSR_P6_PERFCTRx handling. Nor will the KVM emulate more counters than it can support. Co-developed-by: Jinrong Liang Signed-off-by: Jinrong Liang Signed-off-by: Like Xu --- .../selftests/kvm/x86_64/pmu_cpuid_test.c | 102 ++++++++++++++++++ 1 file changed, 102 insertions(+) diff --git a/tools/testing/selftests/kvm/x86_64/pmu_cpuid_test.c b/tools/testing/selftests/kvm/x86_64/pmu_cpuid_test.c index 75434aa2a0ec..50902187d2c9 100644 --- a/tools/testing/selftests/kvm/x86_64/pmu_cpuid_test.c +++ b/tools/testing/selftests/kvm/x86_64/pmu_cpuid_test.c @@ -49,11 +49,31 @@ static const uint64_t arch_events[] = { /* Association of Fixed Counters with Architectural Performance Events */ static int fixed_events[] = {1, 0, 7}; +static const uint64_t perf_caps[] = { + 0, + PMU_CAP_FW_WRITES, +}; + +/* + * KVM implements the first two non-existent counters (MSR_P6_PERFCTRx) + * via kvm_pr_unimpl_wrmsr() instead of #GP. It is acceptable here to test + * the third counter as there are usually more than 3 available gp counters. + */ +#define MSR_INTEL_ARCH_PMU_GPCTR (MSR_IA32_PERFCTR0 + 2) + static uint64_t evt_code_for_fixed_ctr(uint8_t idx) { return arch_events[fixed_events[idx]]; } +static uint8_t kvm_gp_ctrs_num(void) +{ + const struct kvm_cpuid_entry2 *kvm_entry; + + kvm_entry = get_cpuid_entry(kvm_get_supported_cpuid(), 0xa, 0); + return (kvm_entry->eax & GP_CTR_NUM_MASK) >> GP_CTR_NUM_OFS_BIT; +} + static struct kvm_vcpu *new_vcpu(void *guest_code) { struct kvm_vm *vm; @@ -98,6 +118,30 @@ static bool first_uc_arg_non_zero(struct ucall *uc, void *data) return uc->args[1]; } +static bool first_uc_arg_equals(struct ucall *uc, void *data) +{ + return uc->args[1] == (uint64_t)data; +} + +static void guest_gp_handler(struct ex_regs *regs) +{ + GUEST_SYNC(GP_VECTOR); + GUEST_DONE(); +} + +static void guest_wr_and_rd_msrs(uint32_t base, uint64_t value, + uint8_t begin, uint8_t offset) +{ + unsigned int i; + + for (i = begin; i < begin + offset; i++) { + wrmsr(base + i, value); + GUEST_SYNC(rdmsr(base + i)); + } + + GUEST_DONE(); +} + static void intel_guest_run_arch_event(uint8_t version, uint8_t max_gp_num, uint8_t max_fixed_num, bool supported, uint32_t ctr_base_msr, uint64_t evt_code) @@ -165,6 +209,27 @@ static void test_arch_events_setup(struct kvm_vcpu *vcpu, uint8_t evt_vector, ctr_msr, arch_events[idx]); } +static void test_oob_gp_counter_setup(struct kvm_vcpu *vcpu, uint8_t eax_gp_num, + uint64_t perf_cap) +{ + struct kvm_cpuid_entry2 *entry; + uint32_t ctr_msr = MSR_IA32_PERFCTR0; + + entry = vcpu_get_cpuid_entry(vcpu, 0xa); + entry->eax = (entry->eax & ~GP_CTR_NUM_MASK) | + (eax_gp_num << GP_CTR_NUM_OFS_BIT); + vcpu_set_cpuid(vcpu); + + if (perf_cap & PMU_CAP_FW_WRITES) + ctr_msr = MSR_IA32_PMC0; + + vcpu_set_msr(vcpu, MSR_IA32_PERF_CAPABILITIES, perf_cap); + vcpu_args_set(vcpu, 4, ctr_msr, 0xffff, + min(eax_gp_num, kvm_gp_ctrs_num()), 1); + + vm_install_exception_handler(vcpu->vm, GP_VECTOR, guest_gp_handler); +} + static void intel_check_arch_event_is_unavl(uint8_t idx) { const char *msg = "Unavailable arch event is counting."; @@ -190,6 +255,42 @@ static void intel_check_arch_event_is_unavl(uint8_t idx) } } +/* Access the first out-of-range counter register to trigger #GP */ +static void test_oob_gp_counter(uint8_t eax_gp_num, uint64_t perf_cap) +{ + const char *msg = "At least one unsupported GP counter is visible."; + struct kvm_vcpu *vcpu; + + vcpu = new_vcpu(guest_wr_and_rd_msrs); + test_oob_gp_counter_setup(vcpu, eax_gp_num, perf_cap); + run_vcpu(vcpu, msg, first_uc_arg_equals, (void *)GP_VECTOR); + free_vcpu(vcpu); +} + +static void intel_test_counters_num(void) +{ + uint8_t kvm_gp_num = kvm_gp_ctrs_num(); + unsigned int i; + + TEST_REQUIRE(kvm_gp_num > 2); + + for (i = 0; i < ARRAY_SIZE(perf_caps); i++) { + /* + * For compatibility reasons, KVM does not emulate #GP + * when MSR_P6_PERFCTR[0|1] is not present, but it doesn't + * affect checking the presence of MSR_IA32_PMCx with #GP. + */ + if (perf_caps[i] & PMU_CAP_FW_WRITES) + test_oob_gp_counter(0, perf_caps[i]); + + test_oob_gp_counter(2, perf_caps[i]); + test_oob_gp_counter(kvm_gp_num, perf_caps[i]); + + /* KVM doesn't emulate more counters than it can support. */ + test_oob_gp_counter(kvm_gp_num + 1, perf_caps[i]); + } +} + static void intel_test_arch_events(void) { uint8_t idx; @@ -213,6 +314,7 @@ static void intel_test_arch_events(void) static void intel_test_pmu_cpuid(void) { intel_test_arch_events(); + intel_test_counters_num(); } int main(int argc, char *argv[]) From patchwork Thu Mar 23 07:27:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Like Xu X-Patchwork-Id: 73871 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:604a:0:0:0:0:0 with SMTP id j10csp2769980wrt; Thu, 23 Mar 2023 00:36:41 -0700 (PDT) X-Google-Smtp-Source: AK7set+uVK7kDpzoE+2P/98aA9zGh9jUkzlfU+xEYo9LzR68gBzNpYbgqndcJe/7BD8S5McidwKw X-Received: by 2002:a17:906:4a0d:b0:88f:a236:69e6 with SMTP id w13-20020a1709064a0d00b0088fa23669e6mr8897478eju.7.1679557001335; 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Per SDM, fixed-function performance counter 'i' is supported if ECX[i] || (EDX[4:0] > i). KVM doesn't emulate more counters than it can support. Co-developed-by: Like Xu Signed-off-by: Like Xu Signed-off-by: Jinrong Liang --- .../selftests/kvm/x86_64/pmu_cpuid_test.c | 68 +++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/tools/testing/selftests/kvm/x86_64/pmu_cpuid_test.c b/tools/testing/selftests/kvm/x86_64/pmu_cpuid_test.c index 50902187d2c9..c934144be287 100644 --- a/tools/testing/selftests/kvm/x86_64/pmu_cpuid_test.c +++ b/tools/testing/selftests/kvm/x86_64/pmu_cpuid_test.c @@ -74,6 +74,22 @@ static uint8_t kvm_gp_ctrs_num(void) return (kvm_entry->eax & GP_CTR_NUM_MASK) >> GP_CTR_NUM_OFS_BIT; } +static uint8_t kvm_fixed_ctrs_num(void) +{ + const struct kvm_cpuid_entry2 *kvm_entry; + + kvm_entry = get_cpuid_entry(kvm_get_supported_cpuid(), 0xa, 0); + return kvm_entry->edx & FIXED_CTR_NUM_MASK; +} + +static uint32_t kvm_fixed_ctrs_bitmask(void) +{ + const struct kvm_cpuid_entry2 *kvm_entry; + + kvm_entry = get_cpuid_entry(kvm_get_supported_cpuid(), 0xa, 0); + return kvm_entry->ecx; +} + static struct kvm_vcpu *new_vcpu(void *guest_code) { struct kvm_vm *vm; @@ -230,6 +246,39 @@ static void test_oob_gp_counter_setup(struct kvm_vcpu *vcpu, uint8_t eax_gp_num, vm_install_exception_handler(vcpu->vm, GP_VECTOR, guest_gp_handler); } +static uint64_t test_oob_fixed_counter_setup(struct kvm_vcpu *vcpu, + uint8_t edx_fix_num, + uint32_t fixed_bitmask) +{ + struct kvm_cpuid_entry2 *entry; + uint32_t ctr_msr = MSR_CORE_PERF_FIXED_CTR0; + uint8_t idx = edx_fix_num; + bool is_supported = true; + uint64_t ret = 0xffffULL; + + entry = vcpu_get_cpuid_entry(vcpu, 0xa); + entry->ecx = fixed_bitmask; + entry->edx = (entry->edx & ~FIXED_CTR_NUM_MASK) | edx_fix_num; + vcpu_set_cpuid(vcpu); + + /* Per Intel SDM, FixCtr[i]_is_supported := ECX[i] || (EDX[4:0] > i). */ + is_supported = (entry->ecx & BIT_ULL(idx) || + ((entry->edx & FIXED_CTR_NUM_MASK) > idx)); + + /* KVM doesn't emulate more fixed counters than it can support. */ + if (idx >= kvm_fixed_ctrs_num()) + is_supported = false; + + if (!is_supported) { + vm_install_exception_handler(vcpu->vm, GP_VECTOR, guest_gp_handler); + ret = GP_VECTOR; + } + + vcpu_args_set(vcpu, 4, ctr_msr, ret, idx, 1); + + return ret; +} + static void intel_check_arch_event_is_unavl(uint8_t idx) { const char *msg = "Unavailable arch event is counting."; @@ -267,10 +316,23 @@ static void test_oob_gp_counter(uint8_t eax_gp_num, uint64_t perf_cap) free_vcpu(vcpu); } +static void intel_test_oob_fixed_ctr(uint8_t edx_fix_num, uint32_t fixed_bitmask) +{ + const char *msg = "At least one unsupported Fixed counter is visible."; + struct kvm_vcpu *vcpu; + uint64_t ret; + + vcpu = new_vcpu(guest_wr_and_rd_msrs); + ret = test_oob_fixed_counter_setup(vcpu, edx_fix_num, fixed_bitmask); + run_vcpu(vcpu, msg, first_uc_arg_equals, (void *)ret); + free_vcpu(vcpu); +} + static void intel_test_counters_num(void) { uint8_t kvm_gp_num = kvm_gp_ctrs_num(); unsigned int i; + uint32_t ecx; TEST_REQUIRE(kvm_gp_num > 2); @@ -289,6 +351,12 @@ static void intel_test_counters_num(void) /* KVM doesn't emulate more counters than it can support. */ test_oob_gp_counter(kvm_gp_num + 1, perf_caps[i]); } + + for (ecx = 0; ecx <= kvm_fixed_ctrs_bitmask() + 1; ecx++) { + intel_test_oob_fixed_ctr(0, ecx); + intel_test_oob_fixed_ctr(kvm_fixed_ctrs_num(), ecx); + intel_test_oob_fixed_ctr(kvm_fixed_ctrs_num() + 1, ecx); + } } static void intel_test_arch_events(void) From patchwork Thu Mar 23 07:27:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Like Xu X-Patchwork-Id: 73872 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:604a:0:0:0:0:0 with SMTP id j10csp2770008wrt; Thu, 23 Mar 2023 00:36:48 -0700 (PDT) X-Google-Smtp-Source: AK7set9ewf7o1KxZ0JrRCjuBJg6kJmzTdXFRBurmPTrlkCrfU8T/4sR3O7aK+npD7PwzST9TxNxX X-Received: by 2002:a17:903:2301:b0:1a1:dfd6:b0ef with SMTP id d1-20020a170903230100b001a1dfd6b0efmr6838408plh.61.1679557008179; Thu, 23 Mar 2023 00:36:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1679557008; cv=none; d=google.com; s=arc-20160816; b=gRdUXNtVDFbkxMK/gIJElnPlMHljMNIRG9M3ukb8xcnhI98pG37+96W8Du7w2Gs6iZ 4dR6UweqBHX2gl98s3dO5WmaBOtxPLM1swOlGHwXWab0G97ctLfSLSPrgK4Jm5oSXapk 8ZV9nHbEGDKodESUyhAu2QBVRjjhZEBesJ0KUtErG43E1e6uFQuyfjUk+/pUsPgl415c B9lVugcr75xBDsRNxWImuj1/VIJbu1P4o1s8RLCZpo3xfH+CejYM7SB5J6DxIiYSIyHR NnQg96jZ/3wxb6Wpux6tNkEPqbcO8GETQCFu8848nf2aL4B7mz7K3ivVrKe12yuy7XER MGOw== ARC-Message-Signature: i=1; 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Signed-off-by: Like Xu --- .../selftests/kvm/x86_64/pmu_cpuid_test.c | 63 +++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/tools/testing/selftests/kvm/x86_64/pmu_cpuid_test.c b/tools/testing/selftests/kvm/x86_64/pmu_cpuid_test.c index c934144be287..79f2e144c6c6 100644 --- a/tools/testing/selftests/kvm/x86_64/pmu_cpuid_test.c +++ b/tools/testing/selftests/kvm/x86_64/pmu_cpuid_test.c @@ -199,6 +199,27 @@ static void intel_guest_run_arch_event(uint8_t version, uint8_t max_gp_num, GUEST_DONE(); } +static void intel_guest_run_fixed_counters(uint64_t supported_bitmask, + uint8_t max_fixed_num) +{ + unsigned int i; + + for (i = 0; i < max_fixed_num; i++) { + if (!(supported_bitmask & BIT_ULL(i))) + continue; + + wrmsr(MSR_CORE_PERF_FIXED_CTR0 + i, 0); + wrmsr(MSR_CORE_PERF_FIXED_CTR_CTRL, BIT_ULL(4 * i)); + wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, BIT_ULL(INTEL_PMC_IDX_FIXED + i)); + __asm__ __volatile__("loop ." : "+c"((int){NUM_BRANCHES})); + wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, 0); + + GUEST_SYNC(!!_rdpmc(RDPMC_FIXED_BASE | i)); + } + + GUEST_DONE(); +} + static void test_arch_events_setup(struct kvm_vcpu *vcpu, uint8_t evt_vector, uint8_t unavl_mask, uint8_t idx) { @@ -279,6 +300,47 @@ static uint64_t test_oob_fixed_counter_setup(struct kvm_vcpu *vcpu, return ret; } +static void test_fixed_counters_setup(struct kvm_vcpu *vcpu, uint8_t edx_fix_num, + uint32_t fixed_bitmask) +{ + struct kvm_cpuid_entry2 *entry; + uint8_t max_fixed_num = kvm_fixed_ctrs_num(); + uint64_t supported_bitmask = 0; + unsigned int i; + + entry = vcpu_get_cpuid_entry(vcpu, 0xa); + entry->ecx = fixed_bitmask; + entry->edx = (entry->edx & ~FIXED_CTR_NUM_MASK) | edx_fix_num; + vcpu_set_cpuid(vcpu); + + for (i = 0; i < max_fixed_num; i++) { + if (entry->ecx & BIT_ULL(i) || + ((entry->edx & FIXED_CTR_NUM_MASK) > i)) + supported_bitmask |= BIT_ULL(i); + } + + vcpu_args_set(vcpu, 2, supported_bitmask, max_fixed_num); + vm_install_exception_handler(vcpu->vm, GP_VECTOR, guest_gp_handler); +} + +static void intel_test_fixed_counters(void) +{ + const char *msg = "At least one fixed counter is not working as expected"; + uint8_t edx, num = kvm_fixed_ctrs_num(); + struct kvm_vcpu *vcpu; + uint32_t ecx; + + for (edx = 0; edx <= num; edx++) { + /* KVM doesn't emulate more fixed counters than it can support. */ + for (ecx = 0; ecx <= (BIT_ULL(num) - 1); ecx++) { + vcpu = new_vcpu(intel_guest_run_fixed_counters); + test_fixed_counters_setup(vcpu, edx, ecx); + run_vcpu(vcpu, msg, first_uc_arg_equals, (void *)true); + free_vcpu(vcpu); + } + } +} + static void intel_check_arch_event_is_unavl(uint8_t idx) { const char *msg = "Unavailable arch event is counting."; @@ -383,6 +445,7 @@ static void intel_test_pmu_cpuid(void) { intel_test_arch_events(); intel_test_counters_num(); + intel_test_fixed_counters(); } int main(int argc, char *argv[]) From patchwork Thu Mar 23 07:27:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Like Xu X-Patchwork-Id: 73867 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:604a:0:0:0:0:0 with SMTP id j10csp2768949wrt; Thu, 23 Mar 2023 00:33:15 -0700 (PDT) X-Google-Smtp-Source: AK7set9ZUrxnOSpWKCOLuVNUn6Edxy2ca3rzuNQfsUklt7H76vQo1e+0Mx1s7lI6LGGOcr1NoC5e X-Received: by 2002:a17:906:694b:b0:878:7cf3:a9e7 with SMTP id c11-20020a170906694b00b008787cf3a9e7mr9956609ejs.65.1679556795135; Thu, 23 Mar 2023 00:33:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1679556795; cv=none; d=google.com; s=arc-20160816; b=jJQCVjY2zvtzsA9v2ymqPFKFJThivKsi3D6sux+s9R6oqCcyW8DFdkwU4D7yErzonR kuXjCfLTeujxzxrLJaJQAGGW/tSXT+pndWMD1JyPMbHHVPiBtPUljvugqHNnPO7b9JrX IY6yd/sGRKTZynLtLyRgHg/GLWtZ/uNd+uViVQ3xWG/Gfyk9A91HgyGCfj2hFnyaTbJm 8CoBz6HbtQVweIfoCqdo8hFf82n9M10xAhj5D5ap9cJtywTMo6/scj/TCglb5roY8vhg HPAQBcCdQ8Dy66C6lDe5MuSPCMnv3JAoRRC7HO8hW13XRBI7KbOOsBhW/Hz+TGkqwZyE teDg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=PaVBTRG8cSbZezD1tCmSqI5sDhrh3YVPGLoSBE21PFI=; b=cBVKMozetR5iPlLCiZQcb2T2UbPytDPpL3mzyNdbayByaPaaKO6HJYXs72UrSKo9Ca 2SYgf1zsK5vncjoOLEGF2eR3E1Z7NNIUM5MsB52KDXXl17pi0A9giE5tigoCmbj6yYsp jK552dp1rqqVgHkJaNWubgbxoz8gRYZU2YjKBleVnb8Jxme9bJbFGvBgE9ZYi16Ckvy/ a8s6oAFuZdxD7hX0EnPlrcDfQ77BfVdMFIh0jZSAb3XwKnt3rOStXnOsXyaO205YjTHc 7GVkFFSJM7MHyBDSpQX/XKGDbHhkJFfm3oVm6rLuP6Cr9f2hTpsTbkBemsZZEG05IVKe /PhQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=JGFiy5fE; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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A test is added to check if a typical PMU register that is not available at the current version number is leaking. Co-developed-by: Like Xu Signed-off-by: Like Xu Signed-off-by: Jinrong Liang --- .../selftests/kvm/x86_64/pmu_cpuid_test.c | 57 +++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/tools/testing/selftests/kvm/x86_64/pmu_cpuid_test.c b/tools/testing/selftests/kvm/x86_64/pmu_cpuid_test.c index 79f2e144c6c6..caf0d98079c7 100644 --- a/tools/testing/selftests/kvm/x86_64/pmu_cpuid_test.c +++ b/tools/testing/selftests/kvm/x86_64/pmu_cpuid_test.c @@ -17,6 +17,7 @@ #define NUM_BRANCHES 10 #define EVENTSEL_OS BIT_ULL(17) +#define EVENTSEL_ANY BIT_ULL(21) #define EVENTSEL_EN BIT_ULL(22) #define PMU_CAP_FW_WRITES BIT_ULL(13) #define EVENTS_MASK GENMASK_ULL(7, 0) @@ -90,6 +91,14 @@ static uint32_t kvm_fixed_ctrs_bitmask(void) return kvm_entry->ecx; } +static uint32_t kvm_max_pmu_version(void) +{ + const struct kvm_cpuid_entry2 *kvm_entry; + + kvm_entry = get_cpuid_entry(kvm_get_supported_cpuid(), 0xa, 0); + return kvm_entry->eax & PMU_VERSION_MASK; +} + static struct kvm_vcpu *new_vcpu(void *guest_code) { struct kvm_vm *vm; @@ -220,6 +229,25 @@ static void intel_guest_run_fixed_counters(uint64_t supported_bitmask, GUEST_DONE(); } +static void intel_guest_check_pmu_version(uint8_t version) +{ + switch (version) { + case 0: + wrmsr(MSR_INTEL_ARCH_PMU_GPCTR, 0xffffull); + case 1: + wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, 0x1ull); + case 2: + /* AnyThread Bit is only supported in version 3 */ + wrmsr(MSR_P6_EVNTSEL0, EVENTSEL_ANY); + break; + default: + /* KVM currently supports up to pmu version 2 */ + GUEST_SYNC(GP_VECTOR); + } + + GUEST_DONE(); +} + static void test_arch_events_setup(struct kvm_vcpu *vcpu, uint8_t evt_vector, uint8_t unavl_mask, uint8_t idx) { @@ -341,6 +369,18 @@ static void intel_test_fixed_counters(void) } } +static void test_pmu_version_setup(struct kvm_vcpu *vcpu, uint8_t version) +{ + struct kvm_cpuid_entry2 *entry; + + entry = vcpu_get_cpuid_entry(vcpu, 0xa); + entry->eax = (entry->eax & ~PMU_VERSION_MASK) | version; + vcpu_set_cpuid(vcpu); + + vcpu_args_set(vcpu, 1, version); + vm_install_exception_handler(vcpu->vm, GP_VECTOR, guest_gp_handler); +} + static void intel_check_arch_event_is_unavl(uint8_t idx) { const char *msg = "Unavailable arch event is counting."; @@ -441,11 +481,28 @@ static void intel_test_arch_events(void) } } +static void intel_test_pmu_version(void) +{ + const char *msg = "Something beyond this PMU version is leaked."; + uint8_t version, unsupported_version = kvm_max_pmu_version() + 1; + struct kvm_vcpu *vcpu; + + TEST_REQUIRE(kvm_gp_ctrs_num() > 2); + + for (version = 0; version <= unsupported_version; version++) { + vcpu = new_vcpu(intel_guest_check_pmu_version); + test_pmu_version_setup(vcpu, version); + run_vcpu(vcpu, msg, first_uc_arg_equals, (void *)GP_VECTOR); + free_vcpu(vcpu); + } +} + static void intel_test_pmu_cpuid(void) { intel_test_arch_events(); intel_test_counters_num(); intel_test_fixed_counters(); + intel_test_pmu_version(); } int main(int argc, char *argv[]) From patchwork Thu Mar 23 07:27:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Like Xu X-Patchwork-Id: 73880 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:604a:0:0:0:0:0 with SMTP id j10csp2774341wrt; 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When the VM has FW_WRITES bit, the bitwidth of the gp and fixed counters will be specified by the CPUID (no less than 32 bits and no greater than the host bitwidth) and accessing bits that are not within the bitwidth will generate #GP. However, when it does not have FW_WRITES bit, only the low 32-bits signed data will be in effect and naturally #GP will not be generated. Co-developed-by: Jinrong Liang Signed-off-by: Jinrong Liang Signed-off-by: Like Xu --- .../selftests/kvm/x86_64/pmu_cpuid_test.c | 105 ++++++++++++++++++ 1 file changed, 105 insertions(+) diff --git a/tools/testing/selftests/kvm/x86_64/pmu_cpuid_test.c b/tools/testing/selftests/kvm/x86_64/pmu_cpuid_test.c index caf0d98079c7..e7465b01178a 100644 --- a/tools/testing/selftests/kvm/x86_64/pmu_cpuid_test.c +++ b/tools/testing/selftests/kvm/x86_64/pmu_cpuid_test.c @@ -29,6 +29,10 @@ #define INTEL_PMC_IDX_FIXED 32 #define RDPMC_FIXED_BASE BIT_ULL(30) #define FIXED_CTR_NUM_MASK GENMASK_ULL(4, 0) +#define GP_WIDTH_OFS_BIT 16 +#define GP_WIDTH_MASK GENMASK_ULL(23, GP_WIDTH_OFS_BIT) +#define FIXED_WIDTH_OFS_BIT 5 +#define FIXED_WIDTH_MASK GENMASK_ULL(12, FIXED_WIDTH_OFS_BIT) #define ARCH_EVENT(select, umask) (((select) & 0xff) | ((umask) & 0xff) << 8) @@ -62,6 +66,16 @@ static const uint64_t perf_caps[] = { */ #define MSR_INTEL_ARCH_PMU_GPCTR (MSR_IA32_PERFCTR0 + 2) +static const uint32_t msr_bases[] = { + MSR_INTEL_ARCH_PMU_GPCTR, + MSR_IA32_PMC0, + MSR_CORE_PERF_FIXED_CTR0, +}; + +static const uint64_t bit_widths[] = { + 0, 1, 31, 32, 47, 48, 63, 64, +}; + static uint64_t evt_code_for_fixed_ctr(uint8_t idx) { return arch_events[fixed_events[idx]]; @@ -99,6 +113,22 @@ static uint32_t kvm_max_pmu_version(void) return kvm_entry->eax & PMU_VERSION_MASK; } +static uint32_t kvm_gp_ctr_bit_width(void) +{ + const struct kvm_cpuid_entry2 *kvm_entry; + + kvm_entry = get_cpuid_entry(kvm_get_supported_cpuid(), 0xa, 0); + return (kvm_entry->eax & GP_WIDTH_MASK) >> GP_WIDTH_OFS_BIT; +} + +static uint32_t kvm_fixed_ctr_bit_width(void) +{ + const struct kvm_cpuid_entry2 *kvm_entry; + + kvm_entry = get_cpuid_entry(kvm_get_supported_cpuid(), 0xa, 0); + return (kvm_entry->edx & FIXED_WIDTH_MASK) >> FIXED_WIDTH_OFS_BIT; +} + static struct kvm_vcpu *new_vcpu(void *guest_code) { struct kvm_vm *vm; @@ -381,6 +411,50 @@ static void test_pmu_version_setup(struct kvm_vcpu *vcpu, uint8_t version) vm_install_exception_handler(vcpu->vm, GP_VECTOR, guest_gp_handler); } +static uint64_t test_ctrs_bit_width_setup(struct kvm_vcpu *vcpu, + uint8_t bit_width, + uint64_t perf_cap, + uint32_t msr_base) +{ + struct kvm_cpuid_entry2 *entry; + bool fw_wr = perf_cap & PMU_CAP_FW_WRITES; + uint64_t kvm_width; + uint64_t value; + + entry = vcpu_get_cpuid_entry(vcpu, 0xa); + if (msr_base != MSR_CORE_PERF_FIXED_CTR0) { + kvm_width = kvm_gp_ctr_bit_width(); + entry->eax = (entry->eax & ~GP_WIDTH_MASK) | + (bit_width << GP_WIDTH_OFS_BIT); + } else { + kvm_width = kvm_fixed_ctr_bit_width(); + entry->edx = (entry->edx & ~FIXED_WIDTH_MASK) | + (bit_width << FIXED_WIDTH_OFS_BIT); + } + TEST_REQUIRE(kvm_width > 31); + + vcpu_set_cpuid(vcpu); + vcpu_set_msr(vcpu, MSR_IA32_PERF_CAPABILITIES, perf_cap); + + /* No less than 32 bits and no greater than the host bitwidth */ + bit_width = fw_wr ? max_t(int, 32, bit_width) : 32; + bit_width = min_t(int, bit_width, kvm_width); + + /* Unconditionally set signed bit 31 for the case w/o FW_WRITES */ + value = BIT_ULL(bit_width) | 0x1234567ull | BIT_ULL(31); + vcpu_args_set(vcpu, 4, msr_base, value, 1, 1); + + if (fw_wr && msr_base != MSR_INTEL_ARCH_PMU_GPCTR) { + vm_install_exception_handler(vcpu->vm, GP_VECTOR, + guest_gp_handler); + return GP_VECTOR; + } else if (msr_base == MSR_INTEL_ARCH_PMU_GPCTR) { + value = (s32)(value & (BIT_ULL(32) - 1)); + } + + return value & (BIT_ULL(bit_width) - 1); +} + static void intel_check_arch_event_is_unavl(uint8_t idx) { const char *msg = "Unavailable arch event is counting."; @@ -497,12 +571,43 @@ static void intel_test_pmu_version(void) } } +static void vcpu_run_bit_width(uint8_t bit_width, uint64_t perf_cap, + uint32_t msr_base) +{ + const char *msg = "Fail to emulate counters' bit width."; + struct kvm_vcpu *vcpu; + uint64_t ret; + + vcpu = new_vcpu(guest_wr_and_rd_msrs); + ret = test_ctrs_bit_width_setup(vcpu, bit_width, perf_cap, msr_base); + run_vcpu(vcpu, msg, first_uc_arg_equals, (void *)ret); + free_vcpu(vcpu); +} + +static void intel_test_counters_bit_width(void) +{ + uint8_t i, j, k; + + for (i = 0; i < ARRAY_SIZE(perf_caps); i++) { + for (j = 0; j < ARRAY_SIZE(msr_bases); j++) { + if (!(perf_caps[i] & PMU_CAP_FW_WRITES) && + msr_bases[j] == MSR_IA32_PMC0) + continue; + + for (k = 0; k < ARRAY_SIZE(bit_widths); k++) + vcpu_run_bit_width(bit_widths[k], perf_caps[i], + msr_bases[j]); + } + } +} + static void intel_test_pmu_cpuid(void) { intel_test_arch_events(); intel_test_counters_num(); intel_test_fixed_counters(); intel_test_pmu_version(); + intel_test_counters_bit_width(); } int main(int argc, char *argv[])