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[2620:137:e000::1:20]) by mx.google.com with ESMTP id ge3-20020a17090b0e0300b002115bc4b5casi1556587pjb.86.2022.10.19.23.41.14; Wed, 19 Oct 2022 23:41:39 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230161AbiJTGgk (ORCPT + 99 others); Thu, 20 Oct 2022 02:36:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48288 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229752AbiJTGgh (ORCPT ); Thu, 20 Oct 2022 02:36:37 -0400 Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 1D0F418C414; Wed, 19 Oct 2022 23:36:33 -0700 (PDT) Received: from loongson.cn (unknown [10.180.13.64]) by gateway (Coremail) with SMTP id _____8Axbdpw7FBjpvUAAA--.5001S3; Thu, 20 Oct 2022 14:36:32 +0800 (CST) Received: from localhost.localdomain (unknown [10.180.13.64]) by localhost.localdomain (Coremail) with SMTP id AQAAf8Axf+Bq7FBjccEBAA--.7362S2; Thu, 20 Oct 2022 14:36:31 +0800 (CST) From: Yinbo Zhu To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Huacai Chen , WANG Xuerui , Jiaxun Yang , Jianmin Lv , Yang Li , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, Yinbo Zhu Cc: Krzysztof Kozlowski Subject: [PATCH v3 1/3] dt-bindings: clock: add loongson2 clock include file Date: Thu, 20 Oct 2022 14:36:22 +0800 Message-Id: <20221020063624.17548-1-zhuyinbo@loongson.cn> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-CM-TRANSID: AQAAf8Axf+Bq7FBjccEBAA--.7362S2 X-CM-SenderInfo: 52kx5xhqerqz5rrqw2lrqou0/ X-Coremail-Antispam: 1Uk129KBjvJXoW7AF4UWr1kJr1Dtry3Cr18Grg_yoW8Kr4fpr 4kCFWfKry2yF4IkwsYgFy3Kr13uw4xG3W7AF47uF1jvF17Jw18JwnF9F1fAa9IqrWkGFWx Zan7Cw409a9rX3DanT9S1TB71UUUUj7qnTZGkaVYY2UrUUUUj1kv1TuYvTs0mT0YCTnIWj qI5I8CrVACY4xI64kE6c02F40Ex7xfYxn0WfASr-VFAUDa7-sFnT9fnUUIcSsGvfJTRUUU bfAFc2x0x2IEx4CE42xK8VAvwI8IcIk0rVWrJVCq3wAFIxvE14AKwVWUXVWUAwA2ocxC64 kIII0Yj41l84x0c7CEw4AK67xGY2AK021l84ACjcxK6xIIjxv20xvE14v26ryj6F1UM28E F7xvwVC0I7IYx2IY6xkF7I0E14v26F4j6r4UJwA2z4x0Y4vEx4A2jsIE14v26r4UJVWxJr 1l84ACjcxK6I8E87Iv6xkF7I0E14v26r4UJVWxJr1ln4kS14v26r126r1DM2AIxVAIcxkE cVAq07x20xvEncxIr21l57IF6xkI12xvs2x26I8E6xACxx1l5I8CrVACY4xI64kE6c02F4 0Ex7xfMcIj6xIIjxv20xvE14v26r126r1DMcIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC 6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41lc7CjxVAaw2AFwI0_JF0_Jw1l42xK82IYc2 Ij64vIr41l42xK82IY6x8ErcxFaVAv8VWrMxC20s026xCaFVCjc4AY6r1j6r4UMxCIbckI 1I0E14v26r126r1DMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_Jr Wlx4CE17CEb7AF67AKxVWUtVW8ZwCIc40Y0x0EwIxGrwCI42IY6xIIjxv20xvE14v26r1I 6r4UMIIF0xvE2Ix0cI8IcVCY1x0267AKxVW8JVWxJwCI42IY6xAIw20EY4v20xvaj40_Jr 0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aVCY1x0267AKxVW8JVW8JrUv cSsGvfC2KfnxnUUI43ZEXa7IU8FAp5UUUUU== X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_PASS, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747187767078195620?= X-GMAIL-MSGID: =?utf-8?q?1747187767078195620?= This file defines all loongson2 soc clock indexes, it should be included in the device tree in which there's device using the clocks. Signed-off-by: Yinbo Zhu Acked-by: Krzysztof Kozlowski --- Change in v3: 1. Add the review information. MAINTAINERS | 6 ++++ include/dt-bindings/clock/loongson,ls2k-clk.h | 29 +++++++++++++++++++ 2 files changed, 35 insertions(+) create mode 100644 include/dt-bindings/clock/loongson,ls2k-clk.h diff --git a/MAINTAINERS b/MAINTAINERS index 0be0f520c032..b6aae412de9c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11907,6 +11907,12 @@ S: Maintained F: Documentation/devicetree/bindings/thermal/loongson,ls2k-thermal.yaml F: drivers/thermal/loongson2_thermal.c +LOONGSON2 SOC SERIES CLOCK DRIVER +M: Yinbo Zhu +L: linux-clk@vger.kernel.org +S: Maintained +F: include/dt-bindings/clock/loongson,ls2k-clk.h + LSILOGIC MPT FUSION DRIVERS (FC/SAS/SPI) M: Sathya Prakash M: Sreekanth Reddy diff --git a/include/dt-bindings/clock/loongson,ls2k-clk.h b/include/dt-bindings/clock/loongson,ls2k-clk.h new file mode 100644 index 000000000000..db1e27e792ff --- /dev/null +++ b/include/dt-bindings/clock/loongson,ls2k-clk.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Author: Yinbo Zhu + * Copyright (C) 2022-2023 Loongson Technology Corporation Limited + */ + +#ifndef __DT_BINDINGS_CLOCK_LOONGSON2_H +#define __DT_BINDINGS_CLOCK_LOONGSON2_H + +#define LOONGSON2_REF_100M 0 +#define LOONGSON2_NODE_PLL 1 +#define LOONGSON2_DDR_PLL 2 +#define LOONGSON2_DC_PLL 3 +#define LOONGSON2_PIX0_PLL 4 +#define LOONGSON2_PIX1_PLL 5 +#define LOONGSON2_NODE_CLK 6 +#define LOONGSON2_HDA_CLK 7 +#define LOONGSON2_GPU_CLK 8 +#define LOONGSON2_DDR_CLK 9 +#define LOONGSON2_GMAC_CLK 10 +#define LOONGSON2_DC_CLK 11 +#define LOONGSON2_APB_CLK 12 +#define LOONGSON2_USB_CLK 13 +#define LOONGSON2_SATA_CLK 14 +#define LOONGSON2_PIX0_CLK 15 +#define LOONGSON2_PIX1_CLK 16 +#define LOONGSON2_CLK_END 17 + +#endif From patchwork Thu Oct 20 06:36:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yinbo Zhu X-Patchwork-Id: 5978 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp96333wrs; Wed, 19 Oct 2022 23:40:21 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6ChpMYx8H3pE4Mk01QqSnQaJsZglbE1hyvlhXSJmHJVN1dcSz0SsA9q1zO1Y8H7bBIB/ik X-Received: by 2002:a05:6a00:24d2:b0:567:3c7d:d888 with SMTP id d18-20020a056a0024d200b005673c7dd888mr12307064pfv.33.1666248020796; Wed, 19 Oct 2022 23:40:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666248020; cv=none; d=google.com; s=arc-20160816; b=kxxLFknR3p6XrWv62NtSuCfTXdFmhq8o/tHRgJRqLIQB3BUrfZzqkCpUZmazZtA12H dgaj9cjTQn6L0g6FjAcmMaOgylU5Le0AczltNjYgBOflQbxdUzUxziM2+u5ZgiT3awUp fiPTsTkNy4akDcdflw8T6H+PMeY0HBNK9B9j92XBAOdIXsmnPDWU6WhLMwej4pKktSdK HXsCcXsYaVB/HkYf5TdcCtsNTdPK2n0wwPpISubjT7jDLhD0mjwbtVHGmPbJcu1iykdy QriQIqe0Wk2xTxgKrpwiiyzuuz5W6zNvKZPGMRe/+B+oSH2q3Gut5Y4X4EocspZSWOQn Gtsw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:to:from; bh=/9cXyLQRUhuyz+rzkQ1Obc2RkufJPbrwgxiQ4rgyaJA=; b=MPQoSIJfB668HZ9lFYeBQ/ghmjAVO34v4AVSXXXbXEtei8i3/ApAGQUgXJa5UuR0pZ woikCJeLp7wy8CgvuNMgkRFFwVzATDuSX2ItIEwpHpfNaYiEUYY9JmDeGN22ZS5N8c1x yH1F/kvryQ8CyJVa2798UrfBtyKc+oK92k5iQ3dDzosKd7JEjyGUrnCTDlK59p0iSh+M senf11mAMaRbzT58v8JPYJug9aX/VqECM4qXY5LqtDhwAT24iLApqAgJ672XEU9DsW0S o8uaylzg5BTrXnFeidZnxz6zs/way4JKh+VEWbuk0NL8f0B7YzeTV6RkGwzp2jOOITel 50Cg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id ja12-20020a170902efcc00b0016ce3d67e7csi2302071plb.387.2022.10.19.23.40.04; Wed, 19 Oct 2022 23:40:20 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229974AbiJTGgr (ORCPT + 99 others); Thu, 20 Oct 2022 02:36:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48294 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229868AbiJTGgh (ORCPT ); Thu, 20 Oct 2022 02:36:37 -0400 Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 8226018C423; Wed, 19 Oct 2022 23:36:34 -0700 (PDT) Received: from loongson.cn (unknown [10.180.13.64]) by gateway (Coremail) with SMTP id _____8CxKdhx7FBjrvUAAA--.2964S3; Thu, 20 Oct 2022 14:36:33 +0800 (CST) Received: from localhost.localdomain (unknown [10.180.13.64]) by localhost.localdomain (Coremail) with SMTP id AQAAf8Axf+Bq7FBjccEBAA--.7362S3; Thu, 20 Oct 2022 14:36:32 +0800 (CST) From: Yinbo Zhu To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Huacai Chen , WANG Xuerui , Jiaxun Yang , Jianmin Lv , Yang Li , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, Yinbo Zhu Subject: [PATCH v3 2/3] clk: clk-loongson2: add clock controller driver support Date: Thu, 20 Oct 2022 14:36:23 +0800 Message-Id: <20221020063624.17548-2-zhuyinbo@loongson.cn> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20221020063624.17548-1-zhuyinbo@loongson.cn> References: <20221020063624.17548-1-zhuyinbo@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf8Axf+Bq7FBjccEBAA--.7362S3 X-CM-SenderInfo: 52kx5xhqerqz5rrqw2lrqou0/ X-Coremail-Antispam: 1Uk129KBjvJXoW3CFy8Gr47GryDCFWUGw1rZwb_yoWkWr18pF yfAay5WrWjqF4UuwsxtryDGrn8AasFk3W7AFW3Ga4qkrZ7Xa4rWrs7AFyxZF4UAaykAFW2 vFZagrWUCFs8XwUanT9S1TB71UUUUjDqnTZGkaVYY2UrUUUUj1kv1TuYvTs0mT0YCTnIWj qI5I8CrVACY4xI64kE6c02F40Ex7xfYxn0WfASr-VFAUDa7-sFnT9fnUUIcSsGvfJTRUUU bfAFc2x0x2IEx4CE42xK8VAvwI8IcIk0rVWrJVCq3wAFIxvE14AKwVWUXVWUAwA2ocxC64 kIII0Yj41l84x0c7CEw4AK67xGY2AK021l84ACjcxK6xIIjxv20xvE14v26ryj6F1UM28E F7xvwVC0I7IYx2IY6xkF7I0E14v26F4j6r4UJwA2z4x0Y4vEx4A2jsIE14v26r4UJVWxJr 1l84ACjcxK6I8E87Iv6xkF7I0E14v26r4UJVWxJr1ln4kS14v26r126r1DM2AIxVAIcxkE cVAq07x20xvEncxIr21l57IF6xkI12xvs2x26I8E6xACxx1l5I8CrVACY4xI64kE6c02F4 0Ex7xfMcIj6xIIjxv20xvE14v26r1q6rW5McIj6I8E87Iv67AKxVW8JVWxJwAm72CE4IkC 6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41lc7CjxVAaw2AFwI0_JF0_Jw1l42xK82IYc2 Ij64vIr41l42xK82IY6x8ErcxFaVAv8VWrMxC20s026xCaFVCjc4AY6r1j6r4UMxCIbckI 1I0E14v26r126r1DMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_Jr Wlx4CE17CEb7AF67AKxVWUtVW8ZwCIc40Y0x0EwIxGrwCI42IY6xIIjxv20xvE14v26r4j 6ryUMIIF0xvE2Ix0cI8IcVCY1x0267AKxVW8JVWxJwCI42IY6xAIw20EY4v20xvaj40_Jr 0_JF4lIxAIcVC2z280aVAFwI0_Gr0_Cr1lIxAIcVC2z280aVCY1x0267AKxVW8JVW8JrUv cSsGvfC2KfnxnUUI43ZEXa7IU8mQ6JUUUUU== X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_PASS, SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747187684546025471?= X-GMAIL-MSGID: =?utf-8?q?1747187684546025471?= This driver provides support for clock controller on Loongson2 SoC , the Loongson2 SoC uses a 100MHz clock as the PLL reference clock , there are five independent PLLs inside, each of which PLL can provide up to three sets of frequency dependent clock outputs. Signed-off-by: Yinbo Zhu --- MAINTAINERS | 1 + arch/loongarch/Kconfig | 1 + arch/loongarch/kernel/time.c | 3 + drivers/clk/Kconfig | 9 ++ drivers/clk/Makefile | 1 + drivers/clk/clk-loongson2.c | 285 +++++++++++++++++++++++++++++++++++ 6 files changed, 300 insertions(+) create mode 100644 drivers/clk/clk-loongson2.c diff --git a/MAINTAINERS b/MAINTAINERS index b6aae412de9c..f01d60cd5c3b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11911,6 +11911,7 @@ LOONGSON2 SOC SERIES CLOCK DRIVER M: Yinbo Zhu L: linux-clk@vger.kernel.org S: Maintained +F: drivers/clk/clk-loongson2.c F: include/dt-bindings/clock/loongson,ls2k-clk.h LSILOGIC MPT FUSION DRIVERS (FC/SAS/SPI) diff --git a/arch/loongarch/Kconfig b/arch/loongarch/Kconfig index 26aeb1408e56..8b65f349cd6e 100644 --- a/arch/loongarch/Kconfig +++ b/arch/loongarch/Kconfig @@ -122,6 +122,7 @@ config LOONGARCH select USE_PERCPU_NUMA_NODE_ID select USER_STACKTRACE_SUPPORT select ZONE_DMA32 + select COMMON_CLK config 32BIT bool diff --git a/arch/loongarch/kernel/time.c b/arch/loongarch/kernel/time.c index 786735dcc8d6..09f20bc81798 100644 --- a/arch/loongarch/kernel/time.c +++ b/arch/loongarch/kernel/time.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include @@ -214,6 +215,8 @@ int __init constant_clocksource_init(void) void __init time_init(void) { + of_clk_init(NULL); + if (!cpu_has_cpucfg) const_clock_freq = cpu_clock_freq; else diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 48f8f4221e21..88620f86373f 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -428,6 +428,15 @@ config COMMON_CLK_K210 help Support for the Canaan Kendryte K210 RISC-V SoC clocks. +config COMMON_CLK_LOONGSON2 + bool "Clock driver for Loongson2 SoC" + depends on COMMON_CLK && OF + help + This driver provides support for Clock Controller that base on + Common Clock Framework Controller (CCF) on Loongson2 SoC. The + Clock Controller can generates and supplies clock to various + peripherals within the SoC. + source "drivers/clk/actions/Kconfig" source "drivers/clk/analogbits/Kconfig" source "drivers/clk/baikal-t1/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index d5db170d38d2..8ccc7436052f 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -75,6 +75,7 @@ obj-$(CONFIG_COMMON_CLK_RS9_PCIE) += clk-renesas-pcie.o obj-$(CONFIG_COMMON_CLK_VC5) += clk-versaclock5.o obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o +obj-$(CONFIG_COMMON_CLK_LOONGSON2) += clk-loongson2.o # please keep this section sorted lexicographically by directory path name obj-y += actions/ diff --git a/drivers/clk/clk-loongson2.c b/drivers/clk/clk-loongson2.c new file mode 100644 index 000000000000..9b753821052c --- /dev/null +++ b/drivers/clk/clk-loongson2.c @@ -0,0 +1,285 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Author: Yinbo Zhu + * Copyright (C) 2022-2023 Loongson Technology Corporation Limited + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define LOONGSON2_PLL_MULT_SHIFT 32 +#define LOONGSON2_PLL_MULT_WIDTH 10 +#define LOONGSON2_PLL_DIV_SHIFT 26 +#define LOONGSON2_PLL_DIV_WIDTH 6 +#define LOONGSON2_APB_FREQSCALE_SHIFT 20 +#define LOONGSON2_APB_FREQSCALE_WIDTH 3 +#define LOONGSON2_USB_FREQSCALE_SHIFT 16 +#define LOONGSON2_USB_FREQSCALE_WIDTH 3 +#define LOONGSON2_SATA_FREQSCALE_SHIFT 12 +#define LOONGSON2_SATA_FREQSCALE_WIDTH 3 + +void __iomem *loongson2_pll_base; +static DEFINE_SPINLOCK(loongson2_clk_lock); +static struct clk_hw **hws; +static struct clk_hw_onecell_data *clk_hw_data; + +static struct clk_hw *loongson2_clk_register(struct device *dev, + const char *name, + const char *parent_name, + const struct clk_ops *ops, + unsigned long flags) +{ + int ret; + struct clk_hw *hw; + struct clk_init_data init; + + /* allocate the divider */ + hw = kzalloc(sizeof(*hw), GFP_KERNEL); + if (!hw) + return ERR_PTR(-ENOMEM); + + init.name = name; + init.ops = ops; + init.flags = flags | CLK_IS_BASIC; + init.parent_names = (parent_name ? &parent_name : NULL); + init.num_parents = (parent_name ? 1 : 0); + hw->init = &init; + + /* register the clock */ + ret = clk_hw_register(dev, hw); + if (ret) { + kfree(hw); + hw = ERR_PTR(ret); + } + + return hw; +} + +static struct clk_hw *loongson2_clk_pll_register(const char *name, + const char *parent, void __iomem *reg) +{ + u64 val; + u32 mult = 1, div = 1; + + val = readq((void *)reg); + + mult = (val >> LOONGSON2_PLL_MULT_SHIFT) & + clk_div_mask(LOONGSON2_PLL_MULT_WIDTH); + div = (val >> LOONGSON2_PLL_DIV_SHIFT) & + clk_div_mask(LOONGSON2_PLL_DIV_WIDTH); + + return clk_hw_register_fixed_factor(NULL, name, parent, + CLK_SET_RATE_PARENT, mult, div); +} + +static unsigned long loongson2_apb_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + u64 val; + u32 mult; + unsigned long rate; + + val = readq((void *)(loongson2_pll_base + 0x50)); + + mult = (val >> LOONGSON2_APB_FREQSCALE_SHIFT) & + clk_div_mask(LOONGSON2_APB_FREQSCALE_WIDTH); + + rate = parent_rate * (mult + 1); + do_div(rate, 8); + + return rate; +} + +static const struct clk_ops loongson2_apb_clk_ops = { + .recalc_rate = loongson2_apb_recalc_rate, +}; + +static unsigned long loongson2_usb_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + u64 val; + u32 mult; + unsigned long rate; + + val = readq((void *)(loongson2_pll_base + 0x50)); + + mult = (val >> LOONGSON2_USB_FREQSCALE_SHIFT) & + clk_div_mask(LOONGSON2_USB_FREQSCALE_WIDTH); + + rate = parent_rate * (mult + 1); + do_div(rate, 8); + + return rate; +} + +static const struct clk_ops loongson2_usb_clk_ops = { + .recalc_rate = loongson2_usb_recalc_rate, +}; + +static unsigned long loongson2_sata_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + u64 val; + u32 mult; + unsigned long rate; + + val = readq((void *)(loongson2_pll_base + 0x50)); + + mult = (val >> LOONGSON2_SATA_FREQSCALE_SHIFT) & + clk_div_mask(LOONGSON2_SATA_FREQSCALE_WIDTH); + + rate = parent_rate * (mult + 1); + do_div(rate, 8); + + return rate; +} + +static const struct clk_ops loongson2_sata_clk_ops = { + .recalc_rate = loongson2_sata_recalc_rate, +}; + +static void loongson2_check_clk_hws(struct clk_hw *clks[], unsigned int count) +{ + unsigned int i; + + for (i = 0; i < count; i++) + if (IS_ERR(clks[i])) + pr_err("Loongson2 clk %u: register failed with %ld\n" + , i, PTR_ERR(clks[i])); +} + +static struct clk_hw *loongson2_obtain_fixed_clk_hw( + struct device_node *np, + const char *name) +{ + struct clk *clk; + + clk = of_clk_get_by_name(np, name); + if (IS_ERR(clk)) + return ERR_PTR(-ENOENT); + + return __clk_get_hw(clk); +} + +static void __init loongson2_clocks_init(struct device_node *np) +{ + loongson2_pll_base = of_iomap(np, 0); + + if (!loongson2_pll_base) { + pr_err("clk: unable to map loongson2 clk registers\n"); + goto err; + } + + clk_hw_data = kzalloc(struct_size(clk_hw_data, hws, LOONGSON2_CLK_END), + GFP_KERNEL); + if (WARN_ON(!clk_hw_data)) + goto err; + + clk_hw_data->num = LOONGSON2_CLK_END; + hws = clk_hw_data->hws; + + hws[LOONGSON2_REF_100M] = loongson2_obtain_fixed_clk_hw(np, + "ref_100m"); + + hws[LOONGSON2_NODE_PLL] = loongson2_clk_pll_register("node_pll_clk", + "ref_100m", + loongson2_pll_base); + + hws[LOONGSON2_DDR_PLL] = loongson2_clk_pll_register("ddr_pll_clk", + "ref_100m", + loongson2_pll_base + 0x10); + + hws[LOONGSON2_DC_PLL] = loongson2_clk_pll_register("dc_pll_clk", + "ref_100m", + loongson2_pll_base + 0x20); + + hws[LOONGSON2_PIX0_PLL] = loongson2_clk_pll_register("pix0_pll_clk", + "ref_100m", + loongson2_pll_base + 0x30); + + hws[LOONGSON2_PIX1_PLL] = loongson2_clk_pll_register("pix1_pll_clk", + "ref_100m", + loongson2_pll_base + 0x40); + + hws[LOONGSON2_NODE_CLK] = clk_hw_register_divider(NULL, "node_clk", + "node_pll_clk", 0, + loongson2_pll_base + 0x8, 0, + 6, CLK_DIVIDER_ONE_BASED, + &loongson2_clk_lock); + + /* + * The hda_clk divisor in the upper 32bits and the clk-prodiver + * layer code doesn't support 64bit io operation thus a conversion + * is required that subtract shift by 32 and add 4byte to the hda + * address + */ + hws[LOONGSON2_HDA_CLK] = clk_hw_register_divider(NULL, "hda_clk", + "ddr_pll_clk", 0, + loongson2_pll_base + 0x22, 12, + 7, CLK_DIVIDER_ONE_BASED, + &loongson2_clk_lock); + + hws[LOONGSON2_GPU_CLK] = clk_hw_register_divider(NULL, "gpu_clk", + "ddr_pll_clk", 0, + loongson2_pll_base + 0x18, 22, + 6, CLK_DIVIDER_ONE_BASED, + &loongson2_clk_lock); + + hws[LOONGSON2_DDR_CLK] = clk_hw_register_divider(NULL, "ddr_clk", + "ddr_pll_clk", 0, + loongson2_pll_base + 0x18, 0, + 6, CLK_DIVIDER_ONE_BASED, + &loongson2_clk_lock); + + hws[LOONGSON2_GMAC_CLK] = clk_hw_register_divider(NULL, "gmac_clk", + "dc_pll_clk", 0, + loongson2_pll_base + 0x28, 22, + 6, CLK_DIVIDER_ONE_BASED, + &loongson2_clk_lock); + + hws[LOONGSON2_DC_CLK] = clk_hw_register_divider(NULL, "dc_clk", + "dc_pll_clk", 0, + loongson2_pll_base + 0x28, 0, + 6, CLK_DIVIDER_ONE_BASED, + &loongson2_clk_lock); + + hws[LOONGSON2_APB_CLK] = loongson2_clk_register(NULL, "apb_clk", + "gmac_clk", + &loongson2_apb_clk_ops, 0); + + hws[LOONGSON2_USB_CLK] = loongson2_clk_register(NULL, "usb_clk", + "gmac_clk", + &loongson2_usb_clk_ops, 0); + + hws[LOONGSON2_SATA_CLK] = loongson2_clk_register(NULL, "sata_clk", + "gmac_clk", + &loongson2_sata_clk_ops, 0); + + hws[LOONGSON2_PIX0_CLK] = clk_hw_register_divider(NULL, "pix0_clk", + "pix0_pll_clk", 0, + loongson2_pll_base + 0x38, 0, 6, + CLK_DIVIDER_ONE_BASED, + &loongson2_clk_lock); + + hws[LOONGSON2_PIX1_CLK] = clk_hw_register_divider(NULL, "pix1_clk", + "pix1_pll_clk", 0, + loongson2_pll_base + 0x48, 0, 6, + CLK_DIVIDER_ONE_BASED, + &loongson2_clk_lock); + + loongson2_check_clk_hws(hws, LOONGSON2_CLK_END); + + of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data); + +err: + iounmap(loongson2_pll_base); +} + +CLK_OF_DECLARE(loongson2_clk, "loongson,ls2k-clk", loongson2_clocks_init); From patchwork Thu Oct 20 06:36:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yinbo Zhu X-Patchwork-Id: 5979 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp96679wrs; Wed, 19 Oct 2022 23:41:38 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6ktdovdeWY380WLWJ3dZ4W5Tz1Q8fBrDLH7JT3tgtCaHIWgu7KChe3TQzGJIlhChWJ45cU X-Received: by 2002:a63:824a:0:b0:46b:272f:d75f with SMTP id w71-20020a63824a000000b0046b272fd75fmr10378592pgd.268.1666248098680; Wed, 19 Oct 2022 23:41:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666248098; cv=none; d=google.com; s=arc-20160816; b=F7KFwzSDKh/JN8ao4FRelusCUA00ly4Jpw4Q1Gn8R+aEqqoNB7u6b0XPpaIgxgN/kT 10bAatp52I7EYTYj9FRlRnPqfVFe6ZRaNbq84rH1KKS5HyMFJlZZfTuxuctGbds0xV3u o0CStV1QexISA39HN7O4F14dJNqTkta5HQ7d6+1YLee7wGiXNUflCTewkmyylUEDFrkB 0X6S939SGKvnRuSmg2IRmgJ27tKf5NG70twcLcsvyYPymgZELfPySYuNKpRRn3c4EJtZ Wch4JIKBkcn4XW8mfbFsDmZ3vY988JEZUtGM04d72cBhoiizJ/MEXp2FJ63uppKAH1TB XwsQ== ARC-Message-Signature: i=1; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id n6-20020a17090a9f0600b00202fd098892si1943514pjp.190.2022.10.19.23.41.24; Wed, 19 Oct 2022 23:41:38 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229866AbiJTGgn (ORCPT + 99 others); Thu, 20 Oct 2022 02:36:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48296 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229835AbiJTGgh (ORCPT ); Thu, 20 Oct 2022 02:36:37 -0400 Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 6AFA9173589; Wed, 19 Oct 2022 23:36:35 -0700 (PDT) Received: from loongson.cn (unknown [10.180.13.64]) by gateway (Coremail) with SMTP id _____8Dx_Nhy7FBjtvUAAA--.4790S3; Thu, 20 Oct 2022 14:36:34 +0800 (CST) Received: from localhost.localdomain (unknown [10.180.13.64]) by localhost.localdomain (Coremail) with SMTP id AQAAf8Axf+Bq7FBjccEBAA--.7362S4; Thu, 20 Oct 2022 14:36:33 +0800 (CST) From: Yinbo Zhu To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Huacai Chen , WANG Xuerui , Jiaxun Yang , Jianmin Lv , Yang Li , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, loongarch@lists.linux.dev, Yinbo Zhu Subject: [PATCH v3 3/3] dt-bindings: clock: add loongson2 clock Date: Thu, 20 Oct 2022 14:36:24 +0800 Message-Id: <20221020063624.17548-3-zhuyinbo@loongson.cn> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20221020063624.17548-1-zhuyinbo@loongson.cn> References: <20221020063624.17548-1-zhuyinbo@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf8Axf+Bq7FBjccEBAA--.7362S4 X-CM-SenderInfo: 52kx5xhqerqz5rrqw2lrqou0/ X-Coremail-Antispam: 1Uk129KBjvJXoWxXF47tF4kJw4fKFyfWF1kuFg_yoW5GFyrpF sxC34rGry0vF17Zws5tFyxA3Z5Z3Z7CFnrZFsrAa42kF98W3W5XF17K34DZa9rAr17Z39F vFWfWr4UC3WxCr7anT9S1TB71UUUUjDqnTZGkaVYY2UrUUUUj1kv1TuYvTs0mT0YCTnIWj qI5I8CrVACY4xI64kE6c02F40Ex7xfYxn0WfASr-VFAUDa7-sFnT9fnUUIcSsGvfJTRUUU bfAFc2x0x2IEx4CE42xK8VAvwI8IcIk0rVWrJVCq3wAFIxvE14AKwVWUXVWUAwA2ocxC64 kIII0Yj41l84x0c7CEw4AK67xGY2AK021l84ACjcxK6xIIjxv20xvE14v26F1j6w1UM28E F7xvwVC0I7IYx2IY6xkF7I0E14v26F4j6r4UJwA2z4x0Y4vEx4A2jsIE14v26r4UJVWxJr 1l84ACjcxK6I8E87Iv6xkF7I0E14v26r4UJVWxJr1ln4kS14v26r126r1DM2AIxVAIcxkE cVAq07x20xvEncxIr21l57IF6xkI12xvs2x26I8E6xACxx1l5I8CrVACY4xI64kE6c02F4 0Ex7xfMcIj6xIIjxv20xvE14v26r1q6rW5McIj6I8E87Iv67AKxVW8JVWxJwAm72CE4IkC 6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41lc7CjxVAaw2AFwI0_JF0_Jw1l42xK82IYc2 Ij64vIr41l42xK82IY6x8ErcxFaVAv8VWrMxC20s026xCaFVCjc4AY6r1j6r4UMxCIbckI 1I0E14v26r126r1DMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_Jr Wlx4CE17CEb7AF67AKxVWUtVW8ZwCIc40Y0x0EwIxGrwCI42IY6xIIjxv20xvE14v26ryj 6F1UMIIF0xvE2Ix0cI8IcVCY1x0267AKxVW8JVWxJwCI42IY6xAIw20EY4v20xvaj40_Jr 0_JF4lIxAIcVC2z280aVAFwI0_Gr0_Cr1lIxAIcVC2z280aVCY1x0267AKxVW8JVW8JrUv cSsGvfC2KfnxnUUI43ZEXa7IU8mQ6JUUUUU== X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_PASS, SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747187766264234437?= X-GMAIL-MSGID: =?utf-8?q?1747187766264234437?= Add the loongson2 clock binding with DT schema format using json-schema. Signed-off-by: Yinbo Zhu Reviewed-by: Krzysztof Kozlowski --- Change in v3: 1. Drop redundant (last) binding from the title. 2. Drop "- |" between ref_100m node and clk node. .../bindings/clock/loongson,ls2k-clk.yaml | 63 +++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 64 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml diff --git a/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml b/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml new file mode 100644 index 000000000000..6cc6e0755735 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/loongson,ls2k-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Loongson2 SoC Clock Control Module + +maintainers: + - Yinbo Zhu + +description: | + Loongson2 SoC clock control module is an integrated clock controller, which + generates and supplies to all modules. + +properties: + compatible: + enum: + - loongson,ls2k-clk + + reg: + maxItems: 1 + + clocks: + items: + - description: 100m ref + + clock-names: + items: + - const: ref_100m + + '#clock-cells': + const: 1 + description: + The clock consumer should specify the desired clock by having the clock + ID in its "clocks" phandle cell. See include/dt-bindings/clock/loongson,ls2k-clk.h + for the full list of loongson2 SoC clock IDs. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + ref_100m: clock-ref-100m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "ref_100m"; + }; + + clk: clock-controller@1fe00480 { + compatible = "loongson,ls2k-clk"; + reg = <0x1fe00480 0x58>; + #clock-cells = <1>; + clocks = <&ref_100m>; + clock-names = "ref_100m"; + }; diff --git a/MAINTAINERS b/MAINTAINERS index f01d60cd5c3b..f61a431ad8ca 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11911,6 +11911,7 @@ LOONGSON2 SOC SERIES CLOCK DRIVER M: Yinbo Zhu L: linux-clk@vger.kernel.org S: Maintained +F: Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml F: drivers/clk/clk-loongson2.c F: include/dt-bindings/clock/loongson,ls2k-clk.h