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[2620:137:e000::1:20]) by mx.google.com with ESMTP id n17-20020a056a0007d100b006257ed5351esi2770640pfu.194.2023.03.22.19.43.41; Wed, 22 Mar 2023 19:43:54 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230159AbjCWCkm (ORCPT + 99 others); Wed, 22 Mar 2023 22:40:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48542 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229903AbjCWCki (ORCPT ); Wed, 22 Mar 2023 22:40:38 -0400 Received: from mx1.zhaoxin.com (MX1.ZHAOXIN.COM [210.0.225.12]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 995EB2ED62 for ; Wed, 22 Mar 2023 19:40:34 -0700 (PDT) X-ASG-Debug-ID: 1679539227-086e23383d19100002-xx1T2L Received: from ZXSHMBX1.zhaoxin.com (ZXSHMBX1.zhaoxin.com [10.28.252.163]) by mx1.zhaoxin.com with ESMTP id ayoFbDVMQOAafL9L (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NO); Thu, 23 Mar 2023 10:40:28 +0800 (CST) X-Barracuda-Envelope-From: SilviaZhao-oc@zhaoxin.com X-Barracuda-RBL-Trusted-Forwarder: 10.28.252.163 Received: from ZXBJMBX02.zhaoxin.com (10.29.252.6) by ZXSHMBX1.zhaoxin.com (10.28.252.163) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.16; Thu, 23 Mar 2023 10:40:27 +0800 Received: from silvia-OptiPlex-3010.zhaoxin.com (10.29.8.47) by ZXBJMBX02.zhaoxin.com (10.29.252.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.16; Thu, 23 Mar 2023 10:40:26 +0800 X-Barracuda-RBL-Trusted-Forwarder: 10.28.252.163 From: silviazhao X-Barracuda-RBL-Trusted-Forwarder: 10.29.252.6 To: , , , , , , , , , , , , , , , CC: , , , Subject: [PATCH 1/3] x86/cpu/zhaoxin: Introduce macros for Zhaoxin family numbers Date: Thu, 23 Mar 2023 10:40:24 +0800 X-ASG-Orig-Subj: [PATCH 1/3] x86/cpu/zhaoxin: Introduce macros for Zhaoxin family numbers Message-ID: <20230323024026.823-2-silviazhao-oc@zhaoxin.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230323024026.823-1-silviazhao-oc@zhaoxin.com> References: <20230323024026.823-1-silviazhao-oc@zhaoxin.com> MIME-Version: 1.0 X-Originating-IP: [10.29.8.47] X-ClientProxiedBy: zxbjmbx1.zhaoxin.com (10.29.252.163) To ZXBJMBX02.zhaoxin.com (10.29.252.6) X-Barracuda-Connect: ZXSHMBX1.zhaoxin.com[10.28.252.163] X-Barracuda-Start-Time: 1679539227 X-Barracuda-Encrypted: ECDHE-RSA-AES128-GCM-SHA256 X-Barracuda-URL: https://10.28.252.35:4443/cgi-mod/mark.cgi X-Virus-Scanned: by bsmtpd at zhaoxin.com X-Barracuda-Scan-Msg-Size: 1227 X-Barracuda-BRTS-Status: 1 X-Barracuda-Bayes: INNOCENT GLOBAL 0.0000 1.0000 -2.0210 X-Barracuda-Spam-Score: -2.02 X-Barracuda-Spam-Status: No, SCORE=-2.02 using global scores of TAG_LEVEL=1000.0 QUARANTINE_LEVEL=1000.0 KILL_LEVEL=9.0 tests= X-Barracuda-Spam-Report: Code version 3.2, rules version 3.2.3.106421 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------------------------- X-Spam-Status: No, score=0.0 required=5.0 tests=SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761124741548911434?= X-GMAIL-MSGID: =?utf-8?q?1761124741548911434?= Create zhaoxin-family.h to define Zhaoxin family numbers in one header file. So we can use the macros instead of open-coded model numbers in other files. Signed-off-by: silviazhao --- arch/x86/include/asm/zhaoxin-family.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 arch/x86/include/asm/zhaoxin-family.h diff --git a/arch/x86/include/asm/zhaoxin-family.h b/arch/x86/include/asm/zhaoxin-family.h new file mode 100644 index 000000000000..d54e0112207a --- /dev/null +++ b/arch/x86/include/asm/zhaoxin-family.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_X86_ZHAOXIN_FAMILY_H +#define _ASM_X86_ZHAOXIN_FAMILY_H + +/* + * The defined symbol names have the following form: + * ZHAOXIN_FAM7{OPTFAMILY}_{MICROARCH} + * where: + * OPTFAMILY Describes the family of CPUs that this belongs to. Default + * is assumed to be omitted. + * MICROARCH Is the code name for the micro-architecture for this core. + */ + + +#define ZHAOXIN_FAM7_WUDAOKOU 0x1B +#define ZHAOXIN_FAM7_LUJIAZUI 0x3B +#define ZHAOXIN_FAM7_YONGFENG 0x5B + +#endif /* _ASM_X86_ZHAOXIN_FAMILY_H */ From patchwork Thu Mar 23 02:40:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: silviazhao X-Patchwork-Id: 73751 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:604a:0:0:0:0:0 with SMTP id j10csp2684497wrt; Wed, 22 Mar 2023 19:43:47 -0700 (PDT) X-Google-Smtp-Source: AKy350ZKCRekKJQRECmw9DoBdHPL0Buy3Q7gJf2vp/I0wi9KjtR3iACctPnVrFq6L2rla5A1LwW4 X-Received: by 2002:a17:90b:4cc7:b0:234:56aa:f176 with SMTP id nd7-20020a17090b4cc700b0023456aaf176mr3501985pjb.24.1679539426826; Wed, 22 Mar 2023 19:43:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1679539426; cv=none; d=google.com; s=arc-20160816; b=RItEcdlA49sUki4TLORdQ0KyhgTtprQ7ECE8QhcBDGbg9nKYOmqwAv0/ofy4EdK429 +h6/Z8QLXdIgE2PJuArXF0yxxXl1Efl2dEW85ivXwxE9yWzPUS5wBO2a/HOg1koWwvIc j83ceTgr0tjbcbX/q06v6Vb6JDUQNvDdK3cXFJfmJaoFson8gvu7aPC1D3e8hh4dVCOg 2HZO5bqnLRxnT3GpUsdak1UlXsB9060xhmC2q4hndSQ5U4Hpv0Go8U5jtyyQdG7Nv+Td G8zAqlY8h6WB712nvlYg6s9Due+YdB3wGHZW4ib2D3s8Lxl7rO1Bxw1Iuo1fhYWZvwKV Rxng== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from; bh=Kguhd69NxU1yv0p7N7sovQnQvuydQwQS4G4mYnHWh0c=; b=kS2uFoaY05YcaxQ0qQlSN5LT/Su6FVRd845eqSiSbRhKI1lB5qc7VnJPgvUIOm8srh NrI1TKAzVAiY8CjAt1kbaSMHmVx6uwlUHcQAUVAH4LqdYX7LBEpHUn0afBo8iWPSozhd WGW/8oL4BuXNSpblyBeiI74u9XpVJR1X8mIH/BkxOiJ7IqTe0y/vdTuShMiOSwlz+q5F opWZoHCHo5Vp46VGXKfw/Nh29bm+K9MXz2P8dsnwYjc5PzogvmwERWjX9lCradvApTWX cl2Y2Ypwooftl0MXCt7aQ1QMIC+SyHNYV7EP0jxZ8EDONzYADcxMSZMCl/IFjn7l334Z VSWQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id ls17-20020a17090b351100b00240263ef126si372650pjb.126.2023.03.22.19.43.34; Wed, 22 Mar 2023 19:43:46 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230101AbjCWCkp (ORCPT + 99 others); Wed, 22 Mar 2023 22:40:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48562 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230000AbjCWCki (ORCPT ); Wed, 22 Mar 2023 22:40:38 -0400 Received: from mx1.zhaoxin.com (MX1.ZHAOXIN.COM [210.0.225.12]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3FCC12ED65 for ; Wed, 22 Mar 2023 19:40:37 -0700 (PDT) X-ASG-Debug-ID: 1679539227-086e23383d19100003-xx1T2L Received: from ZXSHMBX1.zhaoxin.com (ZXSHMBX1.zhaoxin.com [10.28.252.163]) by mx1.zhaoxin.com with ESMTP id bDEbG0HSgFQx1BTG (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NO); Thu, 23 Mar 2023 10:40:28 +0800 (CST) X-Barracuda-Envelope-From: SilviaZhao-oc@zhaoxin.com X-Barracuda-RBL-Trusted-Forwarder: 10.28.252.163 Received: from ZXBJMBX02.zhaoxin.com (10.29.252.6) by ZXSHMBX1.zhaoxin.com (10.28.252.163) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.16; Thu, 23 Mar 2023 10:40:28 +0800 Received: from silvia-OptiPlex-3010.zhaoxin.com (10.29.8.47) by ZXBJMBX02.zhaoxin.com (10.29.252.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.16; Thu, 23 Mar 2023 10:40:26 +0800 X-Barracuda-RBL-Trusted-Forwarder: 10.28.252.163 From: silviazhao X-Barracuda-RBL-Trusted-Forwarder: 10.29.252.6 To: , , , , , , , , , , , , , , , CC: , , , Subject: [PATCH 2/3] perf/x86/zhaoxin: Replace open-coded model number with macros Date: Thu, 23 Mar 2023 10:40:25 +0800 X-ASG-Orig-Subj: [PATCH 2/3] perf/x86/zhaoxin: Replace open-coded model number with macros Message-ID: <20230323024026.823-3-silviazhao-oc@zhaoxin.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230323024026.823-1-silviazhao-oc@zhaoxin.com> References: <20230323024026.823-1-silviazhao-oc@zhaoxin.com> MIME-Version: 1.0 X-Originating-IP: [10.29.8.47] X-ClientProxiedBy: zxbjmbx1.zhaoxin.com (10.29.252.163) To ZXBJMBX02.zhaoxin.com (10.29.252.6) X-Barracuda-Connect: ZXSHMBX1.zhaoxin.com[10.28.252.163] X-Barracuda-Start-Time: 1679539228 X-Barracuda-Encrypted: ECDHE-RSA-AES128-GCM-SHA256 X-Barracuda-URL: https://10.28.252.35:4443/cgi-mod/mark.cgi X-Virus-Scanned: by bsmtpd at zhaoxin.com X-Barracuda-Scan-Msg-Size: 3668 X-Barracuda-BRTS-Status: 1 X-Barracuda-Bayes: INNOCENT GLOBAL 0.0000 1.0000 -2.0210 X-Barracuda-Spam-Score: -2.02 X-Barracuda-Spam-Status: No, SCORE=-2.02 using global scores of TAG_LEVEL=1000.0 QUARANTINE_LEVEL=1000.0 KILL_LEVEL=9.0 tests= X-Barracuda-Spam-Report: Code version 3.2, rules version 3.2.3.106421 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------------------------- X-Spam-Status: No, score=0.0 required=5.0 tests=SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761124733577204779?= X-GMAIL-MSGID: =?utf-8?q?1761124733577204779?= Replace open-coded family-7 model number in arch/x86/events/zhaoxin/ core.c with the macros defined in zhaoxin-family.h. Zhaoxin used to use non-canonical name for family 7 processors in arch/x86/events/zhaoxin/core.c. Replace them with architecture name to keep consistent with the macros. Following are the correspondences: ZXD -> Wudaokou ZXE -> Lujiazui Signed-off-by: silviazhao --- arch/x86/events/zhaoxin/core.c | 25 +++++++++++++------------ 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/arch/x86/events/zhaoxin/core.c b/arch/x86/events/zhaoxin/core.c index 3e9acdaeed1e..34ccb214478c 100644 --- a/arch/x86/events/zhaoxin/core.c +++ b/arch/x86/events/zhaoxin/core.c @@ -14,6 +14,7 @@ #include #include +#include #include #include "../perf_event.h" @@ -36,7 +37,7 @@ static struct event_constraint zxc_event_constraints[] __read_mostly = { EVENT_CONSTRAINT_END }; -static struct event_constraint zxd_event_constraints[] __read_mostly = { +static struct event_constraint wudaokou_event_constraints[] __read_mostly = { FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* retired instructions */ FIXED_EVENT_CONSTRAINT(0x0082, 1), /* unhalted core clock cycles */ @@ -44,7 +45,7 @@ static struct event_constraint zxd_event_constraints[] __read_mostly = { EVENT_CONSTRAINT_END }; -static __initconst const u64 zxd_hw_cache_event_ids +static __initconst const u64 wudaokou_hw_cache_event_ids [PERF_COUNT_HW_CACHE_MAX] [PERF_COUNT_HW_CACHE_OP_MAX] [PERF_COUNT_HW_CACHE_RESULT_MAX] = { @@ -148,7 +149,7 @@ static __initconst const u64 zxd_hw_cache_event_ids }, }; -static __initconst const u64 zxe_hw_cache_event_ids +static __initconst const u64 lujiazui_hw_cache_event_ids [PERF_COUNT_HW_CACHE_MAX] [PERF_COUNT_HW_CACHE_OP_MAX] [PERF_COUNT_HW_CACHE_RESULT_MAX] = { @@ -471,7 +472,7 @@ static const struct x86_pmu zhaoxin_pmu __initconst = { .max_events = ARRAY_SIZE(zx_pmon_event_map), .apic = 1, /* - * For zxd/zxe, read/write operation for PMCx MSR is 48 bits. + * For wudaokou/lujiazui, read/write operation for PMCx MSR is 48 bits. */ .max_period = (1ULL << 47) - 1, .get_event_constraints = zhaoxin_get_event_constraints, @@ -573,27 +574,27 @@ __init int zhaoxin_pmu_init(void) X86_CONFIG(.event = 0x0f, .umask = 0x04, .inv = 0, .cmask = 0); switch (boot_cpu_data.x86_model) { - case 0x1b: - memcpy(hw_cache_event_ids, zxd_hw_cache_event_ids, + case ZHAOXIN_FAM7_WUDAOKOU: + memcpy(hw_cache_event_ids, wudaokou_hw_cache_event_ids, sizeof(hw_cache_event_ids)); - x86_pmu.event_constraints = zxd_event_constraints; + x86_pmu.event_constraints = wudaokou_event_constraints; zx_pmon_event_map[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x0700; zx_pmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x0709; - pr_cont("ZXD events, "); + pr_cont("Wudaokou events, "); break; - case 0x3b: - memcpy(hw_cache_event_ids, zxe_hw_cache_event_ids, + case ZHAOXIN_FAM7_LUJIAZUI: + memcpy(hw_cache_event_ids, lujiazui_hw_cache_event_ids, sizeof(hw_cache_event_ids)); - x86_pmu.event_constraints = zxd_event_constraints; + x86_pmu.event_constraints = wudaokou_event_constraints; zx_pmon_event_map[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x0028; zx_pmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x0029; - pr_cont("ZXE events, "); + pr_cont("Lujiazui events, "); break; default: return -ENODEV; From patchwork Thu Mar 23 02:40:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: silviazhao X-Patchwork-Id: 73753 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:604a:0:0:0:0:0 with SMTP id j10csp2684838wrt; Wed, 22 Mar 2023 19:45:02 -0700 (PDT) X-Google-Smtp-Source: AK7set+Kwq3ocgivLdtkKIuSJ4U+VVFHrWnn5uZdbpWrd9Mq4Qm8pAP0PJYZRPhTCI/m/t6XXsSa X-Received: by 2002:a05:6a20:6714:b0:da:897b:ae40 with SMTP id q20-20020a056a20671400b000da897bae40mr1646744pzh.37.1679539502548; Wed, 22 Mar 2023 19:45:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1679539502; cv=none; d=google.com; s=arc-20160816; b=FWCtPXzVTNp2k7GUWzGCQa8f2IwAqGggjr3QBck6GGuR48FiorA7d8egf9RWEj3qTk qAgJm566neyu/2q9+w8KbNey+mkPgZUiNsJZrZe+4Xq+w5uMb+enH6fBrYiKCBovWVDW 8/E3hEhOeMRub/bCwzKUQEU6bspFhDfJD0bP4Q/nqxv32crR+YSP4pHyZ5eDzfc5GxHW 42GpV5MdbP+19OkgrER9gx7HVdDojZ6/MBZBLnnWtRs3zgbvJOXCU/o1m3OxY1JPM16L gxyuilxGUoCjh9TiCOaoYHUlXGP9gbuPq5Tu8jHycE59iczWdkjtwozA9mj4zALgzQhH zfaw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from; bh=6ApFnArzcSLVWqT9AAR+pVgW7BkqvEZ5kxseu1qirTs=; b=fZRnM7BcPIYz0m/posxmigpVrZm1Xw0VxuTmxvinTkFL0uNpg3Eb8k9fLiIvO295Qk uQEVh7GNujueXPBKk+/3TjMubdquA2SluRWfSuOlNV5+7y8NAO1NouQMtFM+mjAnK2GI pBrrFls1ksLxtvwdhOno5zpTCSdTq/U8d7U5Wph5Y5HezuRmHKFV5eXPEOsXngJpqhCF Px/GP5BaXY8t2uN+t934Xjj9Rf2cjEt0LY6Kvn4r+1Mo96TwUHlzi6SIKiXFW5HzhoCo y+JpSf/BSvg5xgnPuHL9dawwKXulZpPkLGlgFBCkkYp2Ht04BxyiUgMuhsid6/7rkP/l 8Uxg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Remove PERF_COUNT_HW_CACHE_REFERENCES and PERF_COUNT_HW_CACHE_MISSES from global zx_pmon_event_map, since the cache hierarchy was changed from Yongfeng, and these pmc event map changed too. Add PERF_COUNT_HW_BRANCH_INSTRUCTIONS and PERF_COUNT_HW_BRANCH_MISSES to global zx_pmon_event_map, since these two events will keep consistent for Lujiazui and later. Signed-off-by: silviazhao --- arch/x86/events/zhaoxin/core.c | 30 +++++++++++++++++++++++++----- 1 file changed, 25 insertions(+), 5 deletions(-) diff --git a/arch/x86/events/zhaoxin/core.c b/arch/x86/events/zhaoxin/core.c index 34ccb214478c..634aa0c4a8c6 100644 --- a/arch/x86/events/zhaoxin/core.c +++ b/arch/x86/events/zhaoxin/core.c @@ -20,15 +20,15 @@ #include "../perf_event.h" /* - * Zhaoxin PerfMon, used on zxc and later. + * Zhaoxin PerfMon, used on Lujiazui and later. */ static u64 zx_pmon_event_map[PERF_COUNT_HW_MAX] __read_mostly = { [PERF_COUNT_HW_CPU_CYCLES] = 0x0082, [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, - [PERF_COUNT_HW_CACHE_REFERENCES] = 0x0515, - [PERF_COUNT_HW_CACHE_MISSES] = 0x051a, [PERF_COUNT_HW_BUS_CYCLES] = 0x0083, + [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x0028, + [PERF_COUNT_HW_BRANCH_MISSES] = 0x0029, }; static struct event_constraint zxc_event_constraints[] __read_mostly = { @@ -560,6 +560,8 @@ __init int zhaoxin_pmu_init(void) zx_pmon_event_map[PERF_COUNT_HW_CACHE_REFERENCES] = 0; zx_pmon_event_map[PERF_COUNT_HW_CACHE_MISSES] = 0; zx_pmon_event_map[PERF_COUNT_HW_BUS_CYCLES] = 0; + zx_pmon_event_map[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0; + zx_pmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0; pr_cont("ZXC events, "); break; @@ -580,6 +582,9 @@ __init int zhaoxin_pmu_init(void) x86_pmu.event_constraints = wudaokou_event_constraints; + zx_pmon_event_map[PERF_COUNT_HW_CACHE_REFERENCES] = 0x0515, + zx_pmon_event_map[PERF_COUNT_HW_CACHE_MISSES] = 0x051a, + zx_pmon_event_map[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x0700; zx_pmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x0709; @@ -591,11 +596,26 @@ __init int zhaoxin_pmu_init(void) x86_pmu.event_constraints = wudaokou_event_constraints; - zx_pmon_event_map[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x0028; - zx_pmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x0029; + zx_pmon_event_map[PERF_COUNT_HW_CACHE_REFERENCES] = 0x0515, + zx_pmon_event_map[PERF_COUNT_HW_CACHE_MISSES] = 0x051a, pr_cont("Lujiazui events, "); break; + case ZHAOXIN_FAM7_YONGFENG: + zx_pmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = + X86_CONFIG(.event = 0x02, .umask = 0x01, .inv = 0x01, + .cmask = 0x01); + + memcpy(hw_cache_event_ids, lujiazui_hw_cache_event_ids, + sizeof(hw_cache_event_ids)); + + x86_pmu.event_constraints = wudaokou_event_constraints; + + zx_pmon_event_map[PERF_COUNT_HW_CACHE_REFERENCES] = 0x051a; + zx_pmon_event_map[PERF_COUNT_HW_CACHE_MISSES] = 0; + + pr_cont("Yongfeng events, "); + break; default: return -ENODEV; }