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Signed-off-by: Dipen Patel Acked-by: Thierry Reding --- MAINTAINERS | 3 +++ 1 file changed, 3 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 8d5bc223f305..65b58963f0d2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -9425,6 +9425,9 @@ F: drivers/input/touchscreen/htcpen.c HTE SUBSYSTEM M: Dipen Patel +L: timestamp@lists.linux.dev +T: git git://git.kernel.org/pub/scm/linux/kernel/git/pateldipen1984/linux.git +Q: https://patchwork.kernel.org/project/timestamp/list/ S: Maintained F: Documentation/devicetree/bindings/timestamp/ F: Documentation/driver-api/hte/ From patchwork Thu Mar 23 01:29:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dipen Patel X-Patchwork-Id: 73737 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:604a:0:0:0:0:0 with SMTP id j10csp2664057wrt; Wed, 22 Mar 2023 18:31:08 -0700 (PDT) X-Google-Smtp-Source: AK7set8GLMzvOwfvy+xpBOp0mmAkVw+aJmM0rzhMLNcnd3zAvdMfEVKGddyol4IUq9rO812iCga0 X-Received: by 2002:a17:906:851a:b0:930:e2c:ddc3 with SMTP id i26-20020a170906851a00b009300e2cddc3mr9351414ejx.72.1679535068268; Wed, 22 Mar 2023 18:31:08 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1679535068; cv=pass; d=google.com; s=arc-20160816; b=dClBaVO+MSKv2DmG2aIdPflKanQT4xLDmw3laQ5DCybEeuA/i2E1WgdzZ72i15+4YC bXFg6ZXeJlGrPLhI7ocImWB8a9lQeR+lgUmMtqrGQSXMlQlqfZrS1rbkxOFK64wGufkh MQtixFTZ7obuFiXR8grLuerKjodMbT6uYikk/Hv/0uLoVckmDyUMDsE0mdHlZ3NMTcd1 NutUR1c3wYROGocnlC2DK1W8QuEnBUQ2ln6x3Fu4HZxqnVh5GCk4S5IL3JyQHxSuJWD8 HYXcA8cGoZferPsd7uN6CECWkKNG704o+UaC5cNTHWL7GXw67wnm0bMX8IJFKgZJJwLA aQ2A== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=ZG9Z9etWlohMIrbvOzFyAIxV9lXcepZbcGTnji9eEPI=; b=pwTKXk1LeDfzWfznueyTHdc3JGoacwpVpl/XP+Cr9bpTO2YbOCAR3LJy89akiIHYV4 ZCM6ujlx19BnlPOJCmog73FNJMo9wrFuDpKkKW5ZeXW0gY6T5z/Hwg7zauuMgtJ5KKgK 8MuCJUaG1p7KtWI3D1Oo9y9KcOr4+naPa81vJSa2z9TGKnPsgCGvrr19+zMyo9x0Cf1L vTuZiZUswpCQB3FKg2I3EeMEffXCSto8ps7Geq8qOUmhaNrVrfIAHmJftjhygNvaSSFq 6f1kfGYubmIG3zHDoAtVB+B/RlajV+akZHrivViZNjRQckuHXOpBpkKwfELfsGmXDt71 9pBQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b=PmUajUvt; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Dipen Patel Reviewed-by: Krzysztof Kozlowski --- v2: - Removed nvidia,slices property - Added nvidia,gpio-controller based on review comments from Thierry, this will help simplify the hte provider driver. v3: - Explained changes in detail in commit message - Added allOf section per review comment v4: - Logically divide the v3 patch as follows - Created Tegra234 support patch - Created depracate nvidia,slices property patch - Created addition of the nvidia,gpio-controller property patch .../timestamp/nvidia,tegra194-hte.yaml | 44 +++++++++++++++++-- 1 file changed, 40 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/timestamp/nvidia,tegra194-hte.yaml b/Documentation/devicetree/bindings/timestamp/nvidia,tegra194-hte.yaml index c31e207d1652..158dbe58c49f 100644 --- a/Documentation/devicetree/bindings/timestamp/nvidia,tegra194-hte.yaml +++ b/Documentation/devicetree/bindings/timestamp/nvidia,tegra194-hte.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/timestamp/nvidia,tegra194-hte.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Tegra194 on chip generic hardware timestamping engine (HTE) +title: Tegra on chip generic hardware timestamping engine (HTE) provider maintainers: - Dipen Patel @@ -23,6 +23,8 @@ properties: enum: - nvidia,tegra194-gte-aon - nvidia,tegra194-gte-lic + - nvidia,tegra234-gte-aon + - nvidia,tegra234-gte-lic reg: maxItems: 1 @@ -43,9 +45,8 @@ properties: description: HTE lines are arranged in 32 bit slice where each bit represents different line/signal that it can enable/configure for the timestamp. It is u32 - property and depends on the HTE instance in the chip. The value 3 is for - GPIO GTE and 11 for IRQ GTE. - enum: [3, 11] + property and the value depends on the HTE instance in the chip. + enum: [3, 11, 17] '#timestamp-cells': description: @@ -55,6 +56,41 @@ properties: mentioned in the nvidia GPIO device tree binding document. const: 1 +allOf: + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra194-gte-aon + - nvidia,tegra234-gte-aon + then: + properties: + nvidia,slices: + const: 3 + + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra194-gte-lic + then: + properties: + nvidia,slices: + const: 11 + + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra234-gte-lic + then: + properties: + nvidia,slices: + const: 17 + required: - compatible - reg From patchwork Thu Mar 23 01:29:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dipen Patel X-Patchwork-Id: 73735 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:604a:0:0:0:0:0 with SMTP id j10csp2663928wrt; Wed, 22 Mar 2023 18:30:48 -0700 (PDT) X-Google-Smtp-Source: AK7set/i4AAa+kxIZe1TXnEaPUtP39dHY1f16PD10uAztKTUrCMBiRWdnrohOOsFkrbh/VSbzuao X-Received: by 2002:a17:906:4d4f:b0:91f:32f9:82f0 with SMTP id b15-20020a1709064d4f00b0091f32f982f0mr8257538ejv.29.1679535048560; Wed, 22 Mar 2023 18:30:48 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1679535048; cv=pass; d=google.com; s=arc-20160816; b=yrkzcag4zXoo6AMP0FEaygwMBgQBmSPPZUO8jFq8KmAC/QNpEXo1B0aYL6VRYTeRAZ RqCrvu/l8KNXTv9amyUMaAnpWTpW9d0SLnStqrIn2ZcROw7iUOMhd1l9MM7YSrGf4U+1 hmkeW9byBJvnHPVYNFljLyRzHT+ZRbCc71FkDpRkyPC23l7KwL9r8GgXe7FJ3HfBR2vG 9M9cxQB+C8e3vDMmt1Q/YbNHSpGyMFz1nqwSaPJdCLHe1F3Q5eGtJpt98mGoajDRNu83 H/WQmhtEAh3qeFse1IEGx2jQGVC6FiSQiZJ1qbfNx+G5F+bqbOKc7K1OZKc2qry7XmiI +G5g== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=KXcxWxjWhxhBkMWqcTnUOeQp+YebY9tv93uPQ2Lf9hk=; b=i4MCeGI550KmLJfxp4pohu5SNeFPf+SR9Vu859C4Uq7mA6EEjGTCziRBXZkPpI0Z67 WSrigjnlnDeaT14xe6sCq2LrKIa6EhZ/VObIy2ZTAjtDlXx7fDO32TG9J5q3LBZVaER/ eyhiSu1veMfERxJDavxjmnRXoY2dRexjNEi+B4MmpPma0fEsf43T93nSPiQa8+zvxsp6 Ha/3n3yCasv6S4aSs3ORclE3T5RHljIJQktMo75y/g25BeRbE97p7TuMVtVjVXA2O+Ox 6P0U9zFNCw492vJK5KT/UVfpkET3FsAImP4itBpmCnViXiT3ljsLGSdgmh1U3Bc+DVkf wyxQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b=fHSEFCLV; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Dipen Patel Reviewed-by: Linus Walleij --- .../timestamp/nvidia,tegra194-hte.yaml | 43 ++----------------- 1 file changed, 4 insertions(+), 39 deletions(-) diff --git a/Documentation/devicetree/bindings/timestamp/nvidia,tegra194-hte.yaml b/Documentation/devicetree/bindings/timestamp/nvidia,tegra194-hte.yaml index 158dbe58c49f..eafc33e9ae2e 100644 --- a/Documentation/devicetree/bindings/timestamp/nvidia,tegra194-hte.yaml +++ b/Documentation/devicetree/bindings/timestamp/nvidia,tegra194-hte.yaml @@ -42,10 +42,13 @@ properties: nvidia,slices: $ref: /schemas/types.yaml#/definitions/uint32 + deprecated: true description: HTE lines are arranged in 32 bit slice where each bit represents different line/signal that it can enable/configure for the timestamp. It is u32 - property and the value depends on the HTE instance in the chip. + property and the value depends on the HTE instance in the chip. The AON + GTE instances for both Tegra194 and Tegra234 has 3 slices. The Tegra194 + LIC instance has 11 slices and Tegra234 LIC has 17 slices. enum: [3, 11, 17] '#timestamp-cells': @@ -56,46 +59,10 @@ properties: mentioned in the nvidia GPIO device tree binding document. const: 1 -allOf: - - if: - properties: - compatible: - contains: - enum: - - nvidia,tegra194-gte-aon - - nvidia,tegra234-gte-aon - then: - properties: - nvidia,slices: - const: 3 - - - if: - properties: - compatible: - contains: - enum: - - nvidia,tegra194-gte-lic - then: - properties: - nvidia,slices: - const: 11 - - - if: - properties: - compatible: - contains: - enum: - - nvidia,tegra234-gte-lic - then: - properties: - nvidia,slices: - const: 17 - required: - compatible - reg - interrupts - - nvidia,slices - "#timestamp-cells" additionalProperties: false @@ -107,7 +74,6 @@ examples: reg = <0xc1e0000 0x10000>; interrupts = <0 13 0x4>; nvidia,int-threshold = <1>; - nvidia,slices = <3>; #timestamp-cells = <1>; }; @@ -117,7 +83,6 @@ examples: reg = <0x3aa0000 0x10000>; interrupts = <0 11 0x4>; nvidia,int-threshold = <1>; - nvidia,slices = <11>; #timestamp-cells = <1>; }; From patchwork Thu Mar 23 01:29:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dipen Patel X-Patchwork-Id: 73739 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:604a:0:0:0:0:0 with SMTP id j10csp2664090wrt; Wed, 22 Mar 2023 18:31:14 -0700 (PDT) X-Google-Smtp-Source: AK7set+qi0fSz8tETPbPH0jMnqB7Ti0cMDI+VJXxamrcrjGvBY2UUssaEbI6FL0czASxQmNdK4rS X-Received: by 2002:a17:906:698d:b0:930:28d6:4581 with SMTP id i13-20020a170906698d00b0093028d64581mr8697361ejr.59.1679535073992; Wed, 22 Mar 2023 18:31:13 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1679535073; cv=pass; d=google.com; s=arc-20160816; b=QKWhBxilAwNHUDCnqXbZIWHDvhq8J4JeBDCqkeq8pvsM2yQFoOXj9jZk+EffhIcwA6 Ft/E6qxN7t2Lr9KwHrRPiykP0/zXzDJZxeaAd8kjf91I00KffRCSAJtnNKuUUDAdK3F+ Yk6U+2SzPnwoewE09xh7TBTyDL1M3CvpV5gH30aNbvfl72gl7cia6QWW4kbjrZn7zIdu pMiPWfLDiskmmqNoc3v7qN/gwr140/PdwtjK0Im4k9LmNI1fI9nonWWFiOM7pVcgntFC xuOl10GZ2RARRzGEIPpSRNMPucghAIXZk2spPSNhdmavLrNRhEEgSctl3BXpHYaoHfwK 3WSQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=aRSrneVwlnQEB9m06wEPIjU9TDyL1SRZmKcYT9YP7UM=; b=uPwD2oTXU4j3N6AUXHKwk3Hv10Cg1bmdXK6SnnTpQLtoJkulRie6WGsQHSHua2dL/F AJKRH+NDKDU5S9S1Og2AcvbMCVLrBdRHd/RYGHC8Tv/3TLNL9ofbZUo6oOfQXoTLoDTp ezT1n/7mAdVTEszv7mwcW6qlFNhHaC3vw1x28cuYBU62QsfTBerYlgakab3v2GVx41Yv zp0kT38L82SbFGh2RiB8N1sr3nQRqfvwaHq2a3JohE36rh6jqzQxBfmDdoDo0dm/l31R xu9rf4LJ/NfQk4BWycvWeHSlapWMRKacmuMu2ed/5+avd3Qaw9uaypFZuDZXOh9m87CZ x4ZQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b=USwU3gFr; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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This is done to help below case. Without this property code would look like: if (of_device_is_compatible(dev->of_node, "nvidia,tegra194-gte-aon")) hte_dev->c = gpiochip_find("tegra194-gpio-aon", tegra_get_gpiochip_from_name); else if (of_device_is_compatible(dev->of_node, "nvidia,tegra234-gte-aon")) hte_dev->c = gpiochip_find("tegra234-gpio-aon", tegra_get_gpiochip_from_name); else return -ENODEV; This means for every future addition of the compatible string, if else condition statements have to be expanded. With the property: gpio_ctrl = of_parse_phandle(dev->of_node, "nvidia,gpio-controller", 0); .... hte_dev->c = gpiochip_find(gpio_ctrl, tegra_get_gpiochip_from_of_node); This simplifies the code significantly. The introdunction of this property/binding does not break existing Tegra194 provider driver. Signed-off-by: Dipen Patel Reviewed-by: Linus Walleij --- .../timestamp/nvidia,tegra194-hte.yaml | 31 +++++++++++++++++-- 1 file changed, 29 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/timestamp/nvidia,tegra194-hte.yaml b/Documentation/devicetree/bindings/timestamp/nvidia,tegra194-hte.yaml index eafc33e9ae2e..841273a3d8ae 100644 --- a/Documentation/devicetree/bindings/timestamp/nvidia,tegra194-hte.yaml +++ b/Documentation/devicetree/bindings/timestamp/nvidia,tegra194-hte.yaml @@ -51,6 +51,12 @@ properties: LIC instance has 11 slices and Tegra234 LIC has 17 slices. enum: [3, 11, 17] + nvidia,gpio-controller: + $ref: /schemas/types.yaml#/definitions/phandle + description: + The phandle to AON gpio controller instance. This is required to handle + namespace conversion between GPIO and GTE. + '#timestamp-cells': description: This represents number of line id arguments as specified by the @@ -65,22 +71,43 @@ required: - interrupts - "#timestamp-cells" +allOf: + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra234-gte-aon + then: + required: + - nvidia,gpio-controller + additionalProperties: false examples: - | tegra_hte_aon: timestamp@c1e0000 { compatible = "nvidia,tegra194-gte-aon"; - reg = <0xc1e0000 0x10000>; + reg = <0x0 0xc1e0000 0x0 0x10000>; + interrupts = <0 13 0x4>; + nvidia,int-threshold = <1>; + #timestamp-cells = <1>; + }; + + - | + tegra234_hte_aon: timestamp@c1e0000 { + compatible = "nvidia,tegra234-gte-aon"; + reg = <0x0 0xc1e0000 0x0 0x10000>; interrupts = <0 13 0x4>; nvidia,int-threshold = <1>; + nvidia,gpio-controller = <&gpio_aon>; #timestamp-cells = <1>; }; - | tegra_hte_lic: timestamp@3aa0000 { compatible = "nvidia,tegra194-gte-lic"; - reg = <0x3aa0000 0x10000>; + reg = <0x0 0x3aa0000 0x0 0x10000>; interrupts = <0 11 0x4>; nvidia,int-threshold = <1>; #timestamp-cells = <1>; From patchwork Thu Mar 23 01:29:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dipen Patel X-Patchwork-Id: 73736 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:604a:0:0:0:0:0 with SMTP id j10csp2664010wrt; Wed, 22 Mar 2023 18:31:00 -0700 (PDT) X-Google-Smtp-Source: AK7set81iEfMqY8iKxqgmrg2g0H4XOqoJzlMeVyt+wQvXSHHaEjz3wWZwzNj4viwhUV6QztEWpes X-Received: by 2002:aa7:c405:0:b0:4fa:2363:6806 with SMTP id j5-20020aa7c405000000b004fa23636806mr3673141edq.17.1679535060548; Wed, 22 Mar 2023 18:31:00 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1679535060; cv=pass; d=google.com; s=arc-20160816; b=dKQfMOYHzFM3RZGvsUBOaq1W41UYy3NS468WLSJsaxVIhpxrrIeDCsJvq9+8nnxw23 Ds3tBvgGJXhCrqJbifj4vH3kQKsmF8x57bBAK5aJhG6qApu6cNONbAFv/BWlHFZqnpRp UR4NjES6fhWujPyEYFo1JftNYsg9y0sicH6f5RNGGvIhhGtwsSUMlVDXmbRJgiWFpNHW UyIc27vWlCxkI6WsVwmQjX71L/Ue35Pva2qLS16cimBSsRzBu+9F2wILelLN6pJuCPTu Ol/+kTPoxL7hv3/mKubPjNEy89Vp/XMxsm7MKsOtf+q8fKItvasDAdR4o4uIqCemLD5v Vsrg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=Kx/kpYZ7ir9/y4hkhUOBaWiXie83l6Pngi0Gj/5GgOI=; b=BFnmVxSWfgOHjgv8LiUmTZFoMsbkgzL2946uQZ0T+v5HF96dXbmHC7SYrbEdq9JgG0 dz6ZwZgUU5Ku40wSVguCZ3mPtFoMCNbA+e8sQav/rhqTawvKu8AgpKsDCi2up1xCZue3 I8iROpwx/MfvUSqQyW4qMS7TMINOebr9TwTwajNmmJr/pWZPV2KvnZb0fX63CrIkoMy5 CclGAqDsSarm0DFccivsYvrmACoUj3+6S3pmigxUF/RKtwaxVKp4LmoOE+iXuH65VEJH X+rgACcxlQ77tyAN3tvYQKrLM1bc+PEikiwQ20Hj74DskDCNmdBqvwM3B5paPY5qU1S1 4ShQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b=UVoCIesJ; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Dipen Patel --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 8fe8eda7654d..54790c6b6a2c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -1156,6 +1156,14 @@ clock-names = "fuse"; }; + hte_lic: hardware-timestamp@3aa0000 { + compatible = "nvidia,tegra234-gte-lic"; + reg = <0x0 0x3aa0000 0x0 0x10000>; + interrupts = ; + nvidia,int-threshold = <1>; + #timestamp-cells = <1>; + }; + hsp_top0: hsp@3c00000 { compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; reg = <0x0 0x03c00000 0x0 0xa0000>; @@ -1673,6 +1681,15 @@ #mbox-cells = <2>; }; + hte_aon: hardware-timestamp@c1e0000 { + compatible = "nvidia,tegra234-gte-aon"; + reg = <0x0 0xc1e0000 0x0 0x10000>; + interrupts = ; + nvidia,int-threshold = <1>; + nvidia,gpio-controller = <&gpio_aon>; + #timestamp-cells = <1>; + }; + gen2_i2c: i2c@c240000 { compatible = "nvidia,tegra194-i2c"; reg = <0x0 0xc240000 0x0 0x100>; From patchwork Thu Mar 23 01:29:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dipen Patel X-Patchwork-Id: 73740 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:604a:0:0:0:0:0 with SMTP id j10csp2664181wrt; Wed, 22 Mar 2023 18:31:32 -0700 (PDT) X-Google-Smtp-Source: AK7set+xkynArXws7+aljRgKRtbDl+gzS25sbDQAMdr+nqws3m0+CCwNKavlA03miiqxB3c6JYk3 X-Received: by 2002:a17:906:7054:b0:932:4eea:17ce with SMTP id r20-20020a170906705400b009324eea17cemr9038883ejj.39.1679535092111; Wed, 22 Mar 2023 18:31:32 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1679535092; cv=pass; d=google.com; s=arc-20160816; b=P72x3iPk6ySOznikOKoB7yU1GtS8tgC9emnahC6quNzcLtr1F7tWsdtCoK12Q/OWLC 5uq0sdHWOUzvJ6AoNCO5e+Sioi3AfObYacV/HfcymtLJFI0/RacRTHT7PvTGHUpgjTmj HmvvAKEcudO3HmC/ZZv6pMDBrTtku/mPf8ID+8G50eenB2lLpLclWCFmPrP4jqMF8nto FUV0PLoaQt2bIl8XHGJHsRYPpfFnNzoylb5sK+qt2IDUEIPaX79mlBTRmZ343uqc2enC 1TVbvVMVdTlosPLv3zPCcTV7Qpoqhylocs6pCy1rWJkYSKYoC8KFrRZOICLp4f7/QvXz OBBQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=GjbHZfAEXm7Tpt9u32Vn9q9T4Up+3nN7WFwlqHYtLGs=; b=guk1STGP/Cb87MW8HnrJA6taAaaZYJpvhjWyVCtKK9lJSo8V5Q4EsBa7bbr8dgpXL/ 9T2+F/CwEYB1WdnmsvmQE4L5U2PXrmrOuMQKYf4A8BBrqz+OstDROtYntSJJZXPkXijl uWSU1M4xzss4hM+G1w7grOQEWNwcacVYghWRg28/NTKdvJvyhSKuJaCbrkeNKNwNtGjd dVeC947dzc31F1GyyPxmQz1t5n3MPXCusI4MvVSqTgrIgUNwzgJL9U/EIDltyG2rgtNv NLg84RlnE1UtNBycmaV9sOCNW/cDTUChGZPNB0v6Mr7clrrG62hEkyBksEQxMu5SdKy1 2NQg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b="m6OC/xZs"; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Dipen Patel Reviewed-by: Bagas Sanjaya --- Documentation/driver-api/hte/tegra194-hte.rst | 33 +++++++++---------- 1 file changed, 16 insertions(+), 17 deletions(-) diff --git a/Documentation/driver-api/hte/tegra194-hte.rst b/Documentation/driver-api/hte/tegra194-hte.rst index f2d617265546..85e654772782 100644 --- a/Documentation/driver-api/hte/tegra194-hte.rst +++ b/Documentation/driver-api/hte/tegra194-hte.rst @@ -5,25 +5,25 @@ HTE Kernel provider driver Description ----------- -The Nvidia tegra194 HTE provider driver implements two GTE -(Generic Timestamping Engine) instances: 1) GPIO GTE and 2) LIC -(Legacy Interrupt Controller) IRQ GTE. Both GTE instances get the -timestamp from the system counter TSC which has 31.25MHz clock rate, and the -driver converts clock tick rate to nanoseconds before storing it as timestamp -value. +The Nvidia tegra HTE provider also known as GTE (Generic Timestamping Engine) +driver implements two GTE instances: 1) GPIO GTE and 2) LIC +(Legacy Interrupt Controller) IRQ GTE. Both GTE instances get the timestamp +from the system counter TSC which has 31.25MHz clock rate, and the driver +converts clock tick rate to nanoseconds before storing it as timestamp value. GPIO GTE -------- This GTE instance timestamps GPIO in real time. For that to happen GPIO -needs to be configured as input. The always on (AON) GPIO controller instance -supports timestamping GPIOs in real time and it has 39 GPIO lines. The GPIO GTE -and AON GPIO controller are tightly coupled as it requires very specific bits -to be set in GPIO config register before GPIO GTE can be used, for that GPIOLIB -adds two optional APIs as below. The GPIO GTE code supports both kernel -and userspace consumers. The kernel space consumers can directly talk to HTE -subsystem while userspace consumers timestamp requests go through GPIOLIB CDEV -framework to HTE subsystem. +needs to be configured as input. Only the always on (AON) GPIO controller +instance supports timestamping GPIOs in real time as it is tightly coupled with +the GPIO GTE. To support this, GPIOLIB adds two optional APIs as mentioned +below. The GPIO GTE code supports both kernel and userspace consumers. The +kernel space consumers can directly talk to HTE subsystem while userspace +consumers timestamp requests go through GPIOLIB CDEV framework to HTE +subsystem. The hte devicetree binding described at +``Documentation/devicetree/bindings/timestamp`` provides an example of how a +consumer can request an GPIO line. See gpiod_enable_hw_timestamp_ns() and gpiod_disable_hw_timestamp_ns(). @@ -34,9 +34,8 @@ returns the timestamp in nanoseconds. LIC (Legacy Interrupt Controller) IRQ GTE ----------------------------------------- -This GTE instance timestamps LIC IRQ lines in real time. There are 352 IRQ -lines which this instance can add timestamps to in real time. The hte -devicetree binding described at ``Documentation/devicetree/bindings/timestamp`` +This GTE instance timestamps LIC IRQ lines in real time. The hte devicetree +binding described at ``Documentation/devicetree/bindings/timestamp`` provides an example of how a consumer can request an IRQ line. Since it is a one-to-one mapping with IRQ GTE provider, consumers can simply specify the IRQ number that they are interested in. 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Mar 2023 01:29:43.0442 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 76d690f1-f477-49d5-9299-08db2b3e1450 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT096.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7512 X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761120165812357005?= X-GMAIL-MSGID: =?utf-8?q?1761120165812357005?= The Tegra234 AON GPIO instance and LIC IRQ support HTE. For the GPIO HTE support, it also requires to add mapping between GPIO and HTE framework same as it was done with Tegra194 SoC. Signed-off-by: Dipen Patel --- v2: - Changed how gpio_chip could be aquired for the mapping v3: - Renamed gpio_chip matching function - Used of_node to fwnode field in gpio_chip matching function as data as gpio_chip struct does not have of_node member anymore. v4: - Logically divide the original v3 patch as follows - Created this Tegra234 support patch - Created deprecated nvidia,slices patch - Created handle nvidia,gpio-controller patch drivers/hte/hte-tegra194-test.c | 2 +- drivers/hte/hte-tegra194.c | 124 ++++++++++++++++++++++++++++++-- 2 files changed, 121 insertions(+), 5 deletions(-) diff --git a/drivers/hte/hte-tegra194-test.c b/drivers/hte/hte-tegra194-test.c index 5d776a185bd6..d79c28a80517 100644 --- a/drivers/hte/hte-tegra194-test.c +++ b/drivers/hte/hte-tegra194-test.c @@ -16,7 +16,7 @@ #include /* - * This sample HTE GPIO test driver demonstrates HTE API usage by enabling + * This sample HTE test driver demonstrates HTE API usage by enabling * hardware timestamp on gpio_in and specified LIC IRQ lines. * * Note: gpio_out and gpio_in need to be shorted externally in order for this diff --git a/drivers/hte/hte-tegra194.c b/drivers/hte/hte-tegra194.c index 49a27af22742..5d1f947db0f6 100644 --- a/drivers/hte/hte-tegra194.c +++ b/drivers/hte/hte-tegra194.c @@ -62,6 +62,10 @@ #define NV_AON_HTE_SLICE2_IRQ_GPIO_25 25 #define NV_AON_HTE_SLICE2_IRQ_GPIO_26 26 #define NV_AON_HTE_SLICE2_IRQ_GPIO_27 27 +#define NV_AON_HTE_SLICE2_IRQ_GPIO_28 28 +#define NV_AON_HTE_SLICE2_IRQ_GPIO_29 29 +#define NV_AON_HTE_SLICE2_IRQ_GPIO_30 30 +#define NV_AON_HTE_SLICE2_IRQ_GPIO_31 31 #define HTE_TECTRL 0x0 #define HTE_TETSCH 0x4 @@ -220,7 +224,100 @@ static const struct tegra_hte_line_mapped tegra194_aon_gpio_sec_map[] = { [39] = {NV_AON_SLICE_INVALID, 0}, }; -static const struct tegra_hte_data aon_hte = { +static const struct tegra_hte_line_mapped tegra234_aon_gpio_map[] = { + /* gpio, slice, bit_index */ + /* AA port */ + [0] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_11}, + [1] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_10}, + [2] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_9}, + [3] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_8}, + [4] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_7}, + [5] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_6}, + [6] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_5}, + [7] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_4}, + /* BB port */ + [8] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_3}, + [9] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_2}, + [10] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_1}, + [11] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_0}, + /* CC port */ + [12] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_22}, + [13] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_21}, + [14] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_20}, + [15] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_19}, + [16] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_18}, + [17] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_17}, + [18] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_16}, + [19] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_15}, + /* DD port */ + [20] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_14}, + [21] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_13}, + [22] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_12}, + /* EE port */ + [23] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_31}, + [24] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_30}, + [25] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_29}, + [26] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_28}, + [27] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_27}, + [28] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_26}, + [29] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_25}, + [30] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_24}, + /* GG port */ + [31] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_23}, +}; + +static const struct tegra_hte_line_mapped tegra234_aon_gpio_sec_map[] = { + /* gpio, slice, bit_index */ + /* AA port */ + [0] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_11}, + [1] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_10}, + [2] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_9}, + [3] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_8}, + [4] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_7}, + [5] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_6}, + [6] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_5}, + [7] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_4}, + /* BB port */ + [8] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_3}, + [9] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_2}, + [10] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_1}, + [11] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_0}, + [12] = {NV_AON_SLICE_INVALID, 0}, + [13] = {NV_AON_SLICE_INVALID, 0}, + [14] = {NV_AON_SLICE_INVALID, 0}, + [15] = {NV_AON_SLICE_INVALID, 0}, + /* CC port */ + [16] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_22}, + [17] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_21}, + [18] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_20}, + [19] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_19}, + [20] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_18}, + [21] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_17}, + [22] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_16}, + [23] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_15}, + /* DD port */ + [24] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_14}, + [25] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_13}, + [26] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_12}, + [27] = {NV_AON_SLICE_INVALID, 0}, + [28] = {NV_AON_SLICE_INVALID, 0}, + [29] = {NV_AON_SLICE_INVALID, 0}, + [30] = {NV_AON_SLICE_INVALID, 0}, + [31] = {NV_AON_SLICE_INVALID, 0}, + /* EE port */ + [32] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_31}, + [33] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_30}, + [34] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_29}, + [35] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_28}, + [36] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_27}, + [37] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_26}, + [38] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_25}, + [39] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_24}, + /* GG port */ + [40] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_23}, +}; + +static const struct tegra_hte_data t194_aon_hte = { .map_sz = ARRAY_SIZE(tegra194_aon_gpio_map), .map = tegra194_aon_gpio_map, .sec_map_sz = ARRAY_SIZE(tegra194_aon_gpio_sec_map), @@ -228,6 +325,14 @@ static const struct tegra_hte_data aon_hte = { .type = HTE_TEGRA_TYPE_GPIO, }; +static const struct tegra_hte_data t234_aon_hte = { + .map_sz = ARRAY_SIZE(tegra234_aon_gpio_map), + .map = tegra234_aon_gpio_map, + .sec_map_sz = ARRAY_SIZE(tegra234_aon_gpio_sec_map), + .sec_map = tegra234_aon_gpio_sec_map, + .type = HTE_TEGRA_TYPE_GPIO, +}; + static const struct tegra_hte_data lic_hte = { .map_sz = 0, .map = NULL, @@ -535,7 +640,9 @@ static bool tegra_hte_match_from_linedata(const struct hte_chip *chip, static const struct of_device_id tegra_hte_of_match[] = { { .compatible = "nvidia,tegra194-gte-lic", .data = &lic_hte}, - { .compatible = "nvidia,tegra194-gte-aon", .data = &aon_hte}, + { .compatible = "nvidia,tegra194-gte-aon", .data = &t194_aon_hte}, + { .compatible = "nvidia,tegra234-gte-lic", .data = &lic_hte}, + { .compatible = "nvidia,tegra234-gte-aon", .data = &t234_aon_hte}, { } }; MODULE_DEVICE_TABLE(of, tegra_hte_of_match); @@ -635,8 +742,17 @@ static int tegra_hte_probe(struct platform_device *pdev) gc->match_from_linedata = tegra_hte_match_from_linedata; - hte_dev->c = gpiochip_find("tegra194-gpio-aon", - tegra_get_gpiochip_from_name); + if (of_device_is_compatible(dev->of_node, + "nvidia,tegra194-gte-aon")) + hte_dev->c = gpiochip_find("tegra194-gpio-aon", + tegra_get_gpiochip_from_name); + else if (of_device_is_compatible(dev->of_node, + "nvidia,tegra234-gte-aon")) + hte_dev->c = gpiochip_find("tegra234-gpio-aon", + tegra_get_gpiochip_from_name); + else + return -ENODEV; + if (!hte_dev->c) return dev_err_probe(dev, -EPROBE_DEFER, "wait for gpio controller\n"); From patchwork Thu Mar 23 01:29:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dipen Patel X-Patchwork-Id: 73742 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:604a:0:0:0:0:0 with SMTP id j10csp2664823wrt; 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Signed-off-by: Dipen Patel --- drivers/hte/hte-tegra194.c | 31 +++++++++++++++++++++---------- 1 file changed, 21 insertions(+), 10 deletions(-) diff --git a/drivers/hte/hte-tegra194.c b/drivers/hte/hte-tegra194.c index 5d1f947db0f6..945c68c5e476 100644 --- a/drivers/hte/hte-tegra194.c +++ b/drivers/hte/hte-tegra194.c @@ -118,6 +118,7 @@ struct tegra_hte_line_data { struct tegra_hte_data { enum tegra_hte_type type; + u32 slices; u32 map_sz; u32 sec_map_sz; const struct tegra_hte_line_mapped *map; @@ -323,6 +324,7 @@ static const struct tegra_hte_data t194_aon_hte = { .sec_map_sz = ARRAY_SIZE(tegra194_aon_gpio_sec_map), .sec_map = tegra194_aon_gpio_sec_map, .type = HTE_TEGRA_TYPE_GPIO, + .slices = 3, }; static const struct tegra_hte_data t234_aon_hte = { @@ -331,12 +333,21 @@ static const struct tegra_hte_data t234_aon_hte = { .sec_map_sz = ARRAY_SIZE(tegra234_aon_gpio_sec_map), .sec_map = tegra234_aon_gpio_sec_map, .type = HTE_TEGRA_TYPE_GPIO, + .slices = 3, }; -static const struct tegra_hte_data lic_hte = { +static const struct tegra_hte_data t194_lic_hte = { .map_sz = 0, .map = NULL, .type = HTE_TEGRA_TYPE_LIC, + .slices = 11, +}; + +static const struct tegra_hte_data t234_lic_hte = { + .map_sz = 0, + .map = NULL, + .type = HTE_TEGRA_TYPE_LIC, + .slices = 17, }; static inline u32 tegra_hte_readl(struct tegra_hte_soc *hte, u32 reg) @@ -639,9 +650,9 @@ static bool tegra_hte_match_from_linedata(const struct hte_chip *chip, } static const struct of_device_id tegra_hte_of_match[] = { - { .compatible = "nvidia,tegra194-gte-lic", .data = &lic_hte}, + { .compatible = "nvidia,tegra194-gte-lic", .data = &t194_lic_hte}, { .compatible = "nvidia,tegra194-gte-aon", .data = &t194_aon_hte}, - { .compatible = "nvidia,tegra234-gte-lic", .data = &lic_hte}, + { .compatible = "nvidia,tegra234-gte-lic", .data = &t234_lic_hte}, { .compatible = "nvidia,tegra234-gte-aon", .data = &t234_aon_hte}, { } }; @@ -679,13 +690,6 @@ static int tegra_hte_probe(struct platform_device *pdev) dev = &pdev->dev; - ret = of_property_read_u32(dev->of_node, "nvidia,slices", &slices); - if (ret != 0) { - dev_err(dev, "Could not read slices\n"); - return -EINVAL; - } - nlines = slices << 5; - hte_dev = devm_kzalloc(dev, sizeof(*hte_dev), GFP_KERNEL); if (!hte_dev) return -ENOMEM; @@ -697,6 +701,13 @@ static int tegra_hte_probe(struct platform_device *pdev) dev_set_drvdata(&pdev->dev, hte_dev); hte_dev->prov_data = of_device_get_match_data(&pdev->dev); + ret = of_property_read_u32(dev->of_node, "nvidia,slices", &slices); + if (ret != 0) + slices = hte_dev->prov_data->slices; + + dev_dbg(dev, "slices:%d\n", slices); + nlines = slices << 5; + hte_dev->regs = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(hte_dev->regs)) return PTR_ERR(hte_dev->regs); From patchwork Thu Mar 23 01:29:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dipen Patel X-Patchwork-Id: 73741 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:604a:0:0:0:0:0 with SMTP id j10csp2664506wrt; Wed, 22 Mar 2023 18:32:33 -0700 (PDT) X-Google-Smtp-Source: AK7set+l8MLM0MIVGaE3sdAcA0jgNGFmHqwW7wDg0JOUtS2gcgiTEUf4FugCcE+xs/+EDxDMSKoW X-Received: by 2002:a17:906:3999:b0:933:3705:a9f0 with SMTP id h25-20020a170906399900b009333705a9f0mr9606919eje.19.1679535153559; Wed, 22 Mar 2023 18:32:33 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1679535153; cv=pass; d=google.com; s=arc-20160816; b=YCID/zu8YpShFe48PRUnGt5+4iWM8HD3UBcOsJYEpVEHthgAxEqtc9jsCf+Ee3LNtP q7UpDsiaZqnndPJ+PR7JOuJLsLT7E44FXxMR5v0mhyLqGRpoaXLJ3MA69xXTsT9ZcmiK /QC1USjyovJTojyFESa1s86SmYYS3d+XoARqZxTHn1CcBwgCOMp5D7tud0OgNVXlhH3k GorOFzA0j9ivePGukiYDEq3sRG86Zvu5S9EX93m2E4hxRJ7a+ik52q6ntT/JAN63/rm2 VB++eKxl4Cw+UpiOa/WyRnsN2RoH79IEXyICed1CO+WR4CaohvKKI75X8bryPmbs40AY PgYg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=84187s+87Zv9eZPlcalYEMwzk96EgU1bcgE72lqR3go=; b=J06ogJMsh6XkKlQE1N4YrNTmtf4AeitAov7tc2kkJmaV6AO/mmO0lcjnzdQbB50rIw JQ3Lhn/+mAR7FMaHNgLACgvOEXRHEv0iszRzQixRgstttI4Zjs3Uq7AA4OlWd2vAZhqY m0oX5BFxUSMb/KC0WKnc0NlH4P3ztm4rIqFKWgIwntm/9UCZWnoo7IRyf63EEsugXHTU bN2fJoI0V64pAtXU/+qVLOVPl4g/XIvOZB7usImNhgiaRhl1naG3fbmZurNS9QIMdCK7 d76OW/iSEIabB/M/hlWW7yu5cWGqAWRuYK9Eex0a/cVgx/iE6Bvw3hWqiB1aA1MgKdkm hWcQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b=aOjAv1XL; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Mar 2023 01:29:47.1164 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e5eb480c-76b6-4f62-dc03-08db2b3e16c9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT037.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4917 X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761120252979205589?= X-GMAIL-MSGID: =?utf-8?q?1761120252979205589?= The dt binding adds nvidia,gpio-controller property from Tegra234 SoC onwards to simplify code handling gpio chip search. The gpio chip search is needed for the AON GPIO GTE instances to map the hardware timestamp GPIO request (coming from the GPIO framework) to the tegra HTE providers. The patch also adds new gpio chip match function to match from the fwnode instead of the gpio controller label. The addition of the property does not break ABI for the existing Tegra194 code. Signed-off-by: Dipen Patel Reviewed-by: Linus Walleij --- drivers/hte/hte-tegra194.c | 28 +++++++++++++++++++++------- 1 file changed, 21 insertions(+), 7 deletions(-) diff --git a/drivers/hte/hte-tegra194.c b/drivers/hte/hte-tegra194.c index 945c68c5e476..2c485ff5be22 100644 --- a/drivers/hte/hte-tegra194.c +++ b/drivers/hte/hte-tegra194.c @@ -679,6 +679,11 @@ static int tegra_get_gpiochip_from_name(struct gpio_chip *chip, void *data) return !strcmp(chip->label, data); } +static int tegra_gpiochip_match(struct gpio_chip *chip, void *data) +{ + return chip->fwnode == of_node_to_fwnode(data); +} + static int tegra_hte_probe(struct platform_device *pdev) { int ret; @@ -687,6 +692,7 @@ static int tegra_hte_probe(struct platform_device *pdev) struct device *dev; struct tegra_hte_soc *hte_dev; struct hte_chip *gc; + struct device_node *gpio_ctrl; dev = &pdev->dev; @@ -754,15 +760,23 @@ static int tegra_hte_probe(struct platform_device *pdev) gc->match_from_linedata = tegra_hte_match_from_linedata; if (of_device_is_compatible(dev->of_node, - "nvidia,tegra194-gte-aon")) + "nvidia,tegra194-gte-aon")) { hte_dev->c = gpiochip_find("tegra194-gpio-aon", tegra_get_gpiochip_from_name); - else if (of_device_is_compatible(dev->of_node, - "nvidia,tegra234-gte-aon")) - hte_dev->c = gpiochip_find("tegra234-gpio-aon", - tegra_get_gpiochip_from_name); - else - return -ENODEV; + } else { + gpio_ctrl = of_parse_phandle(dev->of_node, + "nvidia,gpio-controller", + 0); + if (!gpio_ctrl) { + dev_err(dev, + "gpio controller node not found\n"); + return -ENODEV; + } + + hte_dev->c = gpiochip_find(gpio_ctrl, + tegra_gpiochip_match); + of_node_put(gpio_ctrl); + } if (!hte_dev->c) return dev_err_probe(dev, -EPROBE_DEFER, From patchwork Thu Mar 23 01:29:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dipen Patel X-Patchwork-Id: 73743 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:604a:0:0:0:0:0 with SMTP id j10csp2665090wrt; Wed, 22 Mar 2023 18:34:43 -0700 (PDT) X-Google-Smtp-Source: AK7set8bxfQDEo9M37WLQgUVAitodct9o/f39TEu4wfZ40n2h0hX/lwPYLbE0pV7PhabwJp2Q/BA X-Received: by 2002:a17:902:f90b:b0:19c:a9b8:4349 with SMTP id kw11-20020a170902f90b00b0019ca9b84349mr3807343plb.32.1679535283333; Wed, 22 Mar 2023 18:34:43 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1679535283; cv=pass; d=google.com; s=arc-20160816; b=hW4FH+HePsHRidgz58rlVUtBfbBsONZspKoEQkuMK3xGN9Ka5adbINeJTcG4sNtqYG CAcM9FrESQLArld0Xqc1ChO6WysUxnKnxMaEfmiF9e67YhBJG5SezGs0ea//2xsWNLPJ 3NM05pYlsnylHhnhcWzj+K2BKjO3NW0/PNYBPFCgxXW01GOBpX8Njx+UyaCxeonDbChm Oc/UC3I0zTYGkf0KFH7RkzrIWkq/FZ7vUZatCCOvYufk5oFRfy6R2OsAqVvO1cxkKl1b kE/r2knullrj1b5t44KxJxQUvqr3YGGtpf4vx0AtCMtRYOr3kPk2Lx7HGHPeseiae7O5 xqVg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=JP0U9I3hrgeSkY3oFuGo2+HNIsfA/g22/zH1rbrIPQ0=; b=b6rV6fD5LkiW1Q2Y9uKKQz51xlJu5QBSORJPgawhOK2Q2OfwIWLlmdDhSTwG1PMdjk SCIEgOwEgE4i0rFC/bXY9tytiChLKqYib+SoHSRfx5tjKZp5oU5dgn7mgm53fwKg7/gU ZvAaqW9q1GBHS2NvQwvE29CgIkuRRWCIHkegIo8uV7fA8+pNwCtkeBrY2XNlQgkavsKk +OAPTbJrMwIYzz7gEfjy+gySHOUuu6yFel7OYARwWYJhiUb5trPSvDkhlg8AfvN6al0+ z4Vqtg6lHyBV4vWE6YldO1u8AYsDWHrgBawYyM1Bb9Kkz8k9t08PRwOiD/2bqNQ+YVG+ o9MA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b=RP3KtSzo; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Dipen Patel Acked-by: Thierry Reding Acked-by: Bartosz Golaszewski Reviewed-by: Linus Walleij --- drivers/gpio/gpio-tegra186.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpio/gpio-tegra186.c b/drivers/gpio/gpio-tegra186.c index 14c872b6ad05..b904de0b1784 100644 --- a/drivers/gpio/gpio-tegra186.c +++ b/drivers/gpio/gpio-tegra186.c @@ -1134,6 +1134,7 @@ static const struct tegra_gpio_soc tegra234_aon_soc = { .name = "tegra234-gpio-aon", .instance = 1, .num_irqs_per_bank = 8, + .has_gte = true, }; #define TEGRA241_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \