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Wed, 22 Mar 2023 19:07:27 -0500 From: Brad Larson To: CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v12 01/15] dt-bindings: arm: add AMD Pensando boards Date: Wed, 22 Mar 2023 17:06:43 -0700 Message-ID: <20230323000657.28664-2-blarson@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230323000657.28664-1-blarson@amd.com> References: <20230323000657.28664-1-blarson@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT088:EE_|PH7PR12MB6490:EE_ X-MS-Office365-Filtering-Correlation-Id: 6f5eca73-086d-452f-ee4c-08db2b329880 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: HuPtHtlvdRCSlVOoYN4EIt44rdluCCX2Kc+ejsL/+J4NrEaY6h1G/P/wwNMMU4UrPxwXLcgvm2wLRAT9dbcXLNR0EOaCpjrKw25F7NH055b7kKK6HWUSvUneUYUJ9fbL7uaK8QLeZQyLEqel9n4akX54DLC9DZX5AcRiqOVnrkE8oWMCXxENAmEkgMXZTq6oCZmoMJpzjq4RBpNIpyYGXigMNL83uw9nPSxeoFK5eedn0JduntzqbmfGwbqdMjbW5felNoRYY9rMTa2CjrALqnlDgSNVlG6W/AFD7H+D1BCkTM502Gdm2gNS/8bPPOpWBQ99gmEWHQYZI7rfHi1pWh6QuhRvt5/NzuzGEbBa5CEATbvAs5zpTEleI9fvmIQjZVPURZbICsqZV9eqjHYfMorPFculXbZHwMu73dSSfALHXhGVtbJCxVaKdk7YZhm1KQ8zcB4QUM4k1Lsor89FVm9rPBOmX+43ZlsjQaaoHXngipN92ARpXO2YnlW+FG82BaorCJg9YmYBwG1uVNNN/JB2lymvj/xDu41OJzTgTp5lgJkdqLKNCEHuGETJJLm4nfpruy6Bl3GUDhWvmIdz3PWUQM+D+OC6nt4KD7n8VqoqNpgktvFqeCm30W7aBa3c9+J72GRR5XEdPqSvTvz8kKyiGSAv1w80omNJTHDXwfh+d4kXr6UHLlB6jcJEwTsrBKy51egh928a9Swztpd26l3Vdbkts/SB3Qes49InO4Mb2E1v4G4rgjM9ORR36q8w8pCeutC+2c6IqMgc32Z9bQ== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230025)(4636009)(396003)(346002)(136003)(39860400002)(376002)(451199018)(46966006)(36840700001)(40470700004)(966005)(36860700001)(1076003)(81166007)(47076005)(26005)(82310400005)(6666004)(36756003)(336012)(426003)(41300700001)(82740400003)(16526019)(186003)(356005)(40480700001)(2616005)(40460700003)(2906002)(316002)(6916009)(8676002)(70206006)(70586007)(5660300002)(7416002)(7406005)(8936002)(478600001)(4326008)(54906003)(36900700001);DIR:OUT;SFP:1101; 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Signed-off-by: Brad Larson Reviewed-by: Rob Herring --- .../devicetree/bindings/arm/amd,pensando.yaml | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/amd,pensando.yaml diff --git a/Documentation/devicetree/bindings/arm/amd,pensando.yaml b/Documentation/devicetree/bindings/arm/amd,pensando.yaml new file mode 100644 index 000000000000..e5c2591834a8 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/amd,pensando.yaml @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/amd,pensando.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: AMD Pensando SoC Platforms + +maintainers: + - Brad Larson + +properties: + $nodename: + const: "/" + compatible: + oneOf: + + - description: Boards with Pensando Elba SoC + items: + - enum: + - amd,pensando-elba-ortano + - const: amd,pensando-elba + +additionalProperties: true + +... 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Signed-off-by: Brad Larson Reviewed-by: Krzysztof Kozlowski --- v12_changes: - Drop 'resets: false' in the amd,pensando-elba-sd4hc else properties. Passed dtbs_check and dt_binding_check with both versions. v11 changes: - Remove resets description and reset-names - Add descriptions for amd,pensando-elba-sd4hc reg items v10 changes: - Move reset-names property definition next to existing resets prop - Move allOf to the bottom and set resets/reset-names required only for pensando - Fix reg maxItems for existing, must be 1 v9 changes: - Add reset-names and resets properties - Add if/then on property amd,pensando-elba-sd4hc to set reg property values for minItems and maxItems --- .../devicetree/bindings/mmc/cdns,sdhci.yaml | 27 ++++++++++++++++--- 1 file changed, 23 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml index adacd0535c14..6c40611405a0 100644 --- a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml +++ b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml @@ -9,19 +9,18 @@ title: Cadence SD/SDIO/eMMC Host Controller (SD4HC) maintainers: - Masahiro Yamada -allOf: - - $ref: mmc-controller.yaml - properties: compatible: items: - enum: + - amd,pensando-elba-sd4hc - microchip,mpfs-sd4hc - socionext,uniphier-sd4hc - const: cdns,sd4hc reg: - maxItems: 1 + minItems: 1 + maxItems: 2 interrupts: maxItems: 1 @@ -120,6 +119,26 @@ required: - interrupts - clocks +allOf: + - $ref: mmc-controller.yaml + - if: + properties: + compatible: + contains: + const: amd,pensando-elba-sd4hc + then: + properties: + reg: + items: + - description: Host controller registers + - description: Elba byte-lane enable register for writes + required: + - resets + else: + properties: + reg: + maxItems: 1 + unevaluatedProperties: false examples: From patchwork Thu Mar 23 00:06:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brad Larson X-Patchwork-Id: 73707 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:604a:0:0:0:0:0 with SMTP id j10csp2639477wrt; Wed, 22 Mar 2023 17:10:48 -0700 (PDT) X-Google-Smtp-Source: AK7set80mQzcmDUXtRGuWEuaxH9T28atqXmx40SoTiyVqGxzHgrcn5XJOaebiVqJTeb/xFZbC6NU X-Received: by 2002:a17:906:b281:b0:91e:9cc8:427b with SMTP id q1-20020a170906b28100b0091e9cc8427bmr8855262ejz.25.1679530247942; Wed, 22 Mar 2023 17:10:47 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1679530247; cv=pass; d=google.com; s=arc-20160816; b=tUc0P0D96eO22Qdl88/9wk3CAEOoRlRHUx6+B/yLbz1XJSasSnjNd6qru3j6cwy0z5 LvRNyoNQUfH6d0v/suRglMgNYIqfP6+XjIW1VbaRtMn0Y7EUdgkLSievLydk+CKAtCpU iWeBc6G1e9gh/Y9vVkez88p5twJcJyishZV3aEukc48b6YAoQYjRV66KHrVXnVILe/OA XcJAqsy5z6uPSD3pwp98zh0zoOFqdrTW1KeYKFp2VQciuck2Lkp1Dov358gdcQ0qFTc5 xgsRwtEsi/63fpygB6MIa5QqM6TulhQCdAcEoHxIBiRR8nUYGQb6yqV4a1civDIBhvhm GLXw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=6heMFDr/vcoXtcG1ihJG6vNQj/gCmyUGL8Ele90UPF0=; b=FGh+zRr4cPNxGvaTetPjGPm9XYca1bbfCw96L/oLjDI9Roh4aLWi3U+yVAS2OyaCzs 4a6NKk9HJA5v07zhWSIuWyiGEnZIDv9Wn/ETca+kKtv80AQ4qh/2Yj8c8/obopLsUdh/ izdZ0k09SCIkPxehCXRHBN4Teh6Mu3COkKFPSVKV3K0D5+OSjCmK0IhzKoSgrSMkpRph w6ARbi2fuxFADr/HGt55XlEAvtdZ02oaBTNOlYN9qWZc9QNnMi7Stu4FyCgsjbSUIWjk OlnU2DoMhkKGl+/yVwYXeXg0kdSNw4k4nPeYoPqVw7sTkzWkBYLnAb7Birii2QxrUxjy PdfA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=GPsdr984; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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The Elba qspi fifo size is 1024. Signed-off-by: Brad Larson Reviewed-by: Krzysztof Kozlowski --- v11 changes: - Removed redundant if/then for amd,pensando-elba-qspi v10 changes: - Fix cdns,fifo-depth, only amd,pensando-elba-qspi is 1024 bytes v9 changes: - Add 1024 to cdns,fifo-depth property to resolve dtbs_check error --- .../bindings/spi/cdns,qspi-nor.yaml | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml index 5c01db128be0..6e67de9da293 100644 --- a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml +++ b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml @@ -20,11 +20,28 @@ allOf: required: - power-domains + - if: + properties: + compatible: + contains: + const: amd,pensando-elba-qspi + then: + properties: + cdns,fifo-depth: + enum: [ 128, 256, 1024 ] + default: 1024 + else: + properties: + cdns,fifo-depth: + enum: [ 128, 256 ] + default: 128 + properties: compatible: oneOf: - items: - enum: + - amd,pensando-elba-qspi - ti,k2g-qspi - ti,am654-ospi - intel,lgm-qspi @@ -48,8 +65,6 @@ properties: description: Size of the data FIFO in words. $ref: /schemas/types.yaml#/definitions/uint32 - enum: [ 128, 256 ] - default: 128 cdns,fifo-width: $ref: /schemas/types.yaml#/definitions/uint32 From patchwork Thu Mar 23 00:06:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brad Larson X-Patchwork-Id: 73723 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:604a:0:0:0:0:0 with SMTP id j10csp2647699wrt; Wed, 22 Mar 2023 17:35:49 -0700 (PDT) X-Google-Smtp-Source: AK7set8ePh6aut9za687zYv/no1i8sQ3YXOp9Ilz8mq5vU3bFpR4tDhMyo++fSic7DqSet3vUP6l X-Received: by 2002:a17:906:23e9:b0:926:9c33:ea4 with SMTP id j9-20020a17090623e900b009269c330ea4mr7649652ejg.27.1679531748946; Wed, 22 Mar 2023 17:35:48 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1679531748; cv=pass; d=google.com; s=arc-20160816; b=O5drn/XnfJFuVQzmaumzLWYKp8+JJ40Lii4dI0gTQjPNWKkpiN4YFoKEYuH8GZmWoa sqV0zfpPmsmS5ba98mR5D5pAzX8zuJ4h/FCqk8tZ5KkpnIP6wkVVGDdm5oQhFZZoe9CH K3Eim9ha+jE8zEWa3NO69Mngg8A1tDSKPFIOEOxRNCMtNhx1dzPNFD4cJSR0Z4Q050Ul ybcR5e5JyBaLet/3GjdLVCt4DvEeCMmTTPZQD5xZIrF6ZuVyTfqrdrDLCQ9A0bTVtd1L XYEgdg9NlhUFO4xEvF0OpdA5zN1APvOYoElff+75vVB4KAFCE2UTWxWPyMcI23oNtwVI WqPg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=s85HrBK30oYhm+SLURSRXrLkNTK5QT6HCkbpb+RlMFI=; b=M8Uo+KNpj3iVDXng3nNU5j+60C5W/MV1XCR8mjJCAdFBxBMr8dXuUsXOavQmpqa1Yg 5BwL2+h0ECMEP6KaFSrfDB8R7GNQqzpgEuS8AZM+3wHWu1rFyExSvlWaGPl6nwt0Cg/m F7a2qip2ywVl28PSZMQkxaD1hKR0xhkHIhDj28isQYpEilx9KrAl2XXB6JJNrWcowUor 8/btaTeqICVtXUkZIoLzzikqEiuuqFgd+BmgI6SBA7T5WG2RQBgOJ7HBDcryGU27Cf84 LlNkZRg1z61u8/eN7zuGyW3ZOnUgB9KJsgJV3rH/KRNreBarjacIQJjdozDD/sN82mar 6psQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=RGSVNOzB; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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Wed, 22 Mar 2023 19:08:03 -0500 From: Brad Larson To: CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v12 04/15] dt-bindings: spi: dw: Add AMD Pensando Elba SoC SPI Controller Date: Wed, 22 Mar 2023 17:06:46 -0700 Message-ID: <20230323000657.28664-5-blarson@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230323000657.28664-1-blarson@amd.com> References: <20230323000657.28664-1-blarson@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT023:EE_|DS7PR12MB5765:EE_ X-MS-Office365-Filtering-Correlation-Id: c99c3b95-55ad-4270-b4ce-08db2b32ada0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: F68IvmgllyApPsCBeNVUDDE70/yam4uvtjZST4eg9z4yZ/2yAc0mMGXcznMaum9vFm9UfLuqLWKaL4Kwz0meFpo5Vdxb1SQ9SFmV7VsCvauYP4k07keHAcYgoS2ZQU3Ol92B/AQlSaOZ8c7VjB+90sHcEZw8VDAzia2zBoGhxT77kaHXNtF6XXmTFkf7jZB9/v/PU7a5fQ6ereThw0XnfHANwKMtwTbekGAB7KpuVqrJXdvfv+p8tycX3Tbgso5pwEE/KAA+MfqZMnLiSPwfT/ff0nx01AyTNzen82xsG+B6e/XZW9PYn8eBX6BS5on0+e+19XeVgmunMjsou1KuXDYmL6CO17rNVTNiJPduWeeK4A8eeaERzs1azYTmfBC0N4PbZwiGQVrxw4idoTWIB9FDgPnFvuY7zMfuDiX+5CIvyflWRVYYn3+u79YnoShAvkNtEGUvqmWp47SYyHcAj1nJdknrIc6hzsSUsbT4zidMHMSRSvNHR4lCKP35PWUwTwbo1vbASBFOdFRPScCEYmWOzsEQ3Wv5mOwfcWCYWRZpmzqIyfOUoymaEebBCBfhurvkfQWaAQY8LsG7uU4781QiTtltx2uJlzdjcGM8OVQm80ap6FwbAdpxLpsNOANG7vx+BC+4HTLcXUs+gpwk4XQTDClw22H25OPGMCAr8XZp8Xvgv7ct70qYA0OhY0VvlSwLXK4Mg7sHWcaN83Nw8GEaCBMk9rv2Kym+7ZQkaLc= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230025)(4636009)(136003)(376002)(346002)(39860400002)(396003)(451199018)(46966006)(40470700004)(36840700001)(82310400005)(40460700003)(40480700001)(36756003)(16526019)(316002)(4326008)(54906003)(6916009)(83380400001)(8676002)(70586007)(356005)(70206006)(186003)(1076003)(2616005)(6666004)(426003)(47076005)(26005)(336012)(8936002)(82740400003)(5660300002)(7406005)(7416002)(478600001)(36860700001)(81166007)(41300700001)(2906002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Mar 2023 00:08:06.3938 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c99c3b95-55ad-4270-b4ce-08db2b32ada0 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT023.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB5765 X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761116683441987650?= X-GMAIL-MSGID: =?utf-8?q?1761116683441987650?= The AMD Pensando Elba SoC has integrated the DW APB SPI Controller Signed-off-by: Brad Larson Reviewed-by: Krzysztof Kozlowski Reviewed-by: Serge Semin --- v12 changes: - Correct property amd,pensando-elba-syscon description v10 changes: - Move definition of amd,pensando-elba-syscon into properties with a better description - Add amd,pensando-elba-syscon: false for non elba designs v9 changes: - Define property amd,pensando-elba-syscon - Move compatible amd,pensando-elba-spi ahead of baikal,bt1-ssi --- .../bindings/spi/snps,dw-apb-ssi.yaml | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml index a132b5fc56e0..12ca108864c6 100644 --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml @@ -37,6 +37,17 @@ allOf: else: required: - interrupts + - if: + properties: + compatible: + contains: + const: amd,pensando-elba-spi + then: + required: + - amd,pensando-elba-syscon + else: + properties: + amd,pensando-elba-syscon: false properties: compatible: @@ -63,6 +74,8 @@ properties: const: intel,keembay-ssi - description: Intel Thunder Bay SPI Controller const: intel,thunderbay-ssi + - description: AMD Pensando Elba SoC SPI Controller + const: amd,pensando-elba-spi - description: Baikal-T1 SPI Controller const: baikal,bt1-ssi - description: Baikal-T1 System Boot SPI Controller @@ -136,6 +149,12 @@ properties: of the designware controller, and the upper limit is also subject to controller configuration. + amd,pensando-elba-syscon: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + Block address to control SPI chip-selects. The Elba SoC system controller + provides an interface to override the native DWC SSI CS control. + patternProperties: "^.*@[0-9a-f]+$": type: object From patchwork Thu Mar 23 00:06:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brad Larson X-Patchwork-Id: 73708 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:604a:0:0:0:0:0 with SMTP id j10csp2639568wrt; Wed, 22 Mar 2023 17:11:02 -0700 (PDT) X-Google-Smtp-Source: AK7set+/tHTpJUBKtImbOtfaNC5//UtNh/uqRdR0rZLACB3kwnQ5Jk4U0lW4fW6RsBHmY3SWUgNq X-Received: by 2002:aa7:d748:0:b0:4fb:4fc2:e600 with SMTP id a8-20020aa7d748000000b004fb4fc2e600mr7747551eds.42.1679530262087; Wed, 22 Mar 2023 17:11:02 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1679530262; cv=pass; d=google.com; s=arc-20160816; b=YmCyzb5GZC0Rio0zSSaYl9OxT4vzgdBIDgf+mY8xtdqiFy7BPW0xZ8B6LRNWd7AWJ8 XjT95TP86wAfY5vwu55M3td4E8u6gQlejgfXIp71OSyNUZ1qedRsmgHDIBWatITspUoL cEBDdUhVWQJomTgxnai2aUsKA0277CjFogQ+8XxdD5f/cCASFHv1MNMSFZlUZO+bV31E a5qJ+bY+J837Kg81ilD30v1zTSUk3DvNgZMQ0Azcmjh0haWyO4AItd2D2X3FBa7UF0ep OPsimPVa7097X3AGbozLI4nFYtRdit7kMAt+weREtfBhvZtTP97FlCsMfrLraVzKgnEl fYbQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=uKnW45e7WATID2AQ00PmM4L++2zkqYt0EGCGnck4u+o=; b=srsdEvEqUfEUNGNiofkG/XEAzkeBLuYk2M5dQzkb6/WVXeb5E0BVEOemoYna3m0qZJ UKRH2zHh/wEbDWRh8F1TE4PQLzUi3/GVy57TMDqLM/QhXdojpjrjFbQJXWWevnvaTnML 5HYm/U1OEf4ITJdphDb1iAZtEvpt57Hu/WOVYTsh8YNQ2N8o3Pt0tyA+2J7TFZFPL8zZ uHrnQ13iDcM+wbMwREjI+ponPmN+NKW6HEGYKPpg23u9O+I+2GSfvussLxU3w/BFDWyP araIsY/nR0Luhf5zKAeaW13b6iRuyOGbI9D6Sb/uMGPPFAubA37jSAk4fTgrHv6/kH4J 8JfA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=ujQHIfh0; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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This device is present in all Pensando SoC based designs. Signed-off-by: Brad Larson Reviewed-by: Krzysztof Kozlowski --- v11 changes: - Fixed the compatible which should have stayed as 'amd,pensando-elba-ctrl', the commit message, and the filename - Reference spi-peripheral-props - Delete spi-max-frequency - Remove num-cs from example v10 changes: - Property renamed to amd,pensando-ctrl - Driver is renamed and moved to soc/drivers/amd affecting binding - Delete cs property, driver handles device node creation from parent num-cs fixing schema reg error in a different way v9 changes: - Instead of four nodes, one per chip-select, a single node is used with reset-cells in the parent. - No MFD API is used anymore in the driver so it made sense to move this to drivers/spi. - This driver is common for all Pensando SoC based designs so changed the name to pensando-sr.c to not make it Elba SoC specific. - Added property cs for the chip-select number which is used by the driver to create /dev/pensr0. --- .../soc/amd/amd,pensando-elba-ctrl.yaml | 58 +++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/amd/amd,pensando-elba-ctrl.yaml diff --git a/Documentation/devicetree/bindings/soc/amd/amd,pensando-elba-ctrl.yaml b/Documentation/devicetree/bindings/soc/amd/amd,pensando-elba-ctrl.yaml new file mode 100644 index 000000000000..f1d3ed4f519b --- /dev/null +++ b/Documentation/devicetree/bindings/soc/amd/amd,pensando-elba-ctrl.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/amd/amd,pensando-elba-ctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: AMD Pensando Elba SoC Controller + +description: + The AMD Pensando Elba SoC Controller is a SPI connected device with essential + control/status registers accessed on chip select 0. This device is present + in all Pensando SoC based designs. + +maintainers: + - Brad Larson + +properties: + compatible: + enum: + - amd,pensando-elba-ctrl + + reg: + maxItems: 1 + + '#reset-cells': + const: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - '#reset-cells' + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + + spi { + #address-cells = <1>; + #size-cells = <0>; + + system-controller@0 { + compatible = "amd,pensando-elba-ctrl"; + reg = <0>; + spi-max-frequency = <12000000>; + interrupt-parent = <&porta>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + #reset-cells = <1>; + }; + }; + +... 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Wed, 22 Mar 2023 19:08:31 -0500 From: Brad Larson To: CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v12 06/15] MAINTAINERS: Add entry for AMD PENSANDO Date: Wed, 22 Mar 2023 17:06:48 -0700 Message-ID: <20230323000657.28664-7-blarson@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230323000657.28664-1-blarson@amd.com> References: <20230323000657.28664-1-blarson@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT062:EE_|IA0PR12MB9047:EE_ X-MS-Office365-Filtering-Correlation-Id: 58c77c51-040d-4bdc-498a-08db2b32be9e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: PifC26cE4//DvGomvTDDavURj1/vHiy3jq2Trd9TV9PUxFahMqHen0cwRT0KtzjGwoJ8IwzPLuB2ScscsF5sFz7P8bT1HDysxIV2TS597dVcCIP+8NrAzoPQRDpU1maDLvZh2v1quSzin5qPmWNj6I0AnNJuG8mGla5LsR5x0NVieSquBcIt/qMOd0NhtpXSNFCp/CeRKNUo5W1/dR/tQbY+b2GnnnM5NQQXJn3TU5Z8sOrFLsNAYthOLnB15kLOl/hCodjz6SCkf/qbXGu9uRN8699wy2RAl+espPmpJs9xMKpdCwr6V6LePg7umx654gYbPmpFwgkDb3i8oJRwejWaJfdMpbxUMR3kxCNYdguqaJ1g8QF0fcmv4mFaqbvXDdl+8jN4+vN0OA6Wovj84okovRYBbzs7D4uR3MLcLn9sY8+wsIJ+2YIDB4pDdsHXrye0Eh8kfDusRXMFICEOOQRMe/eKySkQSq5unfNfNPdnAC/wtj2WW9VdP0oN3/21lbUGiW9re2TbTbjVVWtnXhW8CKE52n0jd+catDhoYfAEYxNuJ19Y0+7siADBKDMEHIupsQV+OIL30+jjjbvMYCcbAFsV2CWPdQ+OF3XubjaNjgGIZQZ2E51Kbghk6r0xXo331C60SJQ/BeeosAG9IvDgLmFABSQeEk+F3jbPxAO+BNcz3vW/lzmHWy3PdmNvGPoZ3KFShG2GBNHr7TpbaHxe1IS2u5PU/JQ+YJ6cpS8= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230025)(4636009)(39860400002)(376002)(396003)(136003)(346002)(451199018)(46966006)(36840700001)(40470700004)(4326008)(40460700003)(356005)(6916009)(7416002)(36756003)(26005)(41300700001)(47076005)(478600001)(8676002)(54906003)(5660300002)(8936002)(4744005)(7406005)(70206006)(83380400001)(6666004)(36860700001)(40480700001)(426003)(82740400003)(336012)(81166007)(316002)(82310400005)(2616005)(2906002)(186003)(70586007)(16526019)(1076003)(36900700001);DIR:OUT;SFP:1101; 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Signed-off-by: Brad Larson --- arch/arm64/Kconfig.platforms | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 89a0b13b058d..3510daaabe27 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -236,6 +236,18 @@ config ARCH_NPCM General support for NPCM8xx BMC (Arbel). Nuvoton NPCM8xx BMC based on the Cortex A35. +config ARCH_PENSANDO + bool "AMD Pensando Platforms" + help + This enables support for the ARMv8 based AMD Pensando SoC + family to include the Elba SoC. + + AMD Pensando SoCs support a range of Distributed Services + Cards in PCIe format installed into servers. The Elba + SoC includes 16 A-72 CPU cores, 144 programmable P4 + cores for a minimal latency/jitter datapath, and network + interfaces up to 200 Gb/s. + config ARCH_QCOM bool "Qualcomm Platforms" select GPIOLIB From patchwork Thu Mar 23 00:06:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brad Larson X-Patchwork-Id: 73728 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:604a:0:0:0:0:0 with SMTP id j10csp2649388wrt; Wed, 22 Mar 2023 17:41:20 -0700 (PDT) X-Google-Smtp-Source: AK7set/ynP0fU8as57lBypaDAn+T8TjyVZiCH/tfey7zCQaNPzXt57hELFkY7Wehkj2FYdwZ4b68 X-Received: by 2002:aa7:de82:0:b0:4fa:e187:64d1 with SMTP id j2-20020aa7de82000000b004fae18764d1mr7308317edv.38.1679532080371; Wed, 22 Mar 2023 17:41:20 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1679532080; cv=pass; d=google.com; s=arc-20160816; b=HAHV+Vu9HRvUc/iDOaQ246K21LTUDwYMznqRd9tIpRzdROHJpEZPHO7OXuuckGGe6I uf8jwgpQWzxqbCLZHlnmnQaHjmb7HvGUsQH81UNwKBFZIQPuqp0dhXq9u9SB9HAcOLGR xU67ZULqBHkYTtBsStwLo51VzqaWBMNMV9d5R8kkfDundj4y49JXiMQOsSATPT27DQYR tdl2miCp8QVMzi94ItAsYkIHx0Wbqdus7cB0RpTIxeQCfUN2p3ov/l3ibsDz+Y4yNRUE G5u2EzGaRtvwLmZZTOv0ZpJQLjH+m3nLXs3nEqhT/7W5XD223xfbvXPr62vaANr9AbGh 1MGg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=83PU7FEhIF9nAiOm5pRE0SwYJa+LlvFc6t03SX3ut1I=; b=Rf8dvdwZdXuZAsDxJ5uShd+eqSN8NcUxih3g9TQTaMP7yUBp5/Rm+H4n11cxX3rVn/ HdsL0i3dATDkH+0LN4UBuwDnZxsa8JM8/8UOODCQY4k3MAX5KPLTaCghF9UMWcIJBjYc UGuls9ScWc+nFSmXJmwjaqeFe4/Z70yauvrXdVUOiB3pAhM/yQ7i0uKyMCwWSkKKMzVu W/sv+iFk7acbANEeegcHvggUFiOF5xSlFA2pNL+i7kVcA9Le4cfihIG6+wlQDgGKs6qy 4jmN4hVRNELC2Ncq7JY+pgT06cGcwOssbUDGTQ7CNN9yat2E2gQ1n4P2fYlnKXUgg7qn OS3A== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=yWfkBJRX; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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Wed, 22 Mar 2023 19:09:03 -0500 From: Brad Larson To: CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v12 08/15] arm64: dts: Add AMD Pensando Elba SoC support Date: Wed, 22 Mar 2023 17:06:50 -0700 Message-ID: <20230323000657.28664-9-blarson@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230323000657.28664-1-blarson@amd.com> References: <20230323000657.28664-1-blarson@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT100:EE_|SA3PR12MB8000:EE_ X-MS-Office365-Filtering-Correlation-Id: b5cc56e2-5e6a-463d-ba89-08db2b32d121 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: oTrDGAIksSU7QsH1F4w1tsSKrBKBhS0tfZK64HBPx9LA4vgc7DA1w4ri566smj0KYXe6jeLIoOERKvJUebkmftFprV4F9RggHu7+nZWW2I+GwYISExFn8X1wUoFSiMBAMi03Q1fQaMTFHnmaigFmfaq+ogsWxvlbpzKlZrgiqdFLgHR8vok5HJguYBXqEidh8zdTB+YfrhRtMKG3JrwDb8txjD9/q+od/AUNvL9TvclrHqHg5bdFdrmQBAq6MiN3z4ScC2RNKUDQx90n7kApwZhq3vXN15hppYXTxOpkOj2kiwe2T48KB98wneMPDpsLPt6QPThivf4W2Dq9OMPruhrIUUxkNHh4By2GCI3WqBj96Sp/unJyoYjz2U01yUG0Q5Ke548NAqwx8uyBJVEWmS6l5b1EMQ/aps1LjJnOTYEQjzpJiLBDbjS7/dK4v3Bs5qvdypSVVpe00Tc2z8k8bYpOhuGgLrxCX8oTCe0W7qPuuDttUTR+R6s7PTm+jS4QABYUd6h/trT7xtuXiDEjyohJoMeBXOTe+a2RufaIpiqE3CigsMJtP3SU0GvF1exVFds/yQ67+8r/8kjk8SN/uKaB5BaSrvD7BWTVscf2ESRqyMnk/vrP/4Vqce0gJWxMO2a4F5PftGE0lJbTWV+ApXM9fkLhsGJleiXeS20X1FkuXoR/CmOltDZZ//wgAIrGUn3N8yfvFD1TdKOngtCqjPvPm0B/ZlAwjyDziHGox8k= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230025)(4636009)(376002)(136003)(346002)(39860400002)(396003)(451199018)(46966006)(36840700001)(40470700004)(40480700001)(82310400005)(40460700003)(36756003)(83380400001)(70206006)(316002)(16526019)(6916009)(4326008)(8676002)(478600001)(70586007)(54906003)(186003)(26005)(336012)(2616005)(47076005)(6666004)(1076003)(426003)(7406005)(5660300002)(36860700001)(356005)(7416002)(8936002)(41300700001)(30864003)(82740400003)(81166007)(2906002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Mar 2023 00:09:05.9439 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b5cc56e2-5e6a-463d-ba89-08db2b32d121 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT100.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB8000 X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761117030773243628?= X-GMAIL-MSGID: =?utf-8?q?1761117030773243628?= Add AMD Pensando common and Elba SoC specific device nodes Signed-off-by: Brad Larson --- v11 changes: - Delete reset-names - Fix spi0 compatible to be specific 'amd,pensando-elba-ctrl' v9 changes: - Single node for spi0 system-controller and squash the reset-controller child into parent --- arch/arm64/boot/dts/amd/Makefile | 1 + arch/arm64/boot/dts/amd/elba-16core.dtsi | 189 +++++++++++++++++ arch/arm64/boot/dts/amd/elba-asic-common.dtsi | 80 ++++++++ arch/arm64/boot/dts/amd/elba-asic.dts | 28 +++ arch/arm64/boot/dts/amd/elba-flash-parts.dtsi | 106 ++++++++++ arch/arm64/boot/dts/amd/elba.dtsi | 191 ++++++++++++++++++ 6 files changed, 595 insertions(+) create mode 100644 arch/arm64/boot/dts/amd/elba-16core.dtsi create mode 100644 arch/arm64/boot/dts/amd/elba-asic-common.dtsi create mode 100644 arch/arm64/boot/dts/amd/elba-asic.dts create mode 100644 arch/arm64/boot/dts/amd/elba-flash-parts.dtsi create mode 100644 arch/arm64/boot/dts/amd/elba.dtsi diff --git a/arch/arm64/boot/dts/amd/Makefile b/arch/arm64/boot/dts/amd/Makefile index 68103a8b0ef5..8502cc2afbc5 100644 --- a/arch/arm64/boot/dts/amd/Makefile +++ b/arch/arm64/boot/dts/amd/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_PENSANDO) += elba-asic.dtb dtb-$(CONFIG_ARCH_SEATTLE) += amd-overdrive-rev-b0.dtb amd-overdrive-rev-b1.dtb diff --git a/arch/arm64/boot/dts/amd/elba-16core.dtsi b/arch/arm64/boot/dts/amd/elba-16core.dtsi new file mode 100644 index 000000000000..37aadd442db8 --- /dev/null +++ b/arch/arm64/boot/dts/amd/elba-16core.dtsi @@ -0,0 +1,189 @@ +// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +/* + * Copyright 2020-2022 Advanced Micro Devices, Inc. + */ + +/ { + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { cpu = <&cpu0>; }; + core1 { cpu = <&cpu1>; }; + core2 { cpu = <&cpu2>; }; + core3 { cpu = <&cpu3>; }; + }; + + cluster1 { + core0 { cpu = <&cpu4>; }; + core1 { cpu = <&cpu5>; }; + core2 { cpu = <&cpu6>; }; + core3 { cpu = <&cpu7>; }; + }; + + cluster2 { + core0 { cpu = <&cpu8>; }; + core1 { cpu = <&cpu9>; }; + core2 { cpu = <&cpu10>; }; + core3 { cpu = <&cpu11>; }; + }; + + cluster3 { + core0 { cpu = <&cpu12>; }; + core1 { cpu = <&cpu13>; }; + core2 { cpu = <&cpu14>; }; + core3 { cpu = <&cpu15>; }; + }; + }; + + /* CLUSTER 0 */ + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x0>; + next-level-cache = <&l2_0>; + enable-method = "psci"; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x1>; + next-level-cache = <&l2_0>; + enable-method = "psci"; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x2>; + next-level-cache = <&l2_0>; + enable-method = "psci"; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x3>; + next-level-cache = <&l2_0>; + enable-method = "psci"; + }; + + l2_0: l2-cache0 { + compatible = "cache"; + }; + + /* CLUSTER 1 */ + cpu4: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x100>; + next-level-cache = <&l2_1>; + enable-method = "psci"; + }; + + cpu5: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x101>; + next-level-cache = <&l2_1>; + enable-method = "psci"; + }; + + cpu6: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x102>; + next-level-cache = <&l2_1>; + enable-method = "psci"; + }; + + cpu7: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x103>; + next-level-cache = <&l2_1>; + enable-method = "psci"; + }; + + l2_1: l2-cache1 { + compatible = "cache"; + }; + + /* CLUSTER 2 */ + cpu8: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x200>; + next-level-cache = <&l2_2>; + enable-method = "psci"; + }; + + cpu9: cpu@201 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x201>; + next-level-cache = <&l2_2>; + enable-method = "psci"; + }; + + cpu10: cpu@202 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x202>; + next-level-cache = <&l2_2>; + enable-method = "psci"; + }; + + cpu11: cpu@203 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x203>; + next-level-cache = <&l2_2>; + enable-method = "psci"; + }; + + l2_2: l2-cache2 { + compatible = "cache"; + }; + + /* CLUSTER 3 */ + cpu12: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x300>; + next-level-cache = <&l2_3>; + enable-method = "psci"; + }; + + cpu13: cpu@301 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x301>; + next-level-cache = <&l2_3>; + enable-method = "psci"; + }; + + cpu14: cpu@302 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x302>; + next-level-cache = <&l2_3>; + enable-method = "psci"; + }; + + cpu15: cpu@303 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x303>; + next-level-cache = <&l2_3>; + enable-method = "psci"; + }; + + l2_3: l2-cache3 { + compatible = "cache"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/amd/elba-asic-common.dtsi b/arch/arm64/boot/dts/amd/elba-asic-common.dtsi new file mode 100644 index 000000000000..1a615788f54e --- /dev/null +++ b/arch/arm64/boot/dts/amd/elba-asic-common.dtsi @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +/* + * Copyright 2020-2022 Advanced Micro Devices, Inc. + */ + +&ahb_clk { + clock-frequency = <400000000>; +}; + +&emmc_clk { + clock-frequency = <200000000>; +}; + +&flash_clk { + clock-frequency = <400000000>; +}; + +&ref_clk { + clock-frequency = <156250000>; +}; + +&qspi { + status = "okay"; + + flash0: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + spi-rx-bus-width = <2>; + m25p,fast-read; + cdns,read-delay = <0>; + cdns,tshsl-ns = <0>; + cdns,tsd2d-ns = <0>; + cdns,tchsh-ns = <0>; + cdns,tslch-ns = <0>; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&emmc { + bus-width = <8>; + cap-mmc-hw-reset; + resets = <&rstc 0>; + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <100000>; + status = "okay"; + + rtc@51 { + compatible = "nxp,pcf85263"; + reg = <0x51>; + }; +}; + +&spi0 { + #address-cells = <1>; + #size-cells = <0>; + num-cs = <4>; + cs-gpios = <0>, <0>, <&porta 1 GPIO_ACTIVE_LOW>, + <&porta 7 GPIO_ACTIVE_LOW>; + status = "okay"; + + rstc: system-controller@0 { + compatible = "amd,pensando-elba-ctrl"; + reg = <0>; + spi-max-frequency = <12000000>; + interrupt-parent = <&porta>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + #reset-cells = <1>; + }; +}; diff --git a/arch/arm64/boot/dts/amd/elba-asic.dts b/arch/arm64/boot/dts/amd/elba-asic.dts new file mode 100644 index 000000000000..c3f4da2f7449 --- /dev/null +++ b/arch/arm64/boot/dts/amd/elba-asic.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +/* + * Device Tree file for AMD Pensando Elba Board. + * + * Copyright 2020-2022 Advanced Micro Devices, Inc. + */ + +/dts-v1/; + +#include "elba.dtsi" +#include "elba-16core.dtsi" +#include "elba-asic-common.dtsi" +#include "elba-flash-parts.dtsi" + +/ { + model = "AMD Pensando Elba Board"; + compatible = "amd,pensando-elba-ortano", "amd,pensando-elba"; + + aliases { + serial0 = &uart0; + spi0 = &spi0; + spi1 = &qspi; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; diff --git a/arch/arm64/boot/dts/amd/elba-flash-parts.dtsi b/arch/arm64/boot/dts/amd/elba-flash-parts.dtsi new file mode 100644 index 000000000000..734893fef2c3 --- /dev/null +++ b/arch/arm64/boot/dts/amd/elba-flash-parts.dtsi @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +/* + * Copyright 2020-2022 Advanced Micro Devices, Inc. + */ + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "flash"; + reg = <0x10000 0xfff0000>; + }; + + partition@f0000 { + label = "golduenv"; + reg = <0xf0000 0x10000>; + }; + + partition@100000 { + label = "boot0"; + reg = <0x100000 0x80000>; + }; + + partition@180000 { + label = "golduboot"; + reg = <0x180000 0x200000>; + }; + + partition@380000 { + label = "brdcfg0"; + reg = <0x380000 0x10000>; + }; + + partition@390000 { + label = "brdcfg1"; + reg = <0x390000 0x10000>; + }; + + partition@400000 { + label = "goldfw"; + reg = <0x400000 0x3c00000>; + }; + + partition@4010000 { + label = "fwmap"; + reg = <0x4010000 0x20000>; + }; + + partition@4030000 { + label = "fwsel"; + reg = <0x4030000 0x20000>; + }; + + partition@4090000 { + label = "bootlog"; + reg = <0x4090000 0x20000>; + }; + + partition@40b0000 { + label = "panicbuf"; + reg = <0x40b0000 0x20000>; + }; + + partition@40d0000 { + label = "uservars"; + reg = <0x40d0000 0x20000>; + }; + + partition@4200000 { + label = "uboota"; + reg = <0x4200000 0x400000>; + }; + + partition@4600000 { + label = "ubootb"; + reg = <0x4600000 0x400000>; + }; + + partition@4a00000 { + label = "mainfwa"; + reg = <0x4a00000 0x1000000>; + }; + + partition@5a00000 { + label = "mainfwb"; + reg = <0x5a00000 0x1000000>; + }; + + partition@6a00000 { + label = "diaguboot"; + reg = <0x6a00000 0x400000>; + }; + + partition@8000000 { + label = "diagfw"; + reg = <0x8000000 0x7fe0000>; + }; + + partition@ffe0000 { + label = "ubootenv"; + reg = <0xffe0000 0x10000>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/amd/elba.dtsi b/arch/arm64/boot/dts/amd/elba.dtsi new file mode 100644 index 000000000000..674890cf2a34 --- /dev/null +++ b/arch/arm64/boot/dts/amd/elba.dtsi @@ -0,0 +1,191 @@ +// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +/* + * Copyright 2020-2022 Advanced Micro Devices, Inc. + */ + +#include +#include "dt-bindings/interrupt-controller/arm-gic.h" + +/ { + model = "Elba ASIC Board"; + compatible = "amd,pensando-elba"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + dma-coherent; + + ahb_clk: oscillator0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + emmc_clk: oscillator2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + flash_clk: oscillator3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + ref_clk: oscillator4 { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + pmu { + compatible = "arm,cortex-a72-pmu"; + interrupts = ; + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + i2c0: i2c@400 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x400 0x0 0x100>; + clocks = <&ahb_clk>; + #address-cells = <1>; + #size-cells = <0>; + i2c-sda-hold-time-ns = <480>; + interrupts = ; + status = "disabled"; + }; + + wdt0: watchdog@1400 { + compatible = "snps,dw-wdt"; + reg = <0x0 0x1400 0x0 0x100>; + clocks = <&ahb_clk>; + interrupts = ; + status = "disabled"; + }; + + qspi: spi@2400 { + compatible = "amd,pensando-elba-qspi", "cdns,qspi-nor"; + reg = <0x0 0x2400 0x0 0x400>, + <0x0 0x7fff0000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&flash_clk>; + cdns,fifo-depth = <1024>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x7fff0000>; + status = "disabled"; + }; + + spi0: spi@2800 { + compatible = "amd,pensando-elba-spi"; + reg = <0x0 0x2800 0x0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + amd,pensando-elba-syscon = <&syscon>; + clocks = <&ahb_clk>; + interrupts = ; + num-cs = <2>; + status = "disabled"; + }; + + gpio0: gpio@4000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x0 0x4000 0x0 0x78>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + porta: gpio-port@0 { + compatible = "snps,dw-apb-gpio-port"; + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + interrupts = ; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + }; + + portb: gpio-port@1 { + compatible = "snps,dw-apb-gpio-port"; + reg = <1>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + }; + }; + + uart0: serial@4800 { + compatible = "ns16550a"; + reg = <0x0 0x4800 0x0 0x100>; + clocks = <&ref_clk>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + }; + + gic: interrupt-controller@800000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x800000 0x0 0x200000>, /* GICD */ + <0x0 0xa00000 0x0 0x200000>, /* GICR */ + <0x0 0x60000000 0x0 0x2000>, /* GICC */ + <0x0 0x60010000 0x0 0x1000>, /* GICH */ + <0x0 0x60020000 0x0 0x2000>; /* GICV */ + #address-cells = <2>; + #size-cells = <2>; + #interrupt-cells = <3>; + ranges; + interrupt-controller; + interrupts = ; + + /* + * Elba specific pre-ITS is enabled using the + * existing property socionext,synquacer-pre-its + */ + gic_its: msi-controller@820000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0x820000 0x0 0x10000>; + msi-controller; + #msi-cells = <1>; + socionext,synquacer-pre-its = + <0xc00000 0x1000000>; + }; + }; + + emmc: mmc@30440000 { + compatible = "amd,pensando-elba-sd4hc", "cdns,sd4hc"; + reg = <0x0 0x30440000 0x0 0x10000>, + <0x0 0x30480044 0x0 0x4>; /* byte-lane ctrl */ + clocks = <&emmc_clk>; + interrupts = ; + cdns,phy-input-delay-sd-highspeed = <0x4>; + cdns,phy-input-delay-legacy = <0x4>; + cdns,phy-input-delay-sd-uhs-sdr50 = <0x6>; + cdns,phy-input-delay-sd-uhs-ddr50 = <0x16>; + mmc-ddr-1_8v; + status = "disabled"; + }; + + syscon: syscon@307c0000 { + compatible = "amd,pensando-elba-syscon", "syscon"; + reg = <0x0 0x307c0000 0x0 0x3000>; + }; + }; +}; From patchwork Thu Mar 23 00:06:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brad Larson X-Patchwork-Id: 73720 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:604a:0:0:0:0:0 with SMTP id j10csp2646234wrt; Wed, 22 Mar 2023 17:31:18 -0700 (PDT) X-Google-Smtp-Source: AK7set9slxFvfPrx+wJJXHYjop1QRt/ItR7PBEK/ofqKpEmdIywwpM2MHsIKVDQchllPcwgQ0atN X-Received: by 2002:aa7:d419:0:b0:4fc:3cd1:37c8 with SMTP id z25-20020aa7d419000000b004fc3cd137c8mr8985995edq.22.1679531478147; Wed, 22 Mar 2023 17:31:18 -0700 (PDT) ARC-Seal: i=2; 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Wed, 22 Mar 2023 19:09:19 -0500 From: Brad Larson To: CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v12 09/15] spi: cadence-quadspi: Add compatible for AMD Pensando Elba SoC Date: Wed, 22 Mar 2023 17:06:51 -0700 Message-ID: <20230323000657.28664-10-blarson@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230323000657.28664-1-blarson@amd.com> References: <20230323000657.28664-1-blarson@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF000100D1:EE_|SA1PR12MB8144:EE_ X-MS-Office365-Filtering-Correlation-Id: 3fe823b9-70b1-4af7-8352-08db2b32dad0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: BNj/wH4N1SA9MJXhSqx4GO9TS5rO3yaeekqIxVFMhXbn89BtB0qAtLGrSLAN17Z9mrzo63/iwujkHPk09e3Z5JcizvCEGk1vpdDhYsw/bzeoaQi6XYtGOlkF5eWv2sdLViX0ifqQzxrO2ZbEx1tdq2xkIWxp4InElLh/0Y3t9j46AQ24calq5S/CIZ+WEZ0nWtlT327qhv/gqgH0OMeZEQqY6fStUZkhbAwSPauqGMLBlHlMxIvi3DWrXkND12jNv9/ZLZi8yhjEiYTIDWw0T48plcDbkN3vNIJqNWJF91vwLa2g3c9eJBjAipbhJ8s5mwoYJz7gVQhaTWbJOL5ryBYpaB/Bs2PZcTzvprSWM7kSUb9/zVtjc9Pz4XGvj+fPvDo29KQD+7B1rLLWKimw6Lq+5XXDmiS2jdFyWk8f0e2gSPwLJCKlPS1+2VPWUiMymLgjg/lgJEk+wXwHUl2RTKgVlcaL6ytNdF9iI2gCZLErpMOqSOx0irYoEYN6mq+IysoHnmEp1xQl4hk8wEdpkI1C4aCs+vtJNKrqQtDULKBFcB/dzKaV54xNvCzRztMWirUiIhrwT66WrAGl42q7piba64iJOpgA7116XL5pQlASfT7WSATSKuYWpNOPisOYPslx68BXoPRaoOZUCl5+KqBPSbjCsYfQcie//HjEDjT7fqdL1uvMeuKN4DdjsQH9efTx+soIFYLsKo8qCBYatoOWd4JUPZ3G/7EzOnJICdY= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230025)(4636009)(396003)(346002)(376002)(39860400002)(136003)(451199018)(36840700001)(40470700004)(46966006)(8936002)(336012)(36756003)(7416002)(40460700003)(7406005)(5660300002)(40480700001)(426003)(47076005)(36860700001)(2616005)(2906002)(82310400005)(478600001)(316002)(54906003)(81166007)(41300700001)(82740400003)(4326008)(1076003)(26005)(8676002)(6916009)(70586007)(356005)(6666004)(186003)(16526019)(70206006)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Mar 2023 00:09:22.1108 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3fe823b9-70b1-4af7-8352-08db2b32dad0 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF000100D1.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB8144 X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761116399434392897?= X-GMAIL-MSGID: =?utf-8?q?1761116399434392897?= The AMD Pensando Elba SoC has the Cadence QSPI controller integrated. The quirk CQSPI_NEEDS_APB_AHB_HAZARD_WAR is added and if enabled a dummy readback from the controller is performed to ensure synchronization. Signed-off-by: Brad Larson --- v9 changes: - Rebase to linux-next 6.2.0-rc1 --- drivers/spi/spi-cadence-quadspi.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index 64b6a460d739..ad82d2ab3442 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -40,6 +40,7 @@ #define CQSPI_SUPPORT_EXTERNAL_DMA BIT(2) #define CQSPI_NO_SUPPORT_WR_COMPLETION BIT(3) #define CQSPI_SLOW_SRAM BIT(4) +#define CQSPI_NEEDS_APB_AHB_HAZARD_WAR BIT(5) /* Capabilities */ #define CQSPI_SUPPORTS_OCTAL BIT(0) @@ -90,6 +91,7 @@ struct cqspi_st { u32 pd_dev_id; bool wr_completion; bool slow_sram; + bool apb_ahb_hazard; }; struct cqspi_driver_platdata { @@ -1004,6 +1006,13 @@ static int cqspi_indirect_write_execute(struct cqspi_flash_pdata *f_pdata, if (cqspi->wr_delay) ndelay(cqspi->wr_delay); + /* + * If a hazard exists between the APB and AHB interfaces, perform a + * dummy readback from the controller to ensure synchronization. + */ + if (cqspi->apb_ahb_hazard) + readl(reg_base + CQSPI_REG_INDIRECTWR); + while (remaining > 0) { size_t write_words, mod_bytes; @@ -1734,6 +1743,8 @@ static int cqspi_probe(struct platform_device *pdev) cqspi->wr_completion = false; if (ddata->quirks & CQSPI_SLOW_SRAM) cqspi->slow_sram = true; + if (ddata->quirks & CQSPI_NEEDS_APB_AHB_HAZARD_WAR) + cqspi->apb_ahb_hazard = true; if (of_device_is_compatible(pdev->dev.of_node, "xlnx,versal-ospi-1.0")) @@ -1859,6 +1870,10 @@ static const struct cqspi_driver_platdata versal_ospi = { .get_dma_status = cqspi_get_versal_dma_status, }; +static const struct cqspi_driver_platdata pensando_cdns_qspi = { + .quirks = CQSPI_NEEDS_APB_AHB_HAZARD_WAR | CQSPI_DISABLE_DAC_MODE, +}; + static const struct of_device_id cqspi_dt_ids[] = { { .compatible = "cdns,qspi-nor", @@ -1884,6 +1899,10 @@ static const struct of_device_id cqspi_dt_ids[] = { .compatible = "intel,socfpga-qspi", .data = &socfpga_qspi, }, + { + .compatible = "amd,pensando-elba-qspi", + .data = &pensando_cdns_qspi, + }, { /* end of table */ } }; From patchwork Thu Mar 23 00:06:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brad Larson X-Patchwork-Id: 73721 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:604a:0:0:0:0:0 with SMTP id j10csp2646864wrt; Wed, 22 Mar 2023 17:33:20 -0700 (PDT) X-Google-Smtp-Source: AK7set+vVZMlK/uLQK0/r7yGvnnxWHcyTNBjeidMUSlv0qzPVusfSEqvTehuIeCEngP0d9emEleT X-Received: by 2002:a17:906:d8ba:b0:933:32a9:bfb2 with SMTP id qc26-20020a170906d8ba00b0093332a9bfb2mr7814429ejb.57.1679531600672; Wed, 22 Mar 2023 17:33:20 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1679531600; cv=pass; d=google.com; s=arc-20160816; b=DZAai6BI9rkWazWMFQT0cj/vuxpvEE4dPMw3CGzwqraJ0T0KmHHRhj7RZoCjAj5/no XGKFtgr6gTzyqKNSQkMbrwsDyYS/4joA6DOIHvMwOF95kAngaPHcRuQFjG/J9Kapiz2Z cYNdkRIG1qSGDH+emXatz7ErI+qUXbcMCaL18J7e65OL9te+5TxWRWlFr9Gxkl+cCs5/ 7EIUVXLTodWBkJlEnlKUZmk11AqVHnuGTGh+gYMeFvkCaV5/fmgcCPBs5G6IadcxUV3d ROmXucK9aGAHthh3SNy5Y053+84wSPPEY64wFlgTs0UVilgPdJzxGcNqU7FXr7fPEDbI Wlng== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=UYkoSlbMMUE1LcDfRYmOgiXWrpEnjJ0YKyuk1LOG4Ns=; b=IxgMmpYJCtqEfJtiFc7H+sqD0tvevE34EqxWQTLPcCByvS5Il6PAe3E7e7TKR/edRh VMwsEsg4NZouaepFZsgcl2PiiXwSaOVHc70Oh+Dld08bOaNKjuWnqHH1OZFsLZHPqCsA FuwAD1axCo+xYi7bhBXoeptW4xo/XH+Qw58fF6QmGtu8napIBtUhKkndAbIWUuM9woT9 CRBp9Z8GA76Le3D04Aq3k0x8Vi95EYdRAxbEZVCtNW/C4mJ62+CMq59SBOTaPTO8KjFO eTKhwY7zG9vhWQi5lE15n3StSPF3jKRiaAWgMz09P7XbYApRB/DazEnGfKNFiKbEZjDH dsrg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=RSa1bRHU; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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Wed, 22 Mar 2023 19:09:37 -0500 From: Brad Larson To: CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v12 10/15] spi: dw: Add support for AMD Pensando Elba SoC Date: Wed, 22 Mar 2023 17:06:52 -0700 Message-ID: <20230323000657.28664-11-blarson@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230323000657.28664-1-blarson@amd.com> References: <20230323000657.28664-1-blarson@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF000100D3:EE_|IA0PR12MB8647:EE_ X-MS-Office365-Filtering-Correlation-Id: 6404ce8e-3265-46f8-8508-08db2b32e614 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: CV4MTeJz/rPCkS97zsoS7LRSsru/KNI+hugmHdpFSpSbMZOgPgywoVn2Hb4Eq/geejCnSZoEYcCAxA0bjRNCUJnQyV+b0TqugzM7luwneOnVj7mnZ5RB6K2i4NCXqOLqIhBWI4Ly/jMAzW1EQ9ivOt4Vof1RB2F6ImjRTp6yGh5dIwhtSQVULO+ynumQKKBtXQQDtbQwjojfKGu6jTDVdVWCQqstGPARrhxCzgs0saeFuvGkr9mJ7uQxeSEKbN0ZTX7w/I9VkcfQNYTsq+XhCJsnCRSVip8RHbe+pXSiA3BWLimG7b2mkJ4u+1gPQHwkitvGbJy3IpJrpYjp4iPu2J+CAtI7RUY2jJrN2eOyDiBYMHBHua1nO+LBebPd1Cule49EIqp0oF8H/5BVT535Dj3jeqVRTocRsfv7+jqsYfqW2lGC2gr3WFMu2xnxwn+Em8ta3vzziJPx8GDfhey1WrNDj9LVtO/r9R6lQiUmzqZWURwTOYFhv9qq/pHM1BCG+B6qfi6fqgzsj0pXJyPjBsvVat0kmZ3r6CTPgY7LY2L6+mbZwOQBf0VfV1AGtgc6M+tvLcYBYWYyAH1Fl03qLZVOGfWOUbaRckhAVGfNUEkOvKZhUBAbCULogJ/nGNzAMFjah/Lyhr/p3K6Ixoht3euRyXrYM0PUY2igpEPCHssE5pnvGhDwFPGgaMreiUs6EZ8WMEuiEFPZ4hfMVmIkEuFre6NIPNmfYbMxga741LA= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230025)(4636009)(376002)(136003)(396003)(39860400002)(346002)(451199018)(36840700001)(40470700004)(46966006)(82310400005)(82740400003)(2616005)(16526019)(1076003)(26005)(6666004)(36756003)(336012)(7406005)(2906002)(7416002)(356005)(47076005)(426003)(81166007)(5660300002)(8936002)(36860700001)(41300700001)(40460700003)(83380400001)(478600001)(40480700001)(54906003)(186003)(6916009)(70586007)(316002)(8676002)(4326008)(70206006)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Mar 2023 00:09:41.0895 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6404ce8e-3265-46f8-8508-08db2b32e614 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF000100D3.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8647 X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761116527759858266?= X-GMAIL-MSGID: =?utf-8?q?1761116527759858266?= The AMD Pensando Elba SoC includes a DW apb_ssi v4 controller with device specific chip-select control. The Elba SoC provides four chip-selects where the native DW IP supports two chip-selects. The Elba DW_SPI instance has two native CS signals that are always overridden. Signed-off-by: Brad Larson Reviewed-by: Serge Semin --- v12 changes: - Add a newline in function dw_spi_elba_init() v11 changes: - Simplify dw_spi_elb_init by using syscon_regmap_lookup_by_phandle() v10 changes: - Delete struct dw_spi_elba, use regmap directly in priv v9 changes: - Add use of macros GENMASK() and BIT() - Change ELBA_SPICS_SHIFT() to ELBA_SPICS_OFFSET() --- drivers/spi/spi-dw-mmio.c | 58 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c index 26c40ea6dd12..8cfad64b5463 100644 --- a/drivers/spi/spi-dw-mmio.c +++ b/drivers/spi/spi-dw-mmio.c @@ -53,6 +53,20 @@ struct dw_spi_mscc { void __iomem *spi_mst; /* Not sparx5 */ }; +/* + * Elba SoC does not use ssi, pin override is used for cs 0,1 and + * gpios for cs 2,3 as defined in the device tree. + * + * cs: | 1 0 + * bit: |---3-------2-------1-------0 + * | cs1 cs1_ovr cs0 cs0_ovr + */ +#define ELBA_SPICS_REG 0x2468 +#define ELBA_SPICS_OFFSET(cs) ((cs) << 1) +#define ELBA_SPICS_MASK(cs) (GENMASK(1, 0) << ELBA_SPICS_OFFSET(cs)) +#define ELBA_SPICS_SET(cs, val) \ + ((((val) << 1) | BIT(0)) << ELBA_SPICS_OFFSET(cs)) + /* * The Designware SPI controller (referred to as master in the documentation) * automatically deasserts chip select when the tx fifo is empty. The chip @@ -237,6 +251,49 @@ static int dw_spi_canaan_k210_init(struct platform_device *pdev, return 0; } +static void dw_spi_elba_override_cs(struct regmap *syscon, int cs, int enable) +{ + regmap_update_bits(syscon, ELBA_SPICS_REG, ELBA_SPICS_MASK(cs), + ELBA_SPICS_SET(cs, enable)); +} + +static void dw_spi_elba_set_cs(struct spi_device *spi, bool enable) +{ + struct dw_spi *dws = spi_master_get_devdata(spi->master); + struct dw_spi_mmio *dwsmmio = container_of(dws, struct dw_spi_mmio, dws); + struct regmap *syscon = dwsmmio->priv; + u8 cs; + + cs = spi->chip_select; + if (cs < 2) + dw_spi_elba_override_cs(syscon, spi->chip_select, enable); + + /* + * The DW SPI controller needs a native CS bit selected to start + * the serial engine. + */ + spi->chip_select = 0; + dw_spi_set_cs(spi, enable); + spi->chip_select = cs; +} + +static int dw_spi_elba_init(struct platform_device *pdev, + struct dw_spi_mmio *dwsmmio) +{ + struct regmap *syscon; + + syscon = syscon_regmap_lookup_by_phandle(dev_of_node(&pdev->dev), + "amd,pensando-elba-syscon"); + if (IS_ERR(syscon)) + return dev_err_probe(&pdev->dev, PTR_ERR(syscon), + "syscon regmap lookup failed\n"); + + dwsmmio->priv = syscon; + dwsmmio->dws.set_cs = dw_spi_elba_set_cs; + + return 0; +} + static int dw_spi_mmio_probe(struct platform_device *pdev) { int (*init_func)(struct platform_device *pdev, @@ -352,6 +409,7 @@ static const struct of_device_id dw_spi_mmio_of_match[] = { { .compatible = "intel,thunderbay-ssi", .data = dw_spi_intel_init}, { .compatible = "microchip,sparx5-spi", dw_spi_mscc_sparx5_init}, { .compatible = "canaan,k210-spi", dw_spi_canaan_k210_init}, + { .compatible = "amd,pensando-elba-spi", .data = dw_spi_elba_init}, { /* end of table */} }; MODULE_DEVICE_TABLE(of, dw_spi_mmio_of_match); From patchwork Thu Mar 23 00:06:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brad Larson X-Patchwork-Id: 73713 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:604a:0:0:0:0:0 with SMTP id j10csp2640268wrt; Wed, 22 Mar 2023 17:13:03 -0700 (PDT) X-Google-Smtp-Source: AK7set8+4FROHcatCXOhakJz+dK+yIarJKVGNSIOlcITVKeHQ+SepstQt2SkZm0NYFb0GUTD9crq X-Received: by 2002:a17:906:bcce:b0:933:89a1:57e6 with SMTP id lw14-20020a170906bcce00b0093389a157e6mr8594741ejb.26.1679530383172; Wed, 22 Mar 2023 17:13:03 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1679530383; cv=pass; d=google.com; s=arc-20160816; b=AeAs5kVnwSjNX9pHzdjhj2SDf943aRlJC0U2efaBELebfsuKpMVhx4SItVFVI7z48J ZbVw62KkoyL5qq8iMlOnTm4sGMS8OxDtPjDrvKA+YrYX022A8Nq8jIx1sje8aLthW3k6 JrpnTsXobxJUStgPkQhZaoN90P0zWUvO0EKMIva5lKuZmg38rSmpmvVq2Yog6/RjkfsG 1oOy/rJKRFYPxFoBC4egUX3/SAPLkCWAtiqqRNkHyJQnkTY67TXnbkIdyP8RynOqF5wh PNvAHbw32n+Sd1TFibtJvr6VLrXujcv+bS+3cx3FcxdJpXUr7myuHraiuK/RKvlFkPfP EG1Q== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=ymfACAjSLWbCk+4U3bvrCLTQlZYsf0VDrwtsvVsOjLE=; b=goCipwm5L1/55th7GISkxhoPPwnODlZhvGDR6CRga0ASZC5uKh87DOZiLUHq4mL5fZ SRWkDkAxUU/NigyFavPLdWa/+yPM4lXa8YdD+zFhhkTgctKeYIlg9pLpMV2ys/Wlem47 4spnJbOYUSpVGNLeJjaZ3QGP4mNFtxXXbcjdzmzpY1l4zofSj07Q5iIzlTp+wv30FOvp xPrjlp/Ju5HYse8UiHAcFFTJncOmwnKqdXW1yS1C2z3SjEVc0uPCRpf3+Wl4fzYgrO4W XYiTXGBXBedUGLi2SttGpuVrpJRQV93M2wcNN87FGdhdyBGuHncdrtK+Q2b1mrJzHEBj oUeQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=xQLmccMV; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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Wed, 22 Mar 2023 19:09:57 -0500 From: Brad Larson To: CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v12 11/15] mmc: sdhci-cadence: Enable device specific override of writel() Date: Wed, 22 Mar 2023 17:06:53 -0700 Message-ID: <20230323000657.28664-12-blarson@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230323000657.28664-1-blarson@amd.com> References: <20230323000657.28664-1-blarson@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF000100D0:EE_|BL0PR12MB5506:EE_ X-MS-Office365-Filtering-Correlation-Id: 0bdbfc15-741f-4fe6-6d47-08db2b32f1c4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: uzI6ke5ikwd2dHSVTV1j9PvcvYw+A+eOGQYCx0oxrJ9DwoIpuQhLyCHj4djG4bb6HEVLds4+Jr6pljoUEYADapcZ8C3t7TXgvsud7sCiLj3q7M7F/lwoMxkbF2R4mmYQN5r3c/h0PaaNjJTQ99NCC6Yr2LQ4IrG8i46uftBKUUx3beqAsNNZnTZohHwA+U0D/MresNTPfQ5KXaWgL8rpiJ2IEqptGJ5k2mH0I3R/VSkhqpcHq1fZgTKlOhrO0Mj14QvBx1sfb7ZFBsycoT0oLeNgpafdE7pOrbtl2lb5KlBz0DwlZgBYYw5qClYbSmEcEznG35XDi+P9JKSFrTpTBXz3/H6fqE06a0dcdk3c5EsEsAidCB2kagWcMOUGTJNxy+0bGd77cS0jlpKIvYtrpvL2uqO4uefjVQ7X8RLgDwa+KgaDCKKtE7lQjHlFUCDVh+U+e3tezBKjpYTvl+39ice/Fe1FLcQM7pCsKjsioJhyMMrrWr5E0biPWrGe3Ea5StIr+yj63vjV1JgyMIW9ACa7uET7FqgE5BoabTYJ05lEKv862wvvoOE6ZpepOArpKBG7/itJUlnX4KWnpITiN3DNP6YvvjjZfeegrhmAoKzTS0NJHF3EYTSg0vCpAhFsmL7OvmxIesxUxuqs5HVFzGcGnwXXgYwb9k8Q0cVTF4bA6CYEWdphijHKOyxeKm1LwJZyYjjRmf/X1nh84VfIUKJ7iVFGsGOEJZSjJ2nARVQ= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230025)(4636009)(396003)(136003)(346002)(39860400002)(376002)(451199018)(46966006)(40470700004)(36840700001)(7416002)(5660300002)(8936002)(7406005)(41300700001)(36860700001)(82310400005)(40480700001)(36756003)(356005)(40460700003)(82740400003)(81166007)(2906002)(47076005)(16526019)(336012)(1076003)(83380400001)(6666004)(426003)(478600001)(2616005)(186003)(26005)(4326008)(54906003)(316002)(70206006)(8676002)(6916009)(70586007)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Mar 2023 00:10:00.6973 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0bdbfc15-741f-4fe6-6d47-08db2b32f1c4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF000100D0.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR12MB5506 X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761115250758836583?= X-GMAIL-MSGID: =?utf-8?q?1761115250758836583?= SoCs with device specific Cadence implementation, such as setting byte-enables before the write, need to override writel(). Add a callback where the default is writel() for all existing chips. Signed-off-by: Brad Larson Acked-by: Adrian Hunter --- v10 changes: - The 1st patch adding private writel() is unchanged. The 2nd patch is split into two patches to provide for device specific init in one patch with no effect on existing designs. Then add the pensando support into the next patch. Then the 4th patch is mmc hardware reset support which is unchanged. v9 changes: - No change to this patch but as some patches are deleted and this is a respin the three successive patches to sdhci-cadence.c are patches 12, 13, and 14 which do the following: 1. Add ability for Cadence specific design to have priv writel(). 2. Add Elba SoC support that requires its own priv writel() for byte-lane control . 3. Add support for mmc hardware reset. --- drivers/mmc/host/sdhci-cadence.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c index 6f2de54a5987..708d4297f241 100644 --- a/drivers/mmc/host/sdhci-cadence.c +++ b/drivers/mmc/host/sdhci-cadence.c @@ -67,6 +67,7 @@ struct sdhci_cdns_phy_param { struct sdhci_cdns_priv { void __iomem *hrs_addr; bool enhanced_strobe; + void (*priv_writel)(struct sdhci_cdns_priv *priv, u32 val, void __iomem *reg); unsigned int nr_phy_params; struct sdhci_cdns_phy_param phy_params[]; }; @@ -90,6 +91,12 @@ static const struct sdhci_cdns_phy_cfg sdhci_cdns_phy_cfgs[] = { { "cdns,phy-dll-delay-strobe", SDHCI_CDNS_PHY_DLY_STROBE, }, }; +static inline void cdns_writel(struct sdhci_cdns_priv *priv, u32 val, + void __iomem *reg) +{ + writel(val, reg); +} + static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_priv *priv, u8 addr, u8 data) { @@ -104,17 +111,17 @@ static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_priv *priv, tmp = FIELD_PREP(SDHCI_CDNS_HRS04_WDATA, data) | FIELD_PREP(SDHCI_CDNS_HRS04_ADDR, addr); - writel(tmp, reg); + priv->priv_writel(priv, tmp, reg); tmp |= SDHCI_CDNS_HRS04_WR; - writel(tmp, reg); + priv->priv_writel(priv, tmp, reg); ret = readl_poll_timeout(reg, tmp, tmp & SDHCI_CDNS_HRS04_ACK, 0, 10); if (ret) return ret; tmp &= ~SDHCI_CDNS_HRS04_WR; - writel(tmp, reg); + priv->priv_writel(priv, tmp, reg); ret = readl_poll_timeout(reg, tmp, !(tmp & SDHCI_CDNS_HRS04_ACK), 0, 10); @@ -191,7 +198,7 @@ static void sdhci_cdns_set_emmc_mode(struct sdhci_cdns_priv *priv, u32 mode) tmp = readl(priv->hrs_addr + SDHCI_CDNS_HRS06); tmp &= ~SDHCI_CDNS_HRS06_MODE; tmp |= FIELD_PREP(SDHCI_CDNS_HRS06_MODE, mode); - writel(tmp, priv->hrs_addr + SDHCI_CDNS_HRS06); + priv->priv_writel(priv, tmp, priv->hrs_addr + SDHCI_CDNS_HRS06); } static u32 sdhci_cdns_get_emmc_mode(struct sdhci_cdns_priv *priv) @@ -223,7 +230,7 @@ static int sdhci_cdns_set_tune_val(struct sdhci_host *host, unsigned int val) */ for (i = 0; i < 2; i++) { tmp |= SDHCI_CDNS_HRS06_TUNE_UP; - writel(tmp, reg); + priv->priv_writel(priv, tmp, reg); ret = readl_poll_timeout(reg, tmp, !(tmp & SDHCI_CDNS_HRS06_TUNE_UP), @@ -386,6 +393,7 @@ static int sdhci_cdns_probe(struct platform_device *pdev) priv->nr_phy_params = nr_phy_params; priv->hrs_addr = host->ioaddr; priv->enhanced_strobe = false; + priv->priv_writel = cdns_writel; host->ioaddr += SDHCI_CDNS_SRS_BASE; host->mmc_host_ops.hs400_enhanced_strobe = sdhci_cdns_hs400_enhanced_strobe; From patchwork Thu Mar 23 00:06:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brad Larson X-Patchwork-Id: 73722 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:604a:0:0:0:0:0 with SMTP id j10csp2647632wrt; Wed, 22 Mar 2023 17:35:36 -0700 (PDT) X-Google-Smtp-Source: AK7set9+A5+jehJc2T7M0T+yRWHHOAvpqz+YigIoNwq9cYuVv0TpvwV3J4wRgLBiyxDFT4xlAZaz X-Received: by 2002:aa7:d596:0:b0:4fd:7f6f:3179 with SMTP id r22-20020aa7d596000000b004fd7f6f3179mr7898344edq.3.1679531736798; Wed, 22 Mar 2023 17:35:36 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1679531736; cv=pass; d=google.com; s=arc-20160816; b=LTaqrzPXjZEDKUyHysiUOXK58Sj8XjXzhPYMlJEIyN48pfxkpJvNv+p2/NJzhhGKcj K+3zQjaKCU1BKpQZwKqP56dVAaTFas0ubdlblTlLI5+hBIkSbKXs155M3Xv0gXIdRJv4 ERjSP2w9XuijHtwrlkmI06fedrsrWfSduHLz3VQoH/Vj4msQFSpRUkBYPo+MmTC4rVtf tS5a/dYe51gd/cBxmqFP6FLaQz5QSx5AHjSqrOAFmmfQ6bqfgYpAM1p90nL4BXq6ThuM ll4Ph3Q62QxdCo5kdLCoBSeYSmX6Mspf19A9956pYnThsuFDSJX0TvCDjUCjji1+Dr7N oPvQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=1MDls9ITIFGGKkwfzufckKk9fjZ1Lh0w+zr7TA/z5wc=; b=tk2rNJ8jcua+MgeE4ifZXJlZj2stzkIjgDgXfOn9W1tOgdHyYgjbpHWgbOMb3uoMoO yTrIq3oCw0sXus1Q4wtO+bgeVGdpRuVzYzsJW48EYE6K5X4znPgIuvIkgRYwjAOVysGR oNQ6a/3+34mo8sUhUa1PQDPdcqyu97cStFIBwo8KLCENWCgseGw7ccYiKYaNPzU8lAm7 oczVBfi2F2yCK117QOPK84HwjIXPD39nQaJVrTJ05a9VidLXu04tnscGX4NeT/sNjHob ayYI6hDj/Ee2KxmOjsnNPy9riWhtfp3RjfHmkP4GrpHdFv9qvburtArj0GILzPlVErJW yKpw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=Jnymu99B; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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Wed, 22 Mar 2023 19:10:16 -0500 From: Brad Larson To: CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v12 12/15] mmc: sdhci-cadence: Support device specific init during probe Date: Wed, 22 Mar 2023 17:06:54 -0700 Message-ID: <20230323000657.28664-13-blarson@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230323000657.28664-1-blarson@amd.com> References: <20230323000657.28664-1-blarson@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF000100D3:EE_|MN2PR12MB4517:EE_ X-MS-Office365-Filtering-Correlation-Id: 519749aa-39ef-412f-539a-08db2b32fcef X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: CrdNSGjl+Xzyf1NStkBP1cYKS5J4NHFTzF27gfPDPL3jNeJdl94cpL4bMt6Nl/xNugF/12H2HPhmjPlzGaeqS9WricERWLTdRN4lLihxFM/HY4zR+xs5vdRbu60gZq6/xK70fC5I6Mw7Jg5bDgmjYUmmhTsKI5gKg1wnJf3mlIhWD1suwGZS7EATcg0bl+FmkIQxOVJq55C8JAu2wpeiNAAvpXwU2/jO9NdLClMNMDuNvniC5HhqlhWFvm0okFIsMDbvP61k2yLDi7Tczig0iNhqQ5JEOERMt2RwHqcB2qX9boi8v/Rws3xfU8DQhKGnSdVqhtNaAYhhHng3q2YX/Z8chCCCQhFaTu4z0//GCpp9sdAlvkFiPVjQNnvofeG8XO0CZJZ1MmJCyB0YRt429MlQVX0PowoWZyFy/Qg6lNlUQd0MUsxxv4O742jBn2u66OHOHkIFeWA+KL/kk/CPMEcrfcZIf+ikOzydWlpQMAF+MVrZl/5uTSvgVf6OAy+ZF4ZP0uaV4YTzc89N+FrmvsoRebDOZP1rL1xzUmS35iKooNwvJmhMBKOtq7HotKRnaEU2H8N/HCpz/QJ5H8lvRTqnG3a+iPrxaWIRQFKLKwjz2u/rC8hC+cMjlZ8letknoKt/zzMS5C4+Bu0oNZlFX+nSaYbVBFlGM0pRvm9zNB6KBdXbCbQ+gp95tIx3zOsRwwdLgc0E0AIXPh1n4EgCGlV86qQPBA8WQtimu68lwd8= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230025)(4636009)(396003)(376002)(39860400002)(346002)(136003)(451199018)(36840700001)(40470700004)(46966006)(82740400003)(356005)(40480700001)(81166007)(40460700003)(186003)(16526019)(54906003)(336012)(2906002)(316002)(47076005)(83380400001)(36860700001)(426003)(41300700001)(82310400005)(70586007)(6916009)(4326008)(70206006)(2616005)(8676002)(26005)(1076003)(7416002)(7406005)(478600001)(6666004)(8936002)(5660300002)(36756003)(36900700001);DIR:OUT;SFP:1101; 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Add an init() into sdhci_cdns_drv_data for platform specific device initialization in the device probe which is not used for existing devices. Signed-off-by: Brad Larson Acked-by: Adrian Hunter --- v10 changes: - New patch to provide for platform specific init() with no change to existing designs. --- drivers/mmc/host/sdhci-cadence.c | 32 +++++++++++++++++++++++--------- 1 file changed, 23 insertions(+), 9 deletions(-) diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c index 708d4297f241..c528a25f48b8 100644 --- a/drivers/mmc/host/sdhci-cadence.c +++ b/drivers/mmc/host/sdhci-cadence.c @@ -77,6 +77,11 @@ struct sdhci_cdns_phy_cfg { u8 addr; }; +struct sdhci_cdns_drv_data { + int (*init)(struct platform_device *pdev); + const struct sdhci_pltfm_data pltfm_data; +}; + static const struct sdhci_cdns_phy_cfg sdhci_cdns_phy_cfgs[] = { { "cdns,phy-input-delay-sd-highspeed", SDHCI_CDNS_PHY_DLY_SD_HS, }, { "cdns,phy-input-delay-legacy", SDHCI_CDNS_PHY_DLY_SD_DEFAULT, }, @@ -325,13 +330,17 @@ static const struct sdhci_ops sdhci_cdns_ops = { .set_uhs_signaling = sdhci_cdns_set_uhs_signaling, }; -static const struct sdhci_pltfm_data sdhci_cdns_uniphier_pltfm_data = { - .ops = &sdhci_cdns_ops, - .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, +static const struct sdhci_cdns_drv_data sdhci_cdns_uniphier_drv_data = { + .pltfm_data = { + .ops = &sdhci_cdns_ops, + .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, + }, }; -static const struct sdhci_pltfm_data sdhci_cdns_pltfm_data = { - .ops = &sdhci_cdns_ops, +static const struct sdhci_cdns_drv_data sdhci_cdns_drv_data = { + .pltfm_data = { + .ops = &sdhci_cdns_ops, + }, }; static void sdhci_cdns_hs400_enhanced_strobe(struct mmc_host *mmc, @@ -357,7 +366,7 @@ static void sdhci_cdns_hs400_enhanced_strobe(struct mmc_host *mmc, static int sdhci_cdns_probe(struct platform_device *pdev) { struct sdhci_host *host; - const struct sdhci_pltfm_data *data; + const struct sdhci_cdns_drv_data *data; struct sdhci_pltfm_host *pltfm_host; struct sdhci_cdns_priv *priv; struct clk *clk; @@ -376,10 +385,10 @@ static int sdhci_cdns_probe(struct platform_device *pdev) data = of_device_get_match_data(dev); if (!data) - data = &sdhci_cdns_pltfm_data; + data = &sdhci_cdns_drv_data; nr_phy_params = sdhci_cdns_phy_param_count(dev->of_node); - host = sdhci_pltfm_init(pdev, data, + host = sdhci_pltfm_init(pdev, &data->pltfm_data, struct_size(priv, phy_params, nr_phy_params)); if (IS_ERR(host)) { ret = PTR_ERR(host); @@ -397,6 +406,11 @@ static int sdhci_cdns_probe(struct platform_device *pdev) host->ioaddr += SDHCI_CDNS_SRS_BASE; host->mmc_host_ops.hs400_enhanced_strobe = sdhci_cdns_hs400_enhanced_strobe; + if (data->init) { + ret = data->init(pdev); + if (ret) + goto free; + } sdhci_enable_v4_mode(host); __sdhci_read_caps(host, &version, NULL, NULL); @@ -461,7 +475,7 @@ static const struct dev_pm_ops sdhci_cdns_pm_ops = { static const struct of_device_id sdhci_cdns_match[] = { { .compatible = "socionext,uniphier-sd4hc", - .data = &sdhci_cdns_uniphier_pltfm_data, + .data = &sdhci_cdns_uniphier_drv_data, }, { .compatible = "cdns,sd4hc" }, { /* sentinel */ } From patchwork Thu Mar 23 00:06:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brad Larson X-Patchwork-Id: 73718 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:604a:0:0:0:0:0 with SMTP id j10csp2644261wrt; Wed, 22 Mar 2023 17:25:13 -0700 (PDT) Authentication-Results: mx.google.com; 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Wed, 22 Mar 2023 19:10:31 -0500 From: Brad Larson To: CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v12 13/15] mmc: sdhci-cadence: Add AMD Pensando Elba SoC support Date: Wed, 22 Mar 2023 17:06:55 -0700 Message-ID: <20230323000657.28664-14-blarson@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230323000657.28664-1-blarson@amd.com> References: <20230323000657.28664-1-blarson@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF000100D2:EE_|MW4PR12MB5627:EE_ X-MS-Office365-Filtering-Correlation-Id: fb2008a5-bb39-4e9b-e457-08db2b3305a9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: luoOiRiGmtwpMoPdG3HlX3wOrCnPgqFd5IgNfdDbFKEKQiJ7DmI7ySCOcnfGEMQvSb99JOiz9BEjAgR/98fahKbO4PhybxqYHyFmJSFKWSfuE1LdsOmmyshSIaCnp7z+0FmJ1GcJePpWeLe6UOTDvSHoNomfBNaeHlalZYQDVEslr0P40fiAvfvlpv89HW50uDDK5O8LV/kva/t44bmqIQ7glrP00+JfwyWs/Z3EdtVlXzuwLtcdwiYB6SqjTg6l9DBr6ccU9LMsRebEE6O9UKpwWZyeawwnB19VokO06GgWHWtorxMfyqv7gJ1UJz8i9Wt2dkuZAtYbwD734zgOKu0IBK4ek+UE6hT/1BxBnZ5qnU8cArf2gif2Y4F5VrsMcohmrrCFnBe7istl2bb7M10sykclMnp4uq6jFxPRbqRIOgVRsO0M50q5x9hiaaKxZr49bwQQwTFyehDj3RlGUcuKCC8Y475YnOnkYfRxNPwOXgAXnSzkVOuL73LuL/ZV/hpe+FnMWXqEvQqYV6C3mnRaSaJdEd+T8x2/mnuvTt+ZchZ7gk/ebIgMrDw5oa2nvaAVOJSi3z2TPeR1g3H36Sj97DT71f4qdzXrkODJrX9Ao5mX6HS1MLyMmGZ9Fdwa471wXEPjbyNKFCf4zVGPk3P96jAQ9lmZaeLp7XAL2F5SASCNzD4aCD66C7zbV2/yZCBEFxPV2Vg+L/YkfWZZk+xmW1ImV7MfCyr/uGiGCCg= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230025)(4636009)(39860400002)(136003)(396003)(376002)(346002)(451199018)(46966006)(36840700001)(40470700004)(36860700001)(41300700001)(54906003)(7416002)(7406005)(5660300002)(47076005)(4326008)(6916009)(8676002)(2616005)(70586007)(70206006)(82310400005)(8936002)(81166007)(82740400003)(316002)(16526019)(426003)(2906002)(83380400001)(336012)(186003)(40460700003)(40480700001)(6666004)(356005)(1076003)(26005)(478600001)(36756003)(36900700001);DIR:OUT;SFP:1101; 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Select MMC_SDHCI_IO_ACCESSORS for MMC_SDHCI_CADENCE which allows Elba SoC sdhci_elba_ops to overwrite the SDHCI IO memory accessors Signed-off-by: Brad Larson Acked-by: Adrian Hunter --- v11 changes: - Remove elba-drv_init() call to platform_get_resource() since that check is done inside devm_platform_ioremap_resource() - Move spin_lock_init() before error check - Remove extra parentheses v10 changes: - Add Elba specific support into this 3rd patch. This builds on the private writel() enabled in patch 1 followed by platform specific init() in patch 2. - Specify when first used the reason for the spinlock use to order byte-enable prior to write data. --- drivers/mmc/host/Kconfig | 1 + drivers/mmc/host/sdhci-cadence.c | 96 ++++++++++++++++++++++++++++++++ 2 files changed, 97 insertions(+) diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index 4745fe217ade..9f793892123c 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -255,6 +255,7 @@ config MMC_SDHCI_CADENCE tristate "SDHCI support for the Cadence SD/SDIO/eMMC controller" depends on MMC_SDHCI_PLTFM depends on OF + select MMC_SDHCI_IO_ACCESSORS help This selects the Cadence SD/SDIO/eMMC driver. diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c index c528a25f48b8..c0024d1e69a8 100644 --- a/drivers/mmc/host/sdhci-cadence.c +++ b/drivers/mmc/host/sdhci-cadence.c @@ -66,6 +66,8 @@ struct sdhci_cdns_phy_param { struct sdhci_cdns_priv { void __iomem *hrs_addr; + void __iomem *ctl_addr; /* write control */ + spinlock_t wrlock; /* write lock */ bool enhanced_strobe; void (*priv_writel)(struct sdhci_cdns_priv *priv, u32 val, void __iomem *reg); unsigned int nr_phy_params; @@ -321,6 +323,89 @@ static void sdhci_cdns_set_uhs_signaling(struct sdhci_host *host, sdhci_set_uhs_signaling(host, timing); } +/* Elba control register bits [6:3] are byte-lane enables */ +#define ELBA_BYTE_ENABLE_MASK(x) ((x) << 3) + +/* + * The Pensando Elba SoC explicitly controls byte-lane enabling on writes + * which includes writes to the HRS registers. The write lock (wrlock) + * is used to ensure byte-lane enable, using write control (ctl_addr), + * occurs before the data write. + */ +static void elba_priv_writel(struct sdhci_cdns_priv *priv, u32 val, + void __iomem *reg) +{ + unsigned long flags; + + spin_lock_irqsave(&priv->wrlock, flags); + writel(ELBA_BYTE_ENABLE_MASK(0xf), priv->ctl_addr); + writel(val, reg); + spin_unlock_irqrestore(&priv->wrlock, flags); +} + +static void elba_write_l(struct sdhci_host *host, u32 val, int reg) +{ + elba_priv_writel(sdhci_cdns_priv(host), val, host->ioaddr + reg); +} + +static void elba_write_w(struct sdhci_host *host, u16 val, int reg) +{ + struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host); + u32 byte_enables; + unsigned long flags; + + byte_enables = GENMASK(1, 0) << (reg & 0x3); + spin_lock_irqsave(&priv->wrlock, flags); + writel(ELBA_BYTE_ENABLE_MASK(byte_enables), priv->ctl_addr); + writew(val, host->ioaddr + reg); + spin_unlock_irqrestore(&priv->wrlock, flags); +} + +static void elba_write_b(struct sdhci_host *host, u8 val, int reg) +{ + struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host); + u32 byte_enables; + unsigned long flags; + + byte_enables = BIT(0) << (reg & 0x3); + spin_lock_irqsave(&priv->wrlock, flags); + writel(ELBA_BYTE_ENABLE_MASK(byte_enables), priv->ctl_addr); + writeb(val, host->ioaddr + reg); + spin_unlock_irqrestore(&priv->wrlock, flags); +} + +static const struct sdhci_ops sdhci_elba_ops = { + .write_l = elba_write_l, + .write_w = elba_write_w, + .write_b = elba_write_b, + .set_clock = sdhci_set_clock, + .get_timeout_clock = sdhci_cdns_get_timeout_clock, + .set_bus_width = sdhci_set_bus_width, + .reset = sdhci_reset, + .set_uhs_signaling = sdhci_cdns_set_uhs_signaling, +}; + +static int elba_drv_init(struct platform_device *pdev) +{ + struct sdhci_host *host = platform_get_drvdata(pdev); + struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host); + void __iomem *ioaddr; + + host->mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_8_BIT_DATA; + spin_lock_init(&priv->wrlock); + + /* Byte-lane control register */ + ioaddr = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(ioaddr)) + return PTR_ERR(ioaddr); + + priv->ctl_addr = ioaddr; + priv->priv_writel = elba_priv_writel; + writel(ELBA_BYTE_ENABLE_MASK(0xf), priv->ctl_addr); + + return 0; +} + static const struct sdhci_ops sdhci_cdns_ops = { .set_clock = sdhci_set_clock, .get_timeout_clock = sdhci_cdns_get_timeout_clock, @@ -337,6 +422,13 @@ static const struct sdhci_cdns_drv_data sdhci_cdns_uniphier_drv_data = { }, }; +static const struct sdhci_cdns_drv_data sdhci_elba_drv_data = { + .init = elba_drv_init, + .pltfm_data = { + .ops = &sdhci_elba_ops, + }, +}; + static const struct sdhci_cdns_drv_data sdhci_cdns_drv_data = { .pltfm_data = { .ops = &sdhci_cdns_ops, @@ -477,6 +569,10 @@ static const struct of_device_id sdhci_cdns_match[] = { .compatible = "socionext,uniphier-sd4hc", .data = &sdhci_cdns_uniphier_drv_data, }, + { + .compatible = "amd,pensando-elba-sd4hc", + .data = &sdhci_elba_drv_data, + }, { .compatible = "cdns,sd4hc" }, { /* sentinel */ } }; From patchwork Thu Mar 23 00:06:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brad Larson X-Patchwork-Id: 73726 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:604a:0:0:0:0:0 with SMTP id j10csp2649172wrt; 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Wed, 22 Mar 2023 19:10:53 -0500 From: Brad Larson To: CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v12 14/15] mmc: sdhci-cadence: Support mmc hardware reset Date: Wed, 22 Mar 2023 17:06:56 -0700 Message-ID: <20230323000657.28664-15-blarson@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230323000657.28664-1-blarson@amd.com> References: <20230323000657.28664-1-blarson@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF000100D0:EE_|DM6PR12MB4909:EE_ X-MS-Office365-Filtering-Correlation-Id: 6df70512-ce8b-434b-d9a9-08db2b3312be X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 2RxSXhIl0qyY73ihWxKrZ32IRkCzY3BF+exF5vSGP7FnrmtSx2juE+lZoc44tmY/UxoI9EtMBcshuwr9HD3573OyMrWxZBf45fS8vV8tZ6QflGzUf70xkpxOxykLqfDRDqO01Nw5EnxTxU/ZkGyRZ6ldaCgzLLZWu6YKx4vNk0XbPc9pgi1vPLM4U9lU7lhsiIsdQQCYgAMRPVdyFnLtUufVDM5ivYu77gFM/iGZeW5+aP3cDz3IpshHhNE0mIa5zXzDbjQz/N8mrYiQys4X2c308SHpaS+bKkuJ4L5cEmlrJc8Jnm8VfWdU1k7ZMoZ7VAsfvfxMo4GWilOFIamnp5FzXuKYVFC0Hmd+9V98lOo4qohWYM8GSSORhaQCTr6B9R+iODyUPq8x0eVgEj4iX+yhzh77kB/dFq2Ihcq/BKLKMxia+1Yb4TmGA9PegBVOrSIIpj4UxmohsB7kqyGetHBMfFuDJeTnazw4wziZz3ylmqc8SdgRUD5YA6lCBEYhelpF3JTnGSSbT2gg77zp81BZxXbeGdtNgUeDNG0BgyjuAG4gnD9QKibNqSFZeuSbaX7UCOAr+eAQNX257nP44/FzldFK5M9D1UlxfxFrO+Nqek6auaeQOZVIxKDQheSoEKpqxD668X7I9dOhpTEAV9TcjnIlilK1gU7A6QdRYHAiefnMvyWHIG+zRDGnYrV6ZZV8A5JSZCT64hvUdyQCOua5ZJTl8Sbq4M7AQuNUu0k= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230025)(4636009)(136003)(376002)(346002)(39860400002)(396003)(451199018)(36840700001)(40470700004)(46966006)(7406005)(54906003)(47076005)(336012)(83380400001)(2616005)(82310400005)(426003)(316002)(8936002)(478600001)(1076003)(186003)(82740400003)(26005)(356005)(40480700001)(40460700003)(4326008)(6916009)(2906002)(81166007)(16526019)(70586007)(70206006)(7416002)(36860700001)(36756003)(5660300002)(8676002)(41300700001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Mar 2023 00:10:56.0412 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6df70512-ce8b-434b-d9a9-08db2b3312be X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF000100D0.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4909 X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761116987490539288?= X-GMAIL-MSGID: =?utf-8?q?1761116987490539288?= Add support for mmc hardware reset using a reset-controller that would need to be enabled in the device tree with a supporting driver. The default is disabled for all existing designs. Signed-off-by: Brad Larson Acked-by: Adrian Hunter Reviewed-by: Philipp Zabel --- v9 changes: - Previously patch 17/17 - Changed delay after reset_control_assert() from 9 to 3 usec - Renamed sdhci_mmc_hw_reset() to sdhci_cdns_mmc_hw_reset() --- drivers/mmc/host/sdhci-cadence.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c index c0024d1e69a8..0d8db1a54729 100644 --- a/drivers/mmc/host/sdhci-cadence.c +++ b/drivers/mmc/host/sdhci-cadence.c @@ -12,6 +12,7 @@ #include #include #include +#include #include "sdhci-pltfm.h" @@ -70,6 +71,7 @@ struct sdhci_cdns_priv { spinlock_t wrlock; /* write lock */ bool enhanced_strobe; void (*priv_writel)(struct sdhci_cdns_priv *priv, u32 val, void __iomem *reg); + struct reset_control *rst_hw; unsigned int nr_phy_params; struct sdhci_cdns_phy_param phy_params[]; }; @@ -455,6 +457,22 @@ static void sdhci_cdns_hs400_enhanced_strobe(struct mmc_host *mmc, SDHCI_CDNS_HRS06_MODE_MMC_HS400); } +static void sdhci_cdns_mmc_hw_reset(struct mmc_host *mmc) +{ + struct sdhci_host *host = mmc_priv(mmc); + struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host); + + dev_dbg(mmc_dev(host->mmc), "emmc hardware reset\n"); + + reset_control_assert(priv->rst_hw); + /* For eMMC, minimum is 1us but give it 3us for good measure */ + udelay(3); + + reset_control_deassert(priv->rst_hw); + /* For eMMC, minimum is 200us but give it 300us for good measure */ + usleep_range(300, 1000); +} + static int sdhci_cdns_probe(struct platform_device *pdev) { struct sdhci_host *host; @@ -518,6 +536,15 @@ static int sdhci_cdns_probe(struct platform_device *pdev) if (ret) goto free; + if (host->mmc->caps & MMC_CAP_HW_RESET) { + priv->rst_hw = devm_reset_control_get_optional_exclusive(dev, NULL); + if (IS_ERR(priv->rst_hw)) + return dev_err_probe(mmc_dev(host->mmc), PTR_ERR(priv->rst_hw), + "reset controller error\n"); + if (priv->rst_hw) + host->mmc_host_ops.card_hw_reset = sdhci_cdns_mmc_hw_reset; + } + ret = sdhci_add_host(host); if (ret) goto free; From patchwork Thu Mar 23 00:06:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brad Larson X-Patchwork-Id: 73727 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:604a:0:0:0:0:0 with SMTP id j10csp2649383wrt; Wed, 22 Mar 2023 17:41:19 -0700 (PDT) X-Google-Smtp-Source: AK7set+Jdr8bfXv8uRfQfEzBwRMhW0P/6AunEHcgDdvW2ttXLRZfXo0twkFcY7kd1meGYrw81OGP X-Received: by 2002:a17:906:fa06:b0:933:1702:a12b with SMTP id lo6-20020a170906fa0600b009331702a12bmr9546025ejb.17.1679532079163; Wed, 22 Mar 2023 17:41:19 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1679532079; cv=pass; d=google.com; s=arc-20160816; b=tBtlQdVCTF3MHabxvYS7NbuQLsnic6YFRn4uV2IQeu5Fv5xd39/lCJ8me9Gs3vqXA1 RZDXvVyxgRrttScuH6bmsyYxyN71v+2TPEcK0orvpeK7XcK1huFYS/Y1PZ462t2chMKP PzF+SK5gypxNlWf+JuIPcGtyWG7tkTbaqNOdC/01KX3+uqRt5lKM6ZqCtxo1L0BHD3Rm bL9zIwQdySg90SXCESyMeCauu+Jli6alVcrXHcpiHTx+UlUglX+NVq/Ka5XdTKLVP4vf PcO2glcj6KgM8lA4XGcYbecgZzoR/iCpQ1NC5imdgkKjABgE1xxibQNcf5y6l2uPGnFS /x0w== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=fMJ5ouM3RXZe6xXRXCMZmk2bZJxFPzmBPojtz6wi8nI=; b=FsUE0tHrTnzO7bp5paVIFcSUZwokmZS2nvAWbYhZ6kOXyeMKvveAz2XUqBW323EG6V uiOBxROaXMqPz5N+LOZtW2NTEYhS8nuwlRpoSytqnrV7ZW4B++OF+fL9YyAgs4Zm9Gwj dv+b4KvxHE3HbX0UfnexfeIgrCtbwTkFRgMThb+WHxd2fkAhovbz4Jw1CHLW4MZaWQan tenOuMZYvX420XK2aXdxkcJo0mGoZR0WoD1MctgzWx9jw79VqUIIanRprA8SliaBy7PN 8C/on6btuV4BHdj4hAADcM3+PBTidWomPnRa+Uzht6EW6zdMDj6UVSolZPmpv4oXeCwC 2h2g== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=bcHz4Pdt; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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Wed, 22 Mar 2023 19:11:29 -0500 From: Brad Larson To: CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v12 15/15] soc: amd: Add support for AMD Pensando SoC Controller Date: Wed, 22 Mar 2023 17:06:57 -0700 Message-ID: <20230323000657.28664-16-blarson@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230323000657.28664-1-blarson@amd.com> References: <20230323000657.28664-1-blarson@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF000100D3:EE_|PH7PR12MB8105:EE_ X-MS-Office365-Filtering-Correlation-Id: 9e8874c2-f841-4d36-f33d-08db2b332a66 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: uEdqdlZ4znygZ72VEj2Cvne02W9S/OQmjw3Ryq7WAZb3XPHh8mYxuO3its2PVTpNlkQsEMx7e0lmSYMzvGUiNCOYLBx7kXvNi+6MxSj5R72wrRhjxkbRzxkK0h4C1PGAxhpvic4s8mfoAuOn1Sxo2bwkN6QsFFOJ7EcRmQiXxpK1Hf1rLSefg5VquCT03IiT7YDovBnQ3hM6wC/ivQD9erdhrmng5pD2MQlmabFWRQlnr8VlJum0wp5rw5YDBOaSbg2TZNnQA+DVTloSQzNIRxTnZeD1xLEZssVKkuiKTHt2sY5BoalBkJoTvtjvOSbAOH55922HFFP/E32UKn2q6gIcGiI69fOW7Pfiyxc/OU7xFIqMJ05CYKicev0Mip3JnR3o9jn4+NCyztZEFgQzjGzD26ohimntL0oeWB+P6b57WenwXPgSh5sp3PECi2iBuQ8ovOmcqMmZ4hGrEv0W08QZMj0wLDJGJIAzI9+54IPLVtl7aDCvSQzE690nxOmWfsI8uD+IswGMZFaYJhVFlJYeQxFTose2QgH8SxXAujXM1jVvMSNKgTB/V7CxSl+2Ml0TZRj8N3+fZOuSjzXTQn2vFIoPnqeukC1y+wtWDYnU6lxfpNrXD3p9d1+nTUaznmx7tvtOmEuRmTDg3JWtBoG5AGPmCMGa5nbo2z5xYi4T4P4XqkhjNvAsOrgQ36zWU13+aV+iCjk/dpGihfDpR10Hj1mzThE2ZhmUzhwuUic= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230025)(4636009)(136003)(376002)(346002)(39860400002)(396003)(451199018)(46966006)(40470700004)(36840700001)(5660300002)(7416002)(7406005)(30864003)(36860700001)(41300700001)(82310400005)(40480700001)(36756003)(356005)(8936002)(82740400003)(81166007)(40460700003)(2906002)(6666004)(83380400001)(336012)(478600001)(426003)(47076005)(2616005)(186003)(16526019)(966005)(26005)(54906003)(1076003)(8676002)(4326008)(316002)(70586007)(70206006)(6916009)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Mar 2023 00:11:35.7304 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9e8874c2-f841-4d36-f33d-08db2b332a66 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF000100D3.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB8105 X-Spam-Status: No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO,SPF_HELO_PASS,SPF_NONE, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761117029513374157?= X-GMAIL-MSGID: =?utf-8?q?1761117029513374157?= The Pensando SoC controller is a SPI connected companion device that is present in all Pensando SoC board designs. The essential board management registers are accessed on chip select 0 with board mgmt IO support accessed using additional chip selects. Signed-off-by: Brad Larson --- v12 changes: - Fix gcc-12.1.0 warning: Reported-by: kernel test robot Link: https://lore.kernel.org/oe-kbuild-all/202303120925.SxLjwOd2-lkp@intel.com/ v11 changes: - Fix the compatible to be specific 'amd,pensando-elba-ctrl' v10 changes: - Different driver implementation specific to this Pensando controller device. - Moved to soc/amd directory under new name based on guidance. This driver is of no use to any design other than all Pensando SoC based cards. - Removed use of builtin_driver, can be built as a module. v9 changes: - Previously patch 14/17 - After the change to the device tree node and squashing reset-cells into the parent simplified this to not use any MFD API and move it to drivers/spi/pensando-sr.c. - Change the naming to remove elba since this driver is common for all Pensando SoC designs . - Default yes SPI_PENSANDO_SR for ARCH_PENSANDO --- drivers/soc/Kconfig | 1 + drivers/soc/Makefile | 1 + drivers/soc/amd/Kconfig | 16 ++ drivers/soc/amd/Makefile | 2 + drivers/soc/amd/pensando-ctrl.c | 380 +++++++++++++++++++++++++ include/uapi/linux/amd-pensando-ctrl.h | 30 ++ 6 files changed, 430 insertions(+) create mode 100644 drivers/soc/amd/Kconfig create mode 100644 drivers/soc/amd/Makefile create mode 100644 drivers/soc/amd/pensando-ctrl.c create mode 100644 include/uapi/linux/amd-pensando-ctrl.h diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index 4e176280113a..9e023f74e47c 100644 --- a/drivers/soc/Kconfig +++ b/drivers/soc/Kconfig @@ -2,6 +2,7 @@ menu "SOC (System On Chip) specific Drivers" source "drivers/soc/actions/Kconfig" +source "drivers/soc/amd/Kconfig" source "drivers/soc/amlogic/Kconfig" source "drivers/soc/apple/Kconfig" source "drivers/soc/aspeed/Kconfig" diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index 3b0f9fb3b5c8..8914530f2721 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -4,6 +4,7 @@ # obj-$(CONFIG_ARCH_ACTIONS) += actions/ +obj-y += amd/ obj-y += apple/ obj-y += aspeed/ obj-$(CONFIG_ARCH_AT91) += atmel/ diff --git a/drivers/soc/amd/Kconfig b/drivers/soc/amd/Kconfig new file mode 100644 index 000000000000..9fc03de49f11 --- /dev/null +++ b/drivers/soc/amd/Kconfig @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-only +menu "AMD Pensando SoC drivers" + +config AMD_PENSANDO_CTRL + tristate "AMD Pensando SoC Controller" + depends on SPI_MASTER=y + depends on (ARCH_PENSANDO && OF) || COMPILE_TEST + default y if ARCH_PENSANDO + select REGMAP_SPI + select MFD_SYSCON + help + Enables AMD Pensando SoC controller device support. This is a SPI + attached companion device in all Pensando SoC board designs which + provides essential board control/status registers and management IO + support. +endmenu diff --git a/drivers/soc/amd/Makefile b/drivers/soc/amd/Makefile new file mode 100644 index 000000000000..a2de0424f68d --- /dev/null +++ b/drivers/soc/amd/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_AMD_PENSANDO_CTRL) += pensando-ctrl.o diff --git a/drivers/soc/amd/pensando-ctrl.c b/drivers/soc/amd/pensando-ctrl.c new file mode 100644 index 000000000000..91ed0ee424c9 --- /dev/null +++ b/drivers/soc/amd/pensando-ctrl.c @@ -0,0 +1,380 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * AMD Pensando SoC Controller + * + * Userspace interface and reset driver support for SPI connected Pensando SoC + * controller device. This device is present in all Pensando SoC designs and + * contains board control/status regsiters and management IO support. + * + * Copyright 2023 Advanced Micro Devices, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct penctrl_device { + struct spi_device *spi_dev; + struct reset_controller_dev rcdev; +}; + +static DEFINE_MUTEX(spi_lock); +static dev_t penctrl_devt; +static struct penctrl_device *penctrl; +static struct class *penctrl_class; + +static long +penctrl_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) +{ + struct spi_transfer t[2] = { 0 }; + struct penctrl_device *penctrl; + struct penctrl_spi_xfer *msg; + struct spi_device *spi_dev; + unsigned int num_msgs; + struct spi_message m; + u8 tx_buf[PENCTRL_MAX_MSG_LEN]; + u8 rx_buf[PENCTRL_MAX_MSG_LEN]; + u32 size; + int ret; + + /* Check for a valid command */ + if (_IOC_TYPE(cmd) != PENCTRL_IOC_MAGIC) + return -ENOTTY; + + if (_IOC_NR(cmd) > PENCTRL_IOC_MAXNR) + return -ENOTTY; + + if (_IOC_DIR(cmd) & _IOC_READ) + ret = !access_ok((void __user *)arg, _IOC_SIZE(cmd)); + else if (_IOC_DIR(cmd) & _IOC_WRITE) + ret = !access_ok((void __user *)arg, _IOC_SIZE(cmd)); + + if (ret) + return -EFAULT; + + /* Get a reference to the SPI device */ + penctrl = filp->private_data; + if (!penctrl) + return -ESHUTDOWN; + + spi_dev = spi_dev_get(penctrl->spi_dev); + if (!spi_dev) + return -ESHUTDOWN; + + /* Verify and prepare spi message */ + size = _IOC_SIZE(cmd); + if ((size % sizeof(struct penctrl_spi_xfer)) != 0) { + ret = -EINVAL; + goto done; + } + num_msgs = size / sizeof(struct penctrl_spi_xfer); + if (num_msgs == 0) { + ret = -EINVAL; + goto done; + } + msg = memdup_user((struct penctrl_spi_xfer __user *)arg, size); + if (!msg) { + ret = PTR_ERR(msg); + goto done; + } + if (msg->len > PENCTRL_MAX_MSG_LEN) { + ret = -EINVAL; + goto done; + } + + t[0].tx_buf = tx_buf; + t[0].len = msg->len; + if (copy_from_user((void *)(uintptr_t)tx_buf, + (void __user *)msg->tx_buf, msg->len)) { + ret = -EFAULT; + goto done; + } + if (num_msgs > 1) { + msg++; + if (msg->len > PENCTRL_MAX_MSG_LEN) { + ret = -EINVAL; + goto done; + } + t[1].rx_buf = rx_buf; + t[1].len = msg->len; + } + spi_message_init_with_transfers(&m, t, num_msgs); + + /* Perform the transfer */ + mutex_lock(&spi_lock); + ret = spi_sync(spi_dev, &m); + mutex_unlock(&spi_lock); + + if (ret || (num_msgs == 1)) + goto done; + + if (copy_to_user((void __user *)msg->rx_buf, + (void *)(uintptr_t)rx_buf, msg->len)) + ret = -EFAULT; + +done: + spi_dev_put(spi_dev); + return ret; +} + +static int penctrl_open(struct inode *inode, struct file *filp) +{ + struct spi_device *spi_dev; + u8 current_cs; + + if (!penctrl) + return -ENODEV; + + filp->private_data = penctrl; + current_cs = iminor(inode); + spi_dev = penctrl->spi_dev; + spi_dev->chip_select = current_cs; + spi_dev->cs_gpiod = spi_dev->controller->cs_gpiods[current_cs]; + spi_setup(spi_dev); + stream_open(inode, filp); + + return 0; +} + +static int penctrl_release(struct inode *inode, struct file *filp) +{ + filp->private_data = NULL; + return 0; +} + +static const struct file_operations penctrl_fops = { + .owner = THIS_MODULE, + .unlocked_ioctl = penctrl_ioctl, + .open = penctrl_open, + .release = penctrl_release, + .llseek = no_llseek, +}; + +static int penctrl_regs_read(struct penctrl_device *penctrl, u32 reg, u32 *val) +{ + struct spi_device *spi_dev = penctrl->spi_dev; + struct spi_transfer t[2] = { 0 }; + struct spi_message m; + u8 txbuf[3]; + u8 rxbuf[1]; + int ret; + + txbuf[0] = PENCTRL_SPI_CMD_REGRD; + txbuf[1] = reg; + txbuf[2] = 0x0; + t[0].tx_buf = txbuf; + t[0].len = 3; + + rxbuf[0] = 0x0; + t[1].rx_buf = rxbuf; + t[1].len = 1; + + spi_message_init_with_transfers(&m, t, ARRAY_SIZE(t)); + ret = spi_sync(spi_dev, &m); + if (ret == 0) + *val = rxbuf[0]; + + return ret; +} + +static int penctrl_regs_write(struct penctrl_device *penctrl, u32 reg, u32 val) +{ + struct spi_device *spi_dev = penctrl->spi_dev; + struct spi_transfer t[1] = { 0 }; + struct spi_message m; + u8 txbuf[4]; + int ret; + + txbuf[0] = PENCTRL_SPI_CMD_REGWR; + txbuf[1] = reg; + txbuf[2] = val; + txbuf[3] = 0; + + t[0].tx_buf = txbuf; + t[0].len = 4; + spi_message_init_with_transfers(&m, t, ARRAY_SIZE(t)); + ret = spi_sync(spi_dev, &m); + return ret; +} + +static int penctrl_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct penctrl_device *penctrl = + container_of(rcdev, struct penctrl_device, rcdev); + struct spi_device *spi_dev = penctrl->spi_dev; + unsigned int val; + int ret; + + mutex_lock(&spi_lock); + spi_dev->chip_select = 0; + spi_dev->cs_gpiod = spi_dev->controller->cs_gpiods[0]; + spi_setup(spi_dev); + ret = penctrl_regs_read(penctrl, PENCTRL_REG_CTRL0, &val); + if (ret) { + dev_err(&spi_dev->dev, "error reading ctrl0 reg\n"); + goto done; + } + + val |= BIT(6); + ret = penctrl_regs_write(penctrl, PENCTRL_REG_CTRL0, val); + if (ret) + dev_err(&spi_dev->dev, "error writing ctrl0 reg\n"); + +done: + mutex_unlock(&spi_lock); + return ret; +} + +static int penctrl_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct penctrl_device *penctrl = + container_of(rcdev, struct penctrl_device, rcdev); + struct spi_device *spi_dev = penctrl->spi_dev; + unsigned int val; + int ret; + + mutex_lock(&spi_lock); + spi_dev->chip_select = 0; + spi_dev->cs_gpiod = spi_dev->controller->cs_gpiods[0]; + spi_setup(spi_dev); + ret = penctrl_regs_read(penctrl, PENCTRL_REG_CTRL0, &val); + if (ret) { + dev_err(&spi_dev->dev, "error reading ctrl0 reg\n"); + goto done; + } + + val &= ~BIT(6); + ret = penctrl_regs_write(penctrl, PENCTRL_REG_CTRL0, val); + if (ret) + dev_err(&spi_dev->dev, "error writing ctrl0 reg\n"); + +done: + mutex_unlock(&spi_lock); + return ret; +} + +static const struct reset_control_ops penctrl_reset_ops = { + .assert = penctrl_reset_assert, + .deassert = penctrl_reset_deassert, +}; + +static int penctrl_spi_probe(struct spi_device *spi_dev) +{ + struct device_node *np; + struct device *dev; + struct cdev *cdev; + u32 num_cs; + int ret; + u32 cs; + + np = spi_dev->dev.parent->of_node; + ret = of_property_read_u32(np, "num-cs", &num_cs); + if (ret) + return dev_err_probe(&spi_dev->dev, ret, + "number of chip-selects not defined"); + + ret = alloc_chrdev_region(&penctrl_devt, 0, num_cs, "penctrl"); + if (ret) + return dev_err_probe(&spi_dev->dev, ret, + "failed to alloc chrdev region\n"); + + penctrl_class = class_create(THIS_MODULE, "penctrl"); + if (IS_ERR(penctrl_class)) { + unregister_chrdev(MAJOR(penctrl_devt), "penctrl"); + return dev_err_probe(&spi_dev->dev, PTR_ERR(penctrl_class), + "failed to create class\n"); + } + + cdev = cdev_alloc(); + if (!cdev) { + dev_err(&spi_dev->dev, "allocation of cdev failed"); + ret = -ENOMEM; + goto cdev_failed; + } + cdev->owner = THIS_MODULE; + cdev_init(cdev, &penctrl_fops); + + ret = cdev_add(cdev, penctrl_devt, num_cs); + if (ret) { + dev_err(&spi_dev->dev, "register of cdev failed"); + goto cdev_delete; + } + + /* Allocate driver data */ + penctrl = kzalloc(sizeof(*penctrl), GFP_KERNEL); + if (!penctrl) { + ret = -ENOMEM; + dev_err(&spi_dev->dev, "allocate driver data failed"); + goto cdev_delete; + } + + penctrl->spi_dev = spi_dev; + mutex_init(&spi_lock); + + /* Create a device for each chip select */ + for (cs = 0; cs < num_cs; cs++) { + dev = device_create(penctrl_class, + &spi_dev->dev, + MKDEV(MAJOR(penctrl_devt), cs), + penctrl, + "penctrl0.%d", + cs); + if (IS_ERR(dev)) { + ret = IS_ERR(dev); + dev_err(&spi_dev->dev, "error creating device\n"); + goto cdev_delete; + } + dev_dbg(&spi_dev->dev, "created device major %u, minor %d\n", + MAJOR(penctrl_devt), cs); + } + + spi_set_drvdata(spi_dev, penctrl); + + /* Register emmc hardware reset */ + penctrl->rcdev.nr_resets = 1; + penctrl->rcdev.owner = THIS_MODULE; + penctrl->rcdev.dev = &spi_dev->dev; + penctrl->rcdev.ops = &penctrl_reset_ops; + penctrl->rcdev.of_node = spi_dev->dev.of_node; + ret = reset_controller_register(&penctrl->rcdev); + if (ret) + return dev_err_probe(&spi_dev->dev, ret, + "failed to register reset controller\n"); + return ret; + +cdev_delete: + cdev_del(cdev); +cdev_failed: + device_destroy(penctrl_class, penctrl_devt); + return ret; +} + +static const struct of_device_id penctrl_dt_match[] = { + { .compatible = "amd,pensando-elba-ctrl" }, + { /* sentinel */ } +}; + +static struct spi_driver penctrl_spi_driver = { + .probe = penctrl_spi_probe, + .driver = { + .name = "pensando-ctrl", + .of_match_table = penctrl_dt_match, + }, +}; +module_spi_driver(penctrl_spi_driver); + +MODULE_AUTHOR("Brad Larson "); +MODULE_DESCRIPTION("AMD Pensando SoC Controller via SPI"); +MODULE_LICENSE("GPL"); diff --git a/include/uapi/linux/amd-pensando-ctrl.h b/include/uapi/linux/amd-pensando-ctrl.h new file mode 100644 index 000000000000..0a6caf3b764c --- /dev/null +++ b/include/uapi/linux/amd-pensando-ctrl.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ +/* + * Userspace interface for /dev/penctrl + * + * This file can be used by applications that need to communicate + * with the AMD Pensando SoC controller device via the ioctl interface. + */ +#ifndef _UAPI_LINUX_AMD_PENSANDO_CTRL_H +#define _UAPI_LINUX_AMD_PENSANDO_CTRL_H + +#include +#include + +#define PENCTRL_SPI_CMD_REGRD 0x0b +#define PENCTRL_SPI_CMD_REGWR 0x02 +#define PENCTRL_IOC_MAGIC 'k' +#define PENCTRL_IOC_MAXNR 0 +#define PENCTRL_MAX_MSG_LEN 16 +#define PENCTRL_MAX_REG 0xff +#define PENCTRL_REG_CTRL0 0x10 + +struct penctrl_spi_xfer { + __u64 tx_buf; + __u64 rx_buf; + __u32 len; + __u32 speed_hz; + __u64 compat; +}; + +#endif /* _UAPI_LINUX_AMD_PENSANDO_CTRL_H */