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[2620:137:e000::1:20]) by mx.google.com with ESMTP id d17-20020a170902ced100b001a18ec2d863si7745333plg.112.2023.03.21.13.14.00; Tue, 21 Mar 2023 13:14:15 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=fail header.i=@gmail.com header.s=20210112 header.b=PAd7Jgh4; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230018AbjCUUBL (ORCPT + 99 others); Tue, 21 Mar 2023 16:01:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36198 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230010AbjCUUBI (ORCPT ); Tue, 21 Mar 2023 16:01:08 -0400 Received: from mail-pj1-x1030.google.com (mail-pj1-x1030.google.com [IPv6:2607:f8b0:4864:20::1030]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CDDDE52F6C; Tue, 21 Mar 2023 13:00:59 -0700 (PDT) Received: by mail-pj1-x1030.google.com with SMTP id d13so16624306pjh.0; Tue, 21 Mar 2023 13:00:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1679428859; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=aLzZHqL9WDRVGnePjQNNc3Xx0tLOUWtULszDoChdvHo=; b=PAd7Jgh4UiuSw3F79lpFl8RJpUKfwS9lBfkjSM9xaIRgfsp7p2oKgM5GIJRRWt4RRY A0TZ1q6sZEG85BGy84x4AqyZ+bj+WN50lQPs/xJv6UuR4OqnffccriGzPqdfvGqYWoXL wIYRLKJAF8GxWKZxnvdVrdUc85JpjPGQIHB+Jikg90ZeLwa+Mf6Ro+2HUZUmvHZjElBt lgG6nx/2yn7+8QNPBQKzgx4NMuXBR8a5dK/+iVPbxD60XYUCmo2F2rRShBsOIs239KHO mKmzDAJHOhiaHbqfJHNOw4OG4OVRxy84P6GAl2cZ0z6jjQ+SbACZ6bYKjDTF1YvOKoeO YxvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679428859; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=aLzZHqL9WDRVGnePjQNNc3Xx0tLOUWtULszDoChdvHo=; b=S6MOqj+zggZu2EWVouUTD8tw8/byhlSzl7dKPj3n/9neg2x46WkPTXZa9tNuJFrVOv +UxWjjuTEAgEnEt6b+1sXow0g3bSjETkJRKUbJ/P95W0juJt2aLL0zmq5FcsY2Zg/8gU bEwbtC5cRj4cSVhBYrOMoeNTEhwmSv7kKaK8d3yJQ/RYqJJwC1dtJPGM5/sCZSCmNkB/ 1ZEUDa13TW7jBthZiUxV9EW3oulqC5GDT0OYhuHaRjrJ6Qqu+LGcJmevLMMQny8JHyyb CDRHJlAj5QIyuhVfMgtsAbxEya026CVQ2SyW+GOg+YyVPNHNV0rwbHmkwkhWR4T/17IV R83Q== X-Gm-Message-State: AO0yUKXyO0lLfTpH8Y2hXaxZ0J+Cw0Hji1TeANUOuvnxdUhQAbXrOTfE M8b8TdWxwZLpzsKdMlgg+IE= X-Received: by 2002:a17:90b:1c07:b0:237:f018:6433 with SMTP id oc7-20020a17090b1c0700b00237f0186433mr842111pjb.27.1679428858847; Tue, 21 Mar 2023 13:00:58 -0700 (PDT) Received: from d.home.yangfl.dn42 ([104.28.245.199]) by smtp.gmail.com with ESMTPSA id mt19-20020a17090b231300b0023b5528b8d4sm930557pjb.19.2023.03.21.13.00.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Mar 2023 13:00:58 -0700 (PDT) From: David Yang Cc: David Yang , Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 1/6] clk: hisilicon: Rename Hi3798CV200 to Hi3798 Date: Wed, 22 Mar 2023 04:00:22 +0800 Message-Id: <20230321200031.1812026-2-mmyangfl@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230321200031.1812026-1-mmyangfl@gmail.com> References: <20230321200031.1812026-1-mmyangfl@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761009630058358931?= X-GMAIL-MSGID: =?utf-8?q?1761009630058358931?= Rename Hisilicon Hi3798CV200 to Hi3798, to be reused with other Hi3798 series SoCs. Signed-off-by: David Yang --- drivers/clk/hisilicon/Kconfig | 6 +- drivers/clk/hisilicon/Makefile | 2 +- .../{crg-hi3798cv200.c => crg-hi3798.c} | 181 +++++++++--------- 3 files changed, 95 insertions(+), 94 deletions(-) rename drivers/clk/hisilicon/{crg-hi3798cv200.c => crg-hi3798.c} (68%) diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig index c1ec75aa4..fa2d9920f 100644 --- a/drivers/clk/hisilicon/Kconfig +++ b/drivers/clk/hisilicon/Kconfig @@ -37,13 +37,13 @@ config COMMON_CLK_HI3670 help Build the clock driver for hi3670. -config COMMON_CLK_HI3798CV200 - tristate "Hi3798CV200 Clock Driver" +config COMMON_CLK_HI3798 + tristate "Hi3798 Clock Driver" depends on ARCH_HISI || COMPILE_TEST select RESET_HISI default ARCH_HISI help - Build the clock driver for hi3798cv200. + Build the clock driver for hi3798. config COMMON_CLK_HI6220 bool "Hi6220 Clock Driver" diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile index 2978e56cb..cfef47a19 100644 --- a/drivers/clk/hisilicon/Makefile +++ b/drivers/clk/hisilicon/Makefile @@ -13,7 +13,7 @@ obj-$(CONFIG_COMMON_CLK_HI3519) += clk-hi3519.o obj-$(CONFIG_COMMON_CLK_HI3559A) += clk-hi3559a.o obj-$(CONFIG_COMMON_CLK_HI3660) += clk-hi3660.o obj-$(CONFIG_COMMON_CLK_HI3670) += clk-hi3670.o -obj-$(CONFIG_COMMON_CLK_HI3798CV200) += crg-hi3798cv200.o +obj-$(CONFIG_COMMON_CLK_HI3798) += crg-hi3798.o obj-$(CONFIG_COMMON_CLK_HI6220) += clk-hi6220.o obj-$(CONFIG_RESET_HISI) += reset.o obj-$(CONFIG_STUB_CLK_HI6220) += clk-hi6220-stub.o diff --git a/drivers/clk/hisilicon/crg-hi3798cv200.c b/drivers/clk/hisilicon/crg-hi3798.c similarity index 68% rename from drivers/clk/hisilicon/crg-hi3798cv200.c rename to drivers/clk/hisilicon/crg-hi3798.c index 08a19ba77..7e9507de2 100644 --- a/drivers/clk/hisilicon/crg-hi3798cv200.c +++ b/drivers/clk/hisilicon/crg-hi3798.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-or-later /* - * Hi3798CV200 Clock and Reset Generator Driver + * Hi3798 Clock and Reset Generator Driver * * Copyright (c) 2016 HiSilicon Technologies Co., Ltd. */ @@ -14,75 +14,76 @@ #include "crg.h" #include "reset.h" -/* hi3798CV200 core CRG */ -#define HI3798CV200_INNER_CLK_OFFSET 64 -#define HI3798CV200_FIXED_24M 65 -#define HI3798CV200_FIXED_25M 66 -#define HI3798CV200_FIXED_50M 67 -#define HI3798CV200_FIXED_75M 68 -#define HI3798CV200_FIXED_100M 69 -#define HI3798CV200_FIXED_150M 70 -#define HI3798CV200_FIXED_200M 71 -#define HI3798CV200_FIXED_250M 72 -#define HI3798CV200_FIXED_300M 73 -#define HI3798CV200_FIXED_400M 74 -#define HI3798CV200_MMC_MUX 75 -#define HI3798CV200_ETH_PUB_CLK 76 -#define HI3798CV200_ETH_BUS_CLK 77 -#define HI3798CV200_ETH_BUS0_CLK 78 -#define HI3798CV200_ETH_BUS1_CLK 79 -#define HI3798CV200_COMBPHY1_MUX 80 -#define HI3798CV200_FIXED_12M 81 -#define HI3798CV200_FIXED_48M 82 -#define HI3798CV200_FIXED_60M 83 -#define HI3798CV200_FIXED_166P5M 84 -#define HI3798CV200_SDIO0_MUX 85 -#define HI3798CV200_COMBPHY0_MUX 86 - -#define HI3798CV200_CRG_NR_CLKS 128 - -static const struct hisi_fixed_rate_clock hi3798cv200_fixed_rate_clks[] = { +/* hi3798 core CRG */ +#define HI3798_INNER_CLK_OFFSET 64 +#define HI3798_FIXED_24M 65 +#define HI3798_FIXED_25M 66 +#define HI3798_FIXED_50M 67 +#define HI3798_FIXED_75M 68 +#define HI3798_FIXED_100M 69 +#define HI3798_FIXED_150M 70 +#define HI3798_FIXED_200M 71 +#define HI3798_FIXED_250M 72 +#define HI3798_FIXED_300M 73 +#define HI3798_FIXED_400M 74 +#define HI3798_MMC_MUX 75 +#define HI3798_ETH_PUB_CLK 76 +#define HI3798_ETH_BUS_CLK 77 +#define HI3798_ETH_BUS0_CLK 78 +#define HI3798_ETH_BUS1_CLK 79 +#define HI3798_COMBPHY1_MUX 80 +#define HI3798_FIXED_12M 81 +#define HI3798_FIXED_48M 82 +#define HI3798_FIXED_60M 83 +#define HI3798_FIXED_166P5M 84 +#define HI3798_SDIO0_MUX 85 +#define HI3798_COMBPHY0_MUX 86 + +#define HI3798_CRG_NR_CLKS 128 + +static const struct hisi_fixed_rate_clock hi3798_fixed_rate_clks[] = { { HISTB_OSC_CLK, "clk_osc", NULL, 0, 24000000, }, { HISTB_APB_CLK, "clk_apb", NULL, 0, 100000000, }, { HISTB_AHB_CLK, "clk_ahb", NULL, 0, 200000000, }, - { HI3798CV200_FIXED_12M, "12m", NULL, 0, 12000000, }, - { HI3798CV200_FIXED_24M, "24m", NULL, 0, 24000000, }, - { HI3798CV200_FIXED_25M, "25m", NULL, 0, 25000000, }, - { HI3798CV200_FIXED_48M, "48m", NULL, 0, 48000000, }, - { HI3798CV200_FIXED_50M, "50m", NULL, 0, 50000000, }, - { HI3798CV200_FIXED_60M, "60m", NULL, 0, 60000000, }, - { HI3798CV200_FIXED_75M, "75m", NULL, 0, 75000000, }, - { HI3798CV200_FIXED_100M, "100m", NULL, 0, 100000000, }, - { HI3798CV200_FIXED_150M, "150m", NULL, 0, 150000000, }, - { HI3798CV200_FIXED_166P5M, "166p5m", NULL, 0, 165000000, }, - { HI3798CV200_FIXED_200M, "200m", NULL, 0, 200000000, }, - { HI3798CV200_FIXED_250M, "250m", NULL, 0, 250000000, }, + { HI3798_FIXED_12M, "12m", NULL, 0, 12000000, }, + { HI3798_FIXED_24M, "24m", NULL, 0, 24000000, }, + { HI3798_FIXED_25M, "25m", NULL, 0, 25000000, }, + { HI3798_FIXED_48M, "48m", NULL, 0, 48000000, }, + { HI3798_FIXED_50M, "50m", NULL, 0, 50000000, }, + { HI3798_FIXED_60M, "60m", NULL, 0, 60000000, }, + { HI3798_FIXED_75M, "75m", NULL, 0, 75000000, }, + { HI3798_FIXED_100M, "100m", NULL, 0, 100000000, }, + { HI3798_FIXED_150M, "150m", NULL, 0, 150000000, }, + { HI3798_FIXED_166P5M, "166p5m", NULL, 0, 165000000, }, + { HI3798_FIXED_200M, "200m", NULL, 0, 200000000, }, + { HI3798_FIXED_250M, "250m", NULL, 0, 250000000, }, }; -static const char *const mmc_mux_p[] = { +static const char *const hi3798cv200_mmc_mux_p[] = { "100m", "50m", "25m", "200m", "150m" }; -static u32 mmc_mux_table[] = {0, 1, 2, 3, 6}; +static u32 hi3798cv200_mmc_mux_table[] = {0, 1, 2, 3, 6}; -static const char *const comphy_mux_p[] = { +static const char *const hi3798cv200_comphy_mux_p[] = { "100m", "25m"}; -static u32 comphy_mux_table[] = {2, 3}; +static u32 hi3798cv200_comphy_mux_table[] = {2, 3}; -static const char *const sdio_mux_p[] = { +static const char *const hi3798cv200_sdio_mux_p[] = { "100m", "50m", "150m", "166p5m" }; -static u32 sdio_mux_table[] = {0, 1, 2, 3}; +static u32 hi3798cv200_sdio_mux_table[] = {0, 1, 2, 3}; static struct hisi_mux_clock hi3798cv200_mux_clks[] = { - { HI3798CV200_MMC_MUX, "mmc_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p), - CLK_SET_RATE_PARENT, 0xa0, 8, 3, 0, mmc_mux_table, }, - { HI3798CV200_COMBPHY0_MUX, "combphy0_mux", - comphy_mux_p, ARRAY_SIZE(comphy_mux_p), - CLK_SET_RATE_PARENT, 0x188, 2, 2, 0, comphy_mux_table, }, - { HI3798CV200_COMBPHY1_MUX, "combphy1_mux", - comphy_mux_p, ARRAY_SIZE(comphy_mux_p), - CLK_SET_RATE_PARENT, 0x188, 10, 2, 0, comphy_mux_table, }, - { HI3798CV200_SDIO0_MUX, "sdio0_mux", sdio_mux_p, - ARRAY_SIZE(sdio_mux_p), CLK_SET_RATE_PARENT, - 0x9c, 8, 2, 0, sdio_mux_table, }, + { HI3798_MMC_MUX, "mmc_mux", hi3798cv200_mmc_mux_p, + ARRAY_SIZE(hi3798cv200_mmc_mux_p), CLK_SET_RATE_PARENT, + 0xa0, 8, 3, 0, hi3798cv200_mmc_mux_table, }, + { HI3798_COMBPHY0_MUX, "combphy0_mux", hi3798cv200_comphy_mux_p, + ARRAY_SIZE(hi3798cv200_comphy_mux_p), CLK_SET_RATE_PARENT, + 0x188, 2, 2, 0, hi3798cv200_comphy_mux_table, }, + { HI3798_COMBPHY1_MUX, "combphy1_mux", hi3798cv200_comphy_mux_p, + ARRAY_SIZE(hi3798cv200_comphy_mux_p), CLK_SET_RATE_PARENT, + 0x188, 10, 2, 0, hi3798cv200_comphy_mux_table, }, + { HI3798_SDIO0_MUX, "sdio0_mux", hi3798cv200_sdio_mux_p, + ARRAY_SIZE(hi3798cv200_sdio_mux_p), CLK_SET_RATE_PARENT, + 0x9c, 8, 2, 0, hi3798cv200_sdio_mux_table, }, }; static u32 mmc_phase_regvals[] = {0, 1, 2, 3, 4, 5, 6, 7}; @@ -117,7 +118,7 @@ static const struct hisi_gate_clock hi3798cv200_gate_clks[] = { CLK_SET_RATE_PARENT, 0x70, 0, 0, }, /* SDIO */ { HISTB_SDIO0_BIU_CLK, "clk_sdio0_biu", "200m", - CLK_SET_RATE_PARENT, 0x9c, 0, 0, }, + CLK_SET_RATE_PARENT, 0x9c, 0, 0, }, { HISTB_SDIO0_CIU_CLK, "clk_sdio0_ciu", "sdio0_mux", CLK_SET_RATE_PARENT, 0x9c, 1, 0, }, /* EMMC */ @@ -135,13 +136,13 @@ static const struct hisi_gate_clock hi3798cv200_gate_clks[] = { { HISTB_PCIE_AUX_CLK, "clk_pcie_aux", "24m", CLK_SET_RATE_PARENT, 0x18c, 3, 0, }, /* Ethernet */ - { HI3798CV200_ETH_PUB_CLK, "clk_pub", NULL, + { HI3798_ETH_PUB_CLK, "clk_pub", NULL, CLK_SET_RATE_PARENT, 0xcc, 5, 0, }, - { HI3798CV200_ETH_BUS_CLK, "clk_bus", "clk_pub", + { HI3798_ETH_BUS_CLK, "clk_bus", "clk_pub", CLK_SET_RATE_PARENT, 0xcc, 0, 0, }, - { HI3798CV200_ETH_BUS0_CLK, "clk_bus_m0", "clk_bus", + { HI3798_ETH_BUS0_CLK, "clk_bus_m0", "clk_bus", CLK_SET_RATE_PARENT, 0xcc, 1, 0, }, - { HI3798CV200_ETH_BUS1_CLK, "clk_bus_m1", "clk_bus", + { HI3798_ETH_BUS1_CLK, "clk_bus_m1", "clk_bus", CLK_SET_RATE_PARENT, 0xcc, 2, 0, }, { HISTB_ETH0_MAC_CLK, "clk_mac0", "clk_bus_m0", CLK_SET_RATE_PARENT, 0xcc, 3, 0, }, @@ -199,7 +200,7 @@ static struct hisi_clock_data *hi3798cv200_clk_register( struct hisi_clock_data *clk_data; int ret; - clk_data = hisi_clk_alloc(pdev, HI3798CV200_CRG_NR_CLKS); + clk_data = hisi_clk_alloc(pdev, HI3798_CRG_NR_CLKS); if (!clk_data) return ERR_PTR(-ENOMEM); @@ -211,8 +212,8 @@ static struct hisi_clock_data *hi3798cv200_clk_register( if (ret) return ERR_PTR(ret); - ret = hisi_clk_register_fixed_rate(hi3798cv200_fixed_rate_clks, - ARRAY_SIZE(hi3798cv200_fixed_rate_clks), + ret = hisi_clk_register_fixed_rate(hi3798_fixed_rate_clks, + ARRAY_SIZE(hi3798_fixed_rate_clks), clk_data); if (ret) return ERR_PTR(ret); @@ -245,8 +246,8 @@ static struct hisi_clock_data *hi3798cv200_clk_register( ARRAY_SIZE(hi3798cv200_mux_clks), clk_data); unregister_fixed_rate: - hisi_clk_unregister_fixed_rate(hi3798cv200_fixed_rate_clks, - ARRAY_SIZE(hi3798cv200_fixed_rate_clks), + hisi_clk_unregister_fixed_rate(hi3798_fixed_rate_clks, + ARRAY_SIZE(hi3798_fixed_rate_clks), clk_data); return ERR_PTR(ret); } @@ -263,8 +264,8 @@ static void hi3798cv200_clk_unregister(struct platform_device *pdev) hisi_clk_unregister_mux(hi3798cv200_mux_clks, ARRAY_SIZE(hi3798cv200_mux_clks), crg->clk_data); - hisi_clk_unregister_fixed_rate(hi3798cv200_fixed_rate_clks, - ARRAY_SIZE(hi3798cv200_fixed_rate_clks), + hisi_clk_unregister_fixed_rate(hi3798_fixed_rate_clks, + ARRAY_SIZE(hi3798_fixed_rate_clks), crg->clk_data); } @@ -273,9 +274,9 @@ static const struct hisi_crg_funcs hi3798cv200_crg_funcs = { .unregister_clks = hi3798cv200_clk_unregister, }; -/* hi3798CV200 sysctrl CRG */ +/* hi3798 sysctrl CRG */ -#define HI3798CV200_SYSCTRL_NR_CLKS 16 +#define HI3798_SYSCTRL_NR_CLKS 16 static const struct hisi_gate_clock hi3798cv200_sysctrl_gate_clks[] = { { HISTB_IR_CLK, "clk_ir", "24m", @@ -292,7 +293,7 @@ static struct hisi_clock_data *hi3798cv200_sysctrl_clk_register( struct hisi_clock_data *clk_data; int ret; - clk_data = hisi_clk_alloc(pdev, HI3798CV200_SYSCTRL_NR_CLKS); + clk_data = hisi_clk_alloc(pdev, HI3798_SYSCTRL_NR_CLKS); if (!clk_data) return ERR_PTR(-ENOMEM); @@ -332,16 +333,16 @@ static const struct hisi_crg_funcs hi3798cv200_sysctrl_funcs = { .unregister_clks = hi3798cv200_sysctrl_clk_unregister, }; -static const struct of_device_id hi3798cv200_crg_match_table[] = { +static const struct of_device_id hi3798_crg_match_table[] = { { .compatible = "hisilicon,hi3798cv200-crg", .data = &hi3798cv200_crg_funcs }, { .compatible = "hisilicon,hi3798cv200-sysctrl", .data = &hi3798cv200_sysctrl_funcs }, { } }; -MODULE_DEVICE_TABLE(of, hi3798cv200_crg_match_table); +MODULE_DEVICE_TABLE(of, hi3798_crg_match_table); -static int hi3798cv200_crg_probe(struct platform_device *pdev) +static int hi3798_crg_probe(struct platform_device *pdev) { struct hisi_crg_dev *crg; @@ -367,7 +368,7 @@ static int hi3798cv200_crg_probe(struct platform_device *pdev) return 0; } -static int hi3798cv200_crg_remove(struct platform_device *pdev) +static int hi3798_crg_remove(struct platform_device *pdev) { struct hisi_crg_dev *crg = platform_get_drvdata(pdev); @@ -376,26 +377,26 @@ static int hi3798cv200_crg_remove(struct platform_device *pdev) return 0; } -static struct platform_driver hi3798cv200_crg_driver = { - .probe = hi3798cv200_crg_probe, - .remove = hi3798cv200_crg_remove, - .driver = { - .name = "hi3798cv200-crg", - .of_match_table = hi3798cv200_crg_match_table, +static struct platform_driver hi3798_crg_driver = { + .probe = hi3798_crg_probe, + .remove = hi3798_crg_remove, + .driver = { + .name = "hi3798-crg", + .of_match_table = hi3798_crg_match_table, }, }; -static int __init hi3798cv200_crg_init(void) +static int __init hi3798_crg_init(void) { - return platform_driver_register(&hi3798cv200_crg_driver); + return platform_driver_register(&hi3798_crg_driver); } -core_initcall(hi3798cv200_crg_init); +core_initcall(hi3798_crg_init); -static void __exit hi3798cv200_crg_exit(void) +static void __exit hi3798_crg_exit(void) { - platform_driver_unregister(&hi3798cv200_crg_driver); + platform_driver_unregister(&hi3798_crg_driver); } -module_exit(hi3798cv200_crg_exit); +module_exit(hi3798_crg_exit); MODULE_LICENSE("GPL v2"); -MODULE_DESCRIPTION("HiSilicon Hi3798CV200 CRG Driver"); +MODULE_DESCRIPTION("HiSilicon Hi3798 CRG Driver"); From patchwork Tue Mar 21 20:00:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yangfl X-Patchwork-Id: 73038 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:604a:0:0:0:0:0 with SMTP id j10csp1986506wrt; Tue, 21 Mar 2023 13:11:49 -0700 (PDT) X-Google-Smtp-Source: AK7set+gQjqyAQVqtpBWOC63ZHc4M5f8TAegzQw1vjATsjulqpw8++lUIYBolUryN2hv6e9i8gzT X-Received: by 2002:a62:7997:0:b0:627:ef8d:117a with SMTP id u145-20020a627997000000b00627ef8d117amr983887pfc.15.1679429509691; Tue, 21 Mar 2023 13:11:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1679429509; cv=none; d=google.com; s=arc-20160816; b=oGQB4ko4xCwsnRPU8Pi0zl2EW5u6BsxG4J2F6VsuPQPPk/3kl1kpWsrXn22FvwJk6A 0gbEthIb41qY5DEEH/4yFLaEciJdtkah34TnC/vXN1EkLtCODsFeCtc1n/p3ImbSIMU8 Lv8sVERRo9/UAMO7nYME2bAt4q+2KsTAmr2T3e2LMfap8cSlpFIXXFLQ7itI2wBM+T9+ OLw54HuLlSEV3xSBDDynfW8IE9GdtZtT4X48OLfSd/pQ7IHCHrwE7kA4Y8LUYYBSvjoZ SzgHoXrhGSo23QAdubur/XQvA+RclVfisgczKAqH5ZDplh0AoOYsW3dsoEIN2uKdV00o CcTg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:to:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:from :dkim-signature; bh=FS9JTRcWDJXKghFeO1Ewd82eQaR9XI3VWrHV848ZxsA=; b=L+tFKkLDVM53fG+w6b5wZCcxXj+7nS8XvauI79ZUlF4NJrlgwEEgLn6UFtNYY/e2Cy 3wM3ivdqBzlR/lWOHLtLG6gT/ODMV/vQGp4LH5GAX39Q86XPkHERG8zAs+33R33m84i9 AlZvSD4gMI7vnw4VNQLzhHnHRZkGpEg5IsTtN6h+mB8jdDiJidCwlqYlkaAlQsetkKCh KE248hE9gg9y4qEKMtQjO2hanK1bKYaiGAPggDefdKYoNSujleksOGU2v3O2Xc63jRuu YQwsEPEY9ftaTTiQL9dNIIg7etja+RdHmR+sxKfhpHveEibtPhB7IQAiD6kEOMii9iEk CoyA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20210112 header.b=ZOUedwkm; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: David Yang --- drivers/clk/hisilicon/crg-hi3798.c | 243 ++++++++++++++++------------- 1 file changed, 137 insertions(+), 106 deletions(-) diff --git a/drivers/clk/hisilicon/crg-hi3798.c b/drivers/clk/hisilicon/crg-hi3798.c index 7e9507de2..778637131 100644 --- a/drivers/clk/hisilicon/crg-hi3798.c +++ b/drivers/clk/hisilicon/crg-hi3798.c @@ -59,6 +59,121 @@ static const struct hisi_fixed_rate_clock hi3798_fixed_rate_clks[] = { { HI3798_FIXED_250M, "250m", NULL, 0, 250000000, }, }; +struct hi3798_clks { + const struct hisi_gate_clock *gate_clks; + int gate_clks_nums; + const struct hisi_mux_clock *mux_clks; + int mux_clks_nums; + const struct hisi_phase_clock *phase_clks; + int phase_clks_nums; +}; + +static struct hisi_clock_data * +hi3798_clk_register(struct platform_device *pdev, + const struct hi3798_clks *clks) +{ + struct hisi_clock_data *clk_data; + int ret; + + clk_data = hisi_clk_alloc(pdev, HI3798_CRG_NR_CLKS); + if (!clk_data) + return ERR_PTR(-ENOMEM); + + /* hisi_phase_clock is resource managed */ + ret = hisi_clk_register_phase(&pdev->dev, clks->phase_clks, + clks->phase_clks_nums, clk_data); + if (ret) + return ERR_PTR(ret); + + ret = hisi_clk_register_fixed_rate(hi3798_fixed_rate_clks, + ARRAY_SIZE(hi3798_fixed_rate_clks), + clk_data); + if (ret) + return ERR_PTR(ret); + + ret = hisi_clk_register_mux(clks->mux_clks, clks->mux_clks_nums, clk_data); + if (ret) + goto unregister_fixed_rate; + + ret = hisi_clk_register_gate(clks->gate_clks, clks->gate_clks_nums, clk_data); + if (ret) + goto unregister_mux; + + ret = of_clk_add_provider(pdev->dev.of_node, + of_clk_src_onecell_get, &clk_data->clk_data); + if (ret) + goto unregister_gate; + + return clk_data; + +unregister_gate: + hisi_clk_unregister_gate(clks->gate_clks, clks->gate_clks_nums, clk_data); +unregister_mux: + hisi_clk_unregister_mux(clks->mux_clks, clks->mux_clks_nums, clk_data); +unregister_fixed_rate: + hisi_clk_unregister_fixed_rate(hi3798_fixed_rate_clks, + ARRAY_SIZE(hi3798_fixed_rate_clks), + clk_data); + return ERR_PTR(ret); +} + +static void hi3798_clk_unregister(struct platform_device *pdev, + const struct hi3798_clks *clks) +{ + struct hisi_crg_dev *crg = platform_get_drvdata(pdev); + + of_clk_del_provider(pdev->dev.of_node); + + hisi_clk_unregister_gate(clks->gate_clks, clks->gate_clks_nums, crg->clk_data); + hisi_clk_unregister_mux(clks->mux_clks, clks->mux_clks_nums, crg->clk_data); + hisi_clk_unregister_fixed_rate(hi3798_fixed_rate_clks, + ARRAY_SIZE(hi3798_fixed_rate_clks), + crg->clk_data); +} + +/* hi3798 sysctrl CRG */ + +#define HI3798_SYSCTRL_NR_CLKS 16 + +static struct hisi_clock_data * +hi3798_sysctrl_clk_register(struct platform_device *pdev, + const struct hi3798_clks *clks) +{ + struct hisi_clock_data *clk_data; + int ret; + + clk_data = hisi_clk_alloc(pdev, HI3798_SYSCTRL_NR_CLKS); + if (!clk_data) + return ERR_PTR(-ENOMEM); + + ret = hisi_clk_register_gate(clks->gate_clks, clks->gate_clks_nums, clk_data); + if (ret) + return ERR_PTR(ret); + + ret = of_clk_add_provider(pdev->dev.of_node, + of_clk_src_onecell_get, &clk_data->clk_data); + if (ret) + goto unregister_gate; + + return clk_data; + +unregister_gate: + hisi_clk_unregister_gate(clks->gate_clks, clks->gate_clks_nums, clk_data); + return ERR_PTR(ret); +} + +static void hi3798_sysctrl_clk_unregister(struct platform_device *pdev, + const struct hi3798_clks *clks) +{ + struct hisi_crg_dev *crg = platform_get_drvdata(pdev); + + of_clk_del_provider(pdev->dev.of_node); + + hisi_clk_unregister_gate(clks->gate_clks, clks->gate_clks_nums, crg->clk_data); +} + +/* hi3798CV200 */ + static const char *const hi3798cv200_mmc_mux_p[] = { "100m", "50m", "25m", "200m", "150m" }; static u32 hi3798cv200_mmc_mux_table[] = {0, 1, 2, 3, 6}; @@ -194,79 +309,24 @@ static const struct hisi_gate_clock hi3798cv200_gate_clks[] = { CLK_SET_RATE_PARENT, 0xb0, 18, 0 }, }; -static struct hisi_clock_data *hi3798cv200_clk_register( - struct platform_device *pdev) -{ - struct hisi_clock_data *clk_data; - int ret; - - clk_data = hisi_clk_alloc(pdev, HI3798_CRG_NR_CLKS); - if (!clk_data) - return ERR_PTR(-ENOMEM); - - /* hisi_phase_clock is resource managed */ - ret = hisi_clk_register_phase(&pdev->dev, - hi3798cv200_phase_clks, - ARRAY_SIZE(hi3798cv200_phase_clks), - clk_data); - if (ret) - return ERR_PTR(ret); - - ret = hisi_clk_register_fixed_rate(hi3798_fixed_rate_clks, - ARRAY_SIZE(hi3798_fixed_rate_clks), - clk_data); - if (ret) - return ERR_PTR(ret); - - ret = hisi_clk_register_mux(hi3798cv200_mux_clks, - ARRAY_SIZE(hi3798cv200_mux_clks), - clk_data); - if (ret) - goto unregister_fixed_rate; - - ret = hisi_clk_register_gate(hi3798cv200_gate_clks, - ARRAY_SIZE(hi3798cv200_gate_clks), - clk_data); - if (ret) - goto unregister_mux; - - ret = of_clk_add_provider(pdev->dev.of_node, - of_clk_src_onecell_get, &clk_data->clk_data); - if (ret) - goto unregister_gate; - - return clk_data; +static const struct hi3798_clks hi3798cv200_crg_clks = { + .gate_clks = hi3798cv200_gate_clks, + .gate_clks_nums = ARRAY_SIZE(hi3798cv200_gate_clks), + .mux_clks = hi3798cv200_mux_clks, + .mux_clks_nums = ARRAY_SIZE(hi3798cv200_mux_clks), + .phase_clks = hi3798cv200_phase_clks, + .phase_clks_nums = ARRAY_SIZE(hi3798cv200_phase_clks), +}; -unregister_gate: - hisi_clk_unregister_gate(hi3798cv200_gate_clks, - ARRAY_SIZE(hi3798cv200_gate_clks), - clk_data); -unregister_mux: - hisi_clk_unregister_mux(hi3798cv200_mux_clks, - ARRAY_SIZE(hi3798cv200_mux_clks), - clk_data); -unregister_fixed_rate: - hisi_clk_unregister_fixed_rate(hi3798_fixed_rate_clks, - ARRAY_SIZE(hi3798_fixed_rate_clks), - clk_data); - return ERR_PTR(ret); +static struct hisi_clock_data * +hi3798cv200_clk_register(struct platform_device *pdev) +{ + return hi3798_clk_register(pdev, &hi3798cv200_crg_clks); } static void hi3798cv200_clk_unregister(struct platform_device *pdev) { - struct hisi_crg_dev *crg = platform_get_drvdata(pdev); - - of_clk_del_provider(pdev->dev.of_node); - - hisi_clk_unregister_gate(hi3798cv200_gate_clks, - ARRAY_SIZE(hi3798cv200_gate_clks), - crg->clk_data); - hisi_clk_unregister_mux(hi3798cv200_mux_clks, - ARRAY_SIZE(hi3798cv200_mux_clks), - crg->clk_data); - hisi_clk_unregister_fixed_rate(hi3798_fixed_rate_clks, - ARRAY_SIZE(hi3798_fixed_rate_clks), - crg->clk_data); + hi3798_clk_unregister(pdev, &hi3798cv200_crg_clks); } static const struct hisi_crg_funcs hi3798cv200_crg_funcs = { @@ -274,10 +334,6 @@ static const struct hisi_crg_funcs hi3798cv200_crg_funcs = { .unregister_clks = hi3798cv200_clk_unregister, }; -/* hi3798 sysctrl CRG */ - -#define HI3798_SYSCTRL_NR_CLKS 16 - static const struct hisi_gate_clock hi3798cv200_sysctrl_gate_clks[] = { { HISTB_IR_CLK, "clk_ir", "24m", CLK_SET_RATE_PARENT, 0x48, 4, 0, }, @@ -287,45 +343,20 @@ static const struct hisi_gate_clock hi3798cv200_sysctrl_gate_clks[] = { CLK_SET_RATE_PARENT, 0x48, 10, 0, }, }; -static struct hisi_clock_data *hi3798cv200_sysctrl_clk_register( - struct platform_device *pdev) -{ - struct hisi_clock_data *clk_data; - int ret; - - clk_data = hisi_clk_alloc(pdev, HI3798_SYSCTRL_NR_CLKS); - if (!clk_data) - return ERR_PTR(-ENOMEM); - - ret = hisi_clk_register_gate(hi3798cv200_sysctrl_gate_clks, - ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks), - clk_data); - if (ret) - return ERR_PTR(ret); - - ret = of_clk_add_provider(pdev->dev.of_node, - of_clk_src_onecell_get, &clk_data->clk_data); - if (ret) - goto unregister_gate; - - return clk_data; +static const struct hi3798_clks hi3798cv200_sysctrl_clks = { + .gate_clks = hi3798cv200_sysctrl_gate_clks, + .gate_clks_nums = ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks), +}; -unregister_gate: - hisi_clk_unregister_gate(hi3798cv200_sysctrl_gate_clks, - ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks), - clk_data); - return ERR_PTR(ret); +static struct hisi_clock_data * +hi3798cv200_sysctrl_clk_register(struct platform_device *pdev) +{ + return hi3798_sysctrl_clk_register(pdev, &hi3798cv200_sysctrl_clks); } static void hi3798cv200_sysctrl_clk_unregister(struct platform_device *pdev) { - struct hisi_crg_dev *crg = platform_get_drvdata(pdev); - - of_clk_del_provider(pdev->dev.of_node); - - hisi_clk_unregister_gate(hi3798cv200_sysctrl_gate_clks, - ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks), - crg->clk_data); + hi3798_sysctrl_clk_unregister(pdev, &hi3798cv200_sysctrl_clks); } static const struct hisi_crg_funcs hi3798cv200_sysctrl_funcs = { From patchwork Tue Mar 21 20:00:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yangfl X-Patchwork-Id: 73041 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:604a:0:0:0:0:0 with SMTP id j10csp1987206wrt; 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Signed-off-by: David Yang --- drivers/clk/hisilicon/clk-hi3519.c | 45 +--- drivers/clk/hisilicon/clk-hi3559a.c | 111 ++++------ drivers/clk/hisilicon/clk-hi3620.c | 12 +- drivers/clk/hisilicon/clk-hi3660.c | 46 ++-- drivers/clk/hisilicon/clk-hi3670.c | 52 +++-- drivers/clk/hisilicon/clk-hi6220.c | 34 +-- drivers/clk/hisilicon/clk-hip04.c | 4 +- drivers/clk/hisilicon/clk-hisi-phase.c | 15 +- drivers/clk/hisilicon/clk-hix5hd2.c | 33 +-- drivers/clk/hisilicon/clk.c | 245 ++++++++++------------ drivers/clk/hisilicon/clk.h | 89 ++++---- drivers/clk/hisilicon/clkdivider-hi6220.c | 23 +- drivers/clk/hisilicon/clkgate-separated.c | 16 +- drivers/clk/hisilicon/crg-hi3516cv300.c | 60 ++---- drivers/clk/hisilicon/crg-hi3798.c | 56 ++--- 15 files changed, 364 insertions(+), 477 deletions(-) diff --git a/drivers/clk/hisilicon/clk-hi3519.c b/drivers/clk/hisilicon/clk-hi3519.c index ad0c7f350..5900140c7 100644 --- a/drivers/clk/hisilicon/clk-hi3519.c +++ b/drivers/clk/hisilicon/clk-hi3519.c @@ -75,6 +75,7 @@ static const struct hisi_gate_clock hi3519_gate_clks[] = { static struct hisi_clock_data *hi3519_clk_register(struct platform_device *pdev) { + struct device *dev = &pdev->dev; struct hisi_clock_data *clk_data; int ret; @@ -82,62 +83,34 @@ static struct hisi_clock_data *hi3519_clk_register(struct platform_device *pdev) if (!clk_data) return ERR_PTR(-ENOMEM); - ret = hisi_clk_register_fixed_rate(hi3519_fixed_rate_clks, + ret = hisi_clk_register_fixed_rate(dev, hi3519_fixed_rate_clks, ARRAY_SIZE(hi3519_fixed_rate_clks), clk_data); if (ret) return ERR_PTR(ret); - ret = hisi_clk_register_mux(hi3519_mux_clks, + ret = hisi_clk_register_mux(dev, hi3519_mux_clks, ARRAY_SIZE(hi3519_mux_clks), clk_data); if (ret) - goto unregister_fixed_rate; + return ERR_PTR(ret); - ret = hisi_clk_register_gate(hi3519_gate_clks, + ret = hisi_clk_register_gate(dev, hi3519_gate_clks, ARRAY_SIZE(hi3519_gate_clks), clk_data); if (ret) - goto unregister_mux; + return ERR_PTR(ret); - ret = of_clk_add_provider(pdev->dev.of_node, - of_clk_src_onecell_get, &clk_data->clk_data); + ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, + clk_data->clk_data); if (ret) - goto unregister_gate; + return ERR_PTR(ret); return clk_data; - -unregister_fixed_rate: - hisi_clk_unregister_fixed_rate(hi3519_fixed_rate_clks, - ARRAY_SIZE(hi3519_fixed_rate_clks), - clk_data); - -unregister_mux: - hisi_clk_unregister_mux(hi3519_mux_clks, - ARRAY_SIZE(hi3519_mux_clks), - clk_data); -unregister_gate: - hisi_clk_unregister_gate(hi3519_gate_clks, - ARRAY_SIZE(hi3519_gate_clks), - clk_data); - return ERR_PTR(ret); } static void hi3519_clk_unregister(struct platform_device *pdev) { - struct hi3519_crg_data *crg = platform_get_drvdata(pdev); - - of_clk_del_provider(pdev->dev.of_node); - - hisi_clk_unregister_gate(hi3519_gate_clks, - ARRAY_SIZE(hi3519_mux_clks), - crg->clk_data); - hisi_clk_unregister_mux(hi3519_mux_clks, - ARRAY_SIZE(hi3519_mux_clks), - crg->clk_data); - hisi_clk_unregister_fixed_rate(hi3519_fixed_rate_clks, - ARRAY_SIZE(hi3519_fixed_rate_clks), - crg->clk_data); } static int hi3519_clk_probe(struct platform_device *pdev) diff --git a/drivers/clk/hisilicon/clk-hi3559a.c b/drivers/clk/hisilicon/clk-hi3559a.c index 8036bd8cb..7dbfd949a 100644 --- a/drivers/clk/hisilicon/clk-hi3559a.c +++ b/drivers/clk/hisilicon/clk-hi3559a.c @@ -452,19 +452,20 @@ static const struct clk_ops hisi_clk_pll_ops = { .recalc_rate = clk_pll_recalc_rate, }; -static void hisi_clk_register_pll(struct hi3559av100_pll_clock *clks, - int nums, struct hisi_clock_data *data, struct device *dev) +static int hisi_clk_register_pll(struct device *dev, + const struct hi3559av100_pll_clock *clks, + int nums, struct hisi_clock_data *data) { void __iomem *base = data->base; struct hi3559av100_clk_pll *p_clk = NULL; - struct clk *clk = NULL; struct clk_init_data init; int i; + int ret; p_clk = devm_kzalloc(dev, sizeof(*p_clk) * nums, GFP_KERNEL); if (!p_clk) - return; + return 0; for (i = 0; i < nums; i++) { init.name = clks[i].name; @@ -489,22 +490,24 @@ static void hisi_clk_register_pll(struct hi3559av100_pll_clock *clks, p_clk->refdiv_width = clks[i].refdiv_width; p_clk->hw.init = &init; - clk = clk_register(NULL, &p_clk->hw); - if (IS_ERR(clk)) { - devm_kfree(dev, p_clk); + ret = devm_clk_hw_register(dev, &p_clk->hw); + if (ret) { dev_err(dev, "%s: failed to register clock %s\n", __func__, clks[i].name); - continue; + return ret; } - data->clk_data.clks[clks[i].id] = clk; + data->clk_data->hws[clks[i].id] = &p_clk->hw; p_clk++; } + + return 0; } static struct hisi_clock_data *hi3559av100_clk_register( struct platform_device *pdev) { + struct device *dev = &pdev->dev; struct hisi_clock_data *clk_data; int ret; @@ -512,55 +515,36 @@ static struct hisi_clock_data *hi3559av100_clk_register( if (!clk_data) return ERR_PTR(-ENOMEM); - ret = hisi_clk_register_fixed_rate(hi3559av100_fixed_rate_clks_crg, + ret = hisi_clk_register_fixed_rate(dev, hi3559av100_fixed_rate_clks_crg, ARRAY_SIZE(hi3559av100_fixed_rate_clks_crg), clk_data); if (ret) return ERR_PTR(ret); - hisi_clk_register_pll(hi3559av100_pll_clks, - ARRAY_SIZE(hi3559av100_pll_clks), clk_data, &pdev->dev); + ret = hisi_clk_register_pll(dev, hi3559av100_pll_clks, + ARRAY_SIZE(hi3559av100_pll_clks), clk_data); + if (ret) + return ERR_PTR(ret); - ret = hisi_clk_register_mux(hi3559av100_mux_clks_crg, + ret = hisi_clk_register_mux(dev, hi3559av100_mux_clks_crg, ARRAY_SIZE(hi3559av100_mux_clks_crg), clk_data); if (ret) - goto unregister_fixed_rate; + return ERR_PTR(ret); - ret = hisi_clk_register_gate(hi3559av100_gate_clks, + ret = hisi_clk_register_gate(dev, hi3559av100_gate_clks, ARRAY_SIZE(hi3559av100_gate_clks), clk_data); if (ret) - goto unregister_mux; + return ERR_PTR(ret); - ret = of_clk_add_provider(pdev->dev.of_node, - of_clk_src_onecell_get, &clk_data->clk_data); + ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, + clk_data->clk_data); if (ret) - goto unregister_gate; + return ERR_PTR(ret); return clk_data; - -unregister_gate: - hisi_clk_unregister_gate(hi3559av100_gate_clks, - ARRAY_SIZE(hi3559av100_gate_clks), clk_data); -unregister_mux: - hisi_clk_unregister_mux(hi3559av100_mux_clks_crg, - ARRAY_SIZE(hi3559av100_mux_clks_crg), clk_data); -unregister_fixed_rate: - hisi_clk_unregister_fixed_rate(hi3559av100_fixed_rate_clks_crg, - ARRAY_SIZE(hi3559av100_fixed_rate_clks_crg), clk_data); - return ERR_PTR(ret); } static void hi3559av100_clk_unregister(struct platform_device *pdev) { - struct hisi_crg_dev *crg = platform_get_drvdata(pdev); - - of_clk_del_provider(pdev->dev.of_node); - - hisi_clk_unregister_gate(hi3559av100_gate_clks, - ARRAY_SIZE(hi3559av100_gate_clks), crg->clk_data); - hisi_clk_unregister_mux(hi3559av100_mux_clks_crg, - ARRAY_SIZE(hi3559av100_mux_clks_crg), crg->clk_data); - hisi_clk_unregister_fixed_rate(hi3559av100_fixed_rate_clks_crg, - ARRAY_SIZE(hi3559av100_fixed_rate_clks_crg), crg->clk_data); } static const struct hisi_crg_funcs hi3559av100_crg_funcs = { @@ -699,6 +683,7 @@ static int hi3559av100_shub_default_clk_set(void) static struct hisi_clock_data *hi3559av100_shub_clk_register( struct platform_device *pdev) { + struct device *dev = &pdev->dev; struct hisi_clock_data *clk_data = NULL; int ret; @@ -708,62 +693,36 @@ static struct hisi_clock_data *hi3559av100_shub_clk_register( if (!clk_data) return ERR_PTR(-ENOMEM); - ret = hisi_clk_register_fixed_rate(hi3559av100_shub_fixed_rate_clks, + ret = hisi_clk_register_fixed_rate(dev, hi3559av100_shub_fixed_rate_clks, ARRAY_SIZE(hi3559av100_shub_fixed_rate_clks), clk_data); if (ret) return ERR_PTR(ret); - ret = hisi_clk_register_mux(hi3559av100_shub_mux_clks, + ret = hisi_clk_register_mux(dev, hi3559av100_shub_mux_clks, ARRAY_SIZE(hi3559av100_shub_mux_clks), clk_data); if (ret) - goto unregister_fixed_rate; + return ERR_PTR(ret); - ret = hisi_clk_register_divider(hi3559av100_shub_div_clks, + ret = hisi_clk_register_divider(dev, hi3559av100_shub_div_clks, ARRAY_SIZE(hi3559av100_shub_div_clks), clk_data); if (ret) - goto unregister_mux; + return ERR_PTR(ret); - ret = hisi_clk_register_gate(hi3559av100_shub_gate_clks, + ret = hisi_clk_register_gate(dev, hi3559av100_shub_gate_clks, ARRAY_SIZE(hi3559av100_shub_gate_clks), clk_data); if (ret) - goto unregister_factor; + return ERR_PTR(ret); - ret = of_clk_add_provider(pdev->dev.of_node, - of_clk_src_onecell_get, &clk_data->clk_data); + ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, + clk_data->clk_data); if (ret) - goto unregister_gate; + return ERR_PTR(ret); return clk_data; - -unregister_gate: - hisi_clk_unregister_gate(hi3559av100_shub_gate_clks, - ARRAY_SIZE(hi3559av100_shub_gate_clks), clk_data); -unregister_factor: - hisi_clk_unregister_divider(hi3559av100_shub_div_clks, - ARRAY_SIZE(hi3559av100_shub_div_clks), clk_data); -unregister_mux: - hisi_clk_unregister_mux(hi3559av100_shub_mux_clks, - ARRAY_SIZE(hi3559av100_shub_mux_clks), clk_data); -unregister_fixed_rate: - hisi_clk_unregister_fixed_rate(hi3559av100_shub_fixed_rate_clks, - ARRAY_SIZE(hi3559av100_shub_fixed_rate_clks), clk_data); - return ERR_PTR(ret); } static void hi3559av100_shub_clk_unregister(struct platform_device *pdev) { - struct hisi_crg_dev *crg = platform_get_drvdata(pdev); - - of_clk_del_provider(pdev->dev.of_node); - - hisi_clk_unregister_gate(hi3559av100_shub_gate_clks, - ARRAY_SIZE(hi3559av100_shub_gate_clks), crg->clk_data); - hisi_clk_unregister_divider(hi3559av100_shub_div_clks, - ARRAY_SIZE(hi3559av100_shub_div_clks), crg->clk_data); - hisi_clk_unregister_mux(hi3559av100_shub_mux_clks, - ARRAY_SIZE(hi3559av100_shub_mux_clks), crg->clk_data); - hisi_clk_unregister_fixed_rate(hi3559av100_shub_fixed_rate_clks, - ARRAY_SIZE(hi3559av100_shub_fixed_rate_clks), crg->clk_data); } static const struct hisi_crg_funcs hi3559av100_shub_crg_funcs = { diff --git a/drivers/clk/hisilicon/clk-hi3620.c b/drivers/clk/hisilicon/clk-hi3620.c index a3d04c7c3..d6307a8cd 100644 --- a/drivers/clk/hisilicon/clk-hi3620.c +++ b/drivers/clk/hisilicon/clk-hi3620.c @@ -194,23 +194,25 @@ static struct hisi_gate_clock hi3620_separated_gate_clks[] __initdata = { static void __init hi3620_clk_init(struct device_node *np) { + struct platform_device *pdev = of_find_device_by_node(np); + struct device *dev = &pdev->dev; struct hisi_clock_data *clk_data; clk_data = hisi_clk_init(np, HI3620_NR_CLKS); if (!clk_data) return; - hisi_clk_register_fixed_rate(hi3620_fixed_rate_clks, + hisi_clk_register_fixed_rate(dev, hi3620_fixed_rate_clks, ARRAY_SIZE(hi3620_fixed_rate_clks), clk_data); - hisi_clk_register_fixed_factor(hi3620_fixed_factor_clks, + hisi_clk_register_fixed_factor(dev, hi3620_fixed_factor_clks, ARRAY_SIZE(hi3620_fixed_factor_clks), clk_data); - hisi_clk_register_mux(hi3620_mux_clks, ARRAY_SIZE(hi3620_mux_clks), + hisi_clk_register_mux(dev, hi3620_mux_clks, ARRAY_SIZE(hi3620_mux_clks), clk_data); - hisi_clk_register_divider(hi3620_div_clks, ARRAY_SIZE(hi3620_div_clks), + hisi_clk_register_divider(dev, hi3620_div_clks, ARRAY_SIZE(hi3620_div_clks), clk_data); - hisi_clk_register_gate_sep(hi3620_separated_gate_clks, + hisi_clk_register_gate_sep(dev, hi3620_separated_gate_clks, ARRAY_SIZE(hi3620_separated_gate_clks), clk_data); } diff --git a/drivers/clk/hisilicon/clk-hi3660.c b/drivers/clk/hisilicon/clk-hi3660.c index 41f61726a..d605c2a08 100644 --- a/drivers/clk/hisilicon/clk-hi3660.c +++ b/drivers/clk/hisilicon/clk-hi3660.c @@ -473,6 +473,8 @@ static struct hisi_clock_data *clk_crgctrl_data; static void hi3660_clk_iomcu_init(struct device_node *np) { + struct platform_device *pdev = of_find_device_by_node(np); + struct device *dev = &pdev->dev; struct hisi_clock_data *clk_data; int nr = ARRAY_SIZE(hi3660_iomcu_gate_sep_clks); @@ -480,13 +482,15 @@ static void hi3660_clk_iomcu_init(struct device_node *np) if (!clk_data) return; - hisi_clk_register_gate_sep(hi3660_iomcu_gate_sep_clks, + hisi_clk_register_gate_sep(dev, hi3660_iomcu_gate_sep_clks, ARRAY_SIZE(hi3660_iomcu_gate_sep_clks), clk_data); } static void hi3660_clk_pmuctrl_init(struct device_node *np) { + struct platform_device *pdev = of_find_device_by_node(np); + struct device *dev = &pdev->dev; struct hisi_clock_data *clk_data; int nr = ARRAY_SIZE(hi3660_pmu_gate_clks); @@ -494,24 +498,28 @@ static void hi3660_clk_pmuctrl_init(struct device_node *np) if (!clk_data) return; - hisi_clk_register_gate(hi3660_pmu_gate_clks, + hisi_clk_register_gate(dev, hi3660_pmu_gate_clks, ARRAY_SIZE(hi3660_pmu_gate_clks), clk_data); } static void hi3660_clk_pctrl_init(struct device_node *np) { + struct platform_device *pdev = of_find_device_by_node(np); + struct device *dev = &pdev->dev; struct hisi_clock_data *clk_data; int nr = ARRAY_SIZE(hi3660_pctrl_gate_clks); clk_data = hisi_clk_init(np, nr); if (!clk_data) return; - hisi_clk_register_gate(hi3660_pctrl_gate_clks, + hisi_clk_register_gate(dev, hi3660_pctrl_gate_clks, ARRAY_SIZE(hi3660_pctrl_gate_clks), clk_data); } static void hi3660_clk_sctrl_init(struct device_node *np) { + struct platform_device *pdev = of_find_device_by_node(np); + struct device *dev = &pdev->dev; struct hisi_clock_data *clk_data; int nr = ARRAY_SIZE(hi3660_sctrl_gate_clks) + ARRAY_SIZE(hi3660_sctrl_gate_sep_clks) + @@ -521,20 +529,22 @@ static void hi3660_clk_sctrl_init(struct device_node *np) clk_data = hisi_clk_init(np, nr); if (!clk_data) return; - hisi_clk_register_gate(hi3660_sctrl_gate_clks, + hisi_clk_register_gate(dev, hi3660_sctrl_gate_clks, ARRAY_SIZE(hi3660_sctrl_gate_clks), clk_data); - hisi_clk_register_gate_sep(hi3660_sctrl_gate_sep_clks, + hisi_clk_register_gate_sep(dev, hi3660_sctrl_gate_sep_clks, ARRAY_SIZE(hi3660_sctrl_gate_sep_clks), clk_data); - hisi_clk_register_mux(hi3660_sctrl_mux_clks, + hisi_clk_register_mux(dev, hi3660_sctrl_mux_clks, ARRAY_SIZE(hi3660_sctrl_mux_clks), clk_data); - hisi_clk_register_divider(hi3660_sctrl_divider_clks, + hisi_clk_register_divider(dev, hi3660_sctrl_divider_clks, ARRAY_SIZE(hi3660_sctrl_divider_clks), clk_data); } static void hi3660_clk_crgctrl_early_init(struct device_node *np) { + struct platform_device *pdev = of_find_device_by_node(np); + struct device *dev = &pdev->dev; int nr = ARRAY_SIZE(hi3660_fixed_rate_clks) + ARRAY_SIZE(hi3660_crgctrl_gate_sep_clks) + ARRAY_SIZE(hi3660_crgctrl_gate_clks) + @@ -548,9 +558,9 @@ static void hi3660_clk_crgctrl_early_init(struct device_node *np) return; for (i = 0; i < nr; i++) - clk_crgctrl_data->clk_data.clks[i] = ERR_PTR(-EPROBE_DEFER); + clk_crgctrl_data->clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER); - hisi_clk_register_fixed_rate(hi3660_fixed_rate_clks, + hisi_clk_register_fixed_rate(dev, hi3660_fixed_rate_clks, ARRAY_SIZE(hi3660_fixed_rate_clks), clk_crgctrl_data); } @@ -559,7 +569,9 @@ CLK_OF_DECLARE_DRIVER(hi3660_clk_crgctrl, "hisilicon,hi3660-crgctrl", static void hi3660_clk_crgctrl_init(struct device_node *np) { - struct clk **clks; + struct platform_device *pdev = of_find_device_by_node(np); + struct device *dev = &pdev->dev; + struct clk_hw **clks; int i; if (!clk_crgctrl_data) @@ -569,24 +581,24 @@ static void hi3660_clk_crgctrl_init(struct device_node *np) if (!clk_crgctrl_data) return; - hisi_clk_register_gate_sep(hi3660_crgctrl_gate_sep_clks, + hisi_clk_register_gate_sep(dev, hi3660_crgctrl_gate_sep_clks, ARRAY_SIZE(hi3660_crgctrl_gate_sep_clks), clk_crgctrl_data); - hisi_clk_register_gate(hi3660_crgctrl_gate_clks, + hisi_clk_register_gate(dev, hi3660_crgctrl_gate_clks, ARRAY_SIZE(hi3660_crgctrl_gate_clks), clk_crgctrl_data); - hisi_clk_register_mux(hi3660_crgctrl_mux_clks, + hisi_clk_register_mux(dev, hi3660_crgctrl_mux_clks, ARRAY_SIZE(hi3660_crgctrl_mux_clks), clk_crgctrl_data); - hisi_clk_register_fixed_factor(hi3660_crg_fixed_factor_clks, + hisi_clk_register_fixed_factor(dev, hi3660_crg_fixed_factor_clks, ARRAY_SIZE(hi3660_crg_fixed_factor_clks), clk_crgctrl_data); - hisi_clk_register_divider(hi3660_crgctrl_divider_clks, + hisi_clk_register_divider(dev, hi3660_crgctrl_divider_clks, ARRAY_SIZE(hi3660_crgctrl_divider_clks), clk_crgctrl_data); - clks = clk_crgctrl_data->clk_data.clks; - for (i = 0; i < clk_crgctrl_data->clk_data.clk_num; i++) { + clks = clk_crgctrl_data->clk_data->hws; + for (i = 0; i < clk_crgctrl_data->clk_data->num; i++) { if (IS_ERR(clks[i]) && PTR_ERR(clks[i]) != -EPROBE_DEFER) pr_err("Failed to register crgctrl clock[%d] err=%ld\n", i, PTR_ERR(clks[i])); diff --git a/drivers/clk/hisilicon/clk-hi3670.c b/drivers/clk/hisilicon/clk-hi3670.c index 4d05a7168..1e6da7cc2 100644 --- a/drivers/clk/hisilicon/clk-hi3670.c +++ b/drivers/clk/hisilicon/clk-hi3670.c @@ -824,6 +824,8 @@ static const struct hisi_gate_clock hi3670_media2_gate_sep_clks[] = { static void hi3670_clk_crgctrl_init(struct device_node *np) { + struct platform_device *pdev = of_find_device_by_node(np); + struct device *dev = &pdev->dev; struct hisi_clock_data *clk_data; int nr = ARRAY_SIZE(hi3670_fixed_rate_clks) + @@ -837,40 +839,44 @@ static void hi3670_clk_crgctrl_init(struct device_node *np) if (!clk_data) return; - hisi_clk_register_fixed_rate(hi3670_fixed_rate_clks, + hisi_clk_register_fixed_rate(dev, hi3670_fixed_rate_clks, ARRAY_SIZE(hi3670_fixed_rate_clks), clk_data); - hisi_clk_register_gate_sep(hi3670_crgctrl_gate_sep_clks, + hisi_clk_register_gate_sep(dev, hi3670_crgctrl_gate_sep_clks, ARRAY_SIZE(hi3670_crgctrl_gate_sep_clks), clk_data); - hisi_clk_register_gate(hi3670_crgctrl_gate_clks, + hisi_clk_register_gate(dev, hi3670_crgctrl_gate_clks, ARRAY_SIZE(hi3670_crgctrl_gate_clks), clk_data); - hisi_clk_register_mux(hi3670_crgctrl_mux_clks, + hisi_clk_register_mux(dev, hi3670_crgctrl_mux_clks, ARRAY_SIZE(hi3670_crgctrl_mux_clks), clk_data); - hisi_clk_register_fixed_factor(hi3670_crg_fixed_factor_clks, + hisi_clk_register_fixed_factor(dev, hi3670_crg_fixed_factor_clks, ARRAY_SIZE(hi3670_crg_fixed_factor_clks), clk_data); - hisi_clk_register_divider(hi3670_crgctrl_divider_clks, + hisi_clk_register_divider(dev, hi3670_crgctrl_divider_clks, ARRAY_SIZE(hi3670_crgctrl_divider_clks), clk_data); } static void hi3670_clk_pctrl_init(struct device_node *np) { + struct platform_device *pdev = of_find_device_by_node(np); + struct device *dev = &pdev->dev; struct hisi_clock_data *clk_data; int nr = ARRAY_SIZE(hi3670_pctrl_gate_clks); clk_data = hisi_clk_init(np, nr); if (!clk_data) return; - hisi_clk_register_gate(hi3670_pctrl_gate_clks, + hisi_clk_register_gate(dev, hi3670_pctrl_gate_clks, ARRAY_SIZE(hi3670_pctrl_gate_clks), clk_data); } static void hi3670_clk_pmuctrl_init(struct device_node *np) { + struct platform_device *pdev = of_find_device_by_node(np); + struct device *dev = &pdev->dev; struct hisi_clock_data *clk_data; int nr = ARRAY_SIZE(hi3670_pmu_gate_clks); @@ -878,12 +884,14 @@ static void hi3670_clk_pmuctrl_init(struct device_node *np) if (!clk_data) return; - hisi_clk_register_gate(hi3670_pmu_gate_clks, + hisi_clk_register_gate(dev, hi3670_pmu_gate_clks, ARRAY_SIZE(hi3670_pmu_gate_clks), clk_data); } static void hi3670_clk_sctrl_init(struct device_node *np) { + struct platform_device *pdev = of_find_device_by_node(np); + struct device *dev = &pdev->dev; struct hisi_clock_data *clk_data; int nr = ARRAY_SIZE(hi3670_sctrl_gate_sep_clks) + ARRAY_SIZE(hi3670_sctrl_gate_clks) + @@ -894,22 +902,24 @@ static void hi3670_clk_sctrl_init(struct device_node *np) if (!clk_data) return; - hisi_clk_register_gate_sep(hi3670_sctrl_gate_sep_clks, + hisi_clk_register_gate_sep(dev, hi3670_sctrl_gate_sep_clks, ARRAY_SIZE(hi3670_sctrl_gate_sep_clks), clk_data); - hisi_clk_register_gate(hi3670_sctrl_gate_clks, + hisi_clk_register_gate(dev, hi3670_sctrl_gate_clks, ARRAY_SIZE(hi3670_sctrl_gate_clks), clk_data); - hisi_clk_register_mux(hi3670_sctrl_mux_clks, + hisi_clk_register_mux(dev, hi3670_sctrl_mux_clks, ARRAY_SIZE(hi3670_sctrl_mux_clks), clk_data); - hisi_clk_register_divider(hi3670_sctrl_divider_clks, + hisi_clk_register_divider(dev, hi3670_sctrl_divider_clks, ARRAY_SIZE(hi3670_sctrl_divider_clks), clk_data); } static void hi3670_clk_iomcu_init(struct device_node *np) { + struct platform_device *pdev = of_find_device_by_node(np); + struct device *dev = &pdev->dev; struct hisi_clock_data *clk_data; int nr = ARRAY_SIZE(hi3670_iomcu_gate_sep_clks) + ARRAY_SIZE(hi3670_iomcu_fixed_factor_clks); @@ -918,16 +928,18 @@ static void hi3670_clk_iomcu_init(struct device_node *np) if (!clk_data) return; - hisi_clk_register_gate(hi3670_iomcu_gate_sep_clks, + hisi_clk_register_gate(dev, hi3670_iomcu_gate_sep_clks, ARRAY_SIZE(hi3670_iomcu_gate_sep_clks), clk_data); - hisi_clk_register_fixed_factor(hi3670_iomcu_fixed_factor_clks, + hisi_clk_register_fixed_factor(dev, hi3670_iomcu_fixed_factor_clks, ARRAY_SIZE(hi3670_iomcu_fixed_factor_clks), clk_data); } static void hi3670_clk_media1_init(struct device_node *np) { + struct platform_device *pdev = of_find_device_by_node(np); + struct device *dev = &pdev->dev; struct hisi_clock_data *clk_data; int nr = ARRAY_SIZE(hi3670_media1_gate_sep_clks) + @@ -939,22 +951,24 @@ static void hi3670_clk_media1_init(struct device_node *np) if (!clk_data) return; - hisi_clk_register_gate_sep(hi3670_media1_gate_sep_clks, + hisi_clk_register_gate_sep(dev, hi3670_media1_gate_sep_clks, ARRAY_SIZE(hi3670_media1_gate_sep_clks), clk_data); - hisi_clk_register_gate(hi3670_media1_gate_clks, + hisi_clk_register_gate(dev, hi3670_media1_gate_clks, ARRAY_SIZE(hi3670_media1_gate_clks), clk_data); - hisi_clk_register_mux(hi3670_media1_mux_clks, + hisi_clk_register_mux(dev, hi3670_media1_mux_clks, ARRAY_SIZE(hi3670_media1_mux_clks), clk_data); - hisi_clk_register_divider(hi3670_media1_divider_clks, + hisi_clk_register_divider(dev, hi3670_media1_divider_clks, ARRAY_SIZE(hi3670_media1_divider_clks), clk_data); } static void hi3670_clk_media2_init(struct device_node *np) { + struct platform_device *pdev = of_find_device_by_node(np); + struct device *dev = &pdev->dev; struct hisi_clock_data *clk_data; int nr = ARRAY_SIZE(hi3670_media2_gate_sep_clks); @@ -963,7 +977,7 @@ static void hi3670_clk_media2_init(struct device_node *np) if (!clk_data) return; - hisi_clk_register_gate_sep(hi3670_media2_gate_sep_clks, + hisi_clk_register_gate_sep(dev, hi3670_media2_gate_sep_clks, ARRAY_SIZE(hi3670_media2_gate_sep_clks), clk_data); } diff --git a/drivers/clk/hisilicon/clk-hi6220.c b/drivers/clk/hisilicon/clk-hi6220.c index e7cdf72d4..892f3d61f 100644 --- a/drivers/clk/hisilicon/clk-hi6220.c +++ b/drivers/clk/hisilicon/clk-hi6220.c @@ -71,19 +71,21 @@ static struct hisi_gate_clock hi6220_separated_gate_clks_ao[] __initdata = { static void __init hi6220_clk_ao_init(struct device_node *np) { + struct platform_device *pdev = of_find_device_by_node(np); + struct device *dev = &pdev->dev; struct hisi_clock_data *clk_data_ao; clk_data_ao = hisi_clk_init(np, HI6220_AO_NR_CLKS); if (!clk_data_ao) return; - hisi_clk_register_fixed_rate(hi6220_fixed_rate_clks, + hisi_clk_register_fixed_rate(dev, hi6220_fixed_rate_clks, ARRAY_SIZE(hi6220_fixed_rate_clks), clk_data_ao); - hisi_clk_register_fixed_factor(hi6220_fixed_factor_clks, + hisi_clk_register_fixed_factor(dev, hi6220_fixed_factor_clks, ARRAY_SIZE(hi6220_fixed_factor_clks), clk_data_ao); - hisi_clk_register_gate_sep(hi6220_separated_gate_clks_ao, + hisi_clk_register_gate_sep(dev, hi6220_separated_gate_clks_ao, ARRAY_SIZE(hi6220_separated_gate_clks_ao), clk_data_ao); } /* Allow reset driver to probe as well */ @@ -179,19 +181,21 @@ static struct hi6220_divider_clock hi6220_div_clks_sys[] __initdata = { static void __init hi6220_clk_sys_init(struct device_node *np) { + struct platform_device *pdev = of_find_device_by_node(np); + struct device *dev = &pdev->dev; struct hisi_clock_data *clk_data; clk_data = hisi_clk_init(np, HI6220_SYS_NR_CLKS); if (!clk_data) return; - hisi_clk_register_gate_sep(hi6220_separated_gate_clks_sys, + hisi_clk_register_gate_sep(dev, hi6220_separated_gate_clks_sys, ARRAY_SIZE(hi6220_separated_gate_clks_sys), clk_data); - hisi_clk_register_mux(hi6220_mux_clks_sys, + hisi_clk_register_mux(dev, hi6220_mux_clks_sys, ARRAY_SIZE(hi6220_mux_clks_sys), clk_data); - hi6220_clk_register_divider(hi6220_div_clks_sys, + hi6220_clk_register_divider(dev, hi6220_div_clks_sys, ARRAY_SIZE(hi6220_div_clks_sys), clk_data); } CLK_OF_DECLARE_DRIVER(hi6220_clk_sys, "hisilicon,hi6220-sysctrl", hi6220_clk_sys_init); @@ -236,19 +240,21 @@ static struct hi6220_divider_clock hi6220_div_clks_media[] __initdata = { static void __init hi6220_clk_media_init(struct device_node *np) { + struct platform_device *pdev = of_find_device_by_node(np); + struct device *dev = &pdev->dev; struct hisi_clock_data *clk_data; clk_data = hisi_clk_init(np, HI6220_MEDIA_NR_CLKS); if (!clk_data) return; - hisi_clk_register_gate_sep(hi6220_separated_gate_clks_media, + hisi_clk_register_gate_sep(dev, hi6220_separated_gate_clks_media, ARRAY_SIZE(hi6220_separated_gate_clks_media), clk_data); - hisi_clk_register_mux(hi6220_mux_clks_media, + hisi_clk_register_mux(dev, hi6220_mux_clks_media, ARRAY_SIZE(hi6220_mux_clks_media), clk_data); - hi6220_clk_register_divider(hi6220_div_clks_media, + hi6220_clk_register_divider(dev, hi6220_div_clks_media, ARRAY_SIZE(hi6220_div_clks_media), clk_data); } CLK_OF_DECLARE_DRIVER(hi6220_clk_media, "hisilicon,hi6220-mediactrl", hi6220_clk_media_init); @@ -270,16 +276,18 @@ static struct hi6220_divider_clock hi6220_div_clks_power[] __initdata = { static void __init hi6220_clk_power_init(struct device_node *np) { + struct platform_device *pdev = of_find_device_by_node(np); + struct device *dev = &pdev->dev; struct hisi_clock_data *clk_data; clk_data = hisi_clk_init(np, HI6220_POWER_NR_CLKS); if (!clk_data) return; - hisi_clk_register_gate(hi6220_gate_clks_power, + hisi_clk_register_gate(dev, hi6220_gate_clks_power, ARRAY_SIZE(hi6220_gate_clks_power), clk_data); - hi6220_clk_register_divider(hi6220_div_clks_power, + hi6220_clk_register_divider(dev, hi6220_div_clks_power, ARRAY_SIZE(hi6220_div_clks_power), clk_data); } CLK_OF_DECLARE(hi6220_clk_power, "hisilicon,hi6220-pmctrl", hi6220_clk_power_init); @@ -292,6 +300,8 @@ static const struct hisi_gate_clock hi6220_acpu_sc_gate_sep_clks[] = { static void __init hi6220_clk_acpu_init(struct device_node *np) { + struct platform_device *pdev = of_find_device_by_node(np); + struct device *dev = &pdev->dev; struct hisi_clock_data *clk_data; int nr = ARRAY_SIZE(hi6220_acpu_sc_gate_sep_clks); @@ -299,7 +309,7 @@ static void __init hi6220_clk_acpu_init(struct device_node *np) if (!clk_data) return; - hisi_clk_register_gate_sep(hi6220_acpu_sc_gate_sep_clks, + hisi_clk_register_gate_sep(dev, hi6220_acpu_sc_gate_sep_clks, ARRAY_SIZE(hi6220_acpu_sc_gate_sep_clks), clk_data); } diff --git a/drivers/clk/hisilicon/clk-hip04.c b/drivers/clk/hisilicon/clk-hip04.c index 785b9faf3..babb45bce 100644 --- a/drivers/clk/hisilicon/clk-hip04.c +++ b/drivers/clk/hisilicon/clk-hip04.c @@ -29,13 +29,15 @@ static struct hisi_fixed_rate_clock hip04_fixed_rate_clks[] __initdata = { static void __init hip04_clk_init(struct device_node *np) { + struct platform_device *pdev = of_find_device_by_node(np); + struct device *dev = &pdev->dev; struct hisi_clock_data *clk_data; clk_data = hisi_clk_init(np, HIP04_NR_CLKS); if (!clk_data) return; - hisi_clk_register_fixed_rate(hip04_fixed_rate_clks, + hisi_clk_register_fixed_rate(dev, hip04_fixed_rate_clks, ARRAY_SIZE(hip04_fixed_rate_clks), clk_data); } diff --git a/drivers/clk/hisilicon/clk-hisi-phase.c b/drivers/clk/hisilicon/clk-hisi-phase.c index ba6afad66..cea5c773c 100644 --- a/drivers/clk/hisilicon/clk-hisi-phase.c +++ b/drivers/clk/hisilicon/clk-hisi-phase.c @@ -5,11 +5,11 @@ * Simple HiSilicon phase clock implementation. */ +#include #include #include #include #include -#include #include "clk.h" @@ -90,14 +90,15 @@ static const struct clk_ops clk_phase_ops = { .set_phase = hisi_clk_set_phase, }; -struct clk *clk_register_hisi_phase(struct device *dev, +struct clk_hw *devm_clk_hw_register_hisi_phase(struct device *dev, const struct hisi_phase_clock *clks, void __iomem *base, spinlock_t *lock) { struct clk_hisi_phase *phase; struct clk_init_data init; + int ret; - phase = devm_kzalloc(dev, sizeof(struct clk_hisi_phase), GFP_KERNEL); + phase = devm_kzalloc(dev, sizeof(*phase), GFP_KERNEL); if (!phase) return ERR_PTR(-ENOMEM); @@ -116,6 +117,10 @@ struct clk *clk_register_hisi_phase(struct device *dev, phase->phase_num = clks->phase_num; phase->hw.init = &init; - return devm_clk_register(dev, &phase->hw); + ret = devm_clk_hw_register(dev, &phase->hw); + if (ret) + return ERR_PTR(ret); + + return &phase->hw; } -EXPORT_SYMBOL_GPL(clk_register_hisi_phase); +EXPORT_SYMBOL_GPL(devm_clk_hw_register_hisi_phase); diff --git a/drivers/clk/hisilicon/clk-hix5hd2.c b/drivers/clk/hisilicon/clk-hix5hd2.c index 64bdd3f05..368ef02a1 100644 --- a/drivers/clk/hisilicon/clk-hix5hd2.c +++ b/drivers/clk/hisilicon/clk-hix5hd2.c @@ -249,21 +249,23 @@ static const struct clk_ops clk_complex_ops = { .disable = clk_complex_disable, }; -static void __init -hix5hd2_clk_register_complex(struct hix5hd2_complex_clock *clks, int nums, +static int __init +hix5hd2_clk_register_complex(struct device *dev, + struct hix5hd2_complex_clock *clks, int nums, struct hisi_clock_data *data) { void __iomem *base = data->base; int i; + int ret; for (i = 0; i < nums; i++) { struct hix5hd2_clk_complex *p_clk; - struct clk *clk; + struct clk_hw *clk; struct clk_init_data init; - p_clk = kzalloc(sizeof(*p_clk), GFP_KERNEL); + p_clk = devm_kzalloc(dev, sizeof(*p_clk), GFP_KERNEL); if (!p_clk) - return; + return 0; init.name = clks[i].name; if (clks[i].type == TYPE_ETHER) @@ -284,34 +286,37 @@ hix5hd2_clk_register_complex(struct hix5hd2_complex_clock *clks, int nums, p_clk->phy_rst_mask = clks[i].phy_rst_mask; p_clk->hw.init = &init; - clk = clk_register(NULL, &p_clk->hw); - if (IS_ERR(clk)) { - kfree(p_clk); + ret = devm_clk_hw_register(dev, &p_clk->hw); + if (ret) { pr_err("%s: failed to register clock %s\n", __func__, clks[i].name); - continue; + return ret; } - data->clk_data.clks[clks[i].id] = clk; + data->clk_data->hws[clks[i].id] = &p_clk->hw; } + + return 0; } static void __init hix5hd2_clk_init(struct device_node *np) { + struct platform_device *pdev = of_find_device_by_node(np); + struct device *dev = &pdev->dev; struct hisi_clock_data *clk_data; clk_data = hisi_clk_init(np, HIX5HD2_NR_CLKS); if (!clk_data) return; - hisi_clk_register_fixed_rate(hix5hd2_fixed_rate_clks, + hisi_clk_register_fixed_rate(dev, hix5hd2_fixed_rate_clks, ARRAY_SIZE(hix5hd2_fixed_rate_clks), clk_data); - hisi_clk_register_mux(hix5hd2_mux_clks, ARRAY_SIZE(hix5hd2_mux_clks), + hisi_clk_register_mux(dev, hix5hd2_mux_clks, ARRAY_SIZE(hix5hd2_mux_clks), clk_data); - hisi_clk_register_gate(hix5hd2_gate_clks, + hisi_clk_register_gate(dev, hix5hd2_gate_clks, ARRAY_SIZE(hix5hd2_gate_clks), clk_data); - hix5hd2_clk_register_complex(hix5hd2_complex_clks, + hix5hd2_clk_register_complex(dev, hix5hd2_complex_clks, ARRAY_SIZE(hix5hd2_complex_clks), clk_data); } diff --git a/drivers/clk/hisilicon/clk.c b/drivers/clk/hisilicon/clk.c index 54d9fdc93..33a312935 100644 --- a/drivers/clk/hisilicon/clk.c +++ b/drivers/clk/hisilicon/clk.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -23,14 +24,13 @@ static DEFINE_SPINLOCK(hisi_clk_lock); -struct hisi_clock_data *hisi_clk_alloc(struct platform_device *pdev, - int nr_clks) +struct hisi_clock_data *hisi_clk_alloc(struct platform_device *pdev, int nr_clks) { + struct device *dev = &pdev->dev; struct hisi_clock_data *clk_data; struct resource *res; - struct clk **clk_table; - clk_data = devm_kmalloc(&pdev->dev, sizeof(*clk_data), GFP_KERNEL); + clk_data = devm_kmalloc(dev, sizeof(*clk_data), GFP_KERNEL); if (!clk_data) return NULL; @@ -42,146 +42,125 @@ struct hisi_clock_data *hisi_clk_alloc(struct platform_device *pdev, if (!clk_data->base) return NULL; - clk_table = devm_kmalloc_array(&pdev->dev, nr_clks, - sizeof(*clk_table), - GFP_KERNEL); - if (!clk_table) + clk_data->clk_data = devm_kzalloc(dev, + sizeof(*clk_data->clk_data) + nr_clks * sizeof(clk_data->clk_data->hws[0]), + GFP_KERNEL); + if (!clk_data->clk_data) return NULL; - clk_data->clk_data.clks = clk_table; - clk_data->clk_data.clk_num = nr_clks; + clk_data->clk_data->num = nr_clks; return clk_data; } EXPORT_SYMBOL_GPL(hisi_clk_alloc); -struct hisi_clock_data *hisi_clk_init(struct device_node *np, - int nr_clks) +struct hisi_clock_data *hisi_clk_init(struct device_node *np, int nr_clks) { + struct platform_device *pdev = of_find_device_by_node(np); + struct device *dev = &pdev->dev; struct hisi_clock_data *clk_data; - struct clk **clk_table; void __iomem *base; base = of_iomap(np, 0); if (!base) { pr_err("%s: failed to map clock registers\n", __func__); - goto err; + return NULL; } - clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL); + clk_data = devm_kmalloc(dev, sizeof(*clk_data), GFP_KERNEL); if (!clk_data) - goto err; + return NULL; clk_data->base = base; - clk_table = kcalloc(nr_clks, sizeof(*clk_table), GFP_KERNEL); - if (!clk_table) - goto err_data; + clk_data->clk_data = devm_kzalloc(dev, + sizeof(*clk_data->clk_data) + nr_clks * sizeof(clk_data->clk_data->hws[0]), + GFP_KERNEL); + if (!clk_data->clk_data) + return NULL; - clk_data->clk_data.clks = clk_table; - clk_data->clk_data.clk_num = nr_clks; - of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data->clk_data); + clk_data->clk_data->num = nr_clks; + devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data->clk_data); return clk_data; -err_data: - kfree(clk_data); -err: - return NULL; } EXPORT_SYMBOL_GPL(hisi_clk_init); -int hisi_clk_register_fixed_rate(const struct hisi_fixed_rate_clock *clks, - int nums, struct hisi_clock_data *data) +int hisi_clk_register_fixed_rate(struct device *dev, + const struct hisi_fixed_rate_clock *clks, + int nums, struct hisi_clock_data *data) { - struct clk *clk; + struct clk_hw *clk; int i; for (i = 0; i < nums; i++) { - clk = clk_register_fixed_rate(NULL, clks[i].name, - clks[i].parent_name, - clks[i].flags, - clks[i].fixed_rate); + clk = devm_clk_hw_register_fixed_rate(dev, clks[i].name, + clks[i].parent_name, + clks[i].flags, + clks[i].fixed_rate); if (IS_ERR(clk)) { pr_err("%s: failed to register clock %s\n", __func__, clks[i].name); - goto err; + return PTR_ERR(clk); } - data->clk_data.clks[clks[i].id] = clk; + data->clk_data->hws[clks[i].id] = clk; } return 0; - -err: - while (i--) - clk_unregister_fixed_rate(data->clk_data.clks[clks[i].id]); - - return PTR_ERR(clk); } EXPORT_SYMBOL_GPL(hisi_clk_register_fixed_rate); -int hisi_clk_register_fixed_factor(const struct hisi_fixed_factor_clock *clks, - int nums, - struct hisi_clock_data *data) +int hisi_clk_register_fixed_factor(struct device *dev, + const struct hisi_fixed_factor_clock *clks, + int nums, struct hisi_clock_data *data) { - struct clk *clk; + struct clk_hw *clk; int i; for (i = 0; i < nums; i++) { - clk = clk_register_fixed_factor(NULL, clks[i].name, - clks[i].parent_name, - clks[i].flags, clks[i].mult, - clks[i].div); + clk = devm_clk_hw_register_fixed_factor(dev, clks[i].name, + clks[i].parent_name, + clks[i].flags, clks[i].mult, + clks[i].div); if (IS_ERR(clk)) { pr_err("%s: failed to register clock %s\n", __func__, clks[i].name); - goto err; + return PTR_ERR(clk); } - data->clk_data.clks[clks[i].id] = clk; + data->clk_data->hws[clks[i].id] = clk; } return 0; - -err: - while (i--) - clk_unregister_fixed_factor(data->clk_data.clks[clks[i].id]); - - return PTR_ERR(clk); } EXPORT_SYMBOL_GPL(hisi_clk_register_fixed_factor); -int hisi_clk_register_mux(const struct hisi_mux_clock *clks, - int nums, struct hisi_clock_data *data) +int hisi_clk_register_mux(struct device *dev, + const struct hisi_mux_clock *clks, + int nums, struct hisi_clock_data *data) { - struct clk *clk; + struct clk_hw *clk; void __iomem *base = data->base; int i; for (i = 0; i < nums; i++) { - u32 mask = BIT(clks[i].width) - 1; - - clk = clk_register_mux_table(NULL, clks[i].name, - clks[i].parent_names, - clks[i].num_parents, clks[i].flags, - base + clks[i].offset, clks[i].shift, - mask, clks[i].mux_flags, - clks[i].table, &hisi_clk_lock); + clk = __devm_clk_hw_register_mux(dev, NULL, clks[i].name, + clks[i].num_parents, + clks[i].parent_names, NULL, NULL, + clks[i].flags, + base + clks[i].offset, clks[i].shift, + BIT(clks[i].width) - 1, clks[i].mux_flags, + clks[i].table, &hisi_clk_lock); if (IS_ERR(clk)) { pr_err("%s: failed to register clock %s\n", __func__, clks[i].name); - goto err; + return PTR_ERR(clk); } if (clks[i].alias) - clk_register_clkdev(clk, clks[i].alias, NULL); + clk_hw_register_clkdev(clk, clks[i].alias, NULL); - data->clk_data.clks[clks[i].id] = clk; + data->clk_data->hws[clks[i].id] = clk; } return 0; - -err: - while (i--) - clk_unregister_mux(data->clk_data.clks[clks[i].id]); - - return PTR_ERR(clk); } EXPORT_SYMBOL_GPL(hisi_clk_register_mux); @@ -190,72 +169,68 @@ int hisi_clk_register_phase(struct device *dev, int nums, struct hisi_clock_data *data) { void __iomem *base = data->base; - struct clk *clk; + struct clk_hw *clk; int i; for (i = 0; i < nums; i++) { - clk = clk_register_hisi_phase(dev, &clks[i], base, - &hisi_clk_lock); + clk = devm_clk_hw_register_hisi_phase(dev, &clks[i], base, + &hisi_clk_lock); if (IS_ERR(clk)) { pr_err("%s: failed to register clock %s\n", __func__, clks[i].name); return PTR_ERR(clk); } - data->clk_data.clks[clks[i].id] = clk; + data->clk_data->hws[clks[i].id] = clk; } return 0; } EXPORT_SYMBOL_GPL(hisi_clk_register_phase); -int hisi_clk_register_divider(const struct hisi_divider_clock *clks, - int nums, struct hisi_clock_data *data) +int hisi_clk_register_divider(struct device *dev, + const struct hisi_divider_clock *clks, + int nums, struct hisi_clock_data *data) { - struct clk *clk; + struct clk_hw *clk; void __iomem *base = data->base; int i; for (i = 0; i < nums; i++) { - clk = clk_register_divider_table(NULL, clks[i].name, - clks[i].parent_name, - clks[i].flags, - base + clks[i].offset, - clks[i].shift, clks[i].width, - clks[i].div_flags, - clks[i].table, - &hisi_clk_lock); + clk = devm_clk_hw_register_divider_table(dev, clks[i].name, + clks[i].parent_name, + clks[i].flags, + base + clks[i].offset, + clks[i].shift, clks[i].width, + clks[i].div_flags, + clks[i].table, + &hisi_clk_lock); if (IS_ERR(clk)) { pr_err("%s: failed to register clock %s\n", __func__, clks[i].name); - goto err; + return PTR_ERR(clk); } if (clks[i].alias) - clk_register_clkdev(clk, clks[i].alias, NULL); + clk_hw_register_clkdev(clk, clks[i].alias, NULL); - data->clk_data.clks[clks[i].id] = clk; + data->clk_data->hws[clks[i].id] = clk; } return 0; - -err: - while (i--) - clk_unregister_divider(data->clk_data.clks[clks[i].id]); - - return PTR_ERR(clk); } EXPORT_SYMBOL_GPL(hisi_clk_register_divider); -int hisi_clk_register_gate(const struct hisi_gate_clock *clks, - int nums, struct hisi_clock_data *data) +int hisi_clk_register_gate(struct device *dev, + const struct hisi_gate_clock *clks, + int nums, struct hisi_clock_data *data) { - struct clk *clk; + struct clk_hw *clk; void __iomem *base = data->base; int i; for (i = 0; i < nums; i++) { - clk = clk_register_gate(NULL, clks[i].name, + clk = devm_clk_hw_register_gate(dev, clks[i].name, clks[i].parent_name, clks[i].flags, base + clks[i].offset, @@ -265,34 +240,29 @@ int hisi_clk_register_gate(const struct hisi_gate_clock *clks, if (IS_ERR(clk)) { pr_err("%s: failed to register clock %s\n", __func__, clks[i].name); - goto err; + return PTR_ERR(clk); } if (clks[i].alias) - clk_register_clkdev(clk, clks[i].alias, NULL); + clk_hw_register_clkdev(clk, clks[i].alias, NULL); - data->clk_data.clks[clks[i].id] = clk; + data->clk_data->hws[clks[i].id] = clk; } return 0; - -err: - while (i--) - clk_unregister_gate(data->clk_data.clks[clks[i].id]); - - return PTR_ERR(clk); } EXPORT_SYMBOL_GPL(hisi_clk_register_gate); -void hisi_clk_register_gate_sep(const struct hisi_gate_clock *clks, - int nums, struct hisi_clock_data *data) +int hisi_clk_register_gate_sep(struct device *dev, + const struct hisi_gate_clock *clks, + int nums, struct hisi_clock_data *data) { - struct clk *clk; + struct clk_hw *clk; void __iomem *base = data->base; int i; for (i = 0; i < nums; i++) { - clk = hisi_register_clkgate_sep(NULL, clks[i].name, + clk = hisi_register_clkgate_sep(dev, clks[i].name, clks[i].parent_name, clks[i].flags, base + clks[i].offset, @@ -302,42 +272,47 @@ void hisi_clk_register_gate_sep(const struct hisi_gate_clock *clks, if (IS_ERR(clk)) { pr_err("%s: failed to register clock %s\n", __func__, clks[i].name); - continue; + return PTR_ERR(clk); } if (clks[i].alias) - clk_register_clkdev(clk, clks[i].alias, NULL); + clk_hw_register_clkdev(clk, clks[i].alias, NULL); - data->clk_data.clks[clks[i].id] = clk; + data->clk_data->hws[clks[i].id] = clk; } + + return 0; } EXPORT_SYMBOL_GPL(hisi_clk_register_gate_sep); -void __init hi6220_clk_register_divider(const struct hi6220_divider_clock *clks, - int nums, struct hisi_clock_data *data) +int hi6220_clk_register_divider(struct device *dev, + const struct hi6220_divider_clock *clks, + int nums, struct hisi_clock_data *data) { - struct clk *clk; + struct clk_hw *clk; void __iomem *base = data->base; int i; for (i = 0; i < nums; i++) { - clk = hi6220_register_clkdiv(NULL, clks[i].name, - clks[i].parent_name, - clks[i].flags, - base + clks[i].offset, - clks[i].shift, - clks[i].width, - clks[i].mask_bit, - &hisi_clk_lock); + clk = hi6220_register_clkdiv(dev, clks[i].name, + clks[i].parent_name, + clks[i].flags, + base + clks[i].offset, + clks[i].shift, + clks[i].width, + clks[i].mask_bit, + &hisi_clk_lock); if (IS_ERR(clk)) { pr_err("%s: failed to register clock %s\n", __func__, clks[i].name); - continue; + return PTR_ERR(clk); } if (clks[i].alias) - clk_register_clkdev(clk, clks[i].alias, NULL); + clk_hw_register_clkdev(clk, clks[i].alias, NULL); - data->clk_data.clks[clks[i].id] = clk; + data->clk_data->hws[clks[i].id] = clk; } + + return 0; } diff --git a/drivers/clk/hisilicon/clk.h b/drivers/clk/hisilicon/clk.h index 7a9b42e1b..9df5e9bed 100644 --- a/drivers/clk/hisilicon/clk.h +++ b/drivers/clk/hisilicon/clk.h @@ -19,8 +19,8 @@ struct platform_device; struct hisi_clock_data { - struct clk_onecell_data clk_data; - void __iomem *base; + struct clk_hw_onecell_data *clk_data; + void __iomem *base; }; struct hisi_fixed_rate_clock { @@ -103,55 +103,44 @@ struct hisi_gate_clock { const char *alias; }; -struct clk *hisi_register_clkgate_sep(struct device *, const char *, - const char *, unsigned long, - void __iomem *, u8, - u8, spinlock_t *); -struct clk *hi6220_register_clkdiv(struct device *dev, const char *name, - const char *parent_name, unsigned long flags, void __iomem *reg, - u8 shift, u8 width, u32 mask_bit, spinlock_t *lock); - -struct hisi_clock_data *hisi_clk_alloc(struct platform_device *, int); -struct hisi_clock_data *hisi_clk_init(struct device_node *, int); -int hisi_clk_register_fixed_rate(const struct hisi_fixed_rate_clock *, - int, struct hisi_clock_data *); -int hisi_clk_register_fixed_factor(const struct hisi_fixed_factor_clock *, - int, struct hisi_clock_data *); -int hisi_clk_register_mux(const struct hisi_mux_clock *, int, - struct hisi_clock_data *); -struct clk *clk_register_hisi_phase(struct device *dev, - const struct hisi_phase_clock *clks, - void __iomem *base, spinlock_t *lock); +struct clk_hw *hisi_register_clkgate_sep(struct device *dev, const char *name, + const char *parent_name, + unsigned long flags, + void __iomem *reg, u8 bit_idx, + u8 clk_gate_flags, spinlock_t *lock); +struct clk_hw *hi6220_register_clkdiv(struct device *dev, const char *name, + const char *parent_name, unsigned long flags, + void __iomem *reg, u8 shift, + u8 width, u32 mask_bit, spinlock_t *lock); + +struct hisi_clock_data *hisi_clk_alloc(struct platform_device *pdev, int nr_clks); +struct hisi_clock_data *hisi_clk_init(struct device_node *np, int nr_clks); +int hisi_clk_register_fixed_rate(struct device *dev, + const struct hisi_fixed_rate_clock *clks, + int nums, struct hisi_clock_data *data); +int hisi_clk_register_fixed_factor(struct device *dev, + const struct hisi_fixed_factor_clock *clks, + int nums, struct hisi_clock_data *data); +int hisi_clk_register_mux(struct device *dev, + const struct hisi_mux_clock *clks, int nums, + struct hisi_clock_data *data); +struct clk_hw *devm_clk_hw_register_hisi_phase(struct device *dev, + const struct hisi_phase_clock *clks, + void __iomem *base, spinlock_t *lock); int hisi_clk_register_phase(struct device *dev, - const struct hisi_phase_clock *clks, + const struct hisi_phase_clock *clks, + int nums, struct hisi_clock_data *data); +int hisi_clk_register_divider(struct device *dev, + const struct hisi_divider_clock *clks, + int nums, struct hisi_clock_data *data); +int hisi_clk_register_gate(struct device *dev, + const struct hisi_gate_clock *clks, + int nums, struct hisi_clock_data *data); +int hisi_clk_register_gate_sep(struct device *dev, + const struct hisi_gate_clock *clks, + int nums, struct hisi_clock_data *data); +int hi6220_clk_register_divider(struct device *dev, + const struct hi6220_divider_clock *clks, int nums, struct hisi_clock_data *data); -int hisi_clk_register_divider(const struct hisi_divider_clock *, - int, struct hisi_clock_data *); -int hisi_clk_register_gate(const struct hisi_gate_clock *, - int, struct hisi_clock_data *); -void hisi_clk_register_gate_sep(const struct hisi_gate_clock *, - int, struct hisi_clock_data *); -void hi6220_clk_register_divider(const struct hi6220_divider_clock *, - int, struct hisi_clock_data *); - -#define hisi_clk_unregister(type) \ -static inline \ -void hisi_clk_unregister_##type(const struct hisi_##type##_clock *clks, \ - int nums, struct hisi_clock_data *data) \ -{ \ - struct clk **clocks = data->clk_data.clks; \ - int i; \ - for (i = 0; i < nums; i++) { \ - int id = clks[i].id; \ - if (clocks[id]) \ - clk_unregister_##type(clocks[id]); \ - } \ -} - -hisi_clk_unregister(fixed_rate) -hisi_clk_unregister(fixed_factor) -hisi_clk_unregister(mux) -hisi_clk_unregister(divider) -hisi_clk_unregister(gate) #endif /* __HISI_CLK_H */ diff --git a/drivers/clk/hisilicon/clkdivider-hi6220.c b/drivers/clk/hisilicon/clkdivider-hi6220.c index 5348bafe6..a8f1b3e51 100644 --- a/drivers/clk/hisilicon/clkdivider-hi6220.c +++ b/drivers/clk/hisilicon/clkdivider-hi6220.c @@ -7,9 +7,9 @@ * Author: Bintian Wang */ +#include #include #include -#include #include #include #include @@ -97,19 +97,20 @@ static const struct clk_ops hi6220_clkdiv_ops = { .set_rate = hi6220_clkdiv_set_rate, }; -struct clk *hi6220_register_clkdiv(struct device *dev, const char *name, +struct clk_hw *hi6220_register_clkdiv(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width, u32 mask_bit, spinlock_t *lock) { struct hi6220_clk_divider *div; - struct clk *clk; + struct clk_hw *clk; struct clk_init_data init; struct clk_div_table *table; u32 max_div, min_div; int i; + int ret; /* allocate the divider */ - div = kzalloc(sizeof(*div), GFP_KERNEL); + div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL); if (!div) return ERR_PTR(-ENOMEM); @@ -117,11 +118,9 @@ struct clk *hi6220_register_clkdiv(struct device *dev, const char *name, max_div = div_mask(width) + 1; min_div = 1; - table = kcalloc(max_div + 1, sizeof(*table), GFP_KERNEL); - if (!table) { - kfree(div); + table = devm_kcalloc(dev, max_div + 1, sizeof(*table), GFP_KERNEL); + if (!table) return ERR_PTR(-ENOMEM); - } for (i = 0; i < max_div; i++) { table[i].div = min_div + i; @@ -144,11 +143,9 @@ struct clk *hi6220_register_clkdiv(struct device *dev, const char *name, div->table = table; /* register the clock */ - clk = clk_register(dev, &div->hw); - if (IS_ERR(clk)) { - kfree(table); - kfree(div); - } + ret = devm_clk_hw_register(dev, &div->hw); + if (ret) + return ERR_PTR(ret); return clk; } diff --git a/drivers/clk/hisilicon/clkgate-separated.c b/drivers/clk/hisilicon/clkgate-separated.c index 90d858522..04bc73925 100644 --- a/drivers/clk/hisilicon/clkgate-separated.c +++ b/drivers/clk/hisilicon/clkgate-separated.c @@ -9,10 +9,10 @@ * Xin Li */ +#include #include #include #include -#include #include "clk.h" @@ -80,17 +80,18 @@ static const struct clk_ops clkgate_separated_ops = { .is_enabled = clkgate_separated_is_enabled, }; -struct clk *hisi_register_clkgate_sep(struct device *dev, const char *name, +struct clk_hw *hisi_register_clkgate_sep(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 bit_idx, u8 clk_gate_flags, spinlock_t *lock) { struct clkgate_separated *sclk; - struct clk *clk; + struct clk_hw *clk; struct clk_init_data init; + int ret; - sclk = kzalloc(sizeof(*sclk), GFP_KERNEL); + sclk = devm_kzalloc(dev, sizeof(*sclk), GFP_KERNEL); if (!sclk) return ERR_PTR(-ENOMEM); @@ -106,8 +107,9 @@ struct clk *hisi_register_clkgate_sep(struct device *dev, const char *name, sclk->hw.init = &init; sclk->lock = lock; - clk = clk_register(dev, &sclk->hw); - if (IS_ERR(clk)) - kfree(sclk); + ret = devm_clk_hw_register(dev, &sclk->hw); + if (ret) + return ERR_PTR(ret); + return clk; } diff --git a/drivers/clk/hisilicon/crg-hi3516cv300.c b/drivers/clk/hisilicon/crg-hi3516cv300.c index 5d4e61c7a..5f56fb3e5 100644 --- a/drivers/clk/hisilicon/crg-hi3516cv300.c +++ b/drivers/clk/hisilicon/crg-hi3516cv300.c @@ -129,6 +129,7 @@ static const struct hisi_gate_clock hi3516cv300_gate_clks[] = { static struct hisi_clock_data *hi3516cv300_clk_register( struct platform_device *pdev) { + struct device *dev = &pdev->dev; struct hisi_clock_data *clk_data; int ret; @@ -136,52 +137,31 @@ static struct hisi_clock_data *hi3516cv300_clk_register( if (!clk_data) return ERR_PTR(-ENOMEM); - ret = hisi_clk_register_fixed_rate(hi3516cv300_fixed_rate_clks, + ret = hisi_clk_register_fixed_rate(dev, hi3516cv300_fixed_rate_clks, ARRAY_SIZE(hi3516cv300_fixed_rate_clks), clk_data); if (ret) return ERR_PTR(ret); - ret = hisi_clk_register_mux(hi3516cv300_mux_clks, + ret = hisi_clk_register_mux(dev, hi3516cv300_mux_clks, ARRAY_SIZE(hi3516cv300_mux_clks), clk_data); if (ret) - goto unregister_fixed_rate; + return ERR_PTR(ret); - ret = hisi_clk_register_gate(hi3516cv300_gate_clks, + ret = hisi_clk_register_gate(dev, hi3516cv300_gate_clks, ARRAY_SIZE(hi3516cv300_gate_clks), clk_data); if (ret) - goto unregister_mux; + return ERR_PTR(ret); - ret = of_clk_add_provider(pdev->dev.of_node, - of_clk_src_onecell_get, &clk_data->clk_data); + ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, + clk_data->clk_data); if (ret) - goto unregister_gate; + return ERR_PTR(ret); return clk_data; - -unregister_gate: - hisi_clk_unregister_gate(hi3516cv300_gate_clks, - ARRAY_SIZE(hi3516cv300_gate_clks), clk_data); -unregister_mux: - hisi_clk_unregister_mux(hi3516cv300_mux_clks, - ARRAY_SIZE(hi3516cv300_mux_clks), clk_data); -unregister_fixed_rate: - hisi_clk_unregister_fixed_rate(hi3516cv300_fixed_rate_clks, - ARRAY_SIZE(hi3516cv300_fixed_rate_clks), clk_data); - return ERR_PTR(ret); } static void hi3516cv300_clk_unregister(struct platform_device *pdev) { - struct hisi_crg_dev *crg = platform_get_drvdata(pdev); - - of_clk_del_provider(pdev->dev.of_node); - - hisi_clk_unregister_gate(hi3516cv300_gate_clks, - ARRAY_SIZE(hi3516cv300_gate_clks), crg->clk_data); - hisi_clk_unregister_mux(hi3516cv300_mux_clks, - ARRAY_SIZE(hi3516cv300_mux_clks), crg->clk_data); - hisi_clk_unregister_fixed_rate(hi3516cv300_fixed_rate_clks, - ARRAY_SIZE(hi3516cv300_fixed_rate_clks), crg->clk_data); } static const struct hisi_crg_funcs hi3516cv300_crg_funcs = { @@ -203,6 +183,7 @@ static const struct hisi_mux_clock hi3516cv300_sysctrl_mux_clks[] = { static struct hisi_clock_data *hi3516cv300_sysctrl_clk_register( struct platform_device *pdev) { + struct device *dev = &pdev->dev; struct hisi_clock_data *clk_data; int ret; @@ -210,34 +191,21 @@ static struct hisi_clock_data *hi3516cv300_sysctrl_clk_register( if (!clk_data) return ERR_PTR(-ENOMEM); - ret = hisi_clk_register_mux(hi3516cv300_sysctrl_mux_clks, + ret = hisi_clk_register_mux(dev, hi3516cv300_sysctrl_mux_clks, ARRAY_SIZE(hi3516cv300_sysctrl_mux_clks), clk_data); if (ret) return ERR_PTR(ret); - - ret = of_clk_add_provider(pdev->dev.of_node, - of_clk_src_onecell_get, &clk_data->clk_data); + ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, + &clk_data->clk_data); if (ret) - goto unregister_mux; + return ERR_PTR(ret); return clk_data; - -unregister_mux: - hisi_clk_unregister_mux(hi3516cv300_sysctrl_mux_clks, - ARRAY_SIZE(hi3516cv300_sysctrl_mux_clks), clk_data); - return ERR_PTR(ret); } static void hi3516cv300_sysctrl_clk_unregister(struct platform_device *pdev) { - struct hisi_crg_dev *crg = platform_get_drvdata(pdev); - - of_clk_del_provider(pdev->dev.of_node); - - hisi_clk_unregister_mux(hi3516cv300_sysctrl_mux_clks, - ARRAY_SIZE(hi3516cv300_sysctrl_mux_clks), - crg->clk_data); } static const struct hisi_crg_funcs hi3516cv300_sysctrl_funcs = { diff --git a/drivers/clk/hisilicon/crg-hi3798.c b/drivers/clk/hisilicon/crg-hi3798.c index 778637131..d05151d0e 100644 --- a/drivers/clk/hisilicon/crg-hi3798.c +++ b/drivers/clk/hisilicon/crg-hi3798.c @@ -72,6 +72,7 @@ static struct hisi_clock_data * hi3798_clk_register(struct platform_device *pdev, const struct hi3798_clks *clks) { + struct device *dev = &pdev->dev; struct hisi_clock_data *clk_data; int ret; @@ -80,55 +81,36 @@ hi3798_clk_register(struct platform_device *pdev, return ERR_PTR(-ENOMEM); /* hisi_phase_clock is resource managed */ - ret = hisi_clk_register_phase(&pdev->dev, clks->phase_clks, + ret = hisi_clk_register_phase(dev, clks->phase_clks, clks->phase_clks_nums, clk_data); if (ret) return ERR_PTR(ret); - ret = hisi_clk_register_fixed_rate(hi3798_fixed_rate_clks, + ret = hisi_clk_register_fixed_rate(dev, hi3798_fixed_rate_clks, ARRAY_SIZE(hi3798_fixed_rate_clks), clk_data); if (ret) return ERR_PTR(ret); - ret = hisi_clk_register_mux(clks->mux_clks, clks->mux_clks_nums, clk_data); + ret = hisi_clk_register_mux(dev, clks->mux_clks, clks->mux_clks_nums, clk_data); if (ret) - goto unregister_fixed_rate; + return ERR_PTR(ret); - ret = hisi_clk_register_gate(clks->gate_clks, clks->gate_clks_nums, clk_data); + ret = hisi_clk_register_gate(dev, clks->gate_clks, clks->gate_clks_nums, clk_data); if (ret) - goto unregister_mux; + return ERR_PTR(ret); - ret = of_clk_add_provider(pdev->dev.of_node, - of_clk_src_onecell_get, &clk_data->clk_data); + ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, + clk_data->clk_data); if (ret) - goto unregister_gate; + return ERR_PTR(ret); return clk_data; - -unregister_gate: - hisi_clk_unregister_gate(clks->gate_clks, clks->gate_clks_nums, clk_data); -unregister_mux: - hisi_clk_unregister_mux(clks->mux_clks, clks->mux_clks_nums, clk_data); -unregister_fixed_rate: - hisi_clk_unregister_fixed_rate(hi3798_fixed_rate_clks, - ARRAY_SIZE(hi3798_fixed_rate_clks), - clk_data); - return ERR_PTR(ret); } static void hi3798_clk_unregister(struct platform_device *pdev, const struct hi3798_clks *clks) { - struct hisi_crg_dev *crg = platform_get_drvdata(pdev); - - of_clk_del_provider(pdev->dev.of_node); - - hisi_clk_unregister_gate(clks->gate_clks, clks->gate_clks_nums, crg->clk_data); - hisi_clk_unregister_mux(clks->mux_clks, clks->mux_clks_nums, crg->clk_data); - hisi_clk_unregister_fixed_rate(hi3798_fixed_rate_clks, - ARRAY_SIZE(hi3798_fixed_rate_clks), - crg->clk_data); } /* hi3798 sysctrl CRG */ @@ -139,6 +121,7 @@ static struct hisi_clock_data * hi3798_sysctrl_clk_register(struct platform_device *pdev, const struct hi3798_clks *clks) { + struct device *dev = &pdev->dev; struct hisi_clock_data *clk_data; int ret; @@ -146,30 +129,21 @@ hi3798_sysctrl_clk_register(struct platform_device *pdev, if (!clk_data) return ERR_PTR(-ENOMEM); - ret = hisi_clk_register_gate(clks->gate_clks, clks->gate_clks_nums, clk_data); + ret = hisi_clk_register_gate(dev, clks->gate_clks, clks->gate_clks_nums, clk_data); if (ret) return ERR_PTR(ret); - ret = of_clk_add_provider(pdev->dev.of_node, - of_clk_src_onecell_get, &clk_data->clk_data); + ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, + clk_data->clk_data); if (ret) - goto unregister_gate; + return ERR_PTR(ret); return clk_data; - -unregister_gate: - hisi_clk_unregister_gate(clks->gate_clks, clks->gate_clks_nums, clk_data); - return ERR_PTR(ret); } static void hi3798_sysctrl_clk_unregister(struct platform_device *pdev, const struct hi3798_clks *clks) { - struct hisi_crg_dev *crg = platform_get_drvdata(pdev); - - of_clk_del_provider(pdev->dev.of_node); - - hisi_clk_unregister_gate(clks->gate_clks, clks->gate_clks_nums, crg->clk_data); } /* hi3798CV200 */ From patchwork Tue Mar 21 20:00:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yangfl X-Patchwork-Id: 73042 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:604a:0:0:0:0:0 with SMTP id j10csp1987543wrt; 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Signed-off-by: David Yang --- drivers/clk/hisilicon/crg-hi3798.c | 126 +++++++++++++++++++++++++++++ 1 file changed, 126 insertions(+) diff --git a/drivers/clk/hisilicon/crg-hi3798.c b/drivers/clk/hisilicon/crg-hi3798.c index d05151d0e..78915bd26 100644 --- a/drivers/clk/hisilicon/crg-hi3798.c +++ b/drivers/clk/hisilicon/crg-hi3798.c @@ -7,9 +7,13 @@ #include #include +#include +#include +#include #include #include #include +#include #include "clk.h" #include "crg.h" #include "reset.h" @@ -59,6 +63,121 @@ static const struct hisi_fixed_rate_clock hi3798_fixed_rate_clks[] = { { HI3798_FIXED_250M, "250m", NULL, 0, 250000000, }, }; +struct hi3798_complex_clock { + unsigned int id; + const char *name; + const char *parent_name; + unsigned long flags; + unsigned long offset; + u32 mask; + u32 value; + const char *alias; +}; + +struct hi3798_clk_complex { + struct clk_hw hw; + void __iomem *reg; + u32 mask; + u32 value; +}; + +#define to_complex_clk(_hw) container_of(_hw, struct hi3798_clk_complex, hw) + +static int hi3798_clk_complex_prepare(struct clk_hw *hw) +{ + struct hi3798_clk_complex *clk = to_complex_clk(hw); + u32 val; + + val = readl_relaxed(clk->reg); + val &= ~(clk->mask); + val |= clk->value; + writel_relaxed(val, clk->reg); + + return 0; +} + +static void hi3798_clk_complex_unprepare(struct clk_hw *hw) +{ + struct hi3798_clk_complex *clk = to_complex_clk(hw); + u32 val; + + val = readl_relaxed(clk->reg); + val &= ~(clk->mask); + writel_relaxed(val, clk->reg); +} + +static int hi3798_clk_complex_is_prepared(struct clk_hw *hw) +{ + struct hi3798_clk_complex *clk = to_complex_clk(hw); + u32 val; + + val = readl_relaxed(clk->reg); + return (val & clk->mask) == clk->value; +} + +static const struct clk_ops hi3798_clk_complex_ops = { + .prepare = hi3798_clk_complex_prepare, + .unprepare = hi3798_clk_complex_unprepare, + .is_prepared = hi3798_clk_complex_is_prepared, +}; + +static int hi3798_clk_register_complex(struct device *dev, + const struct hi3798_complex_clock *clks, int nums, + struct hisi_clock_data *data) +{ + void __iomem *base = data->base; + int i; + int ret; + + for (i = 0; i < nums; i++) { + struct hi3798_clk_complex *p_clk; + struct clk_init_data init; + + p_clk = devm_kzalloc(dev, sizeof(*p_clk), GFP_KERNEL); + if (!p_clk) + return -ENOMEM; + + init.name = clks[i].name; + init.ops = &hi3798_clk_complex_ops; + + init.flags = 0; + init.parent_names = + (clks[i].parent_name ? &clks[i].parent_name : NULL); + init.num_parents = (clks[i].parent_name ? 1 : 0); + + p_clk->reg = base + clks[i].offset; + p_clk->mask = clks[i].mask; + p_clk->value = clks[i].value; + p_clk->hw.init = &init; + + ret = devm_clk_hw_register(dev, &p_clk->hw); + if (ret) { + pr_err("%s: failed to register clock %s\n", + __func__, clks[i].name); + return ret; + } + + if (clks[i].alias) + clk_register_clkdev(clk, clks[i].alias, NULL); + + data->clk_data->hws[clks[i].id] = &p_clk->hw; + } + + return 0; +} + +static void hi3798_clk_unregister_complex(const struct hi3798_complex_clock *clks, int nums, + struct hisi_clock_data *data) +{ + struct clk **clocks = data->clk_data.clks; + int i; + + for (i = 0; i < nums; i++) { + if (clocks[clks[i].id]) + clk_unregister(clocks[clks[i].id]); + } +} + struct hi3798_clks { const struct hisi_gate_clock *gate_clks; int gate_clks_nums; @@ -66,6 +185,8 @@ struct hi3798_clks { int mux_clks_nums; const struct hisi_phase_clock *phase_clks; int phase_clks_nums; + const struct hi3798_complex_clock *complex_clks; + int complex_clks_nums; }; static struct hisi_clock_data * @@ -100,6 +221,11 @@ hi3798_clk_register(struct platform_device *pdev, if (ret) return ERR_PTR(ret); + ret = hi3798_clk_register_complex(dev, clks->complex_clks, + clks->complex_clks_nums, clk_data); + if (ret) + return ERR_PTR(ret); + ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data->clk_data); if (ret) From patchwork Tue Mar 21 20:00:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yangfl X-Patchwork-Id: 73040 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:604a:0:0:0:0:0 with SMTP id j10csp1987125wrt; Tue, 21 Mar 2023 13:13:11 -0700 (PDT) X-Google-Smtp-Source: AK7set9dWnCQcRlVlkqQftA2BJfaK1o2Q7oVLDUBhW5TG6gf5yAMWfFJ7CQSGB5VbfOPY1rcfCKF X-Received: by 2002:a05:6a00:4c10:b0:594:1f1c:3d3a with SMTP id ea16-20020a056a004c1000b005941f1c3d3amr968387pfb.15.1679429591251; Tue, 21 Mar 2023 13:13:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1679429591; cv=none; d=google.com; s=arc-20160816; b=wNvXFy5F2FCeNUYxWkNADwOgPCFM0MW7BnBuEMAdl+dm/3kJOpPTXsaPQ0YXD9FQ5K ozlR1dq4nAb//G6gFuhyDAdSZkBD9cwpdo349Q0RKacGB0fyKxUipBCsg48d1z9zQdPI AAIhD9oyAcYufLjUs7U+rwSZQK/HRr5xMpXyqpm/dh0GLm3u88f95IMU50LEHFT2DpOk xj6d9Sz33DMF03nYljt8QLG/HDC/TijjvFG0lCc9cFkHdSgmytq0Yf7AoeY/Aw4Xk4vi h7PDOh7WCX+ypueZaEL4BwuXbUFLGul86RWB/wLnj4NojVAdGEkNDmQEbmvHHh5rx31B bs/g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:to:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:from :dkim-signature; bh=P1nihvRARKpi6tkVd5cEgKMlSNEP4XWbbAUmPmevZWQ=; b=S9lfqdPjmgOxT8I6csm3RKV+IFmG6cM6H1+ENiJ4qQWBP9OiKgDbXFW82YZY494oEO dlpgsqesSOwH/jrRTjGaIEYKucEhf3w5hV/VBvgF8CJ4O99E5Bx24QhI5SzRpz5Ce03s +xJ2awZrKRdOskH0HJDrB2FEE1uORkVj6negiwLSQb1XdhGegjIhBprWbqzvGgv3kQ82 1MP5wJSr2djxv34apkN0F5oYM5CRCFRsKWpXZZ2NM+gD4BUAmcg3br2ZNdZqWqpC3Fm/ bGtRGR5SKq45m/4WsEcjWwlQSaC3nXfPz2VsubcG6YTejAad6BEGz+C9WaZxo0Gip0NS KHuA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20210112 header.b=CjACuUfh; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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CRG (Clock and Reset Generator) module generates clock and reset signals used by other module blocks on SoC. Signed-off-by: David Yang Acked-by: Krzysztof Kozlowski --- .../devicetree/bindings/clock/hisi-crg.txt | 2 ++ include/dt-bindings/clock/histb-clock.h | 13 +++++++++++++ 2 files changed, 15 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/hisi-crg.txt b/Documentation/devicetree/bindings/clock/hisi-crg.txt index cc60b3d42..972c038c8 100644 --- a/Documentation/devicetree/bindings/clock/hisi-crg.txt +++ b/Documentation/devicetree/bindings/clock/hisi-crg.txt @@ -13,6 +13,8 @@ Required Properties: - "hisilicon,hi3516cv300-crg" - "hisilicon,hi3516cv300-sysctrl" - "hisilicon,hi3519-crg" + - "hisilicon,hi3798mv100-crg" + - "hisilicon,hi3798mv100-sysctrl" - "hisilicon,hi3798cv200-crg" - "hisilicon,hi3798cv200-sysctrl" diff --git a/include/dt-bindings/clock/histb-clock.h b/include/dt-bindings/clock/histb-clock.h index e64e5770a..126b1f839 100644 --- a/include/dt-bindings/clock/histb-clock.h +++ b/include/dt-bindings/clock/histb-clock.h @@ -58,6 +58,19 @@ #define HISTB_USB3_UTMI_CLK1 48 #define HISTB_USB3_PIPE_CLK1 49 #define HISTB_USB3_SUSPEND_CLK1 50 +#define HISTB_USB2_UTMI_CLK1 51 +#define HISTB_USB2_2_BUS_CLK 52 +#define HISTB_USB2_2_PHY_CLK 53 +#define HISTB_USB2_2_UTMI_CLK 54 +#define HISTB_USB2_2_UTMI_CLK1 55 +#define HISTB_USB2_2_12M_CLK 56 +#define HISTB_USB2_2_48M_CLK 57 +#define HISTB_USB2_2_OTG_UTMI_CLK 58 +#define HISTB_USB2_2_PHY1_REF_CLK 59 +#define HISTB_USB2_2_PHY2_REF_CLK 60 +#define HISTB_FEPHY_CLK 61 +#define HISTB_GPU_BUS_CLK 62 +#define HISTB_GPU_CORE_CLK 63 /* clocks provided by mcu CRG */ #define HISTB_MCE_CLK 1 From patchwork Tue Mar 21 20:00:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yangfl X-Patchwork-Id: 73039 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:604a:0:0:0:0:0 with SMTP id j10csp1987046wrt; Tue, 21 Mar 2023 13:12:57 -0700 (PDT) X-Google-Smtp-Source: AK7set9fMYoZFXpQiG+Zs5Jqp9QUjxdYRyN0QxSseb8hQicMilIEmbLuW/6jFDkGUnBNsq+5+Gsv X-Received: by 2002:a17:902:e0d4:b0:19e:6c02:801c with SMTP id e20-20020a170902e0d400b0019e6c02801cmr302371pla.14.1679429577336; Tue, 21 Mar 2023 13:12:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1679429577; cv=none; d=google.com; s=arc-20160816; b=l94v4K0FdQJ4bd1ILNXA/T75UjB70Nc/bVeNIkZJwdIdwJTD9R2zMoe7dkFq7st+1Q YZCutuUptnF2BVFrad+97863q+1arl14BzRJZour2ZLZ8zQOW8KQriOq2ed4p366FHdz wGTrc06n8Zu6C/GVALOYUBvyMajwUXj7ToRmDLVsNctnw4V9kB9lTAsfehlUDEaDvnBM qH7oyilwY3zAi1uWwK+9XNbTQ5o/X/yykdebzeLJVTp4/L3zZ/3hml6QyELU73klTCIG cav49vaN7qdEPQe5Dl3W9hixgKmewL7hrnl/UizLvklK1ET2zjrql0clY3ZGTF5xMDAQ it5g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:to:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:from :dkim-signature; bh=8phvAVZ6WLP5gFAw+M761A2GnXN7k1pWxMfd/tGnvds=; b=m+ueZciO5dn1IGGDbwYwb04lbA3f4Ac8Tjfh0QkNTP50Ow67XqlJJlaaFqdPPtC5P+ zhLaCf3YbP2gGRyrzz0cOTu+275KKi4GURxxkvoq8wgkSyZJN7I7iI/4R6BbQ+WFEfXl +YcddzboLyNcvt1/yR95sQIsmgarttZoo3df67QcuUo1OMz6/qJfbLzAXG2eGKsq2+8B Xs4ywg33pt+hOTq2awZXfENOI5iwWLslJWwS2ksl9Ak2fHmZKellqx8caHytuc3gxfni NjPpb5kZVBNrVnnYvfwbouXV8X7LQZafKRpfpQLlsoygjndjuoBEKhB+NGOtgoIeaokL VyrQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20210112 header.b=PZJRTsm9; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id v10-20020a170902b7ca00b0019b0b007981si13233071plz.531.2023.03.21.13.12.44; Tue, 21 Mar 2023 13:12:57 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=fail header.i=@gmail.com header.s=20210112 header.b=PZJRTsm9; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230083AbjCUUCW (ORCPT + 99 others); Tue, 21 Mar 2023 16:02:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37990 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230044AbjCUUCU (ORCPT ); Tue, 21 Mar 2023 16:02:20 -0400 Received: from mail-pl1-x636.google.com (mail-pl1-x636.google.com [IPv6:2607:f8b0:4864:20::636]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 098DA53712; Tue, 21 Mar 2023 13:01:48 -0700 (PDT) Received: by mail-pl1-x636.google.com with SMTP id o11so17261204ple.1; Tue, 21 Mar 2023 13:01:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1679428902; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8phvAVZ6WLP5gFAw+M761A2GnXN7k1pWxMfd/tGnvds=; b=PZJRTsm92ozFzAei+hay/FfSkwTCCSAUQJBsS9oQEhNAxtuJZ9LBeSC+u+HyKsd13g qIEPmTZpqYJ4Mq8HOwCIOK8thNiHQ7W9oRq8KokcB9OH5uWUZvQ3KGL/Txay9KNCjP3N y3MOKRhL5sVLPz0n3G/kF4xAZFtvmtQTU4/OSID0bMCyncxevwpa+hDFZ7Iatm+KmhoV oCp23FElAmgoBDEUCgzbqhOV9HVClM9mRV3CnReTbKaU3Y11BnXKxumQJ63yxXXh4jsl cQWMzvNesLWu5lXT9rqB4fBNjLeddcJItrQ2fmFtJKeGarZjkxLcZFYu1jifk6pMR+ib Byvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679428902; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8phvAVZ6WLP5gFAw+M761A2GnXN7k1pWxMfd/tGnvds=; b=JhivQo7YwqOyYLsDKU6Wms7/6qGJbnTXG+fcxnOoHtivt/pkYgonrvzfs23R4K1sdM fL+Zme9dzZ0VUObAOmuSQ8p/mqALRSj08aCKZgzx8eFVnVS0eiSFP54peAUkdnps+2sr W1BIzZNyi9DzXXRUerRqjpCzQ8X3cFgOsZZ5EMtTA/HZ8BJnIFJD6KHcRN5j30gX/LdF R2V/9S8NB/K4wS48ufGNlG/MjVS8wP760Kvg4969tbrdoLLV4ROD0JHi2OfUV53V+H7F GSqUU431VndFtx75lbVsVEX30fF/18d9WBFJg5xTFa/1/c/ANowtg/wLg2bTTy7jYxeZ CV8Q== X-Gm-Message-State: AO0yUKWVn/FQ7G0Y97Nod/fjZTO0Wn34GlNom4yzj6C2c7elDf+pk2t3 jtnE5l3T8EknAIo2QFyU88U= X-Received: by 2002:a17:90b:38cf:b0:23d:2027:c355 with SMTP id nn15-20020a17090b38cf00b0023d2027c355mr1122058pjb.10.1679428902504; Tue, 21 Mar 2023 13:01:42 -0700 (PDT) Received: from d.home.yangfl.dn42 ([104.28.245.199]) by smtp.gmail.com with ESMTPSA id mt19-20020a17090b231300b0023b5528b8d4sm930557pjb.19.2023.03.21.13.01.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Mar 2023 13:01:42 -0700 (PDT) From: David Yang Cc: David Yang , Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 6/6] clk: hisilicon: Add CRG driver for Hi3798MV100 SoC Date: Wed, 22 Mar 2023 04:00:27 +0800 Message-Id: <20230321200031.1812026-7-mmyangfl@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230321200031.1812026-1-mmyangfl@gmail.com> References: <20230321200031.1812026-1-mmyangfl@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761009548828750598?= X-GMAIL-MSGID: =?utf-8?q?1761009548828750598?= Add CRG driver for Hi3798MV100 SoC. CRG (Clock and Reset Generator) module generates clock and reset signals used by other module blocks on SoC. Signed-off-by: David Yang --- drivers/clk/hisilicon/crg-hi3798.c | 191 ++++++++++++++++++++++++++--- 1 file changed, 175 insertions(+), 16 deletions(-) diff --git a/drivers/clk/hisilicon/crg-hi3798.c b/drivers/clk/hisilicon/crg-hi3798.c index 78915bd26..34f92f492 100644 --- a/drivers/clk/hisilicon/crg-hi3798.c +++ b/drivers/clk/hisilicon/crg-hi3798.c @@ -42,6 +42,9 @@ #define HI3798_FIXED_166P5M 84 #define HI3798_SDIO0_MUX 85 #define HI3798_COMBPHY0_MUX 86 +#define HI3798_FIXED_3M 87 +#define HI3798_FIXED_15M 88 +#define HI3798_FIXED_83P3M 89 #define HI3798_CRG_NR_CLKS 128 @@ -49,13 +52,16 @@ static const struct hisi_fixed_rate_clock hi3798_fixed_rate_clks[] = { { HISTB_OSC_CLK, "clk_osc", NULL, 0, 24000000, }, { HISTB_APB_CLK, "clk_apb", NULL, 0, 100000000, }, { HISTB_AHB_CLK, "clk_ahb", NULL, 0, 200000000, }, + { HI3798_FIXED_3M, "3m", NULL, 0, 3000000, }, { HI3798_FIXED_12M, "12m", NULL, 0, 12000000, }, + { HI3798_FIXED_15M, "15m", NULL, 0, 15000000, }, { HI3798_FIXED_24M, "24m", NULL, 0, 24000000, }, { HI3798_FIXED_25M, "25m", NULL, 0, 25000000, }, { HI3798_FIXED_48M, "48m", NULL, 0, 48000000, }, { HI3798_FIXED_50M, "50m", NULL, 0, 50000000, }, { HI3798_FIXED_60M, "60m", NULL, 0, 60000000, }, { HI3798_FIXED_75M, "75m", NULL, 0, 75000000, }, + { HI3798_FIXED_83P3M, "83p3m", NULL, 0, 83333333, }, { HI3798_FIXED_100M, "100m", NULL, 0, 100000000, }, { HI3798_FIXED_150M, "150m", NULL, 0, 150000000, }, { HI3798_FIXED_166P5M, "166p5m", NULL, 0, 165000000, }, @@ -71,7 +77,6 @@ struct hi3798_complex_clock { unsigned long offset; u32 mask; u32 value; - const char *alias; }; struct hi3798_clk_complex { @@ -157,27 +162,12 @@ static int hi3798_clk_register_complex(struct device *dev, return ret; } - if (clks[i].alias) - clk_register_clkdev(clk, clks[i].alias, NULL); - data->clk_data->hws[clks[i].id] = &p_clk->hw; } return 0; } -static void hi3798_clk_unregister_complex(const struct hi3798_complex_clock *clks, int nums, - struct hisi_clock_data *data) -{ - struct clk **clocks = data->clk_data.clks; - int i; - - for (i = 0; i < nums; i++) { - if (clocks[clks[i].id]) - clk_unregister(clocks[clks[i].id]); - } -} - struct hi3798_clks { const struct hisi_gate_clock *gate_clks; int gate_clks_nums; @@ -464,11 +454,180 @@ static const struct hisi_crg_funcs hi3798cv200_sysctrl_funcs = { .unregister_clks = hi3798cv200_sysctrl_clk_unregister, }; +/* hi3798MV100 */ + +static const char *const hi3798mv100_mmc_mux_p[] = { + "75m", "100m", "50m", "15m" }; +static u32 hi3798mv100_mmc_mux_table[] = {0, 1, 2, 3}; + +static struct hisi_mux_clock hi3798mv100_mux_clks[] = { + { HI3798_MMC_MUX, "mmc_mux", hi3798mv100_mmc_mux_p, + ARRAY_SIZE(hi3798mv100_mmc_mux_p), CLK_SET_RATE_PARENT, + 0xa0, 8, 2, 0, hi3798mv100_mmc_mux_table, }, + { HI3798_SDIO0_MUX, "sdio0_mux", hi3798mv100_mmc_mux_p, + ARRAY_SIZE(hi3798mv100_mmc_mux_p), CLK_SET_RATE_PARENT, + 0x9c, 8, 2, 0, hi3798mv100_mmc_mux_table, }, +}; + +static const struct hisi_gate_clock hi3798mv100_gate_clks[] = { + /* NAND */ + /* hi3798MV100 NAND driver does not get into mainline yet, + * expose these clocks when it gets ready */ + /* { HISTB_NAND_CLK, "clk_nand", "clk_apb", + CLK_SET_RATE_PARENT, 0x60, 0, 0, }, */ + /* UART */ + { HISTB_UART1_CLK, "clk_uart1", "3m", + CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0x68, 0, 0, }, + { HISTB_UART2_CLK, "clk_uart2", "83p3m", + CLK_SET_RATE_PARENT, 0x68, 4, 0, }, + /* I2C */ + { HISTB_I2C0_CLK, "clk_i2c0", "clk_apb", + CLK_SET_RATE_PARENT, 0x6C, 4, 0, }, + { HISTB_I2C1_CLK, "clk_i2c1", "clk_apb", + CLK_SET_RATE_PARENT, 0x6C, 8, 0, }, + { HISTB_I2C2_CLK, "clk_i2c2", "clk_apb", + CLK_SET_RATE_PARENT, 0x6C, 12, 0, }, + /* SPI */ + { HISTB_SPI0_CLK, "clk_spi0", "clk_apb", + CLK_SET_RATE_PARENT, 0x70, 0, 0, }, + /* SDIO */ + { HISTB_SDIO0_BIU_CLK, "clk_sdio0_biu", "200m", + CLK_SET_RATE_PARENT, 0x9c, 0, 0, }, + { HISTB_SDIO0_CIU_CLK, "clk_sdio0_ciu", "sdio0_mux", + CLK_SET_RATE_PARENT, 0x9c, 1, 0, }, + /* EMMC */ + { HISTB_MMC_BIU_CLK, "clk_mmc_biu", "200m", + CLK_SET_RATE_PARENT, 0xa0, 0, 0, }, + { HISTB_MMC_CIU_CLK, "clk_mmc_ciu", "mmc_mux", + CLK_SET_RATE_PARENT, 0xa0, 1, 0, }, + /* USB2 */ + { HISTB_USB2_BUS_CLK, "clk_u2_bus", "clk_ahb", + CLK_SET_RATE_PARENT, 0xb8, 0, 0, }, + { HISTB_USB2_PHY_CLK, "clk_u2_phy", "60m", + CLK_SET_RATE_PARENT, 0xb8, 4, 0, }, + { HISTB_USB2_12M_CLK, "clk_u2_12m", "12m", + CLK_SET_RATE_PARENT, 0xb8, 2, 0 }, + { HISTB_USB2_48M_CLK, "clk_u2_48m", "48m", + CLK_SET_RATE_PARENT, 0xb8, 1, 0 }, + { HISTB_USB2_UTMI_CLK, "clk_u2_utmi", "60m", + CLK_SET_RATE_PARENT, 0xb8, 5, 0 }, + { HISTB_USB2_UTMI_CLK1, "clk_u2_utmi1", "60m", + CLK_SET_RATE_PARENT, 0xb8, 6, 0 }, + { HISTB_USB2_OTG_UTMI_CLK, "clk_u2_otg_utmi", "60m", + CLK_SET_RATE_PARENT, 0xb8, 3, 0 }, + { HISTB_USB2_PHY1_REF_CLK, "clk_u2_phy1_ref", "24m", + CLK_SET_RATE_PARENT, 0xbc, 0, 0 }, + { HISTB_USB2_PHY2_REF_CLK, "clk_u2_phy2_ref", "24m", + CLK_SET_RATE_PARENT, 0xbc, 2, 0 }, + /* USB2 2 */ + { HISTB_USB2_2_BUS_CLK, "clk_u2_2_bus", "clk_ahb", + CLK_SET_RATE_PARENT, 0x198, 0, 0, }, + { HISTB_USB2_2_PHY_CLK, "clk_u2_2_phy", "60m", + CLK_SET_RATE_PARENT, 0x198, 4, 0, }, + { HISTB_USB2_2_12M_CLK, "clk_u2_2_12m", "12m", + CLK_SET_RATE_PARENT, 0x198, 2, 0 }, + { HISTB_USB2_2_48M_CLK, "clk_u2_2_48m", "48m", + CLK_SET_RATE_PARENT, 0x198, 1, 0 }, + { HISTB_USB2_2_UTMI_CLK, "clk_u2_2_utmi", "60m", + CLK_SET_RATE_PARENT, 0x198, 5, 0 }, + { HISTB_USB2_2_UTMI_CLK1, "clk_u2_2_utmi1", "60m", + CLK_SET_RATE_PARENT, 0x198, 6, 0 }, + { HISTB_USB2_2_OTG_UTMI_CLK, "clk_u2_2_otg_utmi", "60m", + CLK_SET_RATE_PARENT, 0x198, 3, 0 }, + { HISTB_USB2_2_PHY1_REF_CLK, "clk_u2_2_phy1_ref", "24m", + CLK_SET_RATE_PARENT, 0x190, 0, 0 }, + { HISTB_USB2_2_PHY2_REF_CLK, "clk_u2_2_phy2_ref", "24m", + CLK_SET_RATE_PARENT, 0x190, 2, 0 }, + /* USB3 */ + { HISTB_USB3_BUS_CLK, "clk_u3_bus", NULL, + CLK_SET_RATE_PARENT, 0xb0, 0, 0 }, + { HISTB_USB3_UTMI_CLK, "clk_u3_utmi", NULL, + CLK_SET_RATE_PARENT, 0xb0, 4, 0 }, + { HISTB_USB3_PIPE_CLK, "clk_u3_pipe", NULL, + CLK_SET_RATE_PARENT, 0xb0, 3, 0 }, + { HISTB_USB3_SUSPEND_CLK, "clk_u3_suspend", NULL, + CLK_SET_RATE_PARENT, 0xb0, 2, 0 }, + /* GPU */ + { HISTB_GPU_BUS_CLK, "clk_gpu", "200m", + CLK_SET_RATE_PARENT, 0xd4, 0, 0 }, + /* FEPHY */ + { HISTB_FEPHY_CLK, "clk_fephy", "25m", + CLK_SET_RATE_PARENT, 0x120, 0, 0, }, +}; + +static const struct hi3798_complex_clock hi3798mv100_complex_clks[] = { + { HISTB_ETH0_MAC_CLK, "clk_mac0", NULL, + CLK_SET_RATE_PARENT, 0xcc, 0xf, 0xb, }, + { HISTB_GPU_CORE_CLK, "clk_gpu_gp", "200m", + CLK_SET_RATE_PARENT, 0xd4, 0x700, 0x700, }, +}; + +static const struct hi3798_clks hi3798mv100_crg_clks = { + .gate_clks = hi3798mv100_gate_clks, + .gate_clks_nums = ARRAY_SIZE(hi3798mv100_gate_clks), + .mux_clks = hi3798mv100_mux_clks, + .mux_clks_nums = ARRAY_SIZE(hi3798mv100_mux_clks), + .phase_clks = hi3798cv200_phase_clks, + .phase_clks_nums = ARRAY_SIZE(hi3798cv200_phase_clks), + .complex_clks = hi3798mv100_complex_clks, + .complex_clks_nums = ARRAY_SIZE(hi3798mv100_complex_clks), +}; + +static struct hisi_clock_data *hi3798mv100_clk_register( + struct platform_device *pdev) +{ + return hi3798_clk_register(pdev, &hi3798mv100_crg_clks); +} + +static void hi3798mv100_clk_unregister(struct platform_device *pdev) +{ + hi3798_clk_unregister(pdev, &hi3798mv100_crg_clks); +} + +static const struct hisi_crg_funcs hi3798mv100_crg_funcs = { + .register_clks = hi3798mv100_clk_register, + .unregister_clks = hi3798mv100_clk_unregister, +}; + +static const struct hisi_gate_clock hi3798mv100_sysctrl_gate_clks[] = { + { HISTB_IR_CLK, "clk_ir", "24m", + CLK_SET_RATE_PARENT, 0x48, 4, 0, }, + { HISTB_TIMER01_CLK, "clk_timer01", "24m", + CLK_SET_RATE_PARENT, 0x48, 6, 0, }, + { HISTB_UART0_CLK, "clk_uart0", "83p3m", + CLK_SET_RATE_PARENT, 0x48, 12, 0, }, +}; + +static const struct hi3798_clks hi3798mv100_sysctrl_clks = { + .gate_clks = hi3798mv100_sysctrl_gate_clks, + .gate_clks_nums = ARRAY_SIZE(hi3798mv100_sysctrl_gate_clks), +}; + +static struct hisi_clock_data *hi3798mv100_sysctrl_clk_register( + struct platform_device *pdev) +{ + return hi3798_sysctrl_clk_register(pdev, &hi3798mv100_sysctrl_clks); +} + +static void hi3798mv100_sysctrl_clk_unregister(struct platform_device *pdev) +{ + hi3798_sysctrl_clk_unregister(pdev, &hi3798mv100_sysctrl_clks); +} + +static const struct hisi_crg_funcs hi3798mv100_sysctrl_funcs = { + .register_clks = hi3798mv100_sysctrl_clk_register, + .unregister_clks = hi3798mv100_sysctrl_clk_unregister, +}; + static const struct of_device_id hi3798_crg_match_table[] = { { .compatible = "hisilicon,hi3798cv200-crg", .data = &hi3798cv200_crg_funcs }, { .compatible = "hisilicon,hi3798cv200-sysctrl", .data = &hi3798cv200_sysctrl_funcs }, + { .compatible = "hisilicon,hi3798mv100-crg", + .data = &hi3798mv100_crg_funcs }, + { .compatible = "hisilicon,hi3798mv100-sysctrl", + .data = &hi3798mv100_sysctrl_funcs }, { } }; MODULE_DEVICE_TABLE(of, hi3798_crg_match_table);