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[2620:137:e000::1:20]) by mx.google.com with ESMTP id l198-20020a633ecf000000b0043ce6a5a14bsi19624979pga.99.2022.10.19.12.14.29; Wed, 19 Oct 2022 12:14:47 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230359AbiJSTMA (ORCPT + 99 others); Wed, 19 Oct 2022 15:12:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50196 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230441AbiJSTLh (ORCPT ); Wed, 19 Oct 2022 15:11:37 -0400 Received: from mail-ot1-f50.google.com (mail-ot1-f50.google.com [209.85.210.50]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3BAB11C2F20; Wed, 19 Oct 2022 12:11:34 -0700 (PDT) Received: by mail-ot1-f50.google.com with SMTP id d18-20020a05683025d200b00661c6f1b6a4so10070618otu.1; Wed, 19 Oct 2022 12:11:34 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JxlkIVs552Ejp+aX9wrJgo7YCeTd9sG0ZHnn6ZfglP4=; b=uWT3wBwWtuLmr4ZFpImtSCFfr1YxpJey1dB3KFW3NOUuly34N42oSSmh1I7UNcCj39 laiWiBt2t4prnwhmhwAdEXkq9LgQKviX/1lNX0II98mBkFzE1r8zkHQjRhxGv/l5S+QZ UXcEdFaftsd7nrN+n+cpo4PTlmYPHPJQXNQ8TbuCWWvs5+RAmmPHf1eXn9xyt5vAgBAF EFc6jpOYJlTyHZyIf9ajHMqQJDYtTKE8sKH4ZrntllecgkKe7YfkiDv3pqESVMIAGF6Q gYAeWH4b8vADJ+eHTcc+Kj8zMZ4w100p5PgwF+8nCpsWi8Ln0Bo8fsgAw4AOzbtewADb XQBQ== X-Gm-Message-State: ACrzQf2qyPswqBV2SuoZzSHKNcUSTO5KiNRdWAkw53/Dc/MB8+fmc5h0 AXLjna2eRJcckxBAqK4SFQ== X-Received: by 2002:a05:6830:25c3:b0:661:c7e4:e785 with SMTP id d3-20020a05683025c300b00661c7e4e785mr4817162otu.134.1666206692965; Wed, 19 Oct 2022 12:11:32 -0700 (PDT) Received: from robh_at_kernel.org (66-90-144-107.dyn.grandenetworks.net. [66.90.144.107]) by smtp.gmail.com with ESMTPSA id f17-20020a4ae611000000b00480b7efd5d9sm5922591oot.6.2022.10.19.12.11.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Oct 2022 12:11:32 -0700 (PDT) Received: (nullmailer pid 3420898 invoked by uid 1000); Wed, 19 Oct 2022 19:11:25 -0000 From: Rob Herring Date: Wed, 19 Oct 2022 14:11:24 -0500 Subject: [PATCH v2 1/7] perf: arm_spe: Use feature numbering for PMSEVFR_EL1 defines MIME-Version: 1.0 Message-Id: <20220825-arm-spe-v8-7-v2-1-e37322d68ac0@kernel.org> References: <20220825-arm-spe-v8-7-v2-0-e37322d68ac0@kernel.org> In-Reply-To: <20220825-arm-spe-v8-7-v2-0-e37322d68ac0@kernel.org> To: Namhyung Kim , James Morse , Ingo Molnar , Mark Rutland , Marc Zyngier , Suzuki K Poulose , Will Deacon , Alexandru Elisei , Catalin Marinas , Arnaldo Carvalho de Melo , Peter Zijlstra , Alexander Shishkin , Oliver Upton , Jiri Olsa Cc: kvmarm@lists.cs.columbia.edu, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.11.0-dev X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00, FREEMAIL_ENVFROM_END_DIGIT,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747144552804979670?= X-GMAIL-MSGID: =?utf-8?q?1747144552804979670?= Similar to commit 121a8fc088f1 ("arm64/sysreg: Use feature numbering for PMU and SPE revisions") use feature numbering instead of architecture versions for the PMSEVFR_EL1 Res0 defines. Signed-off-by: Rob Herring --- v2: - New patch --- arch/arm64/include/asm/sysreg.h | 6 +++--- drivers/perf/arm_spe_pmu.c | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 7d301700d1a9..9a4cf12e3e16 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -294,11 +294,11 @@ #define SYS_PMSFCR_EL1_ST_SHIFT 18 #define SYS_PMSEVFR_EL1 sys_reg(3, 0, 9, 9, 5) -#define SYS_PMSEVFR_EL1_RES0_8_2 \ +#define PMSEVFR_EL1_RES0_IMP \ (GENMASK_ULL(47, 32) | GENMASK_ULL(23, 16) | GENMASK_ULL(11, 8) |\ BIT_ULL(6) | BIT_ULL(4) | BIT_ULL(2) | BIT_ULL(0)) -#define SYS_PMSEVFR_EL1_RES0_8_3 \ - (SYS_PMSEVFR_EL1_RES0_8_2 & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11))) +#define PMSEVFR_EL1_RES0_V1P1 \ + (PMSEVFR_EL1_RES0_IMP & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11))) #define SYS_PMSLATFR_EL1 sys_reg(3, 0, 9, 9, 6) #define SYS_PMSLATFR_EL1_MINLAT_SHIFT 0 diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c index 00e3a637f7b6..65cf93dcc8ee 100644 --- a/drivers/perf/arm_spe_pmu.c +++ b/drivers/perf/arm_spe_pmu.c @@ -677,11 +677,11 @@ static u64 arm_spe_pmsevfr_res0(u16 pmsver) { switch (pmsver) { case ID_AA64DFR0_EL1_PMSVer_IMP: - return SYS_PMSEVFR_EL1_RES0_8_2; + return PMSEVFR_EL1_RES0_IMP; case ID_AA64DFR0_EL1_PMSVer_V1P1: /* Return the highest version we support in default */ default: - return SYS_PMSEVFR_EL1_RES0_8_3; + return PMSEVFR_EL1_RES0_V1P1; } } From patchwork Wed Oct 19 19:11:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 5813 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp492431wrs; Wed, 19 Oct 2022 12:14:27 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5AtUDymwVwdVN1Xg0pgORq+1D0GcXz8uALnbIwoAUQbwSm7/UnInB2OF8PRTnT6d2kB5+T X-Received: by 2002:a63:e22:0:b0:458:cfe7:958 with SMTP id d34-20020a630e22000000b00458cfe70958mr8350086pgl.449.1666206867533; Wed, 19 Oct 2022 12:14:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666206867; cv=none; d=google.com; s=arc-20160816; b=m/oUdH0HHOC1WW+WKHqCLzTbZaPA5FTlaepzhWA0O7CIqgddvGuPmTeBRNCQ5PAnZ6 AIevd40FSYexyf67FfKjoB5X2fYtd+kNElgWzle7fU5TslG0hOogPthjUEf7dGmCvO7S HZ5yyqruZzzMDFiRtM8e1f/RKUuiw2BDADOYbXu0TLsnnE59zhPjHOJw04ohX+NUD5Eh nFaxVztBxsuvYoPcihfu2mwIJWsEesJzzNkiT6sE7tjQzbNhVaw6Tf5HuRjOJuelQs+d EexGcjLMq7iF5btAMFy9JoY4Bh/C711y3cOWCSY2i1UOuL+MTAcwZprQPkjjZLA1znf9 B8OA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from; bh=k24AQgKpVvc1442j/biKSQfKpOyhAXCqlqrMvI7oSIc=; b=TIUC3QlRC0ObC5MNZhEDR/BtlZJIn3IsnYEjRCP5rQwa9roSJ34KoyA+eI6dxHAlbA zZXSReXLbbytJai0CUoMBkB8knKI5LdmNEjSFpnDd23aXGwccoV/Is8Yzjgkbu6YM4Ko NWs9T4f99R/TB5mmekBK2QklrVOt1tSt4MReOuNfLUtEW5FdBLwp/vQMGJCJrJP1KoMI EgS7NAiBSu/KRYePFv6r2GWObjW5xrygdVdprYgvcjojtJCk/7jTWwhvrhsrGF84V+UG FUhDBPMUQ4HNLQs6lrw3XbLiR/E0Cy4Nw28vpWL35BJ5zDCvcb/rRur1p0an9UAaADWy 0zKw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (out1.vger.email. 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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id i9-20020aca2b09000000b00354b1edb60fsm6945231oik.32.2022.10.19.12.11.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Oct 2022 12:11:25 -0700 (PDT) Received: (nullmailer pid 3420900 invoked by uid 1000); Wed, 19 Oct 2022 19:11:25 -0000 From: Rob Herring Date: Wed, 19 Oct 2022 14:11:25 -0500 Subject: [PATCH v2 2/7] arm64: Drop SYS_ from SPE register defines MIME-Version: 1.0 Message-Id: <20220825-arm-spe-v8-7-v2-2-e37322d68ac0@kernel.org> References: <20220825-arm-spe-v8-7-v2-0-e37322d68ac0@kernel.org> In-Reply-To: <20220825-arm-spe-v8-7-v2-0-e37322d68ac0@kernel.org> To: Namhyung Kim , James Morse , Ingo Molnar , Mark Rutland , Marc Zyngier , Suzuki K Poulose , Will Deacon , Alexandru Elisei , Catalin Marinas , Arnaldo Carvalho de Melo , Peter Zijlstra , Alexander Shishkin , Oliver Upton , Jiri Olsa Cc: kvmarm@lists.cs.columbia.edu, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.11.0-dev X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00, FREEMAIL_ENVFROM_END_DIGIT,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2, SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747144532598362351?= X-GMAIL-MSGID: =?utf-8?q?1747144532598362351?= We currently have a non-standard SYS_ prefix in the constants generated for the SPE register bitfields. Drop this in preparation for automatic register definition generation. The SPE mask defines were unshifted, and the SPE register field enumerations were shifted. The autogenerated defines are the opposite, so make the necessary adjustments. No functional changes. Signed-off-by: Rob Herring --- v2: - New patch --- arch/arm64/include/asm/el2_setup.h | 6 +- arch/arm64/include/asm/sysreg.h | 112 ++++++++++++++++++------------------- arch/arm64/kvm/debug.c | 2 +- arch/arm64/kvm/hyp/nvhe/debug-sr.c | 2 +- drivers/perf/arm_spe_pmu.c | 85 ++++++++++++++-------------- 5 files changed, 103 insertions(+), 104 deletions(-) diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h index 668569adf4d3..f9da43e53cdb 100644 --- a/arch/arm64/include/asm/el2_setup.h +++ b/arch/arm64/include/asm/el2_setup.h @@ -53,10 +53,10 @@ cbz x0, .Lskip_spe_\@ // Skip if SPE not present mrs_s x0, SYS_PMBIDR_EL1 // If SPE available at EL2, - and x0, x0, #(1 << SYS_PMBIDR_EL1_P_SHIFT) + and x0, x0, #(1 << PMBIDR_EL1_P_SHIFT) cbnz x0, .Lskip_spe_el2_\@ // then permit sampling of physical - mov x0, #(1 << SYS_PMSCR_EL2_PCT_SHIFT | \ - 1 << SYS_PMSCR_EL2_PA_SHIFT) + mov x0, #(1 << PMSCR_EL2_PCT_SHIFT | \ + 1 << PMSCR_EL2_PA_SHIFT) msr_s SYS_PMSCR_EL2, x0 // addresses and physical counter .Lskip_spe_el2_\@: mov x0, #(MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 9a4cf12e3e16..8df8a0a51273 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -239,59 +239,59 @@ /*** Statistical Profiling Extension ***/ /* ID registers */ #define SYS_PMSIDR_EL1 sys_reg(3, 0, 9, 9, 7) -#define SYS_PMSIDR_EL1_FE_SHIFT 0 -#define SYS_PMSIDR_EL1_FT_SHIFT 1 -#define SYS_PMSIDR_EL1_FL_SHIFT 2 -#define SYS_PMSIDR_EL1_ARCHINST_SHIFT 3 -#define SYS_PMSIDR_EL1_LDS_SHIFT 4 -#define SYS_PMSIDR_EL1_ERND_SHIFT 5 -#define SYS_PMSIDR_EL1_INTERVAL_SHIFT 8 -#define SYS_PMSIDR_EL1_INTERVAL_MASK 0xfUL -#define SYS_PMSIDR_EL1_MAXSIZE_SHIFT 12 -#define SYS_PMSIDR_EL1_MAXSIZE_MASK 0xfUL -#define SYS_PMSIDR_EL1_COUNTSIZE_SHIFT 16 -#define SYS_PMSIDR_EL1_COUNTSIZE_MASK 0xfUL +#define PMSIDR_EL1_FE_SHIFT 0 +#define PMSIDR_EL1_FT_SHIFT 1 +#define PMSIDR_EL1_FL_SHIFT 2 +#define PMSIDR_EL1_ARCHINST_SHIFT 3 +#define PMSIDR_EL1_LDS_SHIFT 4 +#define PMSIDR_EL1_ERND_SHIFT 5 +#define PMSIDR_EL1_INTERVAL_SHIFT 8 +#define PMSIDR_EL1_INTERVAL_MASK GENMASK_ULL(11, 8) +#define PMSIDR_EL1_MAXSIZE_SHIFT 12 +#define PMSIDR_EL1_MAXSIZE_MASK GENMASK_ULL(15, 12) +#define PMSIDR_EL1_COUNTSIZE_SHIFT 16 +#define PMSIDR_EL1_COUNTSIZE_MASK GENMASK_ULL(19, 16) #define SYS_PMBIDR_EL1 sys_reg(3, 0, 9, 10, 7) -#define SYS_PMBIDR_EL1_ALIGN_SHIFT 0 -#define SYS_PMBIDR_EL1_ALIGN_MASK 0xfU -#define SYS_PMBIDR_EL1_P_SHIFT 4 -#define SYS_PMBIDR_EL1_F_SHIFT 5 +#define PMBIDR_EL1_ALIGN_SHIFT 0 +#define PMBIDR_EL1_ALIGN_MASK 0xfU +#define PMBIDR_EL1_P_SHIFT 4 +#define PMBIDR_EL1_F_SHIFT 5 /* Sampling controls */ #define SYS_PMSCR_EL1 sys_reg(3, 0, 9, 9, 0) -#define SYS_PMSCR_EL1_E0SPE_SHIFT 0 -#define SYS_PMSCR_EL1_E1SPE_SHIFT 1 -#define SYS_PMSCR_EL1_CX_SHIFT 3 -#define SYS_PMSCR_EL1_PA_SHIFT 4 -#define SYS_PMSCR_EL1_TS_SHIFT 5 -#define SYS_PMSCR_EL1_PCT_SHIFT 6 +#define PMSCR_EL1_E0SPE_SHIFT 0 +#define PMSCR_EL1_E1SPE_SHIFT 1 +#define PMSCR_EL1_CX_SHIFT 3 +#define PMSCR_EL1_PA_SHIFT 4 +#define PMSCR_EL1_TS_SHIFT 5 +#define PMSCR_EL1_PCT_SHIFT 6 #define SYS_PMSCR_EL2 sys_reg(3, 4, 9, 9, 0) -#define SYS_PMSCR_EL2_E0HSPE_SHIFT 0 -#define SYS_PMSCR_EL2_E2SPE_SHIFT 1 -#define SYS_PMSCR_EL2_CX_SHIFT 3 -#define SYS_PMSCR_EL2_PA_SHIFT 4 -#define SYS_PMSCR_EL2_TS_SHIFT 5 -#define SYS_PMSCR_EL2_PCT_SHIFT 6 +#define PMSCR_EL2_E0HSPE_SHIFT 0 +#define PMSCR_EL2_E2SPE_SHIFT 1 +#define PMSCR_EL2_CX_SHIFT 3 +#define PMSCR_EL2_PA_SHIFT 4 +#define PMSCR_EL2_TS_SHIFT 5 +#define PMSCR_EL2_PCT_SHIFT 6 #define SYS_PMSICR_EL1 sys_reg(3, 0, 9, 9, 2) #define SYS_PMSIRR_EL1 sys_reg(3, 0, 9, 9, 3) -#define SYS_PMSIRR_EL1_RND_SHIFT 0 -#define SYS_PMSIRR_EL1_INTERVAL_SHIFT 8 -#define SYS_PMSIRR_EL1_INTERVAL_MASK 0xffffffUL +#define PMSIRR_EL1_RND_SHIFT 0 +#define PMSIRR_EL1_INTERVAL_SHIFT 8 +#define PMSIRR_EL1_INTERVAL_MASK GENMASK_ULL(31, 8) /* Filtering controls */ #define SYS_PMSNEVFR_EL1 sys_reg(3, 0, 9, 9, 1) #define SYS_PMSFCR_EL1 sys_reg(3, 0, 9, 9, 4) -#define SYS_PMSFCR_EL1_FE_SHIFT 0 -#define SYS_PMSFCR_EL1_FT_SHIFT 1 -#define SYS_PMSFCR_EL1_FL_SHIFT 2 -#define SYS_PMSFCR_EL1_B_SHIFT 16 -#define SYS_PMSFCR_EL1_LD_SHIFT 17 -#define SYS_PMSFCR_EL1_ST_SHIFT 18 +#define PMSFCR_EL1_FE_SHIFT 0 +#define PMSFCR_EL1_FT_SHIFT 1 +#define PMSFCR_EL1_FL_SHIFT 2 +#define PMSFCR_EL1_B_SHIFT 16 +#define PMSFCR_EL1_LD_SHIFT 17 +#define PMSFCR_EL1_ST_SHIFT 18 #define SYS_PMSEVFR_EL1 sys_reg(3, 0, 9, 9, 5) #define PMSEVFR_EL1_RES0_IMP \ @@ -301,37 +301,37 @@ (PMSEVFR_EL1_RES0_IMP & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11))) #define SYS_PMSLATFR_EL1 sys_reg(3, 0, 9, 9, 6) -#define SYS_PMSLATFR_EL1_MINLAT_SHIFT 0 +#define PMSLATFR_EL1_MINLAT_SHIFT 0 /* Buffer controls */ #define SYS_PMBLIMITR_EL1 sys_reg(3, 0, 9, 10, 0) -#define SYS_PMBLIMITR_EL1_E_SHIFT 0 -#define SYS_PMBLIMITR_EL1_FM_SHIFT 1 -#define SYS_PMBLIMITR_EL1_FM_MASK 0x3UL -#define SYS_PMBLIMITR_EL1_FM_STOP_IRQ (0 << SYS_PMBLIMITR_EL1_FM_SHIFT) +#define PMBLIMITR_EL1_E_SHIFT 0 +#define PMBLIMITR_EL1_FM_SHIFT 1 +#define PMBLIMITR_EL1_FM_MASK GENMASK_ULL(2, 1) +#define PMBLIMITR_EL1_FM_STOP_IRQ 0 #define SYS_PMBPTR_EL1 sys_reg(3, 0, 9, 10, 1) /* Buffer error reporting */ #define SYS_PMBSR_EL1 sys_reg(3, 0, 9, 10, 3) -#define SYS_PMBSR_EL1_COLL_SHIFT 16 -#define SYS_PMBSR_EL1_S_SHIFT 17 -#define SYS_PMBSR_EL1_EA_SHIFT 18 -#define SYS_PMBSR_EL1_DL_SHIFT 19 -#define SYS_PMBSR_EL1_EC_SHIFT 26 -#define SYS_PMBSR_EL1_EC_MASK 0x3fUL +#define PMBSR_EL1_COLL_SHIFT 16 +#define PMBSR_EL1_S_SHIFT 17 +#define PMBSR_EL1_EA_SHIFT 18 +#define PMBSR_EL1_DL_SHIFT 19 +#define PMBSR_EL1_EC_SHIFT 26 +#define PMBSR_EL1_EC_MASK GENMASK_ULL(31, 26) -#define SYS_PMBSR_EL1_EC_BUF (0x0UL << SYS_PMBSR_EL1_EC_SHIFT) -#define SYS_PMBSR_EL1_EC_FAULT_S1 (0x24UL << SYS_PMBSR_EL1_EC_SHIFT) -#define SYS_PMBSR_EL1_EC_FAULT_S2 (0x25UL << SYS_PMBSR_EL1_EC_SHIFT) +#define PMBSR_EL1_EC_BUF 0x0UL +#define PMBSR_EL1_EC_FAULT_S1 0x24UL +#define PMBSR_EL1_EC_FAULT_S2 0x25UL -#define SYS_PMBSR_EL1_FAULT_FSC_SHIFT 0 -#define SYS_PMBSR_EL1_FAULT_FSC_MASK 0x3fUL +#define PMBSR_EL1_FAULT_FSC_SHIFT 0 +#define PMBSR_EL1_FAULT_FSC_MASK 0x3fUL -#define SYS_PMBSR_EL1_BUF_BSC_SHIFT 0 -#define SYS_PMBSR_EL1_BUF_BSC_MASK 0x3fUL +#define PMBSR_EL1_BUF_BSC_SHIFT 0 +#define PMBSR_EL1_BUF_BSC_MASK 0x3fUL -#define SYS_PMBSR_EL1_BUF_BSC_FULL (0x1UL << SYS_PMBSR_EL1_BUF_BSC_SHIFT) +#define PMBSR_EL1_BUF_BSC_FULL 0x1UL /*** End of Statistical Profiling Extension ***/ diff --git a/arch/arm64/kvm/debug.c b/arch/arm64/kvm/debug.c index fccf9ec01813..55f80fb93925 100644 --- a/arch/arm64/kvm/debug.c +++ b/arch/arm64/kvm/debug.c @@ -328,7 +328,7 @@ void kvm_arch_vcpu_load_debug_state_flags(struct kvm_vcpu *vcpu) * we may need to check if the host state needs to be saved. */ if (cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_EL1_PMSVer_SHIFT) && - !(read_sysreg_s(SYS_PMBIDR_EL1) & BIT(SYS_PMBIDR_EL1_P_SHIFT))) + !(read_sysreg_s(SYS_PMBIDR_EL1) & BIT(PMBIDR_EL1_P_SHIFT))) vcpu_set_flag(vcpu, DEBUG_STATE_SAVE_SPE); /* Check if we have TRBE implemented and available at the host */ diff --git a/arch/arm64/kvm/hyp/nvhe/debug-sr.c b/arch/arm64/kvm/hyp/nvhe/debug-sr.c index e17455773b98..2673bde62fad 100644 --- a/arch/arm64/kvm/hyp/nvhe/debug-sr.c +++ b/arch/arm64/kvm/hyp/nvhe/debug-sr.c @@ -27,7 +27,7 @@ static void __debug_save_spe(u64 *pmscr_el1) * Check if the host is actually using it ? */ reg = read_sysreg_s(SYS_PMBLIMITR_EL1); - if (!(reg & BIT(SYS_PMBLIMITR_EL1_E_SHIFT))) + if (!(reg & BIT(PMBLIMITR_EL1_E_SHIFT))) return; /* Yes; save the control register and disable data generation */ diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c index 65cf93dcc8ee..814ed18346b6 100644 --- a/drivers/perf/arm_spe_pmu.c +++ b/drivers/perf/arm_spe_pmu.c @@ -12,6 +12,7 @@ #define DRVNAME PMUNAME "_pmu" #define pr_fmt(fmt) DRVNAME ": " fmt +#include #include #include #include @@ -282,18 +283,18 @@ static u64 arm_spe_event_to_pmscr(struct perf_event *event) struct perf_event_attr *attr = &event->attr; u64 reg = 0; - reg |= ATTR_CFG_GET_FLD(attr, ts_enable) << SYS_PMSCR_EL1_TS_SHIFT; - reg |= ATTR_CFG_GET_FLD(attr, pa_enable) << SYS_PMSCR_EL1_PA_SHIFT; - reg |= ATTR_CFG_GET_FLD(attr, pct_enable) << SYS_PMSCR_EL1_PCT_SHIFT; + reg |= ATTR_CFG_GET_FLD(attr, ts_enable) << PMSCR_EL1_TS_SHIFT; + reg |= ATTR_CFG_GET_FLD(attr, pa_enable) << PMSCR_EL1_PA_SHIFT; + reg |= ATTR_CFG_GET_FLD(attr, pct_enable) << PMSCR_EL1_PCT_SHIFT; if (!attr->exclude_user) - reg |= BIT(SYS_PMSCR_EL1_E0SPE_SHIFT); + reg |= BIT(PMSCR_EL1_E0SPE_SHIFT); if (!attr->exclude_kernel) - reg |= BIT(SYS_PMSCR_EL1_E1SPE_SHIFT); + reg |= BIT(PMSCR_EL1_E1SPE_SHIFT); if (get_spe_event_has_cx(event)) - reg |= BIT(SYS_PMSCR_EL1_CX_SHIFT); + reg |= BIT(PMSCR_EL1_CX_SHIFT); return reg; } @@ -302,8 +303,7 @@ static void arm_spe_event_sanitise_period(struct perf_event *event) { struct arm_spe_pmu *spe_pmu = to_spe_pmu(event->pmu); u64 period = event->hw.sample_period; - u64 max_period = SYS_PMSIRR_EL1_INTERVAL_MASK - << SYS_PMSIRR_EL1_INTERVAL_SHIFT; + u64 max_period = PMSIRR_EL1_INTERVAL_MASK; if (period < spe_pmu->min_period) period = spe_pmu->min_period; @@ -322,7 +322,7 @@ static u64 arm_spe_event_to_pmsirr(struct perf_event *event) arm_spe_event_sanitise_period(event); - reg |= ATTR_CFG_GET_FLD(attr, jitter) << SYS_PMSIRR_EL1_RND_SHIFT; + reg |= ATTR_CFG_GET_FLD(attr, jitter) << PMSIRR_EL1_RND_SHIFT; reg |= event->hw.sample_period; return reg; @@ -333,18 +333,18 @@ static u64 arm_spe_event_to_pmsfcr(struct perf_event *event) struct perf_event_attr *attr = &event->attr; u64 reg = 0; - reg |= ATTR_CFG_GET_FLD(attr, load_filter) << SYS_PMSFCR_EL1_LD_SHIFT; - reg |= ATTR_CFG_GET_FLD(attr, store_filter) << SYS_PMSFCR_EL1_ST_SHIFT; - reg |= ATTR_CFG_GET_FLD(attr, branch_filter) << SYS_PMSFCR_EL1_B_SHIFT; + reg |= ATTR_CFG_GET_FLD(attr, load_filter) << PMSFCR_EL1_LD_SHIFT; + reg |= ATTR_CFG_GET_FLD(attr, store_filter) << PMSFCR_EL1_ST_SHIFT; + reg |= ATTR_CFG_GET_FLD(attr, branch_filter) << PMSFCR_EL1_B_SHIFT; if (reg) - reg |= BIT(SYS_PMSFCR_EL1_FT_SHIFT); + reg |= BIT(PMSFCR_EL1_FT_SHIFT); if (ATTR_CFG_GET_FLD(attr, event_filter)) - reg |= BIT(SYS_PMSFCR_EL1_FE_SHIFT); + reg |= BIT(PMSFCR_EL1_FE_SHIFT); if (ATTR_CFG_GET_FLD(attr, min_latency)) - reg |= BIT(SYS_PMSFCR_EL1_FL_SHIFT); + reg |= BIT(PMSFCR_EL1_FL_SHIFT); return reg; } @@ -359,7 +359,7 @@ static u64 arm_spe_event_to_pmslatfr(struct perf_event *event) { struct perf_event_attr *attr = &event->attr; return ATTR_CFG_GET_FLD(attr, min_latency) - << SYS_PMSLATFR_EL1_MINLAT_SHIFT; + << PMSLATFR_EL1_MINLAT_SHIFT; } static void arm_spe_pmu_pad_buf(struct perf_output_handle *handle, int len) @@ -511,7 +511,7 @@ static void arm_spe_perf_aux_output_begin(struct perf_output_handle *handle, limit = buf->snapshot ? arm_spe_pmu_next_snapshot_off(handle) : arm_spe_pmu_next_off(handle); if (limit) - limit |= BIT(SYS_PMBLIMITR_EL1_E_SHIFT); + limit |= BIT(PMBLIMITR_EL1_E_SHIFT); limit += (u64)buf->base; base = (u64)buf->base + PERF_IDX2OFF(handle->head, buf); @@ -570,28 +570,28 @@ arm_spe_pmu_buf_get_fault_act(struct perf_output_handle *handle) /* Service required? */ pmbsr = read_sysreg_s(SYS_PMBSR_EL1); - if (!(pmbsr & BIT(SYS_PMBSR_EL1_S_SHIFT))) + if (!(pmbsr & BIT(PMBSR_EL1_S_SHIFT))) return SPE_PMU_BUF_FAULT_ACT_SPURIOUS; /* * If we've lost data, disable profiling and also set the PARTIAL * flag to indicate that the last record is corrupted. */ - if (pmbsr & BIT(SYS_PMBSR_EL1_DL_SHIFT)) + if (pmbsr & BIT(PMBSR_EL1_DL_SHIFT)) perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED | PERF_AUX_FLAG_PARTIAL); /* Report collisions to userspace so that it can up the period */ - if (pmbsr & BIT(SYS_PMBSR_EL1_COLL_SHIFT)) + if (pmbsr & BIT(PMBSR_EL1_COLL_SHIFT)) perf_aux_output_flag(handle, PERF_AUX_FLAG_COLLISION); /* We only expect buffer management events */ - switch (pmbsr & (SYS_PMBSR_EL1_EC_MASK << SYS_PMBSR_EL1_EC_SHIFT)) { - case SYS_PMBSR_EL1_EC_BUF: + switch (FIELD_GET(PMBSR_EL1_EC_MASK, pmbsr)) { + case PMBSR_EL1_EC_BUF: /* Handled below */ break; - case SYS_PMBSR_EL1_EC_FAULT_S1: - case SYS_PMBSR_EL1_EC_FAULT_S2: + case PMBSR_EL1_EC_FAULT_S1: + case PMBSR_EL1_EC_FAULT_S2: err_str = "Unexpected buffer fault"; goto out_err; default: @@ -600,9 +600,8 @@ arm_spe_pmu_buf_get_fault_act(struct perf_output_handle *handle) } /* Buffer management event */ - switch (pmbsr & - (SYS_PMBSR_EL1_BUF_BSC_MASK << SYS_PMBSR_EL1_BUF_BSC_SHIFT)) { - case SYS_PMBSR_EL1_BUF_BSC_FULL: + switch (FIELD_GET(PMBSR_EL1_BUF_BSC_MASK, pmbsr)) { + case PMBSR_EL1_BUF_BSC_FULL: ret = SPE_PMU_BUF_FAULT_ACT_OK; goto out_stop; default: @@ -717,23 +716,23 @@ static int arm_spe_pmu_event_init(struct perf_event *event) return -EINVAL; reg = arm_spe_event_to_pmsfcr(event); - if ((reg & BIT(SYS_PMSFCR_EL1_FE_SHIFT)) && + if ((reg & BIT(PMSFCR_EL1_FE_SHIFT)) && !(spe_pmu->features & SPE_PMU_FEAT_FILT_EVT)) return -EOPNOTSUPP; - if ((reg & BIT(SYS_PMSFCR_EL1_FT_SHIFT)) && + if ((reg & BIT(PMSFCR_EL1_FT_SHIFT)) && !(spe_pmu->features & SPE_PMU_FEAT_FILT_TYP)) return -EOPNOTSUPP; - if ((reg & BIT(SYS_PMSFCR_EL1_FL_SHIFT)) && + if ((reg & BIT(PMSFCR_EL1_FL_SHIFT)) && !(spe_pmu->features & SPE_PMU_FEAT_FILT_LAT)) return -EOPNOTSUPP; set_spe_event_has_cx(event); reg = arm_spe_event_to_pmscr(event); if (!perfmon_capable() && - (reg & (BIT(SYS_PMSCR_EL1_PA_SHIFT) | - BIT(SYS_PMSCR_EL1_PCT_SHIFT)))) + (reg & (BIT(PMSCR_EL1_PA_SHIFT) | + BIT(PMSCR_EL1_PCT_SHIFT)))) return -EACCES; return 0; @@ -971,14 +970,14 @@ static void __arm_spe_pmu_dev_probe(void *info) /* Read PMBIDR first to determine whether or not we have access */ reg = read_sysreg_s(SYS_PMBIDR_EL1); - if (reg & BIT(SYS_PMBIDR_EL1_P_SHIFT)) { + if (reg & BIT(PMBIDR_EL1_P_SHIFT)) { dev_err(dev, "profiling buffer owned by higher exception level\n"); return; } /* Minimum alignment. If it's out-of-range, then fail the probe */ - fld = reg >> SYS_PMBIDR_EL1_ALIGN_SHIFT & SYS_PMBIDR_EL1_ALIGN_MASK; + fld = (reg & PMBIDR_EL1_ALIGN_MASK) >> PMBIDR_EL1_ALIGN_SHIFT; spe_pmu->align = 1 << fld; if (spe_pmu->align > SZ_2K) { dev_err(dev, "unsupported PMBIDR.Align [%d] on CPU %d\n", @@ -988,26 +987,26 @@ static void __arm_spe_pmu_dev_probe(void *info) /* It's now safe to read PMSIDR and figure out what we've got */ reg = read_sysreg_s(SYS_PMSIDR_EL1); - if (reg & BIT(SYS_PMSIDR_EL1_FE_SHIFT)) + if (reg & BIT(PMSIDR_EL1_FE_SHIFT)) spe_pmu->features |= SPE_PMU_FEAT_FILT_EVT; - if (reg & BIT(SYS_PMSIDR_EL1_FT_SHIFT)) + if (reg & BIT(PMSIDR_EL1_FT_SHIFT)) spe_pmu->features |= SPE_PMU_FEAT_FILT_TYP; - if (reg & BIT(SYS_PMSIDR_EL1_FL_SHIFT)) + if (reg & BIT(PMSIDR_EL1_FL_SHIFT)) spe_pmu->features |= SPE_PMU_FEAT_FILT_LAT; - if (reg & BIT(SYS_PMSIDR_EL1_ARCHINST_SHIFT)) + if (reg & BIT(PMSIDR_EL1_ARCHINST_SHIFT)) spe_pmu->features |= SPE_PMU_FEAT_ARCH_INST; - if (reg & BIT(SYS_PMSIDR_EL1_LDS_SHIFT)) + if (reg & BIT(PMSIDR_EL1_LDS_SHIFT)) spe_pmu->features |= SPE_PMU_FEAT_LDS; - if (reg & BIT(SYS_PMSIDR_EL1_ERND_SHIFT)) + if (reg & BIT(PMSIDR_EL1_ERND_SHIFT)) spe_pmu->features |= SPE_PMU_FEAT_ERND; /* This field has a spaced out encoding, so just use a look-up */ - fld = reg >> SYS_PMSIDR_EL1_INTERVAL_SHIFT & SYS_PMSIDR_EL1_INTERVAL_MASK; + fld = (reg & PMSIDR_EL1_INTERVAL_MASK) >> PMSIDR_EL1_INTERVAL_SHIFT; switch (fld) { case 0: spe_pmu->min_period = 256; @@ -1039,7 +1038,7 @@ static void __arm_spe_pmu_dev_probe(void *info) } /* Maximum record size. If it's out-of-range, then fail the probe */ - fld = reg >> SYS_PMSIDR_EL1_MAXSIZE_SHIFT & SYS_PMSIDR_EL1_MAXSIZE_MASK; + fld = (reg & PMSIDR_EL1_MAXSIZE_MASK) >> PMSIDR_EL1_MAXSIZE_SHIFT; spe_pmu->max_record_sz = 1 << fld; if (spe_pmu->max_record_sz > SZ_2K || spe_pmu->max_record_sz < 16) { dev_err(dev, "unsupported PMSIDR_EL1.MaxSize [%d] on CPU %d\n", @@ -1047,7 +1046,7 @@ static void __arm_spe_pmu_dev_probe(void *info) return; } - fld = reg >> SYS_PMSIDR_EL1_COUNTSIZE_SHIFT & SYS_PMSIDR_EL1_COUNTSIZE_MASK; + fld = (reg & PMSIDR_EL1_COUNTSIZE_MASK) >> PMSIDR_EL1_COUNTSIZE_SHIFT; switch (fld) { default: dev_warn(dev, "unknown PMSIDR_EL1.CountSize [%d]; assuming 2\n", From patchwork Wed Oct 19 19:11:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 5814 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp492437wrs; Wed, 19 Oct 2022 12:14:28 -0700 (PDT) X-Google-Smtp-Source: AMsMyM7zJFdlinW+WUf52C7v3ikip4c3BrbU9H0BwbJptEbatFwqjBAUablvjcbwCQGa8g3KU6u2 X-Received: by 2002:a05:6a00:4093:b0:563:2d96:8f44 with SMTP id bw19-20020a056a00409300b005632d968f44mr10004824pfb.4.1666206868407; Wed, 19 Oct 2022 12:14:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666206868; cv=none; d=google.com; s=arc-20160816; b=d4Hf53KO6DWl5fgm9HEmozwAirMC414CZvE9Qi4YyWrNLzil89RrB/P2ShYetn883w qAPcLGb5StCiWRboil4tcyMKUEDodr/GSXfskMCi/h04CFFT6vPZueoI5i8DEqQN5PbX b7s7DwPI/4TxH1h42zT0YvwQC881yb8oLGRmuxufaKq6sKdFZ0R5RCVVQTL04ztjgCSi H94v48QomGKrcuWU7Xh51rCg3OVsmh+pRCInfUSjF8Fq+rXqNs3jdgAOt6wsYkPF/dVY TK+wJDrNaIh72V1QSm6qh1LIxVJzG6XkovnCgbKopaHK5xkiAZ/uXakSvM030PK5Ppka m35A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from; bh=mQp/SgU2k3oDYw9yCnKZ2Ab4A7I/j7N7D9SRUWxHwOE=; b=O1ue4DWY6fxUrmVpdZo/k3ZBMcnyKie3nnKMSK90S0TDjd1/O9cFS8Gk6AOxhvap1w lKzpRzLt3RLLTFBUFp5m0LQTVDTRD159Mo+0o3LwEx3yv3amJQ6VMr0Fz4PxC8he+zV0 NmJYKvptMecuwASlEwcj3CfBfszGV+9PT+eRk83367CTOtSTj9N6dq4MIwCIorKtO2cB TwVaD/sO7KJpoSffvDKteydTUzoqs6VGPiAkHOr4TSrYGRQ5PlkeGBfQtO6KScUkDFlN 8AUZSxKE/v2x4I/KIHnAL0pPZ2c5U4gGK7l7N0SFMLmVaPvBB3G4fh2d74FjgiIm0IUa eCOQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (out1.vger.email. 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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id h7-20020a9d61c7000000b00661c3846b4csm7429899otk.27.2022.10.19.12.11.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Oct 2022 12:11:26 -0700 (PDT) Received: (nullmailer pid 3420902 invoked by uid 1000); Wed, 19 Oct 2022 19:11:25 -0000 From: Rob Herring Date: Wed, 19 Oct 2022 14:11:26 -0500 Subject: [PATCH v2 3/7] arm64/sysreg: Convert SPE registers to automatic generation MIME-Version: 1.0 Message-Id: <20220825-arm-spe-v8-7-v2-3-e37322d68ac0@kernel.org> References: <20220825-arm-spe-v8-7-v2-0-e37322d68ac0@kernel.org> In-Reply-To: <20220825-arm-spe-v8-7-v2-0-e37322d68ac0@kernel.org> To: Namhyung Kim , James Morse , Ingo Molnar , Mark Rutland , Marc Zyngier , Suzuki K Poulose , Will Deacon , Alexandru Elisei , Catalin Marinas , Arnaldo Carvalho de Melo , Peter Zijlstra , Alexander Shishkin , Oliver Upton , Jiri Olsa Cc: kvmarm@lists.cs.columbia.edu, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.11.0-dev X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00, FREEMAIL_ENVFROM_END_DIGIT,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747144533089114233?= X-GMAIL-MSGID: =?utf-8?q?1747144533089114233?= Convert all the SPE register defines to automatic generation. No functional changes. New registers and fields for SPEv1.2 are added with the conversion. Some of the PMBSR MSS field defines are kept as the automatic generation has no way to create multiple names for the same register bits. The meaning of the MSS field depends on other bits. Signed-off-by: Rob Herring --- v2: - New patch --- arch/arm64/include/asm/sysreg.h | 91 ++----------------------------- arch/arm64/tools/sysreg | 116 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 121 insertions(+), 86 deletions(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 8df8a0a51273..d002dd00e53e 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -237,99 +237,18 @@ #define SYS_PAR_EL1_FST GENMASK(6, 1) /*** Statistical Profiling Extension ***/ -/* ID registers */ -#define SYS_PMSIDR_EL1 sys_reg(3, 0, 9, 9, 7) -#define PMSIDR_EL1_FE_SHIFT 0 -#define PMSIDR_EL1_FT_SHIFT 1 -#define PMSIDR_EL1_FL_SHIFT 2 -#define PMSIDR_EL1_ARCHINST_SHIFT 3 -#define PMSIDR_EL1_LDS_SHIFT 4 -#define PMSIDR_EL1_ERND_SHIFT 5 -#define PMSIDR_EL1_INTERVAL_SHIFT 8 -#define PMSIDR_EL1_INTERVAL_MASK GENMASK_ULL(11, 8) -#define PMSIDR_EL1_MAXSIZE_SHIFT 12 -#define PMSIDR_EL1_MAXSIZE_MASK GENMASK_ULL(15, 12) -#define PMSIDR_EL1_COUNTSIZE_SHIFT 16 -#define PMSIDR_EL1_COUNTSIZE_MASK GENMASK_ULL(19, 16) - -#define SYS_PMBIDR_EL1 sys_reg(3, 0, 9, 10, 7) -#define PMBIDR_EL1_ALIGN_SHIFT 0 -#define PMBIDR_EL1_ALIGN_MASK 0xfU -#define PMBIDR_EL1_P_SHIFT 4 -#define PMBIDR_EL1_F_SHIFT 5 - -/* Sampling controls */ -#define SYS_PMSCR_EL1 sys_reg(3, 0, 9, 9, 0) -#define PMSCR_EL1_E0SPE_SHIFT 0 -#define PMSCR_EL1_E1SPE_SHIFT 1 -#define PMSCR_EL1_CX_SHIFT 3 -#define PMSCR_EL1_PA_SHIFT 4 -#define PMSCR_EL1_TS_SHIFT 5 -#define PMSCR_EL1_PCT_SHIFT 6 - -#define SYS_PMSCR_EL2 sys_reg(3, 4, 9, 9, 0) -#define PMSCR_EL2_E0HSPE_SHIFT 0 -#define PMSCR_EL2_E2SPE_SHIFT 1 -#define PMSCR_EL2_CX_SHIFT 3 -#define PMSCR_EL2_PA_SHIFT 4 -#define PMSCR_EL2_TS_SHIFT 5 -#define PMSCR_EL2_PCT_SHIFT 6 - -#define SYS_PMSICR_EL1 sys_reg(3, 0, 9, 9, 2) - -#define SYS_PMSIRR_EL1 sys_reg(3, 0, 9, 9, 3) -#define PMSIRR_EL1_RND_SHIFT 0 -#define PMSIRR_EL1_INTERVAL_SHIFT 8 -#define PMSIRR_EL1_INTERVAL_MASK GENMASK_ULL(31, 8) - -/* Filtering controls */ -#define SYS_PMSNEVFR_EL1 sys_reg(3, 0, 9, 9, 1) - -#define SYS_PMSFCR_EL1 sys_reg(3, 0, 9, 9, 4) -#define PMSFCR_EL1_FE_SHIFT 0 -#define PMSFCR_EL1_FT_SHIFT 1 -#define PMSFCR_EL1_FL_SHIFT 2 -#define PMSFCR_EL1_B_SHIFT 16 -#define PMSFCR_EL1_LD_SHIFT 17 -#define PMSFCR_EL1_ST_SHIFT 18 - -#define SYS_PMSEVFR_EL1 sys_reg(3, 0, 9, 9, 5) #define PMSEVFR_EL1_RES0_IMP \ (GENMASK_ULL(47, 32) | GENMASK_ULL(23, 16) | GENMASK_ULL(11, 8) |\ BIT_ULL(6) | BIT_ULL(4) | BIT_ULL(2) | BIT_ULL(0)) #define PMSEVFR_EL1_RES0_V1P1 \ (PMSEVFR_EL1_RES0_IMP & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11))) -#define SYS_PMSLATFR_EL1 sys_reg(3, 0, 9, 9, 6) -#define PMSLATFR_EL1_MINLAT_SHIFT 0 - -/* Buffer controls */ -#define SYS_PMBLIMITR_EL1 sys_reg(3, 0, 9, 10, 0) -#define PMBLIMITR_EL1_E_SHIFT 0 -#define PMBLIMITR_EL1_FM_SHIFT 1 -#define PMBLIMITR_EL1_FM_MASK GENMASK_ULL(2, 1) -#define PMBLIMITR_EL1_FM_STOP_IRQ 0 - -#define SYS_PMBPTR_EL1 sys_reg(3, 0, 9, 10, 1) - /* Buffer error reporting */ -#define SYS_PMBSR_EL1 sys_reg(3, 0, 9, 10, 3) -#define PMBSR_EL1_COLL_SHIFT 16 -#define PMBSR_EL1_S_SHIFT 17 -#define PMBSR_EL1_EA_SHIFT 18 -#define PMBSR_EL1_DL_SHIFT 19 -#define PMBSR_EL1_EC_SHIFT 26 -#define PMBSR_EL1_EC_MASK GENMASK_ULL(31, 26) - -#define PMBSR_EL1_EC_BUF 0x0UL -#define PMBSR_EL1_EC_FAULT_S1 0x24UL -#define PMBSR_EL1_EC_FAULT_S2 0x25UL - -#define PMBSR_EL1_FAULT_FSC_SHIFT 0 -#define PMBSR_EL1_FAULT_FSC_MASK 0x3fUL - -#define PMBSR_EL1_BUF_BSC_SHIFT 0 -#define PMBSR_EL1_BUF_BSC_MASK 0x3fUL +#define PMBSR_EL1_FAULT_FSC_SHIFT PMBSR_EL1_MSS_SHIFT +#define PMBSR_EL1_FAULT_FSC_MASK PMBSR_EL1_MSS_MASK + +#define PMBSR_EL1_BUF_BSC_SHIFT PMBSR_EL1_MSS_SHIFT +#define PMBSR_EL1_BUF_BSC_MASK PMBSR_EL1_MSS_MASK #define PMBSR_EL1_BUF_BSC_FULL 0x1UL diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 384757a7eda9..2fbfe625dacc 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -854,6 +854,111 @@ Sysreg FAR_EL1 3 0 6 0 0 Field 63:0 ADDR EndSysreg +Sysreg PMSCR_EL1 3 0 9 9 0 +Res0 63:8 +Field 7:6 PCT +Field 5 TS +Field 4 PA +Field 3 CX +Res0 2 +Field 1 E1SPE +Field 0 E0SPE +EndSysreg + +Sysreg PMSNEVFR_EL1 3 0 9 9 1 +Field 63:0 E +EndSysreg + +Sysreg PMSICR_EL1 3 0 9 9 2 +Field 63:56 ECOUNT +Res0 55:32 +Field 31:0 COUNT +EndSysreg + +Sysreg PMSIRR_EL1 3 0 9 9 3 +Res0 63:32 +Field 31:8 INTERVAL +Res0 7:1 +Field 0 RND +EndSysreg + +Sysreg PMSFCR_EL1 3 0 9 9 4 +Res0 63:19 +Field 18 ST +Field 17 LD +Field 16 B +Res0 15:4 +Field 3 FnE +Field 2 FL +Field 1 FT +Field 0 FE +EndSysreg + +Sysreg PMSEVFR_EL1 3 0 9 9 5 +Field 63:0 E +EndSysreg + +Sysreg PMSLATFR_EL1 3 0 9 9 6 +Res0 63:16 +Field 15:0 MINLAT +EndSysreg + +Sysreg PMSIDR_EL1 3 0 9 9 7 +Res0 63:25 +Field 24 PBT +Field 23:20 FORMAT +Field 19:16 COUNTSIZE +Field 15:12 MAXSIZE +Field 11:8 INTERVAL +Res0 7 +Field 6 FnE +Field 5 ERND +Field 4 LDS +Field 3 ARCHINST +Field 2 FL +Field 1 FT +Field 0 FE +EndSysreg + +Sysreg PMBLIMITR_EL1 3 0 9 10 0 +Field 63:12 LIMIT +Res0 11:6 +Field 5 PMFZ +Res0 4:3 +Enum 2:1 FM + 0b0000 STOP_IRQ +EndEnum +Field 0 E +EndSysreg + +Sysreg PMBPTR_EL1 3 0 9 10 1 +Field 63:0 PTR +EndSysreg + +Sysreg PMBSR_EL1 3 0 9 10 3 +Res0 63:32 +Enum 31:26 EC + 0b000000 BUF + 0b100100 FAULT_S1 + 0b100101 FAULT_S2 +EndEnum +Res0 25:20 +Field 19 DL +Field 18 EA +Field 17 S +Field 16 COLL +Field 15:0 MSS +EndSysreg + +Sysreg PMBIDR_EL1 3 0 9 10 7 +Res0 63:12 +Field 11:8 EA +Res0 7:6 +Field 5 F +Field 4 P +Field 3:0 ALIGN +EndSysreg + SysregFields CONTEXTIDR_ELx Res0 63:32 Field 31:0 PROCID @@ -1008,6 +1113,17 @@ Sysreg FAR_EL2 3 4 6 0 0 Field 63:0 ADDR EndSysreg +Sysreg PMSCR_EL2 3 4 9 9 0 +Res0 63:8 +Field 7:6 PCT +Field 5 TS +Field 4 PA +Field 3 CX +Res0 2 +Field 1 E2SPE +Field 0 E0HSPE +EndSysreg + Sysreg CONTEXTIDR_EL2 3 4 13 0 1 Fields CONTEXTIDR_ELx EndSysreg From patchwork Wed Oct 19 19:11:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 5819 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp493702wrs; Wed, 19 Oct 2022 12:17:15 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5zgn+Ai0ScyEj+3aZGMPS/i0SVVubaGbdvVhYsjvAkrA4jZcRXl21dwc9/TIRl/jSMlcTv X-Received: by 2002:a17:90b:4c04:b0:20d:4ef6:aacc with SMTP id na4-20020a17090b4c0400b0020d4ef6aaccmr47817344pjb.199.1666207035142; Wed, 19 Oct 2022 12:17:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666207035; cv=none; d=google.com; s=arc-20160816; b=cVrZpgDFBMQvXf8x8gDoleNdAd/1Z79Env3CIqkypU9WYohwtnuxO+BWr9R2RwRLRj Q0xIT2LUF7k3lbBYBAY2e6z7L+wg/TDq/ol83zx2aN7NE8JAAkR9jGyd62NRbndi2nbU Oix2uO7mL0DXudvYQqzfjMe4bPyAxI3Y1nnzrWQhqFlDsn2B79O6QLE9Ixi6z+vvO+RR MJ8elUQ1d/gFAoFKXRJRuDVDf7H/nsxJEkMs/HOq36xfKs3+FAOapVIoa1SYQ253oE3F 9p5QrBl5aMzN11RHOr3OqZuirl7wgXxvLz7Eh+3mfyLBKdpLLEc1hlh3yzJ6H6dueF+R HhMw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from; bh=1uHI8D71nZXIPql0Ea/USh9ISq5jM79VtrVQ2e/RcjE=; b=dfQoZkakDTEa7qB+GUWHg6R5M1JjbudtSWkiwksIHmENA4QMPR+K/Rxw0tvOErd215 PaRg4MpgwK8S0BsKuNJXUpPfxluo68qv0mu4ZQFNcx2wf5B9gnK7jHiv0K47Cob/VOS5 fmY9aPSgUY5yeEAxCIbqbAnKB7wLKb7bv0r0tSW/v5RRfBXqHtI7ShTtdpkSyF7igjFZ kq/9h98yGr37OscOIAKXebBbRyUy/VUFIZ3lrwqfNWAqRuVh3OpyC2iK2WS788x2adYZ c4GvkODukEo1d1sVQHmO5CjS5+Z4EsIXFBdfFPESAGOhCzcST8hyiZyihNiHzxrINYpZ gkTQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (out1.vger.email. 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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id 23-20020aca2117000000b00354efb5be11sm7001508oiz.15.2022.10.19.12.11.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Oct 2022 12:11:33 -0700 (PDT) Received: (nullmailer pid 3420904 invoked by uid 1000); Wed, 19 Oct 2022 19:11:25 -0000 From: Rob Herring Date: Wed, 19 Oct 2022 14:11:27 -0500 Subject: [PATCH v2 4/7] perf: arm_spe: Drop BIT() and use FIELD_GET/PREP accessors MIME-Version: 1.0 Message-Id: <20220825-arm-spe-v8-7-v2-4-e37322d68ac0@kernel.org> References: <20220825-arm-spe-v8-7-v2-0-e37322d68ac0@kernel.org> In-Reply-To: <20220825-arm-spe-v8-7-v2-0-e37322d68ac0@kernel.org> To: Namhyung Kim , James Morse , Ingo Molnar , Mark Rutland , Marc Zyngier , Suzuki K Poulose , Will Deacon , Alexandru Elisei , Catalin Marinas , Arnaldo Carvalho de Melo , Peter Zijlstra , Alexander Shishkin , Oliver Upton , Jiri Olsa Cc: kvmarm@lists.cs.columbia.edu, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.11.0-dev X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00, FREEMAIL_ENVFROM_END_DIGIT,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747144708131813317?= X-GMAIL-MSGID: =?utf-8?q?1747144708131813317?= Now that generated sysregs are in place, update the register field accesses. The use of BIT() is no longer needed with the new defines. Use FIELD_GET and FIELD_PREP instead of open coding masking and shifting. No functional change. Signed-off-by: Rob Herring --- drivers/perf/arm_spe_pmu.c | 70 ++++++++++++++++++++++------------------------ 1 file changed, 34 insertions(+), 36 deletions(-) diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c index 814ed18346b6..9b4bd72087ea 100644 --- a/drivers/perf/arm_spe_pmu.c +++ b/drivers/perf/arm_spe_pmu.c @@ -283,18 +283,18 @@ static u64 arm_spe_event_to_pmscr(struct perf_event *event) struct perf_event_attr *attr = &event->attr; u64 reg = 0; - reg |= ATTR_CFG_GET_FLD(attr, ts_enable) << PMSCR_EL1_TS_SHIFT; - reg |= ATTR_CFG_GET_FLD(attr, pa_enable) << PMSCR_EL1_PA_SHIFT; - reg |= ATTR_CFG_GET_FLD(attr, pct_enable) << PMSCR_EL1_PCT_SHIFT; + reg |= FIELD_PREP(PMSCR_EL1_TS, ATTR_CFG_GET_FLD(attr, ts_enable)); + reg |= FIELD_PREP(PMSCR_EL1_PA, ATTR_CFG_GET_FLD(attr, pa_enable)); + reg |= FIELD_PREP(PMSCR_EL1_PCT, ATTR_CFG_GET_FLD(attr, pct_enable)); if (!attr->exclude_user) - reg |= BIT(PMSCR_EL1_E0SPE_SHIFT); + reg |= PMSCR_EL1_E0SPE; if (!attr->exclude_kernel) - reg |= BIT(PMSCR_EL1_E1SPE_SHIFT); + reg |= PMSCR_EL1_E1SPE; if (get_spe_event_has_cx(event)) - reg |= BIT(PMSCR_EL1_CX_SHIFT); + reg |= PMSCR_EL1_CX; return reg; } @@ -322,7 +322,7 @@ static u64 arm_spe_event_to_pmsirr(struct perf_event *event) arm_spe_event_sanitise_period(event); - reg |= ATTR_CFG_GET_FLD(attr, jitter) << PMSIRR_EL1_RND_SHIFT; + reg |= FIELD_PREP(PMSIRR_EL1_RND, ATTR_CFG_GET_FLD(attr, jitter)); reg |= event->hw.sample_period; return reg; @@ -333,18 +333,18 @@ static u64 arm_spe_event_to_pmsfcr(struct perf_event *event) struct perf_event_attr *attr = &event->attr; u64 reg = 0; - reg |= ATTR_CFG_GET_FLD(attr, load_filter) << PMSFCR_EL1_LD_SHIFT; - reg |= ATTR_CFG_GET_FLD(attr, store_filter) << PMSFCR_EL1_ST_SHIFT; - reg |= ATTR_CFG_GET_FLD(attr, branch_filter) << PMSFCR_EL1_B_SHIFT; + reg |= FIELD_PREP(PMSFCR_EL1_LD, ATTR_CFG_GET_FLD(attr, load_filter)); + reg |= FIELD_PREP(PMSFCR_EL1_ST, ATTR_CFG_GET_FLD(attr, store_filter)); + reg |= FIELD_PREP(PMSFCR_EL1_B, ATTR_CFG_GET_FLD(attr, branch_filter)); if (reg) - reg |= BIT(PMSFCR_EL1_FT_SHIFT); + reg |= PMSFCR_EL1_FT; if (ATTR_CFG_GET_FLD(attr, event_filter)) - reg |= BIT(PMSFCR_EL1_FE_SHIFT); + reg |= PMSFCR_EL1_FE; if (ATTR_CFG_GET_FLD(attr, min_latency)) - reg |= BIT(PMSFCR_EL1_FL_SHIFT); + reg |= PMSFCR_EL1_FL; return reg; } @@ -358,8 +358,7 @@ static u64 arm_spe_event_to_pmsevfr(struct perf_event *event) static u64 arm_spe_event_to_pmslatfr(struct perf_event *event) { struct perf_event_attr *attr = &event->attr; - return ATTR_CFG_GET_FLD(attr, min_latency) - << PMSLATFR_EL1_MINLAT_SHIFT; + return FIELD_PREP(PMSLATFR_EL1_MINLAT, ATTR_CFG_GET_FLD(attr, min_latency)); } static void arm_spe_pmu_pad_buf(struct perf_output_handle *handle, int len) @@ -511,7 +510,7 @@ static void arm_spe_perf_aux_output_begin(struct perf_output_handle *handle, limit = buf->snapshot ? arm_spe_pmu_next_snapshot_off(handle) : arm_spe_pmu_next_off(handle); if (limit) - limit |= BIT(PMBLIMITR_EL1_E_SHIFT); + limit |= PMBLIMITR_EL1_E; limit += (u64)buf->base; base = (u64)buf->base + PERF_IDX2OFF(handle->head, buf); @@ -570,23 +569,23 @@ arm_spe_pmu_buf_get_fault_act(struct perf_output_handle *handle) /* Service required? */ pmbsr = read_sysreg_s(SYS_PMBSR_EL1); - if (!(pmbsr & BIT(PMBSR_EL1_S_SHIFT))) + if (!FIELD_GET(PMBSR_EL1_S, pmbsr)) return SPE_PMU_BUF_FAULT_ACT_SPURIOUS; /* * If we've lost data, disable profiling and also set the PARTIAL * flag to indicate that the last record is corrupted. */ - if (pmbsr & BIT(PMBSR_EL1_DL_SHIFT)) + if (FIELD_GET(PMBSR_EL1_DL, pmbsr)) perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED | PERF_AUX_FLAG_PARTIAL); /* Report collisions to userspace so that it can up the period */ - if (pmbsr & BIT(PMBSR_EL1_COLL_SHIFT)) + if (FIELD_GET(PMBSR_EL1_COLL, pmbsr)) perf_aux_output_flag(handle, PERF_AUX_FLAG_COLLISION); /* We only expect buffer management events */ - switch (FIELD_GET(PMBSR_EL1_EC_MASK, pmbsr)) { + switch (FIELD_GET(PMBSR_EL1_EC, pmbsr)) { case PMBSR_EL1_EC_BUF: /* Handled below */ break; @@ -716,23 +715,22 @@ static int arm_spe_pmu_event_init(struct perf_event *event) return -EINVAL; reg = arm_spe_event_to_pmsfcr(event); - if ((reg & BIT(PMSFCR_EL1_FE_SHIFT)) && + if ((FIELD_GET(PMSFCR_EL1_FE, reg)) && !(spe_pmu->features & SPE_PMU_FEAT_FILT_EVT)) return -EOPNOTSUPP; - if ((reg & BIT(PMSFCR_EL1_FT_SHIFT)) && + if ((FIELD_GET(PMSFCR_EL1_FT, reg)) && !(spe_pmu->features & SPE_PMU_FEAT_FILT_TYP)) return -EOPNOTSUPP; - if ((reg & BIT(PMSFCR_EL1_FL_SHIFT)) && + if ((FIELD_GET(PMSFCR_EL1_FL, reg)) && !(spe_pmu->features & SPE_PMU_FEAT_FILT_LAT)) return -EOPNOTSUPP; set_spe_event_has_cx(event); reg = arm_spe_event_to_pmscr(event); if (!perfmon_capable() && - (reg & (BIT(PMSCR_EL1_PA_SHIFT) | - BIT(PMSCR_EL1_PCT_SHIFT)))) + (reg & (PMSCR_EL1_PA | PMSCR_EL1_PCT))) return -EACCES; return 0; @@ -970,14 +968,14 @@ static void __arm_spe_pmu_dev_probe(void *info) /* Read PMBIDR first to determine whether or not we have access */ reg = read_sysreg_s(SYS_PMBIDR_EL1); - if (reg & BIT(PMBIDR_EL1_P_SHIFT)) { + if (FIELD_GET(PMBIDR_EL1_P, reg)) { dev_err(dev, "profiling buffer owned by higher exception level\n"); return; } /* Minimum alignment. If it's out-of-range, then fail the probe */ - fld = (reg & PMBIDR_EL1_ALIGN_MASK) >> PMBIDR_EL1_ALIGN_SHIFT; + fld = FIELD_GET(PMBIDR_EL1_ALIGN, reg); spe_pmu->align = 1 << fld; if (spe_pmu->align > SZ_2K) { dev_err(dev, "unsupported PMBIDR.Align [%d] on CPU %d\n", @@ -987,26 +985,26 @@ static void __arm_spe_pmu_dev_probe(void *info) /* It's now safe to read PMSIDR and figure out what we've got */ reg = read_sysreg_s(SYS_PMSIDR_EL1); - if (reg & BIT(PMSIDR_EL1_FE_SHIFT)) + if (FIELD_GET(PMSIDR_EL1_FE, reg)) spe_pmu->features |= SPE_PMU_FEAT_FILT_EVT; - if (reg & BIT(PMSIDR_EL1_FT_SHIFT)) + if (FIELD_GET(PMSIDR_EL1_FT, reg)) spe_pmu->features |= SPE_PMU_FEAT_FILT_TYP; - if (reg & BIT(PMSIDR_EL1_FL_SHIFT)) + if (FIELD_GET(PMSIDR_EL1_FL, reg)) spe_pmu->features |= SPE_PMU_FEAT_FILT_LAT; - if (reg & BIT(PMSIDR_EL1_ARCHINST_SHIFT)) + if (FIELD_GET(PMSIDR_EL1_ARCHINST, reg)) spe_pmu->features |= SPE_PMU_FEAT_ARCH_INST; - if (reg & BIT(PMSIDR_EL1_LDS_SHIFT)) + if (FIELD_GET(PMSIDR_EL1_LDS, reg)) spe_pmu->features |= SPE_PMU_FEAT_LDS; - if (reg & BIT(PMSIDR_EL1_ERND_SHIFT)) + if (FIELD_GET(PMSIDR_EL1_ERND, reg)) spe_pmu->features |= SPE_PMU_FEAT_ERND; /* This field has a spaced out encoding, so just use a look-up */ - fld = (reg & PMSIDR_EL1_INTERVAL_MASK) >> PMSIDR_EL1_INTERVAL_SHIFT; + fld = FIELD_GET(PMSIDR_EL1_INTERVAL, reg); switch (fld) { case 0: spe_pmu->min_period = 256; @@ -1038,7 +1036,7 @@ static void __arm_spe_pmu_dev_probe(void *info) } /* Maximum record size. If it's out-of-range, then fail the probe */ - fld = (reg & PMSIDR_EL1_MAXSIZE_MASK) >> PMSIDR_EL1_MAXSIZE_SHIFT; + fld = FIELD_GET(PMSIDR_EL1_MAXSIZE, reg); spe_pmu->max_record_sz = 1 << fld; if (spe_pmu->max_record_sz > SZ_2K || spe_pmu->max_record_sz < 16) { dev_err(dev, "unsupported PMSIDR_EL1.MaxSize [%d] on CPU %d\n", @@ -1046,7 +1044,7 @@ static void __arm_spe_pmu_dev_probe(void *info) return; } - fld = (reg & PMSIDR_EL1_COUNTSIZE_MASK) >> PMSIDR_EL1_COUNTSIZE_SHIFT; + fld = FIELD_GET(PMSIDR_EL1_COUNTSIZE, reg); switch (fld) { default: dev_warn(dev, "unknown PMSIDR_EL1.CountSize [%d]; assuming 2\n", From patchwork Wed Oct 19 19:11:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 5818 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp493563wrs; Wed, 19 Oct 2022 12:17:00 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5xZCykvN4KFUootI07ATDrNU+7DOLHdSxPqSMkEUd+PwiNmujdnPI03D4aXOgjrdW5An+k X-Received: by 2002:a17:90b:2241:b0:20d:b273:26af with SMTP id hk1-20020a17090b224100b0020db27326afmr11021304pjb.245.1666207019870; Wed, 19 Oct 2022 12:16:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666207019; cv=none; d=google.com; s=arc-20160816; b=au1ElieoUXPqLGHr2tSkTaN3DyB+ZOr0VLIFCBs4sD1m7fqgh8JVpeTLNbocb73H/p ZhZllVKonnwS6TU5Glk2LdnxD9pCHh37olMLL4E8g9Uamdu+pHemewomqap+/O1RZiK+ wtJpxZ11LG2GIX6UvLOFlDefEmJlipMy3OLMcftnmKecRgJtwNWiaAumE4I23MPAG342 A9xdlhzN3/RLjOUJGrXksYrPlPisGeRyLFdh37rL8lTeqx/53BqPddZv20fn2s8XdSWM xyTaCgKystApwAOuZQMIVL/+U1b+7UFIkONGK9uP2LbfTA2z1mqsaMyKP8rgUGGmNNiJ AhLg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from; bh=ZBd+XTJESJNOGYoq8Sf5QKUv5aLEk2PWt2aI7lcJy1Q=; b=fkgvhbpi35eUj7l2K4/icuLNHWaNKkkouTBQqg/KphghJ5d188vbNqiuNtO0H4XUse 7OQv0irqPbl70oMm0s/Y2dLCQKMAu5tkr7FTSyHlIWdwJz9p6sc+959S+ttG7rdt5Onn Sy7kKyxkbLE7rmPC8PI4ZkARvUYFXJwEcOIC6zRyFQD9dwKfCKqoDZSsHdUsD4fWCP4K A0KM4HKSIrzhquxJqJFQYrnZ8/DSoVa7TayHrCy3R+GSQZ07dHk1KOj+nbgYt8HZkv3C 7/t/CRwp5JGd0MXOGmL/384UpMEYnYfxtaPNVoBLXoCBul5Rd8+Rdt+E+sdA1yh0XZhC rLEw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (out1.vger.email. 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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id q78-20020a4a3351000000b00480db116926sm2048754ooq.27.2022.10.19.12.11.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Oct 2022 12:11:31 -0700 (PDT) Received: (nullmailer pid 3420906 invoked by uid 1000); Wed, 19 Oct 2022 19:11:25 -0000 From: Rob Herring Date: Wed, 19 Oct 2022 14:11:28 -0500 Subject: [PATCH v2 5/7] perf: arm_spe: Support new SPEv1.2/v8.7 'not taken' event MIME-Version: 1.0 Message-Id: <20220825-arm-spe-v8-7-v2-5-e37322d68ac0@kernel.org> References: <20220825-arm-spe-v8-7-v2-0-e37322d68ac0@kernel.org> In-Reply-To: <20220825-arm-spe-v8-7-v2-0-e37322d68ac0@kernel.org> To: Namhyung Kim , James Morse , Ingo Molnar , Mark Rutland , Marc Zyngier , Suzuki K Poulose , Will Deacon , Alexandru Elisei , Catalin Marinas , Arnaldo Carvalho de Melo , Peter Zijlstra , Alexander Shishkin , Oliver Upton , Jiri Olsa Cc: kvmarm@lists.cs.columbia.edu, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.11.0-dev X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00, FREEMAIL_ENVFROM_END_DIGIT,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2, SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747144691928616889?= X-GMAIL-MSGID: =?utf-8?q?1747144691928616889?= Arm SPEv1.2 (Armv8.7/v9.2) adds a new event, 'not taken', in bit 6 of the PMSEVFR_EL1 register. Update arm_spe_pmsevfr_res0() to support the additional event. Signed-off-by: Rob Herring --- v2: - Update for v6.1 sysreg generated header changes --- arch/arm64/include/asm/sysreg.h | 2 ++ drivers/perf/arm_spe_pmu.c | 4 +++- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index d002dd00e53e..06231e896832 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -242,6 +242,8 @@ BIT_ULL(6) | BIT_ULL(4) | BIT_ULL(2) | BIT_ULL(0)) #define PMSEVFR_EL1_RES0_V1P1 \ (PMSEVFR_EL1_RES0_IMP & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11))) +#define PMSEVFR_EL1_RES0_V1P2 \ + (PMSEVFR_EL1_RES0_V1P1 & ~BIT_ULL(6)) /* Buffer error reporting */ #define PMBSR_EL1_FAULT_FSC_SHIFT PMBSR_EL1_MSS_SHIFT diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c index 9b4bd72087ea..0b9b847919d0 100644 --- a/drivers/perf/arm_spe_pmu.c +++ b/drivers/perf/arm_spe_pmu.c @@ -677,9 +677,11 @@ static u64 arm_spe_pmsevfr_res0(u16 pmsver) case ID_AA64DFR0_EL1_PMSVer_IMP: return PMSEVFR_EL1_RES0_IMP; case ID_AA64DFR0_EL1_PMSVer_V1P1: + return PMSEVFR_EL1_RES0_V1P1; + case ID_AA64DFR0_EL1_PMSVer_V1P2: /* Return the highest version we support in default */ default: - return PMSEVFR_EL1_RES0_V1P1; + return PMSEVFR_EL1_RES0_V1P2; } } From patchwork Wed Oct 19 19:11:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 5815 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp492562wrs; Wed, 19 Oct 2022 12:14:47 -0700 (PDT) X-Google-Smtp-Source: AMsMyM57yke+L5YtkYE0VK3VCJelaBNx+rtAI/gdKyRt15hCB6+ckCx4i0eUJH9GJoxWUXBRaRML X-Received: by 2002:a17:902:cf08:b0:17d:46b6:25f9 with SMTP id i8-20020a170902cf0800b0017d46b625f9mr10003041plg.67.1666206876868; Wed, 19 Oct 2022 12:14:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666206876; cv=none; d=google.com; s=arc-20160816; b=c/82jRuqo2+lBzjyZccjnPA/8q9PyF6SN96Hf6ShLWot761R19O36QfKvPw347Hr1y jtHtW4TfJ+dDXF/1vGPyyLIQNXdthtodDEN5YPcTl3Zrk2LR9bl4woDz2+pvcnJihfpL m0BqgdjK4DZfGIHgvVVPeFKXwBbQOtFCHcdmezXnbeqKR6UtF7wciplza93+A8ADjepl Giuu3ZY4q4O1nL+httgaGIG54zOESNSnxJHIM5wlO1sF2QQgILa0nIjTyNa/FMNNPBzI F0K03lX8SxzAIyHEOmhklSql3j/Ea3Azg5D3DiaEKhKJweG8Koa45whdHF4iQdLvYXY6 Tu+Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from; bh=4nOSzjJQMiiQFtQCXOfHoj5W8uYrP30fMIHaTAT/kCc=; b=qKfZAyE4cmXQjhkKuuAX9J3uNsBFNg7l7XhMC28PYsBenvEdwfR4gk/hBOYc/41w+O LTTKNDgzy9kouVzvxOaHwgLpxG3OBRK9MqTnP6fvScvX2uHAt7YJ5tfMHFDeT8kGBXMP XGtudHB9xbNtYfgoOFwWcqDrG+lj/Miyf2b1lf9VUwiUvJmEcIOxs8TBmWiLquKND15f kOw15WvV0Q2uo1bZDQLhtWkyZSienK89G9IrY0n+ahfCLwuHu+TJte5FNztFtfASuBHR Jeaz+SpRar0jiZYq4Koo6CZd7V/vkW2wtQyn8bUA/BWin6UnHAcwm4lQ+03bVgMQiIpR w97Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (out1.vger.email. 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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id z9-20020a056870460900b0013191b00f72sm7878011oao.17.2022.10.19.12.11.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Oct 2022 12:11:28 -0700 (PDT) Received: (nullmailer pid 3420908 invoked by uid 1000); Wed, 19 Oct 2022 19:11:25 -0000 From: Rob Herring Date: Wed, 19 Oct 2022 14:11:29 -0500 Subject: [PATCH v2 6/7] perf: Add perf_event_attr::config3 MIME-Version: 1.0 Message-Id: <20220825-arm-spe-v8-7-v2-6-e37322d68ac0@kernel.org> References: <20220825-arm-spe-v8-7-v2-0-e37322d68ac0@kernel.org> In-Reply-To: <20220825-arm-spe-v8-7-v2-0-e37322d68ac0@kernel.org> To: Namhyung Kim , James Morse , Ingo Molnar , Mark Rutland , Marc Zyngier , Suzuki K Poulose , Will Deacon , Alexandru Elisei , Catalin Marinas , Arnaldo Carvalho de Melo , Peter Zijlstra , Alexander Shishkin , Oliver Upton , Jiri Olsa Cc: kvmarm@lists.cs.columbia.edu, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.11.0-dev X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00, FREEMAIL_ENVFROM_END_DIGIT,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2, SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747144542217421525?= X-GMAIL-MSGID: =?utf-8?q?1747144542217421525?= Arm SPEv1.2 adds another 64-bits of event filtering control. As the existing perf_event_attr::configN fields are all used up for SPE PMU, an additional field is needed. Add a new 'config3' field. Signed-off-by: Rob Herring --- v2: - Drop tools/ side update --- include/uapi/linux/perf_event.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h index 85be78e0e7f6..b2b1d7b54097 100644 --- a/include/uapi/linux/perf_event.h +++ b/include/uapi/linux/perf_event.h @@ -374,6 +374,7 @@ enum perf_event_read_format { #define PERF_ATTR_SIZE_VER5 112 /* add: aux_watermark */ #define PERF_ATTR_SIZE_VER6 120 /* add: aux_sample_size */ #define PERF_ATTR_SIZE_VER7 128 /* add: sig_data */ +#define PERF_ATTR_SIZE_VER8 136 /* add: config3 */ /* * Hardware event_id to monitor via a performance monitoring event: @@ -515,6 +516,8 @@ struct perf_event_attr { * truncated accordingly on 32 bit architectures. */ __u64 sig_data; + + __u64 config3; /* extension of config2 */ }; /* From patchwork Wed Oct 19 19:11:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 5817 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp492903wrs; Wed, 19 Oct 2022 12:15:35 -0700 (PDT) X-Google-Smtp-Source: AMsMyM76sjxP2eIay2bu+MeTOoYANpR/0VOf/pWSqqoHrbf/2q4z+lHPjBC4BkYTrLUpp8exyC+9 X-Received: by 2002:a17:90a:4fe4:b0:20a:629c:e854 with SMTP id q91-20020a17090a4fe400b0020a629ce854mr48406880pjh.30.1666206935137; Wed, 19 Oct 2022 12:15:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666206935; cv=none; d=google.com; s=arc-20160816; b=gVdnILXgGXBJqeUcsj+ERNf3+Zrsfi7L22uTOXbjWL5EBv9Phji/3g9EDvJpzfoesZ 3r2QCMpcJC11FX6oYivl5CW4S1yebQhyyLACKo2qs6xnf+pqZ7oIF1qFp1JhFAyE4u28 lIoGY65nyGYQk4EYOtrOFBof1C96Z0nzmcOjI5C/BVSMN/uCFmSFRwGgsZoPYPc6ywMO hUp9he6XIQmITutwn+YsxsB9WUeCKACcco9sHZuSgm1eLwevPb/te53TzCnzWu0iLXXa +WkhX2iCVyIDglpQGkq1DiyUXfh6zNrMuU+cjqmEjOo8T/utiS2dbswZFHa6MIXx72ir fRyA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from; bh=43IaqXn32YycCBd3/SGJ6Da4qva/kGDXqjobO4DMXeA=; b=bx1h10HMufY6YFW4e1CI08cIp48KAslbH1shmcNTXuR8kVlvFs8FW141NYmeajxN9D 6C9OdbKVD5uo5a9zUgRK7QHd3ileOYu1nYnW+uQNmUwB4L6QE9enwKoANBQQM0MWUpES LWVJTGjB4zhDjgA8RH7Ae9VmYcezXys+a4xasmmoBCoOudlrGB+fzyVWJHNyi95f/JSm UKaWllw0gbRbd0pR+GCxXErDcj5ei++PhIwpRVWqdnhnMDwCnSKxowhpJgcckGAWE0EW KeQHRQPfhUEWF2eTwh3S7BnTy2PQy+QqS4x6pZX/YU2tRy19FcBjn0bUycRPl2mdFTw1 9d2Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (out1.vger.email. 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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id q7-20020a4aac47000000b0047f8ceca22bsm6816526oon.15.2022.10.19.12.11.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Oct 2022 12:11:29 -0700 (PDT) Received: (nullmailer pid 3420910 invoked by uid 1000); Wed, 19 Oct 2022 19:11:25 -0000 From: Rob Herring Date: Wed, 19 Oct 2022 14:11:30 -0500 Subject: [PATCH v2 7/7] perf: arm_spe: Add support for SPEv1.2 inverted event filtering MIME-Version: 1.0 Message-Id: <20220825-arm-spe-v8-7-v2-7-e37322d68ac0@kernel.org> References: <20220825-arm-spe-v8-7-v2-0-e37322d68ac0@kernel.org> In-Reply-To: <20220825-arm-spe-v8-7-v2-0-e37322d68ac0@kernel.org> To: Namhyung Kim , James Morse , Ingo Molnar , Mark Rutland , Marc Zyngier , Suzuki K Poulose , Will Deacon , Alexandru Elisei , Catalin Marinas , Arnaldo Carvalho de Melo , Peter Zijlstra , Alexander Shishkin , Oliver Upton , Jiri Olsa Cc: kvmarm@lists.cs.columbia.edu, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.11.0-dev X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00, FREEMAIL_ENVFROM_END_DIGIT,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747144603403616134?= X-GMAIL-MSGID: =?utf-8?q?1747144603403616134?= Arm SPEv1.2 (Arm v8.7/v9.2) adds a new feature called Inverted Event Filter which excludes samples matching the event filter. The feature mirrors the existing event filter in PMSEVFR_EL1 adding a new register, PMSNEVFR_EL1, which has the same event bit assignments. Signed-off-by: Rob Herring --- v2: - Update for auto generated register defines - Avoid accessing SYS_PMSNEVFR_EL1 on < v8.7 --- drivers/perf/arm_spe_pmu.c | 45 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c index 0b9b847919d0..ab5fcf02a4ca 100644 --- a/drivers/perf/arm_spe_pmu.c +++ b/drivers/perf/arm_spe_pmu.c @@ -85,6 +85,7 @@ struct arm_spe_pmu { #define SPE_PMU_FEAT_ARCH_INST (1UL << 3) #define SPE_PMU_FEAT_LDS (1UL << 4) #define SPE_PMU_FEAT_ERND (1UL << 5) +#define SPE_PMU_FEAT_INV_FILT_EVT (1UL << 6) #define SPE_PMU_FEAT_DEV_PROBED (1UL << 63) u64 features; @@ -202,6 +203,10 @@ static const struct attribute_group arm_spe_pmu_cap_group = { #define ATTR_CFG_FLD_min_latency_LO 0 #define ATTR_CFG_FLD_min_latency_HI 11 +#define ATTR_CFG_FLD_inv_event_filter_CFG config3 /* PMSNEVFR_EL1 */ +#define ATTR_CFG_FLD_inv_event_filter_LO 0 +#define ATTR_CFG_FLD_inv_event_filter_HI 63 + /* Why does everything I do descend into this? */ #define __GEN_PMU_FORMAT_ATTR(cfg, lo, hi) \ (lo) == (hi) ? #cfg ":" #lo "\n" : #cfg ":" #lo "-" #hi @@ -232,6 +237,7 @@ GEN_PMU_FORMAT_ATTR(branch_filter); GEN_PMU_FORMAT_ATTR(load_filter); GEN_PMU_FORMAT_ATTR(store_filter); GEN_PMU_FORMAT_ATTR(event_filter); +GEN_PMU_FORMAT_ATTR(inv_event_filter); GEN_PMU_FORMAT_ATTR(min_latency); static struct attribute *arm_spe_pmu_formats_attr[] = { @@ -243,12 +249,27 @@ static struct attribute *arm_spe_pmu_formats_attr[] = { &format_attr_load_filter.attr, &format_attr_store_filter.attr, &format_attr_event_filter.attr, + &format_attr_inv_event_filter.attr, &format_attr_min_latency.attr, NULL, }; +static umode_t arm_spe_pmu_format_attr_is_visible(struct kobject *kobj, + struct attribute *attr, + int unused) + { + struct device *dev = kobj_to_dev(kobj); + struct arm_spe_pmu *spe_pmu = dev_get_drvdata(dev); + + if (attr == &format_attr_inv_event_filter.attr && !(spe_pmu->features & SPE_PMU_FEAT_INV_FILT_EVT)) + return 0; + + return attr->mode; +} + static const struct attribute_group arm_spe_pmu_format_group = { .name = "format", + .is_visible = arm_spe_pmu_format_attr_is_visible, .attrs = arm_spe_pmu_formats_attr, }; @@ -343,6 +364,9 @@ static u64 arm_spe_event_to_pmsfcr(struct perf_event *event) if (ATTR_CFG_GET_FLD(attr, event_filter)) reg |= PMSFCR_EL1_FE; + if (ATTR_CFG_GET_FLD(attr, inv_event_filter)) + reg |= PMSFCR_EL1_FnE; + if (ATTR_CFG_GET_FLD(attr, min_latency)) reg |= PMSFCR_EL1_FL; @@ -355,6 +379,12 @@ static u64 arm_spe_event_to_pmsevfr(struct perf_event *event) return ATTR_CFG_GET_FLD(attr, event_filter); } +static u64 arm_spe_event_to_pmsnevfr(struct perf_event *event) +{ + struct perf_event_attr *attr = &event->attr; + return ATTR_CFG_GET_FLD(attr, inv_event_filter); +} + static u64 arm_spe_event_to_pmslatfr(struct perf_event *event) { struct perf_event_attr *attr = &event->attr; @@ -703,6 +733,9 @@ static int arm_spe_pmu_event_init(struct perf_event *event) if (arm_spe_event_to_pmsevfr(event) & arm_spe_pmsevfr_res0(spe_pmu->pmsver)) return -EOPNOTSUPP; + if (arm_spe_event_to_pmsnevfr(event) & arm_spe_pmsevfr_res0(spe_pmu->pmsver)) + return -EOPNOTSUPP; + if (attr->exclude_idle) return -EOPNOTSUPP; @@ -721,6 +754,10 @@ static int arm_spe_pmu_event_init(struct perf_event *event) !(spe_pmu->features & SPE_PMU_FEAT_FILT_EVT)) return -EOPNOTSUPP; + if ((FIELD_GET(PMSFCR_EL1_FnE, reg)) && + !(spe_pmu->features & SPE_PMU_FEAT_INV_FILT_EVT)) + return -EOPNOTSUPP; + if ((FIELD_GET(PMSFCR_EL1_FT, reg)) && !(spe_pmu->features & SPE_PMU_FEAT_FILT_TYP)) return -EOPNOTSUPP; @@ -756,6 +793,11 @@ static void arm_spe_pmu_start(struct perf_event *event, int flags) reg = arm_spe_event_to_pmsevfr(event); write_sysreg_s(reg, SYS_PMSEVFR_EL1); + if (spe_pmu->features & SPE_PMU_FEAT_INV_FILT_EVT) { + reg = arm_spe_event_to_pmsnevfr(event); + write_sysreg_s(reg, SYS_PMSNEVFR_EL1); + } + reg = arm_spe_event_to_pmslatfr(event); write_sysreg_s(reg, SYS_PMSLATFR_EL1); @@ -990,6 +1032,9 @@ static void __arm_spe_pmu_dev_probe(void *info) if (FIELD_GET(PMSIDR_EL1_FE, reg)) spe_pmu->features |= SPE_PMU_FEAT_FILT_EVT; + if (FIELD_GET(PMSIDR_EL1_FnE, reg)) + spe_pmu->features |= SPE_PMU_FEAT_INV_FILT_EVT; + if (FIELD_GET(PMSIDR_EL1_FT, reg)) spe_pmu->features |= SPE_PMU_FEAT_FILT_TYP;