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Mon, 20 Mar 2023 05:03:24 -0500 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB05.amd.com (10.181.40.146) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Mon, 20 Mar 2023 05:03:09 -0500 Received: from xhdlakshmis40.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2375.34 via Frontend Transport; Mon, 20 Mar 2023 05:03:07 -0500 From: Sai Krishna Potthuri To: Mark Brown CC: , , , , Sai Krishna Potthuri Subject: [PATCH 1/2] spi: cadence-quadspi: Update the read timeout based on the length Date: Mon, 20 Mar 2023 15:29:30 +0530 Message-ID: <20230320095931.2651714-2-sai.krishna.potthuri@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230320095931.2651714-1-sai.krishna.potthuri@amd.com> References: <20230320095931.2651714-1-sai.krishna.potthuri@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT056:EE_|PH7PR12MB6465:EE_ X-MS-Office365-Filtering-Correlation-Id: 7e81110b-f3b0-4bca-f6ea-08db292a5aa0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Mar 2023 10:03:28.7514 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7e81110b-f3b0-4bca-f6ea-08db292a5aa0 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT056.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6465 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1760882221382083300?= X-GMAIL-MSGID: =?utf-8?q?1760882221382083300?= When performing indirect read via external DMA the timeout for completion is set equal to the read length instead of fixed timeout value. For reads larger than 500 bytes, the timeout will continue to be equal to the read length whereas for a small read like the Read Status Register command, the timeout would be 1 or 2 milliseconds. This is not enough to cover the overhead needed in setting up DMA, in that case make sure the timeout is at least 500ms to allow DMA to finish. This solution is inline with the timeout used for Direct read via DMA. Signed-off-by: Sai Krishna Potthuri --- drivers/spi/spi-cadence-quadspi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index 79ab7e309644..e281732aba91 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -863,7 +863,7 @@ static int cqspi_versal_indirect_read_dma(struct cqspi_flash_pdata *f_pdata, reinit_completion(&cqspi->transfer_complete); if (!wait_for_completion_timeout(&cqspi->transfer_complete, - msecs_to_jiffies(CQSPI_READ_TIMEOUT_MS))) { + msecs_to_jiffies(max_t(size_t, bytes_to_dma, 500)))) { ret = -ETIMEDOUT; goto failrd; } From patchwork Mon Mar 20 09:59:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sai Krishna Potthuri X-Patchwork-Id: 72063 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:604a:0:0:0:0:0 with SMTP id j10csp1125335wrt; Mon, 20 Mar 2023 03:08:04 -0700 (PDT) X-Google-Smtp-Source: AK7set/LGeCWDBqhpDjNfvmCoLvNFgyyH9Nht4zoGksOTkt3bTEAEVRiQkF3QmmmbEW0dy1PsSI6 X-Received: by 2002:a17:90a:31a:b0:23d:a2a:3ae4 with SMTP id 26-20020a17090a031a00b0023d0a2a3ae4mr19079458pje.44.1679306884417; Mon, 20 Mar 2023 03:08:04 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1679306884; cv=pass; d=google.com; s=arc-20160816; b=uGGhb1GMU10seiqYJfRSI61eWQ+UhqEA3u8y/vegtjjUUvQfYIxw0HH4VKvFmdhYDx hK8IIz300WKg+Km+wKfAZV3gTQXCfW1bau/Gf8Xafj7R8wExMPWsg08NyrN0A8jEtqin 1wOxh3gzVOaRwW+ZPcle9p56ynBSog5HsuFC4wf5InzXZjTIIUfmSpGvM3lFSaUCk5W3 kb4ecQh24PKrdJMAzin3EWlD5lR10k6OyN/Xpcf8Wl5PQdh4YWHyqCUvxwQK+7/wOTrC UbiEoRA8yUjqNW/038MRV/U3zJpr6VL6WQgfUpfayZw/EYIWIw7f1+ixzAk6eyu9CYRr j2Sg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ymbBBZqqJ4+gZVusIXMgD3b2TsKXYiOfyYewbaL57fY=; b=Rq+S2W9pk7R9BOYqyOeXZkqR+qjRprFNoc88bkxI8iMBil9TKVBo97JvJx1EQIrIRu ZCLaXj/fMAAXSvPbYUipXwnSVXqT+nAiSCrxwyh9BQzzj9XF1RXoLNgGCjT1zn+QI4eM 5VI5K81cWJx6MMO+wzluztixy4nMKSJbEbcacdvv2egqBe9q8KdbMO7rUbAH2ZbQzO0+ WDXbOazXYDcXimJjkYrV5RM00PeAkTYRODJgIw5pVoim8ksFjPo2o11qN8u8vrn0bvrc AGpRQoSdD62cXHViD6SSUvmGhwoTmd/R+oD1M0WcOQw3jGaLT1hBM6ipii2tbnXS6ed2 /lLA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=5LmMlo9z; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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Mon, 20 Mar 2023 05:03:25 -0500 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB05.amd.com (10.181.40.146) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Mon, 20 Mar 2023 05:03:11 -0500 Received: from xhdlakshmis40.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2375.34 via Frontend Transport; Mon, 20 Mar 2023 05:03:09 -0500 From: Sai Krishna Potthuri To: Mark Brown CC: , , , , Sai Krishna Potthuri Subject: [PATCH 2/2] spi: cadence-quadspi: Disable the SPI before reconfiguring Date: Mon, 20 Mar 2023 15:29:31 +0530 Message-ID: <20230320095931.2651714-3-sai.krishna.potthuri@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230320095931.2651714-1-sai.krishna.potthuri@amd.com> References: <20230320095931.2651714-1-sai.krishna.potthuri@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT078:EE_|SJ0PR12MB5405:EE_ X-MS-Office365-Filtering-Correlation-Id: c77c9134-e28f-4ffe-3565-08db292a5b82 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Mar 2023 10:03:30.1963 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c77c9134-e28f-4ffe-3565-08db292a5b82 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT078.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB5405 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1760880895610494053?= X-GMAIL-MSGID: =?utf-8?q?1760880895610494053?= Observed random DMA timeout failures while doing back to back transfers which involves switching the modes from DMA to NON-DMA. This issue is observed while testing the OSPI+UBIFS file system test case where rootfs is mounted from OSPI UBIFS partition. To avoid this issue, disable the SPI before changing the configuration from external DMA to NON-DMA and vice versa and reenable it after changing the configuration. As per the Cadence Octal SPI design specification, it is recommended to disable the Octal-SPI enable bit before reconfiguring. Signed-off-by: Sai Krishna Potthuri --- drivers/spi/spi-cadence-quadspi.c | 38 +++++++++++++++++++------------ 1 file changed, 23 insertions(+), 15 deletions(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index e281732aba91..d4a2b72985da 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -791,6 +791,21 @@ static int cqspi_indirect_read_execute(struct cqspi_flash_pdata *f_pdata, return ret; } +static void cqspi_controller_enable(struct cqspi_st *cqspi, bool enable) +{ + void __iomem *reg_base = cqspi->iobase; + unsigned int reg; + + reg = readl(reg_base + CQSPI_REG_CONFIG); + + if (enable) + reg |= CQSPI_REG_CONFIG_ENABLE_MASK; + else + reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK; + + writel(reg, reg_base + CQSPI_REG_CONFIG); +} + static int cqspi_versal_indirect_read_dma(struct cqspi_flash_pdata *f_pdata, u_char *rxbuf, loff_t from_addr, size_t n_rx) @@ -815,10 +830,14 @@ static int cqspi_versal_indirect_read_dma(struct cqspi_flash_pdata *f_pdata, if (ret) return ret; + cqspi_controller_enable(cqspi, 0); + reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); reg |= CQSPI_REG_CONFIG_DMA_MASK; writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); + cqspi_controller_enable(cqspi, 1); + dma_addr = dma_map_single(dev, rxbuf, bytes_to_dma, DMA_FROM_DEVICE); if (dma_mapping_error(dev, dma_addr)) { dev_err(dev, "dma mapping failed\n"); @@ -876,10 +895,14 @@ static int cqspi_versal_indirect_read_dma(struct cqspi_flash_pdata *f_pdata, cqspi->iobase + CQSPI_REG_INDIRECTRD); dma_unmap_single(dev, dma_addr, bytes_to_dma, DMA_FROM_DEVICE); + cqspi_controller_enable(cqspi, 0); + reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); reg &= ~CQSPI_REG_CONFIG_DMA_MASK; writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); + cqspi_controller_enable(cqspi, 1); + ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, PM_OSPI_MUX_SEL_LINEAR); if (ret) @@ -1182,21 +1205,6 @@ static void cqspi_readdata_capture(struct cqspi_st *cqspi, writel(reg, reg_base + CQSPI_REG_READCAPTURE); } -static void cqspi_controller_enable(struct cqspi_st *cqspi, bool enable) -{ - void __iomem *reg_base = cqspi->iobase; - unsigned int reg; - - reg = readl(reg_base + CQSPI_REG_CONFIG); - - if (enable) - reg |= CQSPI_REG_CONFIG_ENABLE_MASK; - else - reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK; - - writel(reg, reg_base + CQSPI_REG_CONFIG); -} - static void cqspi_configure(struct cqspi_flash_pdata *f_pdata, unsigned long sclk) {