From patchwork Wed Oct 19 17:06:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 5767 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp441112wrs; Wed, 19 Oct 2022 10:14:20 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5thWfkmtJqijtZgZuel0Vbi7/2qbGzuK77bWzVZknPwwuyhPjvLadY9lRRgYwYtH7jlT+G X-Received: by 2002:a17:90a:b118:b0:20d:65f4:fde9 with SMTP id z24-20020a17090ab11800b0020d65f4fde9mr44768846pjq.184.1666199649937; Wed, 19 Oct 2022 10:14:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666199649; cv=none; d=google.com; s=arc-20160816; b=Osauq6lnoxYtbPO8jdhoEUredFN0b6DnRfUp3y6brzOlkaYJasIaPd+S7UbOmfD/GW IotgTmWZsRgSYzQLxmlYmOZBZ2FBcMBFYv5E9gAhncrpCS4dEuyVoCnY7c5Py1E1B3il DX81heDABsiuNcu/brn4Q9UoZ6hXcPyp4Ifa34ia+a3FMe8Z+0LLuARElg0P63Vxy+Cn eA6e7qC/iDlnkIEQFURv8sAvAuO2d93G6aaocCVphVLWHcXCGHZXIaZx2I8g0qMraMCv t4RHZ0kUJLH9Z3K2U576aBtkLutJ6CczGuaOrLXD4/+1yWhO4muiR0eFLyuWh902qjqu xTbA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=HB56lgWxOFD+dVrosqnYTIwEIgr+1z8cJQuKzsAZp1k=; b=L2HJdzx887LXDCJUzvrecVVOby0Rzy52pPTk/6qnLkSJNRXqxrhw8Z8VBOiR3PEXyR uopr08A0f4Gf8pVeUqKuWC7HGdQvMjBXEzn9daY2GEjCJIQpo+5boSHssE4FdMYzwHUw b3v3YhAK9VYZKYMjHHnCvwoqlzu2DV8sQ6594VeTroQtHeF8ycjnR55pAjSl+pJc+FfA HRYQeiGhQA93Jx75srrqRvlCdct3tSd+Wnp19UBfMilDs0PeosTWCH4zHk+SOfA2IKS8 mPucVdVwV1nxYxpUJxGxxKeIqmd46BqGgTXw88Aa3FtC1fH8c8FznEzd+LzoAjQFk9mc h2ew== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=duAoc9H9; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id w184-20020a6282c1000000b00562e2899394si17080164pfd.310.2022.10.19.10.13.56; Wed, 19 Oct 2022 10:14:09 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=duAoc9H9; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231536AbiJSRHr (ORCPT + 99 others); Wed, 19 Oct 2022 13:07:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43002 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230469AbiJSRHj (ORCPT ); Wed, 19 Oct 2022 13:07:39 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 31DBF1BFBB7; Wed, 19 Oct 2022 10:07:39 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id D5737B82566; Wed, 19 Oct 2022 17:07:37 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 785C8C433D7; Wed, 19 Oct 2022 17:07:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1666199256; bh=Dk8qulf7jy4RWXliAjjhHRDUCVMa6Eye2Ux3gVAfoAY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=duAoc9H9OeX3W/6PGFEYsZT011cxJEKkxYnu1SMaRL3cH07K3KMnNZF0Z1+dokqeN EhBe0DTaRGyqE9oIJE82E4KnIWnhRlwwe0Gif6yOoyqTvRdrLjn6vRyXApie32+DgZ BkpPsjhJWb+iQ0ZhyZ5dYhE8EpYHDr6D+U4kHa+344RyxDeyy636ZRQgyLIzNQKFkv ugQppV8t6Uv5xKxqWX8E0cs/YcwMacVgCB2644k1YHsoYj7X/jX/nt2QWbk20kbKTO 6F1AyUCQVZomcwATxgMRj4I9WdxF4Dh4vEVYoNYSuAtedpk64cnEFdz228x3U8LXAC r7BUVzkBJyx3Q== From: Dinh Nguyen To: jh80.chung@samsung.com Cc: dinguyen@kernel.org, ulf.hansson@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCHv5 1/6] dt-bindings: mmc: synopsys-dw-mshc: document "altr,sysmgr-syscon" Date: Wed, 19 Oct 2022 12:06:52 -0500 Message-Id: <20221019170657.68014-2-dinguyen@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221019170657.68014-1-dinguyen@kernel.org> References: <20221019170657.68014-1-dinguyen@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747136964512184627?= X-GMAIL-MSGID: =?utf-8?q?1747136964512184627?= Document the optional "altr,sysmgr-syscon" binding that is used to access the System Manager register that controls the SDMMC clock phase. Signed-off-by: Dinh Nguyen Reviewed-by: Krzysztof Kozlowski --- v5: document reg shift v4: add else statement v3: document that the "altr,sysmgr-syscon" binding is only applicable to "altr,socfpga-dw-mshc" v2: document "altr,sysmgr-syscon" in the MMC section --- .../bindings/mmc/synopsys-dw-mshc.yaml | 32 +++++++++++++++++-- 1 file changed, 29 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml index ae6d6fca79e2..950fa6bd11fd 100644 --- a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml +++ b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml @@ -6,9 +6,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Synopsys Designware Mobile Storage Host Controller Binding -allOf: - - $ref: "synopsys-dw-mshc-common.yaml#" - maintainers: - Ulf Hansson @@ -38,6 +35,35 @@ properties: - const: biu - const: ciu + altr,sysmgr-syscon: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to the sysmgr node + - description: register offset that controls the SDMMC clock phase + - description: register shift for the smplsel(drive in) setting + description: + Contains the phandle to System Manager block that contains + the SDMMC clock-phase control register. The first value is the pointer + to the sysmgr, the 2nd value is the register offset for the SDMMC + clock phase register, and the 3rd value is the bit shift for the + smplsel(drive in) setting. + +allOf: + - $ref: "synopsys-dw-mshc-common.yaml#" + + - if: + properties: + compatible: + contains: + const: altr,socfpga-dw-mshc + then: + required: + - altr,sysmgr-syscon + else: + properties: + altr,sysmgr-syscon: false + required: - compatible - reg From patchwork Wed Oct 19 17:06:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 5765 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp440711wrs; Wed, 19 Oct 2022 10:13:38 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4i/0MoM517OirdCqOqAOGd7Y98Ty6pPT5jY4/eMfSbluxh3bJjJBgzPyIj6jtx/SrS9WJh X-Received: by 2002:a63:4949:0:b0:442:b733:2fae with SMTP id y9-20020a634949000000b00442b7332faemr7822734pgk.424.1666199618588; Wed, 19 Oct 2022 10:13:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666199618; cv=none; d=google.com; s=arc-20160816; b=CVzFEavgU8gdQlC8vaxBlSJFlSKPGoicVR5bMzMDYMkZ52AU+h11eZn8CRIokbu337 xc0RMtkxhW5lHilgmhctX1EgEDYnAiCx35Azo2G/2F2zcGlWpFKAlo7PMrpJOKIt6zzR DERrYhSH+oieMYNr+KEwEb2MA8vwZ4Tr2vK2jMaI7UkcEZ0ciQWxk7F/aDDclX3jjL9J Q6bYORc50sjHQxDEkRs7iLdZmkwxQDWDH9qS7kQkfZg5GlkrUpt/kL6+uEkfjceb9EwQ PSPEuunnzjPhd7D+6r013lXTQZmX/K3hdlS4hvXrGUTIZjKW0tZTRLyHvFtyKJTspmcC 4C9Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=6RRb7xUnFoMFJYi5aYJb3iIXdxt0cs6w9nFOzT4A5BI=; b=EHhPxXF6w0vvsyspmZzsJxH+8gnOTWv2S5b4UXE9omcsJyY9JBik9dqoNppcVxk/S6 zBvTKKYtKCiYXTfnZBfFm23MqDYVbgZjjn9ifbTmNkB8xlehl4Nz+O9IOaLGI4K7tYdx seT8Nj5pvT2eEfu1Xdnpvgcl6I3gZi1ZMIwZ/iMsOKgXceDOdSSHNdg1swgC0/GrYV9L ZaG9S9+qr8CIwYwxdRNO6rxGKhv7XA4xwOMwTLx5y0ZpBrOCl/cfEg3Xg7VKrvh8JhAg yFU7XTJs+uuBp23O/H9lnAJ/WvQC1ZBd4t7o60XAlFfISkvMZ3Pyo9GcQ+IZOiUV4Xai CDuA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=GbUdkRsy; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id s15-20020a170902ea0f00b0017f62505522si18354817plg.608.2022.10.19.10.13.25; Wed, 19 Oct 2022 10:13:38 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=GbUdkRsy; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231437AbiJSRHl (ORCPT + 99 others); Wed, 19 Oct 2022 13:07:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42946 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229784AbiJSRHj (ORCPT ); Wed, 19 Oct 2022 13:07:39 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 009EF1BFBA6; Wed, 19 Oct 2022 10:07:38 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 8F74E61978; Wed, 19 Oct 2022 17:07:38 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id DE236C43470; Wed, 19 Oct 2022 17:07:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1666199258; bh=XmJrrbSafjq8zQv0mI05L0CYiojcQ5ZabPJdPGIcFRU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GbUdkRsyHR330P3Tg2l1Tx1JW89l4TQl5CHywB8EFHFHIyI0ZZuf/IqXsPBXx9Gq/ z5H//ryh02h6qsWm3V1xSA4g00OOc+UIWkN4sjY7jXgKXTj9PZDwfhnzA3lfNloLN5 iwoIOVCufKf8NzUmvMRIc/WNY5BQnwh7bNu6x9NKqztZzOMFPxxzMgduG9biEgRqQq hLiJM6weUGjwOAHyZqruQkImqYLu2nPuvztRcNO/f2OXbcnyUybOShQuXHg0iY4M5f kKjh/pgb4HghVMDCgII7r1fgE0SwIDNvdWv5FEskyBFGn5KKwTtfRwT9qsfwIUPBWE EzVIKXsq5L9HQ== From: Dinh Nguyen To: jh80.chung@samsung.com Cc: dinguyen@kernel.org, ulf.hansson@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCHv5 2/6] arm64: dts: socfpga: Add clk-phase-sd-hs property to the sdmmc node Date: Wed, 19 Oct 2022 12:06:53 -0500 Message-Id: <20221019170657.68014-3-dinguyen@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221019170657.68014-1-dinguyen@kernel.org> References: <20221019170657.68014-1-dinguyen@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747136931454668466?= X-GMAIL-MSGID: =?utf-8?q?1747136931454668466?= The sdmmc controller's CIU(Card Interface Unit) clock's phase can be adjusted through the register in the system manager. Add the binding "altr,sysmgr-syscon" to the SDMMC node for the driver to access the system manager. Add the "clk-phase-sd-hs" property in the SDMMC node to designate the smpsel and drvsel properties for the CIU clock. Signed-off-by: Dinh Nguyen --- v5: add back reg_shift v4: no change v3: removed unnecessary property in "altr,sysmgr-syscon" --- arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 1 + arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts | 1 + arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 1 + arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts | 1 + arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts | 1 + 5 files changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi index 14c220d87807..55c5e1fdddc7 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi @@ -309,6 +309,7 @@ mmc: mmc@ff808000 { <&clkmgr STRATIX10_SDMMC_CLK>; clock-names = "biu", "ciu"; iommus = <&smmu 5>; + altr,sysmgr-syscon = <&sysmgr 0x28 4>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts index 48424e459f12..19e7284b4cd5 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts @@ -105,6 +105,7 @@ &mmc { cap-mmc-highspeed; broken-cd; bus-width = <4>; + clk-phase-sd-hs = <0>, <135>; }; &osc1 { diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi index 7bbec8aafa62..849b46dd8098 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi @@ -313,6 +313,7 @@ mmc: mmc@ff808000 { <&clkmgr AGILEX_SDMMC_CLK>; clock-names = "biu", "ciu"; iommus = <&smmu 5>; + altr,sysmgr-syscon = <&sysmgr 0x28 4>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts index 26cd3c121757..07c3f8876613 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts @@ -83,6 +83,7 @@ &mmc { cap-sd-highspeed; broken-cd; bus-width = <4>; + clk-phase-sd-hs = <0>, <135>; }; &osc1 { diff --git a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts index 62c66e52b656..08c088571270 100644 --- a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts @@ -74,6 +74,7 @@ &mmc { cap-sd-highspeed; broken-cd; bus-width = <4>; + clk-phase-sd-hs = <0>, <135>; }; &osc1 { From patchwork Wed Oct 19 17:06:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 5766 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp441047wrs; Wed, 19 Oct 2022 10:14:13 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6dx0bkmW1bY6JA82SbcuvfLkCtn7cjsAt1eMXDKTmUAulfMYhLEiBca/7DcAO/jaIj1L4y X-Received: by 2002:a17:903:32c2:b0:182:1a9c:8f40 with SMTP id i2-20020a17090332c200b001821a9c8f40mr9690476plr.54.1666199653437; Wed, 19 Oct 2022 10:14:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666199653; cv=none; d=google.com; s=arc-20160816; b=rCkecXN0f2Rk+J6gQOVYLK1ztOP5zTzllRvJnLnQ0qlaiVUNNn1Rz2Tscl+7WmKfjx d572eqVVdJHX8QdaO/AqXMhD7rHgzkbbVi13yho+3BBGHlCcb1TGPGhL33zfIo11MPGS p0PmlLLOn2l0S83bq6z9mRbBgJtYpyj7zk4zHJKdpXuGI0e/zwQTtPM7dCrFjTNAa7SF 1kdy3OcvyanhIMtANc+vwNGgdr4VmAJwzbohCRY9R43P3N10upP2xzNLqZlgHgoLYt1R mO9MQL1Y36OMmKAq+lWn2GvrcISuvRL+YtJ3pfFVlkTNMXq+AycXJtDGuUV0odUhXU6/ YkeA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=vflhom0SfcNC0+pECiwT/0CsiHqYgHQPFE4X4C9QfDA=; b=frBmuPNsy+FLFg0dkCLmIUYqnMFJCGjHSuic8Hv9P/JEhur9UqoP8t2J+T8msYGMWW 8kQcstHdy4n7FwXHBTgOC6fylH036hLRDljHniqnOGozexA8FFaakOKgr8iQK4r5gRnY ouNU2I1ZS7mktjqHC0qUnImE8dTUe2Ll5fi+RFojoGNXWTnkutuITN7yv8vX01bLwfSo fEIcZ7Bf2VEUFZe/Ts0wzLHs2Ds/mBiOwkaIXSZrBKD/1Ukmg/V6/2yorBHfl6Shz0bG qwOZwska3vA17qn9b3tB9qGlVnRfYEUQ/3oMZWqMaygfndW1qSYVuv3XUrUH66r077Zp bErA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=Oo5j4N13; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id v14-20020a63b64e000000b0043c05df34c0si19024928pgt.411.2022.10.19.10.14.00; Wed, 19 Oct 2022 10:14:13 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=Oo5j4N13; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230469AbiJSRHv (ORCPT + 99 others); Wed, 19 Oct 2022 13:07:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43060 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231251AbiJSRHn (ORCPT ); Wed, 19 Oct 2022 13:07:43 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 35BD71C19C6; Wed, 19 Oct 2022 10:07:42 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id AA99EB82566; Wed, 19 Oct 2022 17:07:40 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 44A80C433D6; Wed, 19 Oct 2022 17:07:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1666199259; bh=lFPycSPoB3wm8csR87jW68oJ2iL2Ww0URfpup0UfIt0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Oo5j4N1366DG99yyJc5NHE3UtSuMHeAJm/HUbLjaOysNYp+TAriABmNwIE4cJs+Gk jt/dy2PArY0IwA8p4lO01Bs2/K+WL/g3Hroom1jcjG1APbQmJMTQCQNGM5ZplcFufZ gMKc0HUB5Wi6AyQGD0KwISMBfmahj/bT/W+ec74chx7j+v6F0rBI4EkXG3VB8N2O63 nTCl9kfTC9WDfrsZYDKvne5u1EmLYBaKi89hLzgPs0giDoUDdu9btfQ996/UgrlWwY 7JkHUrsEcYR3Kt/+l9nU3f2uJgjSIDOSfUYYsAh6UhxeKF7ycaS5s3+Z99WRB7sCr7 /voItHuVaVIow== From: Dinh Nguyen To: jh80.chung@samsung.com Cc: dinguyen@kernel.org, ulf.hansson@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCHv5 3/6] arm: dts: socfpga: Add clk-phase-sd-hs property to the sdmmc node Date: Wed, 19 Oct 2022 12:06:54 -0500 Message-Id: <20221019170657.68014-4-dinguyen@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221019170657.68014-1-dinguyen@kernel.org> References: <20221019170657.68014-1-dinguyen@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747136968023694423?= X-GMAIL-MSGID: =?utf-8?q?1747136968023694423?= The sdmmc controller's CIU(Card Interface Unit) clock's phase can be adjusted through the register in the system manager. Add the binding "altr,sysmgr-syscon" to the SDMMC node for the driver to access the system manager. Add the "clk-phase-sd-hs" property in the SDMMC node to designate the smpsel and drvsel properties for the CIU clock. Signed-off-by: Dinh Nguyen --- v5: new --- arch/arm/boot/dts/socfpga.dtsi | 1 + arch/arm/boot/dts/socfpga_arria10.dtsi | 1 + arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi | 1 + arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts | 1 + arch/arm/boot/dts/socfpga_arria5.dtsi | 1 + arch/arm/boot/dts/socfpga_cyclone5.dtsi | 1 + arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi | 1 + 7 files changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 2459f3cd7dd9..604fc6e0c4ad 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -765,6 +765,7 @@ mmc: dwmmc0@ff704000 { clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>; clock-names = "biu", "ciu"; resets = <&rst SDMMC_RESET>; + altr,sysmgr-syscon = <&sysmgr 0x108 3>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index 4370e3cbbb4b..b6ebe207e2bc 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -666,6 +666,7 @@ mmc: dwmmc0@ff808000 { clocks = <&l4_mp_clk>, <&sdmmc_clk>; clock-names = "biu", "ciu"; resets = <&rst SDMMC_RESET>; + altr,sysmgr-syscon = <&sysmgr 0x28 4>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi b/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi index ad7cd14de6b6..41f865c8c098 100644 --- a/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi @@ -73,6 +73,7 @@ &mmc { cap-sd-highspeed; broken-cd; bus-width = <4>; + clk-phase-sd-hs = <0>, <135>; }; &osc1 { diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts b/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts index 64dc0799f3d7..d3969367f4b5 100644 --- a/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts +++ b/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts @@ -12,6 +12,7 @@ &mmc { cap-mmc-highspeed; broken-cd; bus-width = <4>; + clk-phase-sd-hs = <0>, <135>; }; &eccmgr { diff --git a/arch/arm/boot/dts/socfpga_arria5.dtsi b/arch/arm/boot/dts/socfpga_arria5.dtsi index 22dbf07afcff..b531639ce7dc 100644 --- a/arch/arm/boot/dts/socfpga_arria5.dtsi +++ b/arch/arm/boot/dts/socfpga_arria5.dtsi @@ -23,6 +23,7 @@ mmc0: dwmmc0@ff704000 { bus-width = <4>; cap-mmc-highspeed; cap-sd-highspeed; + clk-phase-sd-hs = <0>, <135>; }; sysmgr@ffd08000 { diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dtsi b/arch/arm/boot/dts/socfpga_cyclone5.dtsi index 319a71e41ea4..a9d1ba66f1ff 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5.dtsi +++ b/arch/arm/boot/dts/socfpga_cyclone5.dtsi @@ -23,6 +23,7 @@ mmc0: dwmmc0@ff704000 { bus-width = <4>; cap-mmc-highspeed; cap-sd-highspeed; + clk-phase-sd-hs = <0>, <135>; }; sysmgr@ffd08000 { diff --git a/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi b/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi index bd92806ffc12..3b9daddf91cd 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi +++ b/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi @@ -18,5 +18,6 @@ memory@0 { &mmc0 { /* On-SoM eMMC */ bus-width = <8>; + clk-phase-sd-hs = <0>, <135>; status = "okay"; }; From patchwork Wed Oct 19 17:06:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 5771 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp441994wrs; Wed, 19 Oct 2022 10:15:51 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4WznKcvlTYbOUTh13QhJtiQl0JbAQWQdsessLpfAHU1uk9+J8wrCSzyG6XxxyqgZw56L/3 X-Received: by 2002:a17:903:2111:b0:185:4ca4:7511 with SMTP id o17-20020a170903211100b001854ca47511mr9455477ple.164.1666199751307; Wed, 19 Oct 2022 10:15:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666199751; cv=none; d=google.com; s=arc-20160816; b=IMxwWeXaIp5D0LzSg8Hl/vgJ+7mBC1zEo6IMT2ZiJ6OdQHSWd1Sx27IbY+6Ga6jIIP pmFCTIS8fOg1R2ikmQ9J957uX5FHo8KMkUhQorVduauj3ft8vHfqBthdcePFDUW8mlEo jW9pwx0YfNZciktXIDOk5qizofpTSHqle0w9/up5XJUnxyt4tdgwdBETYfNItjrurmAT QvD4jEn++IsC+CXRpJ4aQN17o+nlE0I7Is0U48/VkElC4+IVFi77ptu1fozW255X56rX 5Rl9Fn5qB5cDf/Q+YzXzb+dS/qI12QIDCmS1soNITJOaeKTXrbPWufr144ZWOq1NFiUv xx+g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=No47eGpjBt8HNDml7tfkYihAa6u4mXMKcYQ7O6GDHzg=; b=y00CZUG+RTfFqESN1EEEzWiUnYubYHIiAOE9m+iREbxk9+vv45nxMuvjP8DaXyyvij T70+HnQQtSKIlQc/LQt273u7B1tLDg6+Orx9bnPyq8Z41gdAumyu8yaU+WbaK+26XWqB agE1t5TGalfxW+VBgwGjBj/x4R9cDs13G005HLMzp5nc+meYN/6SB/NX4acDXqwYTfny AuJuKmiE1Qu5j+nsesYkOPeYix9QLRJJac0KP2FttACa5iAIu9xm+NKhmMBRpLYRuPtA B2ewZDHTH7dZkv0GVY7LeKLFQX7aWaxnpZ9IUaUPT8MDoxdfNCIPGDUxXSLDkT5qz3mC tZtg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=d95vUTD+; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id u3-20020a655c03000000b00454a7fa276esi17805433pgr.224.2022.10.19.10.15.38; Wed, 19 Oct 2022 10:15:51 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=d95vUTD+; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230180AbiJSRHz (ORCPT + 99 others); Wed, 19 Oct 2022 13:07:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43062 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231398AbiJSRHn (ORCPT ); Wed, 19 Oct 2022 13:07:43 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 35919165CB3; Wed, 19 Oct 2022 10:07:42 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 7C4C961940; Wed, 19 Oct 2022 17:07:41 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9EFA5C433D7; Wed, 19 Oct 2022 17:07:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1666199260; bh=Gcpvztv6565Yasf4olb+R+dPl9mCbV3+3Cwfb8rNixc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=d95vUTD+osxVR14lWNseq3BJD1x0abDrYME13HolUF5H01Be2TPfO1x4ChDXunueQ 5cemO/QANilVmFtJ6PpeCgLmiiJLd2hCy8pC14dLAxBz3j6cItn0fpy7BWe/1gezEe ULpmlYxG7N3BA80Exbknn2zJvlvs9JUOL136ZtLeCQXgXsS4L9hdYOvbhDcJuMWUnk H9yCZM7h0Hw5eMXOEq0uMBSQ21P8X7a5/d0V1peHEdvd52Xjt9VTJk91QnW6DzCINa gmHPxw4YebPeFF7/xnRJjHaPqnuBJikWrXe2QxYwuYhTEWdS7kaa9j38lp6SmkJgS8 5oqoUE+/YXp9Q== From: Dinh Nguyen To: jh80.chung@samsung.com Cc: dinguyen@kernel.org, ulf.hansson@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCHv5 4/6] mmc: dw_mmc-pltfm: socfpga: add method to configure clk-phase Date: Wed, 19 Oct 2022 12:06:55 -0500 Message-Id: <20221019170657.68014-5-dinguyen@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221019170657.68014-1-dinguyen@kernel.org> References: <20221019170657.68014-1-dinguyen@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747137070427048659?= X-GMAIL-MSGID: =?utf-8?q?1747137070427048659?= The clock-phase settings for the SDMMC controller in the SoCFPGA platforms reside in a register in the System Manager. Add a method to access that register through the syscon interface. Signed-off-by: Dinh Nguyen --- v5: change error handling from of_property_read_variable_u32_array() support arm32 by reading the reg_shift v4: no change v3: add space before &socfpga_drv_data v2: simplify clk-phase calculations --- drivers/mmc/host/dw_mmc-pltfm.c | 43 ++++++++++++++++++++++++++++++++- 1 file changed, 42 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/dw_mmc-pltfm.c b/drivers/mmc/host/dw_mmc-pltfm.c index 9901208be797..74421d13f466 100644 --- a/drivers/mmc/host/dw_mmc-pltfm.c +++ b/drivers/mmc/host/dw_mmc-pltfm.c @@ -17,10 +17,16 @@ #include #include #include +#include +#include #include "dw_mmc.h" #include "dw_mmc-pltfm.h" +#define SOCFPGA_DW_MMC_CLK_PHASE_STEP 45 +#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel, reg_shift) \ + ((((smplsel) & 0x7) << reg_shift) | (((drvsel) & 0x7) << 0)) + int dw_mci_pltfm_register(struct platform_device *pdev, const struct dw_mci_drv_data *drv_data) { @@ -62,9 +68,44 @@ const struct dev_pm_ops dw_mci_pltfm_pmops = { }; EXPORT_SYMBOL_GPL(dw_mci_pltfm_pmops); +static int dw_mci_socfpga_priv_init(struct dw_mci *host) +{ + struct device_node *np = host->dev->of_node; + struct regmap *sys_mgr_base_addr; + u32 clk_phase[2] = {0}, reg_offset, reg_shift; + int i, rc, hs_timing; + + rc = of_property_read_variable_u32_array(np, "clk-phase-sd-hs", &clk_phase[0], 2, 0); + if (rc < 0) { + dev_err(host->dev, "clk-phase-sd-hs not found!\n"); + return rc; + } + + sys_mgr_base_addr = altr_sysmgr_regmap_lookup_by_phandle(np, "altr,sysmgr-syscon"); + if (IS_ERR(sys_mgr_base_addr)) { + dev_err(host->dev, "failed to find altr,sys-mgr regmap!\n"); + return -ENODEV; + } + + of_property_read_u32_index(np, "altr,sysmgr-syscon", 1, ®_offset); + of_property_read_u32_index(np, "altr,sysmgr-syscon", 2, ®_shift); + + for (i = 0; i < ARRAY_SIZE(clk_phase); i++) + clk_phase[i] /= SOCFPGA_DW_MMC_CLK_PHASE_STEP; + + hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1], reg_shift); + regmap_write(sys_mgr_base_addr, reg_offset, hs_timing); + + return 0; +} + +static const struct dw_mci_drv_data socfpga_drv_data = { + .init = dw_mci_socfpga_priv_init, +}; + static const struct of_device_id dw_mci_pltfm_match[] = { { .compatible = "snps,dw-mshc", }, - { .compatible = "altr,socfpga-dw-mshc", }, + { .compatible = "altr,socfpga-dw-mshc", .data = &socfpga_drv_data, }, { .compatible = "img,pistachio-dw-mshc", }, {}, }; From patchwork Wed Oct 19 17:06:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 5768 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp441246wrs; Wed, 19 Oct 2022 10:14:36 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6mEUzs86ip8KpicG568CUWBQXaoz32Yd0JdmErH1FfQ11R1h8d0Bg1CN9H7bV48hf1sJat X-Received: by 2002:a05:6a00:14d4:b0:563:9296:f320 with SMTP id w20-20020a056a0014d400b005639296f320mr9437770pfu.27.1666199676272; Wed, 19 Oct 2022 10:14:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666199676; cv=none; d=google.com; s=arc-20160816; b=dtFo+ImkVp2jmBPvNfsACW1+97X0iD5cBD7icFAsQ4NnQg5Uv4wQ/W96ud/ZDBwmAX t2LQgDZzwC870df7x1NIcQXE0E0pxhSH3gsVpF+3cSsOQ04HHyECKPOvFbIqzlEFqWQi i6040l8+9Mdj/+Ip0FbKewLivvEyWcTtZQze63FwbJ1jFSyT0JrPHhOUhZ2lvfrP4xKE Iikxzzi6RoGbHm1yMaWIFQcjzaapHS4HjfrwhvpDKuxLXO9cYl+JiY9F887VN/vs0Ls/ yIfgun4BQf30KR1+gL1uEMkvJYtEwz7uxldGe9onnXv3cM4HY/3Bu7eTiogWh7WvsKQX Wq1Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=5GeKgxApDedHcYUKwv9ISzBcdUXVyqLW9GLPA8vX3xY=; b=QnJ69T14MG4eokNUWB8IFSa0EIl6f4+gSCzqdj/8Rgpm2QpH5hnzw8BJZnpRbfndHe sWhcg+J6kygeixKigy16AEi2Nl71uh9Lr0ehiuifRdgxE8lp/J/my/oorChLUtkk6O4+ rUdDU+hfmuOojpVJ7Bw5Jc3ulSNaxEroqICiOXh8fFfeZU/aQQPqkj2OQXrjFiY3KKLF W2grx739dAdDqRZbZml848+qcinEHtxdvqpmyvstOFFXW44ZGb4sQ7gQwnUYphahhsla k3UcGYDFtS70xKRq0s5W0fxi5Z9s8STdbv+hGkHBf69mVyfMP0Pgts4Enl54Nr1swjne WdhQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=py2INVJX; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id ay12-20020a1709028b8c00b00178072335cbsi17426921plb.132.2022.10.19.10.14.21; Wed, 19 Oct 2022 10:14:36 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=py2INVJX; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231351AbiJSRIB (ORCPT + 99 others); Wed, 19 Oct 2022 13:08:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43152 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231504AbiJSRHq (ORCPT ); Wed, 19 Oct 2022 13:07:46 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A5AAD1C2098; Wed, 19 Oct 2022 10:07:43 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id CEC7E61967; Wed, 19 Oct 2022 17:07:42 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 28118C433C1; Wed, 19 Oct 2022 17:07:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1666199262; bh=uEKjbDD+8urYCHBuvyX9+nK0j+GP1bQnusGWwlLB/YM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=py2INVJXiCRFE23ZGAwBFqN956OtZ8nMCnBUsLZmUpX6LjeBFIdqUfe2q/SZCJOI4 60SXgFqY1+KlCjWGqCACf1EC+pVQJE84edsyVH3HkbnGY6H3+QHm6AuUZGBnuih3oC Frj9QQd37d6MgAWW/Mbzsl46csWmCZ5HF6JbobcGSfitbnbKCblH+2WQuoY10sMwbx 46uC6CN9s1WSf5JhprGSyw8YVCuqgsLuPMNhEfZQzyV39TxvFYSwHnwLheZen/tv5y 1QwunCZPOaiofwtqOcKPsVarzYF8zehKPbzSkhwMXm+74YzXKg7nLiRHvxe+U+a8Bc Hv3nMSkzfKGWw== From: Dinh Nguyen To: jh80.chung@samsung.com Cc: dinguyen@kernel.org, ulf.hansson@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCHv5 5/6] clk: socfpga: remove the setting of clk-phase for sdmmc_clk Date: Wed, 19 Oct 2022 12:06:56 -0500 Message-Id: <20221019170657.68014-6-dinguyen@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221019170657.68014-1-dinguyen@kernel.org> References: <20221019170657.68014-1-dinguyen@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747136991856459731?= X-GMAIL-MSGID: =?utf-8?q?1747136991856459731?= Now that the SDMMC driver supports setting the clk-phase, we can remove the need to do it in the clock driver. Signed-off-by: Dinh Nguyen --- v5: new --- drivers/clk/socfpga/clk-gate-a10.c | 68 ------------------------------ drivers/clk/socfpga/clk-gate.c | 60 -------------------------- drivers/clk/socfpga/clk.h | 1 - 3 files changed, 129 deletions(-) diff --git a/drivers/clk/socfpga/clk-gate-a10.c b/drivers/clk/socfpga/clk-gate-a10.c index 738c53391e39..7cdf2f07c79b 100644 --- a/drivers/clk/socfpga/clk-gate-a10.c +++ b/drivers/clk/socfpga/clk-gate-a10.c @@ -35,59 +35,7 @@ static unsigned long socfpga_gate_clk_recalc_rate(struct clk_hw *hwclk, return parent_rate / div; } -static int socfpga_clk_prepare(struct clk_hw *hwclk) -{ - struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); - int i; - u32 hs_timing; - u32 clk_phase[2]; - - if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) { - for (i = 0; i < ARRAY_SIZE(clk_phase); i++) { - switch (socfpgaclk->clk_phase[i]) { - case 0: - clk_phase[i] = 0; - break; - case 45: - clk_phase[i] = 1; - break; - case 90: - clk_phase[i] = 2; - break; - case 135: - clk_phase[i] = 3; - break; - case 180: - clk_phase[i] = 4; - break; - case 225: - clk_phase[i] = 5; - break; - case 270: - clk_phase[i] = 6; - break; - case 315: - clk_phase[i] = 7; - break; - default: - clk_phase[i] = 0; - break; - } - } - - hs_timing = SYSMGR_SDMMC_CTRL_SET_AS10(clk_phase[0], clk_phase[1]); - if (!IS_ERR(socfpgaclk->sys_mgr_base_addr)) - regmap_write(socfpgaclk->sys_mgr_base_addr, - SYSMGR_SDMMCGRP_CTRL_OFFSET, hs_timing); - else - pr_err("%s: cannot set clk_phase because sys_mgr_base_addr is not available!\n", - __func__); - } - return 0; -} - static struct clk_ops gateclk_ops = { - .prepare = socfpga_clk_prepare, .recalc_rate = socfpga_gate_clk_recalc_rate, }; @@ -96,7 +44,6 @@ static void __init __socfpga_gate_init(struct device_node *node, { u32 clk_gate[2]; u32 div_reg[3]; - u32 clk_phase[2]; u32 fixed_div; struct clk_hw *hw_clk; struct socfpga_gate_clk *socfpga_clk; @@ -136,21 +83,6 @@ static void __init __socfpga_gate_init(struct device_node *node, socfpga_clk->div_reg = NULL; } - rc = of_property_read_u32_array(node, "clk-phase", clk_phase, 2); - if (!rc) { - socfpga_clk->clk_phase[0] = clk_phase[0]; - socfpga_clk->clk_phase[1] = clk_phase[1]; - - socfpga_clk->sys_mgr_base_addr = - syscon_regmap_lookup_by_compatible("altr,sys-mgr"); - if (IS_ERR(socfpga_clk->sys_mgr_base_addr)) { - pr_err("%s: failed to find altr,sys-mgr regmap!\n", - __func__); - kfree(socfpga_clk); - return; - } - } - of_property_read_string(node, "clock-output-names", &clk_name); init.name = clk_name; diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfpga/clk-gate.c index 53d6e3ec4309..7ea1c00a14dd 100644 --- a/drivers/clk/socfpga/clk-gate.c +++ b/drivers/clk/socfpga/clk-gate.c @@ -108,61 +108,7 @@ static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk, return parent_rate / div; } -static int socfpga_clk_prepare(struct clk_hw *hwclk) -{ - struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); - struct regmap *sys_mgr_base_addr; - int i; - u32 hs_timing; - u32 clk_phase[2]; - - if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) { - sys_mgr_base_addr = syscon_regmap_lookup_by_compatible("altr,sys-mgr"); - if (IS_ERR(sys_mgr_base_addr)) { - pr_err("%s: failed to find altr,sys-mgr regmap!\n", __func__); - return -EINVAL; - } - - for (i = 0; i < 2; i++) { - switch (socfpgaclk->clk_phase[i]) { - case 0: - clk_phase[i] = 0; - break; - case 45: - clk_phase[i] = 1; - break; - case 90: - clk_phase[i] = 2; - break; - case 135: - clk_phase[i] = 3; - break; - case 180: - clk_phase[i] = 4; - break; - case 225: - clk_phase[i] = 5; - break; - case 270: - clk_phase[i] = 6; - break; - case 315: - clk_phase[i] = 7; - break; - default: - clk_phase[i] = 0; - break; - } - } - hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1]); - regmap_write(sys_mgr_base_addr, SYSMGR_SDMMCGRP_CTRL_OFFSET, - hs_timing); - } - return 0; -} - static struct clk_ops gateclk_ops = { - .prepare = socfpga_clk_prepare, .recalc_rate = socfpga_clk_recalc_rate, .get_parent = socfpga_clk_get_parent, .set_parent = socfpga_clk_set_parent, @@ -218,12 +164,6 @@ void __init socfpga_gate_init(struct device_node *node) socfpga_clk->div_reg = NULL; } - rc = of_property_read_u32_array(node, "clk-phase", clk_phase, 2); - if (!rc) { - socfpga_clk->clk_phase[0] = clk_phase[0]; - socfpga_clk->clk_phase[1] = clk_phase[1]; - } - of_property_read_string(node, "clock-output-names", &clk_name); init.name = clk_name; diff --git a/drivers/clk/socfpga/clk.h b/drivers/clk/socfpga/clk.h index d80115fbdd6a..9a2fb2dde5b8 100644 --- a/drivers/clk/socfpga/clk.h +++ b/drivers/clk/socfpga/clk.h @@ -50,7 +50,6 @@ struct socfpga_gate_clk { u32 width; /* only valid if div_reg != 0 */ u32 shift; /* only valid if div_reg != 0 */ u32 bypass_shift; /* only valid if bypass_reg != 0 */ - u32 clk_phase[2]; }; struct socfpga_periph_clk { From patchwork Wed Oct 19 17:06:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 5769 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp441250wrs; Wed, 19 Oct 2022 10:14:36 -0700 (PDT) X-Google-Smtp-Source: AMsMyM61+9IP9MzV8Re12rzuUx6i+ieCqTVkQjGTgf6X7fJRv+xRyRK2beQb20LQznfTkQaRMRvG X-Received: by 2002:a63:2212:0:b0:43b:f03d:856a with SMTP id i18-20020a632212000000b0043bf03d856amr8080070pgi.192.1666199676357; Wed, 19 Oct 2022 10:14:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666199676; cv=none; d=google.com; s=arc-20160816; b=CuJVOVeCOV4KKfC2SOTi0jyjTiZBhVDaTwDmKdk/1DYJc1ZBoPPGrwxfNi04AVDtw1 xNHBrkniT69mVRhLoB6wzIYzS5xsx0aKd20Haovl0rQoe5wc7mYNgawoUgARSJlz0Ek8 TlQhGznNLR2pQ2DXox6EoQ7NaW/FZlru+fwGMMFoKfCgOyxmV8W3UKZVC7wqVo/4D4IR XRm4xVqcFF6EQPKpLswC7Vd5EJoBheHZjlSv3NjzRe4XDOK9AtmrGx7Fz+XtlW68IEUC 56sBig5hEeaE8skIvSznS6tdTCEuQSLrfgC2+DDMbpyDzV3XIokHl6+lO6RzvgkSD5Rn nFIQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=/sVXWY7NuGhUK8jXeZzfexoIk6yT17XPBjsIwi908sw=; b=TlIuyFHNjXD6FgoVN3JRAvBTCiPMF9idNfMs9XGTMCbdFL/IRzRbU/LQKDF6yON9cz 7CrP1khIFi0I2qJfbOgWuaOLx7IFYHBnrVU4IxDAesmgHNWnp5Oy8W3fn6deJtLMjnzi Sb3rgm51uV772M1KD3Jl1KZEzNA9xt58VKTCCd5+RNJnDvE15BF+jRid7n4Rr+D4UNCc y+lcobNRyBWSH4XWGLfF6Ob8Z+CKn6QhNi0ImvgxTy1VUOwrnJ25Pw+92anfToYFrGNn GZKRr/i4dk5bFFooniMV6uhHHtSKHBSPcM6ky+B6P8Tsrq3BYwS37hL8ZhE5al2heURy FNQw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=XDO4lZI7; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id q13-20020a63cc4d000000b0043895127033si19179052pgi.335.2022.10.19.10.14.22; Wed, 19 Oct 2022 10:14:36 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=XDO4lZI7; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230012AbiJSRIG (ORCPT + 99 others); Wed, 19 Oct 2022 13:08:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43202 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231476AbiJSRHr (ORCPT ); Wed, 19 Oct 2022 13:07:47 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6C8101C25DF; Wed, 19 Oct 2022 10:07:46 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id E3572B82569; Wed, 19 Oct 2022 17:07:44 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 88A62C433D6; Wed, 19 Oct 2022 17:07:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1666199263; bh=NBiNwt7o0VNrUfZVe+mze7hfm/agY6VvLH9+RfpkjI4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XDO4lZI7Y+1o0w/32vAGAx5EDuVyphtGY+VGYBpbXLcRmeqKpQfEGyHGeQS/49/4p c0cPG5HOjo/6+hYy5oyrfZklgqYZuuZmXNn7OjTTybluP383b2PvZi3GfPqgR/LKe4 v5oWAlpHGXGb09aidwHCFup7X25IBw4gsHM0YykI6RUw6BkJkiP+C/pnA54t3j335k nqy9FWaQVZaHqs3iGGJ8BSNGm0EkqrGYlHel+8ALJczCBZ+AaZ6DPMhKl3NkylD9Cp 5sYpOyyHNvx5j9ELvxaxNGynJJdr3vmY9uBUtVfsyCMDWZSe+e9bMxq7xgn8MWaqhe k0aNSV6BzO2xQ== From: Dinh Nguyen To: jh80.chung@samsung.com Cc: dinguyen@kernel.org, ulf.hansson@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCHv5 6/6] arm: dts: socfpga: remove "clk-phase" in sdmmc_clk Date: Wed, 19 Oct 2022 12:06:57 -0500 Message-Id: <20221019170657.68014-7-dinguyen@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221019170657.68014-1-dinguyen@kernel.org> References: <20221019170657.68014-1-dinguyen@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747136991481126608?= X-GMAIL-MSGID: =?utf-8?q?1747136991481126608?= Now that the SDMMC driver can use the "clk-phase-sd-hs" binding, we don't need the clk-phase in the sdmmc_clk anymore. Signed-off-by: Dinh Nguyen --- v5: new --- arch/arm/boot/dts/socfpga.dtsi | 1 - arch/arm/boot/dts/socfpga_arria10.dtsi | 1 - 2 files changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 604fc6e0c4ad..a2419a5c6c26 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -453,7 +453,6 @@ sdmmc_clk: sdmmc_clk { compatible = "altr,socfpga-gate-clk"; clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; clk-gate = <0xa0 8>; - clk-phase = <0 135>; }; sdmmc_clk_divided: sdmmc_clk_divided { diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index b6ebe207e2bc..eb528c103d70 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -365,7 +365,6 @@ sdmmc_clk: sdmmc_clk { compatible = "altr,socfpga-a10-gate-clk"; clocks = <&sdmmc_free_clk>; clk-gate = <0xC8 5>; - clk-phase = <0 135>; }; qspi_clk: qspi_clk {