From patchwork Wed Oct 19 15:37:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Golle X-Patchwork-Id: 5718 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp398274wrs; Wed, 19 Oct 2022 08:49:24 -0700 (PDT) X-Google-Smtp-Source: AMsMyM72yrGaeQS2GwqXxx1Msbz1RJdFNvRRFFLA0+IIwk0UChk66YI0g6SAw17eresYLt7zbF1Z X-Received: by 2002:a17:907:7215:b0:791:a61f:56b3 with SMTP id dr21-20020a170907721500b00791a61f56b3mr4064430ejc.331.1666194564368; Wed, 19 Oct 2022 08:49:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666194564; cv=none; d=google.com; s=arc-20160816; b=C/5AfKUsJzt/h9OiFyl1Uk623KiVQ3zIrfAG3pBdArmcdZ6FffFCfNHq0ej9Iqa4oL UKHxl7AwRRwUCO9ZqcoRIhnt1O1cFiyFZuRDbGLO8KHPGnOA4x3SZQIP1hl9UkbetnYO l1NUCXTf6qZjH0w2rfUOFKN586x+WQfuDRNqmwWq0MIbgcNZod4KlaXTWF4D53pRFilT p+hx9DM5Q/Vrjf2Tb1r8/1Z7z2L1zGSKRyS+Lfm4ZkfaQ5HrQbHAaieDm430Ds75Dtud 3wQaTzEx5Az8ZysWd2ueYofhrVajTNVmaSjKQ4NGjSg/k1LXu33VBfgDlEpIRowalCKf Sh1A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-disposition:mime-version:message-id :subject:cc:to:from:date; bh=ISX6QpPRg7V9JoRSnj0d65sQzFiTPSAJngbgVAeUpIw=; b=YeoMiDKHw0oDzXW6L7LYhvb9O+X08mV2ZKhtJno076FTU5nVUtqDxpDbJu9rPGmLiD XcxJ23V1BzwqTDjWhuzco4frT2LxjnW1UzWrGFAc9zTm5bCTsOruMLQov/RrGIQxJtdQ L0QoGpfkz7eSP97kIf6t/ByFx5aFIZfpoUuz5FnQpAx/+7GEU02PUpaEa0YwqQ6XMpz8 ioe8Ng8rimfAHWmu8mSMwbQ58E5/qJmbgVayeTS4kyg9hUjU1e3F78WIDRrLW6A9eDh8 ldAuP8VwmxU8Gy4n7r+3LRXgjR9iIT71iB/HkPq98kDtNKIAsCrAn6YYPA8QNTZ2j4qa 98Ag== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id s23-20020a50d497000000b0045c99ed49ddsi13143932edi.431.2022.10.19.08.48.56; Wed, 19 Oct 2022 08:49:24 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231238AbiJSPnu (ORCPT + 99 others); Wed, 19 Oct 2022 11:43:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50768 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231401AbiJSPnN (ORCPT ); Wed, 19 Oct 2022 11:43:13 -0400 Received: from fudo.makrotopia.org (fudo.makrotopia.org [IPv6:2a07:2ec0:3002::71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B5A8D60C87 for ; Wed, 19 Oct 2022 08:38:51 -0700 (PDT) Received: from local by fudo.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.94.2) (envelope-from ) id 1olB8j-00015j-Gi; Wed, 19 Oct 2022 17:37:53 +0200 Date: Wed, 19 Oct 2022 16:37:44 +0100 From: Daniel Golle To: linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, Chunfeng Yun , Vinod Koul , Kishon Vijay Abraham I , Matthias Brugger Cc: linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/2] phy: phy-mtk-tphy: Add PCIe 2 lane efuse support Message-ID: MIME-Version: 1.0 Content-Disposition: inline X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747131631300068810?= X-GMAIL-MSGID: =?utf-8?q?1747131631300068810?= From: Zhanyong Wang Add PCIe 2 lane efuse support in tphy driver. Signed-off-by: Jie Yang Signed-off-by: Zhanyong Wang Signed-off-by: Daniel Golle --- drivers/phy/mediatek/phy-mtk-tphy.c | 112 ++++++++++++++++++++++++++++ 1 file changed, 112 insertions(+) diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c index e906a82791bdaa..b0c9834efec7ef 100644 --- a/drivers/phy/mediatek/phy-mtk-tphy.c +++ b/drivers/phy/mediatek/phy-mtk-tphy.c @@ -43,6 +43,15 @@ #define SSUSB_SIFSLV_V2_U3PHYD 0x200 #define SSUSB_SIFSLV_V2_U3PHYA 0x400 +/* version V4 sub-banks offset base address */ +/* pcie phy banks */ +#define SSUSB_SIFSLV_V4_SPLLC 0x000 +#define SSUSB_SIFSLV_V4_CHIP 0x100 +#define SSUSB_SIFSLV_V4_U3PHYD 0x900 +#define SSUSB_SIFSLV_V4_U3PHYA 0xb00 + +#define SSUSB_LN1_OFFSET 0x10000 + #define U3P_MISC_REG1 0x04 #define MR1_EFUSE_AUTO_LOAD_DIS BIT(6) @@ -268,6 +277,7 @@ enum mtk_phy_version { MTK_PHY_V1 = 1, MTK_PHY_V2, MTK_PHY_V3, + MTK_PHY_V4, }; struct mtk_phy_pdata { @@ -317,6 +327,9 @@ struct mtk_phy_instance { u32 efuse_intr; u32 efuse_tx_imp; u32 efuse_rx_imp; + u32 efuse_intr_ln1; + u32 efuse_tx_imp_ln1; + u32 efuse_rx_imp_ln1; int eye_src; int eye_vrt; int eye_term; @@ -760,6 +773,36 @@ static void phy_v2_banks_init(struct mtk_tphy *tphy, } } +static void phy_v4_banks_init(struct mtk_tphy *tphy, + struct mtk_phy_instance *instance) +{ + struct u2phy_banks *u2_banks = &instance->u2_banks; + struct u3phy_banks *u3_banks = &instance->u3_banks; + + switch (instance->type) { + case PHY_TYPE_USB2: + u2_banks->misc = instance->port_base + SSUSB_SIFSLV_V2_MISC; + u2_banks->fmreg = instance->port_base + SSUSB_SIFSLV_V2_U2FREQ; + u2_banks->com = instance->port_base + SSUSB_SIFSLV_V2_U2PHY_COM; + break; + case PHY_TYPE_USB3: + u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V2_SPLLC; + u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V2_CHIP; + u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V2_U3PHYD; + u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V2_U3PHYA; + break; + case PHY_TYPE_PCIE: + u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V4_SPLLC; + u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V4_CHIP; + u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V4_U3PHYD; + u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V4_U3PHYA; + break; + default: + dev_err(tphy->dev, "incompatible PHY type\n"); + return; + } +} + static void phy_parse_property(struct mtk_tphy *tphy, struct mtk_phy_instance *instance) { @@ -951,6 +994,40 @@ static int phy_efuse_get(struct mtk_tphy *tphy, struct mtk_phy_instance *instanc dev_dbg(dev, "u3 efuse - intr %x, rx_imp %x, tx_imp %x\n", instance->efuse_intr, instance->efuse_rx_imp,instance->efuse_tx_imp); + + if (tphy->pdata->version != MTK_PHY_V4) + break; + + ret = nvmem_cell_read_variable_le_u32(dev, "intr_ln1", &instance->efuse_intr_ln1); + if (ret) { + dev_err(dev, "fail to get u3 lane1 intr efuse, %d\n", ret); + break; + } + + ret = nvmem_cell_read_variable_le_u32(dev, "rx_imp_ln1", &instance->efuse_rx_imp_ln1); + if (ret) { + dev_err(dev, "fail to get u3 lane1 rx_imp efuse, %d\n", ret); + break; + } + + ret = nvmem_cell_read_variable_le_u32(dev, "tx_imp_ln1", &instance->efuse_tx_imp_ln1); + if (ret) { + dev_err(dev, "fail to get u3 lane1 tx_imp efuse, %d\n", ret); + break; + } + + /* no efuse, ignore it */ + if (!instance->efuse_intr_ln1 && + !instance->efuse_rx_imp_ln1 && + !instance->efuse_tx_imp_ln1) { + dev_warn(dev, "no u3 lane1 efuse, but dts enable it\n"); + instance->efuse_sw_en = 0; + break; + } + + dev_info(dev, "u3 lane1 efuse - intr %x, rx_imp %x, tx_imp %x\n", + instance->efuse_intr_ln1, instance->efuse_rx_imp_ln1, + instance->efuse_tx_imp_ln1); break; default: dev_err(dev, "no sw efuse for type %d\n", instance->type); @@ -990,6 +1067,31 @@ static void phy_efuse_set(struct mtk_phy_instance *instance) mtk_phy_update_field(u3_banks->phya + U3P_U3_PHYA_REG0, P3A_RG_IEXT_INTR, instance->efuse_intr); + if (instance->type == PHY_TYPE_USB3 || ( + !instance->efuse_intr_ln1 && + !instance->efuse_rx_imp_ln1 && + !instance->efuse_tx_imp_ln1)) + break; + + mtk_phy_set_bits(u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_RSV, + P3D_RG_EFUSE_AUTO_LOAD_DIS); + + mtk_phy_update_field(u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_IMPCAL0, + P3D_RG_TX_IMPEL, instance->efuse_tx_imp_ln1); + mtk_phy_set_bits(u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_IMPCAL0, + P3D_RG_FORCE_TX_IMPEL); + + mtk_phy_update_field(u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_IMPCAL1, + P3D_RG_RX_IMPEL, instance->efuse_rx_imp_ln1); + mtk_phy_set_bits(u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_IMPCAL1, + P3D_RG_FORCE_RX_IMPEL); + + mtk_phy_update_field(u3_banks->phya + SSUSB_LN1_OFFSET + U3P_U3_PHYA_REG0, + P3A_RG_IEXT_INTR, instance->efuse_intr_ln1); + + dev_info(dev, "%s set LN1 efuse, tx_imp %x, rx_imp %x intr %x\n", + __func__, instance->efuse_tx_imp_ln1, + instance->efuse_rx_imp_ln1, instance->efuse_intr_ln1); break; default: dev_warn(dev, "no sw efuse for type %d\n", instance->type); @@ -1129,6 +1231,9 @@ static struct phy *mtk_phy_xlate(struct device *dev, case MTK_PHY_V3: phy_v2_banks_init(tphy, instance); break; + case MTK_PHY_V4: + phy_v4_banks_init(tphy, instance); + break; default: dev_err(dev, "phy version is not supported\n"); return ERR_PTR(-EINVAL); @@ -1169,6 +1274,12 @@ static const struct mtk_phy_pdata tphy_v3_pdata = { .version = MTK_PHY_V3, }; +static const struct mtk_phy_pdata tphy_v4_pdata = { + .avoid_rx_sen_degradation = false, + .sw_efuse_supported = true, + .version = MTK_PHY_V4, +}; + static const struct mtk_phy_pdata mt8173_pdata = { .avoid_rx_sen_degradation = true, .version = MTK_PHY_V1, @@ -1188,6 +1299,7 @@ static const struct of_device_id mtk_tphy_id_table[] = { { .compatible = "mediatek,generic-tphy-v1", .data = &tphy_v1_pdata }, { .compatible = "mediatek,generic-tphy-v2", .data = &tphy_v2_pdata }, { .compatible = "mediatek,generic-tphy-v3", .data = &tphy_v3_pdata }, + { .compatible = "mediatek,generic-tphy-v4", .data = &tphy_v4_pdata }, { }, }; MODULE_DEVICE_TABLE(of, mtk_tphy_id_table); From patchwork Wed Oct 19 15:38:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Golle X-Patchwork-Id: 5726 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp407589wrs; Wed, 19 Oct 2022 09:06:29 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4qb4SCv3g02UD528OT7sNRwmOaW+plRnAPFfR61ctBE1xlVJNH+I0772YnIat0L24Irhmn X-Received: by 2002:a17:902:7b87:b0:179:ec0a:7239 with SMTP id w7-20020a1709027b8700b00179ec0a7239mr9330015pll.139.1666195588687; Wed, 19 Oct 2022 09:06:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666195588; cv=none; d=google.com; s=arc-20160816; b=m/99cDfrQAd/dCx04uNwYHqRz7gJyoIhA59kK6zhdrx0FrSoVxd9uh7ZTGjNOu0jpl 6YXLd3Mc9xJi5RL/Bl4tu3/omuoFbww6qKfzbVNWIg+HJdinYsehR19dTcnflswWeRR2 /X6Ch4JS2d03vWQUpkR8SdAgbpv2Dt3CvBQfjkQMRzF4fzYhHtbOSEXB7dsAjmk/+fTr ek0C9RusQPXSJb6jRoiFGHSuu0NsYaNR+XfTh/ZFEs4NGjspynxlh/ghc3oKHhjQW2t0 L5dC7bG8yvEYmU+Cru5Wac33MOnzsY3qrcGuvXawz5JuFRjOAnif3RSwknpW6lAMw6li Vx9g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:in-reply-to:content-disposition:mime-version :references:message-id:subject:cc:to:from:date; bh=QPBVcim80ZEA2cpucSN5geGdm9XZKu9ZntbpN9+CTng=; b=xuuZQVFoivFXdRCJC9uLqVOCYQaJieMI9KdkCpomLa7ZeToq5rsyHbYnaPGfr3gGYr pHag1a2AakrUs8VXZqpSGoHwK3dM4kTCwBFCUxpByFFJx9K9Vk7mPnc3piNe0tggt4H+ OZK3JBPzKdgt3oUeH66ARbuRTclt8JKFWBFAkL9VYhQm4hthSVVQGsbqxQxRO27c9NU9 Vyp/0Sv0YKijt3h0w8hlq6WPJaZjrwvuFcPcXcQA9m44k6YJ/sNrTf+M11H35a3aHr6p OUgag1c7UAUvjvDC69KoDkl1iP2xBzQh/GflSjesjk+7c2NOm5cvMksBsjjR08Yq1vuj RzVw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id p5-20020a17090a348500b00202be5416b1si238439pjb.109.2022.10.19.09.06.14; Wed, 19 Oct 2022 09:06:28 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231437AbiJSPyl (ORCPT + 99 others); Wed, 19 Oct 2022 11:54:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58034 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232428AbiJSPx5 (ORCPT ); Wed, 19 Oct 2022 11:53:57 -0400 X-Greylist: delayed 733 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Wed, 19 Oct 2022 08:51:30 PDT Received: from fudo.makrotopia.org (fudo.makrotopia.org [IPv6:2a07:2ec0:3002::71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3987B196089; Wed, 19 Oct 2022 08:51:30 -0700 (PDT) Received: from local by fudo.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.94.2) (envelope-from ) id 1olB9A-000167-Pv; Wed, 19 Oct 2022 17:38:20 +0200 Date: Wed, 19 Oct 2022 16:38:14 +0100 From: Daniel Golle To: linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, Chunfeng Yun , Vinod Koul , Kishon Vijay Abraham I , Matthias Brugger Cc: linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 2/2] dt-bindings: phy: mediatek: tphy: add compatible for tphy-v4 Message-ID: <07c5d962515c4f675f076bb91d69eaf651b187c6.1666193782.git.daniel@makrotopia.org> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747132705531979071?= X-GMAIL-MSGID: =?utf-8?q?1747132705531979071?= V4 can be found in MT7986 and MT7981 SoCs, it supports PCIe with two lanes. Signed-off-by: Daniel Golle Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/phy/mediatek,tphy.yaml | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml index 5613cc5106e32f..851e3dda7b638b 100644 --- a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml +++ b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml @@ -89,6 +89,11 @@ properties: - mediatek,mt8188-tphy - mediatek,mt8195-tphy - const: mediatek,generic-tphy-v3 + - items: + - enum: + - mediatek,mt7981-tphy + - mediatek,mt7986-tphy + - const: mediatek,generic-tphy-v4 - const: mediatek,mt2701-u3phy deprecated: true - const: mediatek,mt2712-u3phy @@ -99,7 +104,7 @@ properties: description: Register shared by multiple ports, exclude port's private register. It is needed for T-PHY V1, such as mt2701 and mt8173, but not for - T-PHY V2/V3, such as mt2712. + T-PHY V2/V3/V4, such as mt2712. maxItems: 1 "#address-cells":