From patchwork Wed Oct 19 15:03:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Arnd Bergmann X-Patchwork-Id: 5664 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp381152wrs; Wed, 19 Oct 2022 08:14:00 -0700 (PDT) X-Google-Smtp-Source: AMsMyM77fkbRJ87sxjLQjkoy82nGvSESDtlJn0yv2HbPMpdCfV8kqAoZwvaVXh3Bi3UTkOAFjn9n X-Received: by 2002:a17:907:2d8a:b0:78d:4448:e96c with SMTP id gt10-20020a1709072d8a00b0078d4448e96cmr7161885ejc.199.1666192439867; Wed, 19 Oct 2022 08:13:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666192439; cv=none; d=google.com; s=arc-20160816; b=ovYLwxIhaUcIoH4R5yVdB/65CNL57Mu4ii3bHXDsywyNWgt4RlRHCFEK3iYDPi88ap IROittOH11ADQVL4Ruz2pqySI4wHynH1MQNDrlM5My6ZaWoPPvPuCBhZQ9+6dgeJ2t/Y Q0tQo7yK/IRJKBU9vVODCP2jMbK6ewWutA6rUZRn8ubFBuPO4a7PHy8fk7TaO8NV9MzU RZHLuD4ID8pQCB1MCISD4DE5wzDwBXN6gHHT36xI5Z8ZDmRwpQhMgBeQdwA1SkkCvfpi h3Q8OpvPOB8YTlEyLl29L1CAQLqYix+RSA5wQ+YsyGRsgGfPMt8Q6S1SqhqYSIoYJXTh C/lw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=EI/NruPIBkvqDGJKNRwUMD8yrkQnRqyovHRgJ41D0r0=; b=kFv9EKZ5WGmvDIi1+ybF0hOE/X0ZPeSN4i4vqsesvjLTpQ6txEmED8kLAKgVnO1gh1 jDGuNe2VIqVJ/cksid1Ugm226zl5EMYl7FZB+WelMwMbLCBx4Wf66XNZwz0rDI9uYlFd tp5E53hXiV80L3IYkHF9azsFEVwMPBFQRev6L5VGLWNV1s1qQiC8jbU517mESN+524Wg Nd1Er6cTHO1dpSq3C1FnRSJlmOat+8Q5eQykjDRQYl+9zcbJt45PFuDp/qmWcIIVUgS+ az6tIXqyIFIVsorJuRCi+QHiQTrvggU874uMK+YYTWmkASsEWSVlS+3lc25mvaQgWcWq kpnw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=fWyGr6y7; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id w9-20020aa7da49000000b0044e6b43f044si13599537eds.267.2022.10.19.08.13.33; Wed, 19 Oct 2022 08:13:59 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=fWyGr6y7; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232272AbiJSPLq (ORCPT + 99 others); Wed, 19 Oct 2022 11:11:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47954 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232229AbiJSPLU (ORCPT ); Wed, 19 Oct 2022 11:11:20 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3505D21E2D for ; Wed, 19 Oct 2022 08:04:23 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 26063B824A4 for ; Wed, 19 Oct 2022 15:04:22 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 82974C433B5; Wed, 19 Oct 2022 15:04:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1666191860; bh=Pi1k4R02i4ZR/ncs7Qdsgrt+18evANMUSUdhXR9xuDA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fWyGr6y7NBkpWDNITwVplYSgw68+4Y6PZJLGcZ4xw5sQzzYGrItD2Q++MwGqgNxlu HQRgwIoZVz1OMXVS1XszOFYJdPSvxJhKOGckIBKsM1gRFQeD5wzP+ea6IcDnu4DD2r wbLGgPGWorD3kq6B9Pu5cA3Jf+KO5xJU3+PP9IPVOT8RAIJkQ+KiqSApfol5JxS0OK iHiww33jy6JsHgw18EYNfAlPdaQ2y5kT0zRmsulEhtKy0l/M9x3MA1bBu7JyEIhhWQ OppAedxHUxq9pm/FF/KJG7qI5oSehp18dGPABp65uySh/GaWmguCbj8d8b1XdBKDwj lA1LUcb6Vlr6Q== From: Arnd Bergmann To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Arnd Bergmann , Nicolas Ferre , Alexandre Belloni , Claudiu Beznea Subject: [PATCH 01/17] ARM: at91: remove stale MAINTAINER file entries Date: Wed, 19 Oct 2022 17:03:23 +0200 Message-Id: <20221019150410.3851944-1-arnd@kernel.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20221019144119.3848027-1-arnd@kernel.org> References: <20221019144119.3848027-1-arnd@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747129403976634556?= X-GMAIL-MSGID: =?utf-8?q?1747129403976634556?= From: Arnd Bergmann Going through the entries of recently removed machine types, I found these two that were removed a long time ago. Cc: Nicolas Ferre Cc: Alexandre Belloni Cc: Claudiu Beznea Signed-off-by: Arnd Bergmann Acked-by: Nicolas Ferre --- MAINTAINERS | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index cf0f18502372..aedb7c008dd6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1798,16 +1798,6 @@ M: Lennert Buytenhek L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained -ARM/AFEB9260 MACHINE SUPPORT -M: Sergey Lapin -L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -S: Maintained - -ARM/AJECO 1ARM MACHINE SUPPORT -M: Lennert Buytenhek -L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -S: Maintained - ARM/Allwinner SoC Clock Support M: Emilio López S: Maintained From patchwork Wed Oct 19 15:03:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Arnd Bergmann X-Patchwork-Id: 5671 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp383046wrs; Wed, 19 Oct 2022 08:17:50 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5nmfcGF2TRDJrrsP4lMvNPrP6JY9XG1L46R3EI6H/uLgibT/e/KeXmS9ApHhUEgJ0YehXe X-Received: by 2002:a17:906:5dcc:b0:78d:fb98:6f85 with SMTP id p12-20020a1709065dcc00b0078dfb986f85mr7355893ejv.123.1666192670619; Wed, 19 Oct 2022 08:17:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666192670; cv=none; d=google.com; s=arc-20160816; b=Utktcq1O73lSDfV46UC9OWxiwvxOBU6ykzXELAsFpRCQo4RT5cLkPOptf7rqNtcret 8/wYEmQu48edo5aTiJrmGFGIYyZWZ0+q07tcyFyRYSb4o31x8hS5/3HzBumY6oFe4Plr zuFiV9KWrdt147D1OQlNNkRH2yiyX640rxlnMeLQjFR3TMaRvDQvpGyOzX+X4SznPbSZ LrSs771a7uVdQHa6OUHTPinbq/vqG2uMC2avo6S/lyD4nWJfEgqiAJ8auHHy0gFV4I4o mPm2/f80aKodp3YJGBNv6bqaadllYK1b0G8/qp5EqkJls6mrGi8ICIIpKGcgmNV4yPvP oZ7g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=onYO6Q74c+XZAKSA4g3QwYUfz0Z7azDfixfGJvbbY8g=; b=AR3umpwOc+aUWubOetdNdK9mj4rx8GrrmlOydP9c0e2xItb0JlucXzt7ddZRyVHIjp PLQl0Bf+rJnZCOQuo5kjNc/3tVViwZ8wHC2gKDV/0MQQ9k7XzAeKf3d7pGJutYeuEy4U 2lKBMN5EklUQ84PiOwPyHYhVlhLgsmNlr+edl3xpkvoAk/3xchfYH0/V65phAMtXc4XN UDyH8/BE08+OUz/bVT53eXif81M4s/L8eKnVVj01S4b8UdqwK5ZrsouxMIHPm2seiZCF 9JDH5Ux2pF80MZc0SsUFKePgriKEJe8eCpMg5j3mOLICcRxtytHY5e32Lq6NOT2m+Pcz o5wA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=eZE0Pnfi; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id a6-20020a50ff06000000b004571c47b13csi11918568edu.418.2022.10.19.08.17.21; Wed, 19 Oct 2022 08:17:50 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=eZE0Pnfi; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230187AbiJSPQI (ORCPT + 99 others); Wed, 19 Oct 2022 11:16:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50268 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229880AbiJSPPZ (ORCPT ); Wed, 19 Oct 2022 11:15:25 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0C2001CC3E0; Wed, 19 Oct 2022 08:08:48 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 36898B824BE; Wed, 19 Oct 2022 15:06:29 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 61F84C433C1; Wed, 19 Oct 2022 15:06:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1666191988; bh=4pCJEeZb9At0qC25isWEQsNZ7PwhOjcprL1uawADWYE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=eZE0PnfiZgUyFjdWm+njdB1i7IgSohW+6/Nex5KqYLwrMNWv6HOj7UNG5yM3TwJcV 9kZlHnR4Wob0u521frHYecqUmBg7wLrr3vzm3P1w1PTQQMUkm8fxuCtQCkAVbOtV7v mzvbU/bIy0ZHpf4JVkD/NEvzn1eGeclqOj85e87emrvdKoBE5CMbl0RYN44Gv9pa1X TnrJOsXGp+eRpH0chaoDc2UwVA1ocl2+0lFeJULbu+bJ9zitF6ESe95NN2DUoTM/aP JzATNWLoUN2rK6zTrvBiNZiiPfLllju8Zg0GN7NcSMJ8YsBLAvSGfDQNeKAqBo0YxB xERG7115RbZcw== From: Arnd Bergmann To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Arnd Bergmann , Krzysztof Halasa , linux-usb@vger.kernel.org Subject: [PATCH 02/17] ARM: cns3xxx: remove entire platform Date: Wed, 19 Oct 2022 17:03:24 +0200 Message-Id: <20221019150410.3851944-2-arnd@kernel.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20221019150410.3851944-1-arnd@kernel.org> References: <20221019144119.3848027-1-arnd@kernel.org> <20221019150410.3851944-1-arnd@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747129645645576273?= X-GMAIL-MSGID: =?utf-8?q?1747129645645576273?= From: Arnd Bergmann cns3xxx was marked as unused a while ago, and gets removed entirely now. Cc: Krzysztof Halasa Signed-off-by: Arnd Bergmann Acked-by: Krzysztof Hałasa --- MAINTAINERS | 5 - arch/arm/Kconfig | 2 - arch/arm/Kconfig.debug | 10 - arch/arm/Makefile | 1 - arch/arm/configs/cns3420vb_defconfig | 63 --- arch/arm/mach-cns3xxx/Kconfig | 21 - arch/arm/mach-cns3xxx/Makefile | 6 - arch/arm/mach-cns3xxx/cns3420vb.c | 252 ------------ arch/arm/mach-cns3xxx/cns3xxx.h | 593 --------------------------- arch/arm/mach-cns3xxx/core.c | 410 ------------------ arch/arm/mach-cns3xxx/core.h | 32 -- arch/arm/mach-cns3xxx/devices.c | 108 ----- arch/arm/mach-cns3xxx/devices.h | 17 - arch/arm/mach-cns3xxx/pcie.c | 290 ------------- arch/arm/mach-cns3xxx/pm.c | 120 ------ arch/arm/mach-cns3xxx/pm.h | 20 - drivers/usb/host/Kconfig | 23 -- 17 files changed, 1973 deletions(-) delete mode 100644 arch/arm/configs/cns3420vb_defconfig delete mode 100644 arch/arm/mach-cns3xxx/Kconfig delete mode 100644 arch/arm/mach-cns3xxx/Makefile delete mode 100644 arch/arm/mach-cns3xxx/cns3420vb.c delete mode 100644 arch/arm/mach-cns3xxx/cns3xxx.h delete mode 100644 arch/arm/mach-cns3xxx/core.c delete mode 100644 arch/arm/mach-cns3xxx/core.h delete mode 100644 arch/arm/mach-cns3xxx/devices.c delete mode 100644 arch/arm/mach-cns3xxx/devices.h delete mode 100644 arch/arm/mach-cns3xxx/pcie.c delete mode 100644 arch/arm/mach-cns3xxx/pm.c delete mode 100644 arch/arm/mach-cns3xxx/pm.h diff --git a/MAINTAINERS b/MAINTAINERS index aedb7c008dd6..57b74156df3a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1984,11 +1984,6 @@ F: arch/arm/boot/dts/ecx-*.dts* F: arch/arm/boot/dts/highbank.dts F: arch/arm/mach-highbank/ -ARM/CAVIUM NETWORKS CNS3XXX MACHINE SUPPORT -M: Krzysztof Halasa -S: Maintained -F: arch/arm/mach-cns3xxx/ - ARM/CAVIUM THUNDER NETWORK DRIVER M: Sunil Goutham L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index a08c9d092a33..e58dab0303e6 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -433,8 +433,6 @@ source "arch/arm/mach-berlin/Kconfig" source "arch/arm/mach-clps711x/Kconfig" -source "arch/arm/mach-cns3xxx/Kconfig" - source "arch/arm/mach-davinci/Kconfig" source "arch/arm/mach-digicolor/Kconfig" diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index c345775f035b..3b11e1d04625 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -307,14 +307,6 @@ choice Say Y here if you want the debug print routines to direct their output to the second serial port on these devices. - config DEBUG_CNS3XXX - bool "Kernel Kernel low-level debugging on Cavium Networks CNS3xxx" - depends on ARCH_CNS3XXX - select DEBUG_UART_8250 - help - Say Y here if you want the debug print routines to direct - their output to the CNS3xxx UART0. - config DEBUG_DAVINCI_DA8XX_UART1 bool "Kernel low-level debugging on DaVinci DA8XX using UART1" depends on ARCH_DAVINCI_DA8XX @@ -1685,7 +1677,6 @@ config DEBUG_UART_PHYS DEBUG_S3C2410_UART1) default 0x50008000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART2 || \ DEBUG_S3C2410_UART2) - default 0x78000000 if DEBUG_CNS3XXX default 0x7c0003f8 if DEBUG_FOOTBRIDGE_COM1 default 0x7f005000 if DEBUG_S3C64XX_UART && DEBUG_S3C_UART0 default 0x7f005400 if DEBUG_S3C64XX_UART && DEBUG_S3C_UART1 @@ -1818,7 +1809,6 @@ config DEBUG_UART_VIRT DEBUG_OMAP4UART2 || DEBUG_OMAP5UART2 default 0xfa06e000 if DEBUG_OMAP2UART3 || DEBUG_OMAP4UART4 default 0xfa71e000 if DEBUG_QCOM_UARTDM - default 0xfb002000 if DEBUG_CNS3XXX default 0xfb009000 if DEBUG_REALVIEW_STD_PORT default 0xfb00c000 if DEBUG_AT91_SAMA5D4_USART3 default 0xfb020000 if DEBUG_OMAP3UART3 diff --git a/arch/arm/Makefile b/arch/arm/Makefile index c846119c448f..beda22911feb 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -169,7 +169,6 @@ machine-$(CONFIG_ARCH_AXXIA) += axxia machine-$(CONFIG_ARCH_BCM) += bcm machine-$(CONFIG_ARCH_BERLIN) += berlin machine-$(CONFIG_ARCH_CLPS711X) += clps711x -machine-$(CONFIG_ARCH_CNS3XXX) += cns3xxx machine-$(CONFIG_ARCH_DAVINCI) += davinci machine-$(CONFIG_ARCH_DIGICOLOR) += digicolor machine-$(CONFIG_ARCH_DOVE) += dove diff --git a/arch/arm/configs/cns3420vb_defconfig b/arch/arm/configs/cns3420vb_defconfig deleted file mode 100644 index b3aab97c0728..000000000000 --- a/arch/arm/configs/cns3420vb_defconfig +++ /dev/null @@ -1,63 +0,0 @@ -# CONFIG_LOCALVERSION_AUTO is not set -CONFIG_SYSVIPC=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_CGROUPS=y -CONFIG_SYSFS_DEPRECATED_V2=y -CONFIG_RELAY=y -CONFIG_BLK_DEV_INITRD=y -# CONFIG_PERF_EVENTS is not set -CONFIG_PROFILING=y -CONFIG_ARCH_MULTI_V6=y -CONFIG_ARCH_CNS3XXX=y -CONFIG_MACH_CNS3420VB=y -CONFIG_UNUSED_BOARD_FILES=y -CONFIG_CMDLINE="console=ttyS0,38400 mem=128M root=/dev/mmcblk0p1 ro rootwait" -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_IOSCHED_BFQ=m -#CONFIG_ARCH_MULTI_V7 is not set -CONFIG_DEBUG_CNS3XXX=y -CONFIG_AEABI=y -# CONFIG_SWAP is not set -CONFIG_SLAB=y -CONFIG_MTD=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_AMDSTD=y -CONFIG_MTD_PHYSMAP=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=20000 -CONFIG_BLK_DEV_SD=y -# CONFIG_BLK_DEV_BSG is not set -CONFIG_ATA=y -# CONFIG_SATA_PMP is not set -# CONFIG_ATA_SFF is not set -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set -CONFIG_LEGACY_PTY_COUNT=16 -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -# CONFIG_HW_RANDOM is not set -# CONFIG_HWMON is not set -# CONFIG_VGA_CONSOLE is not set -# CONFIG_USB_SUPPORT is not set -CONFIG_MMC=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_PLTFM=y -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -CONFIG_AUTOFS4_FS=y -CONFIG_FSCACHE=y -CONFIG_TMPFS=y -# CONFIG_ENABLE_MUST_CHECK is not set -# CONFIG_ARM_UNWIND is not set -CONFIG_CRC_CCITT=y -CONFIG_DEBUG_FS=y diff --git a/arch/arm/mach-cns3xxx/Kconfig b/arch/arm/mach-cns3xxx/Kconfig deleted file mode 100644 index 1f85deff2486..000000000000 --- a/arch/arm/mach-cns3xxx/Kconfig +++ /dev/null @@ -1,21 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -menuconfig ARCH_CNS3XXX - bool "Cavium Networks CNS3XXX family" - depends on ARCH_MULTI_V6 - depends on ATAGS && UNUSED_BOARD_FILES - select ARM_GIC - help - Support for Cavium Networks CNS3XXX platform. - -if ARCH_CNS3XXX - -config MACH_CNS3420VB - bool "Support for CNS3420 Validation Board" - depends on ATAGS - help - Include support for the Cavium Networks CNS3420 MPCore Platform - Baseboard. - This is a platform with an on-board ARM11 MPCore and has support - for USB, USB-OTG, MMC/SD/SDIO, SATA, PCI-E, etc. - -endif diff --git a/arch/arm/mach-cns3xxx/Makefile b/arch/arm/mach-cns3xxx/Makefile deleted file mode 100644 index 52ca6ed62304..000000000000 --- a/arch/arm/mach-cns3xxx/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -obj-$(CONFIG_ARCH_CNS3XXX) += cns3xxx.o -cns3xxx-y += core.o pm.o -cns3xxx-$(CONFIG_ATAGS) += devices.o -cns3xxx-$(CONFIG_PCI) += pcie.o -cns3xxx-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o diff --git a/arch/arm/mach-cns3xxx/cns3420vb.c b/arch/arm/mach-cns3xxx/cns3420vb.c deleted file mode 100644 index 9099560aa462..000000000000 --- a/arch/arm/mach-cns3xxx/cns3420vb.c +++ /dev/null @@ -1,252 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Cavium Networks CNS3420 Validation Board - * - * Copyright 2000 Deep Blue Solutions Ltd - * Copyright 2008 ARM Limited - * Copyright 2008 Cavium Networks - * Scott Shu - * Copyright 2010 MontaVista Software, LLC. - * Anton Vorontsov - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "cns3xxx.h" -#include "pm.h" -#include "core.h" -#include "devices.h" - -/* - * NOR Flash - */ -static struct mtd_partition cns3420_nor_partitions[] = { - { - .name = "uboot", - .size = 0x00040000, - .offset = 0, - .mask_flags = MTD_WRITEABLE, - }, { - .name = "kernel", - .size = 0x004C0000, - .offset = MTDPART_OFS_APPEND, - }, { - .name = "filesystem", - .size = 0x7000000, - .offset = MTDPART_OFS_APPEND, - }, { - .name = "filesystem2", - .size = 0x0AE0000, - .offset = MTDPART_OFS_APPEND, - }, { - .name = "ubootenv", - .size = MTDPART_SIZ_FULL, - .offset = MTDPART_OFS_APPEND, - }, -}; - -static struct physmap_flash_data cns3420_nor_pdata = { - .width = 2, - .parts = cns3420_nor_partitions, - .nr_parts = ARRAY_SIZE(cns3420_nor_partitions), -}; - -static struct resource cns3420_nor_res = { - .start = CNS3XXX_FLASH_BASE, - .end = CNS3XXX_FLASH_BASE + SZ_128M - 1, - .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT, -}; - -static struct platform_device cns3420_nor_pdev = { - .name = "physmap-flash", - .id = 0, - .resource = &cns3420_nor_res, - .num_resources = 1, - .dev = { - .platform_data = &cns3420_nor_pdata, - }, -}; - -/* - * UART - */ -static void __init cns3420_early_serial_setup(void) -{ -#ifdef CONFIG_SERIAL_8250_CONSOLE - static struct uart_port cns3420_serial_port = { - .membase = (void __iomem *)CNS3XXX_UART0_BASE_VIRT, - .mapbase = CNS3XXX_UART0_BASE, - .irq = IRQ_CNS3XXX_UART0, - .iotype = UPIO_MEM, - .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE, - .regshift = 2, - .uartclk = 24000000, - .line = 0, - .type = PORT_16550A, - .fifosize = 16, - }; - - early_serial_setup(&cns3420_serial_port); -#endif -} - -/* - * USB - */ -static struct resource cns3xxx_usb_ehci_resources[] = { - [0] = { - .start = CNS3XXX_USB_BASE, - .end = CNS3XXX_USB_BASE + SZ_16M - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_CNS3XXX_USB_EHCI, - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 cns3xxx_usb_ehci_dma_mask = DMA_BIT_MASK(32); - -static int csn3xxx_usb_power_on(struct platform_device *pdev) -{ - /* - * EHCI and OHCI share the same clock and power, - * resetting twice would cause the 1st controller been reset. - * Therefore only do power up at the first up device, and - * power down at the last down device. - * - * Set USB AHB INCR length to 16 - */ - if (atomic_inc_return(&usb_pwr_ref) == 1) { - cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB); - cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST); - cns3xxx_pwr_soft_rst(1 << PM_SOFT_RST_REG_OFFST_USB_HOST); - __raw_writel((__raw_readl(MISC_CHIP_CONFIG_REG) | (0X2 << 24)), - MISC_CHIP_CONFIG_REG); - } - - return 0; -} - -static void csn3xxx_usb_power_off(struct platform_device *pdev) -{ - /* - * EHCI and OHCI share the same clock and power, - * resetting twice would cause the 1st controller been reset. - * Therefore only do power up at the first up device, and - * power down at the last down device. - */ - if (atomic_dec_return(&usb_pwr_ref) == 0) - cns3xxx_pwr_clk_dis(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST); -} - -static struct usb_ehci_pdata cns3xxx_usb_ehci_pdata = { - .power_on = csn3xxx_usb_power_on, - .power_off = csn3xxx_usb_power_off, -}; - -static struct platform_device cns3xxx_usb_ehci_device = { - .name = "ehci-platform", - .num_resources = ARRAY_SIZE(cns3xxx_usb_ehci_resources), - .resource = cns3xxx_usb_ehci_resources, - .dev = { - .dma_mask = &cns3xxx_usb_ehci_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = &cns3xxx_usb_ehci_pdata, - }, -}; - -static struct resource cns3xxx_usb_ohci_resources[] = { - [0] = { - .start = CNS3XXX_USB_OHCI_BASE, - .end = CNS3XXX_USB_OHCI_BASE + SZ_16M - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_CNS3XXX_USB_OHCI, - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 cns3xxx_usb_ohci_dma_mask = DMA_BIT_MASK(32); - -static struct usb_ohci_pdata cns3xxx_usb_ohci_pdata = { - .num_ports = 1, - .power_on = csn3xxx_usb_power_on, - .power_off = csn3xxx_usb_power_off, -}; - -static struct platform_device cns3xxx_usb_ohci_device = { - .name = "ohci-platform", - .num_resources = ARRAY_SIZE(cns3xxx_usb_ohci_resources), - .resource = cns3xxx_usb_ohci_resources, - .dev = { - .dma_mask = &cns3xxx_usb_ohci_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = &cns3xxx_usb_ohci_pdata, - }, -}; - -/* - * Initialization - */ -static struct platform_device *cns3420_pdevs[] __initdata = { - &cns3420_nor_pdev, - &cns3xxx_usb_ehci_device, - &cns3xxx_usb_ohci_device, -}; - -static void __init cns3420_init(void) -{ - cns3xxx_l2x0_init(); - - platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs)); - - cns3xxx_ahci_init(); - cns3xxx_sdhci_init(); - - pm_power_off = cns3xxx_power_off; -} - -static struct map_desc cns3420_io_desc[] __initdata = { - { - .virtual = CNS3XXX_UART0_BASE_VIRT, - .pfn = __phys_to_pfn(CNS3XXX_UART0_BASE), - .length = SZ_4K, - .type = MT_DEVICE, - }, -}; - -static void __init cns3420_map_io(void) -{ - cns3xxx_map_io(); - iotable_init(cns3420_io_desc, ARRAY_SIZE(cns3420_io_desc)); - - cns3420_early_serial_setup(); -} - -MACHINE_START(CNS3420VB, "Cavium Networks CNS3420 Validation Board") - .atag_offset = 0x100, - .map_io = cns3420_map_io, - .init_irq = cns3xxx_init_irq, - .init_time = cns3xxx_timer_init, - .init_machine = cns3420_init, - .init_late = cns3xxx_pcie_init_late, - .restart = cns3xxx_restart, -MACHINE_END diff --git a/arch/arm/mach-cns3xxx/cns3xxx.h b/arch/arm/mach-cns3xxx/cns3xxx.h deleted file mode 100644 index cbb105a74f90..000000000000 --- a/arch/arm/mach-cns3xxx/cns3xxx.h +++ /dev/null @@ -1,593 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2008 Cavium Networks - */ - -#ifndef __MACH_BOARD_CNS3XXXH -#define __MACH_BOARD_CNS3XXXH - -/* - * Memory map - */ -#define CNS3XXX_FLASH_BASE 0x10000000 /* Flash/SRAM Memory Bank 0 */ -#define CNS3XXX_FLASH_SIZE SZ_256M - -#define CNS3XXX_DDR2SDRAM_BASE 0x20000000 /* DDR2 SDRAM Memory */ - -#define CNS3XXX_SPI_FLASH_BASE 0x60000000 /* SPI Serial Flash Memory */ - -#define CNS3XXX_SWITCH_BASE 0x70000000 /* Switch and HNAT Control */ - -#define CNS3XXX_PPE_BASE 0x70001000 /* HANT */ - -#define CNS3XXX_EMBEDDED_SRAM_BASE 0x70002000 /* HANT Embedded SRAM */ - -#define CNS3XXX_SSP_BASE 0x71000000 /* Synchronous Serial Port - SPI/PCM/I2C */ - -#define CNS3XXX_DMC_BASE 0x72000000 /* DMC Control (DDR2 SDRAM) */ - -#define CNS3XXX_SMC_BASE 0x73000000 /* SMC Control */ - -#define SMC_MEMC_STATUS_OFFSET 0x000 -#define SMC_MEMIF_CFG_OFFSET 0x004 -#define SMC_MEMC_CFG_SET_OFFSET 0x008 -#define SMC_MEMC_CFG_CLR_OFFSET 0x00C -#define SMC_DIRECT_CMD_OFFSET 0x010 -#define SMC_SET_CYCLES_OFFSET 0x014 -#define SMC_SET_OPMODE_OFFSET 0x018 -#define SMC_REFRESH_PERIOD_0_OFFSET 0x020 -#define SMC_REFRESH_PERIOD_1_OFFSET 0x024 -#define SMC_SRAM_CYCLES0_0_OFFSET 0x100 -#define SMC_NAND_CYCLES0_0_OFFSET 0x100 -#define SMC_OPMODE0_0_OFFSET 0x104 -#define SMC_SRAM_CYCLES0_1_OFFSET 0x120 -#define SMC_NAND_CYCLES0_1_OFFSET 0x120 -#define SMC_OPMODE0_1_OFFSET 0x124 -#define SMC_USER_STATUS_OFFSET 0x200 -#define SMC_USER_CONFIG_OFFSET 0x204 -#define SMC_ECC_STATUS_OFFSET 0x300 -#define SMC_ECC_MEMCFG_OFFSET 0x304 -#define SMC_ECC_MEMCOMMAND1_OFFSET 0x308 -#define SMC_ECC_MEMCOMMAND2_OFFSET 0x30C -#define SMC_ECC_ADDR0_OFFSET 0x310 -#define SMC_ECC_ADDR1_OFFSET 0x314 -#define SMC_ECC_VALUE0_OFFSET 0x318 -#define SMC_ECC_VALUE1_OFFSET 0x31C -#define SMC_ECC_VALUE2_OFFSET 0x320 -#define SMC_ECC_VALUE3_OFFSET 0x324 -#define SMC_PERIPH_ID_0_OFFSET 0xFE0 -#define SMC_PERIPH_ID_1_OFFSET 0xFE4 -#define SMC_PERIPH_ID_2_OFFSET 0xFE8 -#define SMC_PERIPH_ID_3_OFFSET 0xFEC -#define SMC_PCELL_ID_0_OFFSET 0xFF0 -#define SMC_PCELL_ID_1_OFFSET 0xFF4 -#define SMC_PCELL_ID_2_OFFSET 0xFF8 -#define SMC_PCELL_ID_3_OFFSET 0xFFC - -#define CNS3XXX_GPIOA_BASE 0x74000000 /* GPIO port A */ - -#define CNS3XXX_GPIOB_BASE 0x74800000 /* GPIO port B */ - -#define CNS3XXX_RTC_BASE 0x75000000 /* Real Time Clock */ - -#define RTC_SEC_OFFSET 0x00 -#define RTC_MIN_OFFSET 0x04 -#define RTC_HOUR_OFFSET 0x08 -#define RTC_DAY_OFFSET 0x0C -#define RTC_SEC_ALM_OFFSET 0x10 -#define RTC_MIN_ALM_OFFSET 0x14 -#define RTC_HOUR_ALM_OFFSET 0x18 -#define RTC_REC_OFFSET 0x1C -#define RTC_CTRL_OFFSET 0x20 -#define RTC_INTR_STS_OFFSET 0x34 - -#define CNS3XXX_MISC_BASE 0x76000000 /* Misc Control */ -#define CNS3XXX_MISC_BASE_VIRT 0xFB000000 /* Misc Control */ - -#define CNS3XXX_PM_BASE 0x77000000 /* Power Management Control */ -#define CNS3XXX_PM_BASE_VIRT 0xFB001000 - -#define PM_CLK_GATE_OFFSET 0x00 -#define PM_SOFT_RST_OFFSET 0x04 -#define PM_HS_CFG_OFFSET 0x08 -#define PM_CACTIVE_STA_OFFSET 0x0C -#define PM_PWR_STA_OFFSET 0x10 -#define PM_SYS_CLK_CTRL_OFFSET 0x14 -#define PM_PLL_LCD_I2S_CTRL_OFFSET 0x18 -#define PM_PLL_HM_PD_OFFSET 0x1C - -#define CNS3XXX_UART0_BASE 0x78000000 /* UART 0 */ -#define CNS3XXX_UART0_BASE_VIRT 0xFB002000 - -#define CNS3XXX_UART1_BASE 0x78400000 /* UART 1 */ - -#define CNS3XXX_UART2_BASE 0x78800000 /* UART 2 */ - -#define CNS3XXX_DMAC_BASE 0x79000000 /* Generic DMA Control */ - -#define CNS3XXX_CORESIGHT_BASE 0x7A000000 /* CoreSight */ - -#define CNS3XXX_CRYPTO_BASE 0x7B000000 /* Crypto */ - -#define CNS3XXX_I2S_BASE 0x7C000000 /* I2S */ - -#define CNS3XXX_TIMER1_2_3_BASE 0x7C800000 /* Timer */ -#define CNS3XXX_TIMER1_2_3_BASE_VIRT 0xFB003000 - -#define TIMER1_COUNTER_OFFSET 0x00 -#define TIMER1_AUTO_RELOAD_OFFSET 0x04 -#define TIMER1_MATCH_V1_OFFSET 0x08 -#define TIMER1_MATCH_V2_OFFSET 0x0C - -#define TIMER2_COUNTER_OFFSET 0x10 -#define TIMER2_AUTO_RELOAD_OFFSET 0x14 -#define TIMER2_MATCH_V1_OFFSET 0x18 -#define TIMER2_MATCH_V2_OFFSET 0x1C - -#define TIMER1_2_CONTROL_OFFSET 0x30 -#define TIMER1_2_INTERRUPT_STATUS_OFFSET 0x34 -#define TIMER1_2_INTERRUPT_MASK_OFFSET 0x38 - -#define TIMER_FREERUN_OFFSET 0x40 -#define TIMER_FREERUN_CONTROL_OFFSET 0x44 - -#define CNS3XXX_HCIE_BASE 0x7D000000 /* HCIE Control */ - -#define CNS3XXX_RAID_BASE 0x7E000000 /* RAID Control */ - -#define CNS3XXX_AXI_IXC_BASE 0x7F000000 /* AXI IXC */ - -#define CNS3XXX_CLCD_BASE 0x80000000 /* LCD Control */ - -#define CNS3XXX_USBOTG_BASE 0x81000000 /* USB OTG Control */ - -#define CNS3XXX_USB_BASE 0x82000000 /* USB Host Control */ - -#define CNS3XXX_SATA2_BASE 0x83000000 /* SATA */ -#define CNS3XXX_SATA2_SIZE SZ_16M - -#define CNS3XXX_CAMERA_BASE 0x84000000 /* Camera Interface */ - -#define CNS3XXX_SDIO_BASE 0x85000000 /* SDIO */ - -#define CNS3XXX_I2S_TDM_BASE 0x86000000 /* I2S TDM */ - -#define CNS3XXX_2DG_BASE 0x87000000 /* 2D Graphic Control */ - -#define CNS3XXX_USB_OHCI_BASE 0x88000000 /* USB OHCI */ - -#define CNS3XXX_L2C_BASE 0x92000000 /* L2 Cache Control */ - -#define CNS3XXX_PCIE0_MEM_BASE 0xA0000000 /* PCIe Port 0 IO/Memory Space */ - -#define CNS3XXX_PCIE0_HOST_BASE 0xAB000000 /* PCIe Port 0 RC Base */ -#define CNS3XXX_PCIE0_HOST_BASE_VIRT 0xE1000000 - -#define CNS3XXX_PCIE0_IO_BASE 0xAC000000 /* PCIe Port 0 */ - -#define CNS3XXX_PCIE0_CFG0_BASE 0xAD000000 /* PCIe Port 0 CFG Type 0 */ -#define CNS3XXX_PCIE0_CFG0_BASE_VIRT 0xE3000000 - -#define CNS3XXX_PCIE0_CFG1_BASE 0xAE000000 /* PCIe Port 0 CFG Type 1 */ -#define CNS3XXX_PCIE0_CFG1_BASE_VIRT 0xE4000000 - -#define CNS3XXX_PCIE0_MSG_BASE 0xAF000000 /* PCIe Port 0 Message Space */ - -#define CNS3XXX_PCIE1_MEM_BASE 0xB0000000 /* PCIe Port 1 IO/Memory Space */ - -#define CNS3XXX_PCIE1_HOST_BASE 0xBB000000 /* PCIe Port 1 RC Base */ -#define CNS3XXX_PCIE1_HOST_BASE_VIRT 0xE9000000 - -#define CNS3XXX_PCIE1_IO_BASE 0xBC000000 /* PCIe Port 1 */ - -#define CNS3XXX_PCIE1_CFG0_BASE 0xBD000000 /* PCIe Port 1 CFG Type 0 */ -#define CNS3XXX_PCIE1_CFG0_BASE_VIRT 0xEB000000 - -#define CNS3XXX_PCIE1_CFG1_BASE 0xBE000000 /* PCIe Port 1 CFG Type 1 */ -#define CNS3XXX_PCIE1_CFG1_BASE_VIRT 0xEC000000 - -#define CNS3XXX_PCIE1_MSG_BASE 0xBF000000 /* PCIe Port 1 Message Space */ - -/* - * Testchip peripheral and fpga gic regions - */ -#define CNS3XXX_TC11MP_SCU_BASE 0x90000000 /* IRQ, Test chip */ -#define CNS3XXX_TC11MP_SCU_BASE_VIRT 0xFB004000 - -#define CNS3XXX_TC11MP_GIC_CPU_BASE 0x90000100 /* Test chip interrupt controller CPU interface */ -#define CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x100) - -#define CNS3XXX_TC11MP_TWD_BASE 0x90000600 -#define CNS3XXX_TC11MP_TWD_BASE_VIRT (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x600) - -#define CNS3XXX_TC11MP_GIC_DIST_BASE 0x90001000 /* Test chip interrupt controller distributor */ -#define CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x1000) - -#define CNS3XXX_TC11MP_L220_BASE 0x92002000 /* L220 registers */ - -/* - * Misc block - */ -#define MISC_MEM_MAP(offs) (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + (offs)) - -#define MISC_MEMORY_REMAP_REG MISC_MEM_MAP(0x00) -#define MISC_CHIP_CONFIG_REG MISC_MEM_MAP(0x04) -#define MISC_DEBUG_PROBE_DATA_REG MISC_MEM_MAP(0x08) -#define MISC_DEBUG_PROBE_SELECTION_REG MISC_MEM_MAP(0x0C) -#define MISC_IO_PIN_FUNC_SELECTION_REG MISC_MEM_MAP(0x10) -#define MISC_GPIOA_PIN_ENABLE_REG MISC_MEM_MAP(0x14) -#define MISC_GPIOB_PIN_ENABLE_REG MISC_MEM_MAP(0x18) -#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_A MISC_MEM_MAP(0x1C) -#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_B MISC_MEM_MAP(0x20) -#define MISC_GPIOA_15_0_PULL_CTRL_REG MISC_MEM_MAP(0x24) -#define MISC_GPIOA_16_31_PULL_CTRL_REG MISC_MEM_MAP(0x28) -#define MISC_GPIOB_15_0_PULL_CTRL_REG MISC_MEM_MAP(0x2C) -#define MISC_GPIOB_16_31_PULL_CTRL_REG MISC_MEM_MAP(0x30) -#define MISC_IO_PULL_CTRL_REG MISC_MEM_MAP(0x34) -#define MISC_E_FUSE_31_0_REG MISC_MEM_MAP(0x40) -#define MISC_E_FUSE_63_32_REG MISC_MEM_MAP(0x44) -#define MISC_E_FUSE_95_64_REG MISC_MEM_MAP(0x48) -#define MISC_E_FUSE_127_96_REG MISC_MEM_MAP(0x4C) -#define MISC_SOFTWARE_TEST_1_REG MISC_MEM_MAP(0x50) -#define MISC_SOFTWARE_TEST_2_REG MISC_MEM_MAP(0x54) - -#define MISC_SATA_POWER_MODE MISC_MEM_MAP(0x310) - -#define MISC_USB_CFG_REG MISC_MEM_MAP(0x800) -#define MISC_USB_STS_REG MISC_MEM_MAP(0x804) -#define MISC_USBPHY00_CFG_REG MISC_MEM_MAP(0x808) -#define MISC_USBPHY01_CFG_REG MISC_MEM_MAP(0x80c) -#define MISC_USBPHY10_CFG_REG MISC_MEM_MAP(0x810) -#define MISC_USBPHY11_CFG_REG MISC_MEM_MAP(0x814) - -#define MISC_PCIEPHY_CMCTL(x) MISC_MEM_MAP(0x900 + (x) * 0x004) -#define MISC_PCIEPHY_CTL(x) MISC_MEM_MAP(0x940 + (x) * 0x100) -#define MISC_PCIE_AXIS_AWMISC(x) MISC_MEM_MAP(0x944 + (x) * 0x100) -#define MISC_PCIE_AXIS_ARMISC(x) MISC_MEM_MAP(0x948 + (x) * 0x100) -#define MISC_PCIE_AXIS_RMISC(x) MISC_MEM_MAP(0x94C + (x) * 0x100) -#define MISC_PCIE_AXIS_BMISC(x) MISC_MEM_MAP(0x950 + (x) * 0x100) -#define MISC_PCIE_AXIM_RMISC(x) MISC_MEM_MAP(0x954 + (x) * 0x100) -#define MISC_PCIE_AXIM_BMISC(x) MISC_MEM_MAP(0x958 + (x) * 0x100) -#define MISC_PCIE_CTRL(x) MISC_MEM_MAP(0x95C + (x) * 0x100) -#define MISC_PCIE_PM_DEBUG(x) MISC_MEM_MAP(0x960 + (x) * 0x100) -#define MISC_PCIE_RFC_DEBUG(x) MISC_MEM_MAP(0x964 + (x) * 0x100) -#define MISC_PCIE_CXPL_DEBUGL(x) MISC_MEM_MAP(0x968 + (x) * 0x100) -#define MISC_PCIE_CXPL_DEBUGH(x) MISC_MEM_MAP(0x96C + (x) * 0x100) -#define MISC_PCIE_DIAG_DEBUGH(x) MISC_MEM_MAP(0x970 + (x) * 0x100) -#define MISC_PCIE_W1CLR(x) MISC_MEM_MAP(0x974 + (x) * 0x100) -#define MISC_PCIE_INT_MASK(x) MISC_MEM_MAP(0x978 + (x) * 0x100) -#define MISC_PCIE_INT_STATUS(x) MISC_MEM_MAP(0x97C + (x) * 0x100) - -/* - * Power management and clock control - */ -#define PMU_MEM_MAP(offs) (void __iomem *)(CNS3XXX_PM_BASE_VIRT + (offs)) - -#define PM_CLK_GATE_REG PMU_MEM_MAP(0x000) -#define PM_SOFT_RST_REG PMU_MEM_MAP(0x004) -#define PM_HS_CFG_REG PMU_MEM_MAP(0x008) -#define PM_CACTIVE_STA_REG PMU_MEM_MAP(0x00C) -#define PM_PWR_STA_REG PMU_MEM_MAP(0x010) -#define PM_CLK_CTRL_REG PMU_MEM_MAP(0x014) -#define PM_PLL_LCD_I2S_CTRL_REG PMU_MEM_MAP(0x018) -#define PM_PLL_HM_PD_CTRL_REG PMU_MEM_MAP(0x01C) -#define PM_REGULAT_CTRL_REG PMU_MEM_MAP(0x020) -#define PM_WDT_CTRL_REG PMU_MEM_MAP(0x024) -#define PM_WU_CTRL0_REG PMU_MEM_MAP(0x028) -#define PM_WU_CTRL1_REG PMU_MEM_MAP(0x02C) -#define PM_CSR_REG PMU_MEM_MAP(0x030) - -/* PM_CLK_GATE_REG */ -#define PM_CLK_GATE_REG_OFFSET_SDIO (25) -#define PM_CLK_GATE_REG_OFFSET_GPU (24) -#define PM_CLK_GATE_REG_OFFSET_CIM (23) -#define PM_CLK_GATE_REG_OFFSET_LCDC (22) -#define PM_CLK_GATE_REG_OFFSET_I2S (21) -#define PM_CLK_GATE_REG_OFFSET_RAID (20) -#define PM_CLK_GATE_REG_OFFSET_SATA (19) -#define PM_CLK_GATE_REG_OFFSET_PCIE(x) (17 + (x)) -#define PM_CLK_GATE_REG_OFFSET_USB_HOST (16) -#define PM_CLK_GATE_REG_OFFSET_USB_OTG (15) -#define PM_CLK_GATE_REG_OFFSET_TIMER (14) -#define PM_CLK_GATE_REG_OFFSET_CRYPTO (13) -#define PM_CLK_GATE_REG_OFFSET_HCIE (12) -#define PM_CLK_GATE_REG_OFFSET_SWITCH (11) -#define PM_CLK_GATE_REG_OFFSET_GPIO (10) -#define PM_CLK_GATE_REG_OFFSET_UART3 (9) -#define PM_CLK_GATE_REG_OFFSET_UART2 (8) -#define PM_CLK_GATE_REG_OFFSET_UART1 (7) -#define PM_CLK_GATE_REG_OFFSET_RTC (5) -#define PM_CLK_GATE_REG_OFFSET_GDMA (4) -#define PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C (3) -#define PM_CLK_GATE_REG_OFFSET_SMC_NFI (1) -#define PM_CLK_GATE_REG_MASK (0x03FFFFBA) - -/* PM_SOFT_RST_REG */ -#define PM_SOFT_RST_REG_OFFST_WARM_RST_FLAG (31) -#define PM_SOFT_RST_REG_OFFST_CPU1 (29) -#define PM_SOFT_RST_REG_OFFST_CPU0 (28) -#define PM_SOFT_RST_REG_OFFST_SDIO (25) -#define PM_SOFT_RST_REG_OFFST_GPU (24) -#define PM_SOFT_RST_REG_OFFST_CIM (23) -#define PM_SOFT_RST_REG_OFFST_LCDC (22) -#define PM_SOFT_RST_REG_OFFST_I2S (21) -#define PM_SOFT_RST_REG_OFFST_RAID (20) -#define PM_SOFT_RST_REG_OFFST_SATA (19) -#define PM_SOFT_RST_REG_OFFST_PCIE(x) (17 + (x)) -#define PM_SOFT_RST_REG_OFFST_USB_HOST (16) -#define PM_SOFT_RST_REG_OFFST_USB_OTG (15) -#define PM_SOFT_RST_REG_OFFST_TIMER (14) -#define PM_SOFT_RST_REG_OFFST_CRYPTO (13) -#define PM_SOFT_RST_REG_OFFST_HCIE (12) -#define PM_SOFT_RST_REG_OFFST_SWITCH (11) -#define PM_SOFT_RST_REG_OFFST_GPIO (10) -#define PM_SOFT_RST_REG_OFFST_UART3 (9) -#define PM_SOFT_RST_REG_OFFST_UART2 (8) -#define PM_SOFT_RST_REG_OFFST_UART1 (7) -#define PM_SOFT_RST_REG_OFFST_RTC (5) -#define PM_SOFT_RST_REG_OFFST_GDMA (4) -#define PM_SOFT_RST_REG_OFFST_SPI_PCM_I2C (3) -#define PM_SOFT_RST_REG_OFFST_DMC (2) -#define PM_SOFT_RST_REG_OFFST_SMC_NFI (1) -#define PM_SOFT_RST_REG_OFFST_GLOBAL (0) -#define PM_SOFT_RST_REG_MASK (0xF3FFFFBF) - -/* PMHS_CFG_REG */ -#define PM_HS_CFG_REG_OFFSET_SDIO (25) -#define PM_HS_CFG_REG_OFFSET_GPU (24) -#define PM_HS_CFG_REG_OFFSET_CIM (23) -#define PM_HS_CFG_REG_OFFSET_LCDC (22) -#define PM_HS_CFG_REG_OFFSET_I2S (21) -#define PM_HS_CFG_REG_OFFSET_RAID (20) -#define PM_HS_CFG_REG_OFFSET_SATA (19) -#define PM_HS_CFG_REG_OFFSET_PCIE1 (18) -#define PM_HS_CFG_REG_OFFSET_PCIE0 (17) -#define PM_HS_CFG_REG_OFFSET_USB_HOST (16) -#define PM_HS_CFG_REG_OFFSET_USB_OTG (15) -#define PM_HS_CFG_REG_OFFSET_TIMER (14) -#define PM_HS_CFG_REG_OFFSET_CRYPTO (13) -#define PM_HS_CFG_REG_OFFSET_HCIE (12) -#define PM_HS_CFG_REG_OFFSET_SWITCH (11) -#define PM_HS_CFG_REG_OFFSET_GPIO (10) -#define PM_HS_CFG_REG_OFFSET_UART3 (9) -#define PM_HS_CFG_REG_OFFSET_UART2 (8) -#define PM_HS_CFG_REG_OFFSET_UART1 (7) -#define PM_HS_CFG_REG_OFFSET_RTC (5) -#define PM_HS_CFG_REG_OFFSET_GDMA (4) -#define PM_HS_CFG_REG_OFFSET_SPI_PCM_I2S (3) -#define PM_HS_CFG_REG_OFFSET_DMC (2) -#define PM_HS_CFG_REG_OFFSET_SMC_NFI (1) -#define PM_HS_CFG_REG_MASK (0x03FFFFBE) -#define PM_HS_CFG_REG_MASK_SUPPORT (0x01100806) - -/* PM_CACTIVE_STA_REG */ -#define PM_CACTIVE_STA_REG_OFFSET_SDIO (25) -#define PM_CACTIVE_STA_REG_OFFSET_GPU (24) -#define PM_CACTIVE_STA_REG_OFFSET_CIM (23) -#define PM_CACTIVE_STA_REG_OFFSET_LCDC (22) -#define PM_CACTIVE_STA_REG_OFFSET_I2S (21) -#define PM_CACTIVE_STA_REG_OFFSET_RAID (20) -#define PM_CACTIVE_STA_REG_OFFSET_SATA (19) -#define PM_CACTIVE_STA_REG_OFFSET_PCIE1 (18) -#define PM_CACTIVE_STA_REG_OFFSET_PCIE0 (17) -#define PM_CACTIVE_STA_REG_OFFSET_USB_HOST (16) -#define PM_CACTIVE_STA_REG_OFFSET_USB_OTG (15) -#define PM_CACTIVE_STA_REG_OFFSET_TIMER (14) -#define PM_CACTIVE_STA_REG_OFFSET_CRYPTO (13) -#define PM_CACTIVE_STA_REG_OFFSET_HCIE (12) -#define PM_CACTIVE_STA_REG_OFFSET_SWITCH (11) -#define PM_CACTIVE_STA_REG_OFFSET_GPIO (10) -#define PM_CACTIVE_STA_REG_OFFSET_UART3 (9) -#define PM_CACTIVE_STA_REG_OFFSET_UART2 (8) -#define PM_CACTIVE_STA_REG_OFFSET_UART1 (7) -#define PM_CACTIVE_STA_REG_OFFSET_RTC (5) -#define PM_CACTIVE_STA_REG_OFFSET_GDMA (4) -#define PM_CACTIVE_STA_REG_OFFSET_SPI_PCM_I2S (3) -#define PM_CACTIVE_STA_REG_OFFSET_DMC (2) -#define PM_CACTIVE_STA_REG_OFFSET_SMC_NFI (1) -#define PM_CACTIVE_STA_REG_MASK (0x03FFFFBE) - -/* PM_PWR_STA_REG */ -#define PM_PWR_STA_REG_REG_OFFSET_SDIO (25) -#define PM_PWR_STA_REG_REG_OFFSET_GPU (24) -#define PM_PWR_STA_REG_REG_OFFSET_CIM (23) -#define PM_PWR_STA_REG_REG_OFFSET_LCDC (22) -#define PM_PWR_STA_REG_REG_OFFSET_I2S (21) -#define PM_PWR_STA_REG_REG_OFFSET_RAID (20) -#define PM_PWR_STA_REG_REG_OFFSET_SATA (19) -#define PM_PWR_STA_REG_REG_OFFSET_PCIE1 (18) -#define PM_PWR_STA_REG_REG_OFFSET_PCIE0 (17) -#define PM_PWR_STA_REG_REG_OFFSET_USB_HOST (16) -#define PM_PWR_STA_REG_REG_OFFSET_USB_OTG (15) -#define PM_PWR_STA_REG_REG_OFFSET_TIMER (14) -#define PM_PWR_STA_REG_REG_OFFSET_CRYPTO (13) -#define PM_PWR_STA_REG_REG_OFFSET_HCIE (12) -#define PM_PWR_STA_REG_REG_OFFSET_SWITCH (11) -#define PM_PWR_STA_REG_REG_OFFSET_GPIO (10) -#define PM_PWR_STA_REG_REG_OFFSET_UART3 (9) -#define PM_PWR_STA_REG_REG_OFFSET_UART2 (8) -#define PM_PWR_STA_REG_REG_OFFSET_UART1 (7) -#define PM_PWR_STA_REG_REG_OFFSET_RTC (5) -#define PM_PWR_STA_REG_REG_OFFSET_GDMA (4) -#define PM_PWR_STA_REG_REG_OFFSET_SPI_PCM_I2S (3) -#define PM_PWR_STA_REG_REG_OFFSET_DMC (2) -#define PM_PWR_STA_REG_REG_OFFSET_SMC_NFI (1) -#define PM_PWR_STA_REG_REG_MASK (0x03FFFFBE) - -/* PM_CLK_CTRL_REG */ -#define PM_CLK_CTRL_REG_OFFSET_I2S_MCLK (31) -#define PM_CLK_CTRL_REG_OFFSET_DDR2_CHG_EN (30) -#define PM_CLK_CTRL_REG_OFFSET_PCIE_REF1_EN (29) -#define PM_CLK_CTRL_REG_OFFSET_PCIE_REF0_EN (28) -#define PM_CLK_CTRL_REG_OFFSET_TIMER_SIM_MODE (27) -#define PM_CLK_CTRL_REG_OFFSET_I2SCLK_DIV (24) -#define PM_CLK_CTRL_REG_OFFSET_I2SCLK_SEL (22) -#define PM_CLK_CTRL_REG_OFFSET_CLKOUT_DIV (20) -#define PM_CLK_CTRL_REG_OFFSET_CLKOUT_SEL (16) -#define PM_CLK_CTRL_REG_OFFSET_MDC_DIV (14) -#define PM_CLK_CTRL_REG_OFFSET_CRYPTO_CLK_SEL (12) -#define PM_CLK_CTRL_REG_OFFSET_CPU_PWR_MODE (9) -#define PM_CLK_CTRL_REG_OFFSET_PLL_DDR2_SEL (7) -#define PM_CLK_CTRL_REG_OFFSET_DIV_IMMEDIATE (6) -#define PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV (4) -#define PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL (0) - -#define PM_CPU_CLK_DIV(DIV) { \ - PM_CLK_CTRL_REG &= ~((0x3) << PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV); \ - PM_CLK_CTRL_REG |= (((DIV)&0x3) << PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV); \ -} - -#define PM_PLL_CPU_SEL(CPU) { \ - PM_CLK_CTRL_REG &= ~((0xF) << PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL); \ - PM_CLK_CTRL_REG |= (((CPU)&0xF) << PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL); \ -} - -/* PM_PLL_LCD_I2S_CTRL_REG */ -#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_MCLK_SMC_DIV (22) -#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_R_SEL (17) -#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_P (11) -#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_M (3) -#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_S (0) - -/* PM_PLL_HM_PD_CTRL_REG */ -#define PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1 (11) -#define PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0 (10) -#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_I2SCD (6) -#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_I2S (5) -#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_LCD (4) -#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB (3) -#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_RGMII (2) -#define PM_PLL_HM_PD_CTRL_REG_MASK (0x00000C7C) - -/* PM_WDT_CTRL_REG */ -#define PM_WDT_CTRL_REG_OFFSET_RESET_CPU_ONLY (0) - -/* PM_CSR_REG - Clock Scaling Register*/ -#define PM_CSR_REG_OFFSET_CSR_EN (30) -#define PM_CSR_REG_OFFSET_CSR_NUM (0) - -#define CNS3XXX_PWR_CLK_EN(BLOCK) (0x1< -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "cns3xxx.h" -#include "core.h" -#include "pm.h" - -static struct map_desc cns3xxx_io_desc[] __initdata = { - { - .virtual = CNS3XXX_TC11MP_SCU_BASE_VIRT, - .pfn = __phys_to_pfn(CNS3XXX_TC11MP_SCU_BASE), - .length = SZ_8K, - .type = MT_DEVICE, - }, { - .virtual = CNS3XXX_TIMER1_2_3_BASE_VIRT, - .pfn = __phys_to_pfn(CNS3XXX_TIMER1_2_3_BASE), - .length = SZ_4K, - .type = MT_DEVICE, - }, { - .virtual = CNS3XXX_MISC_BASE_VIRT, - .pfn = __phys_to_pfn(CNS3XXX_MISC_BASE), - .length = SZ_4K, - .type = MT_DEVICE, - }, { - .virtual = CNS3XXX_PM_BASE_VIRT, - .pfn = __phys_to_pfn(CNS3XXX_PM_BASE), - .length = SZ_4K, - .type = MT_DEVICE, -#ifdef CONFIG_PCI - }, { - .virtual = CNS3XXX_PCIE0_HOST_BASE_VIRT, - .pfn = __phys_to_pfn(CNS3XXX_PCIE0_HOST_BASE), - .length = SZ_4K, - .type = MT_DEVICE, - }, { - .virtual = CNS3XXX_PCIE0_CFG0_BASE_VIRT, - .pfn = __phys_to_pfn(CNS3XXX_PCIE0_CFG0_BASE), - .length = SZ_64K, /* really 4 KiB at offset 32 KiB */ - .type = MT_DEVICE, - }, { - .virtual = CNS3XXX_PCIE0_CFG1_BASE_VIRT, - .pfn = __phys_to_pfn(CNS3XXX_PCIE0_CFG1_BASE), - .length = SZ_16M, - .type = MT_DEVICE, - }, { - .virtual = CNS3XXX_PCIE1_HOST_BASE_VIRT, - .pfn = __phys_to_pfn(CNS3XXX_PCIE1_HOST_BASE), - .length = SZ_4K, - .type = MT_DEVICE, - }, { - .virtual = CNS3XXX_PCIE1_CFG0_BASE_VIRT, - .pfn = __phys_to_pfn(CNS3XXX_PCIE1_CFG0_BASE), - .length = SZ_64K, /* really 4 KiB at offset 32 KiB */ - .type = MT_DEVICE, - }, { - .virtual = CNS3XXX_PCIE1_CFG1_BASE_VIRT, - .pfn = __phys_to_pfn(CNS3XXX_PCIE1_CFG1_BASE), - .length = SZ_16M, - .type = MT_DEVICE, -#endif - }, -}; - -void __init cns3xxx_map_io(void) -{ - iotable_init(cns3xxx_io_desc, ARRAY_SIZE(cns3xxx_io_desc)); -} - -/* used by entry-macro.S */ -void __init cns3xxx_init_irq(void) -{ - gic_init(IOMEM(CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT), - IOMEM(CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT)); -} - -void cns3xxx_power_off(void) -{ - u32 __iomem *pm_base = IOMEM(CNS3XXX_PM_BASE_VIRT); - u32 clkctrl; - - printk(KERN_INFO "powering system down...\n"); - - clkctrl = readl(pm_base + PM_SYS_CLK_CTRL_OFFSET); - clkctrl &= 0xfffff1ff; - clkctrl |= (0x5 << 9); /* Hibernate */ - writel(clkctrl, pm_base + PM_SYS_CLK_CTRL_OFFSET); - -} - -/* - * Timer - */ -static void __iomem *cns3xxx_tmr1; - -static int cns3xxx_shutdown(struct clock_event_device *clk) -{ - writel(0, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); - return 0; -} - -static int cns3xxx_set_oneshot(struct clock_event_device *clk) -{ - unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); - - /* period set, and timer enabled in 'next_event' hook */ - ctrl |= (1 << 2) | (1 << 9); - writel(ctrl, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); - return 0; -} - -static int cns3xxx_set_periodic(struct clock_event_device *clk) -{ - unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); - int pclk = cns3xxx_cpu_clock() / 8; - int reload; - - reload = pclk * 20 / (3 * HZ) * 0x25000; - writel(reload, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET); - ctrl |= (1 << 0) | (1 << 2) | (1 << 9); - writel(ctrl, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); - return 0; -} - -static int cns3xxx_timer_set_next_event(unsigned long evt, - struct clock_event_device *unused) -{ - unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); - - writel(evt, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET); - writel(ctrl | (1 << 0), cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); - - return 0; -} - -static struct clock_event_device cns3xxx_tmr1_clockevent = { - .name = "cns3xxx timer1", - .features = CLOCK_EVT_FEAT_PERIODIC | - CLOCK_EVT_FEAT_ONESHOT, - .set_state_shutdown = cns3xxx_shutdown, - .set_state_periodic = cns3xxx_set_periodic, - .set_state_oneshot = cns3xxx_set_oneshot, - .tick_resume = cns3xxx_shutdown, - .set_next_event = cns3xxx_timer_set_next_event, - .rating = 350, - .cpumask = cpu_all_mask, -}; - -static void __init cns3xxx_clockevents_init(unsigned int timer_irq) -{ - cns3xxx_tmr1_clockevent.irq = timer_irq; - clockevents_config_and_register(&cns3xxx_tmr1_clockevent, - (cns3xxx_cpu_clock() >> 3) * 1000000, - 0xf, 0xffffffff); -} - -/* - * IRQ handler for the timer - */ -static irqreturn_t cns3xxx_timer_interrupt(int irq, void *dev_id) -{ - struct clock_event_device *evt = &cns3xxx_tmr1_clockevent; - u32 __iomem *stat = cns3xxx_tmr1 + TIMER1_2_INTERRUPT_STATUS_OFFSET; - u32 val; - - /* Clear the interrupt */ - val = readl(stat); - writel(val & ~(1 << 2), stat); - - evt->event_handler(evt); - - return IRQ_HANDLED; -} - -/* - * Set up the clock source and clock events devices - */ -static void __init __cns3xxx_timer_init(unsigned int timer_irq) -{ - u32 val; - u32 irq_mask; - - /* - * Initialise to a known state (all timers off) - */ - - /* disable timer1 and timer2 */ - writel(0, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); - /* stop free running timer3 */ - writel(0, cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET); - - /* timer1 */ - writel(0x5C800, cns3xxx_tmr1 + TIMER1_COUNTER_OFFSET); - writel(0x5C800, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET); - - writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V1_OFFSET); - writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V2_OFFSET); - - /* mask irq, non-mask timer1 overflow */ - irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET); - irq_mask &= ~(1 << 2); - irq_mask |= 0x03; - writel(irq_mask, cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET); - - /* down counter */ - val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); - val |= (1 << 9); - writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); - - /* timer2 */ - writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V1_OFFSET); - writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V2_OFFSET); - - /* mask irq */ - irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET); - irq_mask |= ((1 << 3) | (1 << 4) | (1 << 5)); - writel(irq_mask, cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET); - - /* down counter */ - val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); - val |= (1 << 10); - writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); - - /* Make irqs happen for the system timer */ - if (request_irq(timer_irq, cns3xxx_timer_interrupt, - IRQF_TIMER | IRQF_IRQPOLL, "timer", NULL)) - pr_err("Failed to request irq %d (timer)\n", timer_irq); - - cns3xxx_clockevents_init(timer_irq); -} - -void __init cns3xxx_timer_init(void) -{ - cns3xxx_tmr1 = IOMEM(CNS3XXX_TIMER1_2_3_BASE_VIRT); - - __cns3xxx_timer_init(IRQ_CNS3XXX_TIMER0); -} - -#ifdef CONFIG_CACHE_L2X0 - -void __init cns3xxx_l2x0_init(void) -{ - void __iomem *base = ioremap(CNS3XXX_L2C_BASE, SZ_4K); - u32 val; - - if (WARN_ON(!base)) - return; - - /* - * Tag RAM Control register - * - * bit[10:8] - 1 cycle of write accesses latency - * bit[6:4] - 1 cycle of read accesses latency - * bit[3:0] - 1 cycle of setup latency - * - * 1 cycle of latency for setup, read and write accesses - */ - val = readl(base + L310_TAG_LATENCY_CTRL); - val &= 0xfffff888; - writel(val, base + L310_TAG_LATENCY_CTRL); - - /* - * Data RAM Control register - * - * bit[10:8] - 1 cycles of write accesses latency - * bit[6:4] - 1 cycles of read accesses latency - * bit[3:0] - 1 cycle of setup latency - * - * 1 cycle of latency for setup, read and write accesses - */ - val = readl(base + L310_DATA_LATENCY_CTRL); - val &= 0xfffff888; - writel(val, base + L310_DATA_LATENCY_CTRL); - - /* 32 KiB, 8-way, parity disable */ - l2x0_init(base, 0x00500000, 0xfe0f0fff); -} - -#endif /* CONFIG_CACHE_L2X0 */ - -static int csn3xxx_usb_power_on(struct platform_device *pdev) -{ - /* - * EHCI and OHCI share the same clock and power, - * resetting twice would cause the 1st controller been reset. - * Therefore only do power up at the first up device, and - * power down at the last down device. - * - * Set USB AHB INCR length to 16 - */ - if (atomic_inc_return(&usb_pwr_ref) == 1) { - cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB); - cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST); - cns3xxx_pwr_soft_rst(1 << PM_SOFT_RST_REG_OFFST_USB_HOST); - __raw_writel((__raw_readl(MISC_CHIP_CONFIG_REG) | (0X2 << 24)), - MISC_CHIP_CONFIG_REG); - } - - return 0; -} - -static void csn3xxx_usb_power_off(struct platform_device *pdev) -{ - /* - * EHCI and OHCI share the same clock and power, - * resetting twice would cause the 1st controller been reset. - * Therefore only do power up at the first up device, and - * power down at the last down device. - */ - if (atomic_dec_return(&usb_pwr_ref) == 0) - cns3xxx_pwr_clk_dis(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST); -} - -static struct usb_ehci_pdata cns3xxx_usb_ehci_pdata = { - .power_on = csn3xxx_usb_power_on, - .power_off = csn3xxx_usb_power_off, -}; - -static struct usb_ohci_pdata cns3xxx_usb_ohci_pdata = { - .num_ports = 1, - .power_on = csn3xxx_usb_power_on, - .power_off = csn3xxx_usb_power_off, -}; - -static const struct of_dev_auxdata cns3xxx_auxdata[] __initconst = { - { "intel,usb-ehci", CNS3XXX_USB_BASE, "ehci-platform", &cns3xxx_usb_ehci_pdata }, - { "intel,usb-ohci", CNS3XXX_USB_OHCI_BASE, "ohci-platform", &cns3xxx_usb_ohci_pdata }, - { "cavium,cns3420-ahci", CNS3XXX_SATA2_BASE, "ahci", NULL }, - { "cavium,cns3420-sdhci", CNS3XXX_SDIO_BASE, "ahci", NULL }, - {}, -}; - -static void __init cns3xxx_init(void) -{ - struct device_node *dn; - - cns3xxx_l2x0_init(); - - dn = of_find_compatible_node(NULL, NULL, "cavium,cns3420-ahci"); - if (of_device_is_available(dn)) { - u32 tmp; - - tmp = __raw_readl(MISC_SATA_POWER_MODE); - tmp |= 0x1 << 16; /* Disable SATA PHY 0 from SLUMBER Mode */ - tmp |= 0x1 << 17; /* Disable SATA PHY 1 from SLUMBER Mode */ - __raw_writel(tmp, MISC_SATA_POWER_MODE); - - /* Enable SATA PHY */ - cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0); - cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1); - - /* Enable SATA Clock */ - cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_SATA); - - /* De-Asscer SATA Reset */ - cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SATA)); - } - of_node_put(dn); - - dn = of_find_compatible_node(NULL, NULL, "cavium,cns3420-sdhci"); - if (of_device_is_available(dn)) { - u32 __iomem *gpioa = IOMEM(CNS3XXX_MISC_BASE_VIRT + 0x0014); - u32 gpioa_pins = __raw_readl(gpioa); - - /* MMC/SD pins share with GPIOA */ - gpioa_pins |= 0x1fff0004; - __raw_writel(gpioa_pins, gpioa); - - cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SDIO)); - cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SDIO)); - } - of_node_put(dn); - - pm_power_off = cns3xxx_power_off; - - of_platform_default_populate(NULL, cns3xxx_auxdata, NULL); -} - -static const char *const cns3xxx_dt_compat[] __initconst = { - "cavium,cns3410", - "cavium,cns3420", - NULL, -}; - -DT_MACHINE_START(CNS3XXX_DT, "Cavium Networks CNS3xxx") - .dt_compat = cns3xxx_dt_compat, - .map_io = cns3xxx_map_io, - .init_irq = cns3xxx_init_irq, - .init_time = cns3xxx_timer_init, - .init_machine = cns3xxx_init, - .init_late = cns3xxx_pcie_init_late, - .restart = cns3xxx_restart, -MACHINE_END diff --git a/arch/arm/mach-cns3xxx/core.h b/arch/arm/mach-cns3xxx/core.h deleted file mode 100644 index a96eabaea301..000000000000 --- a/arch/arm/mach-cns3xxx/core.h +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2000 Deep Blue Solutions Ltd - * Copyright 2004 ARM Limited - * Copyright 2008 Cavium Networks - */ - -#ifndef __CNS3XXX_CORE_H -#define __CNS3XXX_CORE_H - -#include - -extern void cns3xxx_timer_init(void); - -#ifdef CONFIG_CACHE_L2X0 -void __init cns3xxx_l2x0_init(void); -#else -static inline void cns3xxx_l2x0_init(void) {} -#endif /* CONFIG_CACHE_L2X0 */ - -#ifdef CONFIG_PCI -extern void __init cns3xxx_pcie_init_late(void); -#else -static inline void __init cns3xxx_pcie_init_late(void) {} -#endif - -void __init cns3xxx_map_io(void); -void __init cns3xxx_init_irq(void); -void cns3xxx_power_off(void); -void cns3xxx_restart(enum reboot_mode, const char *); - -#endif /* __CNS3XXX_CORE_H */ diff --git a/arch/arm/mach-cns3xxx/devices.c b/arch/arm/mach-cns3xxx/devices.c deleted file mode 100644 index 0f1ba8a0377d..000000000000 --- a/arch/arm/mach-cns3xxx/devices.c +++ /dev/null @@ -1,108 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * CNS3xxx common devices - * - * Copyright 2008 Cavium Networks - * Scott Shu - * Copyright 2010 MontaVista Software, LLC. - * Anton Vorontsov - */ - -#include -#include -#include -#include -#include -#include "cns3xxx.h" -#include "pm.h" -#include "core.h" -#include "devices.h" - -/* - * AHCI - */ -static struct resource cns3xxx_ahci_resource[] = { - [0] = { - .start = CNS3XXX_SATA2_BASE, - .end = CNS3XXX_SATA2_BASE + CNS3XXX_SATA2_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_CNS3XXX_SATA, - .end = IRQ_CNS3XXX_SATA, - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 cns3xxx_ahci_dmamask = DMA_BIT_MASK(32); - -static struct platform_device cns3xxx_ahci_pdev = { - .name = "ahci", - .id = 0, - .resource = cns3xxx_ahci_resource, - .num_resources = ARRAY_SIZE(cns3xxx_ahci_resource), - .dev = { - .dma_mask = &cns3xxx_ahci_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -void __init cns3xxx_ahci_init(void) -{ - u32 tmp; - - tmp = __raw_readl(MISC_SATA_POWER_MODE); - tmp |= 0x1 << 16; /* Disable SATA PHY 0 from SLUMBER Mode */ - tmp |= 0x1 << 17; /* Disable SATA PHY 1 from SLUMBER Mode */ - __raw_writel(tmp, MISC_SATA_POWER_MODE); - - /* Enable SATA PHY */ - cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0); - cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1); - - /* Enable SATA Clock */ - cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_SATA); - - /* De-Asscer SATA Reset */ - cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SATA)); - - platform_device_register(&cns3xxx_ahci_pdev); -} - -/* - * SDHCI - */ -static struct resource cns3xxx_sdhci_resources[] = { - [0] = { - .start = CNS3XXX_SDIO_BASE, - .end = CNS3XXX_SDIO_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_CNS3XXX_SDIO, - .end = IRQ_CNS3XXX_SDIO, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device cns3xxx_sdhci_pdev = { - .name = "sdhci-cns3xxx", - .id = 0, - .num_resources = ARRAY_SIZE(cns3xxx_sdhci_resources), - .resource = cns3xxx_sdhci_resources, -}; - -void __init cns3xxx_sdhci_init(void) -{ - u32 __iomem *gpioa = IOMEM(CNS3XXX_MISC_BASE_VIRT + 0x0014); - u32 gpioa_pins = __raw_readl(gpioa); - - /* MMC/SD pins share with GPIOA */ - gpioa_pins |= 0x1fff0004; - __raw_writel(gpioa_pins, gpioa); - - cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SDIO)); - cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SDIO)); - - platform_device_register(&cns3xxx_sdhci_pdev); -} diff --git a/arch/arm/mach-cns3xxx/devices.h b/arch/arm/mach-cns3xxx/devices.h deleted file mode 100644 index ab16530d0116..000000000000 --- a/arch/arm/mach-cns3xxx/devices.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * CNS3xxx common devices - * - * Copyright 2008 Cavium Networks - * Scott Shu - * Copyright 2010 MontaVista Software, LLC. - * Anton Vorontsov - */ - -#ifndef __CNS3XXX_DEVICES_H_ -#define __CNS3XXX_DEVICES_H_ - -void __init cns3xxx_ahci_init(void); -void __init cns3xxx_sdhci_init(void); - -#endif /* __CNS3XXX_DEVICES_H_ */ diff --git a/arch/arm/mach-cns3xxx/pcie.c b/arch/arm/mach-cns3xxx/pcie.c deleted file mode 100644 index e92fbd679dfb..000000000000 --- a/arch/arm/mach-cns3xxx/pcie.c +++ /dev/null @@ -1,290 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * PCI-E support for CNS3xxx - * - * Copyright 2008 Cavium Networks - * Richard Liu - * Copyright 2010 MontaVista Software, LLC. - * Anton Vorontsov - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "cns3xxx.h" -#include "core.h" - -struct cns3xxx_pcie { - void __iomem *host_regs; /* PCI config registers for host bridge */ - void __iomem *cfg0_regs; /* PCI Type 0 config registers */ - void __iomem *cfg1_regs; /* PCI Type 1 config registers */ - unsigned int irqs[2]; - struct resource res_io; - struct resource res_mem; - int port; - bool linked; -}; - -static struct cns3xxx_pcie *sysdata_to_cnspci(void *sysdata) -{ - struct pci_sys_data *root = sysdata; - - return root->private_data; -} - -static struct cns3xxx_pcie *pdev_to_cnspci(const struct pci_dev *dev) -{ - return sysdata_to_cnspci(dev->sysdata); -} - -static struct cns3xxx_pcie *pbus_to_cnspci(struct pci_bus *bus) -{ - return sysdata_to_cnspci(bus->sysdata); -} - -static void __iomem *cns3xxx_pci_map_bus(struct pci_bus *bus, - unsigned int devfn, int where) -{ - struct cns3xxx_pcie *cnspci = pbus_to_cnspci(bus); - int busno = bus->number; - int slot = PCI_SLOT(devfn); - void __iomem *base; - - /* If there is no link, just show the CNS PCI bridge. */ - if (!cnspci->linked && busno > 0) - return NULL; - - /* - * The CNS PCI bridge doesn't fit into the PCI hierarchy, though - * we still want to access it. - * We place the host bridge on bus 0, and the directly connected - * device on bus 1, slot 0. - */ - if (busno == 0) { /* internal PCIe bus, host bridge device */ - if (devfn == 0) /* device# and function# are ignored by hw */ - base = cnspci->host_regs; - else - return NULL; /* no such device */ - - } else if (busno == 1) { /* directly connected PCIe device */ - if (slot == 0) /* device# is ignored by hw */ - base = cnspci->cfg0_regs; - else - return NULL; /* no such device */ - } else /* remote PCI bus */ - base = cnspci->cfg1_regs + ((busno & 0xf) << 20); - - return base + where + (devfn << 12); -} - -static int cns3xxx_pci_read_config(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 *val) -{ - int ret; - u32 mask = (0x1ull << (size * 8)) - 1; - int shift = (where % 4) * 8; - - ret = pci_generic_config_read(bus, devfn, where, size, val); - - if (ret == PCIBIOS_SUCCESSFUL && !bus->number && !devfn && - (where & 0xffc) == PCI_CLASS_REVISION) - /* - * RC's class is 0xb, but Linux PCI driver needs 0x604 - * for a PCIe bridge. So we must fixup the class code - * to 0x604 here. - */ - *val = ((((*val << shift) & 0xff) | (0x604 << 16)) >> shift) & mask; - - return ret; -} - -static int cns3xxx_pci_setup(int nr, struct pci_sys_data *sys) -{ - struct cns3xxx_pcie *cnspci = sysdata_to_cnspci(sys); - struct resource *res_io = &cnspci->res_io; - struct resource *res_mem = &cnspci->res_mem; - - BUG_ON(request_resource(&iomem_resource, res_io) || - request_resource(&iomem_resource, res_mem)); - - pci_add_resource_offset(&sys->resources, res_io, sys->io_offset); - pci_add_resource_offset(&sys->resources, res_mem, sys->mem_offset); - - return 1; -} - -static struct pci_ops cns3xxx_pcie_ops = { - .map_bus = cns3xxx_pci_map_bus, - .read = cns3xxx_pci_read_config, - .write = pci_generic_config_write, -}; - -static int cns3xxx_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - struct cns3xxx_pcie *cnspci = pdev_to_cnspci(dev); - int irq = cnspci->irqs[!!dev->bus->number]; - - pr_info("PCIe map irq: %04d:%02x:%02x.%02x slot %d, pin %d, irq: %d\n", - pci_domain_nr(dev->bus), dev->bus->number, PCI_SLOT(dev->devfn), - PCI_FUNC(dev->devfn), slot, pin, irq); - - return irq; -} - -static struct cns3xxx_pcie cns3xxx_pcie[] = { - [0] = { - .host_regs = (void __iomem *)CNS3XXX_PCIE0_HOST_BASE_VIRT, - .cfg0_regs = (void __iomem *)CNS3XXX_PCIE0_CFG0_BASE_VIRT, - .cfg1_regs = (void __iomem *)CNS3XXX_PCIE0_CFG1_BASE_VIRT, - .res_io = { - .name = "PCIe0 I/O space", - .start = CNS3XXX_PCIE0_IO_BASE, - .end = CNS3XXX_PCIE0_CFG0_BASE - 1, /* 16 MiB */ - .flags = IORESOURCE_IO, - }, - .res_mem = { - .name = "PCIe0 non-prefetchable", - .start = CNS3XXX_PCIE0_MEM_BASE, - .end = CNS3XXX_PCIE0_HOST_BASE - 1, /* 176 MiB */ - .flags = IORESOURCE_MEM, - }, - .irqs = { IRQ_CNS3XXX_PCIE0_RC, IRQ_CNS3XXX_PCIE0_DEVICE, }, - .port = 0, - }, - [1] = { - .host_regs = (void __iomem *)CNS3XXX_PCIE1_HOST_BASE_VIRT, - .cfg0_regs = (void __iomem *)CNS3XXX_PCIE1_CFG0_BASE_VIRT, - .cfg1_regs = (void __iomem *)CNS3XXX_PCIE1_CFG1_BASE_VIRT, - .res_io = { - .name = "PCIe1 I/O space", - .start = CNS3XXX_PCIE1_IO_BASE, - .end = CNS3XXX_PCIE1_CFG0_BASE - 1, /* 16 MiB */ - .flags = IORESOURCE_IO, - }, - .res_mem = { - .name = "PCIe1 non-prefetchable", - .start = CNS3XXX_PCIE1_MEM_BASE, - .end = CNS3XXX_PCIE1_HOST_BASE - 1, /* 176 MiB */ - .flags = IORESOURCE_MEM, - }, - .irqs = { IRQ_CNS3XXX_PCIE1_RC, IRQ_CNS3XXX_PCIE1_DEVICE, }, - .port = 1, - }, -}; - -static void __init cns3xxx_pcie_check_link(struct cns3xxx_pcie *cnspci) -{ - int port = cnspci->port; - u32 reg; - unsigned long time; - - reg = __raw_readl(MISC_PCIE_CTRL(port)); - /* - * Enable Application Request to 1, it will exit L1 automatically, - * but when chip back, it will use another clock, still can use 0x1. - */ - reg |= 0x3; - __raw_writel(reg, MISC_PCIE_CTRL(port)); - - pr_info("PCIe: Port[%d] Enable PCIe LTSSM\n", port); - pr_info("PCIe: Port[%d] Check data link layer...", port); - - time = jiffies; - while (1) { - reg = __raw_readl(MISC_PCIE_PM_DEBUG(port)); - if (reg & 0x1) { - pr_info("Link up.\n"); - cnspci->linked = 1; - break; - } else if (time_after(jiffies, time + 50)) { - pr_info("Device not found.\n"); - break; - } - } -} - -static void cns3xxx_write_config(struct cns3xxx_pcie *cnspci, - int where, int size, u32 val) -{ - void __iomem *base = cnspci->host_regs + (where & 0xffc); - u32 v; - u32 mask = (0x1ull << (size * 8)) - 1; - int shift = (where % 4) * 8; - - v = readl_relaxed(base); - - v &= ~(mask << shift); - v |= (val & mask) << shift; - - writel_relaxed(v, base); - readl_relaxed(base); -} - -static void __init cns3xxx_pcie_hw_init(struct cns3xxx_pcie *cnspci) -{ - u16 mem_base = cnspci->res_mem.start >> 16; - u16 mem_limit = cnspci->res_mem.end >> 16; - u16 io_base = cnspci->res_io.start >> 16; - u16 io_limit = cnspci->res_io.end >> 16; - - cns3xxx_write_config(cnspci, PCI_PRIMARY_BUS, 1, 0); - cns3xxx_write_config(cnspci, PCI_SECONDARY_BUS, 1, 1); - cns3xxx_write_config(cnspci, PCI_SUBORDINATE_BUS, 1, 1); - cns3xxx_write_config(cnspci, PCI_MEMORY_BASE, 2, mem_base); - cns3xxx_write_config(cnspci, PCI_MEMORY_LIMIT, 2, mem_limit); - cns3xxx_write_config(cnspci, PCI_IO_BASE_UPPER16, 2, io_base); - cns3xxx_write_config(cnspci, PCI_IO_LIMIT_UPPER16, 2, io_limit); - - if (!cnspci->linked) - return; - - /* Set Device Max_Read_Request_Size to 128 byte */ - pcie_bus_config = PCIE_BUS_PEER2PEER; - - /* Disable PCIe0 Interrupt Mask INTA to INTD */ - __raw_writel(~0x3FFF, MISC_PCIE_INT_MASK(cnspci->port)); -} - -static int cns3xxx_pcie_abort_handler(unsigned long addr, unsigned int fsr, - struct pt_regs *regs) -{ - if (fsr & (1 << 10)) - regs->ARM_pc += 4; - return 0; -} - -void __init cns3xxx_pcie_init_late(void) -{ - int i; - void *private_data; - struct hw_pci hw_pci = { - .nr_controllers = 1, - .ops = &cns3xxx_pcie_ops, - .setup = cns3xxx_pci_setup, - .map_irq = cns3xxx_pcie_map_irq, - .private_data = &private_data, - }; - - pcibios_min_io = 0; - pcibios_min_mem = 0; - - hook_fault_code(16 + 6, cns3xxx_pcie_abort_handler, SIGBUS, 0, - "imprecise external abort"); - - for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) { - cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_PCIE(i)); - cns3xxx_pwr_soft_rst(0x1 << PM_SOFT_RST_REG_OFFST_PCIE(i)); - cns3xxx_pcie_check_link(&cns3xxx_pcie[i]); - cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]); - private_data = &cns3xxx_pcie[i]; - pci_common_init(&hw_pci); - } - - pci_assign_unassigned_resources(); -} diff --git a/arch/arm/mach-cns3xxx/pm.c b/arch/arm/mach-cns3xxx/pm.c deleted file mode 100644 index 72e8a7ec7a38..000000000000 --- a/arch/arm/mach-cns3xxx/pm.c +++ /dev/null @@ -1,120 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright 2008 Cavium Networks - */ - -#include -#include -#include -#include -#include -#include "cns3xxx.h" -#include "pm.h" -#include "core.h" - -void cns3xxx_pwr_clk_en(unsigned int block) -{ - u32 reg = __raw_readl(PM_CLK_GATE_REG); - - reg |= (block & PM_CLK_GATE_REG_MASK); - __raw_writel(reg, PM_CLK_GATE_REG); -} -EXPORT_SYMBOL(cns3xxx_pwr_clk_en); - -void cns3xxx_pwr_clk_dis(unsigned int block) -{ - u32 reg = __raw_readl(PM_CLK_GATE_REG); - - reg &= ~(block & PM_CLK_GATE_REG_MASK); - __raw_writel(reg, PM_CLK_GATE_REG); -} -EXPORT_SYMBOL(cns3xxx_pwr_clk_dis); - -void cns3xxx_pwr_power_up(unsigned int block) -{ - u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG); - - reg &= ~(block & CNS3XXX_PWR_PLL_ALL); - __raw_writel(reg, PM_PLL_HM_PD_CTRL_REG); - - /* Wait for 300us for the PLL output clock locked. */ - udelay(300); -}; -EXPORT_SYMBOL(cns3xxx_pwr_power_up); - -void cns3xxx_pwr_power_down(unsigned int block) -{ - u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG); - - /* write '1' to power down */ - reg |= (block & CNS3XXX_PWR_PLL_ALL); - __raw_writel(reg, PM_PLL_HM_PD_CTRL_REG); -}; -EXPORT_SYMBOL(cns3xxx_pwr_power_down); - -static void cns3xxx_pwr_soft_rst_force(unsigned int block) -{ - u32 reg = __raw_readl(PM_SOFT_RST_REG); - - /* - * bit 0, 28, 29 => program low to reset, - * the other else program low and then high - */ - if (block & 0x30000001) { - reg &= ~(block & PM_SOFT_RST_REG_MASK); - } else { - reg &= ~(block & PM_SOFT_RST_REG_MASK); - __raw_writel(reg, PM_SOFT_RST_REG); - reg |= (block & PM_SOFT_RST_REG_MASK); - } - - __raw_writel(reg, PM_SOFT_RST_REG); -} - -void cns3xxx_pwr_soft_rst(unsigned int block) -{ - static unsigned int soft_reset; - - if (soft_reset & block) { - /* SPI/I2C/GPIO use the same block, reset once. */ - return; - } else { - soft_reset |= block; - } - cns3xxx_pwr_soft_rst_force(block); -} -EXPORT_SYMBOL(cns3xxx_pwr_soft_rst); - -void cns3xxx_restart(enum reboot_mode mode, const char *cmd) -{ - /* - * To reset, we hit the on-board reset register - * in the system FPGA. - */ - cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(GLOBAL)); -} - -/* - * cns3xxx_cpu_clock - return CPU/L2 clock - * aclk: cpu clock/2 - * hclk: cpu clock/4 - * pclk: cpu clock/8 - */ -int cns3xxx_cpu_clock(void) -{ - u32 reg = __raw_readl(PM_CLK_CTRL_REG); - int cpu; - int cpu_sel; - int div_sel; - - cpu_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL) & 0xf; - div_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV) & 0x3; - - cpu = (300 + ((cpu_sel / 3) * 100) + ((cpu_sel % 3) * 33)) >> div_sel; - - return cpu; -} -EXPORT_SYMBOL(cns3xxx_cpu_clock); - -atomic_t usb_pwr_ref = ATOMIC_INIT(0); -EXPORT_SYMBOL(usb_pwr_ref); diff --git a/arch/arm/mach-cns3xxx/pm.h b/arch/arm/mach-cns3xxx/pm.h deleted file mode 100644 index 61b73e59f0ff..000000000000 --- a/arch/arm/mach-cns3xxx/pm.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2000 Deep Blue Solutions Ltd - * Copyright 2004 ARM Limited - * Copyright 2008 Cavium Networks - */ - -#ifndef __CNS3XXX_PM_H -#define __CNS3XXX_PM_H - -#include - -void cns3xxx_pwr_clk_en(unsigned int block); -void cns3xxx_pwr_clk_dis(unsigned int block); -void cns3xxx_pwr_power_up(unsigned int block); -void cns3xxx_pwr_power_down(unsigned int block); - -extern atomic_t usb_pwr_ref; - -#endif /* __CNS3XXX_PM_H */ diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 247568bc17a2..75b8a3eeb23a 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -316,18 +316,6 @@ config USB_OCTEON_HCD To compile this driver as a module, choose M here. The module will be called octeon-hcd. -config USB_CNS3XXX_EHCI - bool "Cavium CNS3XXX EHCI Module (DEPRECATED)" - depends on ARCH_CNS3XXX || COMPILE_TEST - select USB_EHCI_HCD_PLATFORM - help - This option is deprecated now and the driver was removed, use - USB_EHCI_HCD_PLATFORM instead. - - Enable support for the CNS3XXX SOC's on-chip EHCI controller. - It is needed for high-speed (480Mbit/sec) USB 2.0 device - support. - config USB_EHCI_HCD_PLATFORM tristate "Generic EHCI driver for a platform device" help @@ -577,17 +565,6 @@ config USB_OHCI_EXYNOS Enable support for the Samsung S5Pv210 and Exynos SOC's on-chip OHCI controller. -config USB_CNS3XXX_OHCI - bool "Cavium CNS3XXX OHCI Module (DEPRECATED)" - depends on ARCH_CNS3XXX || COMPILE_TEST - select USB_OHCI_HCD_PLATFORM - help - This option is deprecated now and the driver was removed, use - USB_OHCI_HCD_PLATFORM instead. - - Enable support for the CNS3XXX SOC's on-chip OHCI controller. - It is needed for low-speed USB 1.0 device support. - config USB_OHCI_HCD_PLATFORM tristate "Generic OHCI driver for a platform device" help From patchwork Wed Oct 19 15:03:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnd Bergmann X-Patchwork-Id: 5700 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp395053wrs; Wed, 19 Oct 2022 08:42:25 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4gbeXJSSQcIVtPBLSGrElBboddEvUWyhJ5NiSSlwh0WRKG44WbTPIXcntSY8Uj6KMhRup7 X-Received: by 2002:a17:907:3e01:b0:730:a690:a211 with SMTP id hp1-20020a1709073e0100b00730a690a211mr7271885ejc.596.1666194144840; Wed, 19 Oct 2022 08:42:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666194144; cv=none; d=google.com; s=arc-20160816; b=FnQFJg1myzLvA68GHu/NQSvCxdVkfp2RZl9qXanszKWkiJf1uovU4me9q0VmecnwId unQkawe67ZvRtP9C13VoD9ZkKFSyKJFOdxFPWAxHgYyDSPwi9QBQxLSusO9z5vk1Ewij 04TaXqxjhM0Baf6AfwJRFVKw0QRcCBdOCmEP0DnprxzP2NON2hBxMIuPweI947p5WNRH MDreUbhW7pFJQEpS6eaTEP0JkYZm1F54WrqegutoBMvRVywaBa8mSHrzNtS50q+Jz9Gi MIjVh/QWu8+hGr1p6JV9kN1f6WF9S7zC1AUcxDlbP1nijEhvjgSxh2Kkhe9CYUsGLThS cqYg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=pWOzIoh3Ecoh2U4x7hbzGaMXPPFQoQNumvylNIIkGGQ=; b=nDxyejgTpZfykXji/zA7t1usJ85mKj7gcM7nG7/2rTI/54wNJ57/kCMzEDlrPCpekw /Sa0NGvZo+MQgEurAQpDgWJsvaLpYOPVnKzMypKDegHEKK3qKYcFNM6wF6byewKpsCFo 4DxQR97nC0SZnn7Q7vsuhMBwIJ8DA2jlVUurXKF9/qzdsADSZjqxuTIRVBCDMOwiFKsA K03jwdhlot8jCjN/lV9scYP/kwwVlAAudIrWuxRqnv0LsrSIxWcwzgEeGVRxmcPflSfZ PocytT2705NlslrUO8gnrqczmkoCLw2kpXwl4daphG9y/xrha4KBJFrT2+4ZBWows9/z Svdg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=umD84749; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id mp34-20020a1709071b2200b0078034101c0esi15284616ejc.978.2022.10.19.08.42.00; Wed, 19 Oct 2022 08:42:24 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=umD84749; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229869AbiJSPbT (ORCPT + 99 others); Wed, 19 Oct 2022 11:31:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51118 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231209AbiJSPay (ORCPT ); Wed, 19 Oct 2022 11:30:54 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F242E1D63A8; Wed, 19 Oct 2022 08:23:25 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id B63566192C; Wed, 19 Oct 2022 15:06:57 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 88092C433C1; Wed, 19 Oct 2022 15:06:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1666192017; bh=HS3PFH697lV4ACSOHmqEUYqKoZRf8xn5Q1It8jFYkb4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=umD84749KZwLWWmN922ZOzZI0Xd8j7pVE+dQfuaKJS7DU+PQOHO8wfrNrui7g7cQE lg5vv++L2mqr6/V3DLVZ5KgCreozm4xoROPkEZhiAkuOwR34dw5Es+7imslKlQjs6l ml0LXs7MOMBwYvY0W07O2Yk31XvCQeDMev4IQlaTMk2Nptcl9F2OrV4wEZ1ZPV4noL NDpDYZrObSREXjHeH/EtyGljDsc0klsaiqgMsrKscG6b6jVNOk25Fgt5p3WaNeG5yR kvWURKBkfj0r6l/ISHGugheGLCo7l4nWBapay2XCZwzkCTVtPFKJRnCwaFd1cm1RFP a+HsYXSl/1s/g== From: Arnd Bergmann To: linux-arm-kernel@lists.infradead.org, Ulf Hansson , Adrian Hunter Cc: linux-kernel@vger.kernel.org, Arnd Bergmann , Krzysztof Halasa , linux-mmc@vger.kernel.org Subject: [PATCH 03/17] mmc: remove cns3xxx driver Date: Wed, 19 Oct 2022 17:03:25 +0200 Message-Id: <20221019150410.3851944-3-arnd@kernel.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20221019150410.3851944-1-arnd@kernel.org> References: <20221019144119.3848027-1-arnd@kernel.org> <20221019150410.3851944-1-arnd@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747131192020133419?= X-GMAIL-MSGID: =?utf-8?q?1747131192020133419?= From: Arnd Bergmann The cns3xxx platform is gone, so this driver is now orphaned. Cc: Krzysztof Halasa Signed-off-by: Arnd Bergmann Acked-by: Ulf Hansson --- drivers/mmc/host/Kconfig | 11 --- drivers/mmc/host/Makefile | 1 - drivers/mmc/host/sdhci-cns3xxx.c | 113 ------------------------------- 3 files changed, 125 deletions(-) delete mode 100644 drivers/mmc/host/sdhci-cns3xxx.c diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index f324daadaf70..1c5b1c48a230 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -253,17 +253,6 @@ config MMC_SDHCI_CADENCE If unsure, say N. -config MMC_SDHCI_CNS3XXX - tristate "SDHCI support on the Cavium Networks CNS3xxx SoC" - depends on ARCH_CNS3XXX || COMPILE_TEST - depends on MMC_SDHCI_PLTFM - help - This selects the SDHCI support for CNS3xxx System-on-Chip devices. - - If you have a controller with this interface, say Y or M here. - - If unsure, say N. - config MMC_SDHCI_ESDHC_MCF tristate "SDHCI support for the Freescale eSDHC ColdFire controller" depends on M5441x diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile index 4e4ceb32c4b4..7bea77c28b7e 100644 --- a/drivers/mmc/host/Makefile +++ b/drivers/mmc/host/Makefile @@ -77,7 +77,6 @@ obj-$(CONFIG_MMC_REALTEK_USB) += rtsx_usb_sdmmc.o obj-$(CONFIG_MMC_SDHCI_PLTFM) += sdhci-pltfm.o obj-$(CONFIG_MMC_SDHCI_CADENCE) += sdhci-cadence.o -obj-$(CONFIG_MMC_SDHCI_CNS3XXX) += sdhci-cns3xxx.o obj-$(CONFIG_MMC_SDHCI_ESDHC_MCF) += sdhci-esdhc-mcf.o obj-$(CONFIG_MMC_SDHCI_ESDHC_IMX) += sdhci-esdhc-imx.o obj-$(CONFIG_MMC_SDHCI_DOVE) += sdhci-dove.o diff --git a/drivers/mmc/host/sdhci-cns3xxx.c b/drivers/mmc/host/sdhci-cns3xxx.c deleted file mode 100644 index 2a29c7a4f308..000000000000 --- a/drivers/mmc/host/sdhci-cns3xxx.c +++ /dev/null @@ -1,113 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * SDHCI support for CNS3xxx SoC - * - * Copyright 2008 Cavium Networks - * Copyright 2010 MontaVista Software, LLC. - * - * Authors: Scott Shu - * Anton Vorontsov - */ - -#include -#include -#include -#include -#include "sdhci-pltfm.h" - -static unsigned int sdhci_cns3xxx_get_max_clk(struct sdhci_host *host) -{ - return 150000000; -} - -static void sdhci_cns3xxx_set_clock(struct sdhci_host *host, unsigned int clock) -{ - struct device *dev = mmc_dev(host->mmc); - int div = 1; - u16 clk; - unsigned long timeout; - - host->mmc->actual_clock = 0; - - sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); - - if (clock == 0) - return; - - while (host->max_clk / div > clock) { - /* - * On CNS3xxx divider grows linearly up to 4, and then - * exponentially up to 256. - */ - if (div < 4) - div += 1; - else if (div < 256) - div *= 2; - else - break; - } - - dev_dbg(dev, "desired SD clock: %d, actual: %d\n", - clock, host->max_clk / div); - - /* Divide by 3 is special. */ - if (div != 3) - div >>= 1; - - clk = div << SDHCI_DIVIDER_SHIFT; - clk |= SDHCI_CLOCK_INT_EN; - sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); - - timeout = 20; - while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) - & SDHCI_CLOCK_INT_STABLE)) { - if (timeout == 0) { - dev_warn(dev, "clock is unstable"); - break; - } - timeout--; - mdelay(1); - } - - clk |= SDHCI_CLOCK_CARD_EN; - sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); -} - -static const struct sdhci_ops sdhci_cns3xxx_ops = { - .get_max_clock = sdhci_cns3xxx_get_max_clk, - .set_clock = sdhci_cns3xxx_set_clock, - .set_bus_width = sdhci_set_bus_width, - .reset = sdhci_reset, - .set_uhs_signaling = sdhci_set_uhs_signaling, -}; - -static const struct sdhci_pltfm_data sdhci_cns3xxx_pdata = { - .ops = &sdhci_cns3xxx_ops, - .quirks = SDHCI_QUIRK_BROKEN_DMA | - SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | - SDHCI_QUIRK_INVERTED_WRITE_PROTECT | - SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | - SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, -}; - -static int sdhci_cns3xxx_probe(struct platform_device *pdev) -{ - return sdhci_pltfm_register(pdev, &sdhci_cns3xxx_pdata, 0); -} - -static struct platform_driver sdhci_cns3xxx_driver = { - .driver = { - .name = "sdhci-cns3xxx", - .probe_type = PROBE_PREFER_ASYNCHRONOUS, - .pm = &sdhci_pltfm_pmops, - }, - .probe = sdhci_cns3xxx_probe, - .remove = sdhci_pltfm_unregister, -}; - -module_platform_driver(sdhci_cns3xxx_driver); - -MODULE_DESCRIPTION("SDHCI driver for CNS3xxx"); -MODULE_AUTHOR("Scott Shu, " - "Anton Vorontsov "); -MODULE_LICENSE("GPL v2"); From patchwork Wed Oct 19 15:03:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Arnd Bergmann X-Patchwork-Id: 5674 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp383378wrs; Wed, 19 Oct 2022 08:18:31 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4OuKtj+sdHUJJhqMDni2juuhnDDMoBImHBFDRPJS4BIECrwCvpSyve24aKK+uZK4t7z1Ms X-Received: by 2002:a17:907:a065:b0:78d:c5dd:45cf with SMTP id ia5-20020a170907a06500b0078dc5dd45cfmr7333339ejc.117.1666192711243; Wed, 19 Oct 2022 08:18:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666192711; cv=none; d=google.com; s=arc-20160816; b=YEpLJCzerZfCySZHBCVfGK0OLjEaQN7hQxhKPRvM2qlUUEDzhlStl3ENFq07vKgZAZ EnQLBnynKe22/QXuVihRvxpd5z1bNCJkQ0Q2wvyQV2i6tyk09Gs4L3lVdngGgV833+OM VAIpyX2IlcLeCn25QwflBF+zbQQOgyLEdMpl1qCfmxWt3wB/9zqR5S1vCtXHW1ZP11hR qftDggpwDm5pgT1KrRcKkJ+dv30U1W36zUuFEk17sLHyUzvOz6i4VmAV/ZK9ETJbHrgY itkMg9hTUMYpjezt9C5Iytw0gybFP71ax3LRnoax6mauULez/lBRY1TbkGubTL6AOIIq 58vg== ARC-Message-Signature: i=1; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id t9-20020a056402524900b0045bd677b3d5si16737436edd.342.2022.10.19.08.18.06; Wed, 19 Oct 2022 08:18:31 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=dXrG90nV; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231231AbiJSPRU (ORCPT + 99 others); Wed, 19 Oct 2022 11:17:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55090 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232207AbiJSPRC (ORCPT ); Wed, 19 Oct 2022 11:17:02 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ED4BD14409D for ; Wed, 19 Oct 2022 08:09:55 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id C0DF4B824A5 for ; Wed, 19 Oct 2022 15:08:04 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id EDC48C433C1; Wed, 19 Oct 2022 15:08:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1666192083; bh=95MlQNM30vmfwNJFsblpQxVcyVh7sYL+rn6OLXApeOA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=dXrG90nVSwcvr2gq5pXRK6RjII348ylQTrCTVeamFy7AnpXi4cBDLcWkyEgBAJeJ9 8sKiNf/ITiCUletwrgC8Hxcgx2nPlO8yzfa7eth3zGVHgi/xsK+6E/QrmbYtW+SQLy F5AKd4+CvWb1Uu/q8vZf0M8Dp2RtctUC9EjbCeKoO/Sm7ITsTVAuVtXTjJkK39VYVW 4Jjz0twFemiEOEFSzNoNtPQct+M/llMGJ5orDlO9rBQmFn/gKWPcBgW73TsLkNNSR6 zdU82WqWumqzrEAY81f1a7ecwoREtXBGBjha5HvJHi8b7fRhZqSMH5zFgFZYlRmi05 NwK7h3sw5mhYw== From: Arnd Bergmann To: linux-arm-kernel@lists.infradead.org, Hartley Sweeten , Alexander Sverdlin Cc: linux-kernel@vger.kernel.org, Arnd Bergmann , Lennert Buytenhek , Hubert Feurstein Subject: [PATCH 04/17] ARM: ep93xx: remove old board files Date: Wed, 19 Oct 2022 17:03:26 +0200 Message-Id: <20221019150410.3851944-4-arnd@kernel.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20221019150410.3851944-1-arnd@kernel.org> References: <20221019144119.3848027-1-arnd@kernel.org> <20221019150410.3851944-1-arnd@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747129688498192032?= X-GMAIL-MSGID: =?utf-8?q?1747129688498192032?= From: Arnd Bergmann These five board files were marked as unused a while ago, and nobody wanted to keep them around for longer, so remove them now. We still have the edb93xx, visision_ep9307 and ts72xx files, which can hopefully be converted to device tree in the future. Cc: Lennert Buytenhek Cc: Hubert Feurstein Signed-off-by: Arnd Bergmann Acked-by: Alexander Sverdlin --- MAINTAINERS | 10 -- arch/arm/boot/compressed/misc-ep93xx.h | 13 +- arch/arm/mach-ep93xx/Kconfig | 63 ---------- arch/arm/mach-ep93xx/Makefile | 5 - arch/arm/mach-ep93xx/adssphere.c | 41 ------- arch/arm/mach-ep93xx/gesbc9312.c | 41 ------- arch/arm/mach-ep93xx/micro9.c | 125 ------------------- arch/arm/mach-ep93xx/simone.c | 128 ------------------- arch/arm/mach-ep93xx/snappercl15.c | 162 ------------------------- 9 files changed, 1 insertion(+), 587 deletions(-) delete mode 100644 arch/arm/mach-ep93xx/adssphere.c delete mode 100644 arch/arm/mach-ep93xx/gesbc9312.c delete mode 100644 arch/arm/mach-ep93xx/micro9.c delete mode 100644 arch/arm/mach-ep93xx/simone.c delete mode 100644 arch/arm/mach-ep93xx/snappercl15.c diff --git a/MAINTAINERS b/MAINTAINERS index 57b74156df3a..89f72dba8e64 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1793,11 +1793,6 @@ F: include/dt-bindings/reset/actions,* F: include/linux/soc/actions/ N: owl -ARM/ADS SPHERE MACHINE SUPPORT -M: Lennert Buytenhek -L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -S: Maintained - ARM/Allwinner SoC Clock Support M: Emilio López S: Maintained @@ -2029,11 +2024,6 @@ S: Maintained F: arch/arm/boot/dts/cx92755* N: digicolor -ARM/CONTEC MICRO9 MACHINE SUPPORT -M: Hubert Feurstein -S: Maintained -F: arch/arm/mach-ep93xx/micro9.c - ARM/CORESIGHT FRAMEWORK AND DRIVERS M: Mathieu Poirier M: Suzuki K Poulose diff --git a/arch/arm/boot/compressed/misc-ep93xx.h b/arch/arm/boot/compressed/misc-ep93xx.h index 3dc942589cba..65b4121d1490 100644 --- a/arch/arm/boot/compressed/misc-ep93xx.h +++ b/arch/arm/boot/compressed/misc-ep93xx.h @@ -57,8 +57,7 @@ static inline void ep93xx_decomp_setup(void) if (machine_is_ts72xx()) ts72xx_watchdog_disable(); - if (machine_is_adssphere() || - machine_is_edb9301() || + if (machine_is_edb9301() || machine_is_edb9302() || machine_is_edb9302a() || machine_is_edb9302a() || @@ -69,16 +68,6 @@ static inline void ep93xx_decomp_setup(void) machine_is_edb9315() || machine_is_edb9315a() || machine_is_edb9315a() || - machine_is_gesbc9312() || - machine_is_micro9() || - machine_is_micro9l() || - machine_is_micro9m() || - machine_is_micro9s() || - machine_is_micro9m() || - machine_is_micro9l() || - machine_is_micro9s() || - machine_is_sim_one() || - machine_is_snapper_cl15() || machine_is_ts72xx() || machine_is_bk3() || machine_is_vision_ep9307()) diff --git a/arch/arm/mach-ep93xx/Kconfig b/arch/arm/mach-ep93xx/Kconfig index 2c40996a444b..703f3d232a60 100644 --- a/arch/arm/mach-ep93xx/Kconfig +++ b/arch/arm/mach-ep93xx/Kconfig @@ -25,13 +25,6 @@ config EP93XX_SOC_COMMON comment "EP93xx Platforms" -config MACH_ADSSPHERE - bool "Support ADS Sphere" - depends on UNUSED_BOARD_FILES - help - Say 'Y' here if you want your kernel to support the ADS - Sphere board. - config MACH_BK3 bool "Support Liebherr BK3.1" select MACH_TS72XX @@ -98,62 +91,6 @@ config MACH_EDB9315A Say 'Y' here if you want your kernel to support the Cirrus Logic EDB9315A Evaluation Board. -config MACH_GESBC9312 - bool "Support Glomation GESBC-9312-sx" - depends on UNUSED_BOARD_FILES - help - Say 'Y' here if you want your kernel to support the Glomation - GESBC-9312-sx board. - -config MACH_MICRO9 - bool - -config MACH_MICRO9H - bool "Support Contec Micro9-High" - select MACH_MICRO9 - depends on UNUSED_BOARD_FILES - help - Say 'Y' here if you want your kernel to support the - Contec Micro9-High board. - -config MACH_MICRO9M - bool "Support Contec Micro9-Mid" - select MACH_MICRO9 - depends on UNUSED_BOARD_FILES - help - Say 'Y' here if you want your kernel to support the - Contec Micro9-Mid board. - -config MACH_MICRO9L - bool "Support Contec Micro9-Lite" - select MACH_MICRO9 - depends on UNUSED_BOARD_FILES - help - Say 'Y' here if you want your kernel to support the - Contec Micro9-Lite board. - -config MACH_MICRO9S - bool "Support Contec Micro9-Slim" - select MACH_MICRO9 - depends on UNUSED_BOARD_FILES - help - Say 'Y' here if you want your kernel to support the - Contec Micro9-Slim board. - -config MACH_SIM_ONE - bool "Support Simplemachines Sim.One board" - depends on UNUSED_BOARD_FILES - help - Say 'Y' here if you want your kernel to support the - Simplemachines Sim.One board. - -config MACH_SNAPPER_CL15 - bool "Support Bluewater Systems Snapper CL15 Module" - depends on UNUSED_BOARD_FILES - help - Say 'Y' here if you want your kernel to support the Bluewater - Systems Snapper CL15 Module. - config MACH_TS72XX bool "Support Technologic Systems TS-72xx SBC" help diff --git a/arch/arm/mach-ep93xx/Makefile b/arch/arm/mach-ep93xx/Makefile index cfad517fac46..62e37403df14 100644 --- a/arch/arm/mach-ep93xx/Makefile +++ b/arch/arm/mach-ep93xx/Makefile @@ -6,11 +6,6 @@ obj-y := core.o clock.o timer-ep93xx.o obj-$(CONFIG_EP93XX_DMA) += dma.o -obj-$(CONFIG_MACH_ADSSPHERE) += adssphere.o obj-$(CONFIG_MACH_EDB93XX) += edb93xx.o -obj-$(CONFIG_MACH_GESBC9312) += gesbc9312.o -obj-$(CONFIG_MACH_MICRO9) += micro9.o -obj-$(CONFIG_MACH_SIM_ONE) += simone.o -obj-$(CONFIG_MACH_SNAPPER_CL15) += snappercl15.o obj-$(CONFIG_MACH_TS72XX) += ts72xx.o obj-$(CONFIG_MACH_VISION_EP9307)+= vision_ep9307.o diff --git a/arch/arm/mach-ep93xx/adssphere.c b/arch/arm/mach-ep93xx/adssphere.c deleted file mode 100644 index 0c48d3c5b8e7..000000000000 --- a/arch/arm/mach-ep93xx/adssphere.c +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * arch/arm/mach-ep93xx/adssphere.c - * ADS Sphere support. - * - * Copyright (C) 2006 Lennert Buytenhek - */ - -#include -#include -#include -#include - -#include "hardware.h" - -#include -#include - -#include "soc.h" - -static struct ep93xx_eth_data __initdata adssphere_eth_data = { - .phy_id = 1, -}; - -static void __init adssphere_init_machine(void) -{ - ep93xx_init_devices(); - ep93xx_register_flash(4, EP93XX_CS6_PHYS_BASE, SZ_32M); - ep93xx_register_eth(&adssphere_eth_data, 1); -} - -MACHINE_START(ADSSPHERE, "ADS Sphere board") - /* Maintainer: Lennert Buytenhek */ - .atag_offset = 0x100, - .nr_irqs = NR_EP93XX_IRQS, - .map_io = ep93xx_map_io, - .init_irq = ep93xx_init_irq, - .init_time = ep93xx_timer_init, - .init_machine = adssphere_init_machine, - .restart = ep93xx_restart, -MACHINE_END diff --git a/arch/arm/mach-ep93xx/gesbc9312.c b/arch/arm/mach-ep93xx/gesbc9312.c deleted file mode 100644 index 0b7043e3e178..000000000000 --- a/arch/arm/mach-ep93xx/gesbc9312.c +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * arch/arm/mach-ep93xx/gesbc9312.c - * Glomation GESBC-9312-sx support. - * - * Copyright (C) 2006 Lennert Buytenhek - */ - -#include -#include -#include -#include - -#include "hardware.h" - -#include -#include - -#include "soc.h" - -static struct ep93xx_eth_data __initdata gesbc9312_eth_data = { - .phy_id = 1, -}; - -static void __init gesbc9312_init_machine(void) -{ - ep93xx_init_devices(); - ep93xx_register_flash(4, EP93XX_CS6_PHYS_BASE, SZ_8M); - ep93xx_register_eth(&gesbc9312_eth_data, 0); -} - -MACHINE_START(GESBC9312, "Glomation GESBC-9312-sx") - /* Maintainer: Lennert Buytenhek */ - .atag_offset = 0x100, - .nr_irqs = NR_EP93XX_IRQS, - .map_io = ep93xx_map_io, - .init_irq = ep93xx_init_irq, - .init_time = ep93xx_timer_init, - .init_machine = gesbc9312_init_machine, - .restart = ep93xx_restart, -MACHINE_END diff --git a/arch/arm/mach-ep93xx/micro9.c b/arch/arm/mach-ep93xx/micro9.c deleted file mode 100644 index c121c459aa17..000000000000 --- a/arch/arm/mach-ep93xx/micro9.c +++ /dev/null @@ -1,125 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/mach-ep93xx/micro9.c - * - * Copyright (C) 2006 Contec Steuerungstechnik & Automation GmbH - * Manfred Gruber - * Copyright (C) 2009 Contec Steuerungstechnik & Automation GmbH - * Hubert Feurstein - */ - -#include -#include -#include -#include - -#include "hardware.h" - -#include -#include - -#include "soc.h" - -/************************************************************************* - * Micro9 NOR Flash - * - * Micro9-High has up to 64MB of 32-bit flash on CS1 - * Micro9-Mid has up to 64MB of either 32-bit or 16-bit flash on CS1 - * Micro9-Lite uses a separate MTD map driver for flash support - * Micro9-Slim has up to 64MB of either 32-bit or 16-bit flash on CS1 - *************************************************************************/ -static unsigned int __init micro9_detect_bootwidth(void) -{ - u32 v; - - /* Detect the bus width of the external flash memory */ - v = __raw_readl(EP93XX_SYSCON_SYSCFG); - if (v & EP93XX_SYSCON_SYSCFG_LCSN7) - return 4; /* 32-bit */ - else - return 2; /* 16-bit */ -} - -static void __init micro9_register_flash(void) -{ - unsigned int width; - - if (machine_is_micro9()) - width = 4; - else if (machine_is_micro9m() || machine_is_micro9s()) - width = micro9_detect_bootwidth(); - else - width = 0; - - if (width) - ep93xx_register_flash(width, EP93XX_CS1_PHYS_BASE, SZ_64M); -} - - -/************************************************************************* - * Micro9 Ethernet - *************************************************************************/ -static struct ep93xx_eth_data __initdata micro9_eth_data = { - .phy_id = 0x1f, -}; - - -static void __init micro9_init_machine(void) -{ - ep93xx_init_devices(); - ep93xx_register_eth(µ9_eth_data, 1); - micro9_register_flash(); -} - - -#ifdef CONFIG_MACH_MICRO9H -MACHINE_START(MICRO9, "Contec Micro9-High") - /* Maintainer: Hubert Feurstein */ - .atag_offset = 0x100, - .nr_irqs = NR_EP93XX_IRQS, - .map_io = ep93xx_map_io, - .init_irq = ep93xx_init_irq, - .init_time = ep93xx_timer_init, - .init_machine = micro9_init_machine, - .restart = ep93xx_restart, -MACHINE_END -#endif - -#ifdef CONFIG_MACH_MICRO9M -MACHINE_START(MICRO9M, "Contec Micro9-Mid") - /* Maintainer: Hubert Feurstein */ - .atag_offset = 0x100, - .nr_irqs = NR_EP93XX_IRQS, - .map_io = ep93xx_map_io, - .init_irq = ep93xx_init_irq, - .init_time = ep93xx_timer_init, - .init_machine = micro9_init_machine, - .restart = ep93xx_restart, -MACHINE_END -#endif - -#ifdef CONFIG_MACH_MICRO9L -MACHINE_START(MICRO9L, "Contec Micro9-Lite") - /* Maintainer: Hubert Feurstein */ - .atag_offset = 0x100, - .nr_irqs = NR_EP93XX_IRQS, - .map_io = ep93xx_map_io, - .init_irq = ep93xx_init_irq, - .init_time = ep93xx_timer_init, - .init_machine = micro9_init_machine, - .restart = ep93xx_restart, -MACHINE_END -#endif - -#ifdef CONFIG_MACH_MICRO9S -MACHINE_START(MICRO9S, "Contec Micro9-Slim") - /* Maintainer: Hubert Feurstein */ - .atag_offset = 0x100, - .nr_irqs = NR_EP93XX_IRQS, - .map_io = ep93xx_map_io, - .init_irq = ep93xx_init_irq, - .init_time = ep93xx_timer_init, - .init_machine = micro9_init_machine, - .restart = ep93xx_restart, -MACHINE_END -#endif diff --git a/arch/arm/mach-ep93xx/simone.c b/arch/arm/mach-ep93xx/simone.c deleted file mode 100644 index 569e72413561..000000000000 --- a/arch/arm/mach-ep93xx/simone.c +++ /dev/null @@ -1,128 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * arch/arm/mach-ep93xx/simone.c - * Simplemachines Sim.One support. - * - * Copyright (C) 2010 Ryan Mallon - * - * Based on the 2.6.24.7 support: - * Copyright (C) 2009 Simplemachines - * MMC support by Peter Ivanov , 2007 - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "hardware.h" -#include "gpio-ep93xx.h" - -#include -#include - -#include "soc.h" - -static struct ep93xx_eth_data __initdata simone_eth_data = { - .phy_id = 1, -}; - -static struct ep93xxfb_mach_info __initdata simone_fb_info = { - .flags = EP93XXFB_USE_SDCSN0 | EP93XXFB_PCLK_FALLING, -}; - -static struct mmc_spi_platform_data simone_mmc_spi_data = { - .detect_delay = 500, - .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, -}; - -static struct gpiod_lookup_table simone_mmc_spi_gpio_table = { - .dev_id = "mmc_spi.0", /* "mmc_spi" @ CS0 */ - .table = { - /* Card detect */ - GPIO_LOOKUP_IDX("A", 0, NULL, 0, GPIO_ACTIVE_LOW), - { }, - }, -}; - -static struct spi_board_info simone_spi_devices[] __initdata = { - { - .modalias = "mmc_spi", - .platform_data = &simone_mmc_spi_data, - /* - * We use 10 MHz even though the maximum is 3.7 MHz. The driver - * will limit it automatically to max. frequency. - */ - .max_speed_hz = 10 * 1000 * 1000, - .bus_num = 0, - .chip_select = 0, - .mode = SPI_MODE_3, - }, -}; - -/* - * Up to v1.3, the Sim.One used SFRMOUT as SD card chip select, but this goes - * low between multi-message command blocks. From v1.4, it uses a GPIO instead. - * v1.3 parts will still work, since the signal on SFRMOUT is automatic. - */ -static struct gpiod_lookup_table simone_spi_cs_gpio_table = { - .dev_id = "spi0", - .table = { - GPIO_LOOKUP("A", 1, "cs", GPIO_ACTIVE_LOW), - { }, - }, -}; - -static struct ep93xx_spi_info simone_spi_info __initdata = { - .use_dma = 1, -}; - -static struct i2c_board_info __initdata simone_i2c_board_info[] = { - { - I2C_BOARD_INFO("ds1337", 0x68), - }, -}; - -static struct platform_device simone_audio_device = { - .name = "simone-audio", - .id = -1, -}; - -static void __init simone_register_audio(void) -{ - ep93xx_register_ac97(); - platform_device_register(&simone_audio_device); -} - -static void __init simone_init_machine(void) -{ - ep93xx_init_devices(); - ep93xx_register_flash(2, EP93XX_CS6_PHYS_BASE, SZ_8M); - ep93xx_register_eth(&simone_eth_data, 1); - ep93xx_register_fb(&simone_fb_info); - ep93xx_register_i2c(simone_i2c_board_info, - ARRAY_SIZE(simone_i2c_board_info)); - gpiod_add_lookup_table(&simone_mmc_spi_gpio_table); - gpiod_add_lookup_table(&simone_spi_cs_gpio_table); - ep93xx_register_spi(&simone_spi_info, simone_spi_devices, - ARRAY_SIZE(simone_spi_devices)); - simone_register_audio(); -} - -MACHINE_START(SIM_ONE, "Simplemachines Sim.One Board") - /* Maintainer: Ryan Mallon */ - .atag_offset = 0x100, - .nr_irqs = NR_EP93XX_IRQS, - .map_io = ep93xx_map_io, - .init_irq = ep93xx_init_irq, - .init_time = ep93xx_timer_init, - .init_machine = simone_init_machine, - .restart = ep93xx_restart, -MACHINE_END diff --git a/arch/arm/mach-ep93xx/snappercl15.c b/arch/arm/mach-ep93xx/snappercl15.c deleted file mode 100644 index 1dfb725671b1..000000000000 --- a/arch/arm/mach-ep93xx/snappercl15.c +++ /dev/null @@ -1,162 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * arch/arm/mach-ep93xx/snappercl15.c - * Bluewater Systems Snapper CL15 system module - * - * Copyright (C) 2009 Bluewater Systems Ltd - * Author: Ryan Mallon - * - * NAND code adapted from driver by: - * Andre Renaud - * James R. McKaskill - */ - -#include -#include -#include -#include -#include -#include - -#include - -#include "hardware.h" -#include -#include "gpio-ep93xx.h" - -#include -#include - -#include "soc.h" - -#define SNAPPERCL15_NAND_BASE (EP93XX_CS7_PHYS_BASE + SZ_16M) - -#define SNAPPERCL15_NAND_WPN (1 << 8) /* Write protect (active low) */ -#define SNAPPERCL15_NAND_ALE (1 << 9) /* Address latch */ -#define SNAPPERCL15_NAND_CLE (1 << 10) /* Command latch */ -#define SNAPPERCL15_NAND_CEN (1 << 11) /* Chip enable (active low) */ -#define SNAPPERCL15_NAND_RDY (1 << 14) /* Device ready */ - -#define NAND_CTRL_ADDR(chip) (chip->legacy.IO_ADDR_W + 0x40) - -static void snappercl15_nand_cmd_ctrl(struct nand_chip *chip, int cmd, - unsigned int ctrl) -{ - static u16 nand_state = SNAPPERCL15_NAND_WPN; - u16 set; - - if (ctrl & NAND_CTRL_CHANGE) { - set = SNAPPERCL15_NAND_CEN | SNAPPERCL15_NAND_WPN; - - if (ctrl & NAND_NCE) - set &= ~SNAPPERCL15_NAND_CEN; - if (ctrl & NAND_CLE) - set |= SNAPPERCL15_NAND_CLE; - if (ctrl & NAND_ALE) - set |= SNAPPERCL15_NAND_ALE; - - nand_state &= ~(SNAPPERCL15_NAND_CEN | - SNAPPERCL15_NAND_CLE | - SNAPPERCL15_NAND_ALE); - nand_state |= set; - __raw_writew(nand_state, NAND_CTRL_ADDR(chip)); - } - - if (cmd != NAND_CMD_NONE) - __raw_writew((cmd & 0xff) | nand_state, - chip->legacy.IO_ADDR_W); -} - -static int snappercl15_nand_dev_ready(struct nand_chip *chip) -{ - return !!(__raw_readw(NAND_CTRL_ADDR(chip)) & SNAPPERCL15_NAND_RDY); -} - -static struct mtd_partition snappercl15_nand_parts[] = { - { - .name = "Kernel", - .offset = 0, - .size = SZ_2M, - }, - { - .name = "Filesystem", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - }, -}; - -static struct platform_nand_data snappercl15_nand_data = { - .chip = { - .nr_chips = 1, - .partitions = snappercl15_nand_parts, - .nr_partitions = ARRAY_SIZE(snappercl15_nand_parts), - .chip_delay = 25, - }, - .ctrl = { - .dev_ready = snappercl15_nand_dev_ready, - .cmd_ctrl = snappercl15_nand_cmd_ctrl, - }, -}; - -static struct resource snappercl15_nand_resource[] = { - { - .start = SNAPPERCL15_NAND_BASE, - .end = SNAPPERCL15_NAND_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device snappercl15_nand_device = { - .name = "gen_nand", - .id = -1, - .dev.platform_data = &snappercl15_nand_data, - .resource = snappercl15_nand_resource, - .num_resources = ARRAY_SIZE(snappercl15_nand_resource), -}; - -static struct ep93xx_eth_data __initdata snappercl15_eth_data = { - .phy_id = 1, -}; - -static struct i2c_board_info __initdata snappercl15_i2c_data[] = { - { - /* Audio codec */ - I2C_BOARD_INFO("tlv320aic23", 0x1a), - }, -}; - -static struct ep93xxfb_mach_info __initdata snappercl15_fb_info = { -}; - -static struct platform_device snappercl15_audio_device = { - .name = "snappercl15-audio", - .id = -1, -}; - -static void __init snappercl15_register_audio(void) -{ - ep93xx_register_i2s(); - platform_device_register(&snappercl15_audio_device); -} - -static void __init snappercl15_init_machine(void) -{ - ep93xx_init_devices(); - ep93xx_register_eth(&snappercl15_eth_data, 1); - ep93xx_register_i2c(snappercl15_i2c_data, - ARRAY_SIZE(snappercl15_i2c_data)); - ep93xx_register_fb(&snappercl15_fb_info); - snappercl15_register_audio(); - platform_device_register(&snappercl15_nand_device); -} - -MACHINE_START(SNAPPER_CL15, "Bluewater Systems Snapper CL15") - /* Maintainer: Ryan Mallon */ - .atag_offset = 0x100, - .nr_irqs = NR_EP93XX_IRQS, - .map_io = ep93xx_map_io, - .init_irq = ep93xx_init_irq, - .init_time = ep93xx_timer_init, - .init_machine = snappercl15_init_machine, - .restart = ep93xx_restart, -MACHINE_END From patchwork Wed Oct 19 15:03:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnd Bergmann X-Patchwork-Id: 5685 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp385650wrs; Wed, 19 Oct 2022 08:23:01 -0700 (PDT) X-Google-Smtp-Source: AMsMyM40WS747SFV2bvPdGltlDPORceLYAXRjdLdCLZfCu9qke6Rk6hErsx+scPw1JmemUAq2WjQ X-Received: by 2002:a05:6402:1052:b0:459:2c49:1aed with SMTP id e18-20020a056402105200b004592c491aedmr7971217edu.212.1666192980957; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id e19-20020a17090658d300b007829d30452asi17809654ejs.583.2022.10.19.08.22.34; Wed, 19 Oct 2022 08:23:00 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=vCT0t7tv; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229795AbiJSPWH (ORCPT + 99 others); Wed, 19 Oct 2022 11:22:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49966 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232355AbiJSPVw (ORCPT ); Wed, 19 Oct 2022 11:21:52 -0400 Received: from sin.source.kernel.org (sin.source.kernel.org [IPv6:2604:1380:40e1:4800::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C120816EA3F for ; Wed, 19 Oct 2022 08:15:08 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id EAD6DCE20F4 for ; Wed, 19 Oct 2022 15:08:35 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id C30C8C433C1; Wed, 19 Oct 2022 15:08:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1666192114; bh=rM4ihlMZEz7jlcwFH6NvhSrb6DAtLdGVREDYqsgOkLk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=vCT0t7tvprdK7zo6svNHgNTnSX1/KyaKyT+me2OTatE/jtZ8ikR12LnKP+1QhJczQ ito+QZQ0OrFGnrfdb+itbPTFS+w9r0q0lGSEs4yw183c1GnRKJ2rvPob3JNCZxYaZz yE/ldLK4QdB+OkY0XB8o4cKY+PnwqOjnvaDY1d0ZkN0qucJOLkIGgTG+WDzed/suHK E4z2QzIKUnzGC9fy4mOs7sOGG8OW+np7F/ffFFJSvskFc9+RwImxkmLkSG5BuZ5v+c Iv8TU8zZrOGJXnSIWK6MXPIv79rL6BYowrVAVPEKgAuhiwMg3kerIkwTweEJTuQDQ3 EdqSfuBc3KJUA== From: Arnd Bergmann To: linux-arm-kernel@lists.infradead.org, Liam Girdwood , Mark Brown , Jaroslav Kysela , Takashi Iwai Cc: linux-kernel@vger.kernel.org, Arnd Bergmann , Mika Westerberg , Ryan Mallon , Charles Keepax , alsa-devel@alsa-project.org Subject: [PATCH 05/17] ASoC: remove unused ep93xx files Date: Wed, 19 Oct 2022 17:03:27 +0200 Message-Id: <20221019150410.3851944-5-arnd@kernel.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20221019150410.3851944-1-arnd@kernel.org> References: <20221019144119.3848027-1-arnd@kernel.org> <20221019150410.3851944-1-arnd@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747129971042401713?= X-GMAIL-MSGID: =?utf-8?q?1747129971042401713?= From: Arnd Bergmann A couple of ep93xx board files were unused and got removed, so the corresponding ASoC support can also be removed. Cc: Mika Westerberg Cc: Ryan Mallon Signed-off-by: Arnd Bergmann Acked-by: Mark Brown --- sound/soc/cirrus/Kconfig | 23 -- sound/soc/cirrus/Makefile | 6 - sound/soc/cirrus/ep93xx-ac97.c | 446 --------------------------------- sound/soc/cirrus/simone.c | 86 ------- sound/soc/cirrus/snappercl15.c | 134 ---------- 5 files changed, 695 deletions(-) delete mode 100644 sound/soc/cirrus/ep93xx-ac97.c delete mode 100644 sound/soc/cirrus/simone.c delete mode 100644 sound/soc/cirrus/snappercl15.c diff --git a/sound/soc/cirrus/Kconfig b/sound/soc/cirrus/Kconfig index 8039a8febefa..34870c2d0cba 100644 --- a/sound/soc/cirrus/Kconfig +++ b/sound/soc/cirrus/Kconfig @@ -27,29 +27,6 @@ config SND_EP93XX_SOC_I2S_WATCHDOG endif # if SND_EP93XX_SOC_I2S -config SND_EP93XX_SOC_AC97 - tristate - select AC97_BUS - select SND_SOC_AC97_BUS - -config SND_EP93XX_SOC_SNAPPERCL15 - tristate "SoC Audio support for Bluewater Systems Snapper CL15 module" - depends on SND_EP93XX_SOC && MACH_SNAPPER_CL15 && I2C - select SND_EP93XX_SOC_I2S - select SND_SOC_TLV320AIC23_I2C - help - Say Y or M here if you want to add support for I2S audio on the - Bluewater Systems Snapper CL15 module. - -config SND_EP93XX_SOC_SIMONE - tristate "SoC Audio support for Simplemachines Sim.One board" - depends on SND_EP93XX_SOC && MACH_SIM_ONE - select SND_EP93XX_SOC_AC97 - select SND_SOC_AC97_CODEC - help - Say Y or M here if you want to add support for AC97 audio on the - Simplemachines Sim.One board. - config SND_EP93XX_SOC_EDB93XX tristate "SoC Audio support for Cirrus Logic EDB93xx boards" depends on SND_EP93XX_SOC && (MACH_EDB9301 || MACH_EDB9302 || MACH_EDB9302A || MACH_EDB9307A || MACH_EDB9315A) diff --git a/sound/soc/cirrus/Makefile b/sound/soc/cirrus/Makefile index bfb8dc409f53..19a86daad660 100644 --- a/sound/soc/cirrus/Makefile +++ b/sound/soc/cirrus/Makefile @@ -2,17 +2,11 @@ # EP93xx Platform Support snd-soc-ep93xx-objs := ep93xx-pcm.o snd-soc-ep93xx-i2s-objs := ep93xx-i2s.o -snd-soc-ep93xx-ac97-objs := ep93xx-ac97.o obj-$(CONFIG_SND_EP93XX_SOC) += snd-soc-ep93xx.o obj-$(CONFIG_SND_EP93XX_SOC_I2S) += snd-soc-ep93xx-i2s.o -obj-$(CONFIG_SND_EP93XX_SOC_AC97) += snd-soc-ep93xx-ac97.o # EP93XX Machine Support -snd-soc-snappercl15-objs := snappercl15.o -snd-soc-simone-objs := simone.o snd-soc-edb93xx-objs := edb93xx.o -obj-$(CONFIG_SND_EP93XX_SOC_SNAPPERCL15) += snd-soc-snappercl15.o -obj-$(CONFIG_SND_EP93XX_SOC_SIMONE) += snd-soc-simone.o obj-$(CONFIG_SND_EP93XX_SOC_EDB93XX) += snd-soc-edb93xx.o diff --git a/sound/soc/cirrus/ep93xx-ac97.c b/sound/soc/cirrus/ep93xx-ac97.c deleted file mode 100644 index 37593abe6053..000000000000 --- a/sound/soc/cirrus/ep93xx-ac97.c +++ /dev/null @@ -1,446 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * ASoC driver for Cirrus Logic EP93xx AC97 controller. - * - * Copyright (c) 2010 Mika Westerberg - * - * Based on s3c-ac97 ASoC driver by Jaswinder Singh. - */ - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include -#include - -#include "ep93xx-pcm.h" - -/* - * Per channel (1-4) registers. - */ -#define AC97CH(n) (((n) - 1) * 0x20) - -#define AC97DR(n) (AC97CH(n) + 0x0000) - -#define AC97RXCR(n) (AC97CH(n) + 0x0004) -#define AC97RXCR_REN BIT(0) -#define AC97RXCR_RX3 BIT(3) -#define AC97RXCR_RX4 BIT(4) -#define AC97RXCR_CM BIT(15) - -#define AC97TXCR(n) (AC97CH(n) + 0x0008) -#define AC97TXCR_TEN BIT(0) -#define AC97TXCR_TX3 BIT(3) -#define AC97TXCR_TX4 BIT(4) -#define AC97TXCR_CM BIT(15) - -#define AC97SR(n) (AC97CH(n) + 0x000c) -#define AC97SR_TXFE BIT(1) -#define AC97SR_TXUE BIT(6) - -#define AC97RISR(n) (AC97CH(n) + 0x0010) -#define AC97ISR(n) (AC97CH(n) + 0x0014) -#define AC97IE(n) (AC97CH(n) + 0x0018) - -/* - * Global AC97 controller registers. - */ -#define AC97S1DATA 0x0080 -#define AC97S2DATA 0x0084 -#define AC97S12DATA 0x0088 - -#define AC97RGIS 0x008c -#define AC97GIS 0x0090 -#define AC97IM 0x0094 -/* - * Common bits for RGIS, GIS and IM registers. - */ -#define AC97_SLOT2RXVALID BIT(1) -#define AC97_CODECREADY BIT(5) -#define AC97_SLOT2TXCOMPLETE BIT(6) - -#define AC97EOI 0x0098 -#define AC97EOI_WINT BIT(0) -#define AC97EOI_CODECREADY BIT(1) - -#define AC97GCR 0x009c -#define AC97GCR_AC97IFE BIT(0) - -#define AC97RESET 0x00a0 -#define AC97RESET_TIMEDRESET BIT(0) - -#define AC97SYNC 0x00a4 -#define AC97SYNC_TIMEDSYNC BIT(0) - -#define AC97_TIMEOUT msecs_to_jiffies(5) - -/** - * struct ep93xx_ac97_info - EP93xx AC97 controller info structure - * @lock: mutex serializing access to the bus (slot 1 & 2 ops) - * @dev: pointer to the platform device dev structure - * @regs: mapped AC97 controller registers - * @done: bus ops wait here for an interrupt - */ -struct ep93xx_ac97_info { - struct mutex lock; - struct device *dev; - void __iomem *regs; - struct completion done; - struct snd_dmaengine_dai_dma_data dma_params_rx; - struct snd_dmaengine_dai_dma_data dma_params_tx; -}; - -/* currently ALSA only supports a single AC97 device */ -static struct ep93xx_ac97_info *ep93xx_ac97_info; - -static struct ep93xx_dma_data ep93xx_ac97_pcm_out = { - .name = "ac97-pcm-out", - .port = EP93XX_DMA_AAC1, - .direction = DMA_MEM_TO_DEV, -}; - -static struct ep93xx_dma_data ep93xx_ac97_pcm_in = { - .name = "ac97-pcm-in", - .port = EP93XX_DMA_AAC1, - .direction = DMA_DEV_TO_MEM, -}; - -static inline unsigned ep93xx_ac97_read_reg(struct ep93xx_ac97_info *info, - unsigned reg) -{ - return __raw_readl(info->regs + reg); -} - -static inline void ep93xx_ac97_write_reg(struct ep93xx_ac97_info *info, - unsigned reg, unsigned val) -{ - __raw_writel(val, info->regs + reg); -} - -static unsigned short ep93xx_ac97_read(struct snd_ac97 *ac97, - unsigned short reg) -{ - struct ep93xx_ac97_info *info = ep93xx_ac97_info; - unsigned short val; - - mutex_lock(&info->lock); - - ep93xx_ac97_write_reg(info, AC97S1DATA, reg); - ep93xx_ac97_write_reg(info, AC97IM, AC97_SLOT2RXVALID); - if (!wait_for_completion_timeout(&info->done, AC97_TIMEOUT)) { - dev_warn(info->dev, "timeout reading register %x\n", reg); - mutex_unlock(&info->lock); - return -ETIMEDOUT; - } - val = (unsigned short)ep93xx_ac97_read_reg(info, AC97S2DATA); - - mutex_unlock(&info->lock); - return val; -} - -static void ep93xx_ac97_write(struct snd_ac97 *ac97, - unsigned short reg, - unsigned short val) -{ - struct ep93xx_ac97_info *info = ep93xx_ac97_info; - - mutex_lock(&info->lock); - - /* - * Writes to the codec need to be done so that slot 2 is filled in - * before slot 1. - */ - ep93xx_ac97_write_reg(info, AC97S2DATA, val); - ep93xx_ac97_write_reg(info, AC97S1DATA, reg); - - ep93xx_ac97_write_reg(info, AC97IM, AC97_SLOT2TXCOMPLETE); - if (!wait_for_completion_timeout(&info->done, AC97_TIMEOUT)) - dev_warn(info->dev, "timeout writing register %x\n", reg); - - mutex_unlock(&info->lock); -} - -static void ep93xx_ac97_warm_reset(struct snd_ac97 *ac97) -{ - struct ep93xx_ac97_info *info = ep93xx_ac97_info; - - mutex_lock(&info->lock); - - /* - * We are assuming that before this functions gets called, the codec - * BIT_CLK is stopped by forcing the codec into powerdown mode. We can - * control the SYNC signal directly via AC97SYNC register. Using - * TIMEDSYNC the controller will keep the SYNC high > 1us. - */ - ep93xx_ac97_write_reg(info, AC97SYNC, AC97SYNC_TIMEDSYNC); - ep93xx_ac97_write_reg(info, AC97IM, AC97_CODECREADY); - if (!wait_for_completion_timeout(&info->done, AC97_TIMEOUT)) - dev_warn(info->dev, "codec warm reset timeout\n"); - - mutex_unlock(&info->lock); -} - -static void ep93xx_ac97_cold_reset(struct snd_ac97 *ac97) -{ - struct ep93xx_ac97_info *info = ep93xx_ac97_info; - - mutex_lock(&info->lock); - - /* - * For doing cold reset, we disable the AC97 controller interface, clear - * WINT and CODECREADY bits, and finally enable the interface again. - */ - ep93xx_ac97_write_reg(info, AC97GCR, 0); - ep93xx_ac97_write_reg(info, AC97EOI, AC97EOI_CODECREADY | AC97EOI_WINT); - ep93xx_ac97_write_reg(info, AC97GCR, AC97GCR_AC97IFE); - - /* - * Now, assert the reset and wait for the codec to become ready. - */ - ep93xx_ac97_write_reg(info, AC97RESET, AC97RESET_TIMEDRESET); - ep93xx_ac97_write_reg(info, AC97IM, AC97_CODECREADY); - if (!wait_for_completion_timeout(&info->done, AC97_TIMEOUT)) - dev_warn(info->dev, "codec cold reset timeout\n"); - - /* - * Give the codec some time to come fully out from the reset. This way - * we ensure that the subsequent reads/writes will work. - */ - usleep_range(15000, 20000); - - mutex_unlock(&info->lock); -} - -static irqreturn_t ep93xx_ac97_interrupt(int irq, void *dev_id) -{ - struct ep93xx_ac97_info *info = dev_id; - unsigned status, mask; - - /* - * Just mask out the interrupt and wake up the waiting thread. - * Interrupts are cleared via reading/writing to slot 1 & 2 registers by - * the waiting thread. - */ - status = ep93xx_ac97_read_reg(info, AC97GIS); - mask = ep93xx_ac97_read_reg(info, AC97IM); - mask &= ~status; - ep93xx_ac97_write_reg(info, AC97IM, mask); - - complete(&info->done); - return IRQ_HANDLED; -} - -static struct snd_ac97_bus_ops ep93xx_ac97_ops = { - .read = ep93xx_ac97_read, - .write = ep93xx_ac97_write, - .reset = ep93xx_ac97_cold_reset, - .warm_reset = ep93xx_ac97_warm_reset, -}; - -static int ep93xx_ac97_trigger(struct snd_pcm_substream *substream, - int cmd, struct snd_soc_dai *dai) -{ - struct ep93xx_ac97_info *info = snd_soc_dai_get_drvdata(dai); - unsigned v = 0; - - switch (cmd) { - case SNDRV_PCM_TRIGGER_START: - case SNDRV_PCM_TRIGGER_RESUME: - case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: - if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { - /* - * Enable compact mode, TX slots 3 & 4, and the TX FIFO - * itself. - */ - v |= AC97TXCR_CM; - v |= AC97TXCR_TX3 | AC97TXCR_TX4; - v |= AC97TXCR_TEN; - ep93xx_ac97_write_reg(info, AC97TXCR(1), v); - } else { - /* - * Enable compact mode, RX slots 3 & 4, and the RX FIFO - * itself. - */ - v |= AC97RXCR_CM; - v |= AC97RXCR_RX3 | AC97RXCR_RX4; - v |= AC97RXCR_REN; - ep93xx_ac97_write_reg(info, AC97RXCR(1), v); - } - break; - - case SNDRV_PCM_TRIGGER_STOP: - case SNDRV_PCM_TRIGGER_SUSPEND: - case SNDRV_PCM_TRIGGER_PAUSE_PUSH: - if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { - /* - * As per Cirrus EP93xx errata described below: - * - * https://www.cirrus.com/en/pubs/errata/ER667E2B.pdf - * - * we will wait for the TX FIFO to be empty before - * clearing the TEN bit. - */ - unsigned long timeout = jiffies + AC97_TIMEOUT; - - do { - v = ep93xx_ac97_read_reg(info, AC97SR(1)); - if (time_after(jiffies, timeout)) { - dev_warn(info->dev, "TX timeout\n"); - break; - } - } while (!(v & (AC97SR_TXFE | AC97SR_TXUE))); - - /* disable the TX FIFO */ - ep93xx_ac97_write_reg(info, AC97TXCR(1), 0); - } else { - /* disable the RX FIFO */ - ep93xx_ac97_write_reg(info, AC97RXCR(1), 0); - } - break; - - default: - dev_warn(info->dev, "unknown command %d\n", cmd); - return -EINVAL; - } - - return 0; -} - -static int ep93xx_ac97_dai_probe(struct snd_soc_dai *dai) -{ - struct ep93xx_ac97_info *info = snd_soc_dai_get_drvdata(dai); - - info->dma_params_tx.filter_data = &ep93xx_ac97_pcm_out; - info->dma_params_rx.filter_data = &ep93xx_ac97_pcm_in; - - dai->playback_dma_data = &info->dma_params_tx; - dai->capture_dma_data = &info->dma_params_rx; - - return 0; -} - -static const struct snd_soc_dai_ops ep93xx_ac97_dai_ops = { - .trigger = ep93xx_ac97_trigger, -}; - -static struct snd_soc_dai_driver ep93xx_ac97_dai = { - .name = "ep93xx-ac97", - .id = 0, - .probe = ep93xx_ac97_dai_probe, - .playback = { - .stream_name = "AC97 Playback", - .channels_min = 2, - .channels_max = 2, - .rates = SNDRV_PCM_RATE_8000_48000, - .formats = SNDRV_PCM_FMTBIT_S16_LE, - }, - .capture = { - .stream_name = "AC97 Capture", - .channels_min = 2, - .channels_max = 2, - .rates = SNDRV_PCM_RATE_8000_48000, - .formats = SNDRV_PCM_FMTBIT_S16_LE, - }, - .ops = &ep93xx_ac97_dai_ops, -}; - -static const struct snd_soc_component_driver ep93xx_ac97_component = { - .name = "ep93xx-ac97", - .legacy_dai_naming = 1, -}; - -static int ep93xx_ac97_probe(struct platform_device *pdev) -{ - struct ep93xx_ac97_info *info; - int irq; - int ret; - - info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); - if (!info) - return -ENOMEM; - - info->regs = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(info->regs)) - return PTR_ERR(info->regs); - - irq = platform_get_irq(pdev, 0); - if (irq <= 0) - return irq < 0 ? irq : -ENODEV; - - ret = devm_request_irq(&pdev->dev, irq, ep93xx_ac97_interrupt, - IRQF_TRIGGER_HIGH, pdev->name, info); - if (ret) - goto fail; - - dev_set_drvdata(&pdev->dev, info); - - mutex_init(&info->lock); - init_completion(&info->done); - info->dev = &pdev->dev; - - ep93xx_ac97_info = info; - platform_set_drvdata(pdev, info); - - ret = snd_soc_set_ac97_ops(&ep93xx_ac97_ops); - if (ret) - goto fail; - - ret = snd_soc_register_component(&pdev->dev, &ep93xx_ac97_component, - &ep93xx_ac97_dai, 1); - if (ret) - goto fail; - - ret = devm_ep93xx_pcm_platform_register(&pdev->dev); - if (ret) - goto fail_unregister; - - return 0; - -fail_unregister: - snd_soc_unregister_component(&pdev->dev); -fail: - ep93xx_ac97_info = NULL; - snd_soc_set_ac97_ops(NULL); - return ret; -} - -static int ep93xx_ac97_remove(struct platform_device *pdev) -{ - struct ep93xx_ac97_info *info = platform_get_drvdata(pdev); - - snd_soc_unregister_component(&pdev->dev); - - /* disable the AC97 controller */ - ep93xx_ac97_write_reg(info, AC97GCR, 0); - - ep93xx_ac97_info = NULL; - - snd_soc_set_ac97_ops(NULL); - - return 0; -} - -static struct platform_driver ep93xx_ac97_driver = { - .probe = ep93xx_ac97_probe, - .remove = ep93xx_ac97_remove, - .driver = { - .name = "ep93xx-ac97", - }, -}; - -module_platform_driver(ep93xx_ac97_driver); - -MODULE_DESCRIPTION("EP93xx AC97 ASoC Driver"); -MODULE_AUTHOR("Mika Westerberg "); -MODULE_LICENSE("GPL"); -MODULE_ALIAS("platform:ep93xx-ac97"); diff --git a/sound/soc/cirrus/simone.c b/sound/soc/cirrus/simone.c deleted file mode 100644 index 801c90877d77..000000000000 --- a/sound/soc/cirrus/simone.c +++ /dev/null @@ -1,86 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * simone.c -- ASoC audio for Simplemachines Sim.One board - * - * Copyright (c) 2010 Mika Westerberg - * - * Based on snappercl15 machine driver by Ryan Mallon. - */ - -#include -#include -#include -#include - -#include -#include -#include - -#include - -SND_SOC_DAILINK_DEFS(hifi, - DAILINK_COMP_ARRAY(COMP_CPU("ep93xx-ac97")), - DAILINK_COMP_ARRAY(COMP_CODEC("ac97-codec", "ac97-hifi")), - DAILINK_COMP_ARRAY(COMP_PLATFORM("ep93xx-ac97"))); - -static struct snd_soc_dai_link simone_dai = { - .name = "AC97", - .stream_name = "AC97 HiFi", - SND_SOC_DAILINK_REG(hifi), -}; - -static struct snd_soc_card snd_soc_simone = { - .name = "Sim.One", - .owner = THIS_MODULE, - .dai_link = &simone_dai, - .num_links = 1, -}; - -static struct platform_device *simone_snd_ac97_device; - -static int simone_probe(struct platform_device *pdev) -{ - struct snd_soc_card *card = &snd_soc_simone; - int ret; - - simone_snd_ac97_device = platform_device_register_simple("ac97-codec", - -1, NULL, 0); - if (IS_ERR(simone_snd_ac97_device)) - return PTR_ERR(simone_snd_ac97_device); - - card->dev = &pdev->dev; - - ret = snd_soc_register_card(card); - if (ret) { - dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n", - ret); - platform_device_unregister(simone_snd_ac97_device); - } - - return ret; -} - -static int simone_remove(struct platform_device *pdev) -{ - struct snd_soc_card *card = platform_get_drvdata(pdev); - - snd_soc_unregister_card(card); - platform_device_unregister(simone_snd_ac97_device); - - return 0; -} - -static struct platform_driver simone_driver = { - .driver = { - .name = "simone-audio", - }, - .probe = simone_probe, - .remove = simone_remove, -}; - -module_platform_driver(simone_driver); - -MODULE_DESCRIPTION("ALSA SoC Simplemachines Sim.One"); -MODULE_AUTHOR("Mika Westerberg "); -MODULE_LICENSE("GPL"); -MODULE_ALIAS("platform:simone-audio"); diff --git a/sound/soc/cirrus/snappercl15.c b/sound/soc/cirrus/snappercl15.c deleted file mode 100644 index a286f5beeaeb..000000000000 --- a/sound/soc/cirrus/snappercl15.c +++ /dev/null @@ -1,134 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * snappercl15.c -- SoC audio for Bluewater Systems Snapper CL15 module - * - * Copyright (C) 2008 Bluewater Systems Ltd - * Author: Ryan Mallon - */ - -#include -#include -#include -#include -#include -#include - -#include - -#include "../codecs/tlv320aic23.h" - -#define CODEC_CLOCK 5644800 - -static int snappercl15_hw_params(struct snd_pcm_substream *substream, - struct snd_pcm_hw_params *params) -{ - struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); - struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0); - struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0); - int err; - - err = snd_soc_dai_set_sysclk(codec_dai, 0, CODEC_CLOCK, - SND_SOC_CLOCK_IN); - if (err) - return err; - - err = snd_soc_dai_set_sysclk(cpu_dai, 0, CODEC_CLOCK, - SND_SOC_CLOCK_OUT); - if (err) - return err; - - return 0; -} - -static const struct snd_soc_ops snappercl15_ops = { - .hw_params = snappercl15_hw_params, -}; - -static const struct snd_soc_dapm_widget tlv320aic23_dapm_widgets[] = { - SND_SOC_DAPM_HP("Headphone Jack", NULL), - SND_SOC_DAPM_LINE("Line In", NULL), - SND_SOC_DAPM_MIC("Mic Jack", NULL), -}; - -static const struct snd_soc_dapm_route audio_map[] = { - {"Headphone Jack", NULL, "LHPOUT"}, - {"Headphone Jack", NULL, "RHPOUT"}, - - {"LLINEIN", NULL, "Line In"}, - {"RLINEIN", NULL, "Line In"}, - - {"MICIN", NULL, "Mic Jack"}, -}; - -SND_SOC_DAILINK_DEFS(aic23, - DAILINK_COMP_ARRAY(COMP_CPU("ep93xx-i2s")), - DAILINK_COMP_ARRAY(COMP_CODEC("tlv320aic23-codec.0-001a", - "tlv320aic23-hifi")), - DAILINK_COMP_ARRAY(COMP_PLATFORM("ep93xx-i2s"))); - -static struct snd_soc_dai_link snappercl15_dai = { - .name = "tlv320aic23", - .stream_name = "AIC23", - .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | - SND_SOC_DAIFMT_CBC_CFC, - .ops = &snappercl15_ops, - SND_SOC_DAILINK_REG(aic23), -}; - -static struct snd_soc_card snd_soc_snappercl15 = { - .name = "Snapper CL15", - .owner = THIS_MODULE, - .dai_link = &snappercl15_dai, - .num_links = 1, - - .dapm_widgets = tlv320aic23_dapm_widgets, - .num_dapm_widgets = ARRAY_SIZE(tlv320aic23_dapm_widgets), - .dapm_routes = audio_map, - .num_dapm_routes = ARRAY_SIZE(audio_map), -}; - -static int snappercl15_probe(struct platform_device *pdev) -{ - struct snd_soc_card *card = &snd_soc_snappercl15; - int ret; - - ret = ep93xx_i2s_acquire(); - if (ret) - return ret; - - card->dev = &pdev->dev; - - ret = snd_soc_register_card(card); - if (ret) { - dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n", - ret); - ep93xx_i2s_release(); - } - - return ret; -} - -static int snappercl15_remove(struct platform_device *pdev) -{ - struct snd_soc_card *card = platform_get_drvdata(pdev); - - snd_soc_unregister_card(card); - ep93xx_i2s_release(); - - return 0; -} - -static struct platform_driver snappercl15_driver = { - .driver = { - .name = "snappercl15-audio", - }, - .probe = snappercl15_probe, - .remove = snappercl15_remove, -}; - -module_platform_driver(snappercl15_driver); - -MODULE_AUTHOR("Ryan Mallon"); -MODULE_DESCRIPTION("ALSA SoC Snapper CL15"); -MODULE_LICENSE("GPL"); -MODULE_ALIAS("platform:snappercl15-audio"); From patchwork Wed Oct 19 15:03:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnd Bergmann X-Patchwork-Id: 5675 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp384133wrs; Wed, 19 Oct 2022 08:20:00 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4fROoPROqQ1kJHgVwmxgiAN+hvRyInL7ZrygQw+v0IORdUD18qVyI3Pcmhl2P++qkLqoN2 X-Received: by 2002:a05:6402:440f:b0:45d:297b:c70a with SMTP id y15-20020a056402440f00b0045d297bc70amr8098015eda.187.1666192800458; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id i6-20020a05640242c600b0045cf886717esi16970236edc.18.2022.10.19.08.19.35; Wed, 19 Oct 2022 08:20:00 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b="kzLJa/CU"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232338AbiJSPRt (ORCPT + 99 others); Wed, 19 Oct 2022 11:17:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51666 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232001AbiJSPRX (ORCPT ); Wed, 19 Oct 2022 11:17:23 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CB787192988 for ; Wed, 19 Oct 2022 08:10:11 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 0EAD661908 for ; Wed, 19 Oct 2022 15:09:08 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id DD1C6C433D6; Wed, 19 Oct 2022 15:09:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1666192147; bh=zUtsmVJ8rL6oHo3JZVWiCC7ZDlsk1P/m+Y1Ap7DEApY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kzLJa/CUu5Mi0FdieqPlUEzMbFAQxp2ZABzGUDmbvMh5z6+G73KNBB4VUIbkHQuz6 MiiQ4rFsc38AvFb9ut3/URT/bL+1yI5jQf0o19A1KyfCgx2DV4HHHDcZGPWp+GTBd0 HOMfz+P9LK568wYAA/g5r/OSX1P3OP/e5JvJ0iddOsdCLtiwi8bN/WZTt6KPuszeSw HQuPwRLumAY0V/Eo6AjSBVia5hjeVX0Bb5cQ1zzrxbYoZDtcOwz0vjcrhbflv1VzfQ m/5Swk+7F6fyGgumh3zo9PIzeItRIFxfx53ysoZwpHxaIr2vSITGh//PY4gyBN7qxp aV7m/rAjtzFBg== From: Arnd Bergmann To: linux-arm-kernel@lists.infradead.org, Andrew Lunn , Sebastian Hesselbarth , Gregory Clement Cc: linux-kernel@vger.kernel.org, Arnd Bergmann , Russell King Subject: [PATCH 06/17] ARM: mv78xx0: un-deprecate Terastation WXL Date: Wed, 19 Oct 2022 17:03:28 +0200 Message-Id: <20221019150410.3851944-6-arnd@kernel.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20221019150410.3851944-1-arnd@kernel.org> References: <20221019144119.3848027-1-arnd@kernel.org> <20221019150410.3851944-1-arnd@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747129782059239155?= X-GMAIL-MSGID: =?utf-8?q?1747129782059239155?= From: Arnd Bergmann This board is still being worked on by the Debian-on-Buffalo project, so let's leave it in the tree for now. Link: https://github.com/1000001101000/Debian_on_Buffalo Cc: Andrew Lunn Cc: Sebastian Hesselbarth Cc: Gregory Clement Signed-off-by: Arnd Bergmann --- arch/arm/configs/mv78xx0_defconfig | 1 - arch/arm/mach-mv78xx0/Kconfig | 4 +++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/configs/mv78xx0_defconfig b/arch/arm/configs/mv78xx0_defconfig index 877c5150a987..f02f29d3fecb 100644 --- a/arch/arm/configs/mv78xx0_defconfig +++ b/arch/arm/configs/mv78xx0_defconfig @@ -17,7 +17,6 @@ CONFIG_MACH_TERASTATION_WXL=y CONFIG_AEABI=y CONFIG_HIGHMEM=y CONFIG_FPE_NWFPE=y -CONFIG_UNUSED_BOARD_FILES=y CONFIG_VFP=y CONFIG_KPROBES=y CONFIG_MODULES=y diff --git a/arch/arm/mach-mv78xx0/Kconfig b/arch/arm/mach-mv78xx0/Kconfig index da92f94494cc..0464b732ead4 100644 --- a/arch/arm/mach-mv78xx0/Kconfig +++ b/arch/arm/mach-mv78xx0/Kconfig @@ -3,7 +3,7 @@ menuconfig ARCH_MV78XX0 bool "Marvell MV78xx0" depends on ARCH_MULTI_V5 depends on CPU_LITTLE_ENDIAN - depends on ATAGS && UNUSED_BOARD_FILES + depends on ATAGS select CPU_FEROCEON select GPIOLIB select MVEBU_MBUS @@ -17,12 +17,14 @@ if ARCH_MV78XX0 config MACH_DB78X00_BP bool "Marvell DB-78x00-BP Development Board" + depends on UNUSED_BOARD_FILES help Say 'Y' here if you want your kernel to support the Marvell DB-78x00-BP Development Board. config MACH_RD78X00_MASA bool "Marvell RD-78x00-mASA Reference Design" + depends on UNUSED_BOARD_FILES help Say 'Y' here if you want your kernel to support the Marvell RD-78x00-mASA Reference Design. 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id e1-20020a17090618e100b00782af8d75fasi12230688ejf.252.2022.10.19.08.20.50; Wed, 19 Oct 2022 08:21:18 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=U1N9wdr4; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230221AbiJSPTf (ORCPT + 99 others); Wed, 19 Oct 2022 11:19:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55092 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232526AbiJSPS7 (ORCPT ); Wed, 19 Oct 2022 11:18:59 -0400 Received: from sin.source.kernel.org (sin.source.kernel.org [IPv6:2604:1380:40e1:4800::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 592F31D5862 for ; Wed, 19 Oct 2022 08:12:35 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id 13C21CE227D for ; Wed, 19 Oct 2022 15:10:19 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0E078C433C1; Wed, 19 Oct 2022 15:10:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1666192217; bh=3bz3ZJ7W3G70xB3Rbx04E4gW+0Cumc2wlNg08joku3o=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=U1N9wdr4v82PQ/U+dKiHdvkba4rPzJRwrpKUQn3ixtl+erVmf5wYsR04XguhAxDmU MBtzeyz0JsQqqc3UqbjWCG3l/H6jC+UNcgoPUeEcHhw74Lvar9KazBSpjDbQD1eRWM s8Ixdko53fTiCEC9RN/UAdiGqeUlnpR9OaO3+fbsSfaQBRLmGCyQDxpJDzV4KCvLYg D0b81rYxmAUxfeWjpj0UxRQRMZB/q+M/kX5BbwEgcxJo4SkLDDVkkmnVR8mGRltCF8 QfMz9M45YS8BHObgmAhpnmQu+9O8WZweHWJUkJmaWE7N29gL8/P+qHNpNdrYaLvaPX qoCdPYHzuulew== From: Arnd Bergmann To: linux-arm-kernel@lists.infradead.org, Andrew Lunn , Sebastian Hesselbarth , Gregory Clement Cc: linux-kernel@vger.kernel.org, Arnd Bergmann , Lennert Buytenhek , Nicolas Pitre , Imre Kaloz , Russell King Subject: [PATCH 07/17] ARM: orion: remove unused board files Date: Wed, 19 Oct 2022 17:03:29 +0200 Message-Id: <20221019150410.3851944-7-arnd@kernel.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20221019150410.3851944-1-arnd@kernel.org> References: <20221019144119.3848027-1-arnd@kernel.org> <20221019150410.3851944-1-arnd@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747129863805092986?= X-GMAIL-MSGID: =?utf-8?q?1747129863805092986?= From: Arnd Bergmann As planned earlier, all board support that was marked unused can be removed now after nobody explicitly asked for these to be kept. In particular, all of the reference designs get removed now, as these are not commonly used productively any more. Also, the machines that were not supported by Debian or the Debian_on_Buffalo group because of limitations with RAM size are gone. Cc: Lennert Buytenhek Cc: Nicolas Pitre Cc: Imre Kaloz Signed-off-by: Arnd Bergmann --- arch/arm/configs/mv78xx0_defconfig | 2 - arch/arm/mach-dove/Kconfig | 8 - arch/arm/mach-dove/Makefile | 1 - arch/arm/mach-dove/dove-db-setup.c | 101 ----- arch/arm/mach-mv78xx0/Kconfig | 14 - arch/arm/mach-mv78xx0/Makefile | 2 - arch/arm/mach-mv78xx0/db78x00-bp-setup.c | 101 ----- arch/arm/mach-mv78xx0/rd78x00-masa-setup.c | 86 ----- arch/arm/mach-orion5x/Kconfig | 59 --- arch/arm/mach-orion5x/Makefile | 8 - arch/arm/mach-orion5x/db88f5281-setup.c | 376 ------------------- arch/arm/mach-orion5x/ls_hgl-setup.c | 275 -------------- arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c | 172 --------- arch/arm/mach-orion5x/rd88f5181l-ge-setup.c | 183 --------- arch/arm/mach-orion5x/rd88f5182-setup.c | 288 -------------- arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c | 120 ------ arch/arm/mach-orion5x/wnr854t-setup.c | 175 --------- arch/arm/mach-orion5x/wrt350n-v2-setup.c | 263 ------------- 18 files changed, 2234 deletions(-) delete mode 100644 arch/arm/mach-dove/dove-db-setup.c delete mode 100644 arch/arm/mach-mv78xx0/db78x00-bp-setup.c delete mode 100644 arch/arm/mach-mv78xx0/rd78x00-masa-setup.c delete mode 100644 arch/arm/mach-orion5x/db88f5281-setup.c delete mode 100644 arch/arm/mach-orion5x/ls_hgl-setup.c delete mode 100644 arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c delete mode 100644 arch/arm/mach-orion5x/rd88f5181l-ge-setup.c delete mode 100644 arch/arm/mach-orion5x/rd88f5182-setup.c delete mode 100644 arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c delete mode 100644 arch/arm/mach-orion5x/wnr854t-setup.c delete mode 100644 arch/arm/mach-orion5x/wrt350n-v2-setup.c diff --git a/arch/arm/configs/mv78xx0_defconfig b/arch/arm/configs/mv78xx0_defconfig index f02f29d3fecb..3a1088079514 100644 --- a/arch/arm/configs/mv78xx0_defconfig +++ b/arch/arm/configs/mv78xx0_defconfig @@ -11,8 +11,6 @@ CONFIG_ARCH_MULTI_V5=y # CONFIG_ARCH_MULTI_V6 is not set # CONFIG_ARCH_MULTI_V7 is not set CONFIG_ARCH_MV78XX0=y -CONFIG_MACH_DB78X00_BP=y -CONFIG_MACH_RD78X00_MASA=y CONFIG_MACH_TERASTATION_WXL=y CONFIG_AEABI=y CONFIG_HIGHMEM=y diff --git a/arch/arm/mach-dove/Kconfig b/arch/arm/mach-dove/Kconfig index 2252f465cafd..996888ffcfe7 100644 --- a/arch/arm/mach-dove/Kconfig +++ b/arch/arm/mach-dove/Kconfig @@ -18,14 +18,6 @@ if ARCH_DOVE config DOVE_LEGACY bool -config MACH_DOVE_DB - bool "Marvell DB-MV88AP510 Development Board" - select DOVE_LEGACY - select I2C_BOARDINFO if I2C - help - Say 'Y' here if you want your kernel to support the - Marvell DB-MV88AP510 Development Board. - config MACH_CM_A510 bool "CompuLab CM-A510 Board" select DOVE_LEGACY diff --git a/arch/arm/mach-dove/Makefile b/arch/arm/mach-dove/Makefile index da373a5768ba..0d31390be069 100644 --- a/arch/arm/mach-dove/Makefile +++ b/arch/arm/mach-dove/Makefile @@ -4,5 +4,4 @@ ccflags-y := -I$(srctree)/arch/arm/plat-orion/include obj-y += common.o obj-$(CONFIG_DOVE_LEGACY) += irq.o mpp.o obj-$(CONFIG_PCI) += pcie.o -obj-$(CONFIG_MACH_DOVE_DB) += dove-db-setup.o obj-$(CONFIG_MACH_CM_A510) += cm-a510.o diff --git a/arch/arm/mach-dove/dove-db-setup.c b/arch/arm/mach-dove/dove-db-setup.c deleted file mode 100644 index d5bf54040577..000000000000 --- a/arch/arm/mach-dove/dove-db-setup.c +++ /dev/null @@ -1,101 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * arch/arm/mach-dove/dove-db-setup.c - * - * Marvell DB-MV88AP510-BP Development Board Setup - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "dove.h" -#include "common.h" - -static struct mv643xx_eth_platform_data dove_db_ge00_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR_DEFAULT, -}; - -static struct mv_sata_platform_data dove_db_sata_data = { - .n_ports = 1, -}; - -/***************************************************************************** - * SPI Devices: - * SPI0: 4M Flash ST-M25P32-VMF6P - ****************************************************************************/ -static const struct flash_platform_data dove_db_spi_flash_data = { - .type = "m25p64", -}; - -static struct spi_board_info __initdata dove_db_spi_flash_info[] = { - { - .modalias = "m25p80", - .platform_data = &dove_db_spi_flash_data, - .irq = -1, - .max_speed_hz = 20000000, - .bus_num = 0, - .chip_select = 0, - }, -}; - -/***************************************************************************** - * PCI - ****************************************************************************/ -static int __init dove_db_pci_init(void) -{ - if (machine_is_dove_db()) - dove_pcie_init(1, 1); - - return 0; -} - -subsys_initcall(dove_db_pci_init); - -/***************************************************************************** - * Board Init - ****************************************************************************/ -static void __init dove_db_init(void) -{ - /* - * Basic Dove setup. Needs to be called early. - */ - dove_init(); - - dove_ge00_init(&dove_db_ge00_data); - dove_ehci0_init(); - dove_ehci1_init(); - dove_sata_init(&dove_db_sata_data); - dove_sdio0_init(); - dove_sdio1_init(); - dove_spi0_init(); - dove_spi1_init(); - dove_uart0_init(); - dove_uart1_init(); - dove_i2c_init(); - spi_register_board_info(dove_db_spi_flash_info, - ARRAY_SIZE(dove_db_spi_flash_info)); -} - -MACHINE_START(DOVE_DB, "Marvell DB-MV88AP510-BP Development Board") - .atag_offset = 0x100, - .nr_irqs = DOVE_NR_IRQS, - .init_machine = dove_db_init, - .map_io = dove_map_io, - .init_early = dove_init_early, - .init_irq = dove_init_irq, - .init_time = dove_timer_init, - .restart = dove_restart, -MACHINE_END diff --git a/arch/arm/mach-mv78xx0/Kconfig b/arch/arm/mach-mv78xx0/Kconfig index 0464b732ead4..9de3bbc09c3a 100644 --- a/arch/arm/mach-mv78xx0/Kconfig +++ b/arch/arm/mach-mv78xx0/Kconfig @@ -15,20 +15,6 @@ menuconfig ARCH_MV78XX0 if ARCH_MV78XX0 -config MACH_DB78X00_BP - bool "Marvell DB-78x00-BP Development Board" - depends on UNUSED_BOARD_FILES - help - Say 'Y' here if you want your kernel to support the - Marvell DB-78x00-BP Development Board. - -config MACH_RD78X00_MASA - bool "Marvell RD-78x00-mASA Reference Design" - depends on UNUSED_BOARD_FILES - help - Say 'Y' here if you want your kernel to support the - Marvell RD-78x00-mASA Reference Design. - config MACH_TERASTATION_WXL bool "Buffalo WLX (Terastation Duo) NAS" help diff --git a/arch/arm/mach-mv78xx0/Makefile b/arch/arm/mach-mv78xx0/Makefile index 50aff70065f2..ddee6ae501bb 100644 --- a/arch/arm/mach-mv78xx0/Makefile +++ b/arch/arm/mach-mv78xx0/Makefile @@ -2,6 +2,4 @@ ccflags-y := -I$(srctree)/arch/arm/plat-orion/include obj-y += common.o mpp.o irq.o pcie.o -obj-$(CONFIG_MACH_DB78X00_BP) += db78x00-bp-setup.o -obj-$(CONFIG_MACH_RD78X00_MASA) += rd78x00-masa-setup.o obj-$(CONFIG_MACH_TERASTATION_WXL) += buffalo-wxl-setup.o diff --git a/arch/arm/mach-mv78xx0/db78x00-bp-setup.c b/arch/arm/mach-mv78xx0/db78x00-bp-setup.c deleted file mode 100644 index da633a33a0c1..000000000000 --- a/arch/arm/mach-mv78xx0/db78x00-bp-setup.c +++ /dev/null @@ -1,101 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * arch/arm/mach-mv78xx0/db78x00-bp-setup.c - * - * Marvell DB-78x00-BP Development Board Setup - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "mv78xx0.h" -#include "common.h" - -static struct mv643xx_eth_platform_data db78x00_ge00_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR(8), -}; - -static struct mv643xx_eth_platform_data db78x00_ge01_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR(9), -}; - -static struct mv643xx_eth_platform_data db78x00_ge10_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR(10), -}; - -static struct mv643xx_eth_platform_data db78x00_ge11_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR(11), -}; - -static struct mv_sata_platform_data db78x00_sata_data = { - .n_ports = 2, -}; - -static struct i2c_board_info __initdata db78x00_i2c_rtc = { - I2C_BOARD_INFO("ds1338", 0x68), -}; - - -static void __init db78x00_init(void) -{ - /* - * Basic MV78xx0 setup. Needs to be called early. - */ - mv78xx0_init(); - - /* - * Partition on-chip peripherals between the two CPU cores. - */ - if (mv78xx0_core_index() == 0) { - mv78xx0_ehci0_init(); - mv78xx0_ehci1_init(); - mv78xx0_ehci2_init(); - mv78xx0_ge00_init(&db78x00_ge00_data); - mv78xx0_ge01_init(&db78x00_ge01_data); - mv78xx0_ge10_init(&db78x00_ge10_data); - mv78xx0_ge11_init(&db78x00_ge11_data); - mv78xx0_sata_init(&db78x00_sata_data); - mv78xx0_uart0_init(); - mv78xx0_uart2_init(); - mv78xx0_i2c_init(); - i2c_register_board_info(0, &db78x00_i2c_rtc, 1); - } else { - mv78xx0_uart1_init(); - mv78xx0_uart3_init(); - } -} - -static int __init db78x00_pci_init(void) -{ - if (machine_is_db78x00_bp()) { - /* - * Assign the x16 PCIe slot on the board to CPU core - * #0, and let CPU core #1 have the four x1 slots. - */ - if (mv78xx0_core_index() == 0) - mv78xx0_pcie_init(0, 1); - else - mv78xx0_pcie_init(1, 0); - } - - return 0; -} -subsys_initcall(db78x00_pci_init); - -MACHINE_START(DB78X00_BP, "Marvell DB-78x00-BP Development Board") - /* Maintainer: Lennert Buytenhek */ - .atag_offset = 0x100, - .nr_irqs = MV78XX0_NR_IRQS, - .init_machine = db78x00_init, - .map_io = mv78xx0_map_io, - .init_early = mv78xx0_init_early, - .init_irq = mv78xx0_init_irq, - .init_time = mv78xx0_timer_init, - .restart = mv78xx0_restart, -MACHINE_END diff --git a/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c b/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c deleted file mode 100644 index 80ca8b1a81de..000000000000 --- a/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c +++ /dev/null @@ -1,86 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * arch/arm/mach-mv78x00/rd78x00-masa-setup.c - * - * Marvell RD-78x00-mASA Development Board Setup - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "mv78xx0.h" -#include "common.h" - -static struct mv643xx_eth_platform_data rd78x00_masa_ge00_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR(8), -}; - -static struct mv643xx_eth_platform_data rd78x00_masa_ge01_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR(9), -}; - -static struct mv643xx_eth_platform_data rd78x00_masa_ge10_data = { -}; - -static struct mv643xx_eth_platform_data rd78x00_masa_ge11_data = { -}; - -static struct mv_sata_platform_data rd78x00_masa_sata_data = { - .n_ports = 2, -}; - -static void __init rd78x00_masa_init(void) -{ - /* - * Basic MV78x00 setup. Needs to be called early. - */ - mv78xx0_init(); - - /* - * Partition on-chip peripherals between the two CPU cores. - */ - if (mv78xx0_core_index() == 0) { - mv78xx0_ehci0_init(); - mv78xx0_ehci1_init(); - mv78xx0_ge00_init(&rd78x00_masa_ge00_data); - mv78xx0_ge10_init(&rd78x00_masa_ge10_data); - mv78xx0_sata_init(&rd78x00_masa_sata_data); - mv78xx0_uart0_init(); - mv78xx0_uart2_init(); - } else { - mv78xx0_ehci2_init(); - mv78xx0_ge01_init(&rd78x00_masa_ge01_data); - mv78xx0_ge11_init(&rd78x00_masa_ge11_data); - mv78xx0_uart1_init(); - mv78xx0_uart3_init(); - } -} - -static int __init rd78x00_pci_init(void) -{ - /* - * Assign all PCIe devices to CPU core #0. - */ - if (machine_is_rd78x00_masa() && mv78xx0_core_index() == 0) - mv78xx0_pcie_init(1, 1); - - return 0; -} -subsys_initcall(rd78x00_pci_init); - -MACHINE_START(RD78X00_MASA, "Marvell RD-78x00-MASA Development Board") - /* Maintainer: Lennert Buytenhek */ - .atag_offset = 0x100, - .nr_irqs = MV78XX0_NR_IRQS, - .init_machine = rd78x00_masa_init, - .map_io = mv78xx0_map_io, - .init_early = mv78xx0_init_early, - .init_irq = mv78xx0_init_irq, - .init_time = mv78xx0_timer_init, - .restart = mv78xx0_restart, -MACHINE_END diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig index 0044b2823710..ee449ca032d2 100644 --- a/arch/arm/mach-orion5x/Kconfig +++ b/arch/arm/mach-orion5x/Kconfig @@ -28,22 +28,6 @@ config ARCH_ORION5X_DT Say 'Y' here if you want your kernel to support the Marvell Orion5x using flattened device tree. -config MACH_DB88F5281 - bool "Marvell Orion-2 Development Board" - select I2C_BOARDINFO if I2C - depends on ATAGS && UNUSED_BOARD_FILES - help - Say 'Y' here if you want your kernel to support the - Marvell Orion-2 (88F5281) Development Board - -config MACH_RD88F5182 - bool "Marvell Orion-NAS Reference Design" - select I2C_BOARDINFO if I2C - depends on ATAGS && UNUSED_BOARD_FILES - help - Say 'Y' here if you want your kernel to support the - Marvell Orion-NAS (88F5182) RD2 - config MACH_RD88F5182_DT bool "Marvell Orion-NAS Reference Design (Flattened Device Tree)" select ARCH_ORION5X_DT @@ -98,14 +82,6 @@ config MACH_LINKSTATION_MINI Say 'Y' here if you want your kernel to support the Buffalo Linkstation Mini (LS-WSGL) platform. -config MACH_LINKSTATION_LS_HGL - bool "Buffalo Linkstation LS-HGL" - depends on ATAGS && UNUSED_BOARD_FILES - select I2C_BOARDINFO if I2C - help - Say 'Y' here if you want your kernel to support the - Buffalo Linkstation LS-HGL platform. - config MACH_TS409 bool "QNAP TS-409" depends on ATAGS @@ -113,13 +89,6 @@ config MACH_TS409 Say 'Y' here if you want your kernel to support the QNAP TS-409 platform. -config MACH_WRT350N_V2 - bool "Linksys WRT350N v2" - depends on ATAGS && UNUSED_BOARD_FILES - help - Say 'Y' here if you want your kernel to support the - Linksys WRT350N v2 platform. - config MACH_TS78XX bool "Technologic Systems TS-78xx" depends on ATAGS @@ -156,32 +125,4 @@ config MACH_MSS2_DT Say 'Y' here if you want your kernel to support the Maxtor Shared Storage II platform. -config MACH_WNR854T - bool "Netgear WNR854T" - depends on ATAGS && UNUSED_BOARD_FILES - help - Say 'Y' here if you want your kernel to support the - Netgear WNR854T platform. - -config MACH_RD88F5181L_GE - bool "Marvell Orion-VoIP GE Reference Design" - depends on ATAGS && UNUSED_BOARD_FILES - help - Say 'Y' here if you want your kernel to support the - Marvell Orion-VoIP GE (88F5181L) RD. - -config MACH_RD88F5181L_FXO - bool "Marvell Orion-VoIP FXO Reference Design" - depends on ATAGS && UNUSED_BOARD_FILES - help - Say 'Y' here if you want your kernel to support the - Marvell Orion-VoIP FXO (88F5181L) RD. - -config MACH_RD88F6183AP_GE - bool "Marvell Orion-1-90 AP GE Reference Design" - depends on ATAGS && UNUSED_BOARD_FILES - help - Say 'Y' here if you want your kernel to support the - Marvell Orion-1-90 (88F6183) AP GE RD. - endif diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile index 572c3520f7fe..6f54d7fef27a 100644 --- a/arch/arm/mach-orion5x/Makefile +++ b/arch/arm/mach-orion5x/Makefile @@ -2,23 +2,15 @@ ccflags-y := -I$(srctree)/arch/arm/plat-orion/include obj-y += common.o pci.o irq.o mpp.o -obj-$(CONFIG_MACH_DB88F5281) += db88f5281-setup.o -obj-$(CONFIG_MACH_RD88F5182) += rd88f5182-setup.o obj-$(CONFIG_MACH_KUROBOX_PRO) += kurobox_pro-setup.o obj-$(CONFIG_MACH_TERASTATION_PRO2) += terastation_pro2-setup.o obj-$(CONFIG_MACH_LINKSTATION_PRO) += kurobox_pro-setup.o -obj-$(CONFIG_MACH_LINKSTATION_LS_HGL) += ls_hgl-setup.o obj-$(CONFIG_MACH_DNS323) += dns323-setup.o obj-$(CONFIG_MACH_TS209) += ts209-setup.o tsx09-common.o obj-$(CONFIG_MACH_TS409) += ts409-setup.o tsx09-common.o -obj-$(CONFIG_MACH_WRT350N_V2) += wrt350n-v2-setup.o obj-$(CONFIG_MACH_TS78XX) += ts78xx-setup.o obj-$(CONFIG_MACH_MV2120) += mv2120-setup.o obj-$(CONFIG_MACH_NET2BIG) += net2big-setup.o -obj-$(CONFIG_MACH_WNR854T) += wnr854t-setup.o -obj-$(CONFIG_MACH_RD88F5181L_GE) += rd88f5181l-ge-setup.o -obj-$(CONFIG_MACH_RD88F5181L_FXO) += rd88f5181l-fxo-setup.o -obj-$(CONFIG_MACH_RD88F6183AP_GE) += rd88f6183ap-ge-setup.o obj-$(CONFIG_ARCH_ORION5X_DT) += board-dt.o obj-$(CONFIG_MACH_D2NET_DT) += board-d2net.o diff --git a/arch/arm/mach-orion5x/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c deleted file mode 100644 index fe1a4cef1ba2..000000000000 --- a/arch/arm/mach-orion5x/db88f5281-setup.c +++ /dev/null @@ -1,376 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * arch/arm/mach-orion5x/db88f5281-setup.c - * - * Marvell Orion-2 Development Board Setup - * - * Maintainer: Tzachi Perelstein - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "common.h" -#include "mpp.h" -#include "orion5x.h" - -/***************************************************************************** - * DB-88F5281 on board devices - ****************************************************************************/ - -/* - * 512K NOR flash Device bus boot chip select - */ - -#define DB88F5281_NOR_BOOT_BASE 0xf4000000 -#define DB88F5281_NOR_BOOT_SIZE SZ_512K - -/* - * 7-Segment on Device bus chip select 0 - */ - -#define DB88F5281_7SEG_BASE 0xfa000000 -#define DB88F5281_7SEG_SIZE SZ_1K - -/* - * 32M NOR flash on Device bus chip select 1 - */ - -#define DB88F5281_NOR_BASE 0xfc000000 -#define DB88F5281_NOR_SIZE SZ_32M - -/* - * 32M NAND flash on Device bus chip select 2 - */ - -#define DB88F5281_NAND_BASE 0xfa800000 -#define DB88F5281_NAND_SIZE SZ_1K - -/* - * PCI - */ - -#define DB88F5281_PCI_SLOT0_OFFS 7 -#define DB88F5281_PCI_SLOT0_IRQ_PIN 12 -#define DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN 13 - -/***************************************************************************** - * 512M NOR Flash on Device bus Boot CS - ****************************************************************************/ - -static struct physmap_flash_data db88f5281_boot_flash_data = { - .width = 1, /* 8 bit bus width */ -}; - -static struct resource db88f5281_boot_flash_resource = { - .flags = IORESOURCE_MEM, - .start = DB88F5281_NOR_BOOT_BASE, - .end = DB88F5281_NOR_BOOT_BASE + DB88F5281_NOR_BOOT_SIZE - 1, -}; - -static struct platform_device db88f5281_boot_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &db88f5281_boot_flash_data, - }, - .num_resources = 1, - .resource = &db88f5281_boot_flash_resource, -}; - -/***************************************************************************** - * 32M NOR Flash on Device bus CS1 - ****************************************************************************/ - -static struct physmap_flash_data db88f5281_nor_flash_data = { - .width = 4, /* 32 bit bus width */ -}; - -static struct resource db88f5281_nor_flash_resource = { - .flags = IORESOURCE_MEM, - .start = DB88F5281_NOR_BASE, - .end = DB88F5281_NOR_BASE + DB88F5281_NOR_SIZE - 1, -}; - -static struct platform_device db88f5281_nor_flash = { - .name = "physmap-flash", - .id = 1, - .dev = { - .platform_data = &db88f5281_nor_flash_data, - }, - .num_resources = 1, - .resource = &db88f5281_nor_flash_resource, -}; - -/***************************************************************************** - * 32M NAND Flash on Device bus CS2 - ****************************************************************************/ - -static struct mtd_partition db88f5281_nand_parts[] = { - { - .name = "kernel", - .offset = 0, - .size = SZ_2M, - }, { - .name = "root", - .offset = SZ_2M, - .size = (SZ_16M - SZ_2M), - }, { - .name = "user", - .offset = SZ_16M, - .size = SZ_8M, - }, { - .name = "recovery", - .offset = (SZ_16M + SZ_8M), - .size = SZ_8M, - }, -}; - -static struct resource db88f5281_nand_resource = { - .flags = IORESOURCE_MEM, - .start = DB88F5281_NAND_BASE, - .end = DB88F5281_NAND_BASE + DB88F5281_NAND_SIZE - 1, -}; - -static struct orion_nand_data db88f5281_nand_data = { - .parts = db88f5281_nand_parts, - .nr_parts = ARRAY_SIZE(db88f5281_nand_parts), - .cle = 0, - .ale = 1, - .width = 8, -}; - -static struct platform_device db88f5281_nand_flash = { - .name = "orion_nand", - .id = -1, - .dev = { - .platform_data = &db88f5281_nand_data, - }, - .resource = &db88f5281_nand_resource, - .num_resources = 1, -}; - -/***************************************************************************** - * 7-Segment on Device bus CS0 - * Dummy counter every 2 sec - ****************************************************************************/ - -static void __iomem *db88f5281_7seg; -static struct timer_list db88f5281_timer; - -static void db88f5281_7seg_event(struct timer_list *unused) -{ - static int count = 0; - writel(0, db88f5281_7seg + (count << 4)); - count = (count + 1) & 7; - mod_timer(&db88f5281_timer, jiffies + 2 * HZ); -} - -static int __init db88f5281_7seg_init(void) -{ - if (machine_is_db88f5281()) { - db88f5281_7seg = ioremap(DB88F5281_7SEG_BASE, - DB88F5281_7SEG_SIZE); - if (!db88f5281_7seg) { - printk(KERN_ERR "Failed to ioremap db88f5281_7seg\n"); - return -EIO; - } - timer_setup(&db88f5281_timer, db88f5281_7seg_event, 0); - mod_timer(&db88f5281_timer, jiffies + 2 * HZ); - } - - return 0; -} - -__initcall(db88f5281_7seg_init); - -/***************************************************************************** - * PCI - ****************************************************************************/ - -static void __init db88f5281_pci_preinit(void) -{ - int pin; - - /* - * Configure PCI GPIO IRQ pins - */ - pin = DB88F5281_PCI_SLOT0_IRQ_PIN; - if (gpio_request(pin, "PCI Int1") == 0) { - if (gpio_direction_input(pin) == 0) { - irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); - } else { - printk(KERN_ERR "db88f5281_pci_preinit failed to " - "set_irq_type pin %d\n", pin); - gpio_free(pin); - } - } else { - printk(KERN_ERR "db88f5281_pci_preinit failed to gpio_request %d\n", pin); - } - - pin = DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN; - if (gpio_request(pin, "PCI Int2") == 0) { - if (gpio_direction_input(pin) == 0) { - irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); - } else { - printk(KERN_ERR "db88f5281_pci_preinit failed " - "to set_irq_type pin %d\n", pin); - gpio_free(pin); - } - } else { - printk(KERN_ERR "db88f5281_pci_preinit failed to gpio_request %d\n", pin); - } -} - -static int __init db88f5281_pci_map_irq(const struct pci_dev *dev, u8 slot, - u8 pin) -{ - int irq; - - /* - * Check for devices with hard-wired IRQs. - */ - irq = orion5x_pci_map_irq(dev, slot, pin); - if (irq != -1) - return irq; - - /* - * PCI IRQs are connected via GPIOs. - */ - switch (slot - DB88F5281_PCI_SLOT0_OFFS) { - case 0: - return gpio_to_irq(DB88F5281_PCI_SLOT0_IRQ_PIN); - case 1: - case 2: - return gpio_to_irq(DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN); - default: - return -1; - } -} - -static struct hw_pci db88f5281_pci __initdata = { - .nr_controllers = 2, - .preinit = db88f5281_pci_preinit, - .setup = orion5x_pci_sys_setup, - .scan = orion5x_pci_sys_scan_bus, - .map_irq = db88f5281_pci_map_irq, -}; - -static int __init db88f5281_pci_init(void) -{ - if (machine_is_db88f5281()) - pci_common_init(&db88f5281_pci); - - return 0; -} - -subsys_initcall(db88f5281_pci_init); - -/***************************************************************************** - * Ethernet - ****************************************************************************/ -static struct mv643xx_eth_platform_data db88f5281_eth_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR(8), -}; - -/***************************************************************************** - * RTC DS1339 on I2C bus - ****************************************************************************/ -static struct i2c_board_info __initdata db88f5281_i2c_rtc = { - I2C_BOARD_INFO("ds1339", 0x68), -}; - -/***************************************************************************** - * General Setup - ****************************************************************************/ -static unsigned int db88f5281_mpp_modes[] __initdata = { - MPP0_GPIO, /* USB Over Current */ - MPP1_GPIO, /* USB Vbat input */ - MPP2_PCI_ARB, /* PCI_REQn[2] */ - MPP3_PCI_ARB, /* PCI_GNTn[2] */ - MPP4_PCI_ARB, /* PCI_REQn[3] */ - MPP5_PCI_ARB, /* PCI_GNTn[3] */ - MPP6_GPIO, /* JP0, CON17.2 */ - MPP7_GPIO, /* JP1, CON17.1 */ - MPP8_GPIO, /* JP2, CON11.2 */ - MPP9_GPIO, /* JP3, CON11.3 */ - MPP10_GPIO, /* RTC int */ - MPP11_GPIO, /* Baud Rate Generator */ - MPP12_GPIO, /* PCI int 1 */ - MPP13_GPIO, /* PCI int 2 */ - MPP14_NAND, /* NAND_REn[2] */ - MPP15_NAND, /* NAND_WEn[2] */ - MPP16_UART, /* UART1_RX */ - MPP17_UART, /* UART1_TX */ - MPP18_UART, /* UART1_CTSn */ - MPP19_UART, /* UART1_RTSn */ - 0, -}; - -static void __init db88f5281_init(void) -{ - /* - * Basic Orion setup. Need to be called early. - */ - orion5x_init(); - - orion5x_mpp_conf(db88f5281_mpp_modes); - writel(0, MPP_DEV_CTRL); /* DEV_D[31:16] */ - - /* - * Configure peripherals. - */ - orion5x_ehci0_init(); - orion5x_eth_init(&db88f5281_eth_data); - orion5x_i2c_init(); - orion5x_uart0_init(); - orion5x_uart1_init(); - - mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, - ORION_MBUS_DEVBUS_BOOT_ATTR, - DB88F5281_NOR_BOOT_BASE, - DB88F5281_NOR_BOOT_SIZE); - platform_device_register(&db88f5281_boot_flash); - - mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(0), - ORION_MBUS_DEVBUS_ATTR(0), - DB88F5281_7SEG_BASE, - DB88F5281_7SEG_SIZE); - - mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(1), - ORION_MBUS_DEVBUS_ATTR(1), - DB88F5281_NOR_BASE, - DB88F5281_NOR_SIZE); - platform_device_register(&db88f5281_nor_flash); - - mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(2), - ORION_MBUS_DEVBUS_ATTR(2), - DB88F5281_NAND_BASE, - DB88F5281_NAND_SIZE); - platform_device_register(&db88f5281_nand_flash); - - i2c_register_board_info(0, &db88f5281_i2c_rtc, 1); -} - -MACHINE_START(DB88F5281, "Marvell Orion-2 Development Board") - /* Maintainer: Tzachi Perelstein */ - .atag_offset = 0x100, - .nr_irqs = ORION5X_NR_IRQS, - .init_machine = db88f5281_init, - .map_io = orion5x_map_io, - .init_early = orion5x_init_early, - .init_irq = orion5x_init_irq, - .init_time = orion5x_timer_init, - .restart = orion5x_restart, -MACHINE_END diff --git a/arch/arm/mach-orion5x/ls_hgl-setup.c b/arch/arm/mach-orion5x/ls_hgl-setup.c deleted file mode 100644 index af07f617465f..000000000000 --- a/arch/arm/mach-orion5x/ls_hgl-setup.c +++ /dev/null @@ -1,275 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * arch/arm/mach-orion5x/ls_hgl-setup.c - * - * Maintainer: Zhu Qingsen - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "common.h" -#include "mpp.h" -#include "orion5x.h" - -/***************************************************************************** - * Linkstation LS-HGL Info - ****************************************************************************/ - -/* - * 256K NOR flash Device bus boot chip select - */ - -#define LS_HGL_NOR_BOOT_BASE 0xf4000000 -#define LS_HGL_NOR_BOOT_SIZE SZ_256K - -/***************************************************************************** - * 256KB NOR Flash on BOOT Device - ****************************************************************************/ - -static struct physmap_flash_data ls_hgl_nor_flash_data = { - .width = 1, -}; - -static struct resource ls_hgl_nor_flash_resource = { - .flags = IORESOURCE_MEM, - .start = LS_HGL_NOR_BOOT_BASE, - .end = LS_HGL_NOR_BOOT_BASE + LS_HGL_NOR_BOOT_SIZE - 1, -}; - -static struct platform_device ls_hgl_nor_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &ls_hgl_nor_flash_data, - }, - .num_resources = 1, - .resource = &ls_hgl_nor_flash_resource, -}; - -/***************************************************************************** - * Ethernet - ****************************************************************************/ - -static struct mv643xx_eth_platform_data ls_hgl_eth_data = { - .phy_addr = 8, -}; - -/***************************************************************************** - * RTC 5C372a on I2C bus - ****************************************************************************/ - -static struct i2c_board_info __initdata ls_hgl_i2c_rtc = { - I2C_BOARD_INFO("rs5c372a", 0x32), -}; - -/***************************************************************************** - * LEDs attached to GPIO - ****************************************************************************/ - -#define LS_HGL_GPIO_LED_ALARM 2 -#define LS_HGL_GPIO_LED_INFO 3 -#define LS_HGL_GPIO_LED_FUNC 17 -#define LS_HGL_GPIO_LED_PWR 0 - - -static struct gpio_led ls_hgl_led_pins[] = { - { - .name = "alarm:red", - .gpio = LS_HGL_GPIO_LED_ALARM, - .active_low = 1, - }, { - .name = "info:amber", - .gpio = LS_HGL_GPIO_LED_INFO, - .active_low = 1, - }, { - .name = "func:blue:top", - .gpio = LS_HGL_GPIO_LED_FUNC, - .active_low = 1, - }, { - .name = "power:blue:bottom", - .gpio = LS_HGL_GPIO_LED_PWR, - }, -}; - -static struct gpio_led_platform_data ls_hgl_led_data = { - .leds = ls_hgl_led_pins, - .num_leds = ARRAY_SIZE(ls_hgl_led_pins), -}; - -static struct platform_device ls_hgl_leds = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &ls_hgl_led_data, - }, -}; - -/**************************************************************************** - * GPIO Attached Keys - ****************************************************************************/ -#define LS_HGL_GPIO_KEY_FUNC 15 -#define LS_HGL_GPIO_KEY_POWER 8 -#define LS_HGL_GPIO_KEY_AUTOPOWER 10 - -#define LS_HGL_SW_POWER 0x00 -#define LS_HGL_SW_AUTOPOWER 0x01 - -static struct gpio_keys_button ls_hgl_buttons[] = { - { - .code = KEY_OPTION, - .gpio = LS_HGL_GPIO_KEY_FUNC, - .desc = "Function Button", - .active_low = 1, - }, { - .type = EV_SW, - .code = LS_HGL_SW_POWER, - .gpio = LS_HGL_GPIO_KEY_POWER, - .desc = "Power-on Switch", - .active_low = 1, - }, { - .type = EV_SW, - .code = LS_HGL_SW_AUTOPOWER, - .gpio = LS_HGL_GPIO_KEY_AUTOPOWER, - .desc = "Power-auto Switch", - .active_low = 1, - }, -}; - -static struct gpio_keys_platform_data ls_hgl_button_data = { - .buttons = ls_hgl_buttons, - .nbuttons = ARRAY_SIZE(ls_hgl_buttons), -}; - -static struct platform_device ls_hgl_button_device = { - .name = "gpio-keys", - .id = -1, - .num_resources = 0, - .dev = { - .platform_data = &ls_hgl_button_data, - }, -}; - - -/***************************************************************************** - * SATA - ****************************************************************************/ -static struct mv_sata_platform_data ls_hgl_sata_data = { - .n_ports = 2, -}; - - -/***************************************************************************** - * Linkstation LS-HGL specific power off method: reboot - ****************************************************************************/ -/* - * On the Linkstation LS-HGL, the shutdown process is following: - * - Userland monitors key events until the power switch goes to off position - * - The board reboots - * - U-boot starts and goes into an idle mode waiting for the user - * to move the switch to ON position - */ - -static void ls_hgl_power_off(void) -{ - orion5x_restart(REBOOT_HARD, NULL); -} - - -/***************************************************************************** - * General Setup - ****************************************************************************/ - -#define LS_HGL_GPIO_USB_POWER 9 -#define LS_HGL_GPIO_AUTO_POWER 10 -#define LS_HGL_GPIO_POWER 8 - -#define LS_HGL_GPIO_HDD_POWER 1 - -static unsigned int ls_hgl_mpp_modes[] __initdata = { - MPP0_GPIO, /* LED_PWR */ - MPP1_GPIO, /* HDD_PWR */ - MPP2_GPIO, /* LED_ALARM */ - MPP3_GPIO, /* LED_INFO */ - MPP4_UNUSED, - MPP5_UNUSED, - MPP6_GPIO, /* FAN_LCK */ - MPP7_GPIO, /* INIT */ - MPP8_GPIO, /* POWER */ - MPP9_GPIO, /* USB_PWR */ - MPP10_GPIO, /* AUTO_POWER */ - MPP11_UNUSED, /* LED_ETH (dummy) */ - MPP12_UNUSED, - MPP13_UNUSED, - MPP14_UNUSED, - MPP15_GPIO, /* FUNC */ - MPP16_UNUSED, - MPP17_GPIO, /* LED_FUNC */ - MPP18_UNUSED, - MPP19_UNUSED, - 0, -}; - -static void __init ls_hgl_init(void) -{ - /* - * Setup basic Orion functions. Need to be called early. - */ - orion5x_init(); - - orion5x_mpp_conf(ls_hgl_mpp_modes); - - /* - * Configure peripherals. - */ - orion5x_ehci0_init(); - orion5x_ehci1_init(); - orion5x_eth_init(&ls_hgl_eth_data); - orion5x_i2c_init(); - orion5x_sata_init(&ls_hgl_sata_data); - orion5x_uart0_init(); - orion5x_xor_init(); - - mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, - ORION_MBUS_DEVBUS_BOOT_ATTR, - LS_HGL_NOR_BOOT_BASE, - LS_HGL_NOR_BOOT_SIZE); - platform_device_register(&ls_hgl_nor_flash); - - platform_device_register(&ls_hgl_button_device); - - platform_device_register(&ls_hgl_leds); - - i2c_register_board_info(0, &ls_hgl_i2c_rtc, 1); - - /* enable USB power */ - gpio_set_value(LS_HGL_GPIO_USB_POWER, 1); - - /* register power-off method */ - pm_power_off = ls_hgl_power_off; - - pr_info("%s: finished\n", __func__); -} - -MACHINE_START(LINKSTATION_LS_HGL, "Buffalo Linkstation LS-HGL") - /* Maintainer: Zhu Qingsen */ - .atag_offset = 0x100, - .nr_irqs = ORION5X_NR_IRQS, - .init_machine = ls_hgl_init, - .map_io = orion5x_map_io, - .init_early = orion5x_init_early, - .init_irq = orion5x_init_irq, - .init_time = orion5x_timer_init, - .fixup = tag_fixup_mem32, - .restart = orion5x_restart, -MACHINE_END diff --git a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c deleted file mode 100644 index 432fc8357d9e..000000000000 --- a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c +++ /dev/null @@ -1,172 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c - * - * Marvell Orion-VoIP FXO Reference Design Setup - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "common.h" -#include "mpp.h" -#include "orion5x.h" - -/***************************************************************************** - * RD-88F5181L FXO Info - ****************************************************************************/ -/* - * 8M NOR flash Device bus boot chip select - */ -#define RD88F5181L_FXO_NOR_BOOT_BASE 0xff800000 -#define RD88F5181L_FXO_NOR_BOOT_SIZE SZ_8M - - -/***************************************************************************** - * 8M NOR Flash on Device bus Boot chip select - ****************************************************************************/ -static struct physmap_flash_data rd88f5181l_fxo_nor_boot_flash_data = { - .width = 1, -}; - -static struct resource rd88f5181l_fxo_nor_boot_flash_resource = { - .flags = IORESOURCE_MEM, - .start = RD88F5181L_FXO_NOR_BOOT_BASE, - .end = RD88F5181L_FXO_NOR_BOOT_BASE + - RD88F5181L_FXO_NOR_BOOT_SIZE - 1, -}; - -static struct platform_device rd88f5181l_fxo_nor_boot_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &rd88f5181l_fxo_nor_boot_flash_data, - }, - .num_resources = 1, - .resource = &rd88f5181l_fxo_nor_boot_flash_resource, -}; - - -/***************************************************************************** - * General Setup - ****************************************************************************/ -static unsigned int rd88f5181l_fxo_mpp_modes[] __initdata = { - MPP0_GPIO, /* LED1 CardBus LED (front panel) */ - MPP1_GPIO, /* PCI_intA */ - MPP2_GPIO, /* Hard Reset / Factory Init*/ - MPP3_GPIO, /* FXS or DAA select */ - MPP4_GPIO, /* LED6 - phone LED (front panel) */ - MPP5_GPIO, /* LED5 - phone LED (front panel) */ - MPP6_PCI_CLK, /* CPU PCI refclk */ - MPP7_PCI_CLK, /* PCI/PCIe refclk */ - MPP8_GPIO, /* CardBus reset */ - MPP9_GPIO, /* GE_RXERR */ - MPP10_GPIO, /* LED2 MiniPCI LED (front panel) */ - MPP11_GPIO, /* Lifeline control */ - MPP12_GIGE, /* GE_TXD[4] */ - MPP13_GIGE, /* GE_TXD[5] */ - MPP14_GIGE, /* GE_TXD[6] */ - MPP15_GIGE, /* GE_TXD[7] */ - MPP16_GIGE, /* GE_RXD[4] */ - MPP17_GIGE, /* GE_RXD[5] */ - MPP18_GIGE, /* GE_RXD[6] */ - MPP19_GIGE, /* GE_RXD[7] */ - 0, -}; - -static struct mv643xx_eth_platform_data rd88f5181l_fxo_eth_data = { - .phy_addr = MV643XX_ETH_PHY_NONE, - .speed = SPEED_1000, - .duplex = DUPLEX_FULL, -}; - -static struct dsa_chip_data rd88f5181l_fxo_switch_chip_data = { - .port_names[0] = "lan2", - .port_names[1] = "lan1", - .port_names[2] = "wan", - .port_names[3] = "cpu", - .port_names[5] = "lan4", - .port_names[7] = "lan3", -}; - -static void __init rd88f5181l_fxo_init(void) -{ - /* - * Setup basic Orion functions. Need to be called early. - */ - orion5x_init(); - - orion5x_mpp_conf(rd88f5181l_fxo_mpp_modes); - - /* - * Configure peripherals. - */ - orion5x_ehci0_init(); - orion5x_eth_init(&rd88f5181l_fxo_eth_data); - orion5x_eth_switch_init(&rd88f5181l_fxo_switch_chip_data); - orion5x_uart0_init(); - - mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, - ORION_MBUS_DEVBUS_BOOT_ATTR, - RD88F5181L_FXO_NOR_BOOT_BASE, - RD88F5181L_FXO_NOR_BOOT_SIZE); - platform_device_register(&rd88f5181l_fxo_nor_boot_flash); -} - -static int __init -rd88f5181l_fxo_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - int irq; - - /* - * Check for devices with hard-wired IRQs. - */ - irq = orion5x_pci_map_irq(dev, slot, pin); - if (irq != -1) - return irq; - - /* - * Mini-PCI / Cardbus slot. - */ - return gpio_to_irq(1); -} - -static struct hw_pci rd88f5181l_fxo_pci __initdata = { - .nr_controllers = 2, - .setup = orion5x_pci_sys_setup, - .scan = orion5x_pci_sys_scan_bus, - .map_irq = rd88f5181l_fxo_pci_map_irq, -}; - -static int __init rd88f5181l_fxo_pci_init(void) -{ - if (machine_is_rd88f5181l_fxo()) { - orion5x_pci_set_cardbus_mode(); - pci_common_init(&rd88f5181l_fxo_pci); - } - - return 0; -} -subsys_initcall(rd88f5181l_fxo_pci_init); - -MACHINE_START(RD88F5181L_FXO, "Marvell Orion-VoIP FXO Reference Design") - /* Maintainer: Nicolas Pitre */ - .atag_offset = 0x100, - .nr_irqs = ORION5X_NR_IRQS, - .init_machine = rd88f5181l_fxo_init, - .map_io = orion5x_map_io, - .init_early = orion5x_init_early, - .init_irq = orion5x_init_irq, - .init_time = orion5x_timer_init, - .fixup = tag_fixup_mem32, - .restart = orion5x_restart, -MACHINE_END diff --git a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c deleted file mode 100644 index d4b1a9c3cd36..000000000000 --- a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c +++ /dev/null @@ -1,183 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * arch/arm/mach-orion5x/rd88f5181l-ge-setup.c - * - * Marvell Orion-VoIP GE Reference Design Setup - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "common.h" -#include "mpp.h" -#include "orion5x.h" - -/***************************************************************************** - * RD-88F5181L GE Info - ****************************************************************************/ -/* - * 16M NOR flash Device bus boot chip select - */ -#define RD88F5181L_GE_NOR_BOOT_BASE 0xff000000 -#define RD88F5181L_GE_NOR_BOOT_SIZE SZ_16M - - -/***************************************************************************** - * 16M NOR Flash on Device bus Boot chip select - ****************************************************************************/ -static struct physmap_flash_data rd88f5181l_ge_nor_boot_flash_data = { - .width = 1, -}; - -static struct resource rd88f5181l_ge_nor_boot_flash_resource = { - .flags = IORESOURCE_MEM, - .start = RD88F5181L_GE_NOR_BOOT_BASE, - .end = RD88F5181L_GE_NOR_BOOT_BASE + - RD88F5181L_GE_NOR_BOOT_SIZE - 1, -}; - -static struct platform_device rd88f5181l_ge_nor_boot_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &rd88f5181l_ge_nor_boot_flash_data, - }, - .num_resources = 1, - .resource = &rd88f5181l_ge_nor_boot_flash_resource, -}; - - -/***************************************************************************** - * General Setup - ****************************************************************************/ -static unsigned int rd88f5181l_ge_mpp_modes[] __initdata = { - MPP0_GPIO, /* LED1 */ - MPP1_GPIO, /* LED5 */ - MPP2_GPIO, /* LED4 */ - MPP3_GPIO, /* LED3 */ - MPP4_GPIO, /* PCI_intA */ - MPP5_GPIO, /* RTC interrupt */ - MPP6_PCI_CLK, /* CPU PCI refclk */ - MPP7_PCI_CLK, /* PCI/PCIe refclk */ - MPP8_GPIO, /* 88e6131 interrupt */ - MPP9_GPIO, /* GE_RXERR */ - MPP10_GPIO, /* PCI_intB */ - MPP11_GPIO, /* LED2 */ - MPP12_GIGE, /* GE_TXD[4] */ - MPP13_GIGE, /* GE_TXD[5] */ - MPP14_GIGE, /* GE_TXD[6] */ - MPP15_GIGE, /* GE_TXD[7] */ - MPP16_GIGE, /* GE_RXD[4] */ - MPP17_GIGE, /* GE_RXD[5] */ - MPP18_GIGE, /* GE_RXD[6] */ - MPP19_GIGE, /* GE_RXD[7] */ - 0, -}; - -static struct mv643xx_eth_platform_data rd88f5181l_ge_eth_data = { - .phy_addr = MV643XX_ETH_PHY_NONE, - .speed = SPEED_1000, - .duplex = DUPLEX_FULL, -}; - -static struct dsa_chip_data rd88f5181l_ge_switch_chip_data = { - .port_names[0] = "lan2", - .port_names[1] = "lan1", - .port_names[2] = "wan", - .port_names[3] = "cpu", - .port_names[5] = "lan4", - .port_names[7] = "lan3", -}; - -static struct i2c_board_info __initdata rd88f5181l_ge_i2c_rtc = { - I2C_BOARD_INFO("ds1338", 0x68), -}; - -static void __init rd88f5181l_ge_init(void) -{ - /* - * Setup basic Orion functions. Need to be called early. - */ - orion5x_init(); - - orion5x_mpp_conf(rd88f5181l_ge_mpp_modes); - - /* - * Configure peripherals. - */ - orion5x_ehci0_init(); - orion5x_eth_init(&rd88f5181l_ge_eth_data); - orion5x_eth_switch_init(&rd88f5181l_ge_switch_chip_data); - orion5x_i2c_init(); - orion5x_uart0_init(); - - mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, - ORION_MBUS_DEVBUS_BOOT_ATTR, - RD88F5181L_GE_NOR_BOOT_BASE, - RD88F5181L_GE_NOR_BOOT_SIZE); - platform_device_register(&rd88f5181l_ge_nor_boot_flash); - - i2c_register_board_info(0, &rd88f5181l_ge_i2c_rtc, 1); -} - -static int __init -rd88f5181l_ge_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - int irq; - - /* - * Check for devices with hard-wired IRQs. - */ - irq = orion5x_pci_map_irq(dev, slot, pin); - if (irq != -1) - return irq; - - /* - * Cardbus slot. - */ - if (pin == 1) - return gpio_to_irq(4); - else - return gpio_to_irq(10); -} - -static struct hw_pci rd88f5181l_ge_pci __initdata = { - .nr_controllers = 2, - .setup = orion5x_pci_sys_setup, - .scan = orion5x_pci_sys_scan_bus, - .map_irq = rd88f5181l_ge_pci_map_irq, -}; - -static int __init rd88f5181l_ge_pci_init(void) -{ - if (machine_is_rd88f5181l_ge()) { - orion5x_pci_set_cardbus_mode(); - pci_common_init(&rd88f5181l_ge_pci); - } - - return 0; -} -subsys_initcall(rd88f5181l_ge_pci_init); - -MACHINE_START(RD88F5181L_GE, "Marvell Orion-VoIP GE Reference Design") - /* Maintainer: Lennert Buytenhek */ - .atag_offset = 0x100, - .nr_irqs = ORION5X_NR_IRQS, - .init_machine = rd88f5181l_ge_init, - .map_io = orion5x_map_io, - .init_early = orion5x_init_early, - .init_irq = orion5x_init_irq, - .init_time = orion5x_timer_init, - .fixup = tag_fixup_mem32, - .restart = orion5x_restart, -MACHINE_END diff --git a/arch/arm/mach-orion5x/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c deleted file mode 100644 index 6ffcfc6445e2..000000000000 --- a/arch/arm/mach-orion5x/rd88f5182-setup.c +++ /dev/null @@ -1,288 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * arch/arm/mach-orion5x/rd88f5182-setup.c - * - * Marvell Orion-NAS Reference Design Setup - * - * Maintainer: Ronen Shitrit - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "common.h" -#include "mpp.h" -#include "orion5x.h" - -/***************************************************************************** - * RD-88F5182 Info - ****************************************************************************/ - -/* - * 512K NOR flash Device bus boot chip select - */ - -#define RD88F5182_NOR_BOOT_BASE 0xf4000000 -#define RD88F5182_NOR_BOOT_SIZE SZ_512K - -/* - * 16M NOR flash on Device bus chip select 1 - */ - -#define RD88F5182_NOR_BASE 0xfc000000 -#define RD88F5182_NOR_SIZE SZ_16M - -/* - * PCI - */ - -#define RD88F5182_PCI_SLOT0_OFFS 7 -#define RD88F5182_PCI_SLOT0_IRQ_A_PIN 7 -#define RD88F5182_PCI_SLOT0_IRQ_B_PIN 6 - -/***************************************************************************** - * 16M NOR Flash on Device bus CS1 - ****************************************************************************/ - -static struct physmap_flash_data rd88f5182_nor_flash_data = { - .width = 1, -}; - -static struct resource rd88f5182_nor_flash_resource = { - .flags = IORESOURCE_MEM, - .start = RD88F5182_NOR_BASE, - .end = RD88F5182_NOR_BASE + RD88F5182_NOR_SIZE - 1, -}; - -static struct platform_device rd88f5182_nor_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &rd88f5182_nor_flash_data, - }, - .num_resources = 1, - .resource = &rd88f5182_nor_flash_resource, -}; - -/***************************************************************************** - * Use GPIO LED as CPU active indication - ****************************************************************************/ - -#define RD88F5182_GPIO_LED 0 - -static struct gpio_led rd88f5182_gpio_led_pins[] = { - { - .name = "rd88f5182:cpu", - .default_trigger = "cpu0", - .gpio = RD88F5182_GPIO_LED, - }, -}; - -static struct gpio_led_platform_data rd88f5182_gpio_led_data = { - .leds = rd88f5182_gpio_led_pins, - .num_leds = ARRAY_SIZE(rd88f5182_gpio_led_pins), -}; - -static struct platform_device rd88f5182_gpio_leds = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &rd88f5182_gpio_led_data, - }, -}; - -/***************************************************************************** - * PCI - ****************************************************************************/ - -static void __init rd88f5182_pci_preinit(void) -{ - int pin; - - /* - * Configure PCI GPIO IRQ pins - */ - pin = RD88F5182_PCI_SLOT0_IRQ_A_PIN; - if (gpio_request(pin, "PCI IntA") == 0) { - if (gpio_direction_input(pin) == 0) { - irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); - } else { - printk(KERN_ERR "rd88f5182_pci_preinit failed to " - "set_irq_type pin %d\n", pin); - gpio_free(pin); - } - } else { - printk(KERN_ERR "rd88f5182_pci_preinit failed to request gpio %d\n", pin); - } - - pin = RD88F5182_PCI_SLOT0_IRQ_B_PIN; - if (gpio_request(pin, "PCI IntB") == 0) { - if (gpio_direction_input(pin) == 0) { - irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); - } else { - printk(KERN_ERR "rd88f5182_pci_preinit failed to " - "set_irq_type pin %d\n", pin); - gpio_free(pin); - } - } else { - printk(KERN_ERR "rd88f5182_pci_preinit failed to gpio_request %d\n", pin); - } -} - -static int __init rd88f5182_pci_map_irq(const struct pci_dev *dev, u8 slot, - u8 pin) -{ - int irq; - - /* - * Check for devices with hard-wired IRQs. - */ - irq = orion5x_pci_map_irq(dev, slot, pin); - if (irq != -1) - return irq; - - /* - * PCI IRQs are connected via GPIOs - */ - switch (slot - RD88F5182_PCI_SLOT0_OFFS) { - case 0: - if (pin == 1) - return gpio_to_irq(RD88F5182_PCI_SLOT0_IRQ_A_PIN); - else - return gpio_to_irq(RD88F5182_PCI_SLOT0_IRQ_B_PIN); - default: - return -1; - } -} - -static struct hw_pci rd88f5182_pci __initdata = { - .nr_controllers = 2, - .preinit = rd88f5182_pci_preinit, - .setup = orion5x_pci_sys_setup, - .scan = orion5x_pci_sys_scan_bus, - .map_irq = rd88f5182_pci_map_irq, -}; - -static int __init rd88f5182_pci_init(void) -{ - if (machine_is_rd88f5182()) - pci_common_init(&rd88f5182_pci); - - return 0; -} - -subsys_initcall(rd88f5182_pci_init); - -/***************************************************************************** - * Ethernet - ****************************************************************************/ - -static struct mv643xx_eth_platform_data rd88f5182_eth_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR(8), -}; - -/***************************************************************************** - * RTC DS1338 on I2C bus - ****************************************************************************/ -static struct i2c_board_info __initdata rd88f5182_i2c_rtc = { - I2C_BOARD_INFO("ds1338", 0x68), -}; - -/***************************************************************************** - * Sata - ****************************************************************************/ -static struct mv_sata_platform_data rd88f5182_sata_data = { - .n_ports = 2, -}; - -/***************************************************************************** - * General Setup - ****************************************************************************/ -static unsigned int rd88f5182_mpp_modes[] __initdata = { - MPP0_GPIO, /* Debug Led */ - MPP1_GPIO, /* Reset Switch */ - MPP2_UNUSED, - MPP3_GPIO, /* RTC Int */ - MPP4_GPIO, - MPP5_GPIO, - MPP6_GPIO, /* PCI_intA */ - MPP7_GPIO, /* PCI_intB */ - MPP8_UNUSED, - MPP9_UNUSED, - MPP10_UNUSED, - MPP11_UNUSED, - MPP12_SATA_LED, /* SATA 0 presence */ - MPP13_SATA_LED, /* SATA 1 presence */ - MPP14_SATA_LED, /* SATA 0 active */ - MPP15_SATA_LED, /* SATA 1 active */ - MPP16_UNUSED, - MPP17_UNUSED, - MPP18_UNUSED, - MPP19_UNUSED, - 0, -}; - -static void __init rd88f5182_init(void) -{ - /* - * Setup basic Orion functions. Need to be called early. - */ - orion5x_init(); - - orion5x_mpp_conf(rd88f5182_mpp_modes); - - /* - * MPP[20] PCI Clock to MV88F5182 - * MPP[21] PCI Clock to mini PCI CON11 - * MPP[22] USB 0 over current indication - * MPP[23] USB 1 over current indication - * MPP[24] USB 1 over current enable - * MPP[25] USB 0 over current enable - */ - - /* - * Configure peripherals. - */ - orion5x_ehci0_init(); - orion5x_ehci1_init(); - orion5x_eth_init(&rd88f5182_eth_data); - orion5x_i2c_init(); - orion5x_sata_init(&rd88f5182_sata_data); - orion5x_uart0_init(); - orion5x_xor_init(); - - mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, - ORION_MBUS_DEVBUS_BOOT_ATTR, - RD88F5182_NOR_BOOT_BASE, - RD88F5182_NOR_BOOT_SIZE); - mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(1), - ORION_MBUS_DEVBUS_ATTR(1), - RD88F5182_NOR_BASE, - RD88F5182_NOR_SIZE); - platform_device_register(&rd88f5182_nor_flash); - platform_device_register(&rd88f5182_gpio_leds); - - i2c_register_board_info(0, &rd88f5182_i2c_rtc, 1); -} - -MACHINE_START(RD88F5182, "Marvell Orion-NAS Reference Design") - /* Maintainer: Ronen Shitrit */ - .atag_offset = 0x100, - .nr_irqs = ORION5X_NR_IRQS, - .init_machine = rd88f5182_init, - .map_io = orion5x_map_io, - .init_early = orion5x_init_early, - .init_irq = orion5x_init_irq, - .init_time = orion5x_timer_init, - .restart = orion5x_restart, -MACHINE_END diff --git a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c deleted file mode 100644 index 93f74fd6b4da..000000000000 --- a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c +++ /dev/null @@ -1,120 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * arch/arm/mach-orion5x/rd88f6183-ap-ge-setup.c - * - * Marvell Orion-1-90 AP GE Reference Design Setup - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "common.h" -#include "orion5x.h" - -static struct mv643xx_eth_platform_data rd88f6183ap_ge_eth_data = { - .phy_addr = -1, - .speed = SPEED_1000, - .duplex = DUPLEX_FULL, -}; - -static struct dsa_chip_data rd88f6183ap_ge_switch_chip_data = { - .port_names[0] = "lan1", - .port_names[1] = "lan2", - .port_names[2] = "lan3", - .port_names[3] = "lan4", - .port_names[4] = "wan", - .port_names[5] = "cpu", -}; - -static struct mtd_partition rd88f6183ap_ge_partitions[] = { - { - .name = "kernel", - .offset = 0x00000000, - .size = 0x00200000, - }, { - .name = "rootfs", - .offset = 0x00200000, - .size = 0x00500000, - }, { - .name = "nvram", - .offset = 0x00700000, - .size = 0x00080000, - }, -}; - -static struct flash_platform_data rd88f6183ap_ge_spi_slave_data = { - .type = "m25p64", - .nr_parts = ARRAY_SIZE(rd88f6183ap_ge_partitions), - .parts = rd88f6183ap_ge_partitions, -}; - -static struct spi_board_info __initdata rd88f6183ap_ge_spi_slave_info[] = { - { - .modalias = "m25p80", - .platform_data = &rd88f6183ap_ge_spi_slave_data, - .max_speed_hz = 20000000, - .bus_num = 0, - .chip_select = 0, - }, -}; - -static void __init rd88f6183ap_ge_init(void) -{ - /* - * Setup basic Orion functions. Need to be called early. - */ - orion5x_init(); - - /* - * Configure peripherals. - */ - orion5x_ehci0_init(); - orion5x_eth_init(&rd88f6183ap_ge_eth_data); - orion5x_eth_switch_init(&rd88f6183ap_ge_switch_chip_data); - spi_register_board_info(rd88f6183ap_ge_spi_slave_info, - ARRAY_SIZE(rd88f6183ap_ge_spi_slave_info)); - orion5x_spi_init(); - orion5x_uart0_init(); -} - -static struct hw_pci rd88f6183ap_ge_pci __initdata = { - .nr_controllers = 2, - .setup = orion5x_pci_sys_setup, - .scan = orion5x_pci_sys_scan_bus, - .map_irq = orion5x_pci_map_irq, -}; - -static int __init rd88f6183ap_ge_pci_init(void) -{ - if (machine_is_rd88f6183ap_ge()) { - orion5x_pci_disable(); - pci_common_init(&rd88f6183ap_ge_pci); - } - - return 0; -} -subsys_initcall(rd88f6183ap_ge_pci_init); - -MACHINE_START(RD88F6183AP_GE, "Marvell Orion-1-90 AP GE Reference Design") - /* Maintainer: Lennert Buytenhek */ - .atag_offset = 0x100, - .nr_irqs = ORION5X_NR_IRQS, - .init_machine = rd88f6183ap_ge_init, - .map_io = orion5x_map_io, - .init_early = orion5x_init_early, - .init_irq = orion5x_init_irq, - .init_time = orion5x_timer_init, - .fixup = tag_fixup_mem32, - .restart = orion5x_restart, -MACHINE_END diff --git a/arch/arm/mach-orion5x/wnr854t-setup.c b/arch/arm/mach-orion5x/wnr854t-setup.c deleted file mode 100644 index e5f327054dd3..000000000000 --- a/arch/arm/mach-orion5x/wnr854t-setup.c +++ /dev/null @@ -1,175 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -// arch/arm/mach-orion5x/wnr854t-setup.c -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "orion5x.h" -#include "common.h" -#include "mpp.h" - -static unsigned int wnr854t_mpp_modes[] __initdata = { - MPP0_GPIO, /* Power LED green (0=on) */ - MPP1_GPIO, /* Reset Button (0=off) */ - MPP2_GPIO, /* Power LED blink (0=off) */ - MPP3_GPIO, /* WAN Status LED amber (0=off) */ - MPP4_GPIO, /* PCI int */ - MPP5_GPIO, /* ??? */ - MPP6_GPIO, /* ??? */ - MPP7_GPIO, /* ??? */ - MPP8_UNUSED, /* ??? */ - MPP9_GIGE, /* GE_RXERR */ - MPP10_UNUSED, /* ??? */ - MPP11_UNUSED, /* ??? */ - MPP12_GIGE, /* GE_TXD[4] */ - MPP13_GIGE, /* GE_TXD[5] */ - MPP14_GIGE, /* GE_TXD[6] */ - MPP15_GIGE, /* GE_TXD[7] */ - MPP16_GIGE, /* GE_RXD[4] */ - MPP17_GIGE, /* GE_RXD[5] */ - MPP18_GIGE, /* GE_RXD[6] */ - MPP19_GIGE, /* GE_RXD[7] */ - 0, -}; - -/* - * 8M NOR flash Device bus boot chip select - */ -#define WNR854T_NOR_BOOT_BASE 0xf4000000 -#define WNR854T_NOR_BOOT_SIZE SZ_8M - -static struct mtd_partition wnr854t_nor_flash_partitions[] = { - { - .name = "kernel", - .offset = 0x00000000, - .size = 0x00100000, - }, { - .name = "rootfs", - .offset = 0x00100000, - .size = 0x00660000, - }, { - .name = "uboot", - .offset = 0x00760000, - .size = 0x00040000, - }, -}; - -static struct physmap_flash_data wnr854t_nor_flash_data = { - .width = 2, - .parts = wnr854t_nor_flash_partitions, - .nr_parts = ARRAY_SIZE(wnr854t_nor_flash_partitions), -}; - -static struct resource wnr854t_nor_flash_resource = { - .flags = IORESOURCE_MEM, - .start = WNR854T_NOR_BOOT_BASE, - .end = WNR854T_NOR_BOOT_BASE + WNR854T_NOR_BOOT_SIZE - 1, -}; - -static struct platform_device wnr854t_nor_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &wnr854t_nor_flash_data, - }, - .num_resources = 1, - .resource = &wnr854t_nor_flash_resource, -}; - -static struct mv643xx_eth_platform_data wnr854t_eth_data = { - .phy_addr = MV643XX_ETH_PHY_NONE, - .speed = SPEED_1000, - .duplex = DUPLEX_FULL, -}; - -static struct dsa_chip_data wnr854t_switch_chip_data = { - .port_names[0] = "lan3", - .port_names[1] = "lan4", - .port_names[2] = "wan", - .port_names[3] = "cpu", - .port_names[5] = "lan1", - .port_names[7] = "lan2", -}; - -static void __init wnr854t_init(void) -{ - /* - * Setup basic Orion functions. Need to be called early. - */ - orion5x_init(); - - orion5x_mpp_conf(wnr854t_mpp_modes); - - /* - * Configure peripherals. - */ - orion5x_eth_init(&wnr854t_eth_data); - orion5x_eth_switch_init(&wnr854t_switch_chip_data); - orion5x_uart0_init(); - - mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, - ORION_MBUS_DEVBUS_BOOT_ATTR, - WNR854T_NOR_BOOT_BASE, - WNR854T_NOR_BOOT_SIZE); - platform_device_register(&wnr854t_nor_flash); -} - -static int __init wnr854t_pci_map_irq(const struct pci_dev *dev, u8 slot, - u8 pin) -{ - int irq; - - /* - * Check for devices with hard-wired IRQs. - */ - irq = orion5x_pci_map_irq(dev, slot, pin); - if (irq != -1) - return irq; - - /* - * Mini-PCI slot. - */ - if (slot == 7) - return gpio_to_irq(4); - - return -1; -} - -static struct hw_pci wnr854t_pci __initdata = { - .nr_controllers = 2, - .setup = orion5x_pci_sys_setup, - .scan = orion5x_pci_sys_scan_bus, - .map_irq = wnr854t_pci_map_irq, -}; - -static int __init wnr854t_pci_init(void) -{ - if (machine_is_wnr854t()) - pci_common_init(&wnr854t_pci); - - return 0; -} -subsys_initcall(wnr854t_pci_init); - -MACHINE_START(WNR854T, "Netgear WNR854T") - /* Maintainer: Imre Kaloz */ - .atag_offset = 0x100, - .nr_irqs = ORION5X_NR_IRQS, - .init_machine = wnr854t_init, - .map_io = orion5x_map_io, - .init_early = orion5x_init_early, - .init_irq = orion5x_init_irq, - .init_time = orion5x_timer_init, - .fixup = tag_fixup_mem32, - .restart = orion5x_restart, -MACHINE_END diff --git a/arch/arm/mach-orion5x/wrt350n-v2-setup.c b/arch/arm/mach-orion5x/wrt350n-v2-setup.c deleted file mode 100644 index e6a2da6662df..000000000000 --- a/arch/arm/mach-orion5x/wrt350n-v2-setup.c +++ /dev/null @@ -1,263 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -// arch/arm/mach-orion5x/wrt350n-v2-setup.c -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "orion5x.h" -#include "common.h" -#include "mpp.h" - -/* - * LEDs attached to GPIO - */ -static struct gpio_led wrt350n_v2_led_pins[] = { - { - .name = "wrt350nv2:green:power", - .gpio = 0, - .active_low = 1, - }, { - .name = "wrt350nv2:green:security", - .gpio = 1, - .active_low = 1, - }, { - .name = "wrt350nv2:orange:power", - .gpio = 5, - .active_low = 1, - }, { - .name = "wrt350nv2:green:usb", - .gpio = 6, - .active_low = 1, - }, { - .name = "wrt350nv2:green:wireless", - .gpio = 7, - .active_low = 1, - }, -}; - -static struct gpio_led_platform_data wrt350n_v2_led_data = { - .leds = wrt350n_v2_led_pins, - .num_leds = ARRAY_SIZE(wrt350n_v2_led_pins), -}; - -static struct platform_device wrt350n_v2_leds = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &wrt350n_v2_led_data, - }, -}; - -/* - * Buttons attached to GPIO - */ -static struct gpio_keys_button wrt350n_v2_buttons[] = { - { - .code = KEY_RESTART, - .gpio = 3, - .desc = "Reset Button", - .active_low = 1, - }, { - .code = KEY_WPS_BUTTON, - .gpio = 2, - .desc = "WPS Button", - .active_low = 1, - }, -}; - -static struct gpio_keys_platform_data wrt350n_v2_button_data = { - .buttons = wrt350n_v2_buttons, - .nbuttons = ARRAY_SIZE(wrt350n_v2_buttons), -}; - -static struct platform_device wrt350n_v2_button_device = { - .name = "gpio-keys", - .id = -1, - .num_resources = 0, - .dev = { - .platform_data = &wrt350n_v2_button_data, - }, -}; - -/* - * General setup - */ -static unsigned int wrt350n_v2_mpp_modes[] __initdata = { - MPP0_GPIO, /* Power LED green (0=on) */ - MPP1_GPIO, /* Security LED (0=on) */ - MPP2_GPIO, /* Internal Button (0=on) */ - MPP3_GPIO, /* Reset Button (0=on) */ - MPP4_GPIO, /* PCI int */ - MPP5_GPIO, /* Power LED orange (0=on) */ - MPP6_GPIO, /* USB LED (0=on) */ - MPP7_GPIO, /* Wireless LED (0=on) */ - MPP8_UNUSED, /* ??? */ - MPP9_GIGE, /* GE_RXERR */ - MPP10_UNUSED, /* ??? */ - MPP11_UNUSED, /* ??? */ - MPP12_GIGE, /* GE_TXD[4] */ - MPP13_GIGE, /* GE_TXD[5] */ - MPP14_GIGE, /* GE_TXD[6] */ - MPP15_GIGE, /* GE_TXD[7] */ - MPP16_GIGE, /* GE_RXD[4] */ - MPP17_GIGE, /* GE_RXD[5] */ - MPP18_GIGE, /* GE_RXD[6] */ - MPP19_GIGE, /* GE_RXD[7] */ - 0, -}; - -/* - * 8M NOR flash Device bus boot chip select - */ -#define WRT350N_V2_NOR_BOOT_BASE 0xf4000000 -#define WRT350N_V2_NOR_BOOT_SIZE SZ_8M - -static struct mtd_partition wrt350n_v2_nor_flash_partitions[] = { - { - .name = "kernel", - .offset = 0x00000000, - .size = 0x00760000, - }, { - .name = "rootfs", - .offset = 0x001a0000, - .size = 0x005c0000, - }, { - .name = "lang", - .offset = 0x00760000, - .size = 0x00040000, - }, { - .name = "nvram", - .offset = 0x007a0000, - .size = 0x00020000, - }, { - .name = "u-boot", - .offset = 0x007c0000, - .size = 0x00040000, - }, -}; - -static struct physmap_flash_data wrt350n_v2_nor_flash_data = { - .width = 1, - .parts = wrt350n_v2_nor_flash_partitions, - .nr_parts = ARRAY_SIZE(wrt350n_v2_nor_flash_partitions), -}; - -static struct resource wrt350n_v2_nor_flash_resource = { - .flags = IORESOURCE_MEM, - .start = WRT350N_V2_NOR_BOOT_BASE, - .end = WRT350N_V2_NOR_BOOT_BASE + WRT350N_V2_NOR_BOOT_SIZE - 1, -}; - -static struct platform_device wrt350n_v2_nor_flash = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &wrt350n_v2_nor_flash_data, - }, - .num_resources = 1, - .resource = &wrt350n_v2_nor_flash_resource, -}; - -static struct mv643xx_eth_platform_data wrt350n_v2_eth_data = { - .phy_addr = MV643XX_ETH_PHY_NONE, - .speed = SPEED_1000, - .duplex = DUPLEX_FULL, -}; - -static struct dsa_chip_data wrt350n_v2_switch_chip_data = { - .port_names[0] = "lan2", - .port_names[1] = "lan1", - .port_names[2] = "wan", - .port_names[3] = "cpu", - .port_names[5] = "lan3", - .port_names[7] = "lan4", -}; - -static void __init wrt350n_v2_init(void) -{ - /* - * Setup basic Orion functions. Need to be called early. - */ - orion5x_init(); - - orion5x_mpp_conf(wrt350n_v2_mpp_modes); - - /* - * Configure peripherals. - */ - orion5x_ehci0_init(); - orion5x_eth_init(&wrt350n_v2_eth_data); - orion5x_eth_switch_init(&wrt350n_v2_switch_chip_data); - orion5x_uart0_init(); - - mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, - ORION_MBUS_DEVBUS_BOOT_ATTR, - WRT350N_V2_NOR_BOOT_BASE, - WRT350N_V2_NOR_BOOT_SIZE); - platform_device_register(&wrt350n_v2_nor_flash); - platform_device_register(&wrt350n_v2_leds); - platform_device_register(&wrt350n_v2_button_device); -} - -static int __init wrt350n_v2_pci_map_irq(const struct pci_dev *dev, u8 slot, - u8 pin) -{ - int irq; - - /* - * Check for devices with hard-wired IRQs. - */ - irq = orion5x_pci_map_irq(dev, slot, pin); - if (irq != -1) - return irq; - - /* - * Mini-PCI slot. - */ - if (slot == 7) - return gpio_to_irq(4); - - return -1; -} - -static struct hw_pci wrt350n_v2_pci __initdata = { - .nr_controllers = 2, - .setup = orion5x_pci_sys_setup, - .scan = orion5x_pci_sys_scan_bus, - .map_irq = wrt350n_v2_pci_map_irq, -}; - -static int __init wrt350n_v2_pci_init(void) -{ - if (machine_is_wrt350n_v2()) - pci_common_init(&wrt350n_v2_pci); - - return 0; -} -subsys_initcall(wrt350n_v2_pci_init); - -MACHINE_START(WRT350N_V2, "Linksys WRT350N v2") - /* Maintainer: Lennert Buytenhek */ - .atag_offset = 0x100, - .nr_irqs = ORION5X_NR_IRQS, - .init_machine = wrt350n_v2_init, - .map_io = orion5x_map_io, - .init_early = orion5x_init_early, - .init_irq = orion5x_init_irq, - .init_time = orion5x_timer_init, - .fixup = tag_fixup_mem32, - .restart = orion5x_restart, -MACHINE_END From patchwork Wed Oct 19 15:03:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnd Bergmann X-Patchwork-Id: 5679 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp384908wrs; Wed, 19 Oct 2022 08:21:32 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6aP1rafD4OBWDwf8nZ/N3e+xVrE8UK/zEZ/qjaguXbqZgD9mqSYFpD24ZtRvo3evJACYnZ X-Received: by 2002:a05:6402:4303:b0:45c:cd3d:f5 with SMTP id m3-20020a056402430300b0045ccd3d00f5mr7957365edc.188.1666192891987; Wed, 19 Oct 2022 08:21:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666192891; cv=none; d=google.com; s=arc-20160816; b=ORfR1KwS1oGc+efUXiN+hcFaEvFasFR8UE4Nbdpbc/YjrA3qW7+ocdTs9fviAB9qfN K9cx6GfBfiZWEPAcbBFTwqlYg2CnycFa4Wt+D4wS5x8komzsj49N1Sk8OJUyyctfGdzf DXnvDLj4UnVUfPsgrOqAH6RQVMxGBQeJHAUjPAZ/JYD9SoWsWY1FiGs4a8whcQyoFMB0 x5jnTEP2kXmuAmtstIvi1ylbrweJisiSumtdAiIC0og8ujMuKaAdJE3j6LihQoyEZ8GS rFNXu2JmOypZyN7iwfkmoslT7dhofarYvx5SM9a9C2ChSLalFrLx1pESOLluCqrXw6yv dssA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=hxGfj6i1aW+8omFWsxriZaULLo+YfXXsdcDp3gJHBjE=; b=Rnl0fjB9DRClJCUqcX6SXDl9o+e/llhfdMfSwZw3vP1AH9Ee+UjTf0Aqwrm7MPZZ0j 5gdgWr58guuROMTcOCvLWrY+EUATX8HXgUl2Q3AJ/k05GnQxS812zC0mn32rS9PVfouo udh5JIFfsar/HPjXGXOmmlKOakEEDzdLEUsz+WRMAmvFid+w07lRLOtLgwOUDvcc1j0I DqTG6l5xBfxGkypR5EUuQvilZpwE2oBK/Nju6AcGsuCf1Clkc3CRxozK6YHLPmSvw/IX 079ArXrNwqCCbrLv1OM8TjS/cF+EFpFOjSBPv2nwIreCFDSzcVsExZqONvqJ6yCNz+gZ 0H6A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=HymqCo6W; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id w7-20020a05640234c700b0045cfa0b1f46si16330717edc.11.2022.10.19.08.21.06; Wed, 19 Oct 2022 08:21:31 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=HymqCo6W; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231633AbiJSPTj (ORCPT + 99 others); Wed, 19 Oct 2022 11:19:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59454 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232609AbiJSPTG (ORCPT ); Wed, 19 Oct 2022 11:19:06 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0B5B61D5E37 for ; Wed, 19 Oct 2022 08:12:41 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 1B4DC61908 for ; Wed, 19 Oct 2022 15:10:58 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2010BC433C1; Wed, 19 Oct 2022 15:10:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1666192257; bh=5xA6B6Lhx1HQ5zgGPm0eHA4kLMFysAAeoFzT5uQjs8E=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HymqCo6Wgbr9158vual4dtY6Z6kWTheel++NX6FxkCDLDPz/WtOfVkY6pPK0X8uIG BZ96t2SpLpDVwZW/1dCg+JX60hiU7+EFrNJSniwPjabX+qdr0fVhMM2Ch9Sudgn0GZ WngN9wQqMCPg6JUuJ4LtNl369yP2Eh7PNbbehbQyMGNWqFETXrtIAAKxAWGk/6yw4M w1zZThnWioAUzYgLmpWGFY+GVY5iXPBSTq5IhETugIBnLxnU4r/iAwJ76A4p0rFURW ujP3ZP5IuAyHvVboSDPwXoXqam013eYLrLVgrPyyrgXwp1vIFiRzJpZnsUYYdXQ7Ta 76wkNub2AdcJw== From: Arnd Bergmann To: linux-arm-kernel@lists.infradead.org, Andrew Lunn , Sebastian Hesselbarth , Gregory Clement Cc: linux-kernel@vger.kernel.org, Arnd Bergmann Subject: [PATCH 08/17] ARM: orion5x: remove dsa_chip_data references Date: Wed, 19 Oct 2022 17:03:30 +0200 Message-Id: <20221019150410.3851944-8-arnd@kernel.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20221019150410.3851944-1-arnd@kernel.org> References: <20221019144119.3848027-1-arnd@kernel.org> <20221019150410.3851944-1-arnd@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747129878257831015?= X-GMAIL-MSGID: =?utf-8?q?1747129878257831015?= From: Arnd Bergmann This is no longer used anywhere, which means we can kill off one link to gpio numbers. Cc: Andrew Lunn Signed-off-by: Arnd Bergmann --- arch/arm/mach-orion5x/common.c | 10 -------- arch/arm/mach-orion5x/common.h | 2 -- arch/arm/plat-orion/common.c | 31 ----------------------- arch/arm/plat-orion/include/plat/common.h | 3 --- 4 files changed, 46 deletions(-) diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c index 2e711b7252c6..df056d60b675 100644 --- a/arch/arm/mach-orion5x/common.c +++ b/arch/arm/mach-orion5x/common.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include #include @@ -100,15 +99,6 @@ void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data) } -/***************************************************************************** - * Ethernet switch - ****************************************************************************/ -void __init orion5x_eth_switch_init(struct dsa_chip_data *d) -{ - orion_ge00_switch_init(d); -} - - /***************************************************************************** * I2C ****************************************************************************/ diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h index eb96009e21c4..f2e0577bf50f 100644 --- a/arch/arm/mach-orion5x/common.h +++ b/arch/arm/mach-orion5x/common.h @@ -4,7 +4,6 @@ #include -struct dsa_chip_data; struct mv643xx_eth_platform_data; struct mv_sata_platform_data; @@ -42,7 +41,6 @@ void orion5x_setup_wins(void); void orion5x_ehci0_init(void); void orion5x_ehci1_init(void); void orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data); -void orion5x_eth_switch_init(struct dsa_chip_data *d); void orion5x_i2c_init(void); void orion5x_sata_init(struct mv_sata_platform_data *sata_data); void orion5x_spi_init(void); diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c index 8647cb80a93b..cabe98386245 100644 --- a/arch/arm/plat-orion/common.c +++ b/arch/arm/plat-orion/common.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include #include @@ -468,36 +467,6 @@ void __init orion_ge11_init(struct mv643xx_eth_platform_data *eth_data, eth_data, &orion_ge11); } -#ifdef CONFIG_ARCH_ORION5X -/***************************************************************************** - * Ethernet switch - ****************************************************************************/ -static __initdata struct mdio_board_info orion_ge00_switch_board_info = { - .bus_id = "orion-mii", - .modalias = "mv88e6085", -}; - -void __init orion_ge00_switch_init(struct dsa_chip_data *d) -{ - unsigned int i; - - if (!IS_BUILTIN(CONFIG_PHYLIB)) - return; - - for (i = 0; i < ARRAY_SIZE(d->port_names); i++) { - if (!strcmp(d->port_names[i], "cpu")) { - d->netdev[i] = &orion_ge00.dev; - break; - } - } - - orion_ge00_switch_board_info.mdio_addr = d->sw_addr; - orion_ge00_switch_board_info.platform_data = d; - - mdiobus_register_board_info(&orion_ge00_switch_board_info, 1); -} -#endif - /***************************************************************************** * I2C ****************************************************************************/ diff --git a/arch/arm/plat-orion/include/plat/common.h b/arch/arm/plat-orion/include/plat/common.h index 3647d3b33c20..d2aad95d20cb 100644 --- a/arch/arm/plat-orion/include/plat/common.h +++ b/arch/arm/plat-orion/include/plat/common.h @@ -12,7 +12,6 @@ #include #include -struct dsa_chip_data; struct mv_sata_platform_data; void __init orion_uart0_init(void __iomem *membase, @@ -57,8 +56,6 @@ void __init orion_ge11_init(struct mv643xx_eth_platform_data *eth_data, unsigned long mapbase, unsigned long irq); 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id y19-20020a056402271300b0045d9a3adf19si8596242edd.564.2022.10.19.08.22.29; Wed, 19 Oct 2022 08:22:55 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=hcqsxINc; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232128AbiJSPVL (ORCPT + 99 others); Wed, 19 Oct 2022 11:21:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44942 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231964AbiJSPUl (ORCPT ); Wed, 19 Oct 2022 11:20:41 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1FDDA43E7E; Wed, 19 Oct 2022 08:14:28 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 0105BB824BC; Wed, 19 Oct 2022 15:13:18 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id A7435C433D7; Wed, 19 Oct 2022 15:13:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1666192396; bh=cjxPuXIUh06Ba3GXCFfVn99lEclLPcRfw+NxBEe4Kg0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hcqsxINcYzTT3DkcHDdYLB3QHhzbGuZGKInydfT12xgHvQHRd+WIXuP/R+G72JcGv 8UsKYmj1ahxyJmVtwy5znbGtIhatHTgimQ0bKYqVvLf5nT+uoyLG5DlBiSi6wqg8aK HQ7odPwMV3m+iM8lqW+mtYrxkBcwzKfb/bfSHmu4Qr5I1og+Bapxwt6ZVQkX/G2KoZ cGkayXvERL+uxCqkHHjG+BVfiodRgnUnAFLCeVdM3ykW5bKp/Z3iYkiKGbHS5rD5Fm UwAx1OMTozZCpDzK8nNraeh4avjKSnvrpt1R9KBMir1uZtRg/J1vsfUk/yGd0yCJYi JEBd8KCEwHd2w== From: Arnd Bergmann To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Arnd Bergmann , Dan Williams , Lennert Buytenhek , Martin Michlmayr , linux-i2c@vger.kernel.org Subject: [PATCH 09/17] ARM: iop32x: remove the platform Date: Wed, 19 Oct 2022 17:03:31 +0200 Message-Id: <20221019150410.3851944-9-arnd@kernel.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20221019150410.3851944-1-arnd@kernel.org> References: <20221019144119.3848027-1-arnd@kernel.org> <20221019150410.3851944-1-arnd@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747129965835840014?= X-GMAIL-MSGID: =?utf-8?q?1747129965835840014?= From: Arnd Bergmann This was marked as unused in 5.19 and can now be removed Cc: Dan Williams Cc: Lennert Buytenhek Cc: Martin Michlmayr Signed-off-by: Arnd Bergmann Acked-by: Dan Williams Acked-by: Wolfram Sang # for I2C --- MAINTAINERS | 30 --- arch/arm/Kconfig | 4 +- arch/arm/Kconfig.debug | 6 +- arch/arm/Makefile | 1 - arch/arm/configs/iop32x_defconfig | 126 --------- arch/arm/kernel/entry-common.S | 15 -- arch/arm/mach-iop32x/Kconfig | 54 ---- arch/arm/mach-iop32x/Makefile | 20 -- arch/arm/mach-iop32x/adma.c | 163 ------------ arch/arm/mach-iop32x/cp6.c | 48 ---- arch/arm/mach-iop32x/em7210.c | 232 ----------------- arch/arm/mach-iop32x/glantank.c | 214 --------------- arch/arm/mach-iop32x/glantank.h | 12 - arch/arm/mach-iop32x/gpio-iop32x.h | 11 - arch/arm/mach-iop32x/hardware.h | 38 --- arch/arm/mach-iop32x/i2c.c | 92 ------- arch/arm/mach-iop32x/iop3xx.h | 326 ----------------------- arch/arm/mach-iop32x/iq31244.c | 333 ------------------------ arch/arm/mach-iop32x/iq31244.h | 16 -- arch/arm/mach-iop32x/iq80321.c | 192 -------------- arch/arm/mach-iop32x/iq80321.h | 16 -- arch/arm/mach-iop32x/irq.c | 95 ------- arch/arm/mach-iop32x/irqs.h | 48 ---- arch/arm/mach-iop32x/n2100.c | 367 -------------------------- arch/arm/mach-iop32x/n2100.h | 18 -- arch/arm/mach-iop32x/pci.c | 404 ----------------------------- arch/arm/mach-iop32x/pmu.c | 29 --- arch/arm/mach-iop32x/restart.c | 17 -- arch/arm/mach-iop32x/setup.c | 31 --- arch/arm/mach-iop32x/time.c | 179 ------------- drivers/i2c/busses/Kconfig | 6 +- 31 files changed, 6 insertions(+), 3137 deletions(-) delete mode 100644 arch/arm/configs/iop32x_defconfig delete mode 100644 arch/arm/mach-iop32x/Kconfig delete mode 100644 arch/arm/mach-iop32x/Makefile delete mode 100644 arch/arm/mach-iop32x/adma.c delete mode 100644 arch/arm/mach-iop32x/cp6.c delete mode 100644 arch/arm/mach-iop32x/em7210.c delete mode 100644 arch/arm/mach-iop32x/glantank.c delete mode 100644 arch/arm/mach-iop32x/glantank.h delete mode 100644 arch/arm/mach-iop32x/gpio-iop32x.h delete mode 100644 arch/arm/mach-iop32x/hardware.h delete mode 100644 arch/arm/mach-iop32x/i2c.c delete mode 100644 arch/arm/mach-iop32x/iop3xx.h delete mode 100644 arch/arm/mach-iop32x/iq31244.c delete mode 100644 arch/arm/mach-iop32x/iq31244.h delete mode 100644 arch/arm/mach-iop32x/iq80321.c delete mode 100644 arch/arm/mach-iop32x/iq80321.h delete mode 100644 arch/arm/mach-iop32x/irq.c delete mode 100644 arch/arm/mach-iop32x/irqs.h delete mode 100644 arch/arm/mach-iop32x/n2100.c delete mode 100644 arch/arm/mach-iop32x/n2100.h delete mode 100644 arch/arm/mach-iop32x/pci.c delete mode 100644 arch/arm/mach-iop32x/pmu.c delete mode 100644 arch/arm/mach-iop32x/restart.c delete mode 100644 arch/arm/mach-iop32x/setup.c delete mode 100644 arch/arm/mach-iop32x/time.c diff --git a/MAINTAINERS b/MAINTAINERS index 89f72dba8e64..da1ff468e27d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2215,21 +2215,6 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained F: arch/arm/mach-pxa/colibri-pxa270-income.c -ARM/INTEL IOP32X ARM ARCHITECTURE -M: Lennert Buytenhek -L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -S: Maintained - -ARM/INTEL IQ81342EX MACHINE SUPPORT -M: Lennert Buytenhek -L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -S: Maintained - -ARM/INTEL IXDP2850 MACHINE SUPPORT -M: Lennert Buytenhek -L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -S: Maintained - ARM/INTEL IXP4XX ARM ARCHITECTURE M: Linus Walleij M: Imre Kaloz @@ -2635,11 +2620,6 @@ F: include/dt-bindings/*/qcom* F: include/linux/*/qcom* F: include/linux/soc/qcom/ -ARM/RADISYS ENP2611 MACHINE SUPPORT -M: Lennert Buytenhek -L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -S: Maintained - ARM/RDA MICRO ARCHITECTURE M: Manivannan Sadhasivam L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) @@ -2971,11 +2951,6 @@ F: arch/arm64/boot/dts/ti/Makefile F: arch/arm64/boot/dts/ti/k3-* F: include/dt-bindings/pinctrl/k3.h -ARM/THECUS N2100 MACHINE SUPPORT -M: Lennert Buytenhek -L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -S: Maintained - ARM/TOSA MACHINE SUPPORT M: Dmitry Eremin-Solenikov M: Dirk Opfer @@ -10307,11 +10282,6 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git F: drivers/iommu/intel/ F: include/linux/intel-svm.h -INTEL IOP-ADMA DMA DRIVER -R: Dan Williams -S: Odd fixes -F: drivers/dma/iop-adma.c - INTEL IPU3 CSI-2 CIO2 DRIVER M: Yong Zhi M: Sakari Ailus diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index e58dab0303e6..698d88343e8e 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -280,7 +280,7 @@ config PHYS_OFFSET default 0x00000000 if ARCH_FOOTBRIDGE default 0x10000000 if ARCH_OMAP1 || ARCH_RPC default 0x30000000 if ARCH_S3C24XX - default 0xa0000000 if ARCH_IOP32X || ARCH_PXA + default 0xa0000000 if ARCH_PXA default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100 default 0 help @@ -455,8 +455,6 @@ source "arch/arm/mach-hpe/Kconfig" source "arch/arm/mach-imx/Kconfig" -source "arch/arm/mach-iop32x/Kconfig" - source "arch/arm/mach-ixp4xx/Kconfig" source "arch/arm/mach-keystone/Kconfig" diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 3b11e1d04625..320c93fabb21 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -1610,7 +1610,7 @@ config DEBUG_UART_PL01X # Compatibility options for 8250 config DEBUG_UART_8250 - def_bool ARCH_IOP32X || ARCH_IXP4XX || ARCH_RPC + def_bool ARCH_IXP4XX || ARCH_RPC config DEBUG_UART_PHYS hex "Physical base address of debug UART" @@ -1720,7 +1720,6 @@ config DEBUG_UART_PHYS default 0xfcb00000 if DEBUG_HI3620_UART default 0xfd883000 if DEBUG_ALPINE_UART0 default 0xfe531000 if DEBUG_STIH41X_SBC_ASC1 - default 0xfe800000 if ARCH_IOP32X default 0xfed32000 if DEBUG_STIH41X_ASC2 default 0xff690000 if DEBUG_RK32_UART2 default 0xffc02000 if DEBUG_SOCFPGA_UART0 @@ -1825,7 +1824,6 @@ config DEBUG_UART_VIRT default 0xfe018000 if DEBUG_MMP_UART3 default 0xfe100000 if DEBUG_IMX23_UART || DEBUG_IMX28_UART default 0xfe300000 if DEBUG_BCM_KONA_UART - default 0xfe800000 if ARCH_IOP32X default 0xfeb00000 if DEBUG_HI3620_UART || DEBUG_HIX5HD2_UART default 0xfeb24000 if DEBUG_RK3X_UART0 default 0xfeb26000 if DEBUG_RK3X_UART1 @@ -1867,7 +1865,7 @@ config DEBUG_UART_VIRT config DEBUG_UART_8250_SHIFT int "Register offset shift for the 8250 debug UART" depends on DEBUG_LL_UART_8250 || DEBUG_UART_8250 - default 0 if DEBUG_FOOTBRIDGE_COM1 || ARCH_IOP32X || DEBUG_BCM_5301X || \ + default 0 if DEBUG_FOOTBRIDGE_COM1 || DEBUG_BCM_5301X || \ DEBUG_BCM_HR2 || DEBUG_OMAP7XXUART1 || DEBUG_OMAP7XXUART2 || \ DEBUG_OMAP7XXUART3 default 3 if DEBUG_MSTARV7_PMUART diff --git a/arch/arm/Makefile b/arch/arm/Makefile index beda22911feb..1a62035d1207 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -179,7 +179,6 @@ machine-$(CONFIG_ARCH_GEMINI) += gemini machine-$(CONFIG_ARCH_HIGHBANK) += highbank machine-$(CONFIG_ARCH_HISI) += hisi machine-$(CONFIG_ARCH_HPE) += hpe -machine-$(CONFIG_ARCH_IOP32X) += iop32x machine-$(CONFIG_ARCH_IXP4XX) += ixp4xx machine-$(CONFIG_ARCH_KEYSTONE) += keystone machine-$(CONFIG_ARCH_LPC18XX) += lpc18xx diff --git a/arch/arm/configs/iop32x_defconfig b/arch/arm/configs/iop32x_defconfig deleted file mode 100644 index 19e30e790d35..000000000000 --- a/arch/arm/configs/iop32x_defconfig +++ /dev/null @@ -1,126 +0,0 @@ -CONFIG_SYSVIPC=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -CONFIG_KALLSYMS_ALL=y -# CONFIG_ARCH_MULTI_V7 is not set -CONFIG_ARCH_IOP32X=y -CONFIG_MACH_GLANTANK=y -CONFIG_ARCH_IQ80321=y -CONFIG_ARCH_IQ31244=y -CONFIG_MACH_N2100=y -CONFIG_UNUSED_BOARD_FILES=y -CONFIG_CMDLINE="console=ttyS0,115200 root=/dev/nfs ip=bootp cachepolicy=writealloc" -CONFIG_FPE_NWFPE=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_SLAB=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IPV6=y -# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET6_XFRM_MODE_TUNNEL is not set -# CONFIG_INET6_XFRM_MODE_BEET is not set -# CONFIG_IPV6_SIT is not set -CONFIG_MTD=y -CONFIG_MTD_REDBOOT_PARTS=y -CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y -CONFIG_MTD_REDBOOT_PARTS_READONLY=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_PHYSMAP=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_NBD=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=8192 -CONFIG_BLK_DEV_SD=y -CONFIG_CHR_DEV_SG=y -# CONFIG_BLK_DEV_BSG is not set -CONFIG_ATA=y -CONFIG_SATA_SIL=y -CONFIG_SATA_VITESSE=y -CONFIG_MD=y -CONFIG_BLK_DEV_MD=y -CONFIG_MD_RAID0=y -CONFIG_MD_RAID1=y -CONFIG_MD_RAID10=y -CONFIG_MD_RAID456=y -CONFIG_BLK_DEV_DM=y -CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y -CONFIG_NET_PCI=y -CONFIG_E100=y -CONFIG_E1000=y -CONFIG_R8169=y -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_HW_RANDOM=y -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_IOP3XX=y -# CONFIG_VGA_CONSOLE is not set -# CONFIG_USB_HID is not set -CONFIG_USB=y -CONFIG_USB_MON=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_ROOT_HUB_TT=y -CONFIG_USB_EHCI_TT_NEWSCHED=y -CONFIG_USB_UHCI_HCD=y -CONFIG_USB_STORAGE=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_RS5C372=y -CONFIG_DMADEVICES=y -CONFIG_INTEL_IOP_ADMA=y -CONFIG_NET_DMA=y -CONFIG_EXT2_FS=y -CONFIG_EXT3_FS=y -CONFIG_TMPFS=y -CONFIG_ECRYPT_FS=y -CONFIG_JFFS2_FS=y -CONFIG_CRAMFS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_ROOT_NFS=y -CONFIG_NFSD=y -CONFIG_KEYS=y -CONFIG_CRYPTO_NULL=y -CONFIG_CRYPTO_LRW=y -CONFIG_CRYPTO_PCBC=m -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_XCBC=y -CONFIG_CRYPTO_MD4=y -CONFIG_CRYPTO_MICHAEL_MIC=y -CONFIG_CRYPTO_SHA1=y -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_SHA512=y -CONFIG_CRYPTO_TGR192=y -CONFIG_CRYPTO_WP512=y -CONFIG_CRYPTO_AES=y -CONFIG_CRYPTO_ANUBIS=y -CONFIG_CRYPTO_ARC4=y -CONFIG_CRYPTO_BLOWFISH=y -CONFIG_CRYPTO_CAST5=y -CONFIG_CRYPTO_CAST6=y -CONFIG_CRYPTO_DES=y -CONFIG_CRYPTO_KHAZAD=y -CONFIG_CRYPTO_SERPENT=y -CONFIG_CRYPTO_TEA=y -CONFIG_CRYPTO_TWOFISH=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_LIBCRC32C=y -CONFIG_DEBUG_KERNEL=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_USER=y -CONFIG_DEBUG_LL=y -CONFIG_DEBUG_LL_UART_8250=y diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S index 405a607b754f..03d4c5578c5c 100644 --- a/arch/arm/kernel/entry-common.S +++ b/arch/arm/kernel/entry-common.S @@ -16,15 +16,6 @@ .equ NR_syscalls, __NR_syscalls - .macro arch_ret_to_user, tmp -#ifdef CONFIG_ARCH_IOP32X - mrc p15, 0, \tmp, c15, c1, 0 - tst \tmp, #(1 << 6) - bicne \tmp, \tmp, #(1 << 6) - mcrne p15, 0, \tmp, c15, c1, 0 @ Disable cp6 access -#endif - .endm - #include "entry-header.S" saved_psr .req r8 @@ -55,10 +46,6 @@ __ret_fast_syscall: movs r1, r1, lsl #16 bne fast_work_pending - - /* perform architecture specific actions before user return */ - arch_ret_to_user r1 - restore_user_regs fast = 1, offset = S_OFF UNWIND(.fnend ) ENDPROC(ret_fast_syscall) @@ -129,8 +116,6 @@ ENTRY(ret_to_user_from_irq) no_work_pending: asm_trace_hardirqs_on save = 0 - /* perform architecture specific actions before user return */ - arch_ret_to_user r1 ct_user_enter save = 0 restore_user_regs fast = 0, offset = 0 diff --git a/arch/arm/mach-iop32x/Kconfig b/arch/arm/mach-iop32x/Kconfig deleted file mode 100644 index 761fbb04faa1..000000000000 --- a/arch/arm/mach-iop32x/Kconfig +++ /dev/null @@ -1,54 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -menuconfig ARCH_IOP32X - bool "IOP32x-based platforms" - depends on ARCH_MULTI_V5 - depends on CPU_LITTLE_ENDIAN - depends on ATAGS && UNUSED_BOARD_FILES - select CPU_XSCALE - select GPIO_IOP - select GPIOLIB - select FORCE_PCI - help - Support for Intel's 80219 and IOP32X (XScale) family of - processors. - -if ARCH_IOP32X - -config MACH_EP80219 - bool - -config MACH_GLANTANK - bool "Enable support for the IO-Data GLAN Tank" - help - Say Y here if you want to run your kernel on the GLAN Tank - NAS appliance or machines from IO-Data's HDL-Gxxx, HDL-GWxxx - and HDL-GZxxx series. - -config ARCH_IQ80321 - bool "Enable support for IQ80321" - help - Say Y here if you want to run your kernel on the Intel IQ80321 - evaluation kit for the IOP321 processor. - -config ARCH_IQ31244 - bool "Enable support for EP80219/IQ31244" - select MACH_EP80219 - help - Say Y here if you want to run your kernel on the Intel EP80219 - evaluation kit for the Intel 80219 processor (a IOP321 variant) - or the IQ31244 evaluation kit for the IOP321 processor. - -config MACH_N2100 - bool "Enable support for the Thecus n2100" - help - Say Y here if you want to run your kernel on the Thecus n2100 - NAS appliance. - -config MACH_EM7210 - bool "Enable support for the Lanner EM7210" - help - Say Y here if you want to run your kernel on the Lanner EM7210 - board. Say also Y here if you have a SS4000e Baxter Creek NAS - appliance." - -endif diff --git a/arch/arm/mach-iop32x/Makefile b/arch/arm/mach-iop32x/Makefile deleted file mode 100644 index c8018ef5c6a9..000000000000 --- a/arch/arm/mach-iop32x/Makefile +++ /dev/null @@ -1,20 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# -# Makefile for the linux kernel. -# - -obj-$(CONFIG_ARCH_IOP32X) += irq.o -obj-$(CONFIG_ARCH_IOP32X) += i2c.o -obj-$(CONFIG_ARCH_IOP32X) += pci.o -obj-$(CONFIG_ARCH_IOP32X) += setup.o -obj-$(CONFIG_ARCH_IOP32X) += time.o -obj-$(CONFIG_ARCH_IOP32X) += cp6.o -obj-$(CONFIG_ARCH_IOP32X) += adma.o -obj-$(CONFIG_ARCH_IOP32X) += pmu.o -obj-$(CONFIG_ARCH_IOP32X) += restart.o - -obj-$(CONFIG_MACH_GLANTANK) += glantank.o -obj-$(CONFIG_ARCH_IQ80321) += iq80321.o -obj-$(CONFIG_ARCH_IQ31244) += iq31244.o -obj-$(CONFIG_MACH_N2100) += n2100.o -obj-$(CONFIG_MACH_EM7210) += em7210.o diff --git a/arch/arm/mach-iop32x/adma.c b/arch/arm/mach-iop32x/adma.c deleted file mode 100644 index 764bcbff98df..000000000000 --- a/arch/arm/mach-iop32x/adma.c +++ /dev/null @@ -1,163 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * platform device definitions for the iop3xx dma/xor engines - * Copyright © 2006, Intel Corporation. - */ -#include -#include -#include - -#include "iop3xx.h" -#include "irqs.h" - -#define IRQ_DMA0_EOT IRQ_IOP32X_DMA0_EOT -#define IRQ_DMA0_EOC IRQ_IOP32X_DMA0_EOC -#define IRQ_DMA0_ERR IRQ_IOP32X_DMA0_ERR - -#define IRQ_DMA1_EOT IRQ_IOP32X_DMA1_EOT -#define IRQ_DMA1_EOC IRQ_IOP32X_DMA1_EOC -#define IRQ_DMA1_ERR IRQ_IOP32X_DMA1_ERR - -#define IRQ_AA_EOT IRQ_IOP32X_AA_EOT -#define IRQ_AA_EOC IRQ_IOP32X_AA_EOC -#define IRQ_AA_ERR IRQ_IOP32X_AA_ERR - -/* AAU and DMA Channels */ -static struct resource iop3xx_dma_0_resources[] = { - [0] = { - .start = IOP3XX_DMA_PHYS_BASE(0), - .end = IOP3XX_DMA_UPPER_PA(0), - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_DMA0_EOT, - .end = IRQ_DMA0_EOT, - .flags = IORESOURCE_IRQ - }, - [2] = { - .start = IRQ_DMA0_EOC, - .end = IRQ_DMA0_EOC, - .flags = IORESOURCE_IRQ - }, - [3] = { - .start = IRQ_DMA0_ERR, - .end = IRQ_DMA0_ERR, - .flags = IORESOURCE_IRQ - } -}; - -static struct resource iop3xx_dma_1_resources[] = { - [0] = { - .start = IOP3XX_DMA_PHYS_BASE(1), - .end = IOP3XX_DMA_UPPER_PA(1), - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_DMA1_EOT, - .end = IRQ_DMA1_EOT, - .flags = IORESOURCE_IRQ - }, - [2] = { - .start = IRQ_DMA1_EOC, - .end = IRQ_DMA1_EOC, - .flags = IORESOURCE_IRQ - }, - [3] = { - .start = IRQ_DMA1_ERR, - .end = IRQ_DMA1_ERR, - .flags = IORESOURCE_IRQ - } -}; - - -static struct resource iop3xx_aau_resources[] = { - [0] = { - .start = IOP3XX_AAU_PHYS_BASE, - .end = IOP3XX_AAU_UPPER_PA, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_AA_EOT, - .end = IRQ_AA_EOT, - .flags = IORESOURCE_IRQ - }, - [2] = { - .start = IRQ_AA_EOC, - .end = IRQ_AA_EOC, - .flags = IORESOURCE_IRQ - }, - [3] = { - .start = IRQ_AA_ERR, - .end = IRQ_AA_ERR, - .flags = IORESOURCE_IRQ - } -}; - -static u64 iop3xx_adma_dmamask = DMA_BIT_MASK(32); - -static struct iop_adma_platform_data iop3xx_dma_0_data = { - .hw_id = DMA0_ID, - .pool_size = PAGE_SIZE, -}; - -static struct iop_adma_platform_data iop3xx_dma_1_data = { - .hw_id = DMA1_ID, - .pool_size = PAGE_SIZE, -}; - -static struct iop_adma_platform_data iop3xx_aau_data = { - .hw_id = AAU_ID, - .pool_size = 3 * PAGE_SIZE, -}; - -struct platform_device iop3xx_dma_0_channel = { - .name = "iop-adma", - .id = 0, - .num_resources = 4, - .resource = iop3xx_dma_0_resources, - .dev = { - .dma_mask = &iop3xx_adma_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = (void *) &iop3xx_dma_0_data, - }, -}; - -struct platform_device iop3xx_dma_1_channel = { - .name = "iop-adma", - .id = 1, - .num_resources = 4, - .resource = iop3xx_dma_1_resources, - .dev = { - .dma_mask = &iop3xx_adma_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = (void *) &iop3xx_dma_1_data, - }, -}; - -struct platform_device iop3xx_aau_channel = { - .name = "iop-adma", - .id = 2, - .num_resources = 4, - .resource = iop3xx_aau_resources, - .dev = { - .dma_mask = &iop3xx_adma_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = (void *) &iop3xx_aau_data, - }, -}; - -static int __init iop3xx_adma_cap_init(void) -{ - dma_cap_set(DMA_MEMCPY, iop3xx_dma_0_data.cap_mask); - dma_cap_set(DMA_INTERRUPT, iop3xx_dma_0_data.cap_mask); - - dma_cap_set(DMA_MEMCPY, iop3xx_dma_1_data.cap_mask); - dma_cap_set(DMA_INTERRUPT, iop3xx_dma_1_data.cap_mask); - - dma_cap_set(DMA_XOR, iop3xx_aau_data.cap_mask); - dma_cap_set(DMA_INTERRUPT, iop3xx_aau_data.cap_mask); - - return 0; -} - -arch_initcall(iop3xx_adma_cap_init); diff --git a/arch/arm/mach-iop32x/cp6.c b/arch/arm/mach-iop32x/cp6.c deleted file mode 100644 index 7135a0ac9949..000000000000 --- a/arch/arm/mach-iop32x/cp6.c +++ /dev/null @@ -1,48 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * IOP Coprocessor-6 access handler - * Copyright (c) 2006, Intel Corporation. - */ -#include -#include -#include - -#include "iop3xx.h" - -void iop_enable_cp6(void) -{ - u32 temp; - - /* enable cp6 access */ - asm volatile ( - "mrc p15, 0, %0, c15, c1, 0\n\t" - "orr %0, %0, #(1 << 6)\n\t" - "mcr p15, 0, %0, c15, c1, 0\n\t" - "mrc p15, 0, %0, c15, c1, 0\n\t" - "mov %0, %0\n\t" - "sub pc, pc, #4 @ cp_wait\n\t" - : "=r"(temp)); -} - -static int cp6_trap(struct pt_regs *regs, unsigned int instr) -{ - iop_enable_cp6(); - - return 0; -} - -/* permit kernel space cp6 access - * deny user space cp6 access - */ -static struct undef_hook cp6_hook = { - .instr_mask = 0x0f000ff0, - .instr_val = 0x0e000610, - .cpsr_mask = MODE_MASK, - .cpsr_val = SVC_MODE, - .fn = cp6_trap, -}; - -void __init iop_init_cp6_handler(void) -{ - register_undef_hook(&cp6_hook); -} diff --git a/arch/arm/mach-iop32x/em7210.c b/arch/arm/mach-iop32x/em7210.c deleted file mode 100644 index ac130aba5a6e..000000000000 --- a/arch/arm/mach-iop32x/em7210.c +++ /dev/null @@ -1,232 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * arch/arm/mach-iop32x/em7210.c - * - * Board support code for the Lanner EM7210 platforms. - * - * Based on arch/arm/mach-iop32x/iq31244.c file. - * - * Copyright (C) 2007 Arnaud Patard - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "hardware.h" -#include "gpio-iop32x.h" -#include "irqs.h" - -static void __init em7210_timer_init(void) -{ - /* http://www.kwaak.net/fotos/fotos-nas/slide_24.html */ - /* 33.333 MHz crystal. */ - iop_init_time(200000000); -} - -/* - * EM7210 RTC - */ -static struct i2c_board_info __initdata em7210_i2c_devices[] = { - { - I2C_BOARD_INFO("rs5c372a", 0x32), - }, -}; - -/* - * EM7210 I/O - */ -static struct map_desc em7210_io_desc[] __initdata = { - { /* on-board devices */ - .virtual = IQ31244_UART, - .pfn = __phys_to_pfn(IQ31244_UART), - .length = 0x00100000, - .type = MT_DEVICE, - }, -}; - -void __init em7210_map_io(void) -{ - iop3xx_map_io(); - iotable_init(em7210_io_desc, ARRAY_SIZE(em7210_io_desc)); -} - - -/* - * EM7210 PCI - */ -#define INTA IRQ_IOP32X_XINT0 -#define INTB IRQ_IOP32X_XINT1 -#define INTC IRQ_IOP32X_XINT2 -#define INTD IRQ_IOP32X_XINT3 - -static int __init -em7210_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - static int pci_irq_table[][4] = { - /* - * PCI IDSEL/INTPIN->INTLINE - * A B C D - */ - {INTB, INTB, INTB, INTB}, /* console / uart */ - {INTA, INTA, INTA, INTA}, /* 1st 82541 */ - {INTD, INTD, INTD, INTD}, /* 2nd 82541 */ - {INTC, INTC, INTC, INTC}, /* GD31244 */ - {INTD, INTA, INTA, INTA}, /* mini-PCI */ - {INTD, INTC, INTA, INTA}, /* NEC USB */ - }; - - if (pin < 1 || pin > 4) - return -1; - - return pci_irq_table[slot % 6][pin - 1]; -} - -static struct hw_pci em7210_pci __initdata = { - .nr_controllers = 1, - .ops = &iop3xx_ops, - .setup = iop3xx_pci_setup, - .preinit = iop3xx_pci_preinit, - .map_irq = em7210_pci_map_irq, -}; - -static int __init em7210_pci_init(void) -{ - if (machine_is_em7210()) - pci_common_init(&em7210_pci); - - return 0; -} - -subsys_initcall(em7210_pci_init); - - -/* - * EM7210 Flash - */ -static struct physmap_flash_data em7210_flash_data = { - .width = 2, -}; - -static struct resource em7210_flash_resource = { - .start = 0xf0000000, - .end = 0xf1ffffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device em7210_flash_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &em7210_flash_data, - }, - .num_resources = 1, - .resource = &em7210_flash_resource, -}; - - -/* - * EM7210 UART - * The physical address of the serial port is 0xfe800000, - * so it can be used for physical and virtual address. - */ -static struct plat_serial8250_port em7210_serial_port[] = { - { - .mapbase = IQ31244_UART, - .membase = (char *)IQ31244_UART, - .irq = IRQ_IOP32X_XINT1, - .flags = UPF_SKIP_TEST, - .iotype = UPIO_MEM, - .regshift = 0, - .uartclk = 1843200, - }, - { }, -}; - -static struct resource em7210_uart_resource = { - .start = IQ31244_UART, - .end = IQ31244_UART + 7, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device em7210_serial_device = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = em7210_serial_port, - }, - .num_resources = 1, - .resource = &em7210_uart_resource, -}; - -#define EM7210_HARDWARE_POWER 0 - -void em7210_power_off(void) -{ - int ret; - - ret = gpio_direction_output(EM7210_HARDWARE_POWER, 1); - if (ret) - pr_crit("could not drive power off GPIO high\n"); -} - -static int __init em7210_request_gpios(void) -{ - int ret; - - if (!machine_is_em7210()) - return 0; - - ret = gpio_request(EM7210_HARDWARE_POWER, "power"); - if (ret) { - pr_err("could not request power off GPIO\n"); - return 0; - } - - pm_power_off = em7210_power_off; - - return 0; -} -device_initcall(em7210_request_gpios); - -static void __init em7210_init_machine(void) -{ - register_iop32x_gpio(); - platform_device_register(&em7210_serial_device); - gpiod_add_lookup_table(&iop3xx_i2c0_gpio_lookup); - gpiod_add_lookup_table(&iop3xx_i2c1_gpio_lookup); - platform_device_register(&iop3xx_i2c0_device); - platform_device_register(&iop3xx_i2c1_device); - platform_device_register(&em7210_flash_device); - platform_device_register(&iop3xx_dma_0_channel); - platform_device_register(&iop3xx_dma_1_channel); - - i2c_register_board_info(0, em7210_i2c_devices, - ARRAY_SIZE(em7210_i2c_devices)); -} - -MACHINE_START(EM7210, "Lanner EM7210") - .atag_offset = 0x100, - .nr_irqs = IOP32X_NR_IRQS, - .map_io = em7210_map_io, - .init_irq = iop32x_init_irq, - .init_time = em7210_timer_init, - .init_machine = em7210_init_machine, - .restart = iop3xx_restart, -MACHINE_END diff --git a/arch/arm/mach-iop32x/glantank.c b/arch/arm/mach-iop32x/glantank.c deleted file mode 100644 index cd6e7da2ea10..000000000000 --- a/arch/arm/mach-iop32x/glantank.c +++ /dev/null @@ -1,214 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * arch/arm/mach-iop32x/glantank.c - * - * Board support code for the GLAN Tank. - * - * Copyright (C) 2006, 2007 Martin Michlmayr - * Copyright (C) 2006 Lennert Buytenhek - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "hardware.h" -#include "gpio-iop32x.h" -#include "irqs.h" - -/* - * GLAN Tank timer tick configuration. - */ -static void __init glantank_timer_init(void) -{ - /* 33.333 MHz crystal. */ - iop_init_time(200000000); -} - - -/* - * GLAN Tank I/O. - */ -static struct map_desc glantank_io_desc[] __initdata = { - { /* on-board devices */ - .virtual = GLANTANK_UART, - .pfn = __phys_to_pfn(GLANTANK_UART), - .length = 0x00100000, - .type = MT_DEVICE - }, -}; - -void __init glantank_map_io(void) -{ - iop3xx_map_io(); - iotable_init(glantank_io_desc, ARRAY_SIZE(glantank_io_desc)); -} - - -/* - * GLAN Tank PCI. - */ -#define INTA IRQ_IOP32X_XINT0 -#define INTB IRQ_IOP32X_XINT1 -#define INTC IRQ_IOP32X_XINT2 -#define INTD IRQ_IOP32X_XINT3 - -static int __init -glantank_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - static int pci_irq_table[][4] = { - /* - * PCI IDSEL/INTPIN->INTLINE - * A B C D - */ - {INTD, INTD, INTD, INTD}, /* UART (8250) */ - {INTA, INTA, INTA, INTA}, /* Ethernet (E1000) */ - {INTB, INTB, INTB, INTB}, /* IDE (AEC6280R) */ - {INTC, INTC, INTC, INTC}, /* USB (NEC) */ - }; - - BUG_ON(pin < 1 || pin > 4); - - return pci_irq_table[slot % 4][pin - 1]; -} - -static struct hw_pci glantank_pci __initdata = { - .nr_controllers = 1, - .ops = &iop3xx_ops, - .setup = iop3xx_pci_setup, - .preinit = iop3xx_pci_preinit, - .map_irq = glantank_pci_map_irq, -}; - -static int __init glantank_pci_init(void) -{ - if (machine_is_glantank()) - pci_common_init(&glantank_pci); - - return 0; -} - -subsys_initcall(glantank_pci_init); - - -/* - * GLAN Tank machine initialization. - */ -static struct physmap_flash_data glantank_flash_data = { - .width = 2, -}; - -static struct resource glantank_flash_resource = { - .start = 0xf0000000, - .end = 0xf007ffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device glantank_flash_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &glantank_flash_data, - }, - .num_resources = 1, - .resource = &glantank_flash_resource, -}; - -static struct plat_serial8250_port glantank_serial_port[] = { - { - .mapbase = GLANTANK_UART, - .membase = (char *)GLANTANK_UART, - .irq = IRQ_IOP32X_XINT3, - .flags = UPF_SKIP_TEST, - .iotype = UPIO_MEM, - .regshift = 0, - .uartclk = 1843200, - }, - { }, -}; - -static struct resource glantank_uart_resource = { - .start = GLANTANK_UART, - .end = GLANTANK_UART + 7, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device glantank_serial_device = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = glantank_serial_port, - }, - .num_resources = 1, - .resource = &glantank_uart_resource, -}; - -static struct f75375s_platform_data glantank_f75375s = { - .pwm = { 255, 255 }, - .pwm_enable = { 0, 0 }, -}; - -static struct i2c_board_info __initdata glantank_i2c_devices[] = { - { - I2C_BOARD_INFO("rs5c372a", 0x32), - }, - { - I2C_BOARD_INFO("f75375", 0x2e), - .platform_data = &glantank_f75375s, - }, -}; - -static void glantank_power_off(void) -{ - __raw_writeb(0x01, IOMEM(0xfe8d0004)); - - while (1) - ; -} - -static void __init glantank_init_machine(void) -{ - register_iop32x_gpio(); - gpiod_add_lookup_table(&iop3xx_i2c0_gpio_lookup); - gpiod_add_lookup_table(&iop3xx_i2c1_gpio_lookup); - platform_device_register(&iop3xx_i2c0_device); - platform_device_register(&iop3xx_i2c1_device); - platform_device_register(&glantank_flash_device); - platform_device_register(&glantank_serial_device); - platform_device_register(&iop3xx_dma_0_channel); - platform_device_register(&iop3xx_dma_1_channel); - - i2c_register_board_info(0, glantank_i2c_devices, - ARRAY_SIZE(glantank_i2c_devices)); - - pm_power_off = glantank_power_off; -} - -MACHINE_START(GLANTANK, "GLAN Tank") - /* Maintainer: Lennert Buytenhek */ - .atag_offset = 0x100, - .nr_irqs = IOP32X_NR_IRQS, - .map_io = glantank_map_io, - .init_irq = iop32x_init_irq, - .init_time = glantank_timer_init, - .init_machine = glantank_init_machine, - .restart = iop3xx_restart, -MACHINE_END diff --git a/arch/arm/mach-iop32x/glantank.h b/arch/arm/mach-iop32x/glantank.h deleted file mode 100644 index f38e86b82c3d..000000000000 --- a/arch/arm/mach-iop32x/glantank.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * IO-Data GLAN Tank board registers - */ - -#ifndef __GLANTANK_H -#define __GLANTANK_H - -#define GLANTANK_UART 0xfe800000 /* UART */ - - -#endif diff --git a/arch/arm/mach-iop32x/gpio-iop32x.h b/arch/arm/mach-iop32x/gpio-iop32x.h deleted file mode 100644 index 20af87e4c5e8..000000000000 --- a/arch/arm/mach-iop32x/gpio-iop32x.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -static struct resource iop32x_gpio_res[] = { - DEFINE_RES_MEM((IOP3XX_PERIPHERAL_PHYS_BASE + 0x07c4), 0x10), -}; - -static inline void register_iop32x_gpio(void) -{ - platform_device_register_simple("gpio-iop", 0, - iop32x_gpio_res, - ARRAY_SIZE(iop32x_gpio_res)); -} diff --git a/arch/arm/mach-iop32x/hardware.h b/arch/arm/mach-iop32x/hardware.h deleted file mode 100644 index 43ab4fb8f9b0..000000000000 --- a/arch/arm/mach-iop32x/hardware.h +++ /dev/null @@ -1,38 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __HARDWARE_H -#define __HARDWARE_H - -#include - -/* - * Note about PCI IO space mappings - * - * To make IO space accesses efficient, we store virtual addresses in - * the IO resources. - * - * The PCI IO space is located at virtual 0xfe000000 from physical - * 0x90000000. The PCI BARs must be programmed with physical addresses, - * but when we read them, we convert them to virtual addresses. See - * arch/arm/plat-iop/pci.c. - */ - -#ifndef __ASSEMBLY__ -void iop32x_init_irq(void); -#endif - - -/* - * Generic chipset bits - */ -#include "iop3xx.h" - -/* - * Board specific bits - */ -#include "glantank.h" -#include "iq80321.h" -#include "iq31244.h" -#include "n2100.h" - - -#endif diff --git a/arch/arm/mach-iop32x/i2c.c b/arch/arm/mach-iop32x/i2c.c deleted file mode 100644 index e422286af469..000000000000 --- a/arch/arm/mach-iop32x/i2c.c +++ /dev/null @@ -1,92 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * arch/arm/plat-iop/i2c.c - * - * Author: Nicolas Pitre - * Copyright (C) 2001 MontaVista Software, Inc. - * Copyright (C) 2004 Intel Corporation. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "hardware.h" -#include "iop3xx.h" -#include "irqs.h" - -/* - * Each of the I2C busses have corresponding GPIO lines, and the driver - * need to access these directly to drive the bus low at times. - */ - -struct gpiod_lookup_table iop3xx_i2c0_gpio_lookup = { - .dev_id = "IOP3xx-I2C.0", - .table = { - GPIO_LOOKUP("gpio-iop", 7, "scl", GPIO_ACTIVE_HIGH), - GPIO_LOOKUP("gpio-iop", 6, "sda", GPIO_ACTIVE_HIGH), - { } - }, -}; - -struct gpiod_lookup_table iop3xx_i2c1_gpio_lookup = { - .dev_id = "IOP3xx-I2C.1", - .table = { - GPIO_LOOKUP("gpio-iop", 5, "scl", GPIO_ACTIVE_HIGH), - GPIO_LOOKUP("gpio-iop", 4, "sda", GPIO_ACTIVE_HIGH), - { } - }, -}; - -static struct resource iop3xx_i2c0_resources[] = { - [0] = { - .start = 0xfffff680, - .end = 0xfffff697, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_IOP32X_I2C_0, - .end = IRQ_IOP32X_I2C_0, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device iop3xx_i2c0_device = { - .name = "IOP3xx-I2C", - .id = 0, - .num_resources = 2, - .resource = iop3xx_i2c0_resources, -}; - - -static struct resource iop3xx_i2c1_resources[] = { - [0] = { - .start = 0xfffff6a0, - .end = 0xfffff6b7, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_IOP32X_I2C_1, - .end = IRQ_IOP32X_I2C_1, - .flags = IORESOURCE_IRQ, - } -}; - -struct platform_device iop3xx_i2c1_device = { - .name = "IOP3xx-I2C", - .id = 1, - .num_resources = 2, - .resource = iop3xx_i2c1_resources, -}; diff --git a/arch/arm/mach-iop32x/iop3xx.h b/arch/arm/mach-iop32x/iop3xx.h deleted file mode 100644 index a6ec7ebadb35..000000000000 --- a/arch/arm/mach-iop32x/iop3xx.h +++ /dev/null @@ -1,326 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Intel IOP32X and IOP33X register definitions - * - * Author: Rory Bolt - * Copyright (C) 2002 Rory Bolt - * Copyright (C) 2004 Intel Corp. - */ - -#ifndef __IOP3XX_H -#define __IOP3XX_H - -/* - * Peripherals that are shared between the iop32x and iop33x but - * located at different addresses. - */ -#define IOP3XX_TIMER_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07e0 + (reg)) - -#include "iop3xx.h" - -/* ATU Parameters - * set up a 1:1 bus to physical ram relationship - * w/ physical ram on top of pci in the memory map - */ -#define IOP32X_MAX_RAM_SIZE 0x40000000UL -#define IOP3XX_MAX_RAM_SIZE IOP32X_MAX_RAM_SIZE -#define IOP3XX_PCI_LOWER_MEM_BA 0x80000000 - -/* - * IOP3XX GPIO handling - */ -#define IOP3XX_GPIO_LINE(x) (x) - -#ifndef __ASSEMBLY__ -extern int init_atu; -extern int iop3xx_get_init_atu(void); -#endif - - -/* - * IOP3XX processor registers - */ -#define IOP3XX_PERIPHERAL_PHYS_BASE 0xffffe000 -#define IOP3XX_PERIPHERAL_VIRT_BASE 0xfedfe000 -#define IOP3XX_PERIPHERAL_SIZE 0x00002000 -#define IOP3XX_PERIPHERAL_UPPER_PA (IOP3XX_PERIPHERAL_PHYS_BASE +\ - IOP3XX_PERIPHERAL_SIZE - 1) -#define IOP3XX_PERIPHERAL_UPPER_VA (IOP3XX_PERIPHERAL_VIRT_BASE +\ - IOP3XX_PERIPHERAL_SIZE - 1) -#define IOP3XX_PMMR_PHYS_TO_VIRT(addr) (u32) ((u32) (addr) -\ - (IOP3XX_PERIPHERAL_PHYS_BASE\ - - IOP3XX_PERIPHERAL_VIRT_BASE)) -#define IOP3XX_REG_ADDR(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + (reg)) - -/* Address Translation Unit */ -#define IOP3XX_ATUVID (volatile u16 *)IOP3XX_REG_ADDR(0x0100) -#define IOP3XX_ATUDID (volatile u16 *)IOP3XX_REG_ADDR(0x0102) -#define IOP3XX_ATUCMD (volatile u16 *)IOP3XX_REG_ADDR(0x0104) -#define IOP3XX_ATUSR (volatile u16 *)IOP3XX_REG_ADDR(0x0106) -#define IOP3XX_ATURID (volatile u8 *)IOP3XX_REG_ADDR(0x0108) -#define IOP3XX_ATUCCR (volatile u32 *)IOP3XX_REG_ADDR(0x0109) -#define IOP3XX_ATUCLSR (volatile u8 *)IOP3XX_REG_ADDR(0x010c) -#define IOP3XX_ATULT (volatile u8 *)IOP3XX_REG_ADDR(0x010d) -#define IOP3XX_ATUHTR (volatile u8 *)IOP3XX_REG_ADDR(0x010e) -#define IOP3XX_ATUBIST (volatile u8 *)IOP3XX_REG_ADDR(0x010f) -#define IOP3XX_IABAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0110) -#define IOP3XX_IAUBAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0114) -#define IOP3XX_IABAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0118) -#define IOP3XX_IAUBAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x011c) -#define IOP3XX_IABAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0120) -#define IOP3XX_IAUBAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0124) -#define IOP3XX_ASVIR (volatile u16 *)IOP3XX_REG_ADDR(0x012c) -#define IOP3XX_ASIR (volatile u16 *)IOP3XX_REG_ADDR(0x012e) -#define IOP3XX_ERBAR (volatile u32 *)IOP3XX_REG_ADDR(0x0130) -#define IOP3XX_ATUILR (volatile u8 *)IOP3XX_REG_ADDR(0x013c) -#define IOP3XX_ATUIPR (volatile u8 *)IOP3XX_REG_ADDR(0x013d) -#define IOP3XX_ATUMGNT (volatile u8 *)IOP3XX_REG_ADDR(0x013e) -#define IOP3XX_ATUMLAT (volatile u8 *)IOP3XX_REG_ADDR(0x013f) -#define IOP3XX_IALR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0140) -#define IOP3XX_IATVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0144) -#define IOP3XX_ERLR (volatile u32 *)IOP3XX_REG_ADDR(0x0148) -#define IOP3XX_ERTVR (volatile u32 *)IOP3XX_REG_ADDR(0x014c) -#define IOP3XX_IALR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0150) -#define IOP3XX_IALR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0154) -#define IOP3XX_IATVR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0158) -#define IOP3XX_OIOWTVR (volatile u32 *)IOP3XX_REG_ADDR(0x015c) -#define IOP3XX_OMWTVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0160) -#define IOP3XX_OUMWTVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0164) -#define IOP3XX_OMWTVR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0168) -#define IOP3XX_OUMWTVR1 (volatile u32 *)IOP3XX_REG_ADDR(0x016c) -#define IOP3XX_OUDWTVR (volatile u32 *)IOP3XX_REG_ADDR(0x0178) -#define IOP3XX_ATUCR (volatile u32 *)IOP3XX_REG_ADDR(0x0180) -#define IOP3XX_PCSR (volatile u32 *)IOP3XX_REG_ADDR(0x0184) -#define IOP3XX_ATUISR (volatile u32 *)IOP3XX_REG_ADDR(0x0188) -#define IOP3XX_ATUIMR (volatile u32 *)IOP3XX_REG_ADDR(0x018c) -#define IOP3XX_IABAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0190) -#define IOP3XX_IAUBAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0194) -#define IOP3XX_IALR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0198) -#define IOP3XX_IATVR3 (volatile u32 *)IOP3XX_REG_ADDR(0x019c) -#define IOP3XX_OCCAR (volatile u32 *)IOP3XX_REG_ADDR(0x01a4) -#define IOP3XX_OCCDR (volatile u32 *)IOP3XX_REG_ADDR(0x01ac) -#define IOP3XX_PDSCR (volatile u32 *)IOP3XX_REG_ADDR(0x01bc) -#define IOP3XX_PMCAPID (volatile u8 *)IOP3XX_REG_ADDR(0x01c0) -#define IOP3XX_PMNEXT (volatile u8 *)IOP3XX_REG_ADDR(0x01c1) -#define IOP3XX_APMCR (volatile u16 *)IOP3XX_REG_ADDR(0x01c2) -#define IOP3XX_APMCSR (volatile u16 *)IOP3XX_REG_ADDR(0x01c4) -#define IOP3XX_PCIXCAPID (volatile u8 *)IOP3XX_REG_ADDR(0x01e0) -#define IOP3XX_PCIXNEXT (volatile u8 *)IOP3XX_REG_ADDR(0x01e1) -#define IOP3XX_PCIXCMD (volatile u16 *)IOP3XX_REG_ADDR(0x01e2) -#define IOP3XX_PCIXSR (volatile u32 *)IOP3XX_REG_ADDR(0x01e4) -#define IOP3XX_PCIIRSR (volatile u32 *)IOP3XX_REG_ADDR(0x01ec) -#define IOP3XX_PCSR_OUT_Q_BUSY (1 << 15) -#define IOP3XX_PCSR_IN_Q_BUSY (1 << 14) -#define IOP3XX_ATUCR_OUT_EN (1 << 1) - -#define IOP3XX_INIT_ATU_DEFAULT 0 -#define IOP3XX_INIT_ATU_DISABLE -1 -#define IOP3XX_INIT_ATU_ENABLE 1 - -/* Messaging Unit */ -#define IOP3XX_IMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0310) -#define IOP3XX_IMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0314) -#define IOP3XX_OMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0318) -#define IOP3XX_OMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x031c) -#define IOP3XX_IDR (volatile u32 *)IOP3XX_REG_ADDR(0x0320) -#define IOP3XX_IISR (volatile u32 *)IOP3XX_REG_ADDR(0x0324) -#define IOP3XX_IIMR (volatile u32 *)IOP3XX_REG_ADDR(0x0328) -#define IOP3XX_ODR (volatile u32 *)IOP3XX_REG_ADDR(0x032c) -#define IOP3XX_OISR (volatile u32 *)IOP3XX_REG_ADDR(0x0330) -#define IOP3XX_OIMR (volatile u32 *)IOP3XX_REG_ADDR(0x0334) -#define IOP3XX_MUCR (volatile u32 *)IOP3XX_REG_ADDR(0x0350) -#define IOP3XX_QBAR (volatile u32 *)IOP3XX_REG_ADDR(0x0354) -#define IOP3XX_IFHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0360) -#define IOP3XX_IFTPR (volatile u32 *)IOP3XX_REG_ADDR(0x0364) -#define IOP3XX_IPHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0368) -#define IOP3XX_IPTPR (volatile u32 *)IOP3XX_REG_ADDR(0x036c) -#define IOP3XX_OFHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0370) -#define IOP3XX_OFTPR (volatile u32 *)IOP3XX_REG_ADDR(0x0374) -#define IOP3XX_OPHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0378) -#define IOP3XX_OPTPR (volatile u32 *)IOP3XX_REG_ADDR(0x037c) -#define IOP3XX_IAR (volatile u32 *)IOP3XX_REG_ADDR(0x0380) - -/* DMA Controller */ -#define IOP3XX_DMA_PHYS_BASE(chan) (IOP3XX_PERIPHERAL_PHYS_BASE + \ - (0x400 + (chan << 6))) -#define IOP3XX_DMA_UPPER_PA(chan) (IOP3XX_DMA_PHYS_BASE(chan) + 0x27) - -/* Peripheral bus interface */ -#define IOP3XX_PBCR (volatile u32 *)IOP3XX_REG_ADDR(0x0680) -#define IOP3XX_PBISR (volatile u32 *)IOP3XX_REG_ADDR(0x0684) -#define IOP3XX_PBBAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0688) -#define IOP3XX_PBLR0 (volatile u32 *)IOP3XX_REG_ADDR(0x068c) -#define IOP3XX_PBBAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0690) -#define IOP3XX_PBLR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0694) -#define IOP3XX_PBBAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0698) -#define IOP3XX_PBLR2 (volatile u32 *)IOP3XX_REG_ADDR(0x069c) -#define IOP3XX_PBBAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x06a0) -#define IOP3XX_PBLR3 (volatile u32 *)IOP3XX_REG_ADDR(0x06a4) -#define IOP3XX_PBBAR4 (volatile u32 *)IOP3XX_REG_ADDR(0x06a8) -#define IOP3XX_PBLR4 (volatile u32 *)IOP3XX_REG_ADDR(0x06ac) -#define IOP3XX_PBBAR5 (volatile u32 *)IOP3XX_REG_ADDR(0x06b0) -#define IOP3XX_PBLR5 (volatile u32 *)IOP3XX_REG_ADDR(0x06b4) -#define IOP3XX_PMBR0 (volatile u32 *)IOP3XX_REG_ADDR(0x06c0) -#define IOP3XX_PMBR1 (volatile u32 *)IOP3XX_REG_ADDR(0x06e0) -#define IOP3XX_PMBR2 (volatile u32 *)IOP3XX_REG_ADDR(0x06e4) - -/* Peripheral performance monitoring unit */ -#define IOP3XX_GTMR (volatile u32 *)IOP3XX_REG_ADDR(0x0700) -#define IOP3XX_ESR (volatile u32 *)IOP3XX_REG_ADDR(0x0704) -#define IOP3XX_EMISR (volatile u32 *)IOP3XX_REG_ADDR(0x0708) -#define IOP3XX_GTSR (volatile u32 *)IOP3XX_REG_ADDR(0x0710) -/* PERCR0 DOESN'T EXIST - index from 1! */ -#define IOP3XX_PERCR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0710) - -/* Timers */ -#define IOP3XX_TU_TMR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0000) -#define IOP3XX_TU_TMR1 (volatile u32 *)IOP3XX_TIMER_REG(0x0004) -#define IOP3XX_TU_TCR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0008) -#define IOP3XX_TU_TCR1 (volatile u32 *)IOP3XX_TIMER_REG(0x000c) -#define IOP3XX_TU_TRR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0010) -#define IOP3XX_TU_TRR1 (volatile u32 *)IOP3XX_TIMER_REG(0x0014) -#define IOP3XX_TU_TISR (volatile u32 *)IOP3XX_TIMER_REG(0x0018) -#define IOP3XX_TU_WDTCR (volatile u32 *)IOP3XX_TIMER_REG(0x001c) -#define IOP_TMR_EN 0x02 -#define IOP_TMR_RELOAD 0x04 -#define IOP_TMR_PRIVILEGED 0x08 -#define IOP_TMR_RATIO_1_1 0x00 - -/* Watchdog timer definitions */ -#define IOP_WDTCR_EN_ARM 0x1e1e1e1e -#define IOP_WDTCR_EN 0xe1e1e1e1 -/* iop3xx does not support stopping the watchdog, so we just re-arm */ -#define IOP_WDTCR_DIS_ARM (IOP_WDTCR_EN_ARM) -#define IOP_WDTCR_DIS (IOP_WDTCR_EN) - -/* Application accelerator unit */ -#define IOP3XX_AAU_PHYS_BASE (IOP3XX_PERIPHERAL_PHYS_BASE + 0x800) -#define IOP3XX_AAU_UPPER_PA (IOP3XX_AAU_PHYS_BASE + 0xa7) - -/* I2C bus interface unit */ -#define IOP3XX_ICR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1680) -#define IOP3XX_ISR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1684) -#define IOP3XX_ISAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1688) -#define IOP3XX_IDBR0 (volatile u32 *)IOP3XX_REG_ADDR(0x168c) -#define IOP3XX_IBMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1694) -#define IOP3XX_ICR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a0) -#define IOP3XX_ISR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a4) -#define IOP3XX_ISAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a8) -#define IOP3XX_IDBR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16ac) -#define IOP3XX_IBMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16b4) - - -/* - * IOP3XX I/O and Mem space regions for PCI autoconfiguration - */ -#define IOP3XX_PCI_LOWER_MEM_PA 0x80000000 -#define IOP3XX_PCI_MEM_WINDOW_SIZE 0x08000000 - -#define IOP3XX_PCI_LOWER_IO_PA 0x90000000 -#define IOP3XX_PCI_LOWER_IO_BA 0x00000000 - -#ifndef __ASSEMBLY__ - -#include -#include - -void iop3xx_map_io(void); -void iop_enable_cp6(void); -void iop_init_cp6_handler(void); -void iop_init_time(unsigned long tickrate); -void iop3xx_restart(enum reboot_mode, const char *); - -static inline u32 read_tmr0(void) -{ - u32 val; - asm volatile("mrc p6, 0, %0, c0, c1, 0" : "=r" (val)); - return val; -} - -static inline void write_tmr0(u32 val) -{ - asm volatile("mcr p6, 0, %0, c0, c1, 0" : : "r" (val)); -} - -static inline void write_tmr1(u32 val) -{ - asm volatile("mcr p6, 0, %0, c1, c1, 0" : : "r" (val)); -} - -static inline u32 read_tcr0(void) -{ - u32 val; - asm volatile("mrc p6, 0, %0, c2, c1, 0" : "=r" (val)); - return val; -} - -static inline void write_tcr0(u32 val) -{ - asm volatile("mcr p6, 0, %0, c2, c1, 0" : : "r" (val)); -} - -static inline u32 read_tcr1(void) -{ - u32 val; - asm volatile("mrc p6, 0, %0, c3, c1, 0" : "=r" (val)); - return val; -} - -static inline void write_tcr1(u32 val) -{ - asm volatile("mcr p6, 0, %0, c3, c1, 0" : : "r" (val)); -} - -static inline void write_trr0(u32 val) -{ - asm volatile("mcr p6, 0, %0, c4, c1, 0" : : "r" (val)); -} - -static inline void write_trr1(u32 val) -{ - asm volatile("mcr p6, 0, %0, c5, c1, 0" : : "r" (val)); -} - -static inline void write_tisr(u32 val) -{ - asm volatile("mcr p6, 0, %0, c6, c1, 0" : : "r" (val)); -} - -static inline u32 read_wdtcr(void) -{ - u32 val; - asm volatile("mrc p6, 0, %0, c7, c1, 0":"=r" (val)); - return val; -} -static inline void write_wdtcr(u32 val) -{ - asm volatile("mcr p6, 0, %0, c7, c1, 0"::"r" (val)); -} - -extern unsigned long get_iop_tick_rate(void); - -/* only iop13xx has these registers, we define these to present a - * common register interface for the iop_wdt driver. - */ -#define IOP_RCSR_WDT (0) -static inline u32 read_rcsr(void) -{ - return 0; -} -static inline void write_wdtsr(u32 val) -{ - do { } while (0); -} - -extern struct platform_device iop3xx_dma_0_channel; -extern struct platform_device iop3xx_dma_1_channel; -extern struct platform_device iop3xx_aau_channel; -extern struct platform_device iop3xx_i2c0_device; -extern struct platform_device iop3xx_i2c1_device; -extern struct gpiod_lookup_table iop3xx_i2c0_gpio_lookup; -extern struct gpiod_lookup_table iop3xx_i2c1_gpio_lookup; - -#endif - - -#endif diff --git a/arch/arm/mach-iop32x/iq31244.c b/arch/arm/mach-iop32x/iq31244.c deleted file mode 100644 index 8b4c29d17265..000000000000 --- a/arch/arm/mach-iop32x/iq31244.c +++ /dev/null @@ -1,333 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * arch/arm/mach-iop32x/iq31244.c - * - * Board support code for the Intel EP80219 and IQ31244 platforms. - * - * Author: Rory Bolt - * Copyright (C) 2002 Rory Bolt - * Copyright 2003 (c) MontaVista, Software, Inc. - * Copyright (C) 2004 Intel Corp. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "hardware.h" -#include "irqs.h" -#include "gpio-iop32x.h" - -/* - * Until March of 2007 iq31244 platforms and ep80219 platforms shared the - * same machine id, and the processor type was used to select board type. - * However this assumption breaks for an iq80219 board which is an iop219 - * processor on an iq31244 board. The force_ep80219 flag has been added - * for old boot loaders using the iq31244 machine id for an ep80219 platform. - */ -static int force_ep80219; - -static int is_80219(void) -{ - return !!((read_cpuid_id() & 0xffffffe0) == 0x69052e20); -} - -static int is_ep80219(void) -{ - if (machine_is_ep80219() || force_ep80219) - return 1; - else - return 0; -} - - -/* - * EP80219/IQ31244 timer tick configuration. - */ -static void __init iq31244_timer_init(void) -{ - if (is_ep80219()) { - /* 33.333 MHz crystal. */ - iop_init_time(200000000); - } else { - /* 33.000 MHz crystal. */ - iop_init_time(198000000); - } -} - - -/* - * IQ31244 I/O. - */ -static struct map_desc iq31244_io_desc[] __initdata = { - { /* on-board devices */ - .virtual = IQ31244_UART, - .pfn = __phys_to_pfn(IQ31244_UART), - .length = 0x00100000, - .type = MT_DEVICE, - }, -}; - -void __init iq31244_map_io(void) -{ - iop3xx_map_io(); - iotable_init(iq31244_io_desc, ARRAY_SIZE(iq31244_io_desc)); -} - - -/* - * EP80219/IQ31244 PCI. - */ -static int __init -ep80219_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - int irq; - - if (slot == 0) { - /* CFlash */ - irq = IRQ_IOP32X_XINT1; - } else if (slot == 1) { - /* 82551 Pro 100 */ - irq = IRQ_IOP32X_XINT0; - } else if (slot == 2) { - /* PCI-X Slot */ - irq = IRQ_IOP32X_XINT3; - } else if (slot == 3) { - /* SATA */ - irq = IRQ_IOP32X_XINT2; - } else { - printk(KERN_ERR "ep80219_pci_map_irq() called for unknown " - "device PCI:%d:%d:%d\n", dev->bus->number, - PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn)); - irq = -1; - } - - return irq; -} - -static struct hw_pci ep80219_pci __initdata = { - .nr_controllers = 1, - .ops = &iop3xx_ops, - .setup = iop3xx_pci_setup, - .preinit = iop3xx_pci_preinit, - .map_irq = ep80219_pci_map_irq, -}; - -static int __init -iq31244_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - int irq; - - if (slot == 0) { - /* CFlash */ - irq = IRQ_IOP32X_XINT1; - } else if (slot == 1) { - /* SATA */ - irq = IRQ_IOP32X_XINT2; - } else if (slot == 2) { - /* PCI-X Slot */ - irq = IRQ_IOP32X_XINT3; - } else if (slot == 3) { - /* 82546 GigE */ - irq = IRQ_IOP32X_XINT0; - } else { - printk(KERN_ERR "iq31244_pci_map_irq called for unknown " - "device PCI:%d:%d:%d\n", dev->bus->number, - PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn)); - irq = -1; - } - - return irq; -} - -static struct hw_pci iq31244_pci __initdata = { - .nr_controllers = 1, - .ops = &iop3xx_ops, - .setup = iop3xx_pci_setup, - .preinit = iop3xx_pci_preinit, - .map_irq = iq31244_pci_map_irq, -}; - -static int __init iq31244_pci_init(void) -{ - if (is_ep80219()) - pci_common_init(&ep80219_pci); - else if (machine_is_iq31244()) { - if (is_80219()) { - printk("note: iq31244 board type has been selected\n"); - printk("note: to select ep80219 operation:\n"); - printk("\t1/ specify \"force_ep80219\" on the kernel" - " command line\n"); - printk("\t2/ update boot loader to pass" - " the ep80219 id: %d\n", MACH_TYPE_EP80219); - } - pci_common_init(&iq31244_pci); - } - - return 0; -} - -subsys_initcall(iq31244_pci_init); - - -/* - * IQ31244 machine initialisation. - */ -static struct physmap_flash_data iq31244_flash_data = { - .width = 2, -}; - -static struct resource iq31244_flash_resource = { - .start = 0xf0000000, - .end = 0xf07fffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device iq31244_flash_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &iq31244_flash_data, - }, - .num_resources = 1, - .resource = &iq31244_flash_resource, -}; - -static struct plat_serial8250_port iq31244_serial_port[] = { - { - .mapbase = IQ31244_UART, - .membase = (char *)IQ31244_UART, - .irq = IRQ_IOP32X_XINT1, - .flags = UPF_SKIP_TEST, - .iotype = UPIO_MEM, - .regshift = 0, - .uartclk = 1843200, - }, - { }, -}; - -static struct resource iq31244_uart_resource = { - .start = IQ31244_UART, - .end = IQ31244_UART + 7, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device iq31244_serial_device = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = iq31244_serial_port, - }, - .num_resources = 1, - .resource = &iq31244_uart_resource, -}; - -/* - * This function will send a SHUTDOWN_COMPLETE message to the PIC - * controller over I2C. We are not using the i2c subsystem since - * we are going to power off and it may be removed - */ -void ep80219_power_off(void) -{ - /* - * Send the Address byte w/ the start condition - */ - *IOP3XX_IDBR1 = 0x60; - *IOP3XX_ICR1 = 0xE9; - mdelay(1); - - /* - * Send the START_MSG byte w/ no start or stop condition - */ - *IOP3XX_IDBR1 = 0x0F; - *IOP3XX_ICR1 = 0xE8; - mdelay(1); - - /* - * Send the SHUTDOWN_COMPLETE Message ID byte w/ no start or - * stop condition - */ - *IOP3XX_IDBR1 = 0x03; - *IOP3XX_ICR1 = 0xE8; - mdelay(1); - - /* - * Send an ignored byte w/ stop condition - */ - *IOP3XX_IDBR1 = 0x00; - *IOP3XX_ICR1 = 0xEA; - - while (1) - ; -} - -static void __init iq31244_init_machine(void) -{ - register_iop32x_gpio(); - gpiod_add_lookup_table(&iop3xx_i2c0_gpio_lookup); - gpiod_add_lookup_table(&iop3xx_i2c1_gpio_lookup); - platform_device_register(&iop3xx_i2c0_device); - platform_device_register(&iop3xx_i2c1_device); - platform_device_register(&iq31244_flash_device); - platform_device_register(&iq31244_serial_device); - platform_device_register(&iop3xx_dma_0_channel); - platform_device_register(&iop3xx_dma_1_channel); - - if (is_ep80219()) - pm_power_off = ep80219_power_off; - - if (!is_80219()) - platform_device_register(&iop3xx_aau_channel); -} - -static int __init force_ep80219_setup(char *str) -{ - force_ep80219 = 1; - return 1; -} - -__setup("force_ep80219", force_ep80219_setup); - -MACHINE_START(IQ31244, "Intel IQ31244") - /* Maintainer: Intel Corp. */ - .atag_offset = 0x100, - .map_io = iq31244_map_io, - .init_irq = iop32x_init_irq, - .init_time = iq31244_timer_init, - .init_machine = iq31244_init_machine, - .restart = iop3xx_restart, -MACHINE_END - -/* There should have been an ep80219 machine identifier from the beginning. - * Boot roms older than March 2007 do not know the ep80219 machine id. Pass - * "force_ep80219" on the kernel command line, otherwise iq31244 operation - * will be selected. - */ -MACHINE_START(EP80219, "Intel EP80219") - /* Maintainer: Intel Corp. */ - .atag_offset = 0x100, - .nr_irqs = IOP32X_NR_IRQS, - .map_io = iq31244_map_io, - .init_irq = iop32x_init_irq, - .init_time = iq31244_timer_init, - .init_machine = iq31244_init_machine, - .restart = iop3xx_restart, -MACHINE_END diff --git a/arch/arm/mach-iop32x/iq31244.h b/arch/arm/mach-iop32x/iq31244.h deleted file mode 100644 index a7ac691e48d3..000000000000 --- a/arch/arm/mach-iop32x/iq31244.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Intel IQ31244 evaluation board registers - */ - -#ifndef __IQ31244_H -#define __IQ31244_H - -#define IQ31244_UART 0xfe800000 /* UART #1 */ -#define IQ31244_7SEG_1 0xfe840000 /* 7-Segment MSB */ -#define IQ31244_7SEG_0 0xfe850000 /* 7-Segment LSB (WO) */ -#define IQ31244_ROTARY_SW 0xfe8d0000 /* Rotary Switch */ -#define IQ31244_BATT_STAT 0xfe8f0000 /* Battery Status */ - - -#endif diff --git a/arch/arm/mach-iop32x/iq80321.c b/arch/arm/mach-iop32x/iq80321.c deleted file mode 100644 index d9780c4660cb..000000000000 --- a/arch/arm/mach-iop32x/iq80321.c +++ /dev/null @@ -1,192 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * arch/arm/mach-iop32x/iq80321.c - * - * Board support code for the Intel IQ80321 platform. - * - * Author: Rory Bolt - * Copyright (C) 2002 Rory Bolt - * Copyright (C) 2004 Intel Corp. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "hardware.h" -#include "irqs.h" -#include "gpio-iop32x.h" - -/* - * IQ80321 timer tick configuration. - */ -static void __init iq80321_timer_init(void) -{ - /* 33.333 MHz crystal. */ - iop_init_time(200000000); -} - - -/* - * IQ80321 I/O. - */ -static struct map_desc iq80321_io_desc[] __initdata = { - { /* on-board devices */ - .virtual = IQ80321_UART, - .pfn = __phys_to_pfn(IQ80321_UART), - .length = 0x00100000, - .type = MT_DEVICE, - }, -}; - -void __init iq80321_map_io(void) -{ - iop3xx_map_io(); - iotable_init(iq80321_io_desc, ARRAY_SIZE(iq80321_io_desc)); -} - - -/* - * IQ80321 PCI. - */ -static int __init -iq80321_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - int irq; - - if ((slot == 2 || slot == 6) && pin == 1) { - /* PCI-X Slot INTA */ - irq = IRQ_IOP32X_XINT2; - } else if ((slot == 2 || slot == 6) && pin == 2) { - /* PCI-X Slot INTA */ - irq = IRQ_IOP32X_XINT3; - } else if ((slot == 2 || slot == 6) && pin == 3) { - /* PCI-X Slot INTA */ - irq = IRQ_IOP32X_XINT0; - } else if ((slot == 2 || slot == 6) && pin == 4) { - /* PCI-X Slot INTA */ - irq = IRQ_IOP32X_XINT1; - } else if (slot == 4 || slot == 8) { - /* Gig-E */ - irq = IRQ_IOP32X_XINT0; - } else { - printk(KERN_ERR "iq80321_pci_map_irq() called for unknown " - "device PCI:%d:%d:%d\n", dev->bus->number, - PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn)); - irq = -1; - } - - return irq; -} - -static struct hw_pci iq80321_pci __initdata = { - .nr_controllers = 1, - .ops = &iop3xx_ops, - .setup = iop3xx_pci_setup, - .preinit = iop3xx_pci_preinit_cond, - .map_irq = iq80321_pci_map_irq, -}; - -static int __init iq80321_pci_init(void) -{ - if ((iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) && - machine_is_iq80321()) - pci_common_init(&iq80321_pci); - - return 0; -} - -subsys_initcall(iq80321_pci_init); - - -/* - * IQ80321 machine initialisation. - */ -static struct physmap_flash_data iq80321_flash_data = { - .width = 1, -}; - -static struct resource iq80321_flash_resource = { - .start = 0xf0000000, - .end = 0xf07fffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device iq80321_flash_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &iq80321_flash_data, - }, - .num_resources = 1, - .resource = &iq80321_flash_resource, -}; - -static struct plat_serial8250_port iq80321_serial_port[] = { - { - .mapbase = IQ80321_UART, - .membase = (char *)IQ80321_UART, - .irq = IRQ_IOP32X_XINT1, - .flags = UPF_SKIP_TEST, - .iotype = UPIO_MEM, - .regshift = 0, - .uartclk = 1843200, - }, - { }, -}; - -static struct resource iq80321_uart_resource = { - .start = IQ80321_UART, - .end = IQ80321_UART + 7, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device iq80321_serial_device = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = iq80321_serial_port, - }, - .num_resources = 1, - .resource = &iq80321_uart_resource, -}; - -static void __init iq80321_init_machine(void) -{ - register_iop32x_gpio(); - gpiod_add_lookup_table(&iop3xx_i2c0_gpio_lookup); - gpiod_add_lookup_table(&iop3xx_i2c1_gpio_lookup); - platform_device_register(&iop3xx_i2c0_device); - platform_device_register(&iop3xx_i2c1_device); - platform_device_register(&iq80321_flash_device); - platform_device_register(&iq80321_serial_device); - platform_device_register(&iop3xx_dma_0_channel); - platform_device_register(&iop3xx_dma_1_channel); - platform_device_register(&iop3xx_aau_channel); -} - -MACHINE_START(IQ80321, "Intel IQ80321") - /* Maintainer: Intel Corp. */ - .atag_offset = 0x100, - .nr_irqs = IOP32X_NR_IRQS, - .map_io = iq80321_map_io, - .init_irq = iop32x_init_irq, - .init_time = iq80321_timer_init, - .init_machine = iq80321_init_machine, - .restart = iop3xx_restart, -MACHINE_END diff --git a/arch/arm/mach-iop32x/iq80321.h b/arch/arm/mach-iop32x/iq80321.h deleted file mode 100644 index 3a5d10626ea6..000000000000 --- a/arch/arm/mach-iop32x/iq80321.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Intel IQ80321 evaluation board registers - */ - -#ifndef __IQ80321_H -#define __IQ80321_H - -#define IQ80321_UART 0xfe800000 /* UART #1 */ -#define IQ80321_7SEG_1 0xfe840000 /* 7-Segment MSB */ -#define IQ80321_7SEG_0 0xfe850000 /* 7-Segment LSB (WO) */ -#define IQ80321_ROTARY_SW 0xfe8d0000 /* Rotary Switch */ -#define IQ80321_BATT_STAT 0xfe8f0000 /* Battery Status */ - - -#endif diff --git a/arch/arm/mach-iop32x/irq.c b/arch/arm/mach-iop32x/irq.c deleted file mode 100644 index 6dca7e97d81f..000000000000 --- a/arch/arm/mach-iop32x/irq.c +++ /dev/null @@ -1,95 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * arch/arm/mach-iop32x/irq.c - * - * Generic IOP32X IRQ handling functionality - * - * Author: Rory Bolt - * Copyright (C) 2002 Rory Bolt - */ - -#include -#include -#include -#include -#include -#include - -#include "hardware.h" - -static u32 iop32x_mask; - -static void intctl_write(u32 val) -{ - asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val)); -} - -static void intstr_write(u32 val) -{ - asm volatile("mcr p6, 0, %0, c4, c0, 0" : : "r" (val)); -} - -static u32 iintsrc_read(void) -{ - int irq; - - asm volatile("mrc p6, 0, %0, c8, c0, 0" : "=r" (irq)); - - return irq; -} - -static void -iop32x_irq_mask(struct irq_data *d) -{ - iop32x_mask &= ~(1 << (d->irq - 1)); - intctl_write(iop32x_mask); -} - -static void -iop32x_irq_unmask(struct irq_data *d) -{ - iop32x_mask |= 1 << (d->irq - 1); - intctl_write(iop32x_mask); -} - -struct irq_chip ext_chip = { - .name = "IOP32x", - .irq_ack = iop32x_irq_mask, - .irq_mask = iop32x_irq_mask, - .irq_unmask = iop32x_irq_unmask, -}; - -static void iop_handle_irq(struct pt_regs *regs) -{ - u32 mask; - - iop_enable_cp6(); - - do { - mask = iintsrc_read(); - if (mask) - generic_handle_irq(fls(mask)); - } while (mask); -} - -void __init iop32x_init_irq(void) -{ - int i; - - iop_init_cp6_handler(); - set_handle_irq(iop_handle_irq); - - intctl_write(0); - intstr_write(0); - if (machine_is_glantank() || - machine_is_iq80321() || - machine_is_iq31244() || - machine_is_n2100() || - machine_is_em7210()) - *IOP3XX_PCIIRSR = 0x0f; - - for (i = 1; i < NR_IRQS; i++) { - irq_set_chip_and_handler(i, &ext_chip, handle_level_irq); - irq_clear_status_flags(i, IRQ_NOREQUEST | IRQ_NOPROBE); - } -} diff --git a/arch/arm/mach-iop32x/irqs.h b/arch/arm/mach-iop32x/irqs.h deleted file mode 100644 index e9fc88e09189..000000000000 --- a/arch/arm/mach-iop32x/irqs.h +++ /dev/null @@ -1,48 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Author: Rory Bolt - * Copyright: (C) 2002 Rory Bolt - */ - -#ifndef __IOP32X_IRQS_H -#define __IOP32X_IRQS_H - -/* Interrupts in Linux start at 1, hardware starts at 0 */ - -#define IOP_IRQ(x) ((x) + 1) - -/* - * IOP80321 chipset interrupts - */ -#define IRQ_IOP32X_DMA0_EOT IOP_IRQ(0) -#define IRQ_IOP32X_DMA0_EOC IOP_IRQ(1) -#define IRQ_IOP32X_DMA1_EOT IOP_IRQ(2) -#define IRQ_IOP32X_DMA1_EOC IOP_IRQ(3) -#define IRQ_IOP32X_AA_EOT IOP_IRQ(6) -#define IRQ_IOP32X_AA_EOC IOP_IRQ(7) -#define IRQ_IOP32X_CORE_PMON IOP_IRQ(8) -#define IRQ_IOP32X_TIMER0 IOP_IRQ(9) -#define IRQ_IOP32X_TIMER1 IOP_IRQ(10) -#define IRQ_IOP32X_I2C_0 IOP_IRQ(11) -#define IRQ_IOP32X_I2C_1 IOP_IRQ(12) -#define IRQ_IOP32X_MESSAGING IOP_IRQ(13) -#define IRQ_IOP32X_ATU_BIST IOP_IRQ(14) -#define IRQ_IOP32X_PERFMON IOP_IRQ(15) -#define IRQ_IOP32X_CORE_PMU IOP_IRQ(16) -#define IRQ_IOP32X_BIU_ERR IOP_IRQ(17) -#define IRQ_IOP32X_ATU_ERR IOP_IRQ(18) -#define IRQ_IOP32X_MCU_ERR IOP_IRQ(19) -#define IRQ_IOP32X_DMA0_ERR IOP_IRQ(20) -#define IRQ_IOP32X_DMA1_ERR IOP_IRQ(21) -#define IRQ_IOP32X_AA_ERR IOP_IRQ(23) -#define IRQ_IOP32X_MSG_ERR IOP_IRQ(24) -#define IRQ_IOP32X_SSP IOP_IRQ(25) -#define IRQ_IOP32X_XINT0 IOP_IRQ(27) -#define IRQ_IOP32X_XINT1 IOP_IRQ(28) -#define IRQ_IOP32X_XINT2 IOP_IRQ(29) -#define IRQ_IOP32X_XINT3 IOP_IRQ(30) -#define IRQ_IOP32X_HPI IOP_IRQ(31) - -#define IOP32X_NR_IRQS (IRQ_IOP32X_HPI + 1) - -#endif diff --git a/arch/arm/mach-iop32x/n2100.c b/arch/arm/mach-iop32x/n2100.c deleted file mode 100644 index bb1e2e11bf35..000000000000 --- a/arch/arm/mach-iop32x/n2100.c +++ /dev/null @@ -1,367 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * arch/arm/mach-iop32x/n2100.c - * - * Board support code for the Thecus N2100 platform. - * - * Author: Rory Bolt - * Copyright (C) 2002 Rory Bolt - * Copyright 2003 (c) MontaVista, Software, Inc. - * Copyright (C) 2004 Intel Corp. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "hardware.h" -#include "irqs.h" -#include "gpio-iop32x.h" - -/* - * N2100 timer tick configuration. - */ -static void __init n2100_timer_init(void) -{ - /* 33.000 MHz crystal. */ - iop_init_time(198000000); -} - - -/* - * N2100 I/O. - */ -static struct map_desc n2100_io_desc[] __initdata = { - { /* on-board devices */ - .virtual = N2100_UART, - .pfn = __phys_to_pfn(N2100_UART), - .length = 0x00100000, - .type = MT_DEVICE - }, -}; - -void __init n2100_map_io(void) -{ - iop3xx_map_io(); - iotable_init(n2100_io_desc, ARRAY_SIZE(n2100_io_desc)); -} - - -/* - * N2100 PCI. - */ -static int n2100_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - int irq; - - if (PCI_SLOT(dev->devfn) == 1) { - /* RTL8110SB #1 */ - irq = IRQ_IOP32X_XINT0; - } else if (PCI_SLOT(dev->devfn) == 2) { - /* RTL8110SB #2 */ - irq = IRQ_IOP32X_XINT3; - } else if (PCI_SLOT(dev->devfn) == 3) { - /* Sil3512 */ - irq = IRQ_IOP32X_XINT2; - } else if (PCI_SLOT(dev->devfn) == 4 && pin == 1) { - /* VT6212 INTA */ - irq = IRQ_IOP32X_XINT1; - } else if (PCI_SLOT(dev->devfn) == 4 && pin == 2) { - /* VT6212 INTB */ - irq = IRQ_IOP32X_XINT0; - } else if (PCI_SLOT(dev->devfn) == 4 && pin == 3) { - /* VT6212 INTC */ - irq = IRQ_IOP32X_XINT2; - } else if (PCI_SLOT(dev->devfn) == 5) { - /* Mini-PCI slot */ - irq = IRQ_IOP32X_XINT3; - } else { - printk(KERN_ERR "n2100_pci_map_irq() called for unknown " - "device PCI:%d:%d:%d\n", dev->bus->number, - PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn)); - irq = -1; - } - - return irq; -} - -static struct hw_pci n2100_pci __initdata = { - .nr_controllers = 1, - .ops = &iop3xx_ops, - .setup = iop3xx_pci_setup, - .preinit = iop3xx_pci_preinit, - .map_irq = n2100_pci_map_irq, -}; - -/* - * Both r8169 chips on the n2100 exhibit PCI parity problems. Turn - * off parity reporting for both ports so we don't get error interrupts - * for them. - */ -static void n2100_fixup_r8169(struct pci_dev *dev) -{ - if (dev->bus->number == 0 && - (dev->devfn == PCI_DEVFN(1, 0) || - dev->devfn == PCI_DEVFN(2, 0))) - pci_disable_parity(dev); -} -DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK, PCI_ANY_ID, n2100_fixup_r8169); - -static int __init n2100_pci_init(void) -{ - if (machine_is_n2100()) - pci_common_init(&n2100_pci); - - return 0; -} - -subsys_initcall(n2100_pci_init); - - -/* - * N2100 machine initialisation. - */ -static struct physmap_flash_data n2100_flash_data = { - .width = 2, -}; - -static struct resource n2100_flash_resource = { - .start = 0xf0000000, - .end = 0xf0ffffff, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device n2100_flash_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &n2100_flash_data, - }, - .num_resources = 1, - .resource = &n2100_flash_resource, -}; - - -static struct plat_serial8250_port n2100_serial_port[] = { - { - .mapbase = N2100_UART, - .membase = (char *)N2100_UART, - .irq = 0, - .flags = UPF_SKIP_TEST | UPF_AUTO_IRQ | UPF_SHARE_IRQ, - .iotype = UPIO_MEM, - .regshift = 0, - .uartclk = 1843200, - }, - { }, -}; - -static struct resource n2100_uart_resource = { - .start = N2100_UART, - .end = N2100_UART + 7, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device n2100_serial_device = { - .name = "serial8250", - .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = n2100_serial_port, - }, - .num_resources = 1, - .resource = &n2100_uart_resource, -}; - -static struct f75375s_platform_data n2100_f75375s = { - .pwm = { 255, 255 }, - .pwm_enable = { 0, 0 }, -}; - -static struct pca9532_platform_data n2100_leds = { - .leds = { - { .name = "n2100:red:satafail0", - .state = PCA9532_OFF, - .type = PCA9532_TYPE_LED, - }, - { .name = "n2100:red:satafail1", - .state = PCA9532_OFF, - .type = PCA9532_TYPE_LED, - }, - { .name = "n2100:blue:usb", - .state = PCA9532_OFF, - .type = PCA9532_TYPE_LED, - }, - { .type = PCA9532_TYPE_NONE }, - - { .type = PCA9532_TYPE_NONE }, - { .type = PCA9532_TYPE_NONE }, - { .type = PCA9532_TYPE_NONE }, - { .name = "n2100:red:usb", - .state = PCA9532_OFF, - .type = PCA9532_TYPE_LED, - }, - - { .type = PCA9532_TYPE_NONE }, /* power OFF gpio */ - { .type = PCA9532_TYPE_NONE }, /* reset gpio */ - { .type = PCA9532_TYPE_NONE }, - { .type = PCA9532_TYPE_NONE }, - - { .type = PCA9532_TYPE_NONE }, - { .name = "n2100:orange:system", - .state = PCA9532_OFF, - .type = PCA9532_TYPE_LED, - }, - { .name = "n2100:red:system", - .state = PCA9532_OFF, - .type = PCA9532_TYPE_LED, - }, - { .name = "N2100 beeper" , - .state = PCA9532_OFF, - .type = PCA9532_TYPE_N2100_BEEP, - }, - }, - .psc = { 0, 0 }, - .pwm = { 0, 0 }, -}; - -static struct i2c_board_info __initdata n2100_i2c_devices[] = { - { - I2C_BOARD_INFO("rs5c372b", 0x32), - }, - { - I2C_BOARD_INFO("f75375", 0x2e), - .platform_data = &n2100_f75375s, - }, - { - I2C_BOARD_INFO("pca9532", 0x60), - .platform_data = &n2100_leds, - }, -}; - -/* - * Pull PCA9532 GPIO #8 low to power off the machine. - */ -static void n2100_power_off(void) -{ - local_irq_disable(); - - /* Start condition, I2C address of PCA9532, write transaction. */ - *IOP3XX_IDBR0 = 0xc0; - *IOP3XX_ICR0 = 0xe9; - mdelay(1); - - /* Write address 0x08. */ - *IOP3XX_IDBR0 = 0x08; - *IOP3XX_ICR0 = 0xe8; - mdelay(1); - - /* Write data 0x01, stop condition. */ - *IOP3XX_IDBR0 = 0x01; - *IOP3XX_ICR0 = 0xea; - - while (1) - ; -} - -static void n2100_restart(enum reboot_mode mode, const char *cmd) -{ - int ret; - - ret = gpio_direction_output(N2100_HARDWARE_RESET, 0); - if (ret) { - pr_crit("could not drive reset GPIO low\n"); - return; - } - /* Wait for reset to happen */ - while (1) - ; -} - - -static struct timer_list power_button_poll_timer; - -static void power_button_poll(struct timer_list *unused) -{ - if (gpio_get_value(N2100_POWER_BUTTON) == 0) { - ctrl_alt_del(); - return; - } - - power_button_poll_timer.expires = jiffies + (HZ / 10); - add_timer(&power_button_poll_timer); -} - -static int __init n2100_request_gpios(void) -{ - int ret; - - if (!machine_is_n2100()) - return 0; - - ret = gpio_request(N2100_HARDWARE_RESET, "reset"); - if (ret) - pr_err("could not request reset GPIO\n"); - - ret = gpio_request(N2100_POWER_BUTTON, "power"); - if (ret) - pr_err("could not request power GPIO\n"); - else { - ret = gpio_direction_input(N2100_POWER_BUTTON); - if (ret) - pr_err("could not set power GPIO as input\n"); - } - /* Set up power button poll timer */ - timer_setup(&power_button_poll_timer, power_button_poll, 0); - power_button_poll_timer.expires = jiffies + (HZ / 10); - add_timer(&power_button_poll_timer); - return 0; -} -device_initcall(n2100_request_gpios); - -static void __init n2100_init_machine(void) -{ - register_iop32x_gpio(); - gpiod_add_lookup_table(&iop3xx_i2c0_gpio_lookup); - platform_device_register(&iop3xx_i2c0_device); - platform_device_register(&n2100_flash_device); - platform_device_register(&n2100_serial_device); - platform_device_register(&iop3xx_dma_0_channel); - platform_device_register(&iop3xx_dma_1_channel); - - i2c_register_board_info(0, n2100_i2c_devices, - ARRAY_SIZE(n2100_i2c_devices)); - - pm_power_off = n2100_power_off; -} - -MACHINE_START(N2100, "Thecus N2100") - /* Maintainer: Lennert Buytenhek */ - .atag_offset = 0x100, - .nr_irqs = IOP32X_NR_IRQS, - .map_io = n2100_map_io, - .init_irq = iop32x_init_irq, - .init_time = n2100_timer_init, - .init_machine = n2100_init_machine, - .restart = n2100_restart, -MACHINE_END diff --git a/arch/arm/mach-iop32x/n2100.h b/arch/arm/mach-iop32x/n2100.h deleted file mode 100644 index 0b97b940d3e7..000000000000 --- a/arch/arm/mach-iop32x/n2100.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Thecus N2100 board registers - */ - -#ifndef __N2100_H -#define __N2100_H - -#define N2100_UART 0xfe800000 /* UART */ - -#define N2100_COPY_BUTTON IOP3XX_GPIO_LINE(0) -#define N2100_PCA9532_RESET IOP3XX_GPIO_LINE(2) -#define N2100_RESET_BUTTON IOP3XX_GPIO_LINE(3) -#define N2100_HARDWARE_RESET IOP3XX_GPIO_LINE(4) -#define N2100_POWER_BUTTON IOP3XX_GPIO_LINE(5) - - -#endif diff --git a/arch/arm/mach-iop32x/pci.c b/arch/arm/mach-iop32x/pci.c deleted file mode 100644 index 7a215d2ee7e2..000000000000 --- a/arch/arm/mach-iop32x/pci.c +++ /dev/null @@ -1,404 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * arch/arm/plat-iop/pci.c - * - * PCI support for the Intel IOP32X and IOP33X processors - * - * Author: Rory Bolt - * Copyright (C) 2002 Rory Bolt - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "hardware.h" -#include "iop3xx.h" - -// #define DEBUG - -#ifdef DEBUG -#define DBG(x...) printk(x) -#else -#define DBG(x...) do { } while (0) -#endif - -/* - * This routine builds either a type0 or type1 configuration command. If the - * bus is on the 803xx then a type0 made, else a type1 is created. - */ -static u32 iop3xx_cfg_address(struct pci_bus *bus, int devfn, int where) -{ - struct pci_sys_data *sys = bus->sysdata; - u32 addr; - - if (sys->busnr == bus->number) - addr = 1 << (PCI_SLOT(devfn) + 16) | (PCI_SLOT(devfn) << 11); - else - addr = bus->number << 16 | PCI_SLOT(devfn) << 11 | 1; - - addr |= PCI_FUNC(devfn) << 8 | (where & ~3); - - return addr; -} - -/* - * This routine checks the status of the last configuration cycle. If an error - * was detected it returns a 1, else it returns a 0. The errors being checked - * are parity, master abort, target abort (master and target). These types of - * errors occur during a config cycle where there is no device, like during - * the discovery stage. - */ -static int iop3xx_pci_status(void) -{ - unsigned int status; - int ret = 0; - - /* - * Check the status registers. - */ - status = *IOP3XX_ATUSR; - if (status & 0xf900) { - DBG("\t\t\tPCI: P0 - status = 0x%08x\n", status); - *IOP3XX_ATUSR = status & 0xf900; - ret = 1; - } - - status = *IOP3XX_ATUISR; - if (status & 0x679f) { - DBG("\t\t\tPCI: P1 - status = 0x%08x\n", status); - *IOP3XX_ATUISR = status & 0x679f; - ret = 1; - } - - return ret; -} - -/* - * Simply write the address register and read the configuration - * data. Note that the 4 nops ensure that we are able to handle - * a delayed abort (in theory.) - */ -static u32 iop3xx_read(unsigned long addr) -{ - u32 val; - - __asm__ __volatile__( - "str %1, [%2]\n\t" - "ldr %0, [%3]\n\t" - "nop\n\t" - "nop\n\t" - "nop\n\t" - "nop\n\t" - : "=r" (val) - : "r" (addr), "r" (IOP3XX_OCCAR), "r" (IOP3XX_OCCDR)); - - return val; -} - -/* - * The read routines must check the error status of the last configuration - * cycle. If there was an error, the routine returns all hex f's. - */ -static int -iop3xx_read_config(struct pci_bus *bus, unsigned int devfn, int where, - int size, u32 *value) -{ - unsigned long addr = iop3xx_cfg_address(bus, devfn, where); - u32 val = iop3xx_read(addr) >> ((where & 3) * 8); - - if (iop3xx_pci_status()) - val = 0xffffffff; - - *value = val; - - return PCIBIOS_SUCCESSFUL; -} - -static int -iop3xx_write_config(struct pci_bus *bus, unsigned int devfn, int where, - int size, u32 value) -{ - unsigned long addr = iop3xx_cfg_address(bus, devfn, where); - u32 val; - - if (size != 4) { - val = iop3xx_read(addr); - if (iop3xx_pci_status()) - return PCIBIOS_SUCCESSFUL; - - where = (where & 3) * 8; - - if (size == 1) - val &= ~(0xff << where); - else - val &= ~(0xffff << where); - - *IOP3XX_OCCDR = val | value << where; - } else { - asm volatile( - "str %1, [%2]\n\t" - "str %0, [%3]\n\t" - "nop\n\t" - "nop\n\t" - "nop\n\t" - "nop\n\t" - : - : "r" (value), "r" (addr), - "r" (IOP3XX_OCCAR), "r" (IOP3XX_OCCDR)); - } - - return PCIBIOS_SUCCESSFUL; -} - -struct pci_ops iop3xx_ops = { - .read = iop3xx_read_config, - .write = iop3xx_write_config, -}; - -/* - * When a PCI device does not exist during config cycles, the 80200 gets a - * bus error instead of returning 0xffffffff. This handler simply returns. - */ -static int -iop3xx_pci_abort(unsigned long addr, unsigned int fsr, struct pt_regs *regs) -{ - DBG("PCI abort: address = 0x%08lx fsr = 0x%03x PC = 0x%08lx LR = 0x%08lx\n", - addr, fsr, regs->ARM_pc, regs->ARM_lr); - - /* - * If it was an imprecise abort, then we need to correct the - * return address to be _after_ the instruction. - */ - if (fsr & (1 << 10)) - regs->ARM_pc += 4; - - return 0; -} - -int iop3xx_pci_setup(int nr, struct pci_sys_data *sys) -{ - struct resource *res; - struct resource realio; - - if (nr != 0) - return 0; - - res = kzalloc(sizeof(struct resource), GFP_KERNEL); - if (!res) - panic("PCI: unable to alloc resources"); - - res->start = IOP3XX_PCI_LOWER_MEM_PA; - res->end = IOP3XX_PCI_LOWER_MEM_PA + IOP3XX_PCI_MEM_WINDOW_SIZE - 1; - res->name = "IOP3XX PCI Memory Space"; - res->flags = IORESOURCE_MEM; - request_resource(&iomem_resource, res); - - /* - * Use whatever translation is already setup. - */ - sys->mem_offset = IOP3XX_PCI_LOWER_MEM_PA - *IOP3XX_OMWTVR0; - - pci_add_resource_offset(&sys->resources, res, sys->mem_offset); - - realio.start = 0; - realio.end = realio.start + SZ_64K - 1; - pci_remap_iospace(&realio, IOP3XX_PCI_LOWER_IO_PA); - - return 1; -} - -void __init iop3xx_atu_setup(void) -{ - /* BAR 0 ( Disabled ) */ - *IOP3XX_IAUBAR0 = 0x0; - *IOP3XX_IABAR0 = 0x0; - *IOP3XX_IATVR0 = 0x0; - *IOP3XX_IALR0 = 0x0; - - /* BAR 1 ( Disabled ) */ - *IOP3XX_IAUBAR1 = 0x0; - *IOP3XX_IABAR1 = 0x0; - *IOP3XX_IALR1 = 0x0; - - /* BAR 2 (1:1 mapping with Physical RAM) */ - /* Set limit and enable */ - *IOP3XX_IALR2 = ~((u32)IOP3XX_MAX_RAM_SIZE - 1) & ~0x1; - *IOP3XX_IAUBAR2 = 0x0; - - /* Align the inbound bar with the base of memory */ - *IOP3XX_IABAR2 = PHYS_OFFSET | - PCI_BASE_ADDRESS_MEM_TYPE_64 | - PCI_BASE_ADDRESS_MEM_PREFETCH; - - *IOP3XX_IATVR2 = PHYS_OFFSET; - - /* Outbound window 0 */ - *IOP3XX_OMWTVR0 = IOP3XX_PCI_LOWER_MEM_BA; - *IOP3XX_OUMWTVR0 = 0; - - /* Outbound window 1 */ - *IOP3XX_OMWTVR1 = IOP3XX_PCI_LOWER_MEM_BA + - IOP3XX_PCI_MEM_WINDOW_SIZE / 2; - *IOP3XX_OUMWTVR1 = 0; - - /* BAR 3 ( Disabled ) */ - *IOP3XX_IAUBAR3 = 0x0; - *IOP3XX_IABAR3 = 0x0; - *IOP3XX_IATVR3 = 0x0; - *IOP3XX_IALR3 = 0x0; - - /* Setup the I/O Bar - */ - *IOP3XX_OIOWTVR = IOP3XX_PCI_LOWER_IO_BA; - - /* Enable inbound and outbound cycles - */ - *IOP3XX_ATUCMD |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | - PCI_COMMAND_PARITY | PCI_COMMAND_SERR; - *IOP3XX_ATUCR |= IOP3XX_ATUCR_OUT_EN; -} - -void __init iop3xx_atu_disable(void) -{ - *IOP3XX_ATUCMD = 0; - *IOP3XX_ATUCR = 0; - - /* wait for cycles to quiesce */ - while (*IOP3XX_PCSR & (IOP3XX_PCSR_OUT_Q_BUSY | - IOP3XX_PCSR_IN_Q_BUSY)) - cpu_relax(); - - /* BAR 0 ( Disabled ) */ - *IOP3XX_IAUBAR0 = 0x0; - *IOP3XX_IABAR0 = 0x0; - *IOP3XX_IATVR0 = 0x0; - *IOP3XX_IALR0 = 0x0; - - /* BAR 1 ( Disabled ) */ - *IOP3XX_IAUBAR1 = 0x0; - *IOP3XX_IABAR1 = 0x0; - *IOP3XX_IALR1 = 0x0; - - /* BAR 2 ( Disabled ) */ - *IOP3XX_IAUBAR2 = 0x0; - *IOP3XX_IABAR2 = 0x0; - *IOP3XX_IATVR2 = 0x0; - *IOP3XX_IALR2 = 0x0; - - /* BAR 3 ( Disabled ) */ - *IOP3XX_IAUBAR3 = 0x0; - *IOP3XX_IABAR3 = 0x0; - *IOP3XX_IATVR3 = 0x0; - *IOP3XX_IALR3 = 0x0; - - /* Clear the outbound windows */ - *IOP3XX_OIOWTVR = 0; - - /* Outbound window 0 */ - *IOP3XX_OMWTVR0 = 0; - *IOP3XX_OUMWTVR0 = 0; - - /* Outbound window 1 */ - *IOP3XX_OMWTVR1 = 0; - *IOP3XX_OUMWTVR1 = 0; -} - -/* Flag to determine whether the ATU is initialized and the PCI bus scanned */ -int init_atu; - -int iop3xx_get_init_atu(void) { - /* check if default has been overridden */ - if (init_atu != IOP3XX_INIT_ATU_DEFAULT) - return init_atu; - else - return IOP3XX_INIT_ATU_DISABLE; -} - -static void __init iop3xx_atu_debug(void) -{ - DBG("PCI: Intel IOP3xx PCI init.\n"); - DBG("PCI: Outbound memory window 0: PCI 0x%08x%08x\n", - *IOP3XX_OUMWTVR0, *IOP3XX_OMWTVR0); - DBG("PCI: Outbound memory window 1: PCI 0x%08x%08x\n", - *IOP3XX_OUMWTVR1, *IOP3XX_OMWTVR1); - DBG("PCI: Outbound IO window: PCI 0x%08x\n", - *IOP3XX_OIOWTVR); - - DBG("PCI: Inbound memory window 0: PCI 0x%08x%08x 0x%08x -> 0x%08x\n", - *IOP3XX_IAUBAR0, *IOP3XX_IABAR0, *IOP3XX_IALR0, *IOP3XX_IATVR0); - DBG("PCI: Inbound memory window 1: PCI 0x%08x%08x 0x%08x\n", - *IOP3XX_IAUBAR1, *IOP3XX_IABAR1, *IOP3XX_IALR1); - DBG("PCI: Inbound memory window 2: PCI 0x%08x%08x 0x%08x -> 0x%08x\n", - *IOP3XX_IAUBAR2, *IOP3XX_IABAR2, *IOP3XX_IALR2, *IOP3XX_IATVR2); - DBG("PCI: Inbound memory window 3: PCI 0x%08x%08x 0x%08x -> 0x%08x\n", - *IOP3XX_IAUBAR3, *IOP3XX_IABAR3, *IOP3XX_IALR3, *IOP3XX_IATVR3); - - DBG("PCI: Expansion ROM window: PCI 0x%08x%08x 0x%08x -> 0x%08x\n", - 0, *IOP3XX_ERBAR, *IOP3XX_ERLR, *IOP3XX_ERTVR); - - DBG("ATU: IOP3XX_ATUCMD=0x%04x\n", *IOP3XX_ATUCMD); - DBG("ATU: IOP3XX_ATUCR=0x%08x\n", *IOP3XX_ATUCR); - - hook_fault_code(16+6, iop3xx_pci_abort, SIGBUS, 0, "imprecise external abort"); -} - -/* for platforms that might be host-bus-adapters */ -void __init iop3xx_pci_preinit_cond(void) -{ - if (iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) { - iop3xx_atu_disable(); - iop3xx_atu_setup(); - iop3xx_atu_debug(); - } -} - -void __init iop3xx_pci_preinit(void) -{ - pcibios_min_mem = 0; - - iop3xx_atu_disable(); - iop3xx_atu_setup(); - iop3xx_atu_debug(); -} - -/* allow init_atu to be user overridden */ -static int __init iop3xx_init_atu_setup(char *str) -{ - init_atu = IOP3XX_INIT_ATU_DEFAULT; - if (str) { - while (*str != '\0') { - switch (*str) { - case 'y': - case 'Y': - init_atu = IOP3XX_INIT_ATU_ENABLE; - break; - case 'n': - case 'N': - init_atu = IOP3XX_INIT_ATU_DISABLE; - break; - case ',': - case '=': - break; - default: - printk(KERN_DEBUG "\"%s\" malformed at " - "character: \'%c\'", - __func__, - *str); - *(str + 1) = '\0'; - } - str++; - } - } - - return 1; -} - -__setup("iop3xx_init_atu", iop3xx_init_atu_setup); - diff --git a/arch/arm/mach-iop32x/pmu.c b/arch/arm/mach-iop32x/pmu.c deleted file mode 100644 index bdbc7a3cb8a3..000000000000 --- a/arch/arm/mach-iop32x/pmu.c +++ /dev/null @@ -1,29 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * PMU IRQ registration for the iop3xx xscale PMU families. - * Copyright (C) 2010 Will Deacon, ARM Ltd. - */ - -#include -#include "irqs.h" - -static struct resource pmu_resource = { - .start = IRQ_IOP32X_CORE_PMU, - .end = IRQ_IOP32X_CORE_PMU, - .flags = IORESOURCE_IRQ, -}; - -static struct platform_device pmu_device = { - .name = "xscale-pmu", - .id = -1, - .resource = &pmu_resource, - .num_resources = 1, -}; - -static int __init iop3xx_pmu_init(void) -{ - platform_device_register(&pmu_device); - return 0; -} - -arch_initcall(iop3xx_pmu_init); diff --git a/arch/arm/mach-iop32x/restart.c b/arch/arm/mach-iop32x/restart.c deleted file mode 100644 index 3dfa54d3a7a8..000000000000 --- a/arch/arm/mach-iop32x/restart.c +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * restart.c - * - * Copyright (C) 2001 MontaVista Software, Inc. - */ -#include -#include "hardware.h" -#include "iop3xx.h" - -void iop3xx_restart(enum reboot_mode mode, const char *cmd) -{ - *IOP3XX_PCSR = 0x30; - - /* Jump into ROM at address 0 */ - soft_restart(0); -} diff --git a/arch/arm/mach-iop32x/setup.c b/arch/arm/mach-iop32x/setup.c deleted file mode 100644 index a0a81c28a632..000000000000 --- a/arch/arm/mach-iop32x/setup.c +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * arch/arm/plat-iop/setup.c - * - * Author: Nicolas Pitre - * Copyright (C) 2001 MontaVista Software, Inc. - * Copyright (C) 2004 Intel Corporation. - */ - -#include -#include -#include -#include "iop3xx.h" - -/* - * Standard IO mapping for all IOP3xx based systems. Note that - * the IOP3xx OCCDR must be mapped uncached and unbuffered. - */ -static struct map_desc iop3xx_std_desc[] __initdata = { - { /* mem mapped registers */ - .virtual = IOP3XX_PERIPHERAL_VIRT_BASE, - .pfn = __phys_to_pfn(IOP3XX_PERIPHERAL_PHYS_BASE), - .length = IOP3XX_PERIPHERAL_SIZE, - .type = MT_UNCACHED, - }, -}; - -void __init iop3xx_map_io(void) -{ - iotable_init(iop3xx_std_desc, ARRAY_SIZE(iop3xx_std_desc)); -} diff --git a/arch/arm/mach-iop32x/time.c b/arch/arm/mach-iop32x/time.c deleted file mode 100644 index ae533b66fefd..000000000000 --- a/arch/arm/mach-iop32x/time.c +++ /dev/null @@ -1,179 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * arch/arm/plat-iop/time.c - * - * Timer code for IOP32x and IOP33x based systems - * - * Author: Deepak Saxena - * - * Copyright 2002-2003 MontaVista Software Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "hardware.h" -#include "irqs.h" - -/* - * Minimum clocksource/clockevent timer range in seconds - */ -#define IOP_MIN_RANGE 4 - -/* - * IOP clocksource (free-running timer 1). - */ -static u64 notrace iop_clocksource_read(struct clocksource *unused) -{ - return 0xffffffffu - read_tcr1(); -} - -static struct clocksource iop_clocksource = { - .name = "iop_timer1", - .rating = 300, - .read = iop_clocksource_read, - .mask = CLOCKSOURCE_MASK(32), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, -}; - -/* - * IOP sched_clock() implementation via its clocksource. - */ -static u64 notrace iop_read_sched_clock(void) -{ - return 0xffffffffu - read_tcr1(); -} - -/* - * IOP clockevents (interrupting timer 0). - */ -static int iop_set_next_event(unsigned long delta, - struct clock_event_device *unused) -{ - u32 tmr = IOP_TMR_PRIVILEGED | IOP_TMR_RATIO_1_1; - - BUG_ON(delta == 0); - write_tmr0(tmr & ~(IOP_TMR_EN | IOP_TMR_RELOAD)); - write_tcr0(delta); - write_tmr0((tmr & ~IOP_TMR_RELOAD) | IOP_TMR_EN); - - return 0; -} - -static unsigned long ticks_per_jiffy; - -static int iop_set_periodic(struct clock_event_device *evt) -{ - u32 tmr = read_tmr0(); - - write_tmr0(tmr & ~IOP_TMR_EN); - write_tcr0(ticks_per_jiffy - 1); - write_trr0(ticks_per_jiffy - 1); - tmr |= (IOP_TMR_RELOAD | IOP_TMR_EN); - - write_tmr0(tmr); - return 0; -} - -static int iop_set_oneshot(struct clock_event_device *evt) -{ - u32 tmr = read_tmr0(); - - /* ->set_next_event sets period and enables timer */ - tmr &= ~(IOP_TMR_RELOAD | IOP_TMR_EN); - write_tmr0(tmr); - return 0; -} - -static int iop_shutdown(struct clock_event_device *evt) -{ - u32 tmr = read_tmr0(); - - tmr &= ~IOP_TMR_EN; - write_tmr0(tmr); - return 0; -} - -static int iop_resume(struct clock_event_device *evt) -{ - u32 tmr = read_tmr0(); - - tmr |= IOP_TMR_EN; - write_tmr0(tmr); - return 0; -} - -static struct clock_event_device iop_clockevent = { - .name = "iop_timer0", - .features = CLOCK_EVT_FEAT_PERIODIC | - CLOCK_EVT_FEAT_ONESHOT, - .rating = 300, - .set_next_event = iop_set_next_event, - .set_state_shutdown = iop_shutdown, - .set_state_periodic = iop_set_periodic, - .tick_resume = iop_resume, - .set_state_oneshot = iop_set_oneshot, -}; - -static irqreturn_t -iop_timer_interrupt(int irq, void *dev_id) -{ - struct clock_event_device *evt = dev_id; - - write_tisr(1); - evt->event_handler(evt); - return IRQ_HANDLED; -} - -static unsigned long iop_tick_rate; -unsigned long get_iop_tick_rate(void) -{ - return iop_tick_rate; -} -EXPORT_SYMBOL(get_iop_tick_rate); - -void __init iop_init_time(unsigned long tick_rate) -{ - u32 timer_ctl; - int irq = IRQ_IOP32X_TIMER0; - - sched_clock_register(iop_read_sched_clock, 32, tick_rate); - - ticks_per_jiffy = DIV_ROUND_CLOSEST(tick_rate, HZ); - iop_tick_rate = tick_rate; - - timer_ctl = IOP_TMR_EN | IOP_TMR_PRIVILEGED | - IOP_TMR_RELOAD | IOP_TMR_RATIO_1_1; - - /* - * Set up interrupting clockevent timer 0. - */ - write_tmr0(timer_ctl & ~IOP_TMR_EN); - write_tisr(1); - if (request_irq(irq, iop_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL, - "IOP Timer Tick", &iop_clockevent)) - pr_err("Failed to request irq() %d (IOP Timer Tick)\n", irq); - iop_clockevent.cpumask = cpumask_of(0); - clockevents_config_and_register(&iop_clockevent, tick_rate, - 0xf, 0xfffffffe); - - /* - * Set up free-running clocksource timer 1. - */ - write_trr1(0xffffffff); - write_tcr1(0xffffffff); - write_tmr1(timer_ctl); - clocksource_register_hz(&iop_clocksource, tick_rate); -} diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index 264e780ae32e..e488e1b8e803 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -723,11 +723,11 @@ config I2C_IMX_LPI2C will be called i2c-imx-lpi2c. config I2C_IOP3XX - tristate "Intel IOPx3xx and IXP4xx on-chip I2C interface" - depends on ARCH_IOP32X || ARCH_IXP4XX || COMPILE_TEST + tristate "Intel IXP4xx on-chip I2C interface" + depends on ARCH_IXP4XX || COMPILE_TEST help Say Y here if you want to use the IIC bus controller on - the Intel IOPx3xx I/O Processors or IXP4xx Network Processors. + the Intel IXP4xx Network Processors. This driver can also be built as a module. If so, the module will be called i2c-iop3xx. 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id qf33-20020a1709077f2100b00781bbff1cc1si16192553ejc.455.2022.10.19.08.23.05; Wed, 19 Oct 2022 08:23:33 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=ejD8zL28; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231765AbiJSPW2 (ORCPT + 99 others); Wed, 19 Oct 2022 11:22:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42292 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232452AbiJSPWC (ORCPT ); Wed, 19 Oct 2022 11:22:02 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2A4A51958EA; Wed, 19 Oct 2022 08:15:19 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id F3D0EB81BFB; Wed, 19 Oct 2022 15:13:51 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id DE44DC433D6; Wed, 19 Oct 2022 15:13:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1666192430; bh=VR3NeTBhBtEAIHhHholn1Yrc2xFwDESTvjvXXcZ5ooE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ejD8zL282tR+g0J0OzgNjBtMHkJRCeBEgRk27/7vAix9hZSti1sKvhGOYYtC5yDTg KUR96fHTYqv7ICVCAa2zdPQVjmlcoPtv2OE4W6Yruw4W3JCEKFgz+ffNkN8pFWkzvI upsE9FPdJmirq4kukaidRRGWszc8AjVNez79tvz6w+g536tpXXcW8eYfQUgAkDa0WB qBvlnG7v6s8fsbs9ZC5b0oaVbVjsyzNmMM0j6S/YKlATr9MROSwwGnLRA7dtuTp9TC MEsbfVYLgnY7xPuNzDEKgWq2wu/tvyMWOljCX2PKw5LtrGQGJ1K8on2otNa28MuCqz zdXfvPotknzXQ== From: Arnd Bergmann To: linux-arm-kernel@lists.infradead.org, Vinod Koul Cc: linux-kernel@vger.kernel.org, Arnd Bergmann , Dan Williams , dmaengine@vger.kernel.org Subject: [PATCH 10/17] dmaengine: remove iop-adma driver Date: Wed, 19 Oct 2022 17:03:32 +0200 Message-Id: <20221019150410.3851944-10-arnd@kernel.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20221019150410.3851944-1-arnd@kernel.org> References: <20221019144119.3848027-1-arnd@kernel.org> <20221019150410.3851944-1-arnd@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747130004990958758?= X-GMAIL-MSGID: =?utf-8?q?1747130004990958758?= From: Arnd Bergmann The iop32x platform was removed, so this driver is no longer needed. Cc: Dan Williams Signed-off-by: Arnd Bergmann Acked-by: Dan Williams --- drivers/dma/Kconfig | 8 - drivers/dma/Makefile | 1 - drivers/dma/iop-adma.c | 1554 ---------------------------------------- drivers/dma/iop-adma.h | 914 ----------------------- 4 files changed, 2477 deletions(-) delete mode 100644 drivers/dma/iop-adma.c delete mode 100644 drivers/dma/iop-adma.h diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index 7524b62a8870..b73fc89ba877 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -357,14 +357,6 @@ config INTEL_IOATDMA If unsure, say N. -config INTEL_IOP_ADMA - tristate "Intel IOP32x ADMA support" - depends on ARCH_IOP32X || COMPILE_TEST - select DMA_ENGINE - select ASYNC_TX_ENABLE_CHANNEL_SWITCH - help - Enable support for the Intel(R) IOP Series RAID engines. - config K3_DMA tristate "Hisilicon K3 DMA support" depends on ARCH_HI3xxx || ARCH_HISI || COMPILE_TEST diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index 10f7d4241001..5b55ada052a7 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -44,7 +44,6 @@ obj-$(CONFIG_IMX_SDMA) += imx-sdma.o obj-$(CONFIG_INTEL_IDMA64) += idma64.o obj-$(CONFIG_INTEL_IOATDMA) += ioat/ obj-y += idxd/ -obj-$(CONFIG_INTEL_IOP_ADMA) += iop-adma.o obj-$(CONFIG_K3_DMA) += k3dma.o obj-$(CONFIG_LPC18XX_DMAMUX) += lpc18xx-dmamux.o obj-$(CONFIG_MILBEAUT_HDMAC) += milbeaut-hdmac.o diff --git a/drivers/dma/iop-adma.c b/drivers/dma/iop-adma.c deleted file mode 100644 index 310b899d581f..000000000000 --- a/drivers/dma/iop-adma.c +++ /dev/null @@ -1,1554 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * offload engine driver for the Intel Xscale series of i/o processors - * Copyright © 2006, Intel Corporation. - */ - -/* - * This driver supports the asynchrounous DMA copy and RAID engines available - * on the Intel Xscale(R) family of I/O Processors (IOP 32x, 33x, 134x) - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "iop-adma.h" -#include "dmaengine.h" - -#define to_iop_adma_chan(chan) container_of(chan, struct iop_adma_chan, common) -#define to_iop_adma_device(dev) \ - container_of(dev, struct iop_adma_device, common) -#define tx_to_iop_adma_slot(tx) \ - container_of(tx, struct iop_adma_desc_slot, async_tx) - -/** - * iop_adma_free_slots - flags descriptor slots for reuse - * @slot: Slot to free - * Caller must hold &iop_chan->lock while calling this function - */ -static void iop_adma_free_slots(struct iop_adma_desc_slot *slot) -{ - int stride = slot->slots_per_op; - - while (stride--) { - slot->slots_per_op = 0; - slot = list_entry(slot->slot_node.next, - struct iop_adma_desc_slot, - slot_node); - } -} - -static dma_cookie_t -iop_adma_run_tx_complete_actions(struct iop_adma_desc_slot *desc, - struct iop_adma_chan *iop_chan, dma_cookie_t cookie) -{ - struct dma_async_tx_descriptor *tx = &desc->async_tx; - - BUG_ON(tx->cookie < 0); - if (tx->cookie > 0) { - cookie = tx->cookie; - tx->cookie = 0; - - /* call the callback (must not sleep or submit new - * operations to this channel) - */ - dmaengine_desc_get_callback_invoke(tx, NULL); - - dma_descriptor_unmap(tx); - if (desc->group_head) - desc->group_head = NULL; - } - - /* run dependent operations */ - dma_run_dependencies(tx); - - return cookie; -} - -static int -iop_adma_clean_slot(struct iop_adma_desc_slot *desc, - struct iop_adma_chan *iop_chan) -{ - /* the client is allowed to attach dependent operations - * until 'ack' is set - */ - if (!async_tx_test_ack(&desc->async_tx)) - return 0; - - /* leave the last descriptor in the chain - * so we can append to it - */ - if (desc->chain_node.next == &iop_chan->chain) - return 1; - - dev_dbg(iop_chan->device->common.dev, - "\tfree slot: %d slots_per_op: %d\n", - desc->idx, desc->slots_per_op); - - list_del(&desc->chain_node); - iop_adma_free_slots(desc); - - return 0; -} - -static void __iop_adma_slot_cleanup(struct iop_adma_chan *iop_chan) -{ - struct iop_adma_desc_slot *iter, *_iter, *grp_start = NULL; - dma_cookie_t cookie = 0; - u32 current_desc = iop_chan_get_current_descriptor(iop_chan); - int busy = iop_chan_is_busy(iop_chan); - int seen_current = 0, slot_cnt = 0, slots_per_op = 0; - - dev_dbg(iop_chan->device->common.dev, "%s\n", __func__); - /* free completed slots from the chain starting with - * the oldest descriptor - */ - list_for_each_entry_safe(iter, _iter, &iop_chan->chain, - chain_node) { - pr_debug("\tcookie: %d slot: %d busy: %d " - "this_desc: %pad next_desc: %#llx ack: %d\n", - iter->async_tx.cookie, iter->idx, busy, - &iter->async_tx.phys, (u64)iop_desc_get_next_desc(iter), - async_tx_test_ack(&iter->async_tx)); - prefetch(_iter); - prefetch(&_iter->async_tx); - - /* do not advance past the current descriptor loaded into the - * hardware channel, subsequent descriptors are either in - * process or have not been submitted - */ - if (seen_current) - break; - - /* stop the search if we reach the current descriptor and the - * channel is busy, or if it appears that the current descriptor - * needs to be re-read (i.e. has been appended to) - */ - if (iter->async_tx.phys == current_desc) { - BUG_ON(seen_current++); - if (busy || iop_desc_get_next_desc(iter)) - break; - } - - /* detect the start of a group transaction */ - if (!slot_cnt && !slots_per_op) { - slot_cnt = iter->slot_cnt; - slots_per_op = iter->slots_per_op; - if (slot_cnt <= slots_per_op) { - slot_cnt = 0; - slots_per_op = 0; - } - } - - if (slot_cnt) { - pr_debug("\tgroup++\n"); - if (!grp_start) - grp_start = iter; - slot_cnt -= slots_per_op; - } - - /* all the members of a group are complete */ - if (slots_per_op != 0 && slot_cnt == 0) { - struct iop_adma_desc_slot *grp_iter, *_grp_iter; - int end_of_chain = 0; - pr_debug("\tgroup end\n"); - - /* collect the total results */ - if (grp_start->xor_check_result) { - u32 zero_sum_result = 0; - slot_cnt = grp_start->slot_cnt; - grp_iter = grp_start; - - list_for_each_entry_from(grp_iter, - &iop_chan->chain, chain_node) { - zero_sum_result |= - iop_desc_get_zero_result(grp_iter); - pr_debug("\titer%d result: %d\n", - grp_iter->idx, zero_sum_result); - slot_cnt -= slots_per_op; - if (slot_cnt == 0) - break; - } - pr_debug("\tgrp_start->xor_check_result: %p\n", - grp_start->xor_check_result); - *grp_start->xor_check_result = zero_sum_result; - } - - /* clean up the group */ - slot_cnt = grp_start->slot_cnt; - grp_iter = grp_start; - list_for_each_entry_safe_from(grp_iter, _grp_iter, - &iop_chan->chain, chain_node) { - cookie = iop_adma_run_tx_complete_actions( - grp_iter, iop_chan, cookie); - - slot_cnt -= slots_per_op; - end_of_chain = iop_adma_clean_slot(grp_iter, - iop_chan); - - if (slot_cnt == 0 || end_of_chain) - break; - } - - /* the group should be complete at this point */ - BUG_ON(slot_cnt); - - slots_per_op = 0; - grp_start = NULL; - if (end_of_chain) - break; - else - continue; - } else if (slots_per_op) /* wait for group completion */ - continue; - - /* write back zero sum results (single descriptor case) */ - if (iter->xor_check_result && iter->async_tx.cookie) - *iter->xor_check_result = - iop_desc_get_zero_result(iter); - - cookie = iop_adma_run_tx_complete_actions( - iter, iop_chan, cookie); - - if (iop_adma_clean_slot(iter, iop_chan)) - break; - } - - if (cookie > 0) { - iop_chan->common.completed_cookie = cookie; - pr_debug("\tcompleted cookie %d\n", cookie); - } -} - -static void -iop_adma_slot_cleanup(struct iop_adma_chan *iop_chan) -{ - spin_lock_bh(&iop_chan->lock); - __iop_adma_slot_cleanup(iop_chan); - spin_unlock_bh(&iop_chan->lock); -} - -static void iop_adma_tasklet(struct tasklet_struct *t) -{ - struct iop_adma_chan *iop_chan = from_tasklet(iop_chan, t, - irq_tasklet); - - /* lockdep will flag depedency submissions as potentially - * recursive locking, this is not the case as a dependency - * submission will never recurse a channels submit routine. - * There are checks in async_tx.c to prevent this. - */ - spin_lock_nested(&iop_chan->lock, SINGLE_DEPTH_NESTING); - __iop_adma_slot_cleanup(iop_chan); - spin_unlock(&iop_chan->lock); -} - -static struct iop_adma_desc_slot * -iop_adma_alloc_slots(struct iop_adma_chan *iop_chan, int num_slots, - int slots_per_op) -{ - struct iop_adma_desc_slot *iter, *_iter, *alloc_start = NULL; - LIST_HEAD(chain); - int slots_found, retry = 0; - - /* start search from the last allocated descrtiptor - * if a contiguous allocation can not be found start searching - * from the beginning of the list - */ -retry: - slots_found = 0; - if (retry == 0) - iter = iop_chan->last_used; - else - iter = list_entry(&iop_chan->all_slots, - struct iop_adma_desc_slot, - slot_node); - - list_for_each_entry_safe_continue( - iter, _iter, &iop_chan->all_slots, slot_node) { - prefetch(_iter); - prefetch(&_iter->async_tx); - if (iter->slots_per_op) { - /* give up after finding the first busy slot - * on the second pass through the list - */ - if (retry) - break; - - slots_found = 0; - continue; - } - - /* start the allocation if the slot is correctly aligned */ - if (!slots_found++) { - if (iop_desc_is_aligned(iter, slots_per_op)) - alloc_start = iter; - else { - slots_found = 0; - continue; - } - } - - if (slots_found == num_slots) { - struct iop_adma_desc_slot *alloc_tail = NULL; - struct iop_adma_desc_slot *last_used = NULL; - iter = alloc_start; - while (num_slots) { - int i; - dev_dbg(iop_chan->device->common.dev, - "allocated slot: %d " - "(desc %p phys: %#llx) slots_per_op %d\n", - iter->idx, iter->hw_desc, - (u64)iter->async_tx.phys, slots_per_op); - - /* pre-ack all but the last descriptor */ - if (num_slots != slots_per_op) - async_tx_ack(&iter->async_tx); - - list_add_tail(&iter->chain_node, &chain); - alloc_tail = iter; - iter->async_tx.cookie = 0; - iter->slot_cnt = num_slots; - iter->xor_check_result = NULL; - for (i = 0; i < slots_per_op; i++) { - iter->slots_per_op = slots_per_op - i; - last_used = iter; - iter = list_entry(iter->slot_node.next, - struct iop_adma_desc_slot, - slot_node); - } - num_slots -= slots_per_op; - } - alloc_tail->group_head = alloc_start; - alloc_tail->async_tx.cookie = -EBUSY; - list_splice(&chain, &alloc_tail->tx_list); - iop_chan->last_used = last_used; - iop_desc_clear_next_desc(alloc_start); - iop_desc_clear_next_desc(alloc_tail); - return alloc_tail; - } - } - if (!retry++) - goto retry; - - /* perform direct reclaim if the allocation fails */ - __iop_adma_slot_cleanup(iop_chan); - - return NULL; -} - -static void iop_adma_check_threshold(struct iop_adma_chan *iop_chan) -{ - dev_dbg(iop_chan->device->common.dev, "pending: %d\n", - iop_chan->pending); - - if (iop_chan->pending >= IOP_ADMA_THRESHOLD) { - iop_chan->pending = 0; - iop_chan_append(iop_chan); - } -} - -static dma_cookie_t -iop_adma_tx_submit(struct dma_async_tx_descriptor *tx) -{ - struct iop_adma_desc_slot *sw_desc = tx_to_iop_adma_slot(tx); - struct iop_adma_chan *iop_chan = to_iop_adma_chan(tx->chan); - struct iop_adma_desc_slot *grp_start, *old_chain_tail; - int slot_cnt; - dma_cookie_t cookie; - dma_addr_t next_dma; - - grp_start = sw_desc->group_head; - slot_cnt = grp_start->slot_cnt; - - spin_lock_bh(&iop_chan->lock); - cookie = dma_cookie_assign(tx); - - old_chain_tail = list_entry(iop_chan->chain.prev, - struct iop_adma_desc_slot, chain_node); - list_splice_init(&sw_desc->tx_list, - &old_chain_tail->chain_node); - - /* fix up the hardware chain */ - next_dma = grp_start->async_tx.phys; - iop_desc_set_next_desc(old_chain_tail, next_dma); - BUG_ON(iop_desc_get_next_desc(old_chain_tail) != next_dma); /* flush */ - - /* check for pre-chained descriptors */ - iop_paranoia(iop_desc_get_next_desc(sw_desc)); - - /* increment the pending count by the number of slots - * memcpy operations have a 1:1 (slot:operation) relation - * other operations are heavier and will pop the threshold - * more often. - */ - iop_chan->pending += slot_cnt; - iop_adma_check_threshold(iop_chan); - spin_unlock_bh(&iop_chan->lock); - - dev_dbg(iop_chan->device->common.dev, "%s cookie: %d slot: %d\n", - __func__, sw_desc->async_tx.cookie, sw_desc->idx); - - return cookie; -} - -static void iop_chan_start_null_memcpy(struct iop_adma_chan *iop_chan); -static void iop_chan_start_null_xor(struct iop_adma_chan *iop_chan); - -/** - * iop_adma_alloc_chan_resources - returns the number of allocated descriptors - * @chan: allocate descriptor resources for this channel - * - * Note: We keep the slots for 1 operation on iop_chan->chain at all times. To - * avoid deadlock, via async_xor, num_descs_in_pool must at a minimum be - * greater than 2x the number slots needed to satisfy a device->max_xor - * request. - * */ -static int iop_adma_alloc_chan_resources(struct dma_chan *chan) -{ - char *hw_desc; - dma_addr_t dma_desc; - int idx; - struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan); - struct iop_adma_desc_slot *slot = NULL; - int init = iop_chan->slots_allocated ? 0 : 1; - struct iop_adma_platform_data *plat_data = - dev_get_platdata(&iop_chan->device->pdev->dev); - int num_descs_in_pool = plat_data->pool_size/IOP_ADMA_SLOT_SIZE; - - /* Allocate descriptor slots */ - do { - idx = iop_chan->slots_allocated; - if (idx == num_descs_in_pool) - break; - - slot = kzalloc(sizeof(*slot), GFP_KERNEL); - if (!slot) { - printk(KERN_INFO "IOP ADMA Channel only initialized" - " %d descriptor slots", idx); - break; - } - hw_desc = (char *) iop_chan->device->dma_desc_pool_virt; - slot->hw_desc = (void *) &hw_desc[idx * IOP_ADMA_SLOT_SIZE]; - - dma_async_tx_descriptor_init(&slot->async_tx, chan); - slot->async_tx.tx_submit = iop_adma_tx_submit; - INIT_LIST_HEAD(&slot->tx_list); - INIT_LIST_HEAD(&slot->chain_node); - INIT_LIST_HEAD(&slot->slot_node); - dma_desc = iop_chan->device->dma_desc_pool; - slot->async_tx.phys = dma_desc + idx * IOP_ADMA_SLOT_SIZE; - slot->idx = idx; - - spin_lock_bh(&iop_chan->lock); - iop_chan->slots_allocated++; - list_add_tail(&slot->slot_node, &iop_chan->all_slots); - spin_unlock_bh(&iop_chan->lock); - } while (iop_chan->slots_allocated < num_descs_in_pool); - - if (idx && !iop_chan->last_used) - iop_chan->last_used = list_entry(iop_chan->all_slots.next, - struct iop_adma_desc_slot, - slot_node); - - dev_dbg(iop_chan->device->common.dev, - "allocated %d descriptor slots last_used: %p\n", - iop_chan->slots_allocated, iop_chan->last_used); - - /* initialize the channel and the chain with a null operation */ - if (init) { - if (dma_has_cap(DMA_MEMCPY, - iop_chan->device->common.cap_mask)) - iop_chan_start_null_memcpy(iop_chan); - else if (dma_has_cap(DMA_XOR, - iop_chan->device->common.cap_mask)) - iop_chan_start_null_xor(iop_chan); - else - BUG(); - } - - return (idx > 0) ? idx : -ENOMEM; -} - -static struct dma_async_tx_descriptor * -iop_adma_prep_dma_interrupt(struct dma_chan *chan, unsigned long flags) -{ - struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan); - struct iop_adma_desc_slot *sw_desc, *grp_start; - int slot_cnt, slots_per_op; - - dev_dbg(iop_chan->device->common.dev, "%s\n", __func__); - - spin_lock_bh(&iop_chan->lock); - slot_cnt = iop_chan_interrupt_slot_count(&slots_per_op, iop_chan); - sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op); - if (sw_desc) { - grp_start = sw_desc->group_head; - iop_desc_init_interrupt(grp_start, iop_chan); - sw_desc->async_tx.flags = flags; - } - spin_unlock_bh(&iop_chan->lock); - - return sw_desc ? &sw_desc->async_tx : NULL; -} - -static struct dma_async_tx_descriptor * -iop_adma_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dma_dest, - dma_addr_t dma_src, size_t len, unsigned long flags) -{ - struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan); - struct iop_adma_desc_slot *sw_desc, *grp_start; - int slot_cnt, slots_per_op; - - if (unlikely(!len)) - return NULL; - BUG_ON(len > IOP_ADMA_MAX_BYTE_COUNT); - - dev_dbg(iop_chan->device->common.dev, "%s len: %zu\n", - __func__, len); - - spin_lock_bh(&iop_chan->lock); - slot_cnt = iop_chan_memcpy_slot_count(len, &slots_per_op); - sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op); - if (sw_desc) { - grp_start = sw_desc->group_head; - iop_desc_init_memcpy(grp_start, flags); - iop_desc_set_byte_count(grp_start, iop_chan, len); - iop_desc_set_dest_addr(grp_start, iop_chan, dma_dest); - iop_desc_set_memcpy_src_addr(grp_start, dma_src); - sw_desc->async_tx.flags = flags; - } - spin_unlock_bh(&iop_chan->lock); - - return sw_desc ? &sw_desc->async_tx : NULL; -} - -static struct dma_async_tx_descriptor * -iop_adma_prep_dma_xor(struct dma_chan *chan, dma_addr_t dma_dest, - dma_addr_t *dma_src, unsigned int src_cnt, size_t len, - unsigned long flags) -{ - struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan); - struct iop_adma_desc_slot *sw_desc, *grp_start; - int slot_cnt, slots_per_op; - - if (unlikely(!len)) - return NULL; - BUG_ON(len > IOP_ADMA_XOR_MAX_BYTE_COUNT); - - dev_dbg(iop_chan->device->common.dev, - "%s src_cnt: %d len: %zu flags: %lx\n", - __func__, src_cnt, len, flags); - - spin_lock_bh(&iop_chan->lock); - slot_cnt = iop_chan_xor_slot_count(len, src_cnt, &slots_per_op); - sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op); - if (sw_desc) { - grp_start = sw_desc->group_head; - iop_desc_init_xor(grp_start, src_cnt, flags); - iop_desc_set_byte_count(grp_start, iop_chan, len); - iop_desc_set_dest_addr(grp_start, iop_chan, dma_dest); - sw_desc->async_tx.flags = flags; - while (src_cnt--) - iop_desc_set_xor_src_addr(grp_start, src_cnt, - dma_src[src_cnt]); - } - spin_unlock_bh(&iop_chan->lock); - - return sw_desc ? &sw_desc->async_tx : NULL; -} - -static struct dma_async_tx_descriptor * -iop_adma_prep_dma_xor_val(struct dma_chan *chan, dma_addr_t *dma_src, - unsigned int src_cnt, size_t len, u32 *result, - unsigned long flags) -{ - struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan); - struct iop_adma_desc_slot *sw_desc, *grp_start; - int slot_cnt, slots_per_op; - - if (unlikely(!len)) - return NULL; - - dev_dbg(iop_chan->device->common.dev, "%s src_cnt: %d len: %zu\n", - __func__, src_cnt, len); - - spin_lock_bh(&iop_chan->lock); - slot_cnt = iop_chan_zero_sum_slot_count(len, src_cnt, &slots_per_op); - sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op); - if (sw_desc) { - grp_start = sw_desc->group_head; - iop_desc_init_zero_sum(grp_start, src_cnt, flags); - iop_desc_set_zero_sum_byte_count(grp_start, len); - grp_start->xor_check_result = result; - pr_debug("\t%s: grp_start->xor_check_result: %p\n", - __func__, grp_start->xor_check_result); - sw_desc->async_tx.flags = flags; - while (src_cnt--) - iop_desc_set_zero_sum_src_addr(grp_start, src_cnt, - dma_src[src_cnt]); - } - spin_unlock_bh(&iop_chan->lock); - - return sw_desc ? &sw_desc->async_tx : NULL; -} - -static struct dma_async_tx_descriptor * -iop_adma_prep_dma_pq(struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src, - unsigned int src_cnt, const unsigned char *scf, size_t len, - unsigned long flags) -{ - struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan); - struct iop_adma_desc_slot *sw_desc, *g; - int slot_cnt, slots_per_op; - int continue_srcs; - - if (unlikely(!len)) - return NULL; - BUG_ON(len > IOP_ADMA_XOR_MAX_BYTE_COUNT); - - dev_dbg(iop_chan->device->common.dev, - "%s src_cnt: %d len: %zu flags: %lx\n", - __func__, src_cnt, len, flags); - - if (dmaf_p_disabled_continue(flags)) - continue_srcs = 1+src_cnt; - else if (dmaf_continue(flags)) - continue_srcs = 3+src_cnt; - else - continue_srcs = 0+src_cnt; - - spin_lock_bh(&iop_chan->lock); - slot_cnt = iop_chan_pq_slot_count(len, continue_srcs, &slots_per_op); - sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op); - if (sw_desc) { - int i; - - g = sw_desc->group_head; - iop_desc_set_byte_count(g, iop_chan, len); - - /* even if P is disabled its destination address (bits - * [3:0]) must match Q. It is ok if P points to an - * invalid address, it won't be written. - */ - if (flags & DMA_PREP_PQ_DISABLE_P) - dst[0] = dst[1] & 0x7; - - iop_desc_set_pq_addr(g, dst); - sw_desc->async_tx.flags = flags; - for (i = 0; i < src_cnt; i++) - iop_desc_set_pq_src_addr(g, i, src[i], scf[i]); - - /* if we are continuing a previous operation factor in - * the old p and q values, see the comment for dma_maxpq - * in include/linux/dmaengine.h - */ - if (dmaf_p_disabled_continue(flags)) - iop_desc_set_pq_src_addr(g, i++, dst[1], 1); - else if (dmaf_continue(flags)) { - iop_desc_set_pq_src_addr(g, i++, dst[0], 0); - iop_desc_set_pq_src_addr(g, i++, dst[1], 1); - iop_desc_set_pq_src_addr(g, i++, dst[1], 0); - } - iop_desc_init_pq(g, i, flags); - } - spin_unlock_bh(&iop_chan->lock); - - return sw_desc ? &sw_desc->async_tx : NULL; -} - -static struct dma_async_tx_descriptor * -iop_adma_prep_dma_pq_val(struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src, - unsigned int src_cnt, const unsigned char *scf, - size_t len, enum sum_check_flags *pqres, - unsigned long flags) -{ - struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan); - struct iop_adma_desc_slot *sw_desc, *g; - int slot_cnt, slots_per_op; - - if (unlikely(!len)) - return NULL; - BUG_ON(len > IOP_ADMA_XOR_MAX_BYTE_COUNT); - - dev_dbg(iop_chan->device->common.dev, "%s src_cnt: %d len: %zu\n", - __func__, src_cnt, len); - - spin_lock_bh(&iop_chan->lock); - slot_cnt = iop_chan_pq_zero_sum_slot_count(len, src_cnt + 2, &slots_per_op); - sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op); - if (sw_desc) { - /* for validate operations p and q are tagged onto the - * end of the source list - */ - int pq_idx = src_cnt; - - g = sw_desc->group_head; - iop_desc_init_pq_zero_sum(g, src_cnt+2, flags); - iop_desc_set_pq_zero_sum_byte_count(g, len); - g->pq_check_result = pqres; - pr_debug("\t%s: g->pq_check_result: %p\n", - __func__, g->pq_check_result); - sw_desc->async_tx.flags = flags; - while (src_cnt--) - iop_desc_set_pq_zero_sum_src_addr(g, src_cnt, - src[src_cnt], - scf[src_cnt]); - iop_desc_set_pq_zero_sum_addr(g, pq_idx, src); - } - spin_unlock_bh(&iop_chan->lock); - - return sw_desc ? &sw_desc->async_tx : NULL; -} - -static void iop_adma_free_chan_resources(struct dma_chan *chan) -{ - struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan); - struct iop_adma_desc_slot *iter, *_iter; - int in_use_descs = 0; - - iop_adma_slot_cleanup(iop_chan); - - spin_lock_bh(&iop_chan->lock); - list_for_each_entry_safe(iter, _iter, &iop_chan->chain, - chain_node) { - in_use_descs++; - list_del(&iter->chain_node); - } - list_for_each_entry_safe_reverse( - iter, _iter, &iop_chan->all_slots, slot_node) { - list_del(&iter->slot_node); - kfree(iter); - iop_chan->slots_allocated--; - } - iop_chan->last_used = NULL; - - dev_dbg(iop_chan->device->common.dev, "%s slots_allocated %d\n", - __func__, iop_chan->slots_allocated); - spin_unlock_bh(&iop_chan->lock); - - /* one is ok since we left it on there on purpose */ - if (in_use_descs > 1) - printk(KERN_ERR "IOP: Freeing %d in use descriptors!\n", - in_use_descs - 1); -} - -/** - * iop_adma_status - poll the status of an ADMA transaction - * @chan: ADMA channel handle - * @cookie: ADMA transaction identifier - * @txstate: a holder for the current state of the channel or NULL - */ -static enum dma_status iop_adma_status(struct dma_chan *chan, - dma_cookie_t cookie, - struct dma_tx_state *txstate) -{ - struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan); - int ret; - - ret = dma_cookie_status(chan, cookie, txstate); - if (ret == DMA_COMPLETE) - return ret; - - iop_adma_slot_cleanup(iop_chan); - - return dma_cookie_status(chan, cookie, txstate); -} - -static irqreturn_t iop_adma_eot_handler(int irq, void *data) -{ - struct iop_adma_chan *chan = data; - - dev_dbg(chan->device->common.dev, "%s\n", __func__); - - tasklet_schedule(&chan->irq_tasklet); - - iop_adma_device_clear_eot_status(chan); - - return IRQ_HANDLED; -} - -static irqreturn_t iop_adma_eoc_handler(int irq, void *data) -{ - struct iop_adma_chan *chan = data; - - dev_dbg(chan->device->common.dev, "%s\n", __func__); - - tasklet_schedule(&chan->irq_tasklet); - - iop_adma_device_clear_eoc_status(chan); - - return IRQ_HANDLED; -} - -static irqreturn_t iop_adma_err_handler(int irq, void *data) -{ - struct iop_adma_chan *chan = data; - unsigned long status = iop_chan_get_status(chan); - - dev_err(chan->device->common.dev, - "error ( %s%s%s%s%s%s%s)\n", - iop_is_err_int_parity(status, chan) ? "int_parity " : "", - iop_is_err_mcu_abort(status, chan) ? "mcu_abort " : "", - iop_is_err_int_tabort(status, chan) ? "int_tabort " : "", - iop_is_err_int_mabort(status, chan) ? "int_mabort " : "", - iop_is_err_pci_tabort(status, chan) ? "pci_tabort " : "", - iop_is_err_pci_mabort(status, chan) ? "pci_mabort " : "", - iop_is_err_split_tx(status, chan) ? "split_tx " : ""); - - iop_adma_device_clear_err_status(chan); - - BUG(); - - return IRQ_HANDLED; -} - -static void iop_adma_issue_pending(struct dma_chan *chan) -{ - struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan); - - if (iop_chan->pending) { - iop_chan->pending = 0; - iop_chan_append(iop_chan); - } -} - -/* - * Perform a transaction to verify the HW works. - */ -#define IOP_ADMA_TEST_SIZE 2000 - -static int iop_adma_memcpy_self_test(struct iop_adma_device *device) -{ - int i; - void *src, *dest; - dma_addr_t src_dma, dest_dma; - struct dma_chan *dma_chan; - dma_cookie_t cookie; - struct dma_async_tx_descriptor *tx; - int err = 0; - struct iop_adma_chan *iop_chan; - - dev_dbg(device->common.dev, "%s\n", __func__); - - src = kmalloc(IOP_ADMA_TEST_SIZE, GFP_KERNEL); - if (!src) - return -ENOMEM; - dest = kzalloc(IOP_ADMA_TEST_SIZE, GFP_KERNEL); - if (!dest) { - kfree(src); - return -ENOMEM; - } - - /* Fill in src buffer */ - for (i = 0; i < IOP_ADMA_TEST_SIZE; i++) - ((u8 *) src)[i] = (u8)i; - - /* Start copy, using first DMA channel */ - dma_chan = container_of(device->common.channels.next, - struct dma_chan, - device_node); - if (iop_adma_alloc_chan_resources(dma_chan) < 1) { - err = -ENODEV; - goto out; - } - - dest_dma = dma_map_single(dma_chan->device->dev, dest, - IOP_ADMA_TEST_SIZE, DMA_FROM_DEVICE); - src_dma = dma_map_single(dma_chan->device->dev, src, - IOP_ADMA_TEST_SIZE, DMA_TO_DEVICE); - tx = iop_adma_prep_dma_memcpy(dma_chan, dest_dma, src_dma, - IOP_ADMA_TEST_SIZE, - DMA_PREP_INTERRUPT | DMA_CTRL_ACK); - - cookie = iop_adma_tx_submit(tx); - iop_adma_issue_pending(dma_chan); - msleep(1); - - if (iop_adma_status(dma_chan, cookie, NULL) != - DMA_COMPLETE) { - dev_err(dma_chan->device->dev, - "Self-test copy timed out, disabling\n"); - err = -ENODEV; - goto free_resources; - } - - iop_chan = to_iop_adma_chan(dma_chan); - dma_sync_single_for_cpu(&iop_chan->device->pdev->dev, dest_dma, - IOP_ADMA_TEST_SIZE, DMA_FROM_DEVICE); - if (memcmp(src, dest, IOP_ADMA_TEST_SIZE)) { - dev_err(dma_chan->device->dev, - "Self-test copy failed compare, disabling\n"); - err = -ENODEV; - goto free_resources; - } - -free_resources: - iop_adma_free_chan_resources(dma_chan); -out: - kfree(src); - kfree(dest); - return err; -} - -#define IOP_ADMA_NUM_SRC_TEST 4 /* must be <= 15 */ -static int -iop_adma_xor_val_self_test(struct iop_adma_device *device) -{ - int i, src_idx; - struct page *dest; - struct page *xor_srcs[IOP_ADMA_NUM_SRC_TEST]; - struct page *zero_sum_srcs[IOP_ADMA_NUM_SRC_TEST + 1]; - dma_addr_t dma_srcs[IOP_ADMA_NUM_SRC_TEST + 1]; - dma_addr_t dest_dma; - struct dma_async_tx_descriptor *tx; - struct dma_chan *dma_chan; - dma_cookie_t cookie; - u8 cmp_byte = 0; - u32 cmp_word; - u32 zero_sum_result; - int err = 0; - struct iop_adma_chan *iop_chan; - - dev_dbg(device->common.dev, "%s\n", __func__); - - for (src_idx = 0; src_idx < IOP_ADMA_NUM_SRC_TEST; src_idx++) { - xor_srcs[src_idx] = alloc_page(GFP_KERNEL); - if (!xor_srcs[src_idx]) { - while (src_idx--) - __free_page(xor_srcs[src_idx]); - return -ENOMEM; - } - } - - dest = alloc_page(GFP_KERNEL); - if (!dest) { - while (src_idx--) - __free_page(xor_srcs[src_idx]); - return -ENOMEM; - } - - /* Fill in src buffers */ - for (src_idx = 0; src_idx < IOP_ADMA_NUM_SRC_TEST; src_idx++) { - u8 *ptr = page_address(xor_srcs[src_idx]); - for (i = 0; i < PAGE_SIZE; i++) - ptr[i] = (1 << src_idx); - } - - for (src_idx = 0; src_idx < IOP_ADMA_NUM_SRC_TEST; src_idx++) - cmp_byte ^= (u8) (1 << src_idx); - - cmp_word = (cmp_byte << 24) | (cmp_byte << 16) | - (cmp_byte << 8) | cmp_byte; - - memset(page_address(dest), 0, PAGE_SIZE); - - dma_chan = container_of(device->common.channels.next, - struct dma_chan, - device_node); - if (iop_adma_alloc_chan_resources(dma_chan) < 1) { - err = -ENODEV; - goto out; - } - - /* test xor */ - dest_dma = dma_map_page(dma_chan->device->dev, dest, 0, - PAGE_SIZE, DMA_FROM_DEVICE); - for (i = 0; i < IOP_ADMA_NUM_SRC_TEST; i++) - dma_srcs[i] = dma_map_page(dma_chan->device->dev, xor_srcs[i], - 0, PAGE_SIZE, DMA_TO_DEVICE); - tx = iop_adma_prep_dma_xor(dma_chan, dest_dma, dma_srcs, - IOP_ADMA_NUM_SRC_TEST, PAGE_SIZE, - DMA_PREP_INTERRUPT | DMA_CTRL_ACK); - - cookie = iop_adma_tx_submit(tx); - iop_adma_issue_pending(dma_chan); - msleep(8); - - if (iop_adma_status(dma_chan, cookie, NULL) != - DMA_COMPLETE) { - dev_err(dma_chan->device->dev, - "Self-test xor timed out, disabling\n"); - err = -ENODEV; - goto free_resources; - } - - iop_chan = to_iop_adma_chan(dma_chan); - dma_sync_single_for_cpu(&iop_chan->device->pdev->dev, dest_dma, - PAGE_SIZE, DMA_FROM_DEVICE); - for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) { - u32 *ptr = page_address(dest); - if (ptr[i] != cmp_word) { - dev_err(dma_chan->device->dev, - "Self-test xor failed compare, disabling\n"); - err = -ENODEV; - goto free_resources; - } - } - dma_sync_single_for_device(&iop_chan->device->pdev->dev, dest_dma, - PAGE_SIZE, DMA_TO_DEVICE); - - /* skip zero sum if the capability is not present */ - if (!dma_has_cap(DMA_XOR_VAL, dma_chan->device->cap_mask)) - goto free_resources; - - /* zero sum the sources with the destintation page */ - for (i = 0; i < IOP_ADMA_NUM_SRC_TEST; i++) - zero_sum_srcs[i] = xor_srcs[i]; - zero_sum_srcs[i] = dest; - - zero_sum_result = 1; - - for (i = 0; i < IOP_ADMA_NUM_SRC_TEST + 1; i++) - dma_srcs[i] = dma_map_page(dma_chan->device->dev, - zero_sum_srcs[i], 0, PAGE_SIZE, - DMA_TO_DEVICE); - tx = iop_adma_prep_dma_xor_val(dma_chan, dma_srcs, - IOP_ADMA_NUM_SRC_TEST + 1, PAGE_SIZE, - &zero_sum_result, - DMA_PREP_INTERRUPT | DMA_CTRL_ACK); - - cookie = iop_adma_tx_submit(tx); - iop_adma_issue_pending(dma_chan); - msleep(8); - - if (iop_adma_status(dma_chan, cookie, NULL) != DMA_COMPLETE) { - dev_err(dma_chan->device->dev, - "Self-test zero sum timed out, disabling\n"); - err = -ENODEV; - goto free_resources; - } - - if (zero_sum_result != 0) { - dev_err(dma_chan->device->dev, - "Self-test zero sum failed compare, disabling\n"); - err = -ENODEV; - goto free_resources; - } - - /* test for non-zero parity sum */ - zero_sum_result = 0; - for (i = 0; i < IOP_ADMA_NUM_SRC_TEST + 1; i++) - dma_srcs[i] = dma_map_page(dma_chan->device->dev, - zero_sum_srcs[i], 0, PAGE_SIZE, - DMA_TO_DEVICE); - tx = iop_adma_prep_dma_xor_val(dma_chan, dma_srcs, - IOP_ADMA_NUM_SRC_TEST + 1, PAGE_SIZE, - &zero_sum_result, - DMA_PREP_INTERRUPT | DMA_CTRL_ACK); - - cookie = iop_adma_tx_submit(tx); - iop_adma_issue_pending(dma_chan); - msleep(8); - - if (iop_adma_status(dma_chan, cookie, NULL) != DMA_COMPLETE) { - dev_err(dma_chan->device->dev, - "Self-test non-zero sum timed out, disabling\n"); - err = -ENODEV; - goto free_resources; - } - - if (zero_sum_result != 1) { - dev_err(dma_chan->device->dev, - "Self-test non-zero sum failed compare, disabling\n"); - err = -ENODEV; - goto free_resources; - } - -free_resources: - iop_adma_free_chan_resources(dma_chan); -out: - src_idx = IOP_ADMA_NUM_SRC_TEST; - while (src_idx--) - __free_page(xor_srcs[src_idx]); - __free_page(dest); - return err; -} - -#ifdef CONFIG_RAID6_PQ -static int -iop_adma_pq_zero_sum_self_test(struct iop_adma_device *device) -{ - /* combined sources, software pq results, and extra hw pq results */ - struct page *pq[IOP_ADMA_NUM_SRC_TEST+2+2]; - /* ptr to the extra hw pq buffers defined above */ - struct page **pq_hw = &pq[IOP_ADMA_NUM_SRC_TEST+2]; - /* address conversion buffers (dma_map / page_address) */ - void *pq_sw[IOP_ADMA_NUM_SRC_TEST+2]; - dma_addr_t pq_src[IOP_ADMA_NUM_SRC_TEST+2]; - dma_addr_t *pq_dest = &pq_src[IOP_ADMA_NUM_SRC_TEST]; - - int i; - struct dma_async_tx_descriptor *tx; - struct dma_chan *dma_chan; - dma_cookie_t cookie; - u32 zero_sum_result; - int err = 0; - struct device *dev; - - dev_dbg(device->common.dev, "%s\n", __func__); - - for (i = 0; i < ARRAY_SIZE(pq); i++) { - pq[i] = alloc_page(GFP_KERNEL); - if (!pq[i]) { - while (i--) - __free_page(pq[i]); - return -ENOMEM; - } - } - - /* Fill in src buffers */ - for (i = 0; i < IOP_ADMA_NUM_SRC_TEST; i++) { - pq_sw[i] = page_address(pq[i]); - memset(pq_sw[i], 0x11111111 * (1<common.channels.next, - struct dma_chan, - device_node); - if (iop_adma_alloc_chan_resources(dma_chan) < 1) { - err = -ENODEV; - goto out; - } - - dev = dma_chan->device->dev; - - /* initialize the dests */ - memset(page_address(pq_hw[0]), 0 , PAGE_SIZE); - memset(page_address(pq_hw[1]), 0 , PAGE_SIZE); - - /* test pq */ - pq_dest[0] = dma_map_page(dev, pq_hw[0], 0, PAGE_SIZE, DMA_FROM_DEVICE); - pq_dest[1] = dma_map_page(dev, pq_hw[1], 0, PAGE_SIZE, DMA_FROM_DEVICE); - for (i = 0; i < IOP_ADMA_NUM_SRC_TEST; i++) - pq_src[i] = dma_map_page(dev, pq[i], 0, PAGE_SIZE, - DMA_TO_DEVICE); - - tx = iop_adma_prep_dma_pq(dma_chan, pq_dest, pq_src, - IOP_ADMA_NUM_SRC_TEST, (u8 *)raid6_gfexp, - PAGE_SIZE, - DMA_PREP_INTERRUPT | - DMA_CTRL_ACK); - - cookie = iop_adma_tx_submit(tx); - iop_adma_issue_pending(dma_chan); - msleep(8); - - if (iop_adma_status(dma_chan, cookie, NULL) != - DMA_COMPLETE) { - dev_err(dev, "Self-test pq timed out, disabling\n"); - err = -ENODEV; - goto free_resources; - } - - raid6_call.gen_syndrome(IOP_ADMA_NUM_SRC_TEST+2, PAGE_SIZE, pq_sw); - - if (memcmp(pq_sw[IOP_ADMA_NUM_SRC_TEST], - page_address(pq_hw[0]), PAGE_SIZE) != 0) { - dev_err(dev, "Self-test p failed compare, disabling\n"); - err = -ENODEV; - goto free_resources; - } - if (memcmp(pq_sw[IOP_ADMA_NUM_SRC_TEST+1], - page_address(pq_hw[1]), PAGE_SIZE) != 0) { - dev_err(dev, "Self-test q failed compare, disabling\n"); - err = -ENODEV; - goto free_resources; - } - - /* test correct zero sum using the software generated pq values */ - for (i = 0; i < IOP_ADMA_NUM_SRC_TEST + 2; i++) - pq_src[i] = dma_map_page(dev, pq[i], 0, PAGE_SIZE, - DMA_TO_DEVICE); - - zero_sum_result = ~0; - tx = iop_adma_prep_dma_pq_val(dma_chan, &pq_src[IOP_ADMA_NUM_SRC_TEST], - pq_src, IOP_ADMA_NUM_SRC_TEST, - raid6_gfexp, PAGE_SIZE, &zero_sum_result, - DMA_PREP_INTERRUPT|DMA_CTRL_ACK); - - cookie = iop_adma_tx_submit(tx); - iop_adma_issue_pending(dma_chan); - msleep(8); - - if (iop_adma_status(dma_chan, cookie, NULL) != - DMA_COMPLETE) { - dev_err(dev, "Self-test pq-zero-sum timed out, disabling\n"); - err = -ENODEV; - goto free_resources; - } - - if (zero_sum_result != 0) { - dev_err(dev, "Self-test pq-zero-sum failed to validate: %x\n", - zero_sum_result); - err = -ENODEV; - goto free_resources; - } - - /* test incorrect zero sum */ - i = IOP_ADMA_NUM_SRC_TEST; - memset(pq_sw[i] + 100, 0, 100); - memset(pq_sw[i+1] + 200, 0, 200); - for (i = 0; i < IOP_ADMA_NUM_SRC_TEST + 2; i++) - pq_src[i] = dma_map_page(dev, pq[i], 0, PAGE_SIZE, - DMA_TO_DEVICE); - - zero_sum_result = 0; - tx = iop_adma_prep_dma_pq_val(dma_chan, &pq_src[IOP_ADMA_NUM_SRC_TEST], - pq_src, IOP_ADMA_NUM_SRC_TEST, - raid6_gfexp, PAGE_SIZE, &zero_sum_result, - DMA_PREP_INTERRUPT|DMA_CTRL_ACK); - - cookie = iop_adma_tx_submit(tx); - iop_adma_issue_pending(dma_chan); - msleep(8); - - if (iop_adma_status(dma_chan, cookie, NULL) != - DMA_COMPLETE) { - dev_err(dev, "Self-test !pq-zero-sum timed out, disabling\n"); - err = -ENODEV; - goto free_resources; - } - - if (zero_sum_result != (SUM_CHECK_P_RESULT | SUM_CHECK_Q_RESULT)) { - dev_err(dev, "Self-test !pq-zero-sum failed to validate: %x\n", - zero_sum_result); - err = -ENODEV; - goto free_resources; - } - -free_resources: - iop_adma_free_chan_resources(dma_chan); -out: - i = ARRAY_SIZE(pq); - while (i--) - __free_page(pq[i]); - return err; -} -#endif - -static int iop_adma_remove(struct platform_device *dev) -{ - struct iop_adma_device *device = platform_get_drvdata(dev); - struct dma_chan *chan, *_chan; - struct iop_adma_chan *iop_chan; - struct iop_adma_platform_data *plat_data = dev_get_platdata(&dev->dev); - - dma_async_device_unregister(&device->common); - - dma_free_coherent(&dev->dev, plat_data->pool_size, - device->dma_desc_pool_virt, device->dma_desc_pool); - - list_for_each_entry_safe(chan, _chan, &device->common.channels, - device_node) { - iop_chan = to_iop_adma_chan(chan); - list_del(&chan->device_node); - kfree(iop_chan); - } - kfree(device); - - return 0; -} - -static int iop_adma_probe(struct platform_device *pdev) -{ - struct resource *res; - int ret = 0, i; - struct iop_adma_device *adev; - struct iop_adma_chan *iop_chan; - struct dma_device *dma_dev; - struct iop_adma_platform_data *plat_data = dev_get_platdata(&pdev->dev); - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) - return -ENODEV; - - if (!devm_request_mem_region(&pdev->dev, res->start, - resource_size(res), pdev->name)) - return -EBUSY; - - adev = kzalloc(sizeof(*adev), GFP_KERNEL); - if (!adev) - return -ENOMEM; - dma_dev = &adev->common; - - /* allocate coherent memory for hardware descriptors - * note: writecombine gives slightly better performance, but - * requires that we explicitly flush the writes - */ - adev->dma_desc_pool_virt = dma_alloc_wc(&pdev->dev, - plat_data->pool_size, - &adev->dma_desc_pool, - GFP_KERNEL); - if (!adev->dma_desc_pool_virt) { - ret = -ENOMEM; - goto err_free_adev; - } - - dev_dbg(&pdev->dev, "%s: allocated descriptor pool virt %p phys %pad\n", - __func__, adev->dma_desc_pool_virt, &adev->dma_desc_pool); - - adev->id = plat_data->hw_id; - - /* discover transaction capabilites from the platform data */ - dma_dev->cap_mask = plat_data->cap_mask; - - adev->pdev = pdev; - platform_set_drvdata(pdev, adev); - - INIT_LIST_HEAD(&dma_dev->channels); - - /* set base routines */ - dma_dev->device_alloc_chan_resources = iop_adma_alloc_chan_resources; - dma_dev->device_free_chan_resources = iop_adma_free_chan_resources; - dma_dev->device_tx_status = iop_adma_status; - dma_dev->device_issue_pending = iop_adma_issue_pending; - dma_dev->dev = &pdev->dev; - - /* set prep routines based on capability */ - if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) - dma_dev->device_prep_dma_memcpy = iop_adma_prep_dma_memcpy; - if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) { - dma_dev->max_xor = iop_adma_get_max_xor(); - dma_dev->device_prep_dma_xor = iop_adma_prep_dma_xor; - } - if (dma_has_cap(DMA_XOR_VAL, dma_dev->cap_mask)) - dma_dev->device_prep_dma_xor_val = - iop_adma_prep_dma_xor_val; - if (dma_has_cap(DMA_PQ, dma_dev->cap_mask)) { - dma_set_maxpq(dma_dev, iop_adma_get_max_pq(), 0); - dma_dev->device_prep_dma_pq = iop_adma_prep_dma_pq; - } - if (dma_has_cap(DMA_PQ_VAL, dma_dev->cap_mask)) - dma_dev->device_prep_dma_pq_val = - iop_adma_prep_dma_pq_val; - if (dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask)) - dma_dev->device_prep_dma_interrupt = - iop_adma_prep_dma_interrupt; - - iop_chan = kzalloc(sizeof(*iop_chan), GFP_KERNEL); - if (!iop_chan) { - ret = -ENOMEM; - goto err_free_dma; - } - iop_chan->device = adev; - - iop_chan->mmr_base = devm_ioremap(&pdev->dev, res->start, - resource_size(res)); - if (!iop_chan->mmr_base) { - ret = -ENOMEM; - goto err_free_iop_chan; - } - tasklet_setup(&iop_chan->irq_tasklet, iop_adma_tasklet); - - /* clear errors before enabling interrupts */ - iop_adma_device_clear_err_status(iop_chan); - - for (i = 0; i < 3; i++) { - static const irq_handler_t handler[] = { - iop_adma_eot_handler, - iop_adma_eoc_handler, - iop_adma_err_handler - }; - int irq = platform_get_irq(pdev, i); - if (irq < 0) { - ret = -ENXIO; - goto err_free_iop_chan; - } else { - ret = devm_request_irq(&pdev->dev, irq, - handler[i], 0, pdev->name, iop_chan); - if (ret) - goto err_free_iop_chan; - } - } - - spin_lock_init(&iop_chan->lock); - INIT_LIST_HEAD(&iop_chan->chain); - INIT_LIST_HEAD(&iop_chan->all_slots); - iop_chan->common.device = dma_dev; - dma_cookie_init(&iop_chan->common); - list_add_tail(&iop_chan->common.device_node, &dma_dev->channels); - - if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) { - ret = iop_adma_memcpy_self_test(adev); - dev_dbg(&pdev->dev, "memcpy self test returned %d\n", ret); - if (ret) - goto err_free_iop_chan; - } - - if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) { - ret = iop_adma_xor_val_self_test(adev); - dev_dbg(&pdev->dev, "xor self test returned %d\n", ret); - if (ret) - goto err_free_iop_chan; - } - - if (dma_has_cap(DMA_PQ, dma_dev->cap_mask) && - dma_has_cap(DMA_PQ_VAL, dma_dev->cap_mask)) { - #ifdef CONFIG_RAID6_PQ - ret = iop_adma_pq_zero_sum_self_test(adev); - dev_dbg(&pdev->dev, "pq self test returned %d\n", ret); - #else - /* can not test raid6, so do not publish capability */ - dma_cap_clear(DMA_PQ, dma_dev->cap_mask); - dma_cap_clear(DMA_PQ_VAL, dma_dev->cap_mask); - ret = 0; - #endif - if (ret) - goto err_free_iop_chan; - } - - dev_info(&pdev->dev, "Intel(R) IOP: ( %s%s%s%s%s%s)\n", - dma_has_cap(DMA_PQ, dma_dev->cap_mask) ? "pq " : "", - dma_has_cap(DMA_PQ_VAL, dma_dev->cap_mask) ? "pq_val " : "", - dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "xor " : "", - dma_has_cap(DMA_XOR_VAL, dma_dev->cap_mask) ? "xor_val " : "", - dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask) ? "cpy " : "", - dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask) ? "intr " : ""); - - dma_async_device_register(dma_dev); - goto out; - - err_free_iop_chan: - kfree(iop_chan); - err_free_dma: - dma_free_coherent(&adev->pdev->dev, plat_data->pool_size, - adev->dma_desc_pool_virt, adev->dma_desc_pool); - err_free_adev: - kfree(adev); - out: - return ret; -} - -static void iop_chan_start_null_memcpy(struct iop_adma_chan *iop_chan) -{ - struct iop_adma_desc_slot *sw_desc, *grp_start; - dma_cookie_t cookie; - int slot_cnt, slots_per_op; - - dev_dbg(iop_chan->device->common.dev, "%s\n", __func__); - - spin_lock_bh(&iop_chan->lock); - slot_cnt = iop_chan_memcpy_slot_count(0, &slots_per_op); - sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op); - if (sw_desc) { - grp_start = sw_desc->group_head; - - list_splice_init(&sw_desc->tx_list, &iop_chan->chain); - async_tx_ack(&sw_desc->async_tx); - iop_desc_init_memcpy(grp_start, 0); - iop_desc_set_byte_count(grp_start, iop_chan, 0); - iop_desc_set_dest_addr(grp_start, iop_chan, 0); - iop_desc_set_memcpy_src_addr(grp_start, 0); - - cookie = dma_cookie_assign(&sw_desc->async_tx); - - /* initialize the completed cookie to be less than - * the most recently used cookie - */ - iop_chan->common.completed_cookie = cookie - 1; - - /* channel should not be busy */ - BUG_ON(iop_chan_is_busy(iop_chan)); - - /* clear any prior error-status bits */ - iop_adma_device_clear_err_status(iop_chan); - - /* disable operation */ - iop_chan_disable(iop_chan); - - /* set the descriptor address */ - iop_chan_set_next_descriptor(iop_chan, sw_desc->async_tx.phys); - - /* 1/ don't add pre-chained descriptors - * 2/ dummy read to flush next_desc write - */ - BUG_ON(iop_desc_get_next_desc(sw_desc)); - - /* run the descriptor */ - iop_chan_enable(iop_chan); - } else - dev_err(iop_chan->device->common.dev, - "failed to allocate null descriptor\n"); - spin_unlock_bh(&iop_chan->lock); -} - -static void iop_chan_start_null_xor(struct iop_adma_chan *iop_chan) -{ - struct iop_adma_desc_slot *sw_desc, *grp_start; - dma_cookie_t cookie; - int slot_cnt, slots_per_op; - - dev_dbg(iop_chan->device->common.dev, "%s\n", __func__); - - spin_lock_bh(&iop_chan->lock); - slot_cnt = iop_chan_xor_slot_count(0, 2, &slots_per_op); - sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op); - if (sw_desc) { - grp_start = sw_desc->group_head; - list_splice_init(&sw_desc->tx_list, &iop_chan->chain); - async_tx_ack(&sw_desc->async_tx); - iop_desc_init_null_xor(grp_start, 2, 0); - iop_desc_set_byte_count(grp_start, iop_chan, 0); - iop_desc_set_dest_addr(grp_start, iop_chan, 0); - iop_desc_set_xor_src_addr(grp_start, 0, 0); - iop_desc_set_xor_src_addr(grp_start, 1, 0); - - cookie = dma_cookie_assign(&sw_desc->async_tx); - - /* initialize the completed cookie to be less than - * the most recently used cookie - */ - iop_chan->common.completed_cookie = cookie - 1; - - /* channel should not be busy */ - BUG_ON(iop_chan_is_busy(iop_chan)); - - /* clear any prior error-status bits */ - iop_adma_device_clear_err_status(iop_chan); - - /* disable operation */ - iop_chan_disable(iop_chan); - - /* set the descriptor address */ - iop_chan_set_next_descriptor(iop_chan, sw_desc->async_tx.phys); - - /* 1/ don't add pre-chained descriptors - * 2/ dummy read to flush next_desc write - */ - BUG_ON(iop_desc_get_next_desc(sw_desc)); - - /* run the descriptor */ - iop_chan_enable(iop_chan); - } else - dev_err(iop_chan->device->common.dev, - "failed to allocate null descriptor\n"); - spin_unlock_bh(&iop_chan->lock); -} - -static struct platform_driver iop_adma_driver = { - .probe = iop_adma_probe, - .remove = iop_adma_remove, - .driver = { - .name = "iop-adma", - }, -}; - -module_platform_driver(iop_adma_driver); - -MODULE_AUTHOR("Intel Corporation"); -MODULE_DESCRIPTION("IOP ADMA Engine Driver"); -MODULE_LICENSE("GPL"); -MODULE_ALIAS("platform:iop-adma"); diff --git a/drivers/dma/iop-adma.h b/drivers/dma/iop-adma.h deleted file mode 100644 index d44eabb6f5eb..000000000000 --- a/drivers/dma/iop-adma.h +++ /dev/null @@ -1,914 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright © 2006, Intel Corporation. - */ -#ifndef _ADMA_H -#define _ADMA_H -#include -#include -#include - -/* Memory copy units */ -#define DMA_CCR(chan) (chan->mmr_base + 0x0) -#define DMA_CSR(chan) (chan->mmr_base + 0x4) -#define DMA_DAR(chan) (chan->mmr_base + 0xc) -#define DMA_NDAR(chan) (chan->mmr_base + 0x10) -#define DMA_PADR(chan) (chan->mmr_base + 0x14) -#define DMA_PUADR(chan) (chan->mmr_base + 0x18) -#define DMA_LADR(chan) (chan->mmr_base + 0x1c) -#define DMA_BCR(chan) (chan->mmr_base + 0x20) -#define DMA_DCR(chan) (chan->mmr_base + 0x24) - -/* Application accelerator unit */ -#define AAU_ACR(chan) (chan->mmr_base + 0x0) -#define AAU_ASR(chan) (chan->mmr_base + 0x4) -#define AAU_ADAR(chan) (chan->mmr_base + 0x8) -#define AAU_ANDAR(chan) (chan->mmr_base + 0xc) -#define AAU_SAR(src, chan) (chan->mmr_base + (0x10 + ((src) << 2))) -#define AAU_DAR(chan) (chan->mmr_base + 0x20) -#define AAU_ABCR(chan) (chan->mmr_base + 0x24) -#define AAU_ADCR(chan) (chan->mmr_base + 0x28) -#define AAU_SAR_EDCR(src_edc) (chan->mmr_base + (0x02c + ((src_edc-4) << 2))) -#define AAU_EDCR0_IDX 8 -#define AAU_EDCR1_IDX 17 -#define AAU_EDCR2_IDX 26 - -struct iop3xx_aau_desc_ctrl { - unsigned int int_en:1; - unsigned int blk1_cmd_ctrl:3; - unsigned int blk2_cmd_ctrl:3; - unsigned int blk3_cmd_ctrl:3; - unsigned int blk4_cmd_ctrl:3; - unsigned int blk5_cmd_ctrl:3; - unsigned int blk6_cmd_ctrl:3; - unsigned int blk7_cmd_ctrl:3; - unsigned int blk8_cmd_ctrl:3; - unsigned int blk_ctrl:2; - unsigned int dual_xor_en:1; - unsigned int tx_complete:1; - unsigned int zero_result_err:1; - unsigned int zero_result_en:1; - unsigned int dest_write_en:1; -}; - -struct iop3xx_aau_e_desc_ctrl { - unsigned int reserved:1; - unsigned int blk1_cmd_ctrl:3; - unsigned int blk2_cmd_ctrl:3; - unsigned int blk3_cmd_ctrl:3; - unsigned int blk4_cmd_ctrl:3; - unsigned int blk5_cmd_ctrl:3; - unsigned int blk6_cmd_ctrl:3; - unsigned int blk7_cmd_ctrl:3; - unsigned int blk8_cmd_ctrl:3; - unsigned int reserved2:7; -}; - -struct iop3xx_dma_desc_ctrl { - unsigned int pci_transaction:4; - unsigned int int_en:1; - unsigned int dac_cycle_en:1; - unsigned int mem_to_mem_en:1; - unsigned int crc_data_tx_en:1; - unsigned int crc_gen_en:1; - unsigned int crc_seed_dis:1; - unsigned int reserved:21; - unsigned int crc_tx_complete:1; -}; - -struct iop3xx_desc_dma { - u32 next_desc; - union { - u32 pci_src_addr; - u32 pci_dest_addr; - u32 src_addr; - }; - union { - u32 upper_pci_src_addr; - u32 upper_pci_dest_addr; - }; - union { - u32 local_pci_src_addr; - u32 local_pci_dest_addr; - u32 dest_addr; - }; - u32 byte_count; - union { - u32 desc_ctrl; - struct iop3xx_dma_desc_ctrl desc_ctrl_field; - }; - u32 crc_addr; -}; - -struct iop3xx_desc_aau { - u32 next_desc; - u32 src[4]; - u32 dest_addr; - u32 byte_count; - union { - u32 desc_ctrl; - struct iop3xx_aau_desc_ctrl desc_ctrl_field; - }; - union { - u32 src_addr; - u32 e_desc_ctrl; - struct iop3xx_aau_e_desc_ctrl e_desc_ctrl_field; - } src_edc[31]; -}; - -struct iop3xx_aau_gfmr { - unsigned int gfmr1:8; - unsigned int gfmr2:8; - unsigned int gfmr3:8; - unsigned int gfmr4:8; -}; - -struct iop3xx_desc_pq_xor { - u32 next_desc; - u32 src[3]; - union { - u32 data_mult1; - struct iop3xx_aau_gfmr data_mult1_field; - }; - u32 dest_addr; - u32 byte_count; - union { - u32 desc_ctrl; - struct iop3xx_aau_desc_ctrl desc_ctrl_field; - }; - union { - u32 src_addr; - u32 e_desc_ctrl; - struct iop3xx_aau_e_desc_ctrl e_desc_ctrl_field; - u32 data_multiplier; - struct iop3xx_aau_gfmr data_mult_field; - u32 reserved; - } src_edc_gfmr[19]; -}; - -struct iop3xx_desc_dual_xor { - u32 next_desc; - u32 src0_addr; - u32 src1_addr; - u32 h_src_addr; - u32 d_src_addr; - u32 h_dest_addr; - u32 byte_count; - union { - u32 desc_ctrl; - struct iop3xx_aau_desc_ctrl desc_ctrl_field; - }; - u32 d_dest_addr; -}; - -union iop3xx_desc { - struct iop3xx_desc_aau *aau; - struct iop3xx_desc_dma *dma; - struct iop3xx_desc_pq_xor *pq_xor; - struct iop3xx_desc_dual_xor *dual_xor; - void *ptr; -}; - -/* No support for p+q operations */ -static inline int -iop_chan_pq_slot_count(size_t len, int src_cnt, int *slots_per_op) -{ - BUG(); - return 0; -} - -static inline void -iop_desc_init_pq(struct iop_adma_desc_slot *desc, int src_cnt, - unsigned long flags) -{ - BUG(); -} - -static inline void -iop_desc_set_pq_addr(struct iop_adma_desc_slot *desc, dma_addr_t *addr) -{ - BUG(); -} - -static inline void -iop_desc_set_pq_src_addr(struct iop_adma_desc_slot *desc, int src_idx, - dma_addr_t addr, unsigned char coef) -{ - BUG(); -} - -static inline int -iop_chan_pq_zero_sum_slot_count(size_t len, int src_cnt, int *slots_per_op) -{ - BUG(); - return 0; -} - -static inline void -iop_desc_init_pq_zero_sum(struct iop_adma_desc_slot *desc, int src_cnt, - unsigned long flags) -{ - BUG(); -} - -static inline void -iop_desc_set_pq_zero_sum_byte_count(struct iop_adma_desc_slot *desc, u32 len) -{ - BUG(); -} - -#define iop_desc_set_pq_zero_sum_src_addr iop_desc_set_pq_src_addr - -static inline void -iop_desc_set_pq_zero_sum_addr(struct iop_adma_desc_slot *desc, int pq_idx, - dma_addr_t *src) -{ - BUG(); -} - -static inline int iop_adma_get_max_xor(void) -{ - return 32; -} - -static inline int iop_adma_get_max_pq(void) -{ - BUG(); - return 0; -} - -static inline u32 iop_chan_get_current_descriptor(struct iop_adma_chan *chan) -{ - int id = chan->device->id; - - switch (id) { - case DMA0_ID: - case DMA1_ID: - return __raw_readl(DMA_DAR(chan)); - case AAU_ID: - return __raw_readl(AAU_ADAR(chan)); - default: - BUG(); - } - return 0; -} - -static inline void iop_chan_set_next_descriptor(struct iop_adma_chan *chan, - u32 next_desc_addr) -{ - int id = chan->device->id; - - switch (id) { - case DMA0_ID: - case DMA1_ID: - __raw_writel(next_desc_addr, DMA_NDAR(chan)); - break; - case AAU_ID: - __raw_writel(next_desc_addr, AAU_ANDAR(chan)); - break; - } - -} - -#define IOP_ADMA_STATUS_BUSY (1 << 10) -#define IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT (1024) -#define IOP_ADMA_XOR_MAX_BYTE_COUNT (16 * 1024 * 1024) -#define IOP_ADMA_MAX_BYTE_COUNT (16 * 1024 * 1024) - -static inline int iop_chan_is_busy(struct iop_adma_chan *chan) -{ - u32 status = __raw_readl(DMA_CSR(chan)); - return (status & IOP_ADMA_STATUS_BUSY) ? 1 : 0; -} - -static inline int iop_desc_is_aligned(struct iop_adma_desc_slot *desc, - int num_slots) -{ - /* num_slots will only ever be 1, 2, 4, or 8 */ - return (desc->idx & (num_slots - 1)) ? 0 : 1; -} - -/* to do: support large (i.e. > hw max) buffer sizes */ -static inline int iop_chan_memcpy_slot_count(size_t len, int *slots_per_op) -{ - *slots_per_op = 1; - return 1; -} - -/* to do: support large (i.e. > hw max) buffer sizes */ -static inline int iop_chan_memset_slot_count(size_t len, int *slots_per_op) -{ - *slots_per_op = 1; - return 1; -} - -static inline int iop3xx_aau_xor_slot_count(size_t len, int src_cnt, - int *slots_per_op) -{ - static const char slot_count_table[] = { - 1, 1, 1, 1, /* 01 - 04 */ - 2, 2, 2, 2, /* 05 - 08 */ - 4, 4, 4, 4, /* 09 - 12 */ - 4, 4, 4, 4, /* 13 - 16 */ - 8, 8, 8, 8, /* 17 - 20 */ - 8, 8, 8, 8, /* 21 - 24 */ - 8, 8, 8, 8, /* 25 - 28 */ - 8, 8, 8, 8, /* 29 - 32 */ - }; - *slots_per_op = slot_count_table[src_cnt - 1]; - return *slots_per_op; -} - -static inline int -iop_chan_interrupt_slot_count(int *slots_per_op, struct iop_adma_chan *chan) -{ - switch (chan->device->id) { - case DMA0_ID: - case DMA1_ID: - return iop_chan_memcpy_slot_count(0, slots_per_op); - case AAU_ID: - return iop3xx_aau_xor_slot_count(0, 2, slots_per_op); - default: - BUG(); - } - return 0; -} - -static inline int iop_chan_xor_slot_count(size_t len, int src_cnt, - int *slots_per_op) -{ - int slot_cnt = iop3xx_aau_xor_slot_count(len, src_cnt, slots_per_op); - - if (len <= IOP_ADMA_XOR_MAX_BYTE_COUNT) - return slot_cnt; - - len -= IOP_ADMA_XOR_MAX_BYTE_COUNT; - while (len > IOP_ADMA_XOR_MAX_BYTE_COUNT) { - len -= IOP_ADMA_XOR_MAX_BYTE_COUNT; - slot_cnt += *slots_per_op; - } - - slot_cnt += *slots_per_op; - - return slot_cnt; -} - -/* zero sum on iop3xx is limited to 1k at a time so it requires multiple - * descriptors - */ -static inline int iop_chan_zero_sum_slot_count(size_t len, int src_cnt, - int *slots_per_op) -{ - int slot_cnt = iop3xx_aau_xor_slot_count(len, src_cnt, slots_per_op); - - if (len <= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT) - return slot_cnt; - - len -= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT; - while (len > IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT) { - len -= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT; - slot_cnt += *slots_per_op; - } - - slot_cnt += *slots_per_op; - - return slot_cnt; -} - -static inline u32 iop_desc_get_byte_count(struct iop_adma_desc_slot *desc, - struct iop_adma_chan *chan) -{ - union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, }; - - switch (chan->device->id) { - case DMA0_ID: - case DMA1_ID: - return hw_desc.dma->byte_count; - case AAU_ID: - return hw_desc.aau->byte_count; - default: - BUG(); - } - return 0; -} - -/* translate the src_idx to a descriptor word index */ -static inline int __desc_idx(int src_idx) -{ - static const int desc_idx_table[] = { 0, 0, 0, 0, - 0, 1, 2, 3, - 5, 6, 7, 8, - 9, 10, 11, 12, - 14, 15, 16, 17, - 18, 19, 20, 21, - 23, 24, 25, 26, - 27, 28, 29, 30, - }; - - return desc_idx_table[src_idx]; -} - -static inline u32 iop_desc_get_src_addr(struct iop_adma_desc_slot *desc, - struct iop_adma_chan *chan, - int src_idx) -{ - union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, }; - - switch (chan->device->id) { - case DMA0_ID: - case DMA1_ID: - return hw_desc.dma->src_addr; - case AAU_ID: - break; - default: - BUG(); - } - - if (src_idx < 4) - return hw_desc.aau->src[src_idx]; - else - return hw_desc.aau->src_edc[__desc_idx(src_idx)].src_addr; -} - -static inline void iop3xx_aau_desc_set_src_addr(struct iop3xx_desc_aau *hw_desc, - int src_idx, dma_addr_t addr) -{ - if (src_idx < 4) - hw_desc->src[src_idx] = addr; - else - hw_desc->src_edc[__desc_idx(src_idx)].src_addr = addr; -} - -static inline void -iop_desc_init_memcpy(struct iop_adma_desc_slot *desc, unsigned long flags) -{ - struct iop3xx_desc_dma *hw_desc = desc->hw_desc; - union { - u32 value; - struct iop3xx_dma_desc_ctrl field; - } u_desc_ctrl; - - u_desc_ctrl.value = 0; - u_desc_ctrl.field.mem_to_mem_en = 1; - u_desc_ctrl.field.pci_transaction = 0xe; /* memory read block */ - u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT; - hw_desc->desc_ctrl = u_desc_ctrl.value; - hw_desc->upper_pci_src_addr = 0; - hw_desc->crc_addr = 0; -} - -static inline void -iop_desc_init_memset(struct iop_adma_desc_slot *desc, unsigned long flags) -{ - struct iop3xx_desc_aau *hw_desc = desc->hw_desc; - union { - u32 value; - struct iop3xx_aau_desc_ctrl field; - } u_desc_ctrl; - - u_desc_ctrl.value = 0; - u_desc_ctrl.field.blk1_cmd_ctrl = 0x2; /* memory block fill */ - u_desc_ctrl.field.dest_write_en = 1; - u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT; - hw_desc->desc_ctrl = u_desc_ctrl.value; -} - -static inline u32 -iop3xx_desc_init_xor(struct iop3xx_desc_aau *hw_desc, int src_cnt, - unsigned long flags) -{ - int i, shift; - u32 edcr; - union { - u32 value; - struct iop3xx_aau_desc_ctrl field; - } u_desc_ctrl; - - u_desc_ctrl.value = 0; - switch (src_cnt) { - case 25 ... 32: - u_desc_ctrl.field.blk_ctrl = 0x3; /* use EDCR[2:0] */ - edcr = 0; - shift = 1; - for (i = 24; i < src_cnt; i++) { - edcr |= (1 << shift); - shift += 3; - } - hw_desc->src_edc[AAU_EDCR2_IDX].e_desc_ctrl = edcr; - src_cnt = 24; - fallthrough; - case 17 ... 24: - if (!u_desc_ctrl.field.blk_ctrl) { - hw_desc->src_edc[AAU_EDCR2_IDX].e_desc_ctrl = 0; - u_desc_ctrl.field.blk_ctrl = 0x3; /* use EDCR[2:0] */ - } - edcr = 0; - shift = 1; - for (i = 16; i < src_cnt; i++) { - edcr |= (1 << shift); - shift += 3; - } - hw_desc->src_edc[AAU_EDCR1_IDX].e_desc_ctrl = edcr; - src_cnt = 16; - fallthrough; - case 9 ... 16: - if (!u_desc_ctrl.field.blk_ctrl) - u_desc_ctrl.field.blk_ctrl = 0x2; /* use EDCR0 */ - edcr = 0; - shift = 1; - for (i = 8; i < src_cnt; i++) { - edcr |= (1 << shift); - shift += 3; - } - hw_desc->src_edc[AAU_EDCR0_IDX].e_desc_ctrl = edcr; - src_cnt = 8; - fallthrough; - case 2 ... 8: - shift = 1; - for (i = 0; i < src_cnt; i++) { - u_desc_ctrl.value |= (1 << shift); - shift += 3; - } - - if (!u_desc_ctrl.field.blk_ctrl && src_cnt > 4) - u_desc_ctrl.field.blk_ctrl = 0x1; /* use mini-desc */ - } - - u_desc_ctrl.field.dest_write_en = 1; - u_desc_ctrl.field.blk1_cmd_ctrl = 0x7; /* direct fill */ - u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT; - hw_desc->desc_ctrl = u_desc_ctrl.value; - - return u_desc_ctrl.value; -} - -static inline void -iop_desc_init_xor(struct iop_adma_desc_slot *desc, int src_cnt, - unsigned long flags) -{ - iop3xx_desc_init_xor(desc->hw_desc, src_cnt, flags); -} - -/* return the number of operations */ -static inline int -iop_desc_init_zero_sum(struct iop_adma_desc_slot *desc, int src_cnt, - unsigned long flags) -{ - int slot_cnt = desc->slot_cnt, slots_per_op = desc->slots_per_op; - struct iop3xx_desc_aau *hw_desc, *prev_hw_desc, *iter; - union { - u32 value; - struct iop3xx_aau_desc_ctrl field; - } u_desc_ctrl; - int i, j; - - hw_desc = desc->hw_desc; - - for (i = 0, j = 0; (slot_cnt -= slots_per_op) >= 0; - i += slots_per_op, j++) { - iter = iop_hw_desc_slot_idx(hw_desc, i); - u_desc_ctrl.value = iop3xx_desc_init_xor(iter, src_cnt, flags); - u_desc_ctrl.field.dest_write_en = 0; - u_desc_ctrl.field.zero_result_en = 1; - u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT; - iter->desc_ctrl = u_desc_ctrl.value; - - /* for the subsequent descriptors preserve the store queue - * and chain them together - */ - if (i) { - prev_hw_desc = - iop_hw_desc_slot_idx(hw_desc, i - slots_per_op); - prev_hw_desc->next_desc = - (u32) (desc->async_tx.phys + (i << 5)); - } - } - - return j; -} - -static inline void -iop_desc_init_null_xor(struct iop_adma_desc_slot *desc, int src_cnt, - unsigned long flags) -{ - struct iop3xx_desc_aau *hw_desc = desc->hw_desc; - union { - u32 value; - struct iop3xx_aau_desc_ctrl field; - } u_desc_ctrl; - - u_desc_ctrl.value = 0; - switch (src_cnt) { - case 25 ... 32: - u_desc_ctrl.field.blk_ctrl = 0x3; /* use EDCR[2:0] */ - hw_desc->src_edc[AAU_EDCR2_IDX].e_desc_ctrl = 0; - fallthrough; - case 17 ... 24: - if (!u_desc_ctrl.field.blk_ctrl) { - hw_desc->src_edc[AAU_EDCR2_IDX].e_desc_ctrl = 0; - u_desc_ctrl.field.blk_ctrl = 0x3; /* use EDCR[2:0] */ - } - hw_desc->src_edc[AAU_EDCR1_IDX].e_desc_ctrl = 0; - fallthrough; - case 9 ... 16: - if (!u_desc_ctrl.field.blk_ctrl) - u_desc_ctrl.field.blk_ctrl = 0x2; /* use EDCR0 */ - hw_desc->src_edc[AAU_EDCR0_IDX].e_desc_ctrl = 0; - fallthrough; - case 1 ... 8: - if (!u_desc_ctrl.field.blk_ctrl && src_cnt > 4) - u_desc_ctrl.field.blk_ctrl = 0x1; /* use mini-desc */ - } - - u_desc_ctrl.field.dest_write_en = 0; - u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT; - hw_desc->desc_ctrl = u_desc_ctrl.value; -} - -static inline void iop_desc_set_byte_count(struct iop_adma_desc_slot *desc, - struct iop_adma_chan *chan, - u32 byte_count) -{ - union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, }; - - switch (chan->device->id) { - case DMA0_ID: - case DMA1_ID: - hw_desc.dma->byte_count = byte_count; - break; - case AAU_ID: - hw_desc.aau->byte_count = byte_count; - break; - default: - BUG(); - } -} - -static inline void -iop_desc_init_interrupt(struct iop_adma_desc_slot *desc, - struct iop_adma_chan *chan) -{ - union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, }; - - switch (chan->device->id) { - case DMA0_ID: - case DMA1_ID: - iop_desc_init_memcpy(desc, 1); - hw_desc.dma->byte_count = 0; - hw_desc.dma->dest_addr = 0; - hw_desc.dma->src_addr = 0; - break; - case AAU_ID: - iop_desc_init_null_xor(desc, 2, 1); - hw_desc.aau->byte_count = 0; - hw_desc.aau->dest_addr = 0; - hw_desc.aau->src[0] = 0; - hw_desc.aau->src[1] = 0; - break; - default: - BUG(); - } -} - -static inline void -iop_desc_set_zero_sum_byte_count(struct iop_adma_desc_slot *desc, u32 len) -{ - int slots_per_op = desc->slots_per_op; - struct iop3xx_desc_aau *hw_desc = desc->hw_desc, *iter; - int i = 0; - - if (len <= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT) { - hw_desc->byte_count = len; - } else { - do { - iter = iop_hw_desc_slot_idx(hw_desc, i); - iter->byte_count = IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT; - len -= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT; - i += slots_per_op; - } while (len > IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT); - - iter = iop_hw_desc_slot_idx(hw_desc, i); - iter->byte_count = len; - } -} - -static inline void iop_desc_set_dest_addr(struct iop_adma_desc_slot *desc, - struct iop_adma_chan *chan, - dma_addr_t addr) -{ - union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, }; - - switch (chan->device->id) { - case DMA0_ID: - case DMA1_ID: - hw_desc.dma->dest_addr = addr; - break; - case AAU_ID: - hw_desc.aau->dest_addr = addr; - break; - default: - BUG(); - } -} - -static inline void iop_desc_set_memcpy_src_addr(struct iop_adma_desc_slot *desc, - dma_addr_t addr) -{ - struct iop3xx_desc_dma *hw_desc = desc->hw_desc; - hw_desc->src_addr = addr; -} - -static inline void -iop_desc_set_zero_sum_src_addr(struct iop_adma_desc_slot *desc, int src_idx, - dma_addr_t addr) -{ - - struct iop3xx_desc_aau *hw_desc = desc->hw_desc, *iter; - int slot_cnt = desc->slot_cnt, slots_per_op = desc->slots_per_op; - int i; - - for (i = 0; (slot_cnt -= slots_per_op) >= 0; - i += slots_per_op, addr += IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT) { - iter = iop_hw_desc_slot_idx(hw_desc, i); - iop3xx_aau_desc_set_src_addr(iter, src_idx, addr); - } -} - -static inline void iop_desc_set_xor_src_addr(struct iop_adma_desc_slot *desc, - int src_idx, dma_addr_t addr) -{ - - struct iop3xx_desc_aau *hw_desc = desc->hw_desc, *iter; - int slot_cnt = desc->slot_cnt, slots_per_op = desc->slots_per_op; - int i; - - for (i = 0; (slot_cnt -= slots_per_op) >= 0; - i += slots_per_op, addr += IOP_ADMA_XOR_MAX_BYTE_COUNT) { - iter = iop_hw_desc_slot_idx(hw_desc, i); - iop3xx_aau_desc_set_src_addr(iter, src_idx, addr); - } -} - -static inline void iop_desc_set_next_desc(struct iop_adma_desc_slot *desc, - u32 next_desc_addr) -{ - /* hw_desc->next_desc is the same location for all channels */ - union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, }; - - iop_paranoia(hw_desc.dma->next_desc); - hw_desc.dma->next_desc = next_desc_addr; -} - -static inline u32 iop_desc_get_next_desc(struct iop_adma_desc_slot *desc) -{ - /* hw_desc->next_desc is the same location for all channels */ - union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, }; - return hw_desc.dma->next_desc; -} - -static inline void iop_desc_clear_next_desc(struct iop_adma_desc_slot *desc) -{ - /* hw_desc->next_desc is the same location for all channels */ - union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, }; - hw_desc.dma->next_desc = 0; -} - -static inline void iop_desc_set_block_fill_val(struct iop_adma_desc_slot *desc, - u32 val) -{ - struct iop3xx_desc_aau *hw_desc = desc->hw_desc; - hw_desc->src[0] = val; -} - -static inline enum sum_check_flags -iop_desc_get_zero_result(struct iop_adma_desc_slot *desc) -{ - struct iop3xx_desc_aau *hw_desc = desc->hw_desc; - struct iop3xx_aau_desc_ctrl desc_ctrl = hw_desc->desc_ctrl_field; - - iop_paranoia(!(desc_ctrl.tx_complete && desc_ctrl.zero_result_en)); - return desc_ctrl.zero_result_err << SUM_CHECK_P; -} - -static inline void iop_chan_append(struct iop_adma_chan *chan) -{ - u32 dma_chan_ctrl; - - dma_chan_ctrl = __raw_readl(DMA_CCR(chan)); - dma_chan_ctrl |= 0x2; - __raw_writel(dma_chan_ctrl, DMA_CCR(chan)); -} - -static inline u32 iop_chan_get_status(struct iop_adma_chan *chan) -{ - return __raw_readl(DMA_CSR(chan)); -} - -static inline void iop_chan_disable(struct iop_adma_chan *chan) -{ - u32 dma_chan_ctrl = __raw_readl(DMA_CCR(chan)); - dma_chan_ctrl &= ~1; - __raw_writel(dma_chan_ctrl, DMA_CCR(chan)); -} - -static inline void iop_chan_enable(struct iop_adma_chan *chan) -{ - u32 dma_chan_ctrl = __raw_readl(DMA_CCR(chan)); - - dma_chan_ctrl |= 1; - __raw_writel(dma_chan_ctrl, DMA_CCR(chan)); -} - -static inline void iop_adma_device_clear_eot_status(struct iop_adma_chan *chan) -{ - u32 status = __raw_readl(DMA_CSR(chan)); - status &= (1 << 9); - __raw_writel(status, DMA_CSR(chan)); -} - -static inline void iop_adma_device_clear_eoc_status(struct iop_adma_chan *chan) -{ - u32 status = __raw_readl(DMA_CSR(chan)); - status &= (1 << 8); - __raw_writel(status, DMA_CSR(chan)); -} - -static inline void iop_adma_device_clear_err_status(struct iop_adma_chan *chan) -{ - u32 status = __raw_readl(DMA_CSR(chan)); - - switch (chan->device->id) { - case DMA0_ID: - case DMA1_ID: - status &= (1 << 5) | (1 << 3) | (1 << 2) | (1 << 1); - break; - case AAU_ID: - status &= (1 << 5); - break; - default: - BUG(); - } - - __raw_writel(status, DMA_CSR(chan)); -} - -static inline int -iop_is_err_int_parity(unsigned long status, struct iop_adma_chan *chan) -{ - return 0; -} - -static inline int -iop_is_err_mcu_abort(unsigned long status, struct iop_adma_chan *chan) -{ - return 0; -} - -static inline int -iop_is_err_int_tabort(unsigned long status, struct iop_adma_chan *chan) -{ - return 0; -} - -static inline int -iop_is_err_int_mabort(unsigned long status, struct iop_adma_chan *chan) -{ - return test_bit(5, &status); -} - -static inline int -iop_is_err_pci_tabort(unsigned long status, struct iop_adma_chan *chan) -{ - switch (chan->device->id) { - case DMA0_ID: - case DMA1_ID: - return test_bit(2, &status); - default: - return 0; - } -} - -static inline int -iop_is_err_pci_mabort(unsigned long status, struct iop_adma_chan *chan) -{ - switch (chan->device->id) { - case DMA0_ID: - case DMA1_ID: - return test_bit(3, &status); - default: - return 0; - } -} - -static inline int -iop_is_err_split_tx(unsigned long status, struct iop_adma_chan *chan) -{ - switch (chan->device->id) { - case DMA0_ID: - case DMA1_ID: - return test_bit(1, &status); - default: - return 0; - } -} -#endif /* _ADMA_H */ From patchwork Wed Oct 19 15:03:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnd Bergmann X-Patchwork-Id: 5688 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp385964wrs; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id y88-20020a50bb61000000b0045bdff8a884si13276590ede.268.2022.10.19.08.23.15; Wed, 19 Oct 2022 08:23:40 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=imyorfyg; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230475AbiJSPWd (ORCPT + 99 others); Wed, 19 Oct 2022 11:22:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47578 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232459AbiJSPWG (ORCPT ); Wed, 19 Oct 2022 11:22:06 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B9E1F1D63B5; Wed, 19 Oct 2022 08:15:45 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 91C21B8223A; Wed, 19 Oct 2022 15:14:27 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id AA2D8C433C1; Wed, 19 Oct 2022 15:14:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1666192466; bh=oHhISD/CzMUmkWxHqFyoeUe7ZEcONDoFgdgwOoTRBYs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=imyorfygSIZT3yoeStIWjdN3TSeMWYmRlMZ5hnwx97K39seFcDJYd12q38IubJHar 1qrliULXdMJdBzD5H0lBgje3cgh9fKgzmKm4mmkoitABTbXSrSenqG4Du4mGdkCj6R Wn6IkxkwMKWuT548PQqxHvxw/bhQ29df97xDZuYoLgvpp+0D/u8+7i/dReAFeNWd+U mmLXsM3WmS/lCICWEOP6bwONhJVCnEU8Bsnrde/lmLFVsqZr//Su2g18+OPbQpY1Zl OjFSCLOTXrexFqt3heo6E0QaYXRZJcmJO+mewQ7KPxHOke+LQVWjIHVJm+vd5vyluI 5VpU7GS7gJshA== From: Arnd Bergmann To: linux-arm-kernel@lists.infradead.org, Linus Walleij , Bartosz Golaszewski Cc: linux-kernel@vger.kernel.org, Arnd Bergmann , Lennert Buytenhek , linux-gpio@vger.kernel.org Subject: [PATCH 11/17] gpio: remove iop driver Date: Wed, 19 Oct 2022 17:03:33 +0200 Message-Id: <20221019150410.3851944-11-arnd@kernel.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20221019150410.3851944-1-arnd@kernel.org> References: <20221019144119.3848027-1-arnd@kernel.org> <20221019150410.3851944-1-arnd@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747130012401809477?= X-GMAIL-MSGID: =?utf-8?q?1747130012401809477?= From: Arnd Bergmann The iop32x platform was removed, and its gpio driver is now orphaned. Cc: Lennert Buytenhek Signed-off-by: Arnd Bergmann Acked-by: Linus Walleij Acked-by: Bartosz Golaszewski --- drivers/gpio/Kconfig | 10 ------- drivers/gpio/Makefile | 1 - drivers/gpio/gpio-iop.c | 59 ----------------------------------------- 3 files changed, 70 deletions(-) delete mode 100644 drivers/gpio/gpio-iop.c diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index a01af1180616..30a2b4214472 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -345,16 +345,6 @@ config GPIO_IMX_SCU def_bool y depends on IMX_SCU -config GPIO_IOP - tristate "Intel IOP GPIO" - depends on ARCH_IOP32X || COMPILE_TEST - select GPIO_GENERIC - help - Say yes here to support the GPIO functionality of a number of Intel - IOP32X or IOP33X series of chips. - - If unsure, say N. - config GPIO_IXP4XX bool "Intel IXP4xx GPIO" depends on ARCH_IXP4XX diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 29e3beb6548c..b8c2ebc4bc87 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -70,7 +70,6 @@ obj-$(CONFIG_GPIO_I8255) += gpio-i8255.o obj-$(CONFIG_GPIO_ICH) += gpio-ich.o obj-$(CONFIG_GPIO_IDT3243X) += gpio-idt3243x.o obj-$(CONFIG_GPIO_IMX_SCU) += gpio-imx-scu.o -obj-$(CONFIG_GPIO_IOP) += gpio-iop.o obj-$(CONFIG_GPIO_IT87) += gpio-it87.o obj-$(CONFIG_GPIO_IXP4XX) += gpio-ixp4xx.o obj-$(CONFIG_GPIO_JANZ_TTL) += gpio-janz-ttl.o diff --git a/drivers/gpio/gpio-iop.c b/drivers/gpio/gpio-iop.c deleted file mode 100644 index 7390b5ca09e3..000000000000 --- a/drivers/gpio/gpio-iop.c +++ /dev/null @@ -1,59 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * arch/arm/plat-iop/gpio.c - * GPIO handling for Intel IOP3xx processors. - * - * Copyright (C) 2006 Lennert Buytenhek - */ - -#include -#include -#include -#include - -#define IOP3XX_GPOE 0x0000 -#define IOP3XX_GPID 0x0004 -#define IOP3XX_GPOD 0x0008 - -static int iop3xx_gpio_probe(struct platform_device *pdev) -{ - struct gpio_chip *gc; - void __iomem *base; - int err; - - gc = devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL); - if (!gc) - return -ENOMEM; - - base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); - - err = bgpio_init(gc, &pdev->dev, 1, base + IOP3XX_GPID, - base + IOP3XX_GPOD, NULL, NULL, base + IOP3XX_GPOE, 0); - if (err) - return err; - - gc->base = 0; - gc->owner = THIS_MODULE; - gc->label = "gpio-iop"; - - return devm_gpiochip_add_data(&pdev->dev, gc, NULL); -} - -static struct platform_driver iop3xx_gpio_driver = { - .driver = { - .name = "gpio-iop", - }, - .probe = iop3xx_gpio_probe, -}; - -static int __init iop3xx_gpio_init(void) -{ - return platform_driver_register(&iop3xx_gpio_driver); -} -arch_initcall(iop3xx_gpio_init); - -MODULE_DESCRIPTION("GPIO handling for Intel IOP3xx processors"); -MODULE_AUTHOR("Lennert Buytenhek "); -MODULE_LICENSE("GPL"); From patchwork Wed Oct 19 15:03:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnd Bergmann X-Patchwork-Id: 5692 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp387758wrs; Wed, 19 Oct 2022 08:27:27 -0700 (PDT) X-Google-Smtp-Source: AMsMyM7ek+UL2EpBbYe7dZ4mwP8fPdEWL/pJhaB6lUxpONP+6AR9Moh1i9uDFtRXczRup8L0V6YO X-Received: by 2002:a17:902:b944:b0:179:fdb0:1c39 with SMTP id h4-20020a170902b94400b00179fdb01c39mr9020625pls.98.1666193247091; Wed, 19 Oct 2022 08:27:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666193247; cv=none; d=google.com; s=arc-20160816; b=uqlaIbhRoF2TJhy3Ab7O2Jj18sa2o+ZgEM9FrDvl7DQFfwgYhr3TYFzI8lW7ReW6n3 rXay81LdNWCMaEavtkD49uultw2plGvBAkhg14nDIBOlKG0Sx6Rx5DyAxDm939sehW6i MoTxlARCjVpXcd4eVT/AGjsJLb/DfArraGiQGRkGAvGKBpL9A9/Xd6PS3VRI9ddHKOnS +luTi7JExJGg5Yk0jiNyjdksHBP/wSHcK4d94tnU3gOjfXGiMWanGmG5HXAq09CRC36A 85g/vxHohstSCuL1O6F7a1mwMvZSEOiTiPJn7zgjPb9dvpDbC7Iefz34t5EUmtnccv3Q HmeQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=a/vGg+5kVsRu9SE4me2Zoy0ULM8CSWndMNlkaKRF9JA=; b=XvQFgTb91CM8ahumt4knth4KkeBzqGnnucvIZ08Kb6CkF7klk4n7GYFcaboyyptaug TjFWNN6tpKXhRl4Tng/ONNuTxV2s8nfWr9wlimLYErSMWI3v2i4YICZz7+kpFmhb1IuU nE4PNnFJ+Ke+Fmx8wogYI5rotBQWttmtKhoi2wiH3QKDS3X6xt4KBqrI9+m/j2AaoZEU H1GO1agV0D3QFyyVfID61PNwowoVFtq+ty6Cxj6xvgE+sx8z4TwcBtJT9gMxoNIUjxV2 jMrYRCPF4WJFDYP+WCmJmY3vF27QdwNNKi+OCFohuWTgm+0yDnlKRtViXmLwsThTOK/X K5Qg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=Tkz9T1EI; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id c20-20020a6566d4000000b0043c8ce98a7bsi19798076pgw.802.2022.10.19.08.27.12; Wed, 19 Oct 2022 08:27:27 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=Tkz9T1EI; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231865AbiJSPXc (ORCPT + 99 others); Wed, 19 Oct 2022 11:23:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50028 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232255AbiJSPXI (ORCPT ); Wed, 19 Oct 2022 11:23:08 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 35805181D81; Wed, 19 Oct 2022 08:16:30 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id A9BCA61926; Wed, 19 Oct 2022 15:15:29 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5250DC433C1; Wed, 19 Oct 2022 15:15:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1666192529; bh=jh5ENpwOfOajzp/RAT8KoyE5+r8fU/7pYZZ4l1bhcY8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Tkz9T1EIZMo+85cUiKEcBcvYEi3uEo7GZQ5QNZFTHr9qNQZ+5Lh5pHWJZ45FOsvoi Utv8Qq+9N1SNXxbbSXx6sGawowMVM51e1/I/b63VbUoVZr0aP8JAoTr9BnW7PDaDSk TAGoDYr8xjHBjAsVKMHlC/1gAZFfXHglinXbDmYyYXtDC6A2L5rXobSzT6Cc9CWQNa mdPehRo1kjV9FOPfQDSTdgcAmhUwkyk4eXKrcAITibgXMJvtRyJQk0yAmU63Xtz2WS KFO1Y4tjsHhofW4TVWxe9SroP0YlMzUy+ghQsrfmKEPN9wBtal1vChOeV2Bdtl1/hk YI7QV7tSZDH5g== From: Arnd Bergmann To: linux-arm-kernel@lists.infradead.org, Wim Van Sebroeck , Guenter Roeck Cc: linux-kernel@vger.kernel.org, Arnd Bergmann , Russell King , Linus Walleij , linux-watchdog@vger.kernel.org Subject: [PATCH 12/17] ARM: footbridge: remove CATS Date: Wed, 19 Oct 2022 17:03:34 +0200 Message-Id: <20221019150410.3851944-12-arnd@kernel.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20221019150410.3851944-1-arnd@kernel.org> References: <20221019144119.3848027-1-arnd@kernel.org> <20221019150410.3851944-1-arnd@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS,SUSPICIOUS_RECIPS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747130249881334319?= X-GMAIL-MSGID: =?utf-8?q?1747130249881334319?= From: Arnd Bergmann Nobody seems to have a CATS machine any more, so remove it now, leaving only NetWinder and EBSA285. Cc: Russell King Signed-off-by: Arnd Bergmann Acked-by: Linus Walleij --- arch/arm/kernel/head.S | 2 +- arch/arm/mach-footbridge/Kconfig | 12 ---- arch/arm/mach-footbridge/Makefile | 2 - arch/arm/mach-footbridge/cats-hw.c | 98 ----------------------------- arch/arm/mach-footbridge/cats-pci.c | 64 ------------------- arch/arm/mach-footbridge/common.c | 3 - drivers/watchdog/wdt285.c | 2 - 7 files changed, 1 insertion(+), 182 deletions(-) delete mode 100644 arch/arm/mach-footbridge/cats-hw.c delete mode 100644 arch/arm/mach-footbridge/cats-pci.c diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index 29e2900178a1..656991055bc1 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S @@ -344,7 +344,7 @@ __create_page_tables: ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags #endif -#if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS) +#if defined(CONFIG_ARCH_NETWINDER) /* * If we're using the NetWinder or CATS, we also need to map * in the 16550-type serial port for the debug messages diff --git a/arch/arm/mach-footbridge/Kconfig b/arch/arm/mach-footbridge/Kconfig index b5e7cbfed119..78189997caa1 100644 --- a/arch/arm/mach-footbridge/Kconfig +++ b/arch/arm/mach-footbridge/Kconfig @@ -16,18 +16,6 @@ menuconfig ARCH_FOOTBRIDGE if ARCH_FOOTBRIDGE -config ARCH_CATS - bool "CATS" - depends on UNUSED_BOARD_FILES - select CLKEVT_I8253 - select CLKSRC_I8253 - select ISA - select FORCE_PCI - help - Say Y here if you intend to run this kernel on the CATS. - - Saying N will reduce the size of the Footbridge kernel. - config ARCH_EBSA285_HOST bool "EBSA285 (host mode)" select ARCH_EBSA285 diff --git a/arch/arm/mach-footbridge/Makefile b/arch/arm/mach-footbridge/Makefile index 55d570739f19..1553cc01b45c 100644 --- a/arch/arm/mach-footbridge/Makefile +++ b/arch/arm/mach-footbridge/Makefile @@ -8,11 +8,9 @@ obj-y := common.o isa-irq.o isa.o isa-rtc.o dma-isa.o pci-y += dc21285.o -pci-$(CONFIG_ARCH_CATS) += cats-pci.o pci-$(CONFIG_ARCH_EBSA285) += ebsa285-pci.o pci-$(CONFIG_ARCH_NETWINDER) += netwinder-pci.o -obj-$(CONFIG_ARCH_CATS) += cats-hw.o isa-timer.o obj-$(CONFIG_ARCH_EBSA285) += ebsa285.o dc21285-timer.o obj-$(CONFIG_ARCH_NETWINDER) += netwinder-hw.o isa-timer.o diff --git a/arch/arm/mach-footbridge/cats-hw.c b/arch/arm/mach-footbridge/cats-hw.c deleted file mode 100644 index e575dc0698cd..000000000000 --- a/arch/arm/mach-footbridge/cats-hw.c +++ /dev/null @@ -1,98 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * linux/arch/arm/mach-footbridge/cats-hw.c - * - * CATS machine fixup - * - * Copyright (C) 1998, 1999 Russell King, Phil Blundell - */ -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include - -#include "common.h" - -#define CFG_PORT 0x370 -#define INDEX_PORT (CFG_PORT) -#define DATA_PORT (CFG_PORT + 1) - -static int __init cats_hw_init(void) -{ - if (machine_is_cats()) { - /* Set Aladdin to CONFIGURE mode */ - outb(0x51, CFG_PORT); - outb(0x23, CFG_PORT); - - /* Select logical device 3 */ - outb(0x07, INDEX_PORT); - outb(0x03, DATA_PORT); - - /* Set parallel port to DMA channel 3, ECP+EPP1.9, - enable EPP timeout */ - outb(0x74, INDEX_PORT); - outb(0x03, DATA_PORT); - - outb(0xf0, INDEX_PORT); - outb(0x0f, DATA_PORT); - - outb(0xf1, INDEX_PORT); - outb(0x07, DATA_PORT); - - /* Select logical device 4 */ - outb(0x07, INDEX_PORT); - outb(0x04, DATA_PORT); - - /* UART1 high speed mode */ - outb(0xf0, INDEX_PORT); - outb(0x02, DATA_PORT); - - /* Select logical device 5 */ - outb(0x07, INDEX_PORT); - outb(0x05, DATA_PORT); - - /* UART2 high speed mode */ - outb(0xf0, INDEX_PORT); - outb(0x02, DATA_PORT); - - /* Set Aladdin to RUN mode */ - outb(0xbb, CFG_PORT); - } - - return 0; -} - -__initcall(cats_hw_init); - -/* - * CATS uses soft-reboot by default, since - * hard reboots fail on early boards. - */ -static void __init -fixup_cats(struct tag *tags, char **cmdline) -{ -#if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE) - screen_info.orig_video_lines = 25; - screen_info.orig_video_points = 16; - screen_info.orig_y = 24; -#endif -} - -MACHINE_START(CATS, "Chalice-CATS") - /* Maintainer: Philip Blundell */ - .atag_offset = 0x100, - .reboot_mode = REBOOT_SOFT, - .fixup = fixup_cats, - .map_io = footbridge_map_io, - .init_irq = footbridge_init_irq, - .init_time = isa_timer_init, - .restart = footbridge_restart, -MACHINE_END diff --git a/arch/arm/mach-footbridge/cats-pci.c b/arch/arm/mach-footbridge/cats-pci.c deleted file mode 100644 index 90b1e9be430e..000000000000 --- a/arch/arm/mach-footbridge/cats-pci.c +++ /dev/null @@ -1,64 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * linux/arch/arm/mach-footbridge/cats-pci.c - * - * PCI bios-type initialisation for PCI machines - * - * Bits taken from various places. - */ -#include -#include -#include - -#include -#include -#include - -/* cats host-specific stuff */ -static int irqmap_cats[] = { IRQ_PCI, IRQ_IN0, IRQ_IN1, IRQ_IN3 }; - -static u8 cats_no_swizzle(struct pci_dev *dev, u8 *pin) -{ - return 0; -} - -static int cats_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - if (dev->irq >= 255) - return -1; /* not a valid interrupt. */ - - if (dev->irq >= 128) - return dev->irq & 0x1f; - - if (dev->irq >= 1 && dev->irq <= 4) - return irqmap_cats[dev->irq - 1]; - - if (dev->irq != 0) - printk("PCI: device %02x:%02x has unknown irq line %x\n", - dev->bus->number, dev->devfn, dev->irq); - - return -1; -} - -/* - * why not the standard PCI swizzle? does this prevent 4-port tulip - * cards being used (ie, pci-pci bridge based cards)? - */ -static struct hw_pci cats_pci __initdata = { - .swizzle = cats_no_swizzle, - .map_irq = cats_map_irq, - .nr_controllers = 1, - .ops = &dc21285_ops, - .setup = dc21285_setup, - .preinit = dc21285_preinit, - .postinit = dc21285_postinit, -}; - -static int __init cats_pci_init(void) -{ - if (machine_is_cats()) - pci_common_init(&cats_pci); - return 0; -} - -subsys_initcall(cats_pci_init); diff --git a/arch/arm/mach-footbridge/common.c b/arch/arm/mach-footbridge/common.c index 629e4676ed77..85c598708c10 100644 --- a/arch/arm/mach-footbridge/common.c +++ b/arch/arm/mach-footbridge/common.c @@ -206,9 +206,6 @@ void __init footbridge_init_irq(void) */ isa_init_irq(IRQ_PCI); - if (machine_is_cats()) - isa_init_irq(IRQ_IN2); - if (machine_is_netwinder()) isa_init_irq(IRQ_IN3); } diff --git a/drivers/watchdog/wdt285.c b/drivers/watchdog/wdt285.c index 110249e5f642..5b7be7a62d54 100644 --- a/drivers/watchdog/wdt285.c +++ b/drivers/watchdog/wdt285.c @@ -206,8 +206,6 @@ static int __init footbridge_watchdog_init(void) pr_info("Footbridge Watchdog Timer: 0.01, timer margin: %d sec\n", soft_margin); - if (machine_is_cats()) - pr_warn("Warning: Watchdog reset may not work on this machine\n"); return 0; } From patchwork Wed Oct 19 15:03:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnd Bergmann X-Patchwork-Id: 5701 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp395131wrs; Wed, 19 Oct 2022 08:42:35 -0700 (PDT) X-Google-Smtp-Source: AMsMyM78C9PovRX/+QLKmWCzHTbdEVZuy6i0OnI9b+CD1RQVmfOaD06c4GCj2fQid0dEnC4rmu+L X-Received: by 2002:a17:907:25cc:b0:77b:a6c7:6d2b with SMTP id ae12-20020a17090725cc00b0077ba6c76d2bmr7420017ejc.148.1666194155304; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id s18-20020a1709067b9200b0078df19995e4si13375892ejo.241.2022.10.19.08.42.09; Wed, 19 Oct 2022 08:42:35 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=PVamlZCY; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230239AbiJSP0W (ORCPT + 99 others); Wed, 19 Oct 2022 11:26:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41534 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232467AbiJSPZo (ORCPT ); Wed, 19 Oct 2022 11:25:44 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 021FABE2E0; Wed, 19 Oct 2022 08:19:00 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 2E5136192B; Wed, 19 Oct 2022 15:17:53 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 28AD1C433C1; Wed, 19 Oct 2022 15:17:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1666192672; bh=licWBwVE0eGPVvitf8FzsPC1yn1FBuWaeRY3ctqDXRc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PVamlZCYs5h57CAE3v4SUNyqz8WLnzZ2dC1Bsz5tMHSxGmOVFmsa929A5maezujHt /xAWz6h1cZMjFam6cOMk/bX1jc+Qy8kXcPZeid8uCd1Re0DOwSIW9hy5BNpmspVaZu YTabKvqUQj+V+r3QkE+aMxCNF7QjYe89b9ZspXHSQetNB7sNhWOlGDo8sWi44XpxgJ vthdDJkcHAjHnrt/1vyw1tAYIJIEFF2z4zzY3ariZac3UdGtvDAGNRxlVoEXG6pV6k FmviP19P69uXw/WeJy6/kmEwQHJaweZnTyc1ZUmk8XD1ZBwQNS8g5vFYXJRUx419Lc tcF6pXnN29uTg== From: Arnd Bergmann To: linux-arm-kernel@lists.infradead.org, Aaro Koskinen , Janusz Krzysztofik , Tony Lindgren Cc: linux-kernel@vger.kernel.org, Arnd Bergmann , linux-omap@vger.kernel.org, Lee Jones , Ulf Hansson , Felipe Balbi , Greg Kroah-Hartman , linux-i2c@vger.kernel.org, linux-mmc@vger.kernel.org, linux-usb@vger.kernel.org Subject: [PATCH 13/17] ARM: omap1: remove unused board files Date: Wed, 19 Oct 2022 17:03:35 +0200 Message-Id: <20221019150410.3851944-13-arnd@kernel.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20221019150410.3851944-1-arnd@kernel.org> References: <20221019144119.3848027-1-arnd@kernel.org> <20221019150410.3851944-1-arnd@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747131202504266084?= X-GMAIL-MSGID: =?utf-8?q?1747131202504266084?= From: Arnd Bergmann All board support that was marked as 'unused' earlier can now be removed, leaving the five machines that that still had someone using them in 2022, or that are supported in qemu. Cc: Aaro Koskinen Cc: Janusz Krzysztofik Cc: Tony Lindgren Cc: linux-omap@vger.kernel.org Signed-off-by: Arnd Bergmann Acked-by: Wolfram Sang Acked-by: Lee Jones Acked-by: Greg Kroah-Hartman Acked-by: Tony Lindgren --- MAINTAINERS | 2 - arch/arm/Kconfig.debug | 36 +- arch/arm/configs/omap1_defconfig | 2 - arch/arm/mach-omap1/Kconfig | 93 +--- arch/arm/mach-omap1/Makefile | 18 - arch/arm/mach-omap1/board-fsample.c | 366 --------------- arch/arm/mach-omap1/board-generic.c | 85 ---- arch/arm/mach-omap1/board-h2-mmc.c | 74 --- arch/arm/mach-omap1/board-h2.c | 448 ------------------ arch/arm/mach-omap1/board-h2.h | 38 -- arch/arm/mach-omap1/board-h3-mmc.c | 64 --- arch/arm/mach-omap1/board-h3.c | 455 ------------------ arch/arm/mach-omap1/board-h3.h | 35 -- arch/arm/mach-omap1/board-htcherald.c | 585 ------------------------ arch/arm/mach-omap1/board-innovator.c | 481 ------------------- arch/arm/mach-omap1/board-nand.c | 33 -- arch/arm/mach-omap1/board-palmtt.c | 285 ------------ arch/arm/mach-omap1/board-palmz71.c | 300 ------------ arch/arm/mach-omap1/board-perseus2.c | 333 -------------- arch/arm/mach-omap1/fpga.c | 186 -------- arch/arm/mach-omap1/fpga.h | 49 -- arch/arm/mach-omap1/gpio7xx.c | 272 ----------- drivers/i2c/busses/Kconfig | 2 +- drivers/mfd/Kconfig | 2 +- drivers/mmc/host/Kconfig | 2 +- drivers/usb/gadget/udc/Kconfig | 2 +- drivers/usb/host/Kconfig | 2 +- include/linux/platform_data/leds-omap.h | 19 - 28 files changed, 12 insertions(+), 4257 deletions(-) delete mode 100644 arch/arm/mach-omap1/board-fsample.c delete mode 100644 arch/arm/mach-omap1/board-generic.c delete mode 100644 arch/arm/mach-omap1/board-h2-mmc.c delete mode 100644 arch/arm/mach-omap1/board-h2.c delete mode 100644 arch/arm/mach-omap1/board-h2.h delete mode 100644 arch/arm/mach-omap1/board-h3-mmc.c delete mode 100644 arch/arm/mach-omap1/board-h3.c delete mode 100644 arch/arm/mach-omap1/board-h3.h delete mode 100644 arch/arm/mach-omap1/board-htcherald.c delete mode 100644 arch/arm/mach-omap1/board-innovator.c delete mode 100644 arch/arm/mach-omap1/board-nand.c delete mode 100644 arch/arm/mach-omap1/board-palmtt.c delete mode 100644 arch/arm/mach-omap1/board-palmz71.c delete mode 100644 arch/arm/mach-omap1/board-perseus2.c delete mode 100644 arch/arm/mach-omap1/fpga.c delete mode 100644 arch/arm/mach-omap1/fpga.h delete mode 100644 arch/arm/mach-omap1/gpio7xx.c delete mode 100644 include/linux/platform_data/leds-omap.h diff --git a/MAINTAINERS b/MAINTAINERS index da1ff468e27d..bb3e20381128 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -15031,7 +15031,6 @@ Q: http://patchwork.kernel.org/project/linux-omap/list/ T: git git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap.git F: arch/arm/configs/omap1_defconfig F: arch/arm/mach-omap1/ -F: arch/arm/plat-omap/ F: drivers/i2c/busses/i2c-omap.c F: include/linux/platform_data/ams-delta-fiq.h F: include/linux/platform_data/i2c-omap.h @@ -15046,7 +15045,6 @@ Q: http://patchwork.kernel.org/project/linux-omap/list/ T: git git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap.git F: arch/arm/configs/omap2plus_defconfig F: arch/arm/mach-omap2/ -F: arch/arm/plat-omap/ F: drivers/bus/ti-sysc.c F: drivers/i2c/busses/i2c-omap.c F: drivers/irqchip/irq-omap-intc.c diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 320c93fabb21..c03fd448c59e 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -760,30 +760,6 @@ choice depends on ARCH_OMAP2PLUS select DEBUG_UART_8250 - config DEBUG_OMAP7XXUART1 - bool "Kernel low-level debugging via OMAP730 UART1" - depends on ARCH_OMAP730 - select DEBUG_UART_8250 - help - Say Y here if you want kernel low-level debugging support - on OMAP730 based platforms on the UART1. - - config DEBUG_OMAP7XXUART2 - bool "Kernel low-level debugging via OMAP730 UART2" - depends on ARCH_OMAP730 - select DEBUG_UART_8250 - help - Say Y here if you want kernel low-level debugging support - on OMAP730 based platforms on the UART2. - - config DEBUG_OMAP7XXUART3 - bool "Kernel low-level debugging via OMAP730 UART3" - depends on ARCH_OMAP730 - select DEBUG_UART_8250 - help - Say Y here if you want kernel low-level debugging support - on OMAP730 based platforms on the UART3. - config DEBUG_TI81XXUART1 bool "Kernel low-level debugging messages via TI81XX UART1 (ti8148evm)" depends on ARCH_OMAP2PLUS @@ -1728,9 +1704,9 @@ config DEBUG_UART_PHYS default 0xffe40000 if DEBUG_RCAR_GEN1_SCIF0 default 0xffe42000 if DEBUG_RCAR_GEN1_SCIF2 default 0xfff36000 if DEBUG_HIGHBANK_UART - default 0xfffb0000 if DEBUG_OMAP1UART1 || DEBUG_OMAP7XXUART1 - default 0xfffb0800 if DEBUG_OMAP1UART2 || DEBUG_OMAP7XXUART2 - default 0xfffb9800 if DEBUG_OMAP1UART3 || DEBUG_OMAP7XXUART3 + default 0xfffb0000 if DEBUG_OMAP1UART1 + default 0xfffb0800 if DEBUG_OMAP1UART2 + default 0xfffb9800 if DEBUG_OMAP1UART3 default 0xfffe8600 if DEBUG_BCM63XX_UART default 0xffffee00 if DEBUG_AT91_SAM9263_DBGU default 0xfffff200 if DEBUG_AT91_RM9200_DBGU @@ -1847,9 +1823,9 @@ config DEBUG_UART_VIRT default 0xfec00000 if ARCH_IXP4XX && !CPU_BIG_ENDIAN default 0xfec00003 if ARCH_IXP4XX && CPU_BIG_ENDIAN default 0xfef36000 if DEBUG_HIGHBANK_UART - default 0xff0b0000 if DEBUG_OMAP1UART1 || DEBUG_OMAP7XXUART1 - default 0xff0b0800 if DEBUG_OMAP1UART2 || DEBUG_OMAP7XXUART2 - default 0xff0b9800 if DEBUG_OMAP1UART3 || DEBUG_OMAP7XXUART3 + default 0xff0b0000 if DEBUG_OMAP1UART1 + default 0xff0b0800 if DEBUG_OMAP1UART2 + default 0xff0b9800 if DEBUG_OMAP1UART3 default 0xffd01000 if DEBUG_HIP01_UART default DEBUG_UART_PHYS if !MMU depends on DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \ diff --git a/arch/arm/configs/omap1_defconfig b/arch/arm/configs/omap1_defconfig index 70511fe4b3ec..28d29bc2a20c 100644 --- a/arch/arm/configs/omap1_defconfig +++ b/arch/arm/configs/omap1_defconfig @@ -20,8 +20,6 @@ CONFIG_ARCH_OMAP=y CONFIG_ARCH_OMAP1=y CONFIG_OMAP_32K_TIMER=y CONFIG_OMAP_DM_TIMER=y -CONFIG_ARCH_OMAP730=y -CONFIG_ARCH_OMAP850=y CONFIG_ARCH_OMAP16XX=y # CONFIG_OMAP_MUX is not set CONFIG_OMAP_RESET_CLOCKS=y diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig index 538a960257cc..21968f5a12a7 100644 --- a/arch/arm/mach-omap1/Kconfig +++ b/arch/arm/mach-omap1/Kconfig @@ -18,19 +18,6 @@ menu "TI OMAP1 specific features" comment "OMAP Core Type" -config ARCH_OMAP730 - depends on ARCH_MULTI_V5 - bool "OMAP730 Based System" - select ARCH_OMAP_OTG - select CPU_ARM926T - select OMAP_MPU_TIMER - -config ARCH_OMAP850 - depends on ARCH_MULTI_V5 - bool "OMAP850 Based System" - select ARCH_OMAP_OTG - select CPU_ARM926T - config ARCH_OMAP15XX depends on ARCH_MULTI_V4T default y @@ -47,7 +34,7 @@ config ARCH_OMAP16XX config ARCH_OMAP1_ANY select ARCH_OMAP - def_bool ARCH_OMAP730 || ARCH_OMAP850 || ARCH_OMAP15XX || ARCH_OMAP16XX + def_bool ARCH_OMAP15XX || ARCH_OMAP16XX config ARCH_OMAP bool @@ -129,37 +116,6 @@ config ARCH_OMAP_OTG comment "OMAP Board Type" -config MACH_OMAP_INNOVATOR - bool "TI Innovator" - depends on ARCH_OMAP15XX || ARCH_OMAP16XX - depends on UNUSED_BOARD_FILES - help - TI OMAP 1510 or 1610 Innovator board support. Say Y here if you - have such a board. - -config MACH_OMAP_H2 - bool "TI H2 Support" - depends on ARCH_OMAP16XX - depends on UNUSED_BOARD_FILES - help - TI OMAP 1610/1611B H2 board support. Say Y here if you have such - a board. - -config MACH_OMAP_H3 - bool "TI H3 Support" - depends on ARCH_OMAP16XX - depends on UNUSED_BOARD_FILES - help - TI OMAP 1710 H3 board support. Say Y here if you have such - a board. - -config MACH_HERALD - bool "HTC Herald" - depends on ARCH_OMAP850 - depends on UNUSED_BOARD_FILES - help - HTC Herald smartphone support (AKA T-Mobile Wing, ...) - config MACH_OMAP_OSK bool "TI OSK Support" depends on ARCH_OMAP16XX @@ -170,28 +126,11 @@ config MACH_OMAP_OSK config OMAP_OSK_MISTRAL bool "Mistral QVGA board Support" depends on MACH_OMAP_OSK - depends on UNUSED_BOARD_FILES help The OSK supports an optional add-on board with a Quarter-VGA touchscreen, PDA-ish buttons, a resume button, bicolor LED, and camera connector. Say Y here if you have this board. -config MACH_OMAP_PERSEUS2 - bool "TI Perseus2" - depends on ARCH_OMAP730 - depends on UNUSED_BOARD_FILES - help - Support for TI OMAP 730 Perseus2 board. Say Y here if you have such - a board. - -config MACH_OMAP_FSAMPLE - bool "TI F-Sample" - depends on ARCH_OMAP730 - depends on UNUSED_BOARD_FILES - help - Support for TI OMAP 850 F-Sample board. Say Y here if you have such - a board. - config MACH_OMAP_PALMTE bool "Palm Tungsten E" depends on ARCH_OMAP15XX @@ -201,26 +140,6 @@ config MACH_OMAP_PALMTE http://palmtelinux.sourceforge.net/ for more information. Say Y here if you have this PDA model, say N otherwise. -config MACH_OMAP_PALMZ71 - bool "Palm Zire71" - depends on ARCH_OMAP15XX - depends on UNUSED_BOARD_FILES - help - Support for the Palm Zire71 PDA. To boot the kernel, - you'll need a PalmOS compatible bootloader; check out - http://hackndev.com/palm/z71 for more information. - Say Y here if you have such a PDA, say N otherwise. - -config MACH_OMAP_PALMTT - bool "Palm Tungsten|T" - depends on ARCH_OMAP15XX - depends on UNUSED_BOARD_FILES - help - Support for the Palm Tungsten|T PDA. To boot the kernel, you'll - need a PalmOS compatible bootloader (Garux); check out - http://garux.sourceforge.net/ for more information. - Say Y here if you have this PDA model, say N otherwise. - config MACH_SX1 bool "Siemens SX1" depends on ARCH_OMAP15XX @@ -252,16 +171,6 @@ config MACH_AMS_DELTA Support for the Amstrad E3 (codename Delta) videophone. Say Y here if you have such a device. -config MACH_OMAP_GENERIC - bool "Generic OMAP board" - depends on ARCH_OMAP15XX || ARCH_OMAP16XX - depends on UNUSED_BOARD_FILES - help - Support for generic OMAP-1510, 1610 or 1710 board with - no FPGA. Can be used as template for porting Linux to - custom OMAP boards. Say Y here if you have a custom - board. - endmenu endif diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile index 506074b86333..73722f260a1d 100644 --- a/arch/arm/mach-omap1/Makefile +++ b/arch/arm/mach-omap1/Makefile @@ -31,32 +31,14 @@ usb-fs-$(CONFIG_USB_SUPPORT) := usb.o obj-y += $(usb-fs-m) $(usb-fs-y) # Specific board support -obj-$(CONFIG_MACH_OMAP_H2) += board-h2.o board-h2-mmc.o \ - board-nand.o -obj-$(CONFIG_MACH_OMAP_INNOVATOR) += board-innovator.o -obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o -obj-$(CONFIG_MACH_OMAP_PERSEUS2) += board-perseus2.o board-nand.o -obj-$(CONFIG_MACH_OMAP_FSAMPLE) += board-fsample.o board-nand.o obj-$(CONFIG_MACH_OMAP_OSK) += board-osk.o -obj-$(CONFIG_MACH_OMAP_H3) += board-h3.o board-h3-mmc.o \ - board-nand.o obj-$(CONFIG_MACH_OMAP_PALMTE) += board-palmte.o -obj-$(CONFIG_MACH_OMAP_PALMZ71) += board-palmz71.o -obj-$(CONFIG_MACH_OMAP_PALMTT) += board-palmtt.o obj-$(CONFIG_MACH_NOKIA770) += board-nokia770.o obj-$(CONFIG_MACH_AMS_DELTA) += board-ams-delta.o ams-delta-fiq.o \ ams-delta-fiq-handler.o obj-$(CONFIG_MACH_SX1) += board-sx1.o board-sx1-mmc.o -obj-$(CONFIG_MACH_HERALD) += board-htcherald.o - -ifeq ($(CONFIG_ARCH_OMAP15XX),y) -# Innovator-1510 FPGA -obj-$(CONFIG_MACH_OMAP_INNOVATOR) += fpga.o -endif # GPIO -obj-$(CONFIG_ARCH_OMAP730) += gpio7xx.o -obj-$(CONFIG_ARCH_OMAP850) += gpio7xx.o obj-$(CONFIG_ARCH_OMAP15XX) += gpio15xx.o obj-$(CONFIG_ARCH_OMAP16XX) += gpio16xx.o diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c deleted file mode 100644 index f21e15c7b973..000000000000 --- a/arch/arm/mach-omap1/board-fsample.c +++ /dev/null @@ -1,366 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/mach-omap1/board-fsample.c - * - * Modified from board-perseus2.c - * - * Original OMAP730 support by Jean Pihet - * Updated for 2.6 by Kevin Hilman - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include "tc.h" - -#include "mux.h" -#include "flash.h" -#include "hardware.h" -#include "iomap.h" -#include "common.h" -#include "fpga.h" - -/* fsample is pretty close to p2-sample */ - -#define fsample_cpld_read(reg) __raw_readb(reg) -#define fsample_cpld_write(val, reg) __raw_writeb(val, reg) - -#define FSAMPLE_CPLD_BASE 0xE8100000 -#define FSAMPLE_CPLD_SIZE SZ_4K -#define FSAMPLE_CPLD_START 0x05080000 - -#define FSAMPLE_CPLD_REG_A (FSAMPLE_CPLD_BASE + 0x00) -#define FSAMPLE_CPLD_SWITCH (FSAMPLE_CPLD_BASE + 0x02) -#define FSAMPLE_CPLD_UART (FSAMPLE_CPLD_BASE + 0x02) -#define FSAMPLE_CPLD_REG_B (FSAMPLE_CPLD_BASE + 0x04) -#define FSAMPLE_CPLD_VERSION (FSAMPLE_CPLD_BASE + 0x06) -#define FSAMPLE_CPLD_SET_CLR (FSAMPLE_CPLD_BASE + 0x06) - -#define FSAMPLE_CPLD_BIT_BT_RESET 0 -#define FSAMPLE_CPLD_BIT_LCD_RESET 1 -#define FSAMPLE_CPLD_BIT_CAM_PWDN 2 -#define FSAMPLE_CPLD_BIT_CHARGER_ENABLE 3 -#define FSAMPLE_CPLD_BIT_SD_MMC_EN 4 -#define FSAMPLE_CPLD_BIT_aGPS_PWREN 5 -#define FSAMPLE_CPLD_BIT_BACKLIGHT 6 -#define FSAMPLE_CPLD_BIT_aGPS_EN_RESET 7 -#define FSAMPLE_CPLD_BIT_aGPS_SLEEPx_N 8 -#define FSAMPLE_CPLD_BIT_OTG_RESET 9 - -#define fsample_cpld_set(bit) \ - fsample_cpld_write((((bit) & 15) << 4) | 0x0f, FSAMPLE_CPLD_SET_CLR) - -#define fsample_cpld_clear(bit) \ - fsample_cpld_write(0xf0 | ((bit) & 15), FSAMPLE_CPLD_SET_CLR) - -static const unsigned int fsample_keymap[] = { - KEY(0, 0, KEY_UP), - KEY(1, 0, KEY_RIGHT), - KEY(2, 0, KEY_LEFT), - KEY(3, 0, KEY_DOWN), - KEY(4, 0, KEY_ENTER), - KEY(0, 1, KEY_F10), - KEY(1, 1, KEY_SEND), - KEY(2, 1, KEY_END), - KEY(3, 1, KEY_VOLUMEDOWN), - KEY(4, 1, KEY_VOLUMEUP), - KEY(5, 1, KEY_RECORD), - KEY(0, 2, KEY_F9), - KEY(1, 2, KEY_3), - KEY(2, 2, KEY_6), - KEY(3, 2, KEY_9), - KEY(4, 2, KEY_KPDOT), - KEY(0, 3, KEY_BACK), - KEY(1, 3, KEY_2), - KEY(2, 3, KEY_5), - KEY(3, 3, KEY_8), - KEY(4, 3, KEY_0), - KEY(5, 3, KEY_KPSLASH), - KEY(0, 4, KEY_HOME), - KEY(1, 4, KEY_1), - KEY(2, 4, KEY_4), - KEY(3, 4, KEY_7), - KEY(4, 4, KEY_KPASTERISK), - KEY(5, 4, KEY_POWER), -}; - -static struct smc91x_platdata smc91x_info = { - .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, - .leda = RPC_LED_100_10, - .ledb = RPC_LED_TX_RX, -}; - -static struct resource smc91x_resources[] = { - [0] = { - .start = H2P2_DBG_FPGA_ETHR_START, /* Physical */ - .end = H2P2_DBG_FPGA_ETHR_START + 0xf, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = INT_7XX_MPU_EXT_NIRQ, - .end = 0, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, - }, -}; - -static void __init fsample_init_smc91x(void) -{ - __raw_writeb(1, H2P2_DBG_FPGA_LAN_RESET); - mdelay(50); - __raw_writeb(__raw_readb(H2P2_DBG_FPGA_LAN_RESET) & ~1, - H2P2_DBG_FPGA_LAN_RESET); - mdelay(50); -} - -static struct mtd_partition nor_partitions[] = { - /* bootloader (U-Boot, etc) in first sector */ - { - .name = "bootloader", - .offset = 0, - .size = SZ_128K, - .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, - /* bootloader params in the next sector */ - { - .name = "params", - .offset = MTDPART_OFS_APPEND, - .size = SZ_128K, - .mask_flags = 0, - }, - /* kernel */ - { - .name = "kernel", - .offset = MTDPART_OFS_APPEND, - .size = SZ_2M, - .mask_flags = 0 - }, - /* rest of flash is a file system */ - { - .name = "rootfs", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - .mask_flags = 0 - }, -}; - -static struct physmap_flash_data nor_data = { - .width = 2, - .set_vpp = omap1_set_vpp, - .parts = nor_partitions, - .nr_parts = ARRAY_SIZE(nor_partitions), -}; - -static struct resource nor_resource = { - .start = OMAP_CS0_PHYS, - .end = OMAP_CS0_PHYS + SZ_32M - 1, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device nor_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &nor_data, - }, - .num_resources = 1, - .resource = &nor_resource, -}; - -#define FSAMPLE_NAND_RB_GPIO_PIN 62 - -static int nand_dev_ready(struct nand_chip *chip) -{ - return gpio_get_value(FSAMPLE_NAND_RB_GPIO_PIN); -} - -static struct platform_nand_data nand_data = { - .chip = { - .nr_chips = 1, - .chip_offset = 0, - .options = NAND_SAMSUNG_LP_OPTIONS, - }, - .ctrl = { - .cmd_ctrl = omap1_nand_cmd_ctl, - .dev_ready = nand_dev_ready, - }, -}; - -static struct resource nand_resource = { - .start = OMAP_CS3_PHYS, - .end = OMAP_CS3_PHYS + SZ_4K - 1, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device nand_device = { - .name = "gen_nand", - .id = 0, - .dev = { - .platform_data = &nand_data, - }, - .num_resources = 1, - .resource = &nand_resource, -}; - -static struct platform_device smc91x_device = { - .name = "smc91x", - .id = 0, - .dev = { - .platform_data = &smc91x_info, - }, - .num_resources = ARRAY_SIZE(smc91x_resources), - .resource = smc91x_resources, -}; - -static struct resource kp_resources[] = { - [0] = { - .start = INT_7XX_MPUIO_KEYPAD, - .end = INT_7XX_MPUIO_KEYPAD, - .flags = IORESOURCE_IRQ, - }, -}; - -static const struct matrix_keymap_data fsample_keymap_data = { - .keymap = fsample_keymap, - .keymap_size = ARRAY_SIZE(fsample_keymap), -}; - -static struct omap_kp_platform_data kp_data = { - .rows = 8, - .cols = 8, - .keymap_data = &fsample_keymap_data, - .delay = 4, -}; - -static struct platform_device kp_device = { - .name = "omap-keypad", - .id = -1, - .dev = { - .platform_data = &kp_data, - }, - .num_resources = ARRAY_SIZE(kp_resources), - .resource = kp_resources, -}; - -static struct platform_device *devices[] __initdata = { - &nor_device, - &nand_device, - &smc91x_device, - &kp_device, -}; - -static const struct omap_lcd_config fsample_lcd_config = { - .ctrl_name = "internal", -}; - -static void __init omap_fsample_init(void) -{ - /* Early, board-dependent init */ - - /* - * Hold GSM Reset until needed - */ - omap_writew(omap_readw(OMAP7XX_DSP_M_CTL) & ~1, OMAP7XX_DSP_M_CTL); - - /* - * UARTs -> done automagically by 8250 driver - */ - - /* - * CSx timings, GPIO Mux ... setup - */ - - /* Flash: CS0 timings setup */ - omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_0); - omap_writel(0x00000088, OMAP7XX_FLASH_ACFG_0); - - /* - * Ethernet support through the debug board - * CS1 timings setup - */ - omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_1); - omap_writel(0x00000000, OMAP7XX_FLASH_ACFG_1); - - /* - * Configure MPU_EXT_NIRQ IO in IO_CONF9 register, - * It is used as the Ethernet controller interrupt - */ - omap_writel(omap_readl(OMAP7XX_IO_CONF_9) & 0x1FFFFFFF, - OMAP7XX_IO_CONF_9); - - fsample_init_smc91x(); - - BUG_ON(gpio_request(FSAMPLE_NAND_RB_GPIO_PIN, "NAND ready") < 0); - gpio_direction_input(FSAMPLE_NAND_RB_GPIO_PIN); - - omap_cfg_reg(L3_1610_FLASH_CS2B_OE); - omap_cfg_reg(M8_1610_FLASH_CS2B_WE); - - /* Mux pins for keypad */ - omap_cfg_reg(E2_7XX_KBR0); - omap_cfg_reg(J7_7XX_KBR1); - omap_cfg_reg(E1_7XX_KBR2); - omap_cfg_reg(F3_7XX_KBR3); - omap_cfg_reg(D2_7XX_KBR4); - omap_cfg_reg(C2_7XX_KBC0); - omap_cfg_reg(D3_7XX_KBC1); - omap_cfg_reg(E4_7XX_KBC2); - omap_cfg_reg(F4_7XX_KBC3); - omap_cfg_reg(E3_7XX_KBC4); - - platform_add_devices(devices, ARRAY_SIZE(devices)); - - omap_serial_init(); - omap_register_i2c_bus(1, 100, NULL, 0); - - omapfb_set_lcd_config(&fsample_lcd_config); -} - -/* Only FPGA needs to be mapped here. All others are done with ioremap */ -static struct map_desc omap_fsample_io_desc[] __initdata = { - { - .virtual = H2P2_DBG_FPGA_BASE, - .pfn = __phys_to_pfn(H2P2_DBG_FPGA_START), - .length = H2P2_DBG_FPGA_SIZE, - .type = MT_DEVICE - }, - { - .virtual = FSAMPLE_CPLD_BASE, - .pfn = __phys_to_pfn(FSAMPLE_CPLD_START), - .length = FSAMPLE_CPLD_SIZE, - .type = MT_DEVICE - } -}; - -static void __init omap_fsample_map_io(void) -{ - omap15xx_map_io(); - iotable_init(omap_fsample_io_desc, - ARRAY_SIZE(omap_fsample_io_desc)); -} - -MACHINE_START(OMAP_FSAMPLE, "OMAP730 F-Sample") -/* Maintainer: Brian Swetland */ - .atag_offset = 0x100, - .map_io = omap_fsample_map_io, - .init_early = omap1_init_early, - .init_irq = omap1_init_irq, - .handle_irq = omap1_handle_irq, - .init_machine = omap_fsample_init, - .init_late = omap1_init_late, - .init_time = omap1_timer_init, - .restart = omap1_restart, -MACHINE_END diff --git a/arch/arm/mach-omap1/board-generic.c b/arch/arm/mach-omap1/board-generic.c deleted file mode 100644 index 3b2bcaf4bb01..000000000000 --- a/arch/arm/mach-omap1/board-generic.c +++ /dev/null @@ -1,85 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/mach-omap1/board-generic.c - * - * Modified from board-innovator1510.c - * - * Code for generic OMAP board. Should work on many OMAP systems where - * the device drivers take care of all the necessary hardware initialization. - * Do not put any board specific code to this file; create a new machine - * type if you need custom low-level initializations. - */ -#include -#include -#include -#include - -#include -#include -#include - -#include "hardware.h" -#include "mux.h" -#include "usb.h" -#include "common.h" - -/* assume no Mini-AB port */ - -#ifdef CONFIG_ARCH_OMAP15XX -static struct omap_usb_config generic1510_usb_config __initdata = { - .register_host = 1, - .register_dev = 1, - .hmc_mode = 16, - .pins[0] = 3, -}; -#endif - -#if defined(CONFIG_ARCH_OMAP16XX) -static struct omap_usb_config generic1610_usb_config __initdata = { -#ifdef CONFIG_USB_OTG - .otg = 1, -#endif - .register_host = 1, - .register_dev = 1, - .hmc_mode = 16, - .pins[0] = 6, -}; -#endif - -static void __init omap_generic_init(void) -{ -#ifdef CONFIG_ARCH_OMAP15XX - if (cpu_is_omap15xx()) { - /* mux pins for uarts */ - omap_cfg_reg(UART1_TX); - omap_cfg_reg(UART1_RTS); - omap_cfg_reg(UART2_TX); - omap_cfg_reg(UART2_RTS); - omap_cfg_reg(UART3_TX); - omap_cfg_reg(UART3_RX); - - omap1_usb_init(&generic1510_usb_config); - } -#endif -#if defined(CONFIG_ARCH_OMAP16XX) - if (!cpu_is_omap1510()) { - omap1_usb_init(&generic1610_usb_config); - } -#endif - - omap_serial_init(); - omap_register_i2c_bus(1, 100, NULL, 0); -} - -MACHINE_START(OMAP_GENERIC, "Generic OMAP1510/1610/1710") - /* Maintainer: Tony Lindgren */ - .atag_offset = 0x100, - .map_io = omap16xx_map_io, - .init_early = omap1_init_early, - .init_irq = omap1_init_irq, - .handle_irq = omap1_handle_irq, - .init_machine = omap_generic_init, - .init_late = omap1_init_late, - .init_time = omap1_timer_init, - .restart = omap1_restart, -MACHINE_END diff --git a/arch/arm/mach-omap1/board-h2-mmc.c b/arch/arm/mach-omap1/board-h2-mmc.c deleted file mode 100644 index 06c5404078aa..000000000000 --- a/arch/arm/mach-omap1/board-h2-mmc.c +++ /dev/null @@ -1,74 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/mach-omap1/board-h2-mmc.c - * - * Copyright (C) 2007 Instituto Nokia de Tecnologia - INdT - * Author: Felipe Balbi - * - * This code is based on linux/arch/arm/mach-omap2/board-n800-mmc.c, which is: - * Copyright (C) 2006 Nokia Corporation - */ -#include -#include -#include -#include - -#include "board-h2.h" -#include "mmc.h" - -#if IS_ENABLED(CONFIG_MMC_OMAP) - -static int mmc_set_power(struct device *dev, int slot, int power_on, - int vdd) -{ - gpio_set_value(H2_TPS_GPIO_MMC_PWR_EN, power_on); - return 0; -} - -static int mmc_late_init(struct device *dev) -{ - int ret = gpio_request(H2_TPS_GPIO_MMC_PWR_EN, "MMC power"); - if (ret < 0) - return ret; - - gpio_direction_output(H2_TPS_GPIO_MMC_PWR_EN, 0); - - return ret; -} - -static void mmc_cleanup(struct device *dev) -{ - gpio_free(H2_TPS_GPIO_MMC_PWR_EN); -} - -/* - * H2 could use the following functions tested: - * - mmc_get_cover_state that uses OMAP_MPUIO(1) - * - mmc_get_wp that uses OMAP_MPUIO(3) - */ -static struct omap_mmc_platform_data mmc1_data = { - .nr_slots = 1, - .init = mmc_late_init, - .cleanup = mmc_cleanup, - .slots[0] = { - .set_power = mmc_set_power, - .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, - .name = "mmcblk", - }, -}; - -static struct omap_mmc_platform_data *mmc_data[OMAP16XX_NR_MMC]; - -void __init h2_mmc_init(void) -{ - mmc_data[0] = &mmc1_data; - omap1_init_mmc(mmc_data, OMAP16XX_NR_MMC); -} - -#else - -void __init h2_mmc_init(void) -{ -} - -#endif diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c deleted file mode 100644 index f28a4c3ea501..000000000000 --- a/arch/arm/mach-omap1/board-h2.c +++ /dev/null @@ -1,448 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/mach-omap1/board-h2.c - * - * Board specific inits for OMAP-1610 H2 - * - * Copyright (C) 2001 RidgeRun, Inc. - * Author: Greg Lonnon - * - * Copyright (C) 2002 MontaVista Software, Inc. - * - * Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6 - * Copyright (C) 2004 Nokia Corporation by Tony Lindrgen - * - * H2 specific changes and cleanup - * Copyright (C) 2004 Nokia Corporation by Imre Deak - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include "tc.h" -#include "mux.h" -#include "flash.h" -#include "hardware.h" -#include "usb.h" -#include "common.h" -#include "board-h2.h" - -/* The first 16 SoC GPIO lines are on this GPIO chip */ -#define OMAP_GPIO_LABEL "gpio-0-15" - -/* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */ -#define OMAP1610_ETHR_START 0x04000300 - -static const unsigned int h2_keymap[] = { - KEY(0, 0, KEY_LEFT), - KEY(1, 0, KEY_RIGHT), - KEY(2, 0, KEY_3), - KEY(3, 0, KEY_F10), - KEY(4, 0, KEY_F5), - KEY(5, 0, KEY_9), - KEY(0, 1, KEY_DOWN), - KEY(1, 1, KEY_UP), - KEY(2, 1, KEY_2), - KEY(3, 1, KEY_F9), - KEY(4, 1, KEY_F7), - KEY(5, 1, KEY_0), - KEY(0, 2, KEY_ENTER), - KEY(1, 2, KEY_6), - KEY(2, 2, KEY_1), - KEY(3, 2, KEY_F2), - KEY(4, 2, KEY_F6), - KEY(5, 2, KEY_HOME), - KEY(0, 3, KEY_8), - KEY(1, 3, KEY_5), - KEY(2, 3, KEY_F12), - KEY(3, 3, KEY_F3), - KEY(4, 3, KEY_F8), - KEY(5, 3, KEY_END), - KEY(0, 4, KEY_7), - KEY(1, 4, KEY_4), - KEY(2, 4, KEY_F11), - KEY(3, 4, KEY_F1), - KEY(4, 4, KEY_F4), - KEY(5, 4, KEY_ESC), - KEY(0, 5, KEY_F13), - KEY(1, 5, KEY_F14), - KEY(2, 5, KEY_F15), - KEY(3, 5, KEY_F16), - KEY(4, 5, KEY_SLEEP), -}; - -static struct mtd_partition h2_nor_partitions[] = { - /* bootloader (U-Boot, etc) in first sector */ - { - .name = "bootloader", - .offset = 0, - .size = SZ_128K, - .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, - /* bootloader params in the next sector */ - { - .name = "params", - .offset = MTDPART_OFS_APPEND, - .size = SZ_128K, - .mask_flags = 0, - }, - /* kernel */ - { - .name = "kernel", - .offset = MTDPART_OFS_APPEND, - .size = SZ_2M, - .mask_flags = 0 - }, - /* file system */ - { - .name = "filesystem", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - .mask_flags = 0 - } -}; - -static struct physmap_flash_data h2_nor_data = { - .width = 2, - .set_vpp = omap1_set_vpp, - .parts = h2_nor_partitions, - .nr_parts = ARRAY_SIZE(h2_nor_partitions), -}; - -static struct resource h2_nor_resource = { - /* This is on CS3, wherever it's mapped */ - .flags = IORESOURCE_MEM, -}; - -static struct platform_device h2_nor_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &h2_nor_data, - }, - .num_resources = 1, - .resource = &h2_nor_resource, -}; - -static struct mtd_partition h2_nand_partitions[] = { -#if 0 - /* REVISIT: enable these partitions if you make NAND BOOT - * work on your H2 (rev C or newer); published versions of - * x-load only support P2 and H3. - */ - { - .name = "xloader", - .offset = 0, - .size = 64 * 1024, - .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, - { - .name = "bootloader", - .offset = MTDPART_OFS_APPEND, - .size = 256 * 1024, - .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, - { - .name = "params", - .offset = MTDPART_OFS_APPEND, - .size = 192 * 1024, - }, - { - .name = "kernel", - .offset = MTDPART_OFS_APPEND, - .size = 2 * SZ_1M, - }, -#endif - { - .name = "filesystem", - .size = MTDPART_SIZ_FULL, - .offset = MTDPART_OFS_APPEND, - }, -}; - -#define H2_NAND_RB_GPIO_PIN 62 - -static int h2_nand_dev_ready(struct nand_chip *chip) -{ - return gpio_get_value(H2_NAND_RB_GPIO_PIN); -} - -static struct platform_nand_data h2_nand_platdata = { - .chip = { - .nr_chips = 1, - .chip_offset = 0, - .nr_partitions = ARRAY_SIZE(h2_nand_partitions), - .partitions = h2_nand_partitions, - .options = NAND_SAMSUNG_LP_OPTIONS, - }, - .ctrl = { - .cmd_ctrl = omap1_nand_cmd_ctl, - .dev_ready = h2_nand_dev_ready, - }, -}; - -static struct resource h2_nand_resource = { - .flags = IORESOURCE_MEM, -}; - -static struct platform_device h2_nand_device = { - .name = "gen_nand", - .id = 0, - .dev = { - .platform_data = &h2_nand_platdata, - }, - .num_resources = 1, - .resource = &h2_nand_resource, -}; - -static struct smc91x_platdata h2_smc91x_info = { - .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, - .leda = RPC_LED_100_10, - .ledb = RPC_LED_TX_RX, -}; - -static struct resource h2_smc91x_resources[] = { - [0] = { - .start = OMAP1610_ETHR_START, /* Physical */ - .end = OMAP1610_ETHR_START + 0xf, - .flags = IORESOURCE_MEM, - }, - [1] = { - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, - }, -}; - -static struct platform_device h2_smc91x_device = { - .name = "smc91x", - .id = 0, - .dev = { - .platform_data = &h2_smc91x_info, - }, - .num_resources = ARRAY_SIZE(h2_smc91x_resources), - .resource = h2_smc91x_resources, -}; - -static struct resource h2_kp_resources[] = { - [0] = { - .start = INT_KEYBOARD, - .end = INT_KEYBOARD, - .flags = IORESOURCE_IRQ, - }, -}; - -static const struct matrix_keymap_data h2_keymap_data = { - .keymap = h2_keymap, - .keymap_size = ARRAY_SIZE(h2_keymap), -}; - -static struct omap_kp_platform_data h2_kp_data = { - .rows = 8, - .cols = 8, - .keymap_data = &h2_keymap_data, - .rep = true, - .delay = 9, - .dbounce = true, -}; - -static struct platform_device h2_kp_device = { - .name = "omap-keypad", - .id = -1, - .dev = { - .platform_data = &h2_kp_data, - }, - .num_resources = ARRAY_SIZE(h2_kp_resources), - .resource = h2_kp_resources, -}; - -static const struct gpio_led h2_gpio_led_pins[] = { - { - .name = "h2:red", - .default_trigger = "heartbeat", - .gpio = 3, - }, - { - .name = "h2:green", - .default_trigger = "cpu0", - .gpio = OMAP_MPUIO(4), - }, -}; - -static struct gpio_led_platform_data h2_gpio_led_data = { - .leds = h2_gpio_led_pins, - .num_leds = ARRAY_SIZE(h2_gpio_led_pins), -}; - -static struct platform_device h2_gpio_leds = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &h2_gpio_led_data, - }, -}; - -static struct platform_device *h2_devices[] __initdata = { - &h2_nor_device, - &h2_nand_device, - &h2_smc91x_device, - &h2_kp_device, - &h2_gpio_leds, -}; - -static void __init h2_init_smc91x(void) -{ - if (gpio_request(0, "SMC91x irq") < 0) { - printk("Error requesting gpio 0 for smc91x irq\n"); - return; - } -} - -static int tps_setup(struct i2c_client *client, void *context) -{ - if (!IS_BUILTIN(CONFIG_TPS65010)) - return -ENOSYS; - - tps65010_config_vregs1(TPS_LDO2_ENABLE | TPS_VLDO2_3_0V | - TPS_LDO1_ENABLE | TPS_VLDO1_3_0V); - - return 0; -} - -static struct tps65010_board tps_board = { - .base = H2_TPS_GPIO_BASE, - .outmask = 0x0f, - .setup = tps_setup, -}; - -static struct i2c_board_info __initdata h2_i2c_board_info[] = { - { - I2C_BOARD_INFO("tps65010", 0x48), - .platform_data = &tps_board, - }, { - .type = "isp1301_omap", - .addr = 0x2d, - .dev_name = "isp1301", - }, -}; - -static struct gpiod_lookup_table isp1301_gpiod_table = { - .dev_id = "isp1301", - .table = { - /* Active low since the irq triggers on falling edge */ - GPIO_LOOKUP(OMAP_GPIO_LABEL, 2, - NULL, GPIO_ACTIVE_LOW), - { }, - }, -}; - -static struct omap_usb_config h2_usb_config __initdata = { - /* usb1 has a Mini-AB port and external isp1301 transceiver */ - .otg = 2, - -#if IS_ENABLED(CONFIG_USB_OMAP) - .hmc_mode = 19, /* 0:host(off) 1:dev|otg 2:disabled */ - /* .hmc_mode = 21,*/ /* 0:host(off) 1:dev(loopback) 2:host(loopback) */ -#elif IS_ENABLED(CONFIG_USB_OHCI_HCD) - /* needs OTG cable, or NONSTANDARD (B-to-MiniB) */ - .hmc_mode = 20, /* 1:dev|otg(off) 1:host 2:disabled */ -#endif - - .pins[1] = 3, -}; - -static const struct omap_lcd_config h2_lcd_config __initconst = { - .ctrl_name = "internal", -}; - -static void __init h2_init(void) -{ - h2_init_smc91x(); - - /* Here we assume the NOR boot config: NOR on CS3 (possibly swapped - * to address 0 by a dip switch), NAND on CS2B. The NAND driver will - * notice whether a NAND chip is enabled at probe time. - * - * FIXME revC boards (and H3) support NAND-boot, with a dip switch to - * put NOR on CS2B and NAND (which on H2 may be 16bit) on CS3. Try - * detecting that in code here, to avoid probing every possible flash - * configuration... - */ - h2_nor_resource.end = h2_nor_resource.start = omap_cs3_phys(); - h2_nor_resource.end += SZ_32M - 1; - - h2_nand_resource.end = h2_nand_resource.start = OMAP_CS2B_PHYS; - h2_nand_resource.end += SZ_4K - 1; - BUG_ON(gpio_request(H2_NAND_RB_GPIO_PIN, "NAND ready") < 0); - gpio_direction_input(H2_NAND_RB_GPIO_PIN); - - gpiod_add_lookup_table(&isp1301_gpiod_table); - - omap_cfg_reg(L3_1610_FLASH_CS2B_OE); - omap_cfg_reg(M8_1610_FLASH_CS2B_WE); - - /* MMC: card detect and WP */ - /* omap_cfg_reg(U19_ARMIO1); */ /* CD */ - omap_cfg_reg(BALLOUT_V8_ARMIO3); /* WP */ - - /* Mux pins for keypad */ - omap_cfg_reg(F18_1610_KBC0); - omap_cfg_reg(D20_1610_KBC1); - omap_cfg_reg(D19_1610_KBC2); - omap_cfg_reg(E18_1610_KBC3); - omap_cfg_reg(C21_1610_KBC4); - omap_cfg_reg(G18_1610_KBR0); - omap_cfg_reg(F19_1610_KBR1); - omap_cfg_reg(H14_1610_KBR2); - omap_cfg_reg(E20_1610_KBR3); - omap_cfg_reg(E19_1610_KBR4); - omap_cfg_reg(N19_1610_KBR5); - - /* GPIO based LEDs */ - omap_cfg_reg(P18_1610_GPIO3); - omap_cfg_reg(MPUIO4); - - h2_smc91x_resources[1].start = gpio_to_irq(0); - h2_smc91x_resources[1].end = gpio_to_irq(0); - platform_add_devices(h2_devices, ARRAY_SIZE(h2_devices)); - omap_serial_init(); - - /* ISP1301 IRQ wired at M14 */ - omap_cfg_reg(M14_1510_GPIO2); - h2_i2c_board_info[0].irq = gpio_to_irq(58); - omap_register_i2c_bus(1, 100, h2_i2c_board_info, - ARRAY_SIZE(h2_i2c_board_info)); - omap1_usb_init(&h2_usb_config); - h2_mmc_init(); - - omapfb_set_lcd_config(&h2_lcd_config); -} - -MACHINE_START(OMAP_H2, "TI-H2") - /* Maintainer: Imre Deak */ - .atag_offset = 0x100, - .map_io = omap16xx_map_io, - .init_early = omap1_init_early, - .init_irq = omap1_init_irq, - .handle_irq = omap1_handle_irq, - .init_machine = h2_init, - .init_late = omap1_init_late, - .init_time = omap1_timer_init, - .restart = omap1_restart, -MACHINE_END diff --git a/arch/arm/mach-omap1/board-h2.h b/arch/arm/mach-omap1/board-h2.h deleted file mode 100644 index 315e2662547e..000000000000 --- a/arch/arm/mach-omap1/board-h2.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * arch/arm/mach-omap1/board-h2.h - * - * Hardware definitions for TI OMAP1610 H2 board. - * - * Cleanup for Linux-2.6 by Dirk Behme - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#ifndef __ASM_ARCH_OMAP_H2_H -#define __ASM_ARCH_OMAP_H2_H - -#define H2_TPS_GPIO_BASE (OMAP_MAX_GPIO_LINES + 16 /* MPUIO */) -# define H2_TPS_GPIO_MMC_PWR_EN (H2_TPS_GPIO_BASE + 3) - -extern void h2_mmc_init(void); - -#endif /* __ASM_ARCH_OMAP_H2_H */ - diff --git a/arch/arm/mach-omap1/board-h3-mmc.c b/arch/arm/mach-omap1/board-h3-mmc.c deleted file mode 100644 index f595bd4f5024..000000000000 --- a/arch/arm/mach-omap1/board-h3-mmc.c +++ /dev/null @@ -1,64 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/mach-omap1/board-h3-mmc.c - * - * Copyright (C) 2007 Instituto Nokia de Tecnologia - INdT - * Author: Felipe Balbi - * - * This code is based on linux/arch/arm/mach-omap2/board-n800-mmc.c, which is: - * Copyright (C) 2006 Nokia Corporation - */ -#include -#include - -#include - -#include "common.h" -#include "board-h3.h" -#include "mmc.h" - -#if IS_ENABLED(CONFIG_MMC_OMAP) - -static int mmc_set_power(struct device *dev, int slot, int power_on, - int vdd) -{ - gpio_set_value(H3_TPS_GPIO_MMC_PWR_EN, power_on); - return 0; -} - -/* - * H3 could use the following functions tested: - * - mmc_get_cover_state that uses OMAP_MPUIO(1) - * - mmc_get_wp that maybe uses OMAP_MPUIO(3) - */ -static struct omap_mmc_platform_data mmc1_data = { - .nr_slots = 1, - .slots[0] = { - .set_power = mmc_set_power, - .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, - .name = "mmcblk", - }, -}; - -static struct omap_mmc_platform_data *mmc_data[OMAP16XX_NR_MMC]; - -void __init h3_mmc_init(void) -{ - int ret; - - ret = gpio_request(H3_TPS_GPIO_MMC_PWR_EN, "MMC power"); - if (ret < 0) - return; - gpio_direction_output(H3_TPS_GPIO_MMC_PWR_EN, 0); - - mmc_data[0] = &mmc1_data; - omap1_init_mmc(mmc_data, OMAP16XX_NR_MMC); -} - -#else - -void __init h3_mmc_init(void) -{ -} - -#endif diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c deleted file mode 100644 index 1e4c57710fcc..000000000000 --- a/arch/arm/mach-omap1/board-h3.c +++ /dev/null @@ -1,455 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/mach-omap1/board-h3.c - * - * This file contains OMAP1710 H3 specific code. - * - * Copyright (C) 2004 Texas Instruments, Inc. - * Copyright (C) 2002 MontaVista Software, Inc. - * Copyright (C) 2001 RidgeRun, Inc. - * Author: RidgeRun, Inc. - * Greg Lonnon (glonnon@ridgerun.com) or info@ridgerun.com - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "tc.h" -#include "mux.h" -#include "flash.h" -#include "hardware.h" -#include "irqs.h" -#include "usb.h" -#include "common.h" -#include "board-h3.h" - -/* In OMAP1710 H3 the Ethernet is directly connected to CS1 */ -#define OMAP1710_ETHR_START 0x04000300 - -#define H3_TS_GPIO 48 - -static const unsigned int h3_keymap[] = { - KEY(0, 0, KEY_LEFT), - KEY(1, 0, KEY_RIGHT), - KEY(2, 0, KEY_3), - KEY(3, 0, KEY_F10), - KEY(4, 0, KEY_F5), - KEY(5, 0, KEY_9), - KEY(0, 1, KEY_DOWN), - KEY(1, 1, KEY_UP), - KEY(2, 1, KEY_2), - KEY(3, 1, KEY_F9), - KEY(4, 1, KEY_F7), - KEY(5, 1, KEY_0), - KEY(0, 2, KEY_ENTER), - KEY(1, 2, KEY_6), - KEY(2, 2, KEY_1), - KEY(3, 2, KEY_F2), - KEY(4, 2, KEY_F6), - KEY(5, 2, KEY_HOME), - KEY(0, 3, KEY_8), - KEY(1, 3, KEY_5), - KEY(2, 3, KEY_F12), - KEY(3, 3, KEY_F3), - KEY(4, 3, KEY_F8), - KEY(5, 3, KEY_END), - KEY(0, 4, KEY_7), - KEY(1, 4, KEY_4), - KEY(2, 4, KEY_F11), - KEY(3, 4, KEY_F1), - KEY(4, 4, KEY_F4), - KEY(5, 4, KEY_ESC), - KEY(0, 5, KEY_F13), - KEY(1, 5, KEY_F14), - KEY(2, 5, KEY_F15), - KEY(3, 5, KEY_F16), - KEY(4, 5, KEY_SLEEP), -}; - - -static struct mtd_partition nor_partitions[] = { - /* bootloader (U-Boot, etc) in first sector */ - { - .name = "bootloader", - .offset = 0, - .size = SZ_128K, - .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, - /* bootloader params in the next sector */ - { - .name = "params", - .offset = MTDPART_OFS_APPEND, - .size = SZ_128K, - .mask_flags = 0, - }, - /* kernel */ - { - .name = "kernel", - .offset = MTDPART_OFS_APPEND, - .size = SZ_2M, - .mask_flags = 0 - }, - /* file system */ - { - .name = "filesystem", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - .mask_flags = 0 - } -}; - -static struct physmap_flash_data nor_data = { - .width = 2, - .set_vpp = omap1_set_vpp, - .parts = nor_partitions, - .nr_parts = ARRAY_SIZE(nor_partitions), -}; - -static struct resource nor_resource = { - /* This is on CS3, wherever it's mapped */ - .flags = IORESOURCE_MEM, -}; - -static struct platform_device nor_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &nor_data, - }, - .num_resources = 1, - .resource = &nor_resource, -}; - -static struct mtd_partition nand_partitions[] = { -#if 0 - /* REVISIT: enable these partitions if you make NAND BOOT work */ - { - .name = "xloader", - .offset = 0, - .size = 64 * 1024, - .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, - { - .name = "bootloader", - .offset = MTDPART_OFS_APPEND, - .size = 256 * 1024, - .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, - { - .name = "params", - .offset = MTDPART_OFS_APPEND, - .size = 192 * 1024, - }, - { - .name = "kernel", - .offset = MTDPART_OFS_APPEND, - .size = 2 * SZ_1M, - }, -#endif - { - .name = "filesystem", - .size = MTDPART_SIZ_FULL, - .offset = MTDPART_OFS_APPEND, - }, -}; - -#define H3_NAND_RB_GPIO_PIN 10 - -static int nand_dev_ready(struct nand_chip *chip) -{ - return gpio_get_value(H3_NAND_RB_GPIO_PIN); -} - -static struct platform_nand_data nand_platdata = { - .chip = { - .nr_chips = 1, - .chip_offset = 0, - .nr_partitions = ARRAY_SIZE(nand_partitions), - .partitions = nand_partitions, - .options = NAND_SAMSUNG_LP_OPTIONS, - }, - .ctrl = { - .cmd_ctrl = omap1_nand_cmd_ctl, - .dev_ready = nand_dev_ready, - - }, -}; - -static struct resource nand_resource = { - .flags = IORESOURCE_MEM, -}; - -static struct platform_device nand_device = { - .name = "gen_nand", - .id = 0, - .dev = { - .platform_data = &nand_platdata, - }, - .num_resources = 1, - .resource = &nand_resource, -}; - -static struct smc91x_platdata smc91x_info = { - .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, - .leda = RPC_LED_100_10, - .ledb = RPC_LED_TX_RX, -}; - -static struct resource smc91x_resources[] = { - [0] = { - .start = OMAP1710_ETHR_START, /* Physical */ - .end = OMAP1710_ETHR_START + 0xf, - .flags = IORESOURCE_MEM, - }, - [1] = { - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, - }, -}; - -static struct platform_device smc91x_device = { - .name = "smc91x", - .id = 0, - .dev = { - .platform_data = &smc91x_info, - }, - .num_resources = ARRAY_SIZE(smc91x_resources), - .resource = smc91x_resources, -}; - -static void __init h3_init_smc91x(void) -{ - omap_cfg_reg(W15_1710_GPIO40); - if (gpio_request(40, "SMC91x irq") < 0) { - printk("Error requesting gpio 40 for smc91x irq\n"); - return; - } -} - -#define GPTIMER_BASE 0xFFFB1400 -#define GPTIMER_REGS(x) (0xFFFB1400 + (x * 0x800)) -#define GPTIMER_REGS_SIZE 0x46 - -static struct resource intlat_resources[] = { - [0] = { - .start = GPTIMER_REGS(0), /* Physical */ - .end = GPTIMER_REGS(0) + GPTIMER_REGS_SIZE, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = INT_1610_GPTIMER1, - .end = INT_1610_GPTIMER1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device intlat_device = { - .name = "omap_intlat", - .id = 0, - .num_resources = ARRAY_SIZE(intlat_resources), - .resource = intlat_resources, -}; - -static struct resource h3_kp_resources[] = { - [0] = { - .start = INT_KEYBOARD, - .end = INT_KEYBOARD, - .flags = IORESOURCE_IRQ, - }, -}; - -static const struct matrix_keymap_data h3_keymap_data = { - .keymap = h3_keymap, - .keymap_size = ARRAY_SIZE(h3_keymap), -}; - -static struct omap_kp_platform_data h3_kp_data = { - .rows = 8, - .cols = 8, - .keymap_data = &h3_keymap_data, - .rep = true, - .delay = 9, - .dbounce = true, -}; - -static struct platform_device h3_kp_device = { - .name = "omap-keypad", - .id = -1, - .dev = { - .platform_data = &h3_kp_data, - }, - .num_resources = ARRAY_SIZE(h3_kp_resources), - .resource = h3_kp_resources, -}; - -static struct platform_device h3_lcd_device = { - .name = "lcd_h3", - .id = -1, -}; - -static struct spi_board_info h3_spi_board_info[] __initdata = { - [0] = { - .modalias = "tsc2101", - .bus_num = 2, - .chip_select = 0, - .max_speed_hz = 16000000, - /* .platform_data = &tsc_platform_data, */ - }, -}; - -static const struct gpio_led h3_gpio_led_pins[] = { - { - .name = "h3:red", - .default_trigger = "heartbeat", - .gpio = 3, - }, - { - .name = "h3:green", - .default_trigger = "cpu0", - .gpio = OMAP_MPUIO(4), - }, -}; - -static struct gpio_led_platform_data h3_gpio_led_data = { - .leds = h3_gpio_led_pins, - .num_leds = ARRAY_SIZE(h3_gpio_led_pins), -}; - -static struct platform_device h3_gpio_leds = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &h3_gpio_led_data, - }, -}; - -static struct platform_device *devices[] __initdata = { - &nor_device, - &nand_device, - &smc91x_device, - &intlat_device, - &h3_kp_device, - &h3_lcd_device, - &h3_gpio_leds, -}; - -static struct omap_usb_config h3_usb_config __initdata = { - /* usb1 has a Mini-AB port and external isp1301 transceiver */ - .otg = 2, - -#if IS_ENABLED(CONFIG_USB_OMAP) - .hmc_mode = 19, /* 0:host(off) 1:dev|otg 2:disabled */ -#elif IS_ENABLED(CONFIG_USB_OHCI_HCD) - /* NONSTANDARD CABLE NEEDED (B-to-Mini-B) */ - .hmc_mode = 20, /* 1:dev|otg(off) 1:host 2:disabled */ -#endif - - .pins[1] = 3, -}; - -static const struct omap_lcd_config h3_lcd_config __initconst = { - .ctrl_name = "internal", -}; - -static struct i2c_board_info __initdata h3_i2c_board_info[] = { - { - I2C_BOARD_INFO("tps65013", 0x48), - }, - { - I2C_BOARD_INFO("isp1301_omap", 0x2d), - }, -}; - -static void __init h3_init(void) -{ - h3_init_smc91x(); - - /* Here we assume the NOR boot config: NOR on CS3 (possibly swapped - * to address 0 by a dip switch), NAND on CS2B. The NAND driver will - * notice whether a NAND chip is enabled at probe time. - * - * H3 support NAND-boot, with a dip switch to put NOR on CS2B and NAND - * (which on H2 may be 16bit) on CS3. Try detecting that in code here, - * to avoid probing every possible flash configuration... - */ - nor_resource.end = nor_resource.start = omap_cs3_phys(); - nor_resource.end += SZ_32M - 1; - - nand_resource.end = nand_resource.start = OMAP_CS2B_PHYS; - nand_resource.end += SZ_4K - 1; - BUG_ON(gpio_request(H3_NAND_RB_GPIO_PIN, "NAND ready") < 0); - gpio_direction_input(H3_NAND_RB_GPIO_PIN); - - /* GPIO10 Func_MUX_CTRL reg bit 29:27, Configure V2 to mode1 as GPIO */ - /* GPIO10 pullup/down register, Enable pullup on GPIO10 */ - omap_cfg_reg(V2_1710_GPIO10); - - /* Mux pins for keypad */ - omap_cfg_reg(F18_1610_KBC0); - omap_cfg_reg(D20_1610_KBC1); - omap_cfg_reg(D19_1610_KBC2); - omap_cfg_reg(E18_1610_KBC3); - omap_cfg_reg(C21_1610_KBC4); - omap_cfg_reg(G18_1610_KBR0); - omap_cfg_reg(F19_1610_KBR1); - omap_cfg_reg(H14_1610_KBR2); - omap_cfg_reg(E20_1610_KBR3); - omap_cfg_reg(E19_1610_KBR4); - omap_cfg_reg(N19_1610_KBR5); - - /* GPIO based LEDs */ - omap_cfg_reg(P18_1610_GPIO3); - omap_cfg_reg(MPUIO4); - - smc91x_resources[1].start = gpio_to_irq(40); - smc91x_resources[1].end = gpio_to_irq(40); - platform_add_devices(devices, ARRAY_SIZE(devices)); - h3_spi_board_info[0].irq = gpio_to_irq(H3_TS_GPIO); - spi_register_board_info(h3_spi_board_info, - ARRAY_SIZE(h3_spi_board_info)); - omap_serial_init(); - h3_i2c_board_info[1].irq = gpio_to_irq(14); - omap_register_i2c_bus(1, 100, h3_i2c_board_info, - ARRAY_SIZE(h3_i2c_board_info)); - omap1_usb_init(&h3_usb_config); - h3_mmc_init(); - - omapfb_set_lcd_config(&h3_lcd_config); -} - -MACHINE_START(OMAP_H3, "TI OMAP1710 H3 board") - /* Maintainer: Texas Instruments, Inc. */ - .atag_offset = 0x100, - .map_io = omap16xx_map_io, - .init_early = omap1_init_early, - .init_irq = omap1_init_irq, - .handle_irq = omap1_handle_irq, - .init_machine = h3_init, - .init_late = omap1_init_late, - .init_time = omap1_timer_init, - .restart = omap1_restart, -MACHINE_END diff --git a/arch/arm/mach-omap1/board-h3.h b/arch/arm/mach-omap1/board-h3.h deleted file mode 100644 index 78de535be3c5..000000000000 --- a/arch/arm/mach-omap1/board-h3.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * arch/arm/mach-omap1/board-h3.h - * - * Copyright (C) 2001 RidgeRun, Inc. - * Copyright (C) 2004 Texas Instruments, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#ifndef __ASM_ARCH_OMAP_H3_H -#define __ASM_ARCH_OMAP_H3_H - -#define H3_TPS_GPIO_BASE (OMAP_MAX_GPIO_LINES + 16 /* MPUIO */) -# define H3_TPS_GPIO_MMC_PWR_EN (H3_TPS_GPIO_BASE + 4) - -extern void h3_mmc_init(void); - -#endif /* __ASM_ARCH_OMAP_H3_H */ diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c deleted file mode 100644 index 291d294b5824..000000000000 --- a/arch/arm/mach-omap1/board-htcherald.c +++ /dev/null @@ -1,585 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * HTC Herald board configuration - * Copyright (C) 2009 Cory Maccarrone - * Copyright (C) 2009 Wing Linux - * - * Based on the board-htcwizard.c file from the linwizard project: - * Copyright (C) 2006 Unai Uribarri - * Copyright (C) 2008 linwizard.sourceforge.net - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include "hardware.h" -#include "omap7xx.h" -#include "mmc.h" -#include "irqs.h" -#include "usb.h" -#include "common.h" - -/* LCD register definition */ -#define OMAP_LCDC_CONTROL (0xfffec000 + 0x00) -#define OMAP_LCDC_STATUS (0xfffec000 + 0x10) -#define OMAP_DMA_LCD_CCR (0xfffee300 + 0xc2) -#define OMAP_DMA_LCD_CTRL (0xfffee300 + 0xc4) -#define OMAP_LCDC_CTRL_LCD_EN (1 << 0) -#define OMAP_LCDC_STAT_DONE (1 << 0) - -/* GPIO definitions for the power button and keyboard slide switch */ -#define HTCHERALD_GPIO_POWER 139 -#define HTCHERALD_GPIO_SLIDE 174 -#define HTCHERALD_GIRQ_BTNS 141 - -/* GPIO definitions for the touchscreen */ -#define HTCHERALD_GPIO_TS 76 - -/* HTCPLD definitions */ - -/* - * CPLD Logic - * - * Chip 3 - 0x03 - * - * Function 7 6 5 4 3 2 1 0 - * ------------------------------------ - * DPAD light x x x x x x x 1 - * SoundDev x x x x 1 x x x - * Screen white 1 x x x x x x x - * MMC power on x x x x x 1 x x - * Happy times (n) 0 x x x x 1 x x - * - * Chip 4 - 0x04 - * - * Function 7 6 5 4 3 2 1 0 - * ------------------------------------ - * Keyboard light x x x x x x x 1 - * LCD Bright (4) x x x x x 1 1 x - * LCD Bright (3) x x x x x 0 1 x - * LCD Bright (2) x x x x x 1 0 x - * LCD Bright (1) x x x x x 0 0 x - * LCD Off x x x x 0 x x x - * LCD image (fb) 1 x x x x x x x - * LCD image (white) 0 x x x x x x x - * Caps lock LED x x 1 x x x x x - * - * Chip 5 - 0x05 - * - * Function 7 6 5 4 3 2 1 0 - * ------------------------------------ - * Red (solid) x x x x x 1 x x - * Red (flash) x x x x x x 1 x - * Green (GSM flash) x x x x 1 x x x - * Green (GSM solid) x x x 1 x x x x - * Green (wifi flash) x x 1 x x x x x - * Blue (bt flash) x 1 x x x x x x - * DPAD Int Enable 1 x x x x x x 0 - * - * (Combinations of the above can be made for different colors.) - * The direction pad interrupt enable must be set each time the - * interrupt is handled. - * - * Chip 6 - 0x06 - * - * Function 7 6 5 4 3 2 1 0 - * ------------------------------------ - * Vibrator x x x x 1 x x x - * Alt LED x x x 1 x x x x - * Screen white 1 x x x x x x x - * Screen white x x 1 x x x x x - * Screen white x 0 x x x x x x - * Enable kbd dpad x x x x x x 0 x - * Happy Times 0 1 0 x x x 0 x - */ - -/* - * HTCPLD GPIO lines start 16 after OMAP_MAX_GPIO_LINES to account - * for the 16 MPUIO lines. - */ -#define HTCPLD_GPIO_START_OFFSET (OMAP_MAX_GPIO_LINES + 16) -#define HTCPLD_IRQ(chip, offset) (OMAP_IRQ_END + 8 * (chip) + (offset)) -#define HTCPLD_BASE(chip, offset) \ - (HTCPLD_GPIO_START_OFFSET + 8 * (chip) + (offset)) - -#define HTCPLD_GPIO_LED_DPAD HTCPLD_BASE(0, 0) -#define HTCPLD_GPIO_LED_KBD HTCPLD_BASE(1, 0) -#define HTCPLD_GPIO_LED_CAPS HTCPLD_BASE(1, 5) -#define HTCPLD_GPIO_LED_RED_FLASH HTCPLD_BASE(2, 1) -#define HTCPLD_GPIO_LED_RED_SOLID HTCPLD_BASE(2, 2) -#define HTCPLD_GPIO_LED_GREEN_FLASH HTCPLD_BASE(2, 3) -#define HTCPLD_GPIO_LED_GREEN_SOLID HTCPLD_BASE(2, 4) -#define HTCPLD_GPIO_LED_WIFI HTCPLD_BASE(2, 5) -#define HTCPLD_GPIO_LED_BT HTCPLD_BASE(2, 6) -#define HTCPLD_GPIO_LED_VIBRATE HTCPLD_BASE(3, 3) -#define HTCPLD_GPIO_LED_ALT HTCPLD_BASE(3, 4) - -#define HTCPLD_GPIO_RIGHT_KBD HTCPLD_BASE(6, 7) -#define HTCPLD_GPIO_UP_KBD HTCPLD_BASE(6, 6) -#define HTCPLD_GPIO_LEFT_KBD HTCPLD_BASE(6, 5) -#define HTCPLD_GPIO_DOWN_KBD HTCPLD_BASE(6, 4) - -#define HTCPLD_GPIO_RIGHT_DPAD HTCPLD_BASE(7, 7) -#define HTCPLD_GPIO_UP_DPAD HTCPLD_BASE(7, 6) -#define HTCPLD_GPIO_LEFT_DPAD HTCPLD_BASE(7, 5) -#define HTCPLD_GPIO_DOWN_DPAD HTCPLD_BASE(7, 4) -#define HTCPLD_GPIO_ENTER_DPAD HTCPLD_BASE(7, 3) - -/* Chip 5 */ -#define HTCPLD_IRQ_RIGHT_KBD HTCPLD_IRQ(0, 7) -#define HTCPLD_IRQ_UP_KBD HTCPLD_IRQ(0, 6) -#define HTCPLD_IRQ_LEFT_KBD HTCPLD_IRQ(0, 5) -#define HTCPLD_IRQ_DOWN_KBD HTCPLD_IRQ(0, 4) - -/* Chip 6 */ -#define HTCPLD_IRQ_RIGHT_DPAD HTCPLD_IRQ(1, 7) -#define HTCPLD_IRQ_UP_DPAD HTCPLD_IRQ(1, 6) -#define HTCPLD_IRQ_LEFT_DPAD HTCPLD_IRQ(1, 5) -#define HTCPLD_IRQ_DOWN_DPAD HTCPLD_IRQ(1, 4) -#define HTCPLD_IRQ_ENTER_DPAD HTCPLD_IRQ(1, 3) - -/* Keyboard definition */ - -static const unsigned int htc_herald_keymap[] = { - KEY(0, 0, KEY_RECORD), /* Mail button */ - KEY(1, 0, KEY_CAMERA), /* Camera */ - KEY(2, 0, KEY_PHONE), /* Send key */ - KEY(3, 0, KEY_VOLUMEUP), /* Volume up */ - KEY(4, 0, KEY_F2), /* Right bar (landscape) */ - KEY(5, 0, KEY_MAIL), /* Win key (portrait) */ - KEY(6, 0, KEY_DIRECTORY), /* Right bar (portrait) */ - KEY(0, 1, KEY_LEFTCTRL), /* Windows key */ - KEY(1, 1, KEY_COMMA), - KEY(2, 1, KEY_M), - KEY(3, 1, KEY_K), - KEY(4, 1, KEY_SLASH), /* OK key */ - KEY(5, 1, KEY_I), - KEY(6, 1, KEY_U), - KEY(0, 2, KEY_LEFTALT), - KEY(1, 2, KEY_TAB), - KEY(2, 2, KEY_N), - KEY(3, 2, KEY_J), - KEY(4, 2, KEY_ENTER), - KEY(5, 2, KEY_H), - KEY(6, 2, KEY_Y), - KEY(0, 3, KEY_SPACE), - KEY(1, 3, KEY_L), - KEY(2, 3, KEY_B), - KEY(3, 3, KEY_V), - KEY(4, 3, KEY_BACKSPACE), - KEY(5, 3, KEY_G), - KEY(6, 3, KEY_T), - KEY(0, 4, KEY_CAPSLOCK), /* Shift */ - KEY(1, 4, KEY_C), - KEY(2, 4, KEY_F), - KEY(3, 4, KEY_R), - KEY(4, 4, KEY_O), - KEY(5, 4, KEY_E), - KEY(6, 4, KEY_D), - KEY(0, 5, KEY_X), - KEY(1, 5, KEY_Z), - KEY(2, 5, KEY_S), - KEY(3, 5, KEY_W), - KEY(4, 5, KEY_P), - KEY(5, 5, KEY_Q), - KEY(6, 5, KEY_A), - KEY(0, 6, KEY_CONNECT), /* Voice button */ - KEY(2, 6, KEY_CANCEL), /* End key */ - KEY(3, 6, KEY_VOLUMEDOWN), /* Volume down */ - KEY(4, 6, KEY_F1), /* Left bar (landscape) */ - KEY(5, 6, KEY_WWW), /* OK button (portrait) */ - KEY(6, 6, KEY_CALENDAR), /* Left bar (portrait) */ -}; - -static const struct matrix_keymap_data htc_herald_keymap_data = { - .keymap = htc_herald_keymap, - .keymap_size = ARRAY_SIZE(htc_herald_keymap), -}; - -static struct omap_kp_platform_data htcherald_kp_data = { - .rows = 7, - .cols = 7, - .delay = 20, - .rep = true, - .keymap_data = &htc_herald_keymap_data, -}; - -static struct resource kp_resources[] = { - [0] = { - .start = INT_7XX_MPUIO_KEYPAD, - .end = INT_7XX_MPUIO_KEYPAD, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device kp_device = { - .name = "omap-keypad", - .id = -1, - .dev = { - .platform_data = &htcherald_kp_data, - }, - .num_resources = ARRAY_SIZE(kp_resources), - .resource = kp_resources, -}; - -/* GPIO buttons for keyboard slide and power button */ -static struct gpio_keys_button herald_gpio_keys_table[] = { - {BTN_0, HTCHERALD_GPIO_POWER, 1, "POWER", EV_KEY, 1, 20}, - {SW_LID, HTCHERALD_GPIO_SLIDE, 0, "SLIDE", EV_SW, 1, 20}, - - {KEY_LEFT, HTCPLD_GPIO_LEFT_KBD, 1, "LEFT", EV_KEY, 1, 20}, - {KEY_RIGHT, HTCPLD_GPIO_RIGHT_KBD, 1, "RIGHT", EV_KEY, 1, 20}, - {KEY_UP, HTCPLD_GPIO_UP_KBD, 1, "UP", EV_KEY, 1, 20}, - {KEY_DOWN, HTCPLD_GPIO_DOWN_KBD, 1, "DOWN", EV_KEY, 1, 20}, - - {KEY_LEFT, HTCPLD_GPIO_LEFT_DPAD, 1, "DLEFT", EV_KEY, 1, 20}, - {KEY_RIGHT, HTCPLD_GPIO_RIGHT_DPAD, 1, "DRIGHT", EV_KEY, 1, 20}, - {KEY_UP, HTCPLD_GPIO_UP_DPAD, 1, "DUP", EV_KEY, 1, 20}, - {KEY_DOWN, HTCPLD_GPIO_DOWN_DPAD, 1, "DDOWN", EV_KEY, 1, 20}, - {KEY_ENTER, HTCPLD_GPIO_ENTER_DPAD, 1, "DENTER", EV_KEY, 1, 20}, -}; - -static struct gpio_keys_platform_data herald_gpio_keys_data = { - .buttons = herald_gpio_keys_table, - .nbuttons = ARRAY_SIZE(herald_gpio_keys_table), - .rep = true, -}; - -static struct platform_device herald_gpiokeys_device = { - .name = "gpio-keys", - .id = -1, - .dev = { - .platform_data = &herald_gpio_keys_data, - }, -}; - -/* LEDs for the Herald. These connect to the HTCPLD GPIO device. */ -static const struct gpio_led gpio_leds[] = { - {"dpad", NULL, HTCPLD_GPIO_LED_DPAD, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, - {"kbd", NULL, HTCPLD_GPIO_LED_KBD, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, - {"vibrate", NULL, HTCPLD_GPIO_LED_VIBRATE, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, - {"green_solid", NULL, HTCPLD_GPIO_LED_GREEN_SOLID, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, - {"green_flash", NULL, HTCPLD_GPIO_LED_GREEN_FLASH, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, - {"red_solid", "mmc0", HTCPLD_GPIO_LED_RED_SOLID, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, - {"red_flash", NULL, HTCPLD_GPIO_LED_RED_FLASH, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, - {"wifi", NULL, HTCPLD_GPIO_LED_WIFI, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, - {"bt", NULL, HTCPLD_GPIO_LED_BT, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, - {"caps", NULL, HTCPLD_GPIO_LED_CAPS, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, - {"alt", NULL, HTCPLD_GPIO_LED_ALT, 0, 0, LEDS_GPIO_DEFSTATE_OFF}, -}; - -static struct gpio_led_platform_data gpio_leds_data = { - .leds = gpio_leds, - .num_leds = ARRAY_SIZE(gpio_leds), -}; - -static struct platform_device gpio_leds_device = { - .name = "leds-gpio", - .id = 0, - .dev = { - .platform_data = &gpio_leds_data, - }, -}; - -/* HTC PLD chips */ - -static struct resource htcpld_resources[] = { - [0] = { - .flags = IORESOURCE_IRQ, - }, -}; - -static struct htcpld_chip_platform_data htcpld_chips[] = { - [0] = { - .addr = 0x03, - .reset = 0x04, - .num_gpios = 8, - .gpio_out_base = HTCPLD_BASE(0, 0), - .gpio_in_base = HTCPLD_BASE(4, 0), - }, - [1] = { - .addr = 0x04, - .reset = 0x8e, - .num_gpios = 8, - .gpio_out_base = HTCPLD_BASE(1, 0), - .gpio_in_base = HTCPLD_BASE(5, 0), - }, - [2] = { - .addr = 0x05, - .reset = 0x80, - .num_gpios = 8, - .gpio_out_base = HTCPLD_BASE(2, 0), - .gpio_in_base = HTCPLD_BASE(6, 0), - .irq_base = HTCPLD_IRQ(0, 0), - .num_irqs = 8, - }, - [3] = { - .addr = 0x06, - .reset = 0x40, - .num_gpios = 8, - .gpio_out_base = HTCPLD_BASE(3, 0), - .gpio_in_base = HTCPLD_BASE(7, 0), - .irq_base = HTCPLD_IRQ(1, 0), - .num_irqs = 8, - }, -}; - -static struct htcpld_core_platform_data htcpld_pfdata = { - .i2c_adapter_id = 1, - - .chip = htcpld_chips, - .num_chip = ARRAY_SIZE(htcpld_chips), -}; - -static struct platform_device htcpld_device = { - .name = "i2c-htcpld", - .id = -1, - .resource = htcpld_resources, - .num_resources = ARRAY_SIZE(htcpld_resources), - .dev = { - .platform_data = &htcpld_pfdata, - }, -}; - -/* USB Device */ -static struct omap_usb_config htcherald_usb_config __initdata = { - .otg = 0, - .register_host = 0, - .register_dev = 1, - .hmc_mode = 4, - .pins[0] = 2, -}; - -/* LCD Device resources */ -static const struct omap_lcd_config htcherald_lcd_config __initconst = { - .ctrl_name = "internal", -}; - -static struct platform_device lcd_device = { - .name = "lcd_htcherald", - .id = -1, -}; - -/* MMC Card */ -#if IS_ENABLED(CONFIG_MMC_OMAP) -static struct omap_mmc_platform_data htc_mmc1_data = { - .nr_slots = 1, - .switch_slot = NULL, - .slots[0] = { - .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, - .name = "mmcblk", - .nomux = 1, - .wires = 4, - .switch_pin = -1, - }, -}; - -static struct omap_mmc_platform_data *htc_mmc_data[1]; -#endif - - -/* Platform devices for the Herald */ -static struct platform_device *devices[] __initdata = { - &kp_device, - &lcd_device, - &htcpld_device, - &gpio_leds_device, - &herald_gpiokeys_device, -}; - -/* - * Touchscreen - */ -static const struct ads7846_platform_data htcherald_ts_platform_data = { - .model = 7846, - .keep_vref_on = 1, - .x_plate_ohms = 496, - .gpio_pendown = HTCHERALD_GPIO_TS, - .pressure_max = 10000, - .pressure_min = 5000, - .x_min = 528, - .x_max = 3760, - .y_min = 624, - .y_max = 3760, -}; - -static struct spi_board_info __initdata htcherald_spi_board_info[] = { - { - .modalias = "ads7846", - .platform_data = &htcherald_ts_platform_data, - .max_speed_hz = 2500000, - .bus_num = 2, - .chip_select = 1, - } -}; - -/* - * Init functions from here on - */ - -static void __init htcherald_lcd_init(void) -{ - u32 reg; - unsigned int tries = 200; - - /* disable controller if active */ - reg = omap_readl(OMAP_LCDC_CONTROL); - if (reg & OMAP_LCDC_CTRL_LCD_EN) { - reg &= ~OMAP_LCDC_CTRL_LCD_EN; - omap_writel(reg, OMAP_LCDC_CONTROL); - - /* wait for end of frame */ - while (!(omap_readl(OMAP_LCDC_STATUS) & OMAP_LCDC_STAT_DONE)) { - tries--; - if (!tries) - break; - } - if (!tries) - pr_err("Timeout waiting for end of frame -- LCD may not be available\n"); - - /* turn off DMA */ - reg = omap_readw(OMAP_DMA_LCD_CCR); - reg &= ~(1 << 7); - omap_writew(reg, OMAP_DMA_LCD_CCR); - - reg = omap_readw(OMAP_DMA_LCD_CTRL); - reg &= ~(1 << 8); - omap_writew(reg, OMAP_DMA_LCD_CTRL); - } -} - -static void __init htcherald_map_io(void) -{ - omap7xx_map_io(); - - /* - * The LCD panel must be disabled and DMA turned off here, as doing - * it later causes the LCD never to reinitialize. - */ - htcherald_lcd_init(); - - printk(KERN_INFO "htcherald_map_io done.\n"); -} - -static void __init htcherald_disable_watchdog(void) -{ - /* Disable watchdog if running */ - if (omap_readl(OMAP_WDT_TIMER_MODE) & 0x8000) { - /* - * disable a potentially running watchdog timer before - * it kills us. - */ - printk(KERN_WARNING "OMAP850 Watchdog seems to be activated, disabling it for now.\n"); - omap_writel(0xF5, OMAP_WDT_TIMER_MODE); - omap_writel(0xA0, OMAP_WDT_TIMER_MODE); - } -} - -#define HTCHERALD_GPIO_USB_EN1 33 -#define HTCHERALD_GPIO_USB_EN2 73 -#define HTCHERALD_GPIO_USB_DM 35 -#define HTCHERALD_GPIO_USB_DP 36 - -static void __init htcherald_usb_enable(void) -{ - unsigned int tries = 20; - unsigned int value = 0; - - /* Request the GPIOs we need to control here */ - if (gpio_request(HTCHERALD_GPIO_USB_EN1, "herald_usb") < 0) - goto err1; - - if (gpio_request(HTCHERALD_GPIO_USB_EN2, "herald_usb") < 0) - goto err2; - - if (gpio_request(HTCHERALD_GPIO_USB_DM, "herald_usb") < 0) - goto err3; - - if (gpio_request(HTCHERALD_GPIO_USB_DP, "herald_usb") < 0) - goto err4; - - /* force USB_EN GPIO to 0 */ - do { - /* output low */ - gpio_direction_output(HTCHERALD_GPIO_USB_EN1, 0); - } while ((value = gpio_get_value(HTCHERALD_GPIO_USB_EN1)) == 1 && - --tries); - - if (value == 1) - printk(KERN_WARNING "Unable to reset USB, trying to continue\n"); - - gpio_direction_output(HTCHERALD_GPIO_USB_EN2, 0); /* output low */ - gpio_direction_input(HTCHERALD_GPIO_USB_DM); /* input */ - gpio_direction_input(HTCHERALD_GPIO_USB_DP); /* input */ - - goto done; - -err4: - gpio_free(HTCHERALD_GPIO_USB_DM); -err3: - gpio_free(HTCHERALD_GPIO_USB_EN2); -err2: - gpio_free(HTCHERALD_GPIO_USB_EN1); -err1: - printk(KERN_ERR "Unabled to request GPIO for USB\n"); -done: - printk(KERN_INFO "USB setup complete.\n"); -} - -static void __init htcherald_init(void) -{ - printk(KERN_INFO "HTC Herald init.\n"); - - /* Do board initialization before we register all the devices */ - htcpld_resources[0].start = gpio_to_irq(HTCHERALD_GIRQ_BTNS); - htcpld_resources[0].end = gpio_to_irq(HTCHERALD_GIRQ_BTNS); - platform_add_devices(devices, ARRAY_SIZE(devices)); - - htcherald_disable_watchdog(); - - htcherald_usb_enable(); - omap1_usb_init(&htcherald_usb_config); - - htcherald_spi_board_info[0].irq = gpio_to_irq(HTCHERALD_GPIO_TS); - spi_register_board_info(htcherald_spi_board_info, - ARRAY_SIZE(htcherald_spi_board_info)); - - omap_register_i2c_bus(1, 100, NULL, 0); - -#if IS_ENABLED(CONFIG_MMC_OMAP) - htc_mmc_data[0] = &htc_mmc1_data; - omap1_init_mmc(htc_mmc_data, 1); -#endif - - omapfb_set_lcd_config(&htcherald_lcd_config); -} - -MACHINE_START(HERALD, "HTC Herald") - /* Maintainer: Cory Maccarrone */ - /* Maintainer: wing-linux.sourceforge.net */ - .atag_offset = 0x100, - .map_io = htcherald_map_io, - .init_early = omap1_init_early, - .init_irq = omap1_init_irq, - .handle_irq = omap1_handle_irq, - .init_machine = htcherald_init, - .init_late = omap1_init_late, - .init_time = omap1_timer_init, - .restart = omap1_restart, -MACHINE_END diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c deleted file mode 100644 index 6deb4ca079e9..000000000000 --- a/arch/arm/mach-omap1/board-innovator.c +++ /dev/null @@ -1,481 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/mach-omap1/board-innovator.c - * - * Board specific inits for OMAP-1510 and OMAP-1610 Innovator - * - * Copyright (C) 2001 RidgeRun, Inc. - * Author: Greg Lonnon - * - * Copyright (C) 2002 MontaVista Software, Inc. - * - * Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6 - * Copyright (C) 2004 Nokia Corporation by Tony Lindrgen - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include "tc.h" -#include "mux.h" -#include "flash.h" -#include "hardware.h" -#include "usb.h" -#include "iomap.h" -#include "common.h" -#include "mmc.h" - -/* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */ -#define INNOVATOR1610_ETHR_START 0x04000300 - -static const unsigned int innovator_keymap[] = { - KEY(0, 0, KEY_F1), - KEY(3, 0, KEY_DOWN), - KEY(1, 1, KEY_F2), - KEY(2, 1, KEY_RIGHT), - KEY(0, 2, KEY_F3), - KEY(1, 2, KEY_F4), - KEY(2, 2, KEY_UP), - KEY(2, 3, KEY_ENTER), - KEY(3, 3, KEY_LEFT), -}; - -static struct mtd_partition innovator_partitions[] = { - /* bootloader (U-Boot, etc) in first sector */ - { - .name = "bootloader", - .offset = 0, - .size = SZ_128K, - .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, - /* bootloader params in the next sector */ - { - .name = "params", - .offset = MTDPART_OFS_APPEND, - .size = SZ_128K, - .mask_flags = 0, - }, - /* kernel */ - { - .name = "kernel", - .offset = MTDPART_OFS_APPEND, - .size = SZ_2M, - .mask_flags = 0 - }, - /* rest of flash1 is a file system */ - { - .name = "rootfs", - .offset = MTDPART_OFS_APPEND, - .size = SZ_16M - SZ_2M - 2 * SZ_128K, - .mask_flags = 0 - }, - /* file system */ - { - .name = "filesystem", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - .mask_flags = 0 - } -}; - -static struct physmap_flash_data innovator_flash_data = { - .width = 2, - .set_vpp = omap1_set_vpp, - .parts = innovator_partitions, - .nr_parts = ARRAY_SIZE(innovator_partitions), -}; - -static struct resource innovator_flash_resource = { - .start = OMAP_CS0_PHYS, - .end = OMAP_CS0_PHYS + SZ_32M - 1, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device innovator_flash_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &innovator_flash_data, - }, - .num_resources = 1, - .resource = &innovator_flash_resource, -}; - -static struct resource innovator_kp_resources[] = { - [0] = { - .start = INT_KEYBOARD, - .end = INT_KEYBOARD, - .flags = IORESOURCE_IRQ, - }, -}; - -static const struct matrix_keymap_data innovator_keymap_data = { - .keymap = innovator_keymap, - .keymap_size = ARRAY_SIZE(innovator_keymap), -}; - -static struct omap_kp_platform_data innovator_kp_data = { - .rows = 8, - .cols = 8, - .keymap_data = &innovator_keymap_data, - .delay = 4, -}; - -static struct platform_device innovator_kp_device = { - .name = "omap-keypad", - .id = -1, - .dev = { - .platform_data = &innovator_kp_data, - }, - .num_resources = ARRAY_SIZE(innovator_kp_resources), - .resource = innovator_kp_resources, -}; - -static struct smc91x_platdata innovator_smc91x_info = { - .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, - .leda = RPC_LED_100_10, - .ledb = RPC_LED_TX_RX, -}; - -#ifdef CONFIG_ARCH_OMAP15XX - -#include -#include - - -/* Only FPGA needs to be mapped here. All others are done with ioremap */ -static struct map_desc innovator1510_io_desc[] __initdata = { - { - .virtual = OMAP1510_FPGA_BASE, - .pfn = __phys_to_pfn(OMAP1510_FPGA_START), - .length = OMAP1510_FPGA_SIZE, - .type = MT_DEVICE - } -}; - -static struct resource innovator1510_smc91x_resources[] = { - [0] = { - .start = OMAP1510_FPGA_ETHR_START, /* Physical */ - .end = OMAP1510_FPGA_ETHR_START + 0xf, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = OMAP1510_INT_ETHER, - .end = OMAP1510_INT_ETHER, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, - }, -}; - -static struct platform_device innovator1510_smc91x_device = { - .name = "smc91x", - .id = 0, - .dev = { - .platform_data = &innovator_smc91x_info, - }, - .num_resources = ARRAY_SIZE(innovator1510_smc91x_resources), - .resource = innovator1510_smc91x_resources, -}; - -static struct platform_device innovator1510_lcd_device = { - .name = "lcd_inn1510", - .id = -1, - .dev = { - .platform_data = (void __force *)OMAP1510_FPGA_LCD_PANEL_CONTROL, - } -}; - -static struct platform_device innovator1510_spi_device = { - .name = "spi_inn1510", - .id = -1, -}; - -static struct platform_device *innovator1510_devices[] __initdata = { - &innovator_flash_device, - &innovator1510_smc91x_device, - &innovator_kp_device, - &innovator1510_lcd_device, - &innovator1510_spi_device, -}; - -static int innovator_get_pendown_state(void) -{ - return !(__raw_readb(OMAP1510_FPGA_TOUCHSCREEN) & (1 << 5)); -} - -static const struct ads7846_platform_data innovator1510_ts_info = { - .model = 7846, - .vref_delay_usecs = 100, /* internal, no capacitor */ - .x_plate_ohms = 419, - .y_plate_ohms = 486, - .get_pendown_state = innovator_get_pendown_state, -}; - -static struct spi_board_info __initdata innovator1510_boardinfo[] = { { - /* FPGA (bus "10") CS0 has an ads7846e */ - .modalias = "ads7846", - .platform_data = &innovator1510_ts_info, - .irq = OMAP1510_INT_FPGA_TS, - .max_speed_hz = 120000 /* max sample rate at 3V */ - * 26 /* command + data + overhead */, - .bus_num = 10, - .chip_select = 0, -} }; - -#endif /* CONFIG_ARCH_OMAP15XX */ - -#ifdef CONFIG_ARCH_OMAP16XX - -static struct resource innovator1610_smc91x_resources[] = { - [0] = { - .start = INNOVATOR1610_ETHR_START, /* Physical */ - .end = INNOVATOR1610_ETHR_START + 0xf, - .flags = IORESOURCE_MEM, - }, - [1] = { - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE, - }, -}; - -static struct platform_device innovator1610_smc91x_device = { - .name = "smc91x", - .id = 0, - .dev = { - .platform_data = &innovator_smc91x_info, - }, - .num_resources = ARRAY_SIZE(innovator1610_smc91x_resources), - .resource = innovator1610_smc91x_resources, -}; - -static struct platform_device innovator1610_lcd_device = { - .name = "inn1610_lcd", - .id = -1, -}; - -static struct platform_device *innovator1610_devices[] __initdata = { - &innovator_flash_device, - &innovator1610_smc91x_device, - &innovator_kp_device, - &innovator1610_lcd_device, -}; - -#endif /* CONFIG_ARCH_OMAP16XX */ - -static void __init innovator_init_smc91x(void) -{ - if (cpu_is_omap1510()) { - __raw_writeb(__raw_readb(OMAP1510_FPGA_RST) & ~1, - OMAP1510_FPGA_RST); - udelay(750); - } else { - if (gpio_request(0, "SMC91x irq") < 0) { - printk("Error requesting gpio 0 for smc91x irq\n"); - return; - } - } -} - -#ifdef CONFIG_ARCH_OMAP15XX -/* - * Board specific gang-switched transceiver power on/off. - */ -static int innovator_omap_ohci_transceiver_power(int on) -{ - if (on) - __raw_writeb(__raw_readb(INNOVATOR_FPGA_CAM_USB_CONTROL) - | ((1 << 5/*usb1*/) | (1 << 3/*usb2*/)), - INNOVATOR_FPGA_CAM_USB_CONTROL); - else - __raw_writeb(__raw_readb(INNOVATOR_FPGA_CAM_USB_CONTROL) - & ~((1 << 5/*usb1*/) | (1 << 3/*usb2*/)), - INNOVATOR_FPGA_CAM_USB_CONTROL); - - return 0; -} - -static struct omap_usb_config innovator1510_usb_config __initdata = { - /* for bundled non-standard host and peripheral cables */ - .hmc_mode = 4, - - .register_host = 1, - .pins[1] = 6, - .pins[2] = 6, /* Conflicts with UART2 */ - - .register_dev = 1, - .pins[0] = 2, - - .transceiver_power = innovator_omap_ohci_transceiver_power, -}; - -static const struct omap_lcd_config innovator1510_lcd_config __initconst = { - .ctrl_name = "internal", -}; -#endif - -#ifdef CONFIG_ARCH_OMAP16XX -static struct omap_usb_config h2_usb_config __initdata = { - /* usb1 has a Mini-AB port and external isp1301 transceiver */ - .otg = 2, - -#if IS_ENABLED(CONFIG_USB_OMAP) - .hmc_mode = 19, /* 0:host(off) 1:dev|otg 2:disabled */ - /* .hmc_mode = 21,*/ /* 0:host(off) 1:dev(loopback) 2:host(loopback) */ -#elif IS_ENABLED(CONFIG_USB_OHCI_HCD) - /* NONSTANDARD CABLE NEEDED (B-to-Mini-B) */ - .hmc_mode = 20, /* 1:dev|otg(off) 1:host 2:disabled */ -#endif - - .pins[1] = 3, -}; - -static const struct omap_lcd_config innovator1610_lcd_config __initconst = { - .ctrl_name = "internal", -}; -#endif - -#if IS_ENABLED(CONFIG_MMC_OMAP) - -static int mmc_set_power(struct device *dev, int slot, int power_on, - int vdd) -{ - if (power_on) - __raw_writeb(__raw_readb(OMAP1510_FPGA_POWER) | (1 << 3), - OMAP1510_FPGA_POWER); - else - __raw_writeb(__raw_readb(OMAP1510_FPGA_POWER) & ~(1 << 3), - OMAP1510_FPGA_POWER); - - return 0; -} - -/* - * Innovator could use the following functions tested: - * - mmc_get_wp that uses OMAP_MPUIO(3) - * - mmc_get_cover_state that uses FPGA F4 UIO43 - */ -static struct omap_mmc_platform_data mmc1_data = { - .nr_slots = 1, - .slots[0] = { - .set_power = mmc_set_power, - .wires = 4, - .name = "mmcblk", - }, -}; - -static struct omap_mmc_platform_data *mmc_data[OMAP16XX_NR_MMC]; - -static void __init innovator_mmc_init(void) -{ - mmc_data[0] = &mmc1_data; - omap1_init_mmc(mmc_data, OMAP15XX_NR_MMC); -} - -#else -static inline void innovator_mmc_init(void) -{ -} -#endif - -static void __init innovator_init(void) -{ - if (cpu_is_omap1510()) - omap1510_fpga_init_irq(); - innovator_init_smc91x(); - -#ifdef CONFIG_ARCH_OMAP15XX - if (cpu_is_omap1510()) { - unsigned char reg; - - /* mux pins for uarts */ - omap_cfg_reg(UART1_TX); - omap_cfg_reg(UART1_RTS); - omap_cfg_reg(UART2_TX); - omap_cfg_reg(UART2_RTS); - omap_cfg_reg(UART3_TX); - omap_cfg_reg(UART3_RX); - - reg = __raw_readb(OMAP1510_FPGA_POWER); - reg |= OMAP1510_FPGA_PCR_COM1_EN; - __raw_writeb(reg, OMAP1510_FPGA_POWER); - udelay(10); - - reg = __raw_readb(OMAP1510_FPGA_POWER); - reg |= OMAP1510_FPGA_PCR_COM2_EN; - __raw_writeb(reg, OMAP1510_FPGA_POWER); - udelay(10); - - platform_add_devices(innovator1510_devices, ARRAY_SIZE(innovator1510_devices)); - spi_register_board_info(innovator1510_boardinfo, - ARRAY_SIZE(innovator1510_boardinfo)); - } -#endif -#ifdef CONFIG_ARCH_OMAP16XX - if (!cpu_is_omap1510()) { - innovator1610_smc91x_resources[1].start = gpio_to_irq(0); - innovator1610_smc91x_resources[1].end = gpio_to_irq(0); - platform_add_devices(innovator1610_devices, ARRAY_SIZE(innovator1610_devices)); - } -#endif - -#ifdef CONFIG_ARCH_OMAP15XX - if (cpu_is_omap1510()) { - omap1_usb_init(&innovator1510_usb_config); - omapfb_set_lcd_config(&innovator1510_lcd_config); - } -#endif -#ifdef CONFIG_ARCH_OMAP16XX - if (cpu_is_omap1610()) { - omap1_usb_init(&h2_usb_config); - omapfb_set_lcd_config(&innovator1610_lcd_config); - } -#endif - omap_serial_init(); - omap_register_i2c_bus(1, 100, NULL, 0); - innovator_mmc_init(); -} - -/* - * REVISIT: Assume 15xx for now, we don't want to do revision check - * until later on. The right way to fix this is to set up a different - * machine_id for 16xx Innovator, or use device tree. - */ -static void __init innovator_map_io(void) -{ -#ifdef CONFIG_ARCH_OMAP15XX - omap15xx_map_io(); - - iotable_init(innovator1510_io_desc, ARRAY_SIZE(innovator1510_io_desc)); - udelay(10); /* Delay needed for FPGA */ - - /* Dump the Innovator FPGA rev early - useful info for support. */ - pr_debug("Innovator FPGA Rev %d.%d Board Rev %d\n", - __raw_readb(OMAP1510_FPGA_REV_HIGH), - __raw_readb(OMAP1510_FPGA_REV_LOW), - __raw_readb(OMAP1510_FPGA_BOARD_REV)); -#endif -} - -MACHINE_START(OMAP_INNOVATOR, "TI-Innovator") - /* Maintainer: MontaVista Software, Inc. */ - .atag_offset = 0x100, - .map_io = innovator_map_io, - .init_early = omap1_init_early, - .init_irq = omap1_init_irq, - .handle_irq = omap1_handle_irq, - .init_machine = innovator_init, - .init_late = omap1_init_late, - .init_time = omap1_timer_init, - .restart = omap1_restart, -MACHINE_END diff --git a/arch/arm/mach-omap1/board-nand.c b/arch/arm/mach-omap1/board-nand.c deleted file mode 100644 index 479ab9be784d..000000000000 --- a/arch/arm/mach-omap1/board-nand.c +++ /dev/null @@ -1,33 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/mach-omap1/board-nand.c - * - * Common OMAP1 board NAND code - * - * Copyright (C) 2004, 2012 Texas Instruments, Inc. - * Copyright (C) 2002 MontaVista Software, Inc. - * Copyright (C) 2001 RidgeRun, Inc. - * Author: RidgeRun, Inc. - * Greg Lonnon (glonnon@ridgerun.com) or info@ridgerun.com - */ -#include -#include -#include -#include - -#include "common.h" - -void omap1_nand_cmd_ctl(struct nand_chip *this, int cmd, unsigned int ctrl) -{ - unsigned long mask; - - if (cmd == NAND_CMD_NONE) - return; - - mask = (ctrl & NAND_CLE) ? 0x02 : 0; - if (ctrl & NAND_ALE) - mask |= 0x04; - - writeb(cmd, this->legacy.IO_ADDR_W + mask); -} - diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c deleted file mode 100644 index 537f0e6a2ff7..000000000000 --- a/arch/arm/mach-omap1/board-palmtt.c +++ /dev/null @@ -1,285 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/mach-omap1/board-palmtt.c - * - * Modified from board-palmtt2.c - * - * Modified and amended for Palm Tungsten|T - * by Marek Vasut - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include "tc.h" -#include "flash.h" -#include "mux.h" -#include "hardware.h" -#include "usb.h" -#include "common.h" - -#define PALMTT_USBDETECT_GPIO 0 -#define PALMTT_CABLE_GPIO 1 -#define PALMTT_LED_GPIO 3 -#define PALMTT_PENIRQ_GPIO 6 -#define PALMTT_MMC_WP_GPIO 8 -#define PALMTT_HDQ_GPIO 11 - -static const unsigned int palmtt_keymap[] = { - KEY(0, 0, KEY_ESC), - KEY(1, 0, KEY_SPACE), - KEY(2, 0, KEY_LEFTCTRL), - KEY(3, 0, KEY_TAB), - KEY(4, 0, KEY_ENTER), - KEY(0, 1, KEY_LEFT), - KEY(1, 1, KEY_DOWN), - KEY(2, 1, KEY_UP), - KEY(3, 1, KEY_RIGHT), - KEY(0, 2, KEY_SLEEP), - KEY(4, 2, KEY_Y), -}; - -static struct mtd_partition palmtt_partitions[] = { - { - .name = "write8k", - .offset = 0, - .size = SZ_8K, - .mask_flags = 0, - }, - { - .name = "PalmOS-BootLoader(ro)", - .offset = SZ_8K, - .size = 7 * SZ_8K, - .mask_flags = MTD_WRITEABLE, - }, - { - .name = "u-boot", - .offset = MTDPART_OFS_APPEND, - .size = 8 * SZ_8K, - .mask_flags = 0, - }, - { - .name = "PalmOS-FS(ro)", - .offset = MTDPART_OFS_APPEND, - .size = 7 * SZ_1M + 4 * SZ_64K - 16 * SZ_8K, - .mask_flags = MTD_WRITEABLE, - }, - { - .name = "u-boot(rez)", - .offset = MTDPART_OFS_APPEND, - .size = SZ_128K, - .mask_flags = 0 - }, - { - .name = "empty", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - .mask_flags = 0 - } -}; - -static struct physmap_flash_data palmtt_flash_data = { - .width = 2, - .set_vpp = omap1_set_vpp, - .parts = palmtt_partitions, - .nr_parts = ARRAY_SIZE(palmtt_partitions), -}; - -static struct resource palmtt_flash_resource = { - .start = OMAP_CS0_PHYS, - .end = OMAP_CS0_PHYS + SZ_8M - 1, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device palmtt_flash_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &palmtt_flash_data, - }, - .num_resources = 1, - .resource = &palmtt_flash_resource, -}; - -static struct resource palmtt_kp_resources[] = { - [0] = { - .start = INT_KEYBOARD, - .end = INT_KEYBOARD, - .flags = IORESOURCE_IRQ, - }, -}; - -static const struct matrix_keymap_data palmtt_keymap_data = { - .keymap = palmtt_keymap, - .keymap_size = ARRAY_SIZE(palmtt_keymap), -}; - -static struct omap_kp_platform_data palmtt_kp_data = { - .rows = 6, - .cols = 3, - .keymap_data = &palmtt_keymap_data, -}; - -static struct platform_device palmtt_kp_device = { - .name = "omap-keypad", - .id = -1, - .dev = { - .platform_data = &palmtt_kp_data, - }, - .num_resources = ARRAY_SIZE(palmtt_kp_resources), - .resource = palmtt_kp_resources, -}; - -static struct platform_device palmtt_lcd_device = { - .name = "lcd_palmtt", - .id = -1, -}; - -static struct platform_device palmtt_spi_device = { - .name = "spi_palmtt", - .id = -1, -}; - -static struct omap_backlight_config palmtt_backlight_config = { - .default_intensity = 0xa0, -}; - -static struct platform_device palmtt_backlight_device = { - .name = "omap-bl", - .id = -1, - .dev = { - .platform_data= &palmtt_backlight_config, - }, -}; - -static struct omap_led_config palmtt_led_config[] = { - { - .cdev = { - .name = "palmtt:led0", - }, - .gpio = PALMTT_LED_GPIO, - }, -}; - -static struct omap_led_platform_data palmtt_led_data = { - .nr_leds = ARRAY_SIZE(palmtt_led_config), - .leds = palmtt_led_config, -}; - -static struct platform_device palmtt_led_device = { - .name = "omap-led", - .id = -1, - .dev = { - .platform_data = &palmtt_led_data, - }, -}; - -static struct platform_device *palmtt_devices[] __initdata = { - &palmtt_flash_device, - &palmtt_kp_device, - &palmtt_lcd_device, - &palmtt_spi_device, - &palmtt_backlight_device, - &palmtt_led_device, -}; - -static int palmtt_get_pendown_state(void) -{ - return !gpio_get_value(6); -} - -static const struct ads7846_platform_data palmtt_ts_info = { - .model = 7846, - .vref_delay_usecs = 100, /* internal, no capacitor */ - .x_plate_ohms = 419, - .y_plate_ohms = 486, - .get_pendown_state = palmtt_get_pendown_state, -}; - -static struct spi_board_info __initdata palmtt_boardinfo[] = { - { - /* MicroWire (bus 2) CS0 has an ads7846e */ - .modalias = "ads7846", - .platform_data = &palmtt_ts_info, - .max_speed_hz = 120000 /* max sample rate at 3V */ - * 26 /* command + data + overhead */, - .bus_num = 2, - .chip_select = 0, - } -}; - -static struct omap_usb_config palmtt_usb_config __initdata = { - .register_dev = 1, - .hmc_mode = 0, - .pins[0] = 2, -}; - -static const struct omap_lcd_config palmtt_lcd_config __initconst = { - .ctrl_name = "internal", -}; - -static void __init omap_mpu_wdt_mode(int mode) { - if (mode) - omap_writew(0x8000, OMAP_WDT_TIMER_MODE); - else { - omap_writew(0x00f5, OMAP_WDT_TIMER_MODE); - omap_writew(0x00a0, OMAP_WDT_TIMER_MODE); - } -} - -static void __init omap_palmtt_init(void) -{ - /* mux pins for uarts */ - omap_cfg_reg(UART1_TX); - omap_cfg_reg(UART1_RTS); - omap_cfg_reg(UART2_TX); - omap_cfg_reg(UART2_RTS); - omap_cfg_reg(UART3_TX); - omap_cfg_reg(UART3_RX); - - omap_mpu_wdt_mode(0); - - platform_add_devices(palmtt_devices, ARRAY_SIZE(palmtt_devices)); - - palmtt_boardinfo[0].irq = gpio_to_irq(6); - spi_register_board_info(palmtt_boardinfo,ARRAY_SIZE(palmtt_boardinfo)); - omap_serial_init(); - omap1_usb_init(&palmtt_usb_config); - omap_register_i2c_bus(1, 100, NULL, 0); - - omapfb_set_lcd_config(&palmtt_lcd_config); -} - -MACHINE_START(OMAP_PALMTT, "OMAP1510 based Palm Tungsten|T") - .atag_offset = 0x100, - .map_io = omap15xx_map_io, - .init_early = omap1_init_early, - .init_irq = omap1_init_irq, - .handle_irq = omap1_handle_irq, - .init_machine = omap_palmtt_init, - .init_late = omap1_init_late, - .init_time = omap1_timer_init, - .restart = omap1_restart, -MACHINE_END diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c deleted file mode 100644 index 47f08ae5a2f3..000000000000 --- a/arch/arm/mach-omap1/board-palmz71.c +++ /dev/null @@ -1,300 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/mach-omap1/board-palmz71.c - * - * Modified from board-generic.c - * - * Support for the Palm Zire71 PDA. - * - * Original version : Laurent Gonzalez - * - * Modified for zire71 : Marek Vasut - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include "tc.h" -#include "flash.h" -#include "mux.h" -#include "hardware.h" -#include "usb.h" -#include "common.h" - -#define PALMZ71_USBDETECT_GPIO 0 -#define PALMZ71_PENIRQ_GPIO 6 -#define PALMZ71_MMC_WP_GPIO 8 -#define PALMZ71_HDQ_GPIO 11 - -#define PALMZ71_HOTSYNC_GPIO OMAP_MPUIO(1) -#define PALMZ71_CABLE_GPIO OMAP_MPUIO(2) -#define PALMZ71_SLIDER_GPIO OMAP_MPUIO(3) -#define PALMZ71_MMC_IN_GPIO OMAP_MPUIO(4) - -static const unsigned int palmz71_keymap[] = { - KEY(0, 0, KEY_F1), - KEY(1, 0, KEY_F2), - KEY(2, 0, KEY_F3), - KEY(3, 0, KEY_F4), - KEY(4, 0, KEY_POWER), - KEY(0, 1, KEY_LEFT), - KEY(1, 1, KEY_DOWN), - KEY(2, 1, KEY_UP), - KEY(3, 1, KEY_RIGHT), - KEY(4, 1, KEY_ENTER), - KEY(0, 2, KEY_CAMERA), -}; - -static const struct matrix_keymap_data palmz71_keymap_data = { - .keymap = palmz71_keymap, - .keymap_size = ARRAY_SIZE(palmz71_keymap), -}; - -static struct omap_kp_platform_data palmz71_kp_data = { - .rows = 8, - .cols = 8, - .keymap_data = &palmz71_keymap_data, - .rep = true, - .delay = 80, -}; - -static struct resource palmz71_kp_resources[] = { - [0] = { - .start = INT_KEYBOARD, - .end = INT_KEYBOARD, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device palmz71_kp_device = { - .name = "omap-keypad", - .id = -1, - .dev = { - .platform_data = &palmz71_kp_data, - }, - .num_resources = ARRAY_SIZE(palmz71_kp_resources), - .resource = palmz71_kp_resources, -}; - -static struct mtd_partition palmz71_rom_partitions[] = { - /* PalmOS "Small ROM", contains the bootloader and the debugger */ - { - .name = "smallrom", - .offset = 0, - .size = 0xa000, - .mask_flags = MTD_WRITEABLE, - }, - /* PalmOS "Big ROM", a filesystem with all the OS code and data */ - { - .name = "bigrom", - .offset = SZ_128K, - /* - * 0x5f0000 bytes big in the multi-language ("EFIGS") version, - * 0x7b0000 bytes in the English-only ("enUS") version. - */ - .size = 0x7b0000, - .mask_flags = MTD_WRITEABLE, - }, -}; - -static struct physmap_flash_data palmz71_rom_data = { - .width = 2, - .set_vpp = omap1_set_vpp, - .parts = palmz71_rom_partitions, - .nr_parts = ARRAY_SIZE(palmz71_rom_partitions), -}; - -static struct resource palmz71_rom_resource = { - .start = OMAP_CS0_PHYS, - .end = OMAP_CS0_PHYS + SZ_8M - 1, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device palmz71_rom_device = { - .name = "physmap-flash", - .id = -1, - .dev = { - .platform_data = &palmz71_rom_data, - }, - .num_resources = 1, - .resource = &palmz71_rom_resource, -}; - -static struct platform_device palmz71_lcd_device = { - .name = "lcd_palmz71", - .id = -1, -}; - -static struct platform_device palmz71_spi_device = { - .name = "spi_palmz71", - .id = -1, -}; - -static struct omap_backlight_config palmz71_backlight_config = { - .default_intensity = 0xa0, -}; - -static struct platform_device palmz71_backlight_device = { - .name = "omap-bl", - .id = -1, - .dev = { - .platform_data = &palmz71_backlight_config, - }, -}; - -static struct platform_device *devices[] __initdata = { - &palmz71_rom_device, - &palmz71_kp_device, - &palmz71_lcd_device, - &palmz71_spi_device, - &palmz71_backlight_device, -}; - -static int -palmz71_get_pendown_state(void) -{ - return !gpio_get_value(PALMZ71_PENIRQ_GPIO); -} - -static const struct ads7846_platform_data palmz71_ts_info = { - .model = 7846, - .vref_delay_usecs = 100, /* internal, no capacitor */ - .x_plate_ohms = 419, - .y_plate_ohms = 486, - .get_pendown_state = palmz71_get_pendown_state, -}; - -static struct spi_board_info __initdata palmz71_boardinfo[] = { { - /* MicroWire (bus 2) CS0 has an ads7846e */ - .modalias = "ads7846", - .platform_data = &palmz71_ts_info, - .max_speed_hz = 120000 /* max sample rate at 3V */ - * 26 /* command + data + overhead */, - .bus_num = 2, - .chip_select = 0, -} }; - -static struct omap_usb_config palmz71_usb_config __initdata = { - .register_dev = 1, /* Mini-B only receptacle */ - .hmc_mode = 0, - .pins[0] = 2, -}; - -static const struct omap_lcd_config palmz71_lcd_config __initconst = { - .ctrl_name = "internal", -}; - -static irqreturn_t -palmz71_powercable(int irq, void *dev_id) -{ - if (gpio_get_value(PALMZ71_USBDETECT_GPIO)) { - printk(KERN_INFO "PM: Power cable connected\n"); - irq_set_irq_type(gpio_to_irq(PALMZ71_USBDETECT_GPIO), - IRQ_TYPE_EDGE_FALLING); - } else { - printk(KERN_INFO "PM: Power cable disconnected\n"); - irq_set_irq_type(gpio_to_irq(PALMZ71_USBDETECT_GPIO), - IRQ_TYPE_EDGE_RISING); - } - return IRQ_HANDLED; -} - -static void __init -omap_mpu_wdt_mode(int mode) -{ - if (mode) - omap_writew(0x8000, OMAP_WDT_TIMER_MODE); - else { - omap_writew(0x00f5, OMAP_WDT_TIMER_MODE); - omap_writew(0x00a0, OMAP_WDT_TIMER_MODE); - } -} - -static void __init -palmz71_gpio_setup(int early) -{ - if (early) { - /* Only set GPIO1 so we have a working serial */ - gpio_direction_output(1, 1); - } else { - /* Set MMC/SD host WP pin as input */ - if (gpio_request(PALMZ71_MMC_WP_GPIO, "MMC WP") < 0) { - printk(KERN_ERR "Could not reserve WP GPIO!\n"); - return; - } - gpio_direction_input(PALMZ71_MMC_WP_GPIO); - - /* Monitor the Power-cable-connected signal */ - if (gpio_request(PALMZ71_USBDETECT_GPIO, "USB detect") < 0) { - printk(KERN_ERR - "Could not reserve cable signal GPIO!\n"); - return; - } - gpio_direction_input(PALMZ71_USBDETECT_GPIO); - if (request_irq(gpio_to_irq(PALMZ71_USBDETECT_GPIO), - palmz71_powercable, 0, "palmz71-cable", NULL)) - printk(KERN_ERR - "IRQ request for power cable failed!\n"); - palmz71_powercable(gpio_to_irq(PALMZ71_USBDETECT_GPIO), NULL); - } -} - -static void __init -omap_palmz71_init(void) -{ - /* mux pins for uarts */ - omap_cfg_reg(UART1_TX); - omap_cfg_reg(UART1_RTS); - omap_cfg_reg(UART2_TX); - omap_cfg_reg(UART2_RTS); - omap_cfg_reg(UART3_TX); - omap_cfg_reg(UART3_RX); - - palmz71_gpio_setup(1); - omap_mpu_wdt_mode(0); - - platform_add_devices(devices, ARRAY_SIZE(devices)); - - palmz71_boardinfo[0].irq = gpio_to_irq(PALMZ71_PENIRQ_GPIO); - spi_register_board_info(palmz71_boardinfo, - ARRAY_SIZE(palmz71_boardinfo)); - omap1_usb_init(&palmz71_usb_config); - omap_serial_init(); - omap_register_i2c_bus(1, 100, NULL, 0); - palmz71_gpio_setup(0); - - omapfb_set_lcd_config(&palmz71_lcd_config); -} - -MACHINE_START(OMAP_PALMZ71, "OMAP310 based Palm Zire71") - .atag_offset = 0x100, - .map_io = omap15xx_map_io, - .init_early = omap1_init_early, - .init_irq = omap1_init_irq, - .handle_irq = omap1_handle_irq, - .init_machine = omap_palmz71_init, - .init_late = omap1_init_late, - .init_time = omap1_timer_init, - .restart = omap1_restart, -MACHINE_END diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c deleted file mode 100644 index b041e6f6e9cf..000000000000 --- a/arch/arm/mach-omap1/board-perseus2.c +++ /dev/null @@ -1,333 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/mach-omap1/board-perseus2.c - * - * Modified from board-generic.c - * - * Original OMAP730 support by Jean Pihet - * Updated for 2.6 by Kevin Hilman - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include "tc.h" -#include "mux.h" -#include "flash.h" -#include "hardware.h" -#include "iomap.h" -#include "common.h" -#include "fpga.h" - -static const unsigned int p2_keymap[] = { - KEY(0, 0, KEY_UP), - KEY(1, 0, KEY_RIGHT), - KEY(2, 0, KEY_LEFT), - KEY(3, 0, KEY_DOWN), - KEY(4, 0, KEY_ENTER), - KEY(0, 1, KEY_F10), - KEY(1, 1, KEY_SEND), - KEY(2, 1, KEY_END), - KEY(3, 1, KEY_VOLUMEDOWN), - KEY(4, 1, KEY_VOLUMEUP), - KEY(5, 1, KEY_RECORD), - KEY(0, 2, KEY_F9), - KEY(1, 2, KEY_3), - KEY(2, 2, KEY_6), - KEY(3, 2, KEY_9), - KEY(4, 2, KEY_KPDOT), - KEY(0, 3, KEY_BACK), - KEY(1, 3, KEY_2), - KEY(2, 3, KEY_5), - KEY(3, 3, KEY_8), - KEY(4, 3, KEY_0), - KEY(5, 3, KEY_KPSLASH), - KEY(0, 4, KEY_HOME), - KEY(1, 4, KEY_1), - KEY(2, 4, KEY_4), - KEY(3, 4, KEY_7), - KEY(4, 4, KEY_KPASTERISK), - KEY(5, 4, KEY_POWER), -}; - -static struct smc91x_platdata smc91x_info = { - .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, - .leda = RPC_LED_100_10, - .ledb = RPC_LED_TX_RX, -}; - -static struct resource smc91x_resources[] = { - [0] = { - .start = H2P2_DBG_FPGA_ETHR_START, /* Physical */ - .end = H2P2_DBG_FPGA_ETHR_START + 0xf, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = INT_7XX_MPU_EXT_NIRQ, - .end = 0, - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, - }, -}; - -static struct mtd_partition nor_partitions[] = { - /* bootloader (U-Boot, etc) in first sector */ - { - .name = "bootloader", - .offset = 0, - .size = SZ_128K, - .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, - /* bootloader params in the next sector */ - { - .name = "params", - .offset = MTDPART_OFS_APPEND, - .size = SZ_128K, - .mask_flags = 0, - }, - /* kernel */ - { - .name = "kernel", - .offset = MTDPART_OFS_APPEND, - .size = SZ_2M, - .mask_flags = 0 - }, - /* rest of flash is a file system */ - { - .name = "rootfs", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - .mask_flags = 0 - }, -}; - -static struct physmap_flash_data nor_data = { - .width = 2, - .set_vpp = omap1_set_vpp, - .parts = nor_partitions, - .nr_parts = ARRAY_SIZE(nor_partitions), -}; - -static struct resource nor_resource = { - .start = OMAP_CS0_PHYS, - .end = OMAP_CS0_PHYS + SZ_32M - 1, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device nor_device = { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &nor_data, - }, - .num_resources = 1, - .resource = &nor_resource, -}; - -#define P2_NAND_RB_GPIO_PIN 62 - -static int nand_dev_ready(struct nand_chip *chip) -{ - return gpio_get_value(P2_NAND_RB_GPIO_PIN); -} - -static struct platform_nand_data nand_data = { - .chip = { - .nr_chips = 1, - .chip_offset = 0, - .options = NAND_SAMSUNG_LP_OPTIONS, - }, - .ctrl = { - .cmd_ctrl = omap1_nand_cmd_ctl, - .dev_ready = nand_dev_ready, - }, -}; - -static struct resource nand_resource = { - .start = OMAP_CS3_PHYS, - .end = OMAP_CS3_PHYS + SZ_4K - 1, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device nand_device = { - .name = "gen_nand", - .id = 0, - .dev = { - .platform_data = &nand_data, - }, - .num_resources = 1, - .resource = &nand_resource, -}; - -static struct platform_device smc91x_device = { - .name = "smc91x", - .id = 0, - .dev = { - .platform_data = &smc91x_info, - }, - .num_resources = ARRAY_SIZE(smc91x_resources), - .resource = smc91x_resources, -}; - -static struct resource kp_resources[] = { - [0] = { - .start = INT_7XX_MPUIO_KEYPAD, - .end = INT_7XX_MPUIO_KEYPAD, - .flags = IORESOURCE_IRQ, - }, -}; - -static const struct matrix_keymap_data p2_keymap_data = { - .keymap = p2_keymap, - .keymap_size = ARRAY_SIZE(p2_keymap), -}; - -static struct omap_kp_platform_data kp_data = { - .rows = 8, - .cols = 8, - .keymap_data = &p2_keymap_data, - .delay = 4, - .dbounce = true, -}; - -static struct platform_device kp_device = { - .name = "omap-keypad", - .id = -1, - .dev = { - .platform_data = &kp_data, - }, - .num_resources = ARRAY_SIZE(kp_resources), - .resource = kp_resources, -}; - -static struct platform_device *devices[] __initdata = { - &nor_device, - &nand_device, - &smc91x_device, - &kp_device, -}; - -static const struct omap_lcd_config perseus2_lcd_config __initconst = { - .ctrl_name = "internal", -}; - -static void __init perseus2_init_smc91x(void) -{ - __raw_writeb(1, H2P2_DBG_FPGA_LAN_RESET); - mdelay(50); - __raw_writeb(__raw_readb(H2P2_DBG_FPGA_LAN_RESET) & ~1, - H2P2_DBG_FPGA_LAN_RESET); - mdelay(50); -} - -static void __init omap_perseus2_init(void) -{ - /* Early, board-dependent init */ - - /* - * Hold GSM Reset until needed - */ - omap_writew(omap_readw(OMAP7XX_DSP_M_CTL) & ~1, OMAP7XX_DSP_M_CTL); - - /* - * UARTs -> done automagically by 8250 driver - */ - - /* - * CSx timings, GPIO Mux ... setup - */ - - /* Flash: CS0 timings setup */ - omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_0); - omap_writel(0x00000088, OMAP7XX_FLASH_ACFG_0); - - /* - * Ethernet support through the debug board - * CS1 timings setup - */ - omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_1); - omap_writel(0x00000000, OMAP7XX_FLASH_ACFG_1); - - /* - * Configure MPU_EXT_NIRQ IO in IO_CONF9 register, - * It is used as the Ethernet controller interrupt - */ - omap_writel(omap_readl(OMAP7XX_IO_CONF_9) & 0x1FFFFFFF, - OMAP7XX_IO_CONF_9); - - perseus2_init_smc91x(); - - BUG_ON(gpio_request(P2_NAND_RB_GPIO_PIN, "NAND ready") < 0); - gpio_direction_input(P2_NAND_RB_GPIO_PIN); - - omap_cfg_reg(L3_1610_FLASH_CS2B_OE); - omap_cfg_reg(M8_1610_FLASH_CS2B_WE); - - /* Mux pins for keypad */ - omap_cfg_reg(E2_7XX_KBR0); - omap_cfg_reg(J7_7XX_KBR1); - omap_cfg_reg(E1_7XX_KBR2); - omap_cfg_reg(F3_7XX_KBR3); - omap_cfg_reg(D2_7XX_KBR4); - omap_cfg_reg(C2_7XX_KBC0); - omap_cfg_reg(D3_7XX_KBC1); - omap_cfg_reg(E4_7XX_KBC2); - omap_cfg_reg(F4_7XX_KBC3); - omap_cfg_reg(E3_7XX_KBC4); - - if (IS_ENABLED(CONFIG_SPI_OMAP_UWIRE)) { - /* configure pins: MPU_UW_nSCS1, MPU_UW_SDO, MPU_UW_SCLK */ - int val = omap_readl(OMAP7XX_IO_CONF_9) & ~0x00EEE000; - omap_writel(val | 0x00AAA000, OMAP7XX_IO_CONF_9); - } - - platform_add_devices(devices, ARRAY_SIZE(devices)); - - omap_serial_init(); - omap_register_i2c_bus(1, 100, NULL, 0); - - omapfb_set_lcd_config(&perseus2_lcd_config); -} - -/* Only FPGA needs to be mapped here. All others are done with ioremap */ -static struct map_desc omap_perseus2_io_desc[] __initdata = { - { - .virtual = H2P2_DBG_FPGA_BASE, - .pfn = __phys_to_pfn(H2P2_DBG_FPGA_START), - .length = H2P2_DBG_FPGA_SIZE, - .type = MT_DEVICE - } -}; - -static void __init omap_perseus2_map_io(void) -{ - omap7xx_map_io(); - iotable_init(omap_perseus2_io_desc, - ARRAY_SIZE(omap_perseus2_io_desc)); -} - -MACHINE_START(OMAP_PERSEUS2, "OMAP730 Perseus2") - /* Maintainer: Kevin Hilman */ - .atag_offset = 0x100, - .map_io = omap_perseus2_map_io, - .init_early = omap1_init_early, - .init_irq = omap1_init_irq, - .handle_irq = omap1_handle_irq, - .init_machine = omap_perseus2_init, - .init_late = omap1_init_late, - .init_time = omap1_timer_init, - .restart = omap1_restart, -MACHINE_END diff --git a/arch/arm/mach-omap1/fpga.c b/arch/arm/mach-omap1/fpga.c deleted file mode 100644 index 4c71a195969f..000000000000 --- a/arch/arm/mach-omap1/fpga.c +++ /dev/null @@ -1,186 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/mach-omap1/fpga.c - * - * Interrupt handler for OMAP-1510 Innovator FPGA - * - * Copyright (C) 2001 RidgeRun, Inc. - * Author: Greg Lonnon - * - * Copyright (C) 2002 MontaVista Software, Inc. - * - * Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6 - * Copyright (C) 2004 Nokia Corporation by Tony Lindrgen - */ - -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include "hardware.h" -#include "iomap.h" -#include "common.h" -#include "fpga.h" - -static void fpga_mask_irq(struct irq_data *d) -{ - unsigned int irq = d->irq - OMAP_FPGA_IRQ_BASE; - - if (irq < 8) - __raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_LO) - & ~(1 << irq)), OMAP1510_FPGA_IMR_LO); - else if (irq < 16) - __raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_HI) - & ~(1 << (irq - 8))), OMAP1510_FPGA_IMR_HI); - else - __raw_writeb((__raw_readb(INNOVATOR_FPGA_IMR2) - & ~(1 << (irq - 16))), INNOVATOR_FPGA_IMR2); -} - - -static inline u32 get_fpga_unmasked_irqs(void) -{ - return - ((__raw_readb(OMAP1510_FPGA_ISR_LO) & - __raw_readb(OMAP1510_FPGA_IMR_LO))) | - ((__raw_readb(OMAP1510_FPGA_ISR_HI) & - __raw_readb(OMAP1510_FPGA_IMR_HI)) << 8) | - ((__raw_readb(INNOVATOR_FPGA_ISR2) & - __raw_readb(INNOVATOR_FPGA_IMR2)) << 16); -} - - -static void fpga_ack_irq(struct irq_data *d) -{ - /* Don't need to explicitly ACK FPGA interrupts */ -} - -static void fpga_unmask_irq(struct irq_data *d) -{ - unsigned int irq = d->irq - OMAP_FPGA_IRQ_BASE; - - if (irq < 8) - __raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_LO) | (1 << irq)), - OMAP1510_FPGA_IMR_LO); - else if (irq < 16) - __raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_HI) - | (1 << (irq - 8))), OMAP1510_FPGA_IMR_HI); - else - __raw_writeb((__raw_readb(INNOVATOR_FPGA_IMR2) - | (1 << (irq - 16))), INNOVATOR_FPGA_IMR2); -} - -static void fpga_mask_ack_irq(struct irq_data *d) -{ - fpga_mask_irq(d); - fpga_ack_irq(d); -} - -static void innovator_fpga_IRQ_demux(struct irq_desc *desc) -{ - u32 stat; - int fpga_irq; - - stat = get_fpga_unmasked_irqs(); - - if (!stat) - return; - - for (fpga_irq = OMAP_FPGA_IRQ_BASE; - (fpga_irq < OMAP_FPGA_IRQ_END) && stat; - fpga_irq++, stat >>= 1) { - if (stat & 1) { - generic_handle_irq(fpga_irq); - } - } -} - -static struct irq_chip omap_fpga_irq_ack = { - .name = "FPGA-ack", - .irq_ack = fpga_mask_ack_irq, - .irq_mask = fpga_mask_irq, - .irq_unmask = fpga_unmask_irq, -}; - - -static struct irq_chip omap_fpga_irq = { - .name = "FPGA", - .irq_ack = fpga_ack_irq, - .irq_mask = fpga_mask_irq, - .irq_unmask = fpga_unmask_irq, -}; - -/* - * All of the FPGA interrupt request inputs except for the touchscreen are - * edge-sensitive; the touchscreen is level-sensitive. The edge-sensitive - * interrupts are acknowledged as a side-effect of reading the interrupt - * status register from the FPGA. The edge-sensitive interrupt inputs - * cause a problem with level interrupt requests, such as Ethernet. The - * problem occurs when a level interrupt request is asserted while its - * interrupt input is masked in the FPGA, which results in a missed - * interrupt. - * - * In an attempt to workaround the problem with missed interrupts, the - * mask_ack routine for all of the FPGA interrupts has been changed from - * fpga_mask_ack_irq() to fpga_ack_irq() so that the specific FPGA interrupt - * being serviced is left unmasked. We can do this because the FPGA cascade - * interrupt is run with all interrupts masked. - * - * Limited testing indicates that this workaround appears to be effective - * for the smc9194 Ethernet driver used on the Innovator. It should work - * on other FPGA interrupts as well, but any drivers that explicitly mask - * interrupts at the interrupt controller via disable_irq/enable_irq - * could pose a problem. - */ -void omap1510_fpga_init_irq(void) -{ - int i, res; - - __raw_writeb(0, OMAP1510_FPGA_IMR_LO); - __raw_writeb(0, OMAP1510_FPGA_IMR_HI); - __raw_writeb(0, INNOVATOR_FPGA_IMR2); - - for (i = OMAP_FPGA_IRQ_BASE; i < OMAP_FPGA_IRQ_END; i++) { - - if (i == OMAP1510_INT_FPGA_TS) { - /* - * The touchscreen interrupt is level-sensitive, so - * we'll use the regular mask_ack routine for it. - */ - irq_set_chip(i, &omap_fpga_irq_ack); - } - else { - /* - * All FPGA interrupts except the touchscreen are - * edge-sensitive, so we won't mask them. - */ - irq_set_chip(i, &omap_fpga_irq); - } - - irq_set_handler(i, handle_edge_irq); - irq_clear_status_flags(i, IRQ_NOREQUEST); - } - - /* - * The FPGA interrupt line is connected to GPIO13. Claim this pin for - * the ARM. - * - * NOTE: For general GPIO/MPUIO access and interrupts, please see - * gpio.[ch] - */ - res = gpio_request(13, "FPGA irq"); - if (res) { - pr_err("%s failed to get gpio\n", __func__); - return; - } - gpio_direction_input(13); - irq_set_irq_type(gpio_to_irq(13), IRQ_TYPE_EDGE_RISING); - irq_set_chained_handler(OMAP1510_INT_FPGA, innovator_fpga_IRQ_demux); -} diff --git a/arch/arm/mach-omap1/fpga.h b/arch/arm/mach-omap1/fpga.h deleted file mode 100644 index 7e7450edacc1..000000000000 --- a/arch/arm/mach-omap1/fpga.h +++ /dev/null @@ -1,49 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Interrupt handler for OMAP-1510 FPGA - * - * Copyright (C) 2001 RidgeRun, Inc. - * Author: Greg Lonnon - * - * Copyright (C) 2002 MontaVista Software, Inc. - * - * Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6 - * Copyright (C) 2004 Nokia Corporation by Tony Lindrgen - */ - -#ifndef __ASM_ARCH_OMAP_FPGA_H -#define __ASM_ARCH_OMAP_FPGA_H - -/* - * --------------------------------------------------------------------------- - * H2/P2 Debug board FPGA - * --------------------------------------------------------------------------- - */ -/* maps in the FPGA registers and the ETHR registers */ -#define H2P2_DBG_FPGA_BASE 0xE8000000 /* VA */ -#define H2P2_DBG_FPGA_SIZE SZ_4K /* SIZE */ -#define H2P2_DBG_FPGA_START 0x04000000 /* PA */ - -#define H2P2_DBG_FPGA_ETHR_START (H2P2_DBG_FPGA_START + 0x300) -#define H2P2_DBG_FPGA_FPGA_REV IOMEM(H2P2_DBG_FPGA_BASE + 0x10) /* FPGA Revision */ -#define H2P2_DBG_FPGA_BOARD_REV IOMEM(H2P2_DBG_FPGA_BASE + 0x12) /* Board Revision */ -#define H2P2_DBG_FPGA_GPIO IOMEM(H2P2_DBG_FPGA_BASE + 0x14) /* GPIO outputs */ -#define H2P2_DBG_FPGA_LEDS IOMEM(H2P2_DBG_FPGA_BASE + 0x16) /* LEDs outputs */ -#define H2P2_DBG_FPGA_MISC_INPUTS IOMEM(H2P2_DBG_FPGA_BASE + 0x18) /* Misc inputs */ -#define H2P2_DBG_FPGA_LAN_STATUS IOMEM(H2P2_DBG_FPGA_BASE + 0x1A) /* LAN Status line */ -#define H2P2_DBG_FPGA_LAN_RESET IOMEM(H2P2_DBG_FPGA_BASE + 0x1C) /* LAN Reset line */ - -/* LEDs definition on debug board (16 LEDs, all physically green) */ -#define H2P2_DBG_FPGA_LED_GREEN (1 << 15) -#define H2P2_DBG_FPGA_LED_AMBER (1 << 14) -#define H2P2_DBG_FPGA_LED_RED (1 << 13) -#define H2P2_DBG_FPGA_LED_BLUE (1 << 12) -/* cpu0 load-meter LEDs */ -#define H2P2_DBG_FPGA_LOAD_METER (1 << 0) // A bit of fun on our board ... -#define H2P2_DBG_FPGA_LOAD_METER_SIZE 11 -#define H2P2_DBG_FPGA_LOAD_METER_MASK ((1 << H2P2_DBG_FPGA_LOAD_METER_SIZE) - 1) - -#define H2P2_DBG_FPGA_P2_LED_TIMER (1 << 0) -#define H2P2_DBG_FPGA_P2_LED_IDLE (1 << 1) - -#endif diff --git a/arch/arm/mach-omap1/gpio7xx.c b/arch/arm/mach-omap1/gpio7xx.c deleted file mode 100644 index c372b357eab4..000000000000 --- a/arch/arm/mach-omap1/gpio7xx.c +++ /dev/null @@ -1,272 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * OMAP7xx specific gpio init - * - * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/ - * - * Author: - * Charulatha V - */ - -#include -#include - -#include "irqs.h" -#include "soc.h" - -#define OMAP7XX_GPIO1_BASE 0xfffbc000 -#define OMAP7XX_GPIO2_BASE 0xfffbc800 -#define OMAP7XX_GPIO3_BASE 0xfffbd000 -#define OMAP7XX_GPIO4_BASE 0xfffbd800 -#define OMAP7XX_GPIO5_BASE 0xfffbe000 -#define OMAP7XX_GPIO6_BASE 0xfffbe800 -#define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE - -/* mpu gpio */ -static struct resource omap7xx_mpu_gpio_resources[] = { - { - .start = OMAP1_MPUIO_VBASE, - .end = OMAP1_MPUIO_VBASE + SZ_2K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = INT_7XX_MPUIO, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct omap_gpio_reg_offs omap7xx_mpuio_regs = { - .revision = USHRT_MAX, - .direction = OMAP_MPUIO_IO_CNTL / 2, - .datain = OMAP_MPUIO_INPUT_LATCH / 2, - .dataout = OMAP_MPUIO_OUTPUT / 2, - .irqstatus = OMAP_MPUIO_GPIO_INT / 2, - .irqenable = OMAP_MPUIO_GPIO_MASKIT / 2, - .irqenable_inv = true, - .irqctrl = OMAP_MPUIO_GPIO_INT_EDGE >> 1, -}; - -static struct omap_gpio_platform_data omap7xx_mpu_gpio_config = { - .is_mpuio = true, - .bank_width = 16, - .bank_stride = 2, - .regs = &omap7xx_mpuio_regs, -}; - -static struct platform_device omap7xx_mpu_gpio = { - .name = "omap_gpio", - .id = 0, - .dev = { - .platform_data = &omap7xx_mpu_gpio_config, - }, - .num_resources = ARRAY_SIZE(omap7xx_mpu_gpio_resources), - .resource = omap7xx_mpu_gpio_resources, -}; - -/* gpio1 */ -static struct resource omap7xx_gpio1_resources[] = { - { - .start = OMAP7XX_GPIO1_BASE, - .end = OMAP7XX_GPIO1_BASE + SZ_2K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = INT_7XX_GPIO_BANK1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct omap_gpio_reg_offs omap7xx_gpio_regs = { - .revision = USHRT_MAX, - .direction = OMAP7XX_GPIO_DIR_CONTROL, - .datain = OMAP7XX_GPIO_DATA_INPUT, - .dataout = OMAP7XX_GPIO_DATA_OUTPUT, - .irqstatus = OMAP7XX_GPIO_INT_STATUS, - .irqenable = OMAP7XX_GPIO_INT_MASK, - .irqenable_inv = true, - .irqctrl = OMAP7XX_GPIO_INT_CONTROL, -}; - -static struct omap_gpio_platform_data omap7xx_gpio1_config = { - .bank_width = 32, - .regs = &omap7xx_gpio_regs, -}; - -static struct platform_device omap7xx_gpio1 = { - .name = "omap_gpio", - .id = 1, - .dev = { - .platform_data = &omap7xx_gpio1_config, - }, - .num_resources = ARRAY_SIZE(omap7xx_gpio1_resources), - .resource = omap7xx_gpio1_resources, -}; - -/* gpio2 */ -static struct resource omap7xx_gpio2_resources[] = { - { - .start = OMAP7XX_GPIO2_BASE, - .end = OMAP7XX_GPIO2_BASE + SZ_2K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = INT_7XX_GPIO_BANK2, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct omap_gpio_platform_data omap7xx_gpio2_config = { - .bank_width = 32, - .regs = &omap7xx_gpio_regs, -}; - -static struct platform_device omap7xx_gpio2 = { - .name = "omap_gpio", - .id = 2, - .dev = { - .platform_data = &omap7xx_gpio2_config, - }, - .num_resources = ARRAY_SIZE(omap7xx_gpio2_resources), - .resource = omap7xx_gpio2_resources, -}; - -/* gpio3 */ -static struct resource omap7xx_gpio3_resources[] = { - { - .start = OMAP7XX_GPIO3_BASE, - .end = OMAP7XX_GPIO3_BASE + SZ_2K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = INT_7XX_GPIO_BANK3, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct omap_gpio_platform_data omap7xx_gpio3_config = { - .bank_width = 32, - .regs = &omap7xx_gpio_regs, -}; - -static struct platform_device omap7xx_gpio3 = { - .name = "omap_gpio", - .id = 3, - .dev = { - .platform_data = &omap7xx_gpio3_config, - }, - .num_resources = ARRAY_SIZE(omap7xx_gpio3_resources), - .resource = omap7xx_gpio3_resources, -}; - -/* gpio4 */ -static struct resource omap7xx_gpio4_resources[] = { - { - .start = OMAP7XX_GPIO4_BASE, - .end = OMAP7XX_GPIO4_BASE + SZ_2K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = INT_7XX_GPIO_BANK4, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct omap_gpio_platform_data omap7xx_gpio4_config = { - .bank_width = 32, - .regs = &omap7xx_gpio_regs, -}; - -static struct platform_device omap7xx_gpio4 = { - .name = "omap_gpio", - .id = 4, - .dev = { - .platform_data = &omap7xx_gpio4_config, - }, - .num_resources = ARRAY_SIZE(omap7xx_gpio4_resources), - .resource = omap7xx_gpio4_resources, -}; - -/* gpio5 */ -static struct resource omap7xx_gpio5_resources[] = { - { - .start = OMAP7XX_GPIO5_BASE, - .end = OMAP7XX_GPIO5_BASE + SZ_2K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = INT_7XX_GPIO_BANK5, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct omap_gpio_platform_data omap7xx_gpio5_config = { - .bank_width = 32, - .regs = &omap7xx_gpio_regs, -}; - -static struct platform_device omap7xx_gpio5 = { - .name = "omap_gpio", - .id = 5, - .dev = { - .platform_data = &omap7xx_gpio5_config, - }, - .num_resources = ARRAY_SIZE(omap7xx_gpio5_resources), - .resource = omap7xx_gpio5_resources, -}; - -/* gpio6 */ -static struct resource omap7xx_gpio6_resources[] = { - { - .start = OMAP7XX_GPIO6_BASE, - .end = OMAP7XX_GPIO6_BASE + SZ_2K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = INT_7XX_GPIO_BANK6, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct omap_gpio_platform_data omap7xx_gpio6_config = { - .bank_width = 32, - .regs = &omap7xx_gpio_regs, -}; - -static struct platform_device omap7xx_gpio6 = { - .name = "omap_gpio", - .id = 6, - .dev = { - .platform_data = &omap7xx_gpio6_config, - }, - .num_resources = ARRAY_SIZE(omap7xx_gpio6_resources), - .resource = omap7xx_gpio6_resources, -}; - -static struct platform_device *omap7xx_gpio_dev[] __initdata = { - &omap7xx_mpu_gpio, - &omap7xx_gpio1, - &omap7xx_gpio2, - &omap7xx_gpio3, - &omap7xx_gpio4, - &omap7xx_gpio5, - &omap7xx_gpio6, -}; - -/* - * omap7xx_gpio_init needs to be done before - * machine_init functions access gpio APIs. - * Hence omap7xx_gpio_init is a postcore_initcall. - */ -static int __init omap7xx_gpio_init(void) -{ - int i; - - if (!cpu_is_omap7xx()) - return -EINVAL; - - for (i = 0; i < ARRAY_SIZE(omap7xx_gpio_dev); i++) - platform_device_register(omap7xx_gpio_dev[i]); - - return 0; -} -postcore_initcall(omap7xx_gpio_init); diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index e488e1b8e803..f427c8ea5c7b 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -873,7 +873,7 @@ config I2C_OCORES config I2C_OMAP tristate "OMAP I2C adapter" depends on ARCH_OMAP || ARCH_K3 || COMPILE_TEST - default y if MACH_OMAP_H3 || MACH_OMAP_OSK + default MACH_OMAP_OSK help If you say yes to this option, support will be included for the I2C interface on the Texas Instruments OMAP1/2 family of processors. diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 8b93856de432..c87aab27455f 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -1524,7 +1524,7 @@ config TPS6105X config TPS65010 tristate "TI TPS6501x Power Management chips" depends on I2C && GPIOLIB - default y if MACH_OMAP_H2 || MACH_OMAP_H3 || MACH_OMAP_OSK + default MACH_OMAP_OSK help If you say yes here you get support for the TPS6501x series of Power Management chips. These include voltage regulators, diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index 1c5b1c48a230..1dc88347525a 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -480,7 +480,7 @@ config MMC_SDHCI_ST config MMC_OMAP tristate "TI OMAP Multimedia Card Interface support" depends on ARCH_OMAP - depends on TPS65010 || !MACH_OMAP_H2 + depends on TPS65010 help This selects the TI OMAP Multimedia card Interface. If you have an OMAP board with a Multimedia Card slot, diff --git a/drivers/usb/gadget/udc/Kconfig b/drivers/usb/gadget/udc/Kconfig index 5756acb07b8d..82fe0c72b496 100644 --- a/drivers/usb/gadget/udc/Kconfig +++ b/drivers/usb/gadget/udc/Kconfig @@ -129,7 +129,7 @@ config USB_GR_UDC config USB_OMAP tristate "OMAP USB Device Controller" depends on ARCH_OMAP1 - depends on ISP1301_OMAP || !(MACH_OMAP_H2 || MACH_OMAP_H3) + depends on ISP1301_OMAP help Many Texas Instruments OMAP processors have flexible full speed USB device controllers, with support for up to 30 diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 75b8a3eeb23a..fb7b603dddf8 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -420,7 +420,7 @@ if USB_OHCI_HCD config USB_OHCI_HCD_OMAP1 tristate "OHCI support for OMAP1/2 chips" depends on ARCH_OMAP1 - depends on ISP1301_OMAP || !(MACH_OMAP_H2 || MACH_OMAP_H3) + depends on ISP1301_OMAP default y help Enables support for the OHCI controller on OMAP1/2 chips. diff --git a/include/linux/platform_data/leds-omap.h b/include/linux/platform_data/leds-omap.h deleted file mode 100644 index dd1a3ec86fe4..000000000000 --- a/include/linux/platform_data/leds-omap.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2006 Samsung Electronics - * Kyungmin Park - */ -#ifndef ASMARM_ARCH_LED_H -#define ASMARM_ARCH_LED_H - -struct omap_led_config { - struct led_classdev cdev; - s16 gpio; -}; - -struct omap_led_platform_data { - s16 nr_leds; - struct omap_led_config *leds; -}; - -#endif From patchwork Wed Oct 19 15:03:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnd Bergmann X-Patchwork-Id: 5696 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp394712wrs; Wed, 19 Oct 2022 08:41:42 -0700 (PDT) X-Google-Smtp-Source: AMsMyM7gzlC0ELwszLLyoht/mGpqxTJvW66jQc1xVuv1NMtJx2oUa1F0jZJngz86eFmYElrvBbIC X-Received: by 2002:a17:90b:380d:b0:20d:8a42:1d74 with SMTP id mq13-20020a17090b380d00b0020d8a421d74mr10673479pjb.223.1666194101645; Wed, 19 Oct 2022 08:41:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666194101; cv=none; d=google.com; s=arc-20160816; b=xh4ZhjnKIMiUpfCQMVVDm9rbUXgj7LLS7V2RY7msmpo+IjMKrKMWN8fxydl5npM1nv 4NfuiV0EGY1PDWrNir/YIMmBzvHWjuBWQyPtVPWqR15fvFG/KQo0/bCDBeL2RLLAT5hs 1/cD/8ZHA00OS9KkPGFzKcrbbi/0/aztS5j2+sTrGm9G7qSwnTuW1QxNQ3Vpd/hs8C2m J0gA9ve2w+vPozOomibMvfKxkXHb+6xijIqDSJkt2jS/gyLShTs/mrV+hFwokQyStwF1 hxw9ACo35AICp8KX952kLoqXwYYK6UZFOB8iLxWdRiVsRCSb5pu/zLeg1kHDBqhCp4ka qV/g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=2jpbojYdrNyem4EYTZH1LPx62HMs96Y5eEjdHP/fLew=; b=zphyem7tI7VvFIWfcGYB2LKhsTr1SzebNXgxxJXK4cySlQXqPXTouwk0ngBsX8F7+z 835zwhmoqEjoe4vx90b7NQ/B5SXKju6co+FCJJGRXiNCgjS6PFvCvYtOByibK3025ro2 itFOoy+ATLyvFgZCipkQcYW9WXjnLrCGh0IPwiCl+zEA6gfsG3G37q86YP2Cl3kWj84E dfBDhS1wI9VF71Dwh98LV851mhDAvh4O520Lskx4KlzdUrEguGFxga9iO6wtciXsf3Un NWbBYklxiSwHOm9xl35em+VeLfFfX9zTAUB/8+MN++CtAaDb06WGmpaxjRfweM2Yc1G8 lFVQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=SvNmNUCG; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id oo16-20020a17090b1c9000b0020db7d975ecsi198712pjb.176.2022.10.19.08.41.26; Wed, 19 Oct 2022 08:41:41 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=SvNmNUCG; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231535AbiJSP2s (ORCPT + 99 others); Wed, 19 Oct 2022 11:28:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58728 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231783AbiJSP1i (ORCPT ); Wed, 19 Oct 2022 11:27:38 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A68DC1D6385; Wed, 19 Oct 2022 08:20:34 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 16C2A6183B; Wed, 19 Oct 2022 15:19:37 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 89FFBC433D6; Wed, 19 Oct 2022 15:19:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1666192776; bh=kXSlIp1TRH3h6jAEF0j9o6n7BaKsFbpIUtKAlEcb1So=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SvNmNUCGiRPhVogaJFJ4r8oO5FhCUIfiygaAe/pkhPkwPQOW70xtyWntGpBCFUYSE sFP9YGrB9VEatMDlF7G9rZ40W7xKNedXYWB/+4D4TB6ITrA5q2B/GcgqSpUiy64prh zdfMXV2Yy1b31YE1sat/y0uKNC0j6jJ6awvs4ky8G5oQwcqVZ1u6RGm9kBkX6dpdqk tKqWqMJys5cwegg1NEZz0K6ueAiacfkRnJpeIPEIX/lrqUxu3Z+hpe/gKOZ88OWopT hrrUBpAaZyQchSanGdYKXZCP5KsVy3sNHxQoUjdEEJu98R6b1ZebXLwiuSiGtX6DGN 2hER1HnRXCD+Q== From: Arnd Bergmann To: linux-arm-kernel@lists.infradead.org, Paul Walmsley , Aaro Koskinen , Janusz Krzysztofik , Tony Lindgren Cc: linux-kernel@vger.kernel.org, Arnd Bergmann , linux-omap@vger.kernel.org, Kevin Hilman , Mark Brown , Felipe Balbi , Greg Kroah-Hartman , Alan Stern , Bin Liu , Helge Deller , linux-usb@vger.kernel.org, linux-spi@vger.kernel.org, linux-fbdev@vger.kernel.org, dri-devel@lists.freedesktop.org Subject: [PATCH 14/17] ARM: omap1: remove dead code Date: Wed, 19 Oct 2022 17:03:36 +0200 Message-Id: <20221019150410.3851944-14-arnd@kernel.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20221019150410.3851944-1-arnd@kernel.org> References: <20221019144119.3848027-1-arnd@kernel.org> <20221019150410.3851944-1-arnd@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747131146107158989?= X-GMAIL-MSGID: =?utf-8?q?1747131146107158989?= From: Arnd Bergmann After the removal of the unused board files, I went through the omap1 code to look for code that no longer has any callers and remove that. In particular, support for the omap7xx/omap8xx family is now completely unused, so I'm only leaving omap15xx/omap16xx/omap59xx. Cc: Aaro Koskinen Cc: Janusz Krzysztofik Cc: Tony Lindgren Cc: linux-omap@vger.kernel.org Signed-off-by: Arnd Bergmann Reviewed-by: Greg Kroah-Hartman Acked-by: Tony Lindgren Acked-by: Kevin Hilman --- arch/arm/mach-omap1/clock_data.c | 17 +----- arch/arm/mach-omap1/common.h | 8 --- arch/arm/mach-omap1/devices.c | 58 ++----------------- arch/arm/mach-omap1/dma.c | 25 +------- arch/arm/mach-omap1/i2c.c | 14 +---- arch/arm/mach-omap1/io.c | 24 -------- arch/arm/mach-omap1/irq.c | 20 +------ arch/arm/mach-omap1/irqs.h | 9 --- arch/arm/mach-omap1/mcbsp.c | 83 --------------------------- arch/arm/mach-omap1/mtd-xip.h | 4 -- arch/arm/mach-omap1/mux.c | 52 ----------------- arch/arm/mach-omap1/pm.c | 76 ++++--------------------- arch/arm/mach-omap1/pm.h | 39 +------------ arch/arm/mach-omap1/serial.c | 15 ----- arch/arm/mach-omap1/sleep.S | 80 -------------------------- arch/arm/mach-omap1/sram-init.c | 7 +-- arch/arm/mach-omap1/usb.c | 34 +++-------- drivers/spi/spi-omap-uwire.c | 16 +----- drivers/usb/gadget/udc/omap_udc.c | 24 +------- drivers/usb/host/ohci-omap.c | 6 +- drivers/usb/musb/musb_dma.h | 11 +--- drivers/usb/phy/phy-isp1301-omap.c | 91 +----------------------------- drivers/video/fbdev/omap/lcdc.c | 2 - include/linux/soc/ti/omap1-soc.h | 35 ------------ 24 files changed, 39 insertions(+), 711 deletions(-) diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c index 96d846c37c43..c58d200e4816 100644 --- a/arch/arm/mach-omap1/clock_data.c +++ b/arch/arm/mach-omap1/clock_data.c @@ -720,8 +720,6 @@ int __init omap1_clk_init(void) cpu_mask |= CK_16XX; if (cpu_is_omap1510()) cpu_mask |= CK_1510; - if (cpu_is_omap7xx()) - cpu_mask |= CK_7XX; if (cpu_is_omap310()) cpu_mask |= CK_310; @@ -730,9 +728,6 @@ int __init omap1_clk_init(void) ck_dpll1_p = &ck_dpll1; ck_ref_p = &ck_ref; - if (cpu_is_omap7xx()) - ck_ref.rate = 13000000; - pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n", omap_readw(ARM_SYSST), omap_readw(DPLL_CTL), omap_readw(ARM_CKCTL)); @@ -771,12 +766,6 @@ int __init omap1_clk_init(void) } } - if (machine_is_omap_perseus2() || machine_is_omap_fsample()) { - /* Select slicer output as OMAP input clock */ - omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL) & ~0x1, - OMAP7XX_PCC_UPLD_CTRL); - } - /* Amstrad Delta wants BCLK high when inactive */ if (machine_is_ams_delta()) omap_writel(omap_readl(ULPD_CLOCK_CTRL) | @@ -784,11 +773,7 @@ int __init omap1_clk_init(void) ULPD_CLOCK_CTRL); /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */ - /* (on 730, bit 13 must not be cleared) */ - if (cpu_is_omap7xx()) - omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL); - else - omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL); + omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL); /* Put DSP/MPUI into reset until needed */ omap_writew(0, ARM_RSTCT1); diff --git a/arch/arm/mach-omap1/common.h b/arch/arm/mach-omap1/common.h index 5ceff05e15c0..3fd9ed9efb12 100644 --- a/arch/arm/mach-omap1/common.h +++ b/arch/arm/mach-omap1/common.h @@ -35,14 +35,6 @@ #include "soc.h" #include "i2c.h" -#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) -void omap7xx_map_io(void); -#else -static inline void omap7xx_map_io(void) -{ -} -#endif - #ifdef CONFIG_ARCH_OMAP15XX void omap1510_fpga_init_irq(void); void omap15xx_map_io(void); diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c index 80e94770582a..42d1631cecc0 100644 --- a/arch/arm/mach-omap1/devices.c +++ b/arch/arm/mach-omap1/devices.c @@ -63,8 +63,6 @@ static void omap_init_rtc(void) static inline void omap_init_rtc(void) {} #endif -static inline void omap_init_mbox(void) { } - /*-------------------------------------------------------------------------*/ #if IS_ENABLED(CONFIG_MMC_OMAP) @@ -73,22 +71,16 @@ static inline void omap1_mmc_mux(struct omap_mmc_platform_data *mmc_controller, int controller_nr) { if (controller_nr == 0) { - if (cpu_is_omap7xx()) { - omap_cfg_reg(MMC_7XX_CMD); - omap_cfg_reg(MMC_7XX_CLK); - omap_cfg_reg(MMC_7XX_DAT0); - } else { - omap_cfg_reg(MMC_CMD); - omap_cfg_reg(MMC_CLK); - omap_cfg_reg(MMC_DAT0); - } + omap_cfg_reg(MMC_CMD); + omap_cfg_reg(MMC_CLK); + omap_cfg_reg(MMC_DAT0); if (cpu_is_omap1710()) { omap_cfg_reg(M15_1710_MMC_CLKI); omap_cfg_reg(P19_1710_MMC_CMDDIR); omap_cfg_reg(P20_1710_MMC_DATDIR0); } - if (mmc_controller->slots[0].wires == 4 && !cpu_is_omap7xx()) { + if (mmc_controller->slots[0].wires == 4) { omap_cfg_reg(MMC_DAT1); /* NOTE: DAT2 can be on W10 (here) or M15 */ if (!mmc_controller->slots[0].nomux) @@ -154,8 +146,6 @@ static int __init omap_mmc_add(const char *name, int id, unsigned long base, res[3].name = "tx"; res[3].flags = IORESOURCE_DMA; - if (cpu_is_omap7xx()) - data->slots[0].features = MMC_OMAP7XX; if (cpu_is_omap15xx()) data->slots[0].features = MMC_OMAP15XX; if (cpu_is_omap16xx()) @@ -224,43 +214,6 @@ void __init omap1_init_mmc(struct omap_mmc_platform_data **mmc_data, /*-------------------------------------------------------------------------*/ -/* OMAP7xx SPI support */ -#if IS_ENABLED(CONFIG_SPI_OMAP_100K) - -struct platform_device omap_spi1 = { - .name = "omap1_spi100k", - .id = 1, -}; - -struct platform_device omap_spi2 = { - .name = "omap1_spi100k", - .id = 2, -}; - -static void omap_init_spi100k(void) -{ - if (!cpu_is_omap7xx()) - return; - - omap_spi1.dev.platform_data = ioremap(OMAP7XX_SPI1_BASE, 0x7ff); - if (omap_spi1.dev.platform_data) - platform_device_register(&omap_spi1); - - omap_spi2.dev.platform_data = ioremap(OMAP7XX_SPI2_BASE, 0x7ff); - if (omap_spi2.dev.platform_data) - platform_device_register(&omap_spi2); -} - -#else -static inline void omap_init_spi100k(void) -{ -} -#endif - -/*-------------------------------------------------------------------------*/ - -static inline void omap_init_sti(void) {} - /* Numbering for the SPI-capable controllers when used for SPI: * spi = 1 * uwire = 2 @@ -363,10 +316,7 @@ static int __init omap1_init_devices(void) * in alphabetical order so they're easier to sort through. */ - omap_init_mbox(); omap_init_rtc(); - omap_init_spi100k(); - omap_init_sti(); omap_init_uwire(); omap1_init_rng(); diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c index c3f280c3c5d7..756966cb715f 100644 --- a/arch/arm/mach-omap1/dma.c +++ b/arch/arm/mach-omap1/dma.c @@ -261,22 +261,6 @@ static const struct platform_device_info omap_dma_dev_info = { .num_res = 1, }; -/* OMAP730, OMAP850 */ -static const struct dma_slave_map omap7xx_sdma_map[] = { - { "omap-mcbsp.1", "tx", SDMA_FILTER_PARAM(8) }, - { "omap-mcbsp.1", "rx", SDMA_FILTER_PARAM(9) }, - { "omap-mcbsp.2", "tx", SDMA_FILTER_PARAM(10) }, - { "omap-mcbsp.2", "rx", SDMA_FILTER_PARAM(11) }, - { "mmci-omap.0", "tx", SDMA_FILTER_PARAM(21) }, - { "mmci-omap.0", "rx", SDMA_FILTER_PARAM(22) }, - { "omap_udc", "rx0", SDMA_FILTER_PARAM(26) }, - { "omap_udc", "rx1", SDMA_FILTER_PARAM(27) }, - { "omap_udc", "rx2", SDMA_FILTER_PARAM(28) }, - { "omap_udc", "tx0", SDMA_FILTER_PARAM(29) }, - { "omap_udc", "tx1", SDMA_FILTER_PARAM(30) }, - { "omap_udc", "tx2", SDMA_FILTER_PARAM(31) }, -}; - /* OMAP1510, OMAP1610*/ static const struct dma_slave_map omap1xxx_sdma_map[] = { { "omap-mcbsp.1", "tx", SDMA_FILTER_PARAM(8) }, @@ -371,13 +355,8 @@ static int __init omap1_system_dma_init(void) p.dma_attr = d; p.errata = configure_dma_errata(); - if (cpu_is_omap7xx()) { - p.slave_map = omap7xx_sdma_map; - p.slavecnt = ARRAY_SIZE(omap7xx_sdma_map); - } else { - p.slave_map = omap1xxx_sdma_map; - p.slavecnt = ARRAY_SIZE(omap1xxx_sdma_map); - } + p.slave_map = omap1xxx_sdma_map; + p.slavecnt = ARRAY_SIZE(omap1xxx_sdma_map); ret = platform_device_add_data(pdev, &p, sizeof(p)); if (ret) { diff --git a/arch/arm/mach-omap1/i2c.c b/arch/arm/mach-omap1/i2c.c index 22f945360599..94d3e7883e02 100644 --- a/arch/arm/mach-omap1/i2c.c +++ b/arch/arm/mach-omap1/i2c.c @@ -25,13 +25,8 @@ static struct platform_device omap_i2c_devices[1] = { static void __init omap1_i2c_mux_pins(int bus_id) { - if (cpu_is_omap7xx()) { - omap_cfg_reg(I2C_7XX_SDA); - omap_cfg_reg(I2C_7XX_SCL); - } else { - omap_cfg_reg(I2C_SDA); - omap_cfg_reg(I2C_SCL); - } + omap_cfg_reg(I2C_SDA); + omap_cfg_reg(I2C_SCL); } int __init omap_i2c_add_bus(struct omap_i2c_bus_platform_data *pdata, @@ -68,10 +63,7 @@ int __init omap_i2c_add_bus(struct omap_i2c_bus_platform_data *pdata, /* how the cpu bus is wired up differs for 7xx only */ - if (cpu_is_omap7xx()) - pdata->flags |= OMAP_I2C_FLAG_BUS_SHIFT_1; - else - pdata->flags |= OMAP_I2C_FLAG_BUS_SHIFT_2; + pdata->flags |= OMAP_I2C_FLAG_BUS_SHIFT_2; pdev->dev.platform_data = pdata; diff --git a/arch/arm/mach-omap1/io.c b/arch/arm/mach-omap1/io.c index d2db9b8aed3f..72657413795f 100644 --- a/arch/arm/mach-omap1/io.c +++ b/arch/arm/mach-omap1/io.c @@ -31,22 +31,6 @@ static struct map_desc omap_io_desc[] __initdata = { } }; -#if defined (CONFIG_ARCH_OMAP730) || defined (CONFIG_ARCH_OMAP850) -static struct map_desc omap7xx_io_desc[] __initdata = { - { - .virtual = OMAP7XX_DSP_BASE, - .pfn = __phys_to_pfn(OMAP7XX_DSP_START), - .length = OMAP7XX_DSP_SIZE, - .type = MT_DEVICE - }, { - .virtual = OMAP7XX_DSPREG_BASE, - .pfn = __phys_to_pfn(OMAP7XX_DSPREG_START), - .length = OMAP7XX_DSPREG_SIZE, - .type = MT_DEVICE - } -}; -#endif - #ifdef CONFIG_ARCH_OMAP15XX static struct map_desc omap1510_io_desc[] __initdata = { { @@ -87,14 +71,6 @@ static void __init omap1_map_common_io(void) iotable_init(omap_io_desc, ARRAY_SIZE(omap_io_desc)); } -#if defined (CONFIG_ARCH_OMAP730) || defined (CONFIG_ARCH_OMAP850) -void __init omap7xx_map_io(void) -{ - omap1_map_common_io(); - iotable_init(omap7xx_io_desc, ARRAY_SIZE(omap7xx_io_desc)); -} -#endif - #ifdef CONFIG_ARCH_OMAP15XX void __init omap15xx_map_io(void) { diff --git a/arch/arm/mach-omap1/irq.c b/arch/arm/mach-omap1/irq.c index 70868e9f19ac..9ccc784fd614 100644 --- a/arch/arm/mach-omap1/irq.c +++ b/arch/arm/mach-omap1/irq.c @@ -110,14 +110,6 @@ static void omap_irq_set_cfg(int irq, int fiq, int priority, int trigger) irq_bank_writel(val, bank, offset); } -#if defined (CONFIG_ARCH_OMAP730) || defined (CONFIG_ARCH_OMAP850) -static struct omap_irq_bank omap7xx_irq_banks[] = { - { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3f8e22f }, - { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb9c1f2 }, - { .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0x800040f3 }, -}; -#endif - #ifdef CONFIG_ARCH_OMAP15XX static struct omap_irq_bank omap1510_irq_banks[] = { { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3febfff }, @@ -194,12 +186,6 @@ void __init omap1_init_irq(void) int i, j, irq_base; unsigned long nr_irqs; -#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) - if (cpu_is_omap7xx()) { - irq_banks = omap7xx_irq_banks; - irq_bank_count = ARRAY_SIZE(omap7xx_irq_banks); - } -#endif #ifdef CONFIG_ARCH_OMAP15XX if (cpu_is_omap1510()) { irq_banks = omap1510_irq_banks; @@ -230,7 +216,7 @@ void __init omap1_init_irq(void) pr_warn("Couldn't allocate IRQ numbers\n"); irq_base = 0; } - omap_l2_irq = cpu_is_omap7xx() ? irq_base + 1 : irq_base; + omap_l2_irq = irq_base; omap_l2_irq -= NR_IRQS_LEGACY; domain = irq_domain_add_legacy(NULL, nr_irqs, irq_base, 0, @@ -249,10 +235,6 @@ void __init omap1_init_irq(void) irq_bank_writel(0x03, 0, IRQ_CONTROL_REG_OFFSET); irq_bank_writel(0x03, 1, IRQ_CONTROL_REG_OFFSET); - /* Enable interrupts in global mask */ - if (cpu_is_omap7xx()) - irq_bank_writel(0x0, 0, IRQ_GMR_REG_OFFSET); - /* Install the interrupt handlers for each bank */ for (i = 0; i < irq_bank_count; i++) { for (j = i * 32; j < (i + 1) * 32; j++) { diff --git a/arch/arm/mach-omap1/irqs.h b/arch/arm/mach-omap1/irqs.h index 2851acfe5ff3..3ab7050b1b6b 100644 --- a/arch/arm/mach-omap1/irqs.h +++ b/arch/arm/mach-omap1/irqs.h @@ -231,15 +231,6 @@ #define IH_MPUIO_BASE (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE) #define OMAP_IRQ_END (IH_MPUIO_BASE + 16) -/* External FPGA handles interrupts on Innovator boards */ -#define OMAP_FPGA_IRQ_BASE (OMAP_IRQ_END) -#ifdef CONFIG_MACH_OMAP_INNOVATOR -#define OMAP_FPGA_NR_IRQS 24 -#else -#define OMAP_FPGA_NR_IRQS 0 -#endif -#define OMAP_FPGA_IRQ_END (OMAP_FPGA_IRQ_BASE + OMAP_FPGA_NR_IRQS) - #define OMAP_IRQ_BIT(irq) (1 << ((irq - NR_IRQS_LEGACY) % 32)) #ifdef CONFIG_FIQ diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c index 05c25c432449..72e399ec5ed9 100644 --- a/arch/arm/mach-omap1/mcbsp.c +++ b/arch/arm/mach-omap1/mcbsp.c @@ -89,83 +89,6 @@ static struct omap_mcbsp_ops omap1_mcbsp_ops = { #define OMAP1610_MCBSP2_BASE 0xfffb1000 #define OMAP1610_MCBSP3_BASE 0xe1017000 -#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) -struct resource omap7xx_mcbsp_res[][6] = { - { - { - .start = OMAP7XX_MCBSP1_BASE, - .end = OMAP7XX_MCBSP1_BASE + SZ_256, - .flags = IORESOURCE_MEM, - }, - { - .name = "rx", - .start = INT_7XX_McBSP1RX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "tx", - .start = INT_7XX_McBSP1TX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "rx", - .start = 9, - .flags = IORESOURCE_DMA, - }, - { - .name = "tx", - .start = 8, - .flags = IORESOURCE_DMA, - }, - }, - { - { - .start = OMAP7XX_MCBSP2_BASE, - .end = OMAP7XX_MCBSP2_BASE + SZ_256, - .flags = IORESOURCE_MEM, - }, - { - .name = "rx", - .start = INT_7XX_McBSP2RX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "tx", - .start = INT_7XX_McBSP2TX, - .flags = IORESOURCE_IRQ, - }, - { - .name = "rx", - .start = 11, - .flags = IORESOURCE_DMA, - }, - { - .name = "tx", - .start = 10, - .flags = IORESOURCE_DMA, - }, - }, -}; - -#define omap7xx_mcbsp_res_0 omap7xx_mcbsp_res[0] - -static struct omap_mcbsp_platform_data omap7xx_mcbsp_pdata[] = { - { - .ops = &omap1_mcbsp_ops, - }, - { - .ops = &omap1_mcbsp_ops, - }, -}; -#define OMAP7XX_MCBSP_RES_SZ ARRAY_SIZE(omap7xx_mcbsp_res[1]) -#define OMAP7XX_MCBSP_COUNT ARRAY_SIZE(omap7xx_mcbsp_res) -#else -#define omap7xx_mcbsp_res_0 NULL -#define omap7xx_mcbsp_pdata NULL -#define OMAP7XX_MCBSP_RES_SZ 0 -#define OMAP7XX_MCBSP_COUNT 0 -#endif - #ifdef CONFIG_ARCH_OMAP15XX struct resource omap15xx_mcbsp_res[][6] = { { @@ -418,12 +341,6 @@ static int __init omap1_mcbsp_init(void) if (!cpu_class_is_omap1()) return -ENODEV; - if (cpu_is_omap7xx()) - omap_mcbsp_register_board_cfg(omap7xx_mcbsp_res_0, - OMAP7XX_MCBSP_RES_SZ, - omap7xx_mcbsp_pdata, - OMAP7XX_MCBSP_COUNT); - if (cpu_is_omap15xx()) omap_mcbsp_register_board_cfg(omap15xx_mcbsp_res_0, OMAP15XX_MCBSP_RES_SZ, diff --git a/arch/arm/mach-omap1/mtd-xip.h b/arch/arm/mach-omap1/mtd-xip.h index 5ae312ff08a1..cbeda46dd526 100644 --- a/arch/arm/mach-omap1/mtd-xip.h +++ b/arch/arm/mach-omap1/mtd-xip.h @@ -42,11 +42,7 @@ static inline unsigned long xip_omap_mpu_timer_read(int nr) * (see linux/mtd/xip.h) */ -#ifdef CONFIG_MACH_OMAP_PERSEUS2 -#define xip_elapsed_since(x) (signed)((~xip_omap_mpu_timer_read(0) - (x)) / 7) -#else #define xip_elapsed_since(x) (signed)((~xip_omap_mpu_timer_read(0) - (x)) / 6) -#endif /* * xip_cpu_idle() is used when waiting for a delay equal or larger than diff --git a/arch/arm/mach-omap1/mux.c b/arch/arm/mach-omap1/mux.c index 2d9458ff1d29..4456fbc8aa3d 100644 --- a/arch/arm/mach-omap1/mux.c +++ b/arch/arm/mach-omap1/mux.c @@ -21,52 +21,6 @@ static struct omap_mux_cfg arch_mux_cfg; -#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) -static struct pin_config omap7xx_pins[] = { -MUX_CFG_7XX("E2_7XX_KBR0", 12, 21, 0, 20, 1, 0) -MUX_CFG_7XX("J7_7XX_KBR1", 12, 25, 0, 24, 1, 0) -MUX_CFG_7XX("E1_7XX_KBR2", 12, 29, 0, 28, 1, 0) -MUX_CFG_7XX("F3_7XX_KBR3", 13, 1, 0, 0, 1, 0) -MUX_CFG_7XX("D2_7XX_KBR4", 13, 5, 0, 4, 1, 0) -MUX_CFG_7XX("C2_7XX_KBC0", 13, 9, 0, 8, 1, 0) -MUX_CFG_7XX("D3_7XX_KBC1", 13, 13, 0, 12, 1, 0) -MUX_CFG_7XX("E4_7XX_KBC2", 13, 17, 0, 16, 1, 0) -MUX_CFG_7XX("F4_7XX_KBC3", 13, 21, 0, 20, 1, 0) -MUX_CFG_7XX("E3_7XX_KBC4", 13, 25, 0, 24, 1, 0) - -MUX_CFG_7XX("AA17_7XX_USB_DM", 2, 21, 0, 20, 0, 0) -MUX_CFG_7XX("W16_7XX_USB_PU_EN", 2, 25, 0, 24, 0, 0) -MUX_CFG_7XX("W17_7XX_USB_VBUSI", 2, 29, 6, 28, 1, 0) -MUX_CFG_7XX("W18_7XX_USB_DMCK_OUT",3, 3, 1, 2, 0, 0) -MUX_CFG_7XX("W19_7XX_USB_DCRST", 3, 7, 1, 6, 0, 0) - -/* MMC Pins */ -MUX_CFG_7XX("MMC_7XX_CMD", 2, 9, 0, 8, 1, 0) -MUX_CFG_7XX("MMC_7XX_CLK", 2, 13, 0, 12, 1, 0) -MUX_CFG_7XX("MMC_7XX_DAT0", 2, 17, 0, 16, 1, 0) - -/* I2C interface */ -MUX_CFG_7XX("I2C_7XX_SCL", 5, 1, 0, 0, 1, 0) -MUX_CFG_7XX("I2C_7XX_SDA", 5, 5, 0, 0, 1, 0) - -/* SPI pins */ -MUX_CFG_7XX("SPI_7XX_1", 6, 5, 4, 4, 1, 0) -MUX_CFG_7XX("SPI_7XX_2", 6, 9, 4, 8, 1, 0) -MUX_CFG_7XX("SPI_7XX_3", 6, 13, 4, 12, 1, 0) -MUX_CFG_7XX("SPI_7XX_4", 6, 17, 4, 16, 1, 0) -MUX_CFG_7XX("SPI_7XX_5", 8, 25, 0, 24, 0, 0) -MUX_CFG_7XX("SPI_7XX_6", 9, 5, 0, 4, 0, 0) - -/* UART pins */ -MUX_CFG_7XX("UART_7XX_1", 3, 21, 0, 20, 0, 0) -MUX_CFG_7XX("UART_7XX_2", 8, 1, 6, 0, 0, 0) -}; -#define OMAP7XX_PINS_SZ ARRAY_SIZE(omap7xx_pins) -#else -#define omap7xx_pins NULL -#define OMAP7XX_PINS_SZ 0 -#endif /* CONFIG_ARCH_OMAP730 || CONFIG_ARCH_OMAP850 */ - #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) static struct pin_config omap1xxx_pins[] = { /* @@ -489,12 +443,6 @@ EXPORT_SYMBOL(omap_cfg_reg); int __init omap1_mux_init(void) { - if (cpu_is_omap7xx()) { - arch_mux_cfg.pins = omap7xx_pins; - arch_mux_cfg.size = OMAP7XX_PINS_SZ; - arch_mux_cfg.cfg_reg = omap1_cfg_reg; - } - if (cpu_is_omap15xx() || cpu_is_omap16xx()) { arch_mux_cfg.pins = omap1xxx_pins; arch_mux_cfg.size = OMAP1XXX_PINS_SZ; diff --git a/arch/arm/mach-omap1/pm.c b/arch/arm/mach-omap1/pm.c index fce7d2b572bf..9761d8404949 100644 --- a/arch/arm/mach-omap1/pm.c +++ b/arch/arm/mach-omap1/pm.c @@ -69,7 +69,6 @@ static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE]; static unsigned short dsp_sleep_save[DSP_SLEEP_SAVE_SIZE]; static unsigned short ulpd_sleep_save[ULPD_SLEEP_SAVE_SIZE]; -static unsigned int mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_SIZE]; static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE]; static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE]; @@ -166,10 +165,7 @@ static void omap_pm_wakeup_setup(void) * drivers must still separately call omap_set_gpio_wakeup() to * wake up to a GPIO interrupt. */ - if (cpu_is_omap7xx()) - level1_wake = OMAP_IRQ_BIT(INT_7XX_GPIO_BANK1) | - OMAP_IRQ_BIT(INT_7XX_IH2_IRQ); - else if (cpu_is_omap15xx()) + if (cpu_is_omap15xx()) level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) | OMAP_IRQ_BIT(INT_1510_IH2_IRQ); else if (cpu_is_omap16xx()) @@ -178,12 +174,7 @@ static void omap_pm_wakeup_setup(void) omap_writel(~level1_wake, OMAP_IH1_MIR); - if (cpu_is_omap7xx()) { - omap_writel(~level2_wake, OMAP_IH2_0_MIR); - omap_writel(~(OMAP_IRQ_BIT(INT_7XX_WAKE_UP_REQ) | - OMAP_IRQ_BIT(INT_7XX_MPUIO_KEYPAD)), - OMAP_IH2_1_MIR); - } else if (cpu_is_omap15xx()) { + if (cpu_is_omap15xx()) { level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD); omap_writel(~level2_wake, OMAP_IH2_MIR); } else if (cpu_is_omap16xx()) { @@ -236,17 +227,7 @@ void omap1_pm_suspend(void) * Save interrupt, MPUI, ARM and UPLD control registers. */ - if (cpu_is_omap7xx()) { - MPUI7XX_SAVE(OMAP_IH1_MIR); - MPUI7XX_SAVE(OMAP_IH2_0_MIR); - MPUI7XX_SAVE(OMAP_IH2_1_MIR); - MPUI7XX_SAVE(MPUI_CTRL); - MPUI7XX_SAVE(MPUI_DSP_BOOT_CONFIG); - MPUI7XX_SAVE(MPUI_DSP_API_CONFIG); - MPUI7XX_SAVE(EMIFS_CONFIG); - MPUI7XX_SAVE(EMIFF_SDRAM_CONFIG); - - } else if (cpu_is_omap15xx()) { + if (cpu_is_omap15xx()) { MPUI1510_SAVE(OMAP_IH1_MIR); MPUI1510_SAVE(OMAP_IH2_MIR); MPUI1510_SAVE(MPUI_CTRL); @@ -288,9 +269,8 @@ void omap1_pm_suspend(void) /* stop DSP */ omap_writew(omap_readw(ARM_RSTCT1) & ~(1 << DSP_EN), ARM_RSTCT1); - /* shut down dsp_ck */ - if (!cpu_is_omap7xx()) - omap_writew(omap_readw(ARM_CKCTL) & ~(1 << EN_DSPCK), ARM_CKCTL); + /* shut down dsp_ck */ + omap_writew(omap_readw(ARM_CKCTL) & ~(1 << EN_DSPCK), ARM_CKCTL); /* temporarily enabling api_ck to access DSP registers */ omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2); @@ -366,13 +346,7 @@ void omap1_pm_suspend(void) ULPD_RESTORE(ULPD_CLOCK_CTRL); ULPD_RESTORE(ULPD_STATUS_REQ); - if (cpu_is_omap7xx()) { - MPUI7XX_RESTORE(EMIFS_CONFIG); - MPUI7XX_RESTORE(EMIFF_SDRAM_CONFIG); - MPUI7XX_RESTORE(OMAP_IH1_MIR); - MPUI7XX_RESTORE(OMAP_IH2_0_MIR); - MPUI7XX_RESTORE(OMAP_IH2_1_MIR); - } else if (cpu_is_omap15xx()) { + if (cpu_is_omap15xx()) { MPUI1510_RESTORE(MPUI_CTRL); MPUI1510_RESTORE(MPUI_DSP_BOOT_CONFIG); MPUI1510_RESTORE(MPUI_DSP_API_CONFIG); @@ -433,14 +407,7 @@ static int omap_pm_debug_show(struct seq_file *m, void *v) ULPD_SAVE(ULPD_DPLL_CTRL); ULPD_SAVE(ULPD_POWER_CTRL); - if (cpu_is_omap7xx()) { - MPUI7XX_SAVE(MPUI_CTRL); - MPUI7XX_SAVE(MPUI_DSP_STATUS); - MPUI7XX_SAVE(MPUI_DSP_BOOT_CONFIG); - MPUI7XX_SAVE(MPUI_DSP_API_CONFIG); - MPUI7XX_SAVE(EMIFF_SDRAM_CONFIG); - MPUI7XX_SAVE(EMIFS_CONFIG); - } else if (cpu_is_omap15xx()) { + if (cpu_is_omap15xx()) { MPUI1510_SAVE(MPUI_CTRL); MPUI1510_SAVE(MPUI_DSP_STATUS); MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG); @@ -486,21 +453,7 @@ static int omap_pm_debug_show(struct seq_file *m, void *v) ULPD_SHOW(ULPD_STATUS_REQ), ULPD_SHOW(ULPD_POWER_CTRL)); - if (cpu_is_omap7xx()) { - seq_printf(m, - "MPUI7XX_CTRL_REG 0x%-8x \n" - "MPUI7XX_DSP_STATUS_REG: 0x%-8x \n" - "MPUI7XX_DSP_BOOT_CONFIG_REG: 0x%-8x \n" - "MPUI7XX_DSP_API_CONFIG_REG: 0x%-8x \n" - "MPUI7XX_SDRAM_CONFIG_REG: 0x%-8x \n" - "MPUI7XX_EMIFS_CONFIG_REG: 0x%-8x \n", - MPUI7XX_SHOW(MPUI_CTRL), - MPUI7XX_SHOW(MPUI_DSP_STATUS), - MPUI7XX_SHOW(MPUI_DSP_BOOT_CONFIG), - MPUI7XX_SHOW(MPUI_DSP_API_CONFIG), - MPUI7XX_SHOW(EMIFF_SDRAM_CONFIG), - MPUI7XX_SHOW(EMIFS_CONFIG)); - } else if (cpu_is_omap15xx()) { + if (cpu_is_omap15xx()) { seq_printf(m, "MPUI1510_CTRL_REG 0x%-8x \n" "MPUI1510_DSP_STATUS_REG: 0x%-8x \n" @@ -634,10 +587,7 @@ static int __init omap_pm_init(void) * These routines need to be in SRAM as that's the only * memory the MPU can see when it wakes up. */ - if (cpu_is_omap7xx()) { - omap_sram_suspend = omap_sram_push(omap7xx_cpu_suspend, - omap7xx_cpu_suspend_sz); - } else if (cpu_is_omap15xx()) { + if (cpu_is_omap15xx()) { omap_sram_suspend = omap_sram_push(omap1510_cpu_suspend, omap1510_cpu_suspend_sz); } else if (cpu_is_omap16xx()) { @@ -652,9 +602,7 @@ static int __init omap_pm_init(void) arm_pm_idle = omap1_pm_idle; - if (cpu_is_omap7xx()) - irq = INT_7XX_WAKE_UP_REQ; - else if (cpu_is_omap16xx()) + if (cpu_is_omap16xx()) irq = INT_1610_WAKE_UP_REQ; else irq = -1; @@ -673,9 +621,7 @@ static int __init omap_pm_init(void) omap_writew(ULPD_POWER_CTRL_REG_VAL, ULPD_POWER_CTRL); /* Configure IDLECT3 */ - if (cpu_is_omap7xx()) - omap_writel(OMAP7XX_IDLECT3_VAL, OMAP7XX_IDLECT3); - else if (cpu_is_omap16xx()) + if (cpu_is_omap16xx()) omap_writel(OMAP1610_IDLECT3_VAL, OMAP1610_IDLECT3); suspend_set_ops(&omap_pm_ops); diff --git a/arch/arm/mach-omap1/pm.h b/arch/arm/mach-omap1/pm.h index d9165709c532..146dbfd90ba1 100644 --- a/arch/arm/mach-omap1/pm.h +++ b/arch/arm/mach-omap1/pm.h @@ -100,15 +100,7 @@ #define OMAP1610_IDLECT3 0xfffece24 #define OMAP1610_IDLE_LOOP_REQUEST 0x0400 -#define OMAP7XX_IDLECT1_SLEEP_VAL 0x16c7 -#define OMAP7XX_IDLECT2_SLEEP_VAL 0x09c7 -#define OMAP7XX_IDLECT3_VAL 0x3f -#define OMAP7XX_IDLECT3 0xfffece24 -#define OMAP7XX_IDLE_LOOP_REQUEST 0x0C00 - -#if !defined(CONFIG_ARCH_OMAP730) && \ - !defined(CONFIG_ARCH_OMAP850) && \ - !defined(CONFIG_ARCH_OMAP15XX) && \ +#if !defined(CONFIG_ARCH_OMAP15XX) && \ !defined(CONFIG_ARCH_OMAP16XX) #warning "Power management for this processor not implemented yet" #endif @@ -125,17 +117,13 @@ extern void allow_idle_sleep(void); extern void omap1_pm_idle(void); extern void omap1_pm_suspend(void); -extern void omap7xx_cpu_suspend(unsigned long, unsigned long); extern void omap1510_cpu_suspend(unsigned long, unsigned long); extern void omap1610_cpu_suspend(unsigned long, unsigned long); -extern void omap7xx_idle_loop_suspend(void); extern void omap1510_idle_loop_suspend(void); extern void omap1610_idle_loop_suspend(void); -extern unsigned int omap7xx_cpu_suspend_sz; extern unsigned int omap1510_cpu_suspend_sz; extern unsigned int omap1610_cpu_suspend_sz; -extern unsigned int omap7xx_idle_loop_suspend_sz; extern unsigned int omap1510_idle_loop_suspend_sz; extern unsigned int omap1610_idle_loop_suspend_sz; @@ -158,10 +146,6 @@ extern void omap_serial_wake_trigger(int enable); #define ULPD_RESTORE(x) omap_writew((ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]), (x)) #define ULPD_SHOW(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x] -#define MPUI7XX_SAVE(x) mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_##x] = omap_readl(x) -#define MPUI7XX_RESTORE(x) omap_writel((mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_##x]), (x)) -#define MPUI7XX_SHOW(x) mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_##x] - #define MPUI1510_SAVE(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x] = omap_readl(x) #define MPUI1510_RESTORE(x) omap_writel((mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x]), (x)) #define MPUI1510_SHOW(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x] @@ -235,27 +219,6 @@ enum mpui1510_save_state { #endif }; -enum mpui7xx_save_state { - MPUI7XX_SLEEP_SAVE_START = 0, - /* - * MPUI registers 32 bits - */ - MPUI7XX_SLEEP_SAVE_MPUI_CTRL, - MPUI7XX_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG, - MPUI7XX_SLEEP_SAVE_MPUI_DSP_API_CONFIG, - MPUI7XX_SLEEP_SAVE_MPUI_DSP_STATUS, - MPUI7XX_SLEEP_SAVE_EMIFF_SDRAM_CONFIG, - MPUI7XX_SLEEP_SAVE_EMIFS_CONFIG, - MPUI7XX_SLEEP_SAVE_OMAP_IH1_MIR, - MPUI7XX_SLEEP_SAVE_OMAP_IH2_0_MIR, - MPUI7XX_SLEEP_SAVE_OMAP_IH2_1_MIR, -#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) - MPUI7XX_SLEEP_SAVE_SIZE -#else - MPUI7XX_SLEEP_SAVE_SIZE = 0 -#endif -}; - enum mpui1610_save_state { MPUI1610_SLEEP_SAVE_START = 0, /* diff --git a/arch/arm/mach-omap1/serial.c b/arch/arm/mach-omap1/serial.c index 88928fc33b2e..c7f590645774 100644 --- a/arch/arm/mach-omap1/serial.c +++ b/arch/arm/mach-omap1/serial.c @@ -106,13 +106,6 @@ void __init omap_serial_init(void) { int i; - if (cpu_is_omap7xx()) { - serial_platform_data[0].regshift = 0; - serial_platform_data[1].regshift = 0; - serial_platform_data[0].irq = INT_7XX_UART_MODEM_1; - serial_platform_data[1].irq = INT_7XX_UART_MODEM_IRDA_2; - } - if (cpu_is_omap15xx()) { serial_platform_data[0].uartclk = OMAP1510_BASE_BAUD * 16; serial_platform_data[1].uartclk = OMAP1510_BASE_BAUD * 16; @@ -120,14 +113,6 @@ void __init omap_serial_init(void) } for (i = 0; i < ARRAY_SIZE(serial_platform_data) - 1; i++) { - - /* Don't look at UARTs higher than 2 for omap7xx */ - if (cpu_is_omap7xx() && i > 1) { - serial_platform_data[i].membase = NULL; - serial_platform_data[i].mapbase = 0; - continue; - } - /* Static mapping, never released */ serial_platform_data[i].membase = ioremap(serial_platform_data[i].mapbase, SZ_2K); diff --git a/arch/arm/mach-omap1/sleep.S b/arch/arm/mach-omap1/sleep.S index f111b79512ce..6192f52d531a 100644 --- a/arch/arm/mach-omap1/sleep.S +++ b/arch/arm/mach-omap1/sleep.S @@ -61,86 +61,6 @@ * */ -#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) - .align 3 -ENTRY(omap7xx_cpu_suspend) - - @ save registers on stack - stmfd sp!, {r0 - r12, lr} - - @ Drain write cache - mov r4, #0 - mcr p15, 0, r0, c7, c10, 4 - nop - - @ load base address of Traffic Controller - mov r6, #TCMIF_ASM_BASE & 0xff000000 - orr r6, r6, #TCMIF_ASM_BASE & 0x00ff0000 - orr r6, r6, #TCMIF_ASM_BASE & 0x0000ff00 - - @ prepare to put SDRAM into self-refresh manually - ldr r7, [r6, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff] - orr r9, r7, #SELF_REFRESH_MODE & 0xff000000 - orr r9, r9, #SELF_REFRESH_MODE & 0x000000ff - str r9, [r6, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff] - - @ prepare to put EMIFS to Sleep - ldr r8, [r6, #EMIFS_CONFIG_ASM_OFFSET & 0xff] - orr r9, r8, #IDLE_EMIFS_REQUEST & 0xff - str r9, [r6, #EMIFS_CONFIG_ASM_OFFSET & 0xff] - - @ load base address of ARM_IDLECT1 and ARM_IDLECT2 - mov r4, #CLKGEN_REG_ASM_BASE & 0xff000000 - orr r4, r4, #CLKGEN_REG_ASM_BASE & 0x00ff0000 - orr r4, r4, #CLKGEN_REG_ASM_BASE & 0x0000ff00 - - @ turn off clock domains - @ do not disable PERCK (0x04) - mov r5, #OMAP7XX_IDLECT2_SLEEP_VAL & 0xff - orr r5, r5, #OMAP7XX_IDLECT2_SLEEP_VAL & 0xff00 - strh r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff] - - @ request ARM idle - mov r3, #OMAP7XX_IDLECT1_SLEEP_VAL & 0xff - orr r3, r3, #OMAP7XX_IDLECT1_SLEEP_VAL & 0xff00 - strh r3, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff] - - @ disable instruction cache - mrc p15, 0, r9, c1, c0, 0 - bic r2, r9, #0x1000 - mcr p15, 0, r2, c1, c0, 0 - nop - -/* - * Let's wait for the next wake up event to wake us up. r0 can't be - * used here because r0 holds ARM_IDLECT1 - */ - mov r2, #0 - mcr p15, 0, r2, c7, c0, 4 @ wait for interrupt -/* - * omap7xx_cpu_suspend()'s resume point. - * - * It will just start executing here, so we'll restore stuff from the - * stack. - */ - @ re-enable Icache - mcr p15, 0, r9, c1, c0, 0 - - @ reset the ARM_IDLECT1 and ARM_IDLECT2. - strh r1, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff] - strh r0, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff] - - @ Restore EMIFF controls - str r7, [r6, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff] - str r8, [r6, #EMIFS_CONFIG_ASM_OFFSET & 0xff] - - @ restore regs and return - ldmfd sp!, {r0 - r12, pc} - -ENTRY(omap7xx_cpu_suspend_sz) - .word . - omap7xx_cpu_suspend -#endif /* CONFIG_ARCH_OMAP730 || CONFIG_ARCH_OMAP850 */ - #ifdef CONFIG_ARCH_OMAP15XX .align 3 ENTRY(omap1510_cpu_suspend) diff --git a/arch/arm/mach-omap1/sram-init.c b/arch/arm/mach-omap1/sram-init.c index 27c42e2a21cc..79b5a24420f6 100644 --- a/arch/arm/mach-omap1/sram-init.c +++ b/arch/arm/mach-omap1/sram-init.c @@ -95,9 +95,7 @@ static void __init omap_detect_and_map_sram(void) omap_sram_skip = SRAM_BOOTLOADER_SZ; omap_sram_start = OMAP1_SRAM_PA; - if (cpu_is_omap7xx()) - omap_sram_size = 0x32000; /* 200K */ - else if (cpu_is_omap15xx()) + if (cpu_is_omap15xx()) omap_sram_size = 0x30000; /* 192K */ else if (cpu_is_omap1610() || cpu_is_omap1611() || cpu_is_omap1621() || cpu_is_omap1710()) @@ -135,9 +133,6 @@ static void (*_omap_sram_reprogram_clock)(u32 dpllctl, u32 ckctl); void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl) { BUG_ON(!_omap_sram_reprogram_clock); - /* On 730, bit 13 must always be 1 */ - if (cpu_is_omap7xx()) - ckctl |= 0x2000; _omap_sram_reprogram_clock(dpllctl, ckctl); } diff --git a/arch/arm/mach-omap1/usb.c b/arch/arm/mach-omap1/usb.c index 0119f3ddb7a6..08d42abc4a0f 100644 --- a/arch/arm/mach-omap1/usb.c +++ b/arch/arm/mach-omap1/usb.c @@ -190,12 +190,6 @@ static struct platform_device udc_device = { static inline void udc_device_init(struct omap_usb_config *pdata) { - /* IRQ numbers for omap7xx */ - if(cpu_is_omap7xx()) { - udc_resources[1].start = INT_7XX_USB_GENI; - udc_resources[2].start = INT_7XX_USB_NON_ISO; - udc_resources[3].start = INT_7XX_USB_ISO; - } pdata->udc_device = &udc_device; } @@ -238,8 +232,6 @@ static inline void ohci_device_init(struct omap_usb_config *pdata) if (!IS_ENABLED(CONFIG_USB_OHCI_HCD)) return; - if (cpu_is_omap7xx()) - ohci_resources[1].start = INT_7XX_USB_HHC_1; pdata->ohci_device = &ohci_device; pdata->ocpi_enable = &ocpi_enable; } @@ -267,8 +259,6 @@ static struct platform_device otg_device = { static inline void otg_device_init(struct omap_usb_config *pdata) { - if (cpu_is_omap7xx()) - otg_resources[1].start = INT_7XX_USB_OTG; pdata->otg_device = &otg_device; } @@ -297,14 +287,7 @@ static u32 __init omap1_usb0_init(unsigned nwires, unsigned is_device) } if (is_device) { - if (cpu_is_omap7xx()) { - omap_cfg_reg(AA17_7XX_USB_DM); - omap_cfg_reg(W16_7XX_USB_PU_EN); - omap_cfg_reg(W17_7XX_USB_VBUSI); - omap_cfg_reg(W18_7XX_USB_DMCK_OUT); - omap_cfg_reg(W19_7XX_USB_DCRST); - } else - omap_cfg_reg(W4_USB_PUEN); + omap_cfg_reg(W4_USB_PUEN); } if (nwires == 2) { @@ -324,14 +307,11 @@ static u32 __init omap1_usb0_init(unsigned nwires, unsigned is_device) * - OTG support on this port not yet written */ - /* Don't do this for omap7xx -- it causes USB to not work correctly */ - if (!cpu_is_omap7xx()) { - l = omap_readl(USB_TRANSCEIVER_CTRL); - l &= ~(7 << 4); - if (!is_device) - l |= (3 << 1); - omap_writel(l, USB_TRANSCEIVER_CTRL); - } + l = omap_readl(USB_TRANSCEIVER_CTRL); + l &= ~(7 << 4); + if (!is_device) + l |= (3 << 1); + omap_writel(l, USB_TRANSCEIVER_CTRL); return 3 << 16; } @@ -698,7 +678,7 @@ void __init omap1_usb_init(struct omap_usb_config *_pdata) ohci_device_init(pdata); otg_device_init(pdata); - if (cpu_is_omap7xx() || cpu_is_omap16xx()) + if (cpu_is_omap16xx()) omap_otg_init(pdata); else if (cpu_is_omap15xx()) omap_1510_usb_init(pdata); diff --git a/drivers/spi/spi-omap-uwire.c b/drivers/spi/spi-omap-uwire.c index 29198e6815b2..20c87163d612 100644 --- a/drivers/spi/spi-omap-uwire.c +++ b/drivers/spi/spi-omap-uwire.c @@ -99,7 +99,7 @@ struct uwire_state { * Or, put it in a structure which is used throughout the driver; * that avoids having to issue two loads for each bit of static data. */ -static unsigned int uwire_idx_shift; +static unsigned int uwire_idx_shift = 2; static void __iomem *uwire_base; static inline void uwire_write_reg(int idx, u16 val) @@ -481,11 +481,6 @@ static int uwire_probe(struct platform_device *pdev) } clk_prepare_enable(uwire->ck); - if (cpu_is_omap7xx()) - uwire_idx_shift = 1; - else - uwire_idx_shift = 2; - uwire_write_reg(UWIRE_SR3, 1); /* the spi->mode bits understood by this driver: */ @@ -536,15 +531,6 @@ static struct platform_driver uwire_driver = { static int __init omap_uwire_init(void) { - /* FIXME move these into the relevant board init code. also, include - * H3 support; it uses tsc2101 like H2 (on a different chipselect). - */ - - if (machine_is_omap_h2()) { - /* defaults: W21 SDO, U18 SDI, V19 SCL */ - omap_cfg_reg(N14_1610_UWIRE_CS0); - omap_cfg_reg(N15_1610_UWIRE_CS1); - } return platform_driver_register(&uwire_driver); } diff --git a/drivers/usb/gadget/udc/omap_udc.c b/drivers/usb/gadget/udc/omap_udc.c index bea346e362b2..1be8c19f2a04 100644 --- a/drivers/usb/gadget/udc/omap_udc.c +++ b/drivers/usb/gadget/udc/omap_udc.c @@ -2036,12 +2036,7 @@ static irqreturn_t omap_udc_iso_irq(int irq, void *_dev) static inline int machine_without_vbus_sense(void) { - return machine_is_omap_innovator() - || machine_is_omap_osk() - || machine_is_omap_palmte() - || machine_is_sx1() - /* No known omap7xx boards with vbus sense */ - || cpu_is_omap7xx(); + return machine_is_omap_osk() || machine_is_sx1(); } static int omap_udc_start(struct usb_gadget *g, @@ -2759,9 +2754,6 @@ static int omap_udc_probe(struct platform_device *pdev) struct clk *dc_clk = NULL; struct clk *hhc_clk = NULL; - if (cpu_is_omap7xx()) - use_dma = 0; - /* NOTE: "knows" the order of the resources! */ if (!request_mem_region(pdev->resource[0].start, resource_size(&pdev->resource[0]), @@ -2780,16 +2772,6 @@ static int omap_udc_probe(struct platform_device *pdev) udelay(100); } - if (cpu_is_omap7xx()) { - dc_clk = clk_get(&pdev->dev, "usb_dc_ck"); - hhc_clk = clk_get(&pdev->dev, "l3_ocpi_ck"); - BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk)); - /* can't use omap_udc_enable_clock yet */ - clk_prepare_enable(dc_clk); - clk_prepare_enable(hhc_clk); - udelay(100); - } - INFO("OMAP UDC rev %d.%d%s\n", omap_readw(UDC_REV) >> 4, omap_readw(UDC_REV) & 0xf, config->otg ? ", Mini-AB" : ""); @@ -2914,7 +2896,7 @@ static int omap_udc_probe(struct platform_device *pdev) goto cleanup1; } #endif - if (cpu_is_omap16xx() || cpu_is_omap7xx()) { + if (cpu_is_omap16xx()) { udc->dc_clk = dc_clk; udc->hhc_clk = hhc_clk; clk_disable(hhc_clk); @@ -2933,7 +2915,7 @@ static int omap_udc_probe(struct platform_device *pdev) if (!IS_ERR_OR_NULL(xceiv)) usb_put_phy(xceiv); - if (cpu_is_omap16xx() || cpu_is_omap7xx()) { + if (cpu_is_omap16xx()) { clk_disable_unprepare(hhc_clk); clk_disable_unprepare(dc_clk); clk_put(hhc_clk); diff --git a/drivers/usb/host/ohci-omap.c b/drivers/usb/host/ohci-omap.c index cb29701df911..d7f594db56c6 100644 --- a/drivers/usb/host/ohci-omap.c +++ b/drivers/usb/host/ohci-omap.c @@ -107,10 +107,6 @@ static int ohci_omap_reset(struct usb_hcd *hcd) hcd->power_budget = 8; } - /* boards can use OTG transceivers in non-OTG modes */ - need_transceiver = need_transceiver - || machine_is_omap_h2() || machine_is_omap_h3(); - /* XXX OMAP16xx only */ if (config->ocpi_enable) config->ocpi_enable(); @@ -150,7 +146,7 @@ static int ohci_omap_reset(struct usb_hcd *hcd) } /* board-specific power switching and overcurrent support */ - if (machine_is_omap_osk() || machine_is_omap_innovator()) { + if (machine_is_omap_osk()) { u32 rh = roothub_a (ohci); /* power switching (ganged by default) */ diff --git a/drivers/usb/musb/musb_dma.h b/drivers/usb/musb/musb_dma.h index 7d67b69df0a0..be32c6f90848 100644 --- a/drivers/usb/musb/musb_dma.h +++ b/drivers/usb/musb/musb_dma.h @@ -61,12 +61,6 @@ struct musb_hw_ep; #define musb_dma_cppi41(musb) 0 #endif -#ifdef CONFIG_USB_TI_CPPI_DMA -#define musb_dma_cppi(musb) (musb->ops->quirks & MUSB_DMA_CPPI) -#else -#define musb_dma_cppi(musb) 0 -#endif - #ifdef CONFIG_USB_TUSB_OMAP_DMA #define tusb_dma_omap(musb) (musb->ops->quirks & MUSB_DMA_TUSB_OMAP) #else @@ -79,9 +73,8 @@ struct musb_hw_ep; #define musb_dma_inventra(musb) 0 #endif -#if defined(CONFIG_USB_TI_CPPI_DMA) || defined(CONFIG_USB_TI_CPPI41_DMA) -#define is_cppi_enabled(musb) \ - (musb_dma_cppi(musb) || musb_dma_cppi41(musb)) +#if defined(CONFIG_USB_TI_CPPI41_DMA) +#define is_cppi_enabled(musb) musb_dma_cppi41(musb) #else #define is_cppi_enabled(musb) 0 #endif diff --git a/drivers/usb/phy/phy-isp1301-omap.c b/drivers/usb/phy/phy-isp1301-omap.c index e5d3f206097c..394386a4bef8 100644 --- a/drivers/usb/phy/phy-isp1301-omap.c +++ b/drivers/usb/phy/phy-isp1301-omap.c @@ -77,51 +77,6 @@ struct isp1301 { /*-------------------------------------------------------------------------*/ -/* board-specific PM hooks */ - -#if defined(CONFIG_MACH_OMAP_H2) || defined(CONFIG_MACH_OMAP_H3) - -#if IS_REACHABLE(CONFIG_TPS65010) - -#include - -#else - -static inline int tps65010_set_vbus_draw(unsigned mA) -{ - pr_debug("tps65010: draw %d mA (STUB)\n", mA); - return 0; -} - -#endif - -static void enable_vbus_draw(struct isp1301 *isp, unsigned mA) -{ - int status = tps65010_set_vbus_draw(mA); - if (status < 0) - pr_debug(" VBUS %d mA error %d\n", mA, status); -} - -#else - -static void enable_vbus_draw(struct isp1301 *isp, unsigned mA) -{ - /* H4 controls this by DIP switch S2.4; no soft control. - * ON means the charger is always enabled. Leave it OFF - * unless the OTG port is used only in B-peripheral mode. - */ -} - -#endif - -static void enable_vbus_source(struct isp1301 *isp) -{ - /* this board won't supply more than 8mA vbus power. - * some boards can switch a 100ma "unit load" (or more). - */ -} - - /* products will deliver OTG messages with LEDs, GUI, etc */ static inline void notresponding(struct isp1301 *isp) { @@ -916,10 +871,8 @@ static void b_peripheral(struct isp1301 *isp) usb_gadget_vbus_connect(isp->phy.otg->gadget); #ifdef CONFIG_USB_OTG - enable_vbus_draw(isp, 8); otg_update_isp(isp); #else - enable_vbus_draw(isp, 100); /* UDC driver just set OTG_BSESSVLD */ isp1301_set_bits(isp, ISP1301_OTG_CONTROL_1, OTG1_DP_PULLUP); isp1301_clear_bits(isp, ISP1301_OTG_CONTROL_1, OTG1_DP_PULLDOWN); @@ -947,7 +900,6 @@ static void isp_update_otg(struct isp1301 *isp, u8 stat) a_idle(isp, "idle"); fallthrough; case OTG_STATE_A_IDLE: - enable_vbus_source(isp); fallthrough; case OTG_STATE_A_WAIT_VRISE: /* we skip over OTG_STATE_A_WAIT_BCON, since @@ -1023,7 +975,6 @@ static void isp_update_otg(struct isp1301 *isp, u8 stat) case OTG_STATE_B_HOST: if (likely(isp_bstat & OTG_B_SESS_VLD)) break; - enable_vbus_draw(isp, 0); #ifndef CONFIG_USB_OTG /* UDC driver will clear OTG_BSESSVLD */ isp1301_set_bits(isp, ISP1301_OTG_CONTROL_1, @@ -1283,9 +1234,6 @@ isp1301_set_host(struct usb_otg *otg, struct usb_bus *host) power_up(isp); - if (machine_is_omap_h2()) - isp1301_set_bits(isp, ISP1301_MODE_CONTROL_1, MC1_DAT_SE0); - dev_info(&isp->client->dev, "A-Host sessions ok\n"); isp1301_set_bits(isp, ISP1301_INTERRUPT_RISING, INTR_ID_GND); @@ -1320,8 +1268,6 @@ isp1301_set_peripheral(struct usb_otg *otg, struct usb_gadget *gadget) if (!gadget) { omap_writew(0, OTG_IRQ_EN); - if (!otg->default_a) - enable_vbus_draw(isp, 0); usb_gadget_vbus_disconnect(otg->gadget); otg->gadget = NULL; power_down(isp); @@ -1352,9 +1298,6 @@ isp1301_set_peripheral(struct usb_otg *otg, struct usb_gadget *gadget) power_up(isp); isp->phy.otg->state = OTG_STATE_B_IDLE; - if (machine_is_omap_h2() || machine_is_omap_h3()) - isp1301_set_bits(isp, ISP1301_MODE_CONTROL_1, MC1_DAT_SE0); - isp1301_set_bits(isp, ISP1301_INTERRUPT_RISING, INTR_SESS_VLD); isp1301_set_bits(isp, ISP1301_INTERRUPT_FALLING, @@ -1380,16 +1323,6 @@ isp1301_set_peripheral(struct usb_otg *otg, struct usb_gadget *gadget) /*-------------------------------------------------------------------------*/ -static int -isp1301_set_power(struct usb_phy *dev, unsigned mA) -{ - if (!the_transceiver) - return -ENODEV; - if (dev->otg->state == OTG_STATE_B_PERIPHERAL) - enable_vbus_draw(the_transceiver, mA); - return 0; -} - static int isp1301_start_srp(struct usb_otg *otg) { @@ -1538,26 +1471,7 @@ isp1301_probe(struct i2c_client *i2c, const struct i2c_device_id *id) } #endif - if (machine_is_omap_h2()) { - struct gpio_desc *gpiod; - - /* full speed signaling by default */ - isp1301_set_bits(isp, ISP1301_MODE_CONTROL_1, - MC1_SPEED); - isp1301_set_bits(isp, ISP1301_MODE_CONTROL_2, - MC2_SPD_SUSP_CTRL); - - gpiod = devm_gpiod_get(&i2c->dev, NULL, GPIOD_IN); - if (IS_ERR(gpiod)) { - dev_err(&i2c->dev, "cannot obtain H2 GPIO\n"); - goto fail; - } - gpiod_set_consumer_name(gpiod, "isp1301"); - irq = gpiod_to_irq(gpiod); - isp->irq_type = IRQF_TRIGGER_FALLING; - } else { - irq = i2c->irq; - } + irq = i2c->irq; status = request_irq(irq, isp1301_irq, isp->irq_type, DRIVER_NAME, isp); @@ -1569,15 +1483,12 @@ isp1301_probe(struct i2c_client *i2c, const struct i2c_device_id *id) isp->phy.dev = &i2c->dev; isp->phy.label = DRIVER_NAME; - isp->phy.set_power = isp1301_set_power; - isp->phy.otg->usb_phy = &isp->phy; isp->phy.otg->set_host = isp1301_set_host; isp->phy.otg->set_peripheral = isp1301_set_peripheral; isp->phy.otg->start_srp = isp1301_start_srp; isp->phy.otg->start_hnp = isp1301_start_hnp; - enable_vbus_draw(isp, 0); power_down(isp); the_transceiver = isp; diff --git a/drivers/video/fbdev/omap/lcdc.c b/drivers/video/fbdev/omap/lcdc.c index e7ce783e5215..abb8b11464e8 100644 --- a/drivers/video/fbdev/omap/lcdc.c +++ b/drivers/video/fbdev/omap/lcdc.c @@ -706,8 +706,6 @@ static int omap_lcdc_init(struct omapfb_device *fbdev, int ext_mode, if (machine_is_ams_delta()) rate /= 4; - if (machine_is_omap_h3()) - rate /= 3; r = clk_set_rate(lcdc.lcd_ck, rate); if (r) { dev_err(fbdev->dev, "failed to adjust LCD rate\n"); diff --git a/include/linux/soc/ti/omap1-soc.h b/include/linux/soc/ti/omap1-soc.h index 81008d400bb6..a42d9aa68648 100644 --- a/include/linux/soc/ti/omap1-soc.h +++ b/include/linux/soc/ti/omap1-soc.h @@ -20,22 +20,6 @@ #undef MULTI_OMAP1 #undef OMAP_NAME -#ifdef CONFIG_ARCH_OMAP730 -# ifdef OMAP_NAME -# undef MULTI_OMAP1 -# define MULTI_OMAP1 -# else -# define OMAP_NAME omap730 -# endif -#endif -#ifdef CONFIG_ARCH_OMAP850 -# ifdef OMAP_NAME -# undef MULTI_OMAP1 -# define MULTI_OMAP1 -# else -# define OMAP_NAME omap850 -# endif -#endif #ifdef CONFIG_ARCH_OMAP15XX # ifdef OMAP_NAME # undef MULTI_OMAP1 @@ -69,7 +53,6 @@ unsigned int omap_rev(void); /* * Macros to group OMAP into cpu classes. * These can be used in most places. - * cpu_is_omap7xx(): True for OMAP730, OMAP850 * cpu_is_omap15xx(): True for OMAP1510, OMAP5910 and OMAP310 * cpu_is_omap16xx(): True for OMAP1610, OMAP5912 and OMAP1710 */ @@ -89,23 +72,13 @@ static inline int is_omap ##subclass (void) \ return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \ } -IS_OMAP_CLASS(7xx, 0x07) IS_OMAP_CLASS(15xx, 0x15) IS_OMAP_CLASS(16xx, 0x16) -#define cpu_is_omap7xx() 0 #define cpu_is_omap15xx() 0 #define cpu_is_omap16xx() 0 #if defined(MULTI_OMAP1) -# if defined(CONFIG_ARCH_OMAP730) -# undef cpu_is_omap7xx -# define cpu_is_omap7xx() is_omap7xx() -# endif -# if defined(CONFIG_ARCH_OMAP850) -# undef cpu_is_omap7xx -# define cpu_is_omap7xx() is_omap7xx() -# endif # if defined(CONFIG_ARCH_OMAP15XX) # undef cpu_is_omap15xx # define cpu_is_omap15xx() is_omap15xx() @@ -115,14 +88,6 @@ IS_OMAP_CLASS(16xx, 0x16) # define cpu_is_omap16xx() is_omap16xx() # endif #else -# if defined(CONFIG_ARCH_OMAP730) -# undef cpu_is_omap7xx -# define cpu_is_omap7xx() 1 -# endif -# if defined(CONFIG_ARCH_OMAP850) -# undef cpu_is_omap7xx -# define cpu_is_omap7xx() 1 -# endif # if defined(CONFIG_ARCH_OMAP15XX) # undef cpu_is_omap15xx # define cpu_is_omap15xx() 1 From patchwork Wed Oct 19 15:03:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnd Bergmann X-Patchwork-Id: 5707 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp395523wrs; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id f7-20020a056402354700b0043d00293d23si15637524edd.391.2022.10.19.08.43.03; Wed, 19 Oct 2022 08:43:28 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b="untci+/V"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229962AbiJSP2P (ORCPT + 99 others); Wed, 19 Oct 2022 11:28:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58624 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232233AbiJSP1Y (ORCPT ); Wed, 19 Oct 2022 11:27:24 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AABFF1D4DDA; Wed, 19 Oct 2022 08:20:28 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 0ED4B6184B; Wed, 19 Oct 2022 15:20:16 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8B55BC433D6; Wed, 19 Oct 2022 15:20:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1666192815; bh=OHnFw0JhLweZiz1MQUA1JZLc1dJxeCgP07D/rnW6zd4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=untci+/VB0LLnWeB2Wvp55+ab4w9tkXF5NfFqbqB30zosPvay2h+oJay8MLP3rydj a/qZwLJs2h0S0ByUbglJxnwgFXtaX2FYdKoJRlwBNpIj0WrLjEOLxWf3rCTv47y9Vq cQNtXpZl//qFXnAHdZ91AZ0HfQhr/oyn+dZByNUw0XDn/mIBxzZayg9uJPi3+7T/2l kfp83tfGL3qbD6cRbwDG8Gd0+Ldir5WazJRgFIEq2plXg85e6OzzqaXdUa5d/pGM3v AyZiAwIN1dWJbR1eOYDCCWXwt9zvphICi/0tagJJbvTbcRN8aCeMGRXjjxGkncboWW MjSz6wbmso7cQ== From: Arnd Bergmann To: linux-arm-kernel@lists.infradead.org, Helge Deller Cc: linux-kernel@vger.kernel.org, Arnd Bergmann , Aaro Koskinen , Janusz Krzysztofik , Tony Lindgren , linux-omap@vger.kernel.org, Marek Vasut , Angelo Arrifano , Imre Deak , Bartlomiej Zolnierkiewicz , linux-fbdev@vger.kernel.org, dri-devel@lists.freedesktop.org Subject: [PATCH 15/17] fbdev: omapfb: remove unused board support Date: Wed, 19 Oct 2022 17:03:37 +0200 Message-Id: <20221019150410.3851944-15-arnd@kernel.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20221019150410.3851944-1-arnd@kernel.org> References: <20221019144119.3848027-1-arnd@kernel.org> <20221019150410.3851944-1-arnd@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747131258252389373?= X-GMAIL-MSGID: =?utf-8?q?1747131258252389373?= From: Arnd Bergmann A number of omap1 based board files got removed, so the corresponding framebuffer drivers are no longer used. The remaining ones are for ams_delta, osk and palmTE, which are still part of the mainline kernel. Cc: Aaro Koskinen Cc: Janusz Krzysztofik Cc: Tony Lindgren Cc: linux-omap@vger.kernel.org Cc: Marek Vasut Cc: Angelo Arrifano Cc: Imre Deak Signed-off-by: Arnd Bergmann Acked-by: Tony Lindgren --- drivers/video/fbdev/omap/Kconfig | 9 --- drivers/video/fbdev/omap/Makefile | 6 -- drivers/video/fbdev/omap/lcd_h3.c | 82 -------------------- drivers/video/fbdev/omap/lcd_htcherald.c | 59 -------------- drivers/video/fbdev/omap/lcd_inn1510.c | 69 ----------------- drivers/video/fbdev/omap/lcd_inn1610.c | 99 ------------------------ drivers/video/fbdev/omap/lcd_palmtt.c | 65 ---------------- drivers/video/fbdev/omap/lcd_palmz71.c | 59 -------------- 8 files changed, 448 deletions(-) delete mode 100644 drivers/video/fbdev/omap/lcd_h3.c delete mode 100644 drivers/video/fbdev/omap/lcd_htcherald.c delete mode 100644 drivers/video/fbdev/omap/lcd_inn1510.c delete mode 100644 drivers/video/fbdev/omap/lcd_inn1610.c delete mode 100644 drivers/video/fbdev/omap/lcd_palmtt.c delete mode 100644 drivers/video/fbdev/omap/lcd_palmz71.c diff --git a/drivers/video/fbdev/omap/Kconfig b/drivers/video/fbdev/omap/Kconfig index b1786cf1b486..a6548283451f 100644 --- a/drivers/video/fbdev/omap/Kconfig +++ b/drivers/video/fbdev/omap/Kconfig @@ -40,15 +40,6 @@ config FB_OMAP_LCD_MIPID the Mobile Industry Processor Interface DBI-C/DCS specification. (Supported LCDs: Philips LPH8923, Sharp LS041Y3) -config FB_OMAP_LCD_H3 - bool "TPS65010 LCD controller on OMAP-H3" - depends on MACH_OMAP_H3 || COMPILE_TEST - depends on TPS65010=y - default y - help - Say Y here if you want to have support for the LCD on the - H3 board. - config FB_OMAP_DMA_TUNE bool "Set DMA SDRAM access priority high" depends on FB_OMAP diff --git a/drivers/video/fbdev/omap/Makefile b/drivers/video/fbdev/omap/Makefile index b88e02f5cb1f..504edb9c09dd 100644 --- a/drivers/video/fbdev/omap/Makefile +++ b/drivers/video/fbdev/omap/Makefile @@ -17,16 +17,10 @@ objs-y$(CONFIG_FB_OMAP_LCDC_EXTERNAL) += sossi.o objs-y$(CONFIG_FB_OMAP_LCDC_HWA742) += hwa742.o lcds-y$(CONFIG_MACH_AMS_DELTA) += lcd_ams_delta.o -lcds-y$(CONFIG_FB_OMAP_LCD_H3) += lcd_h3.o lcds-y$(CONFIG_MACH_OMAP_PALMTE) += lcd_palmte.o -lcds-y$(CONFIG_MACH_OMAP_PALMTT) += lcd_palmtt.o -lcds-y$(CONFIG_MACH_OMAP_PALMZ71) += lcd_palmz71.o -lcds-$(CONFIG_ARCH_OMAP16XX)$(CONFIG_MACH_OMAP_INNOVATOR) += lcd_inn1610.o -lcds-$(CONFIG_ARCH_OMAP15XX)$(CONFIG_MACH_OMAP_INNOVATOR) += lcd_inn1510.o lcds-y$(CONFIG_MACH_OMAP_OSK) += lcd_osk.o lcds-y$(CONFIG_FB_OMAP_LCD_MIPID) += lcd_mipid.o -lcds-y$(CONFIG_MACH_HERALD) += lcd_htcherald.o omapfb-objs := $(objs-yy) diff --git a/drivers/video/fbdev/omap/lcd_h3.c b/drivers/video/fbdev/omap/lcd_h3.c deleted file mode 100644 index 1766dff767bb..000000000000 --- a/drivers/video/fbdev/omap/lcd_h3.c +++ /dev/null @@ -1,82 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * LCD panel support for the TI OMAP H3 board - * - * Copyright (C) 2004 Nokia Corporation - * Author: Imre Deak - */ - -#include -#include -#include -#include - -#include "omapfb.h" - -#define MODULE_NAME "omapfb-lcd_h3" - -static int h3_panel_enable(struct lcd_panel *panel) -{ - int r = 0; - - /* GPIO1 and GPIO2 of TPS65010 send LCD_ENBKL and LCD_ENVDD signals */ - r = tps65010_set_gpio_out_value(GPIO1, HIGH); - if (!r) - r = tps65010_set_gpio_out_value(GPIO2, HIGH); - if (r) - pr_err(MODULE_NAME ": Unable to turn on LCD panel\n"); - - return r; -} - -static void h3_panel_disable(struct lcd_panel *panel) -{ - int r = 0; - - /* GPIO1 and GPIO2 of TPS65010 send LCD_ENBKL and LCD_ENVDD signals */ - r = tps65010_set_gpio_out_value(GPIO1, LOW); - if (!r) - tps65010_set_gpio_out_value(GPIO2, LOW); - if (r) - pr_err(MODULE_NAME ": Unable to turn off LCD panel\n"); -} - -static struct lcd_panel h3_panel = { - .name = "h3", - .config = OMAP_LCDC_PANEL_TFT, - - .data_lines = 16, - .bpp = 16, - .x_res = 240, - .y_res = 320, - .pixel_clock = 12000, - .hsw = 12, - .hfp = 14, - .hbp = 72 - 12, - .vsw = 1, - .vfp = 1, - .vbp = 0, - .pcd = 0, - - .enable = h3_panel_enable, - .disable = h3_panel_disable, -}; - -static int h3_panel_probe(struct platform_device *pdev) -{ - omapfb_register_panel(&h3_panel); - return 0; -} - -static struct platform_driver h3_panel_driver = { - .probe = h3_panel_probe, - .driver = { - .name = "lcd_h3", - }, -}; - -module_platform_driver(h3_panel_driver); - -MODULE_AUTHOR("Imre Deak"); -MODULE_DESCRIPTION("LCD panel support for the TI OMAP H3 board"); -MODULE_LICENSE("GPL"); diff --git a/drivers/video/fbdev/omap/lcd_htcherald.c b/drivers/video/fbdev/omap/lcd_htcherald.c deleted file mode 100644 index d1c615c516dd..000000000000 --- a/drivers/video/fbdev/omap/lcd_htcherald.c +++ /dev/null @@ -1,59 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * File: drivers/video/omap/lcd-htcherald.c - * - * LCD panel support for the HTC Herald - * - * Copyright (C) 2009 Cory Maccarrone - * Copyright (C) 2009 Wing Linux - * - * Based on the lcd_htcwizard.c file from the linwizard project: - * Copyright (C) linwizard.sourceforge.net - * Author: Angelo Arrifano - * Based on lcd_h4 by Imre Deak - */ - -#include -#include - -#include "omapfb.h" - -/* Found on WIZ200 (miknix) and some HERA110 models (darkstar62) */ -static struct lcd_panel htcherald_panel_1 = { - .name = "lcd_herald", - .config = OMAP_LCDC_PANEL_TFT | - OMAP_LCDC_INV_HSYNC | - OMAP_LCDC_INV_VSYNC | - OMAP_LCDC_INV_PIX_CLOCK, - .bpp = 16, - .data_lines = 16, - .x_res = 240, - .y_res = 320, - .pixel_clock = 6093, - .pcd = 0, /* 15 */ - .hsw = 10, - .hfp = 10, - .hbp = 20, - .vsw = 3, - .vfp = 2, - .vbp = 2, -}; - -static int htcherald_panel_probe(struct platform_device *pdev) -{ - omapfb_register_panel(&htcherald_panel_1); - return 0; -} - -static struct platform_driver htcherald_panel_driver = { - .probe = htcherald_panel_probe, - .driver = { - .name = "lcd_htcherald", - }, -}; - -module_platform_driver(htcherald_panel_driver); - -MODULE_AUTHOR("Cory Maccarrone"); -MODULE_LICENSE("GPL"); -MODULE_DESCRIPTION("LCD panel support for the HTC Herald"); diff --git a/drivers/video/fbdev/omap/lcd_inn1510.c b/drivers/video/fbdev/omap/lcd_inn1510.c deleted file mode 100644 index bb915637e9b6..000000000000 --- a/drivers/video/fbdev/omap/lcd_inn1510.c +++ /dev/null @@ -1,69 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * LCD panel support for the TI OMAP1510 Innovator board - * - * Copyright (C) 2004 Nokia Corporation - * Author: Imre Deak - */ - -#include -#include -#include - -#include - -#include "omapfb.h" - -static void __iomem *omap1510_fpga_lcd_panel_control; - -static int innovator1510_panel_enable(struct lcd_panel *panel) -{ - __raw_writeb(0x7, omap1510_fpga_lcd_panel_control); - return 0; -} - -static void innovator1510_panel_disable(struct lcd_panel *panel) -{ - __raw_writeb(0x0, omap1510_fpga_lcd_panel_control); -} - -static struct lcd_panel innovator1510_panel = { - .name = "inn1510", - .config = OMAP_LCDC_PANEL_TFT, - - .bpp = 16, - .data_lines = 16, - .x_res = 240, - .y_res = 320, - .pixel_clock = 12500, - .hsw = 40, - .hfp = 40, - .hbp = 72, - .vsw = 1, - .vfp = 1, - .vbp = 0, - .pcd = 12, - - .enable = innovator1510_panel_enable, - .disable = innovator1510_panel_disable, -}; - -static int innovator1510_panel_probe(struct platform_device *pdev) -{ - omap1510_fpga_lcd_panel_control = (void __iomem *)pdev->dev.platform_data; - omapfb_register_panel(&innovator1510_panel); - return 0; -} - -static struct platform_driver innovator1510_panel_driver = { - .probe = innovator1510_panel_probe, - .driver = { - .name = "lcd_inn1510", - }, -}; - -module_platform_driver(innovator1510_panel_driver); - -MODULE_AUTHOR("Imre Deak"); -MODULE_DESCRIPTION("LCD panel support for the TI OMAP1510 Innovator board"); -MODULE_LICENSE("GPL"); diff --git a/drivers/video/fbdev/omap/lcd_inn1610.c b/drivers/video/fbdev/omap/lcd_inn1610.c deleted file mode 100644 index 901b28f35fab..000000000000 --- a/drivers/video/fbdev/omap/lcd_inn1610.c +++ /dev/null @@ -1,99 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * LCD panel support for the TI OMAP1610 Innovator board - * - * Copyright (C) 2004 Nokia Corporation - * Author: Imre Deak - */ - -#include -#include - -#include -#include "omapfb.h" - -#define MODULE_NAME "omapfb-lcd_h3" - -static int innovator1610_panel_init(struct lcd_panel *panel, - struct omapfb_device *fbdev) -{ - int r = 0; - - /* configure GPIO(14, 15) as outputs */ - if (gpio_request_one(14, GPIOF_OUT_INIT_LOW, "lcd_en0")) { - pr_err(MODULE_NAME ": can't request GPIO 14\n"); - r = -1; - goto exit; - } - if (gpio_request_one(15, GPIOF_OUT_INIT_LOW, "lcd_en1")) { - pr_err(MODULE_NAME ": can't request GPIO 15\n"); - gpio_free(14); - r = -1; - goto exit; - } -exit: - return r; -} - -static void innovator1610_panel_cleanup(struct lcd_panel *panel) -{ - gpio_free(15); - gpio_free(14); -} - -static int innovator1610_panel_enable(struct lcd_panel *panel) -{ - /* set GPIO14 and GPIO15 high */ - gpio_set_value(14, 1); - gpio_set_value(15, 1); - return 0; -} - -static void innovator1610_panel_disable(struct lcd_panel *panel) -{ - /* set GPIO13, GPIO14 and GPIO15 low */ - gpio_set_value(14, 0); - gpio_set_value(15, 0); -} - -static struct lcd_panel innovator1610_panel = { - .name = "inn1610", - .config = OMAP_LCDC_PANEL_TFT, - - .bpp = 16, - .data_lines = 16, - .x_res = 320, - .y_res = 240, - .pixel_clock = 12500, - .hsw = 40, - .hfp = 40, - .hbp = 72, - .vsw = 1, - .vfp = 1, - .vbp = 0, - .pcd = 12, - - .init = innovator1610_panel_init, - .cleanup = innovator1610_panel_cleanup, - .enable = innovator1610_panel_enable, - .disable = innovator1610_panel_disable, -}; - -static int innovator1610_panel_probe(struct platform_device *pdev) -{ - omapfb_register_panel(&innovator1610_panel); - return 0; -} - -static struct platform_driver innovator1610_panel_driver = { - .probe = innovator1610_panel_probe, - .driver = { - .name = "lcd_inn1610", - }, -}; - -module_platform_driver(innovator1610_panel_driver); - -MODULE_AUTHOR("Imre Deak"); -MODULE_DESCRIPTION("LCD panel support for the TI OMAP1610 Innovator board"); -MODULE_LICENSE("GPL"); diff --git a/drivers/video/fbdev/omap/lcd_palmtt.c b/drivers/video/fbdev/omap/lcd_palmtt.c deleted file mode 100644 index 703af0bc5c92..000000000000 --- a/drivers/video/fbdev/omap/lcd_palmtt.c +++ /dev/null @@ -1,65 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * LCD panel support for Palm Tungsten|T - * Current version : Marek Vasut - * - * Modified from lcd_inn1510.c - */ - -/* -GPIO11 - backlight -GPIO12 - screen blanking -GPIO13 - screen blanking -*/ - -#include -#include -#include -#include - -#include "omapfb.h" - -static unsigned long palmtt_panel_get_caps(struct lcd_panel *panel) -{ - return OMAPFB_CAPS_SET_BACKLIGHT; -} - -static struct lcd_panel palmtt_panel = { - .name = "palmtt", - .config = OMAP_LCDC_PANEL_TFT | OMAP_LCDC_INV_VSYNC | - OMAP_LCDC_INV_HSYNC | OMAP_LCDC_HSVS_RISING_EDGE | - OMAP_LCDC_HSVS_OPPOSITE, - .bpp = 16, - .data_lines = 16, - .x_res = 320, - .y_res = 320, - .pixel_clock = 10000, - .hsw = 4, - .hfp = 8, - .hbp = 28, - .vsw = 1, - .vfp = 8, - .vbp = 7, - .pcd = 0, - - .get_caps = palmtt_panel_get_caps, -}; - -static int palmtt_panel_probe(struct platform_device *pdev) -{ - omapfb_register_panel(&palmtt_panel); - return 0; -} - -static struct platform_driver palmtt_panel_driver = { - .probe = palmtt_panel_probe, - .driver = { - .name = "lcd_palmtt", - }, -}; - -module_platform_driver(palmtt_panel_driver); - -MODULE_AUTHOR("Marek Vasut "); -MODULE_DESCRIPTION("LCD panel support for Palm Tungsten|T"); -MODULE_LICENSE("GPL"); diff --git a/drivers/video/fbdev/omap/lcd_palmz71.c b/drivers/video/fbdev/omap/lcd_palmz71.c deleted file mode 100644 index a955c908ab14..000000000000 --- a/drivers/video/fbdev/omap/lcd_palmz71.c +++ /dev/null @@ -1,59 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * LCD panel support for the Palm Zire71 - * - * Original version : Romain Goyet - * Current version : Laurent Gonzalez - * Modified for zire71 : Marek Vasut - */ - -#include -#include -#include - -#include "omapfb.h" - -static unsigned long palmz71_panel_get_caps(struct lcd_panel *panel) -{ - return OMAPFB_CAPS_SET_BACKLIGHT; -} - -static struct lcd_panel palmz71_panel = { - .name = "palmz71", - .config = OMAP_LCDC_PANEL_TFT | OMAP_LCDC_INV_VSYNC | - OMAP_LCDC_INV_HSYNC | OMAP_LCDC_HSVS_RISING_EDGE | - OMAP_LCDC_HSVS_OPPOSITE, - .data_lines = 16, - .bpp = 16, - .pixel_clock = 24000, - .x_res = 320, - .y_res = 320, - .hsw = 4, - .hfp = 8, - .hbp = 28, - .vsw = 1, - .vfp = 8, - .vbp = 7, - .pcd = 0, - - .get_caps = palmz71_panel_get_caps, -}; - -static int palmz71_panel_probe(struct platform_device *pdev) -{ - omapfb_register_panel(&palmz71_panel); - return 0; -} - -static struct platform_driver palmz71_panel_driver = { - .probe = palmz71_panel_probe, - .driver = { - .name = "lcd_palmz71", - }, -}; - -module_platform_driver(palmz71_panel_driver); - -MODULE_AUTHOR("Romain Goyet, Laurent Gonzalez, Marek Vasut"); -MODULE_LICENSE("GPL"); -MODULE_DESCRIPTION("LCD panel support for the Palm Zire71"); From patchwork Wed Oct 19 15:03:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnd Bergmann X-Patchwork-Id: 5697 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp394823wrs; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id s3-20020a17090699c300b0078e254ae43fsi15526306ejn.787.2022.10.19.08.41.28; Wed, 19 Oct 2022 08:41:54 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=T0ACXHia; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230082AbiJSP3y (ORCPT + 99 others); Wed, 19 Oct 2022 11:29:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43034 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232596AbiJSP3N (ORCPT ); Wed, 19 Oct 2022 11:29:13 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 197722EF0E; Wed, 19 Oct 2022 08:21:31 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 0112C6183B; Wed, 19 Oct 2022 15:21:05 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 14141C433D6; Wed, 19 Oct 2022 15:21:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1666192864; bh=yWpP5rcBA/V4zM+3Kf0SHoYs8NLhaoSKrOLcnNumx0U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=T0ACXHiaI0xSYoHeg+S7sBaOQxPRtEET+I/nq8S1ezrUd673bqnwW1by0S6xIrMIV H9gDsPGfuGmTFQxDoISfFprnOo3nNljHFz7Cdzr9kZcQEFUEwQ+0SqfFk6cggqxq0b Y/Iz8gioR1ELb4f1YbT+QaZ5gpNRdhGy8aPd+O3PALJSiD8GEZUe21LvPIGNBjdqpB R7Mct+diTuhDEVdZYsZI659jTIq+S6Nq81p5xCxicY89GqNXhM7B8jz0XG4pbf1+2U JIFYnTPgFXnmJCSU6xIsEOHCeBZIgy3LJt8IyL6xbKN6qGoVbumE1DIvPRvXVtiD56 uhr00kvUiZc3Q== From: Arnd Bergmann To: linux-arm-kernel@lists.infradead.org, Mark Brown Cc: linux-kernel@vger.kernel.org, Arnd Bergmann , Aaro Koskinen , Janusz Krzysztofik , Tony Lindgren , linux-omap@vger.kernel.org, Cory Maccarrone , Fabrice Crohas , linux-spi@vger.kernel.org Subject: [PATCH 16/17] spi: remove omap 100K driver Date: Wed, 19 Oct 2022 17:03:38 +0200 Message-Id: <20221019150410.3851944-16-arnd@kernel.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20221019150410.3851944-1-arnd@kernel.org> References: <20221019144119.3848027-1-arnd@kernel.org> <20221019150410.3851944-1-arnd@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747131159797404176?= X-GMAIL-MSGID: =?utf-8?q?1747131159797404176?= From: Arnd Bergmann The OMAP7xx/OMAP8xx support was removed since all of its boards have no remaining users. Remove its spi driver as well. Cc: Aaro Koskinen Cc: Janusz Krzysztofik Cc: Tony Lindgren Cc: linux-omap@vger.kernel.org Cc: Cory Maccarrone Cc: Fabrice Crohas Signed-off-by: Arnd Bergmann Acked-by: Mark Brown Acked-by: Tony Lindgren --- drivers/spi/Kconfig | 6 - drivers/spi/Makefile | 1 - drivers/spi/spi-omap-100k.c | 490 ------------------------------------ 3 files changed, 497 deletions(-) delete mode 100644 drivers/spi/spi-omap-100k.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index d1bb62f7368b..bf0dc704abbe 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -697,12 +697,6 @@ config SPI_TI_QSPI This device supports single, dual and quad read support, while it only supports single write mode. -config SPI_OMAP_100K - tristate "OMAP SPI 100K" - depends on ARCH_OMAP850 || ARCH_OMAP730 || COMPILE_TEST - help - OMAP SPI 100K master controller for omap7xx boards. - config SPI_ORION tristate "Orion SPI master" depends on PLAT_ORION || ARCH_MVEBU || COMPILE_TEST diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 4b34e855c841..ae5ba0109d4b 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -90,7 +90,6 @@ obj-$(CONFIG_SPI_OC_TINY) += spi-oc-tiny.o spi-octeon-objs := spi-cavium.o spi-cavium-octeon.o obj-$(CONFIG_SPI_OCTEON) += spi-octeon.o obj-$(CONFIG_SPI_OMAP_UWIRE) += spi-omap-uwire.o -obj-$(CONFIG_SPI_OMAP_100K) += spi-omap-100k.o obj-$(CONFIG_SPI_OMAP24XX) += spi-omap2-mcspi.o obj-$(CONFIG_SPI_TI_QSPI) += spi-ti-qspi.o obj-$(CONFIG_SPI_ORION) += spi-orion.o diff --git a/drivers/spi/spi-omap-100k.c b/drivers/spi/spi-omap-100k.c deleted file mode 100644 index 061f7394e5b9..000000000000 --- a/drivers/spi/spi-omap-100k.c +++ /dev/null @@ -1,490 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * OMAP7xx SPI 100k controller driver - * Author: Fabrice Crohas - * from original omap1_mcspi driver - * - * Copyright (C) 2005, 2006 Nokia Corporation - * Author: Samuel Ortiz and - * Juha Yrjola - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#define OMAP1_SPI100K_MAX_FREQ 48000000 - -#define ICR_SPITAS (OMAP7XX_ICR_BASE + 0x12) - -#define SPI_SETUP1 0x00 -#define SPI_SETUP2 0x02 -#define SPI_CTRL 0x04 -#define SPI_STATUS 0x06 -#define SPI_TX_LSB 0x08 -#define SPI_TX_MSB 0x0a -#define SPI_RX_LSB 0x0c -#define SPI_RX_MSB 0x0e - -#define SPI_SETUP1_INT_READ_ENABLE (1UL << 5) -#define SPI_SETUP1_INT_WRITE_ENABLE (1UL << 4) -#define SPI_SETUP1_CLOCK_DIVISOR(x) ((x) << 1) -#define SPI_SETUP1_CLOCK_ENABLE (1UL << 0) - -#define SPI_SETUP2_ACTIVE_EDGE_FALLING (0UL << 0) -#define SPI_SETUP2_ACTIVE_EDGE_RISING (1UL << 0) -#define SPI_SETUP2_NEGATIVE_LEVEL (0UL << 5) -#define SPI_SETUP2_POSITIVE_LEVEL (1UL << 5) -#define SPI_SETUP2_LEVEL_TRIGGER (0UL << 10) -#define SPI_SETUP2_EDGE_TRIGGER (1UL << 10) - -#define SPI_CTRL_SEN(x) ((x) << 7) -#define SPI_CTRL_WORD_SIZE(x) (((x) - 1) << 2) -#define SPI_CTRL_WR (1UL << 1) -#define SPI_CTRL_RD (1UL << 0) - -#define SPI_STATUS_WE (1UL << 1) -#define SPI_STATUS_RD (1UL << 0) - -/* use PIO for small transfers, avoiding DMA setup/teardown overhead and - * cache operations; better heuristics consider wordsize and bitrate. - */ -#define DMA_MIN_BYTES 8 - -#define SPI_RUNNING 0 -#define SPI_SHUTDOWN 1 - -struct omap1_spi100k { - struct clk *ick; - struct clk *fck; - - /* Virtual base address of the controller */ - void __iomem *base; -}; - -struct omap1_spi100k_cs { - void __iomem *base; - int word_len; -}; - -static void spi100k_enable_clock(struct spi_master *master) -{ - unsigned int val; - struct omap1_spi100k *spi100k = spi_master_get_devdata(master); - - /* enable SPI */ - val = readw(spi100k->base + SPI_SETUP1); - val |= SPI_SETUP1_CLOCK_ENABLE; - writew(val, spi100k->base + SPI_SETUP1); -} - -static void spi100k_disable_clock(struct spi_master *master) -{ - unsigned int val; - struct omap1_spi100k *spi100k = spi_master_get_devdata(master); - - /* disable SPI */ - val = readw(spi100k->base + SPI_SETUP1); - val &= ~SPI_SETUP1_CLOCK_ENABLE; - writew(val, spi100k->base + SPI_SETUP1); -} - -static void spi100k_write_data(struct spi_master *master, int len, int data) -{ - struct omap1_spi100k *spi100k = spi_master_get_devdata(master); - - /* write 16-bit word, shifting 8-bit data if necessary */ - if (len <= 8) { - data <<= 8; - len = 16; - } - - spi100k_enable_clock(master); - writew(data, spi100k->base + SPI_TX_MSB); - - writew(SPI_CTRL_SEN(0) | - SPI_CTRL_WORD_SIZE(len) | - SPI_CTRL_WR, - spi100k->base + SPI_CTRL); - - /* Wait for bit ack send change */ - while ((readw(spi100k->base + SPI_STATUS) & SPI_STATUS_WE) != SPI_STATUS_WE) - ; - udelay(1000); - - spi100k_disable_clock(master); -} - -static int spi100k_read_data(struct spi_master *master, int len) -{ - int dataL; - struct omap1_spi100k *spi100k = spi_master_get_devdata(master); - - /* Always do at least 16 bits */ - if (len <= 8) - len = 16; - - spi100k_enable_clock(master); - writew(SPI_CTRL_SEN(0) | - SPI_CTRL_WORD_SIZE(len) | - SPI_CTRL_RD, - spi100k->base + SPI_CTRL); - - while ((readw(spi100k->base + SPI_STATUS) & SPI_STATUS_RD) != SPI_STATUS_RD) - ; - udelay(1000); - - dataL = readw(spi100k->base + SPI_RX_LSB); - readw(spi100k->base + SPI_RX_MSB); - spi100k_disable_clock(master); - - return dataL; -} - -static void spi100k_open(struct spi_master *master) -{ - /* get control of SPI */ - struct omap1_spi100k *spi100k = spi_master_get_devdata(master); - - writew(SPI_SETUP1_INT_READ_ENABLE | - SPI_SETUP1_INT_WRITE_ENABLE | - SPI_SETUP1_CLOCK_DIVISOR(0), spi100k->base + SPI_SETUP1); - - /* configure clock and interrupts */ - writew(SPI_SETUP2_ACTIVE_EDGE_FALLING | - SPI_SETUP2_NEGATIVE_LEVEL | - SPI_SETUP2_LEVEL_TRIGGER, spi100k->base + SPI_SETUP2); -} - -static void omap1_spi100k_force_cs(struct omap1_spi100k *spi100k, int enable) -{ - if (enable) - writew(0x05fc, spi100k->base + SPI_CTRL); - else - writew(0x05fd, spi100k->base + SPI_CTRL); -} - -static unsigned -omap1_spi100k_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer) -{ - struct omap1_spi100k_cs *cs = spi->controller_state; - unsigned int count, c; - int word_len; - - count = xfer->len; - c = count; - word_len = cs->word_len; - - if (word_len <= 8) { - u8 *rx; - const u8 *tx; - - rx = xfer->rx_buf; - tx = xfer->tx_buf; - do { - c -= 1; - if (xfer->tx_buf != NULL) - spi100k_write_data(spi->master, word_len, *tx++); - if (xfer->rx_buf != NULL) - *rx++ = spi100k_read_data(spi->master, word_len); - } while (c); - } else if (word_len <= 16) { - u16 *rx; - const u16 *tx; - - rx = xfer->rx_buf; - tx = xfer->tx_buf; - do { - c -= 2; - if (xfer->tx_buf != NULL) - spi100k_write_data(spi->master, word_len, *tx++); - if (xfer->rx_buf != NULL) - *rx++ = spi100k_read_data(spi->master, word_len); - } while (c); - } else if (word_len <= 32) { - u32 *rx; - const u32 *tx; - - rx = xfer->rx_buf; - tx = xfer->tx_buf; - do { - c -= 4; - if (xfer->tx_buf != NULL) - spi100k_write_data(spi->master, word_len, *tx); - if (xfer->rx_buf != NULL) - *rx = spi100k_read_data(spi->master, word_len); - } while (c); - } - return count - c; -} - -/* called only when no transfer is active to this device */ -static int omap1_spi100k_setup_transfer(struct spi_device *spi, - struct spi_transfer *t) -{ - struct omap1_spi100k *spi100k = spi_master_get_devdata(spi->master); - struct omap1_spi100k_cs *cs = spi->controller_state; - u8 word_len; - - if (t != NULL) - word_len = t->bits_per_word; - else - word_len = spi->bits_per_word; - - if (word_len > 32) - return -EINVAL; - cs->word_len = word_len; - - /* SPI init before transfer */ - writew(0x3e, spi100k->base + SPI_SETUP1); - writew(0x00, spi100k->base + SPI_STATUS); - writew(0x3e, spi100k->base + SPI_CTRL); - - return 0; -} - -/* the spi->mode bits understood by this driver: */ -#define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH) - -static int omap1_spi100k_setup(struct spi_device *spi) -{ - int ret; - struct omap1_spi100k *spi100k; - struct omap1_spi100k_cs *cs = spi->controller_state; - - spi100k = spi_master_get_devdata(spi->master); - - if (!cs) { - cs = devm_kzalloc(&spi->dev, sizeof(*cs), GFP_KERNEL); - if (!cs) - return -ENOMEM; - cs->base = spi100k->base + spi->chip_select * 0x14; - spi->controller_state = cs; - } - - spi100k_open(spi->master); - - clk_prepare_enable(spi100k->ick); - clk_prepare_enable(spi100k->fck); - - ret = omap1_spi100k_setup_transfer(spi, NULL); - - clk_disable_unprepare(spi100k->ick); - clk_disable_unprepare(spi100k->fck); - - return ret; -} - -static int omap1_spi100k_transfer_one_message(struct spi_master *master, - struct spi_message *m) -{ - struct omap1_spi100k *spi100k = spi_master_get_devdata(master); - struct spi_device *spi = m->spi; - struct spi_transfer *t = NULL; - int cs_active = 0; - int status = 0; - - list_for_each_entry(t, &m->transfers, transfer_list) { - if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) { - break; - } - status = omap1_spi100k_setup_transfer(spi, t); - if (status < 0) - break; - - if (!cs_active) { - omap1_spi100k_force_cs(spi100k, 1); - cs_active = 1; - } - - if (t->len) { - unsigned count; - - count = omap1_spi100k_txrx_pio(spi, t); - m->actual_length += count; - - if (count != t->len) { - break; - } - } - - spi_transfer_delay_exec(t); - - /* ignore the "leave it on after last xfer" hint */ - - if (t->cs_change) { - omap1_spi100k_force_cs(spi100k, 0); - cs_active = 0; - } - } - - status = omap1_spi100k_setup_transfer(spi, NULL); - - if (cs_active) - omap1_spi100k_force_cs(spi100k, 0); - - m->status = status; - - spi_finalize_current_message(master); - - return status; -} - -static int omap1_spi100k_probe(struct platform_device *pdev) -{ - struct spi_master *master; - struct omap1_spi100k *spi100k; - int status = 0; - - if (!pdev->id) - return -EINVAL; - - master = spi_alloc_master(&pdev->dev, sizeof(*spi100k)); - if (master == NULL) { - dev_dbg(&pdev->dev, "master allocation failed\n"); - return -ENOMEM; - } - - if (pdev->id != -1) - master->bus_num = pdev->id; - - master->setup = omap1_spi100k_setup; - master->transfer_one_message = omap1_spi100k_transfer_one_message; - master->num_chipselect = 2; - master->mode_bits = MODEBITS; - master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); - master->min_speed_hz = OMAP1_SPI100K_MAX_FREQ/(1<<16); - master->max_speed_hz = OMAP1_SPI100K_MAX_FREQ; - master->auto_runtime_pm = true; - - spi100k = spi_master_get_devdata(master); - - /* - * The memory region base address is taken as the platform_data. - * You should allocate this with ioremap() before initializing - * the SPI. - */ - spi100k->base = (void __iomem *)dev_get_platdata(&pdev->dev); - - spi100k->ick = devm_clk_get(&pdev->dev, "ick"); - if (IS_ERR(spi100k->ick)) { - dev_dbg(&pdev->dev, "can't get spi100k_ick\n"); - status = PTR_ERR(spi100k->ick); - goto err; - } - - spi100k->fck = devm_clk_get(&pdev->dev, "fck"); - if (IS_ERR(spi100k->fck)) { - dev_dbg(&pdev->dev, "can't get spi100k_fck\n"); - status = PTR_ERR(spi100k->fck); - goto err; - } - - status = clk_prepare_enable(spi100k->ick); - if (status != 0) { - dev_err(&pdev->dev, "failed to enable ick: %d\n", status); - goto err; - } - - status = clk_prepare_enable(spi100k->fck); - if (status != 0) { - dev_err(&pdev->dev, "failed to enable fck: %d\n", status); - goto err_ick; - } - - pm_runtime_enable(&pdev->dev); - pm_runtime_set_active(&pdev->dev); - - status = devm_spi_register_master(&pdev->dev, master); - if (status < 0) - goto err_fck; - - return status; - -err_fck: - pm_runtime_disable(&pdev->dev); - clk_disable_unprepare(spi100k->fck); -err_ick: - clk_disable_unprepare(spi100k->ick); -err: - spi_master_put(master); - return status; -} - -static int omap1_spi100k_remove(struct platform_device *pdev) -{ - struct spi_master *master = platform_get_drvdata(pdev); - struct omap1_spi100k *spi100k = spi_master_get_devdata(master); - - pm_runtime_disable(&pdev->dev); - - clk_disable_unprepare(spi100k->fck); - clk_disable_unprepare(spi100k->ick); - - return 0; -} - -#ifdef CONFIG_PM -static int omap1_spi100k_runtime_suspend(struct device *dev) -{ - struct spi_master *master = dev_get_drvdata(dev); - struct omap1_spi100k *spi100k = spi_master_get_devdata(master); - - clk_disable_unprepare(spi100k->ick); - clk_disable_unprepare(spi100k->fck); - - return 0; -} - -static int omap1_spi100k_runtime_resume(struct device *dev) -{ - struct spi_master *master = dev_get_drvdata(dev); - struct omap1_spi100k *spi100k = spi_master_get_devdata(master); - int ret; - - ret = clk_prepare_enable(spi100k->ick); - if (ret != 0) { - dev_err(dev, "Failed to enable ick: %d\n", ret); - return ret; - } - - ret = clk_prepare_enable(spi100k->fck); - if (ret != 0) { - dev_err(dev, "Failed to enable fck: %d\n", ret); - clk_disable_unprepare(spi100k->ick); - return ret; - } - - return 0; -} -#endif - -static const struct dev_pm_ops omap1_spi100k_pm = { - SET_RUNTIME_PM_OPS(omap1_spi100k_runtime_suspend, - omap1_spi100k_runtime_resume, NULL) -}; - -static struct platform_driver omap1_spi100k_driver = { - .driver = { - .name = "omap1_spi100k", - .pm = &omap1_spi100k_pm, - }, - .probe = omap1_spi100k_probe, - .remove = omap1_spi100k_remove, -}; - -module_platform_driver(omap1_spi100k_driver); - -MODULE_DESCRIPTION("OMAP7xx SPI 100k controller driver"); -MODULE_AUTHOR("Fabrice Crohas "); -MODULE_LICENSE("GPL"); From patchwork Wed Oct 19 15:03:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnd Bergmann X-Patchwork-Id: 5698 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp394838wrs; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id f20-20020a0564021e9400b0045cecdc1fbcsi16357913edf.9.2022.10.19.08.41.31; Wed, 19 Oct 2022 08:41:56 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=cosxhlVJ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232027AbiJSPaK (ORCPT + 99 others); Wed, 19 Oct 2022 11:30:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45408 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232797AbiJSP3i (ORCPT ); Wed, 19 Oct 2022 11:29:38 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CE38E106E16 for ; Wed, 19 Oct 2022 08:21:50 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 5310D6184B for ; Wed, 19 Oct 2022 15:21:42 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 71FACC433D7; Wed, 19 Oct 2022 15:21:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1666192901; bh=eR60voGgjZ0JfRrxHEMJQ06aOT1Y9tisHlHTWeTdtWU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cosxhlVJ3e1PjbvYh25SF7dLBjNOmA5czQCsC0BlfYfBczyi/5/yjSCnok+ax33+b 7LVcIvgDR98FWQzWi4Agdkb6YUKfSmwB+4YhGTcuU97zPzMxpozbK7HQY/z4p2OyFa e+AE0sPHrQF+b3USOTv9GYc6IzQ9B6ftlwiwOIBQrLQcBZs0CoamLxf6WJ/adZgJqw S77x+yd+BcPEKASdZiZkRvoDto8/mqspBKl7NYzmI8e1hLCm7BYvKUqOhs82IGkjvB C05c2nls5DBNU+6C4vXDYlWP+S+x9bXBa4ZfZULyrpyPMzsiqyOgoTVQ+X7iCtXUUj 3j6XeRNcCWsLg== From: Arnd Bergmann To: linux-arm-kernel@lists.infradead.org, Lee Jones Cc: linux-kernel@vger.kernel.org, Arnd Bergmann , Cory Maccarrone Subject: [PATCH 17/17] mfd: remove htc-i2cpld driver Date: Wed, 19 Oct 2022 17:03:39 +0200 Message-Id: <20221019150410.3851944-17-arnd@kernel.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20221019150410.3851944-1-arnd@kernel.org> References: <20221019144119.3848027-1-arnd@kernel.org> <20221019150410.3851944-1-arnd@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747131161885397797?= X-GMAIL-MSGID: =?utf-8?q?1747131161885397797?= From: Arnd Bergmann The HTC Herald machine was removed, so this driver is no longer used anywhere. Cc: Cory Maccarrone Signed-off-by: Arnd Bergmann --- drivers/mfd/Kconfig | 9 - drivers/mfd/Makefile | 1 - drivers/mfd/htc-i2cpld.c | 627 --------------------------------------- include/linux/htcpld.h | 23 -- 4 files changed, 660 deletions(-) delete mode 100644 drivers/mfd/htc-i2cpld.c delete mode 100644 include/linux/htcpld.h diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index c87aab27455f..11c3bd0bd669 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -547,15 +547,6 @@ config HTC_PASIC3 HTC Magician devices, respectively. Actual functionality is handled by the leds-pasic3 and ds1wm drivers. -config HTC_I2CPLD - bool "HTC I2C PLD chip support" - depends on I2C=y && GPIOLIB - help - If you say yes here you get support for the supposed CPLD - found on omap850 HTC devices like the HTC Wizard and HTC Herald. - This device provides input and output GPIOs through an I2C - interface to one or more sub-chips. - config MFD_INTEL_QUARK_I2C_GPIO tristate "Intel Quark MFD I2C GPIO" depends on PCI diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index 7ed3ef4a698c..d74bf111f88e 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -19,7 +19,6 @@ obj-$(CONFIG_MFD_EXYNOS_LPASS) += exynos-lpass.o obj-$(CONFIG_MFD_GATEWORKS_GSC) += gateworks-gsc.o obj-$(CONFIG_HTC_PASIC3) += htc-pasic3.o -obj-$(CONFIG_HTC_I2CPLD) += htc-i2cpld.o obj-$(CONFIG_MFD_TI_LP873X) += lp873x.o obj-$(CONFIG_MFD_TI_LP87565) += lp87565.o diff --git a/drivers/mfd/htc-i2cpld.c b/drivers/mfd/htc-i2cpld.c deleted file mode 100644 index b45b1346ab54..000000000000 --- a/drivers/mfd/htc-i2cpld.c +++ /dev/null @@ -1,627 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * htc-i2cpld.c - * Chip driver for an unknown CPLD chip found on omap850 HTC devices like - * the HTC Wizard and HTC Herald. - * The cpld is located on the i2c bus and acts as an input/output GPIO - * extender. - * - * Copyright (C) 2009 Cory Maccarrone - * - * Based on work done in the linwizard project - * Copyright (C) 2008-2009 Angelo Arrifano - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -struct htcpld_chip { - spinlock_t lock; - - /* chip info */ - u8 reset; - u8 addr; - struct device *dev; - struct i2c_client *client; - - /* Output details */ - u8 cache_out; - struct gpio_chip chip_out; - - /* Input details */ - u8 cache_in; - struct gpio_chip chip_in; - - u16 irqs_enabled; - uint irq_start; - int nirqs; - - unsigned int flow_type; - /* - * Work structure to allow for setting values outside of any - * possible interrupt context - */ - struct work_struct set_val_work; -}; - -struct htcpld_data { - /* irq info */ - u16 irqs_enabled; - uint irq_start; - int nirqs; - uint chained_irq; - struct gpio_desc *int_reset_gpio_hi; - struct gpio_desc *int_reset_gpio_lo; - - /* htcpld info */ - struct htcpld_chip *chip; - unsigned int nchips; -}; - -/* There does not appear to be a way to proactively mask interrupts - * on the htcpld chip itself. So, we simply ignore interrupts that - * aren't desired. */ -static void htcpld_mask(struct irq_data *data) -{ - struct htcpld_chip *chip = irq_data_get_irq_chip_data(data); - chip->irqs_enabled &= ~(1 << (data->irq - chip->irq_start)); - pr_debug("HTCPLD mask %d %04x\n", data->irq, chip->irqs_enabled); -} -static void htcpld_unmask(struct irq_data *data) -{ - struct htcpld_chip *chip = irq_data_get_irq_chip_data(data); - chip->irqs_enabled |= 1 << (data->irq - chip->irq_start); - pr_debug("HTCPLD unmask %d %04x\n", data->irq, chip->irqs_enabled); -} - -static int htcpld_set_type(struct irq_data *data, unsigned int flags) -{ - struct htcpld_chip *chip = irq_data_get_irq_chip_data(data); - - if (flags & ~IRQ_TYPE_SENSE_MASK) - return -EINVAL; - - /* We only allow edge triggering */ - if (flags & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)) - return -EINVAL; - - chip->flow_type = flags; - return 0; -} - -static struct irq_chip htcpld_muxed_chip = { - .name = "htcpld", - .irq_mask = htcpld_mask, - .irq_unmask = htcpld_unmask, - .irq_set_type = htcpld_set_type, -}; - -/* To properly dispatch IRQ events, we need to read from the - * chip. This is an I2C action that could possibly sleep - * (which is bad in interrupt context) -- so we use a threaded - * interrupt handler to get around that. - */ -static irqreturn_t htcpld_handler(int irq, void *dev) -{ - struct htcpld_data *htcpld = dev; - unsigned int i; - unsigned long flags; - int irqpin; - - if (!htcpld) { - pr_debug("htcpld is null in ISR\n"); - return IRQ_HANDLED; - } - - /* - * For each chip, do a read of the chip and trigger any interrupts - * desired. The interrupts will be triggered from LSB to MSB (i.e. - * bit 0 first, then bit 1, etc.) - * - * For chips that have no interrupt range specified, just skip 'em. - */ - for (i = 0; i < htcpld->nchips; i++) { - struct htcpld_chip *chip = &htcpld->chip[i]; - struct i2c_client *client; - int val; - unsigned long uval, old_val; - - if (!chip) { - pr_debug("chip %d is null in ISR\n", i); - continue; - } - - if (chip->nirqs == 0) - continue; - - client = chip->client; - if (!client) { - pr_debug("client %d is null in ISR\n", i); - continue; - } - - /* Scan the chip */ - val = i2c_smbus_read_byte_data(client, chip->cache_out); - if (val < 0) { - /* Throw a warning and skip this chip */ - dev_warn(chip->dev, "Unable to read from chip: %d\n", - val); - continue; - } - - uval = (unsigned long)val; - - spin_lock_irqsave(&chip->lock, flags); - - /* Save away the old value so we can compare it */ - old_val = chip->cache_in; - - /* Write the new value */ - chip->cache_in = uval; - - spin_unlock_irqrestore(&chip->lock, flags); - - /* - * For each bit in the data (starting at bit 0), trigger - * associated interrupts. - */ - for (irqpin = 0; irqpin < chip->nirqs; irqpin++) { - unsigned oldb, newb, type = chip->flow_type; - - irq = chip->irq_start + irqpin; - - /* Run the IRQ handler, but only if the bit value - * changed, and the proper flags are set */ - oldb = (old_val >> irqpin) & 1; - newb = (uval >> irqpin) & 1; - - if ((!oldb && newb && (type & IRQ_TYPE_EDGE_RISING)) || - (oldb && !newb && (type & IRQ_TYPE_EDGE_FALLING))) { - pr_debug("fire IRQ %d\n", irqpin); - generic_handle_irq(irq); - } - } - } - - /* - * In order to continue receiving interrupts, the int_reset_gpio must - * be asserted. - */ - if (htcpld->int_reset_gpio_hi) - gpiod_set_value(htcpld->int_reset_gpio_hi, 1); - if (htcpld->int_reset_gpio_lo) - gpiod_set_value(htcpld->int_reset_gpio_lo, 0); - - return IRQ_HANDLED; -} - -/* - * The GPIO set routines can be called from interrupt context, especially if, - * for example they're attached to the led-gpio framework and a trigger is - * enabled. As such, we declared work above in the htcpld_chip structure, - * and that work is scheduled in the set routine. The kernel can then run - * the I2C functions, which will sleep, in process context. - */ -static void htcpld_chip_set(struct gpio_chip *chip, unsigned offset, int val) -{ - struct i2c_client *client; - struct htcpld_chip *chip_data = gpiochip_get_data(chip); - unsigned long flags; - - client = chip_data->client; - if (!client) - return; - - spin_lock_irqsave(&chip_data->lock, flags); - if (val) - chip_data->cache_out |= (1 << offset); - else - chip_data->cache_out &= ~(1 << offset); - spin_unlock_irqrestore(&chip_data->lock, flags); - - schedule_work(&(chip_data->set_val_work)); -} - -static void htcpld_chip_set_ni(struct work_struct *work) -{ - struct htcpld_chip *chip_data; - struct i2c_client *client; - - chip_data = container_of(work, struct htcpld_chip, set_val_work); - client = chip_data->client; - i2c_smbus_read_byte_data(client, chip_data->cache_out); -} - -static int htcpld_chip_get(struct gpio_chip *chip, unsigned offset) -{ - struct htcpld_chip *chip_data = gpiochip_get_data(chip); - u8 cache; - - if (!strncmp(chip->label, "htcpld-out", 10)) { - cache = chip_data->cache_out; - } else if (!strncmp(chip->label, "htcpld-in", 9)) { - cache = chip_data->cache_in; - } else - return -EINVAL; - - return (cache >> offset) & 1; -} - -static int htcpld_direction_output(struct gpio_chip *chip, - unsigned offset, int value) -{ - htcpld_chip_set(chip, offset, value); - return 0; -} - -static int htcpld_direction_input(struct gpio_chip *chip, - unsigned offset) -{ - /* - * No-op: this function can only be called on the input chip. - * We do however make sure the offset is within range. - */ - return (offset < chip->ngpio) ? 0 : -EINVAL; -} - -static int htcpld_chip_to_irq(struct gpio_chip *chip, unsigned offset) -{ - struct htcpld_chip *chip_data = gpiochip_get_data(chip); - - if (offset < chip_data->nirqs) - return chip_data->irq_start + offset; - else - return -EINVAL; -} - -static void htcpld_chip_reset(struct i2c_client *client) -{ - struct htcpld_chip *chip_data = i2c_get_clientdata(client); - if (!chip_data) - return; - - i2c_smbus_read_byte_data( - client, (chip_data->cache_out = chip_data->reset)); -} - -static int htcpld_setup_chip_irq( - struct platform_device *pdev, - int chip_index) -{ - struct htcpld_data *htcpld; - struct htcpld_chip *chip; - unsigned int irq, irq_end; - - /* Get the platform and driver data */ - htcpld = platform_get_drvdata(pdev); - chip = &htcpld->chip[chip_index]; - - /* Setup irq handlers */ - irq_end = chip->irq_start + chip->nirqs; - for (irq = chip->irq_start; irq < irq_end; irq++) { - irq_set_chip_and_handler(irq, &htcpld_muxed_chip, - handle_simple_irq); - irq_set_chip_data(irq, chip); - irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE); - } - - return 0; -} - -static int htcpld_register_chip_i2c( - struct platform_device *pdev, - int chip_index) -{ - struct htcpld_data *htcpld; - struct device *dev = &pdev->dev; - struct htcpld_core_platform_data *pdata; - struct htcpld_chip *chip; - struct htcpld_chip_platform_data *plat_chip_data; - struct i2c_adapter *adapter; - struct i2c_client *client; - struct i2c_board_info info; - - /* Get the platform and driver data */ - pdata = dev_get_platdata(dev); - htcpld = platform_get_drvdata(pdev); - chip = &htcpld->chip[chip_index]; - plat_chip_data = &pdata->chip[chip_index]; - - adapter = i2c_get_adapter(pdata->i2c_adapter_id); - if (!adapter) { - /* Eek, no such I2C adapter! Bail out. */ - dev_warn(dev, "Chip at i2c address 0x%x: Invalid i2c adapter %d\n", - plat_chip_data->addr, pdata->i2c_adapter_id); - return -ENODEV; - } - - if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_READ_BYTE_DATA)) { - dev_warn(dev, "i2c adapter %d non-functional\n", - pdata->i2c_adapter_id); - i2c_put_adapter(adapter); - return -EINVAL; - } - - memset(&info, 0, sizeof(struct i2c_board_info)); - info.addr = plat_chip_data->addr; - strscpy(info.type, "htcpld-chip", I2C_NAME_SIZE); - info.platform_data = chip; - - /* Add the I2C device. This calls the probe() function. */ - client = i2c_new_client_device(adapter, &info); - if (IS_ERR(client)) { - /* I2C device registration failed, contineu with the next */ - dev_warn(dev, "Unable to add I2C device for 0x%x\n", - plat_chip_data->addr); - i2c_put_adapter(adapter); - return PTR_ERR(client); - } - - i2c_set_clientdata(client, chip); - snprintf(client->name, I2C_NAME_SIZE, "Chip_0x%x", client->addr); - chip->client = client; - - /* Reset the chip */ - htcpld_chip_reset(client); - chip->cache_in = i2c_smbus_read_byte_data(client, chip->cache_out); - - return 0; -} - -static void htcpld_unregister_chip_i2c( - struct platform_device *pdev, - int chip_index) -{ - struct htcpld_data *htcpld; - struct htcpld_chip *chip; - - /* Get the platform and driver data */ - htcpld = platform_get_drvdata(pdev); - chip = &htcpld->chip[chip_index]; - - i2c_unregister_device(chip->client); -} - -static int htcpld_register_chip_gpio( - struct platform_device *pdev, - int chip_index) -{ - struct htcpld_data *htcpld; - struct device *dev = &pdev->dev; - struct htcpld_core_platform_data *pdata; - struct htcpld_chip *chip; - struct htcpld_chip_platform_data *plat_chip_data; - struct gpio_chip *gpio_chip; - int ret = 0; - - /* Get the platform and driver data */ - pdata = dev_get_platdata(dev); - htcpld = platform_get_drvdata(pdev); - chip = &htcpld->chip[chip_index]; - plat_chip_data = &pdata->chip[chip_index]; - - /* Setup the GPIO chips */ - gpio_chip = &(chip->chip_out); - gpio_chip->label = "htcpld-out"; - gpio_chip->parent = dev; - gpio_chip->owner = THIS_MODULE; - gpio_chip->get = htcpld_chip_get; - gpio_chip->set = htcpld_chip_set; - gpio_chip->direction_input = NULL; - gpio_chip->direction_output = htcpld_direction_output; - gpio_chip->base = plat_chip_data->gpio_out_base; - gpio_chip->ngpio = plat_chip_data->num_gpios; - - gpio_chip = &(chip->chip_in); - gpio_chip->label = "htcpld-in"; - gpio_chip->parent = dev; - gpio_chip->owner = THIS_MODULE; - gpio_chip->get = htcpld_chip_get; - gpio_chip->set = NULL; - gpio_chip->direction_input = htcpld_direction_input; - gpio_chip->direction_output = NULL; - gpio_chip->to_irq = htcpld_chip_to_irq; - gpio_chip->base = plat_chip_data->gpio_in_base; - gpio_chip->ngpio = plat_chip_data->num_gpios; - - /* Add the GPIO chips */ - ret = gpiochip_add_data(&(chip->chip_out), chip); - if (ret) { - dev_warn(dev, "Unable to register output GPIOs for 0x%x: %d\n", - plat_chip_data->addr, ret); - return ret; - } - - ret = gpiochip_add_data(&(chip->chip_in), chip); - if (ret) { - dev_warn(dev, "Unable to register input GPIOs for 0x%x: %d\n", - plat_chip_data->addr, ret); - gpiochip_remove(&(chip->chip_out)); - return ret; - } - - return 0; -} - -static int htcpld_setup_chips(struct platform_device *pdev) -{ - struct htcpld_data *htcpld; - struct device *dev = &pdev->dev; - struct htcpld_core_platform_data *pdata; - int i; - - /* Get the platform and driver data */ - pdata = dev_get_platdata(dev); - htcpld = platform_get_drvdata(pdev); - - /* Setup each chip's output GPIOs */ - htcpld->nchips = pdata->num_chip; - htcpld->chip = devm_kcalloc(dev, - htcpld->nchips, - sizeof(struct htcpld_chip), - GFP_KERNEL); - if (!htcpld->chip) - return -ENOMEM; - - /* Add the chips as best we can */ - for (i = 0; i < htcpld->nchips; i++) { - int ret; - - /* Setup the HTCPLD chips */ - htcpld->chip[i].reset = pdata->chip[i].reset; - htcpld->chip[i].cache_out = pdata->chip[i].reset; - htcpld->chip[i].cache_in = 0; - htcpld->chip[i].dev = dev; - htcpld->chip[i].irq_start = pdata->chip[i].irq_base; - htcpld->chip[i].nirqs = pdata->chip[i].num_irqs; - - INIT_WORK(&(htcpld->chip[i].set_val_work), &htcpld_chip_set_ni); - spin_lock_init(&(htcpld->chip[i].lock)); - - /* Setup the interrupts for the chip */ - if (htcpld->chained_irq) { - ret = htcpld_setup_chip_irq(pdev, i); - if (ret) - continue; - } - - /* Register the chip with I2C */ - ret = htcpld_register_chip_i2c(pdev, i); - if (ret) - continue; - - - /* Register the chips with the GPIO subsystem */ - ret = htcpld_register_chip_gpio(pdev, i); - if (ret) { - /* Unregister the chip from i2c and continue */ - htcpld_unregister_chip_i2c(pdev, i); - continue; - } - - dev_info(dev, "Registered chip at 0x%x\n", pdata->chip[i].addr); - } - - return 0; -} - -static int htcpld_core_probe(struct platform_device *pdev) -{ - struct htcpld_data *htcpld; - struct device *dev = &pdev->dev; - struct htcpld_core_platform_data *pdata; - struct resource *res; - int ret = 0; - - if (!dev) - return -ENODEV; - - pdata = dev_get_platdata(dev); - if (!pdata) { - dev_warn(dev, "Platform data not found for htcpld core!\n"); - return -ENXIO; - } - - htcpld = devm_kzalloc(dev, sizeof(struct htcpld_data), GFP_KERNEL); - if (!htcpld) - return -ENOMEM; - - /* Find chained irq */ - res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); - if (res) { - int flags; - htcpld->chained_irq = res->start; - - /* Setup the chained interrupt handler */ - flags = IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING | - IRQF_ONESHOT; - ret = request_threaded_irq(htcpld->chained_irq, - NULL, htcpld_handler, - flags, pdev->name, htcpld); - if (ret) { - dev_warn(dev, "Unable to setup chained irq handler: %d\n", ret); - return ret; - } else - device_init_wakeup(dev, 0); - } - - /* Set the driver data */ - platform_set_drvdata(pdev, htcpld); - - /* Setup the htcpld chips */ - ret = htcpld_setup_chips(pdev); - if (ret) - return ret; - - /* Request the GPIO(s) for the int reset and set them up */ - htcpld->int_reset_gpio_hi = gpiochip_request_own_desc(&htcpld->chip[2].chip_out, - 7, "htcpld-core", GPIO_ACTIVE_HIGH, - GPIOD_OUT_HIGH); - if (IS_ERR(htcpld->int_reset_gpio_hi)) { - /* - * If it failed, that sucks, but we can probably - * continue on without it. - */ - htcpld->int_reset_gpio_hi = NULL; - dev_warn(dev, "Unable to request int_reset_gpio_hi -- interrupts may not work\n"); - } - - htcpld->int_reset_gpio_lo = gpiochip_request_own_desc(&htcpld->chip[2].chip_out, - 0, "htcpld-core", GPIO_ACTIVE_HIGH, - GPIOD_OUT_LOW); - if (IS_ERR(htcpld->int_reset_gpio_lo)) { - /* - * If it failed, that sucks, but we can probably - * continue on without it. - */ - htcpld->int_reset_gpio_lo = NULL; - dev_warn(dev, "Unable to request int_reset_gpio_lo -- interrupts may not work\n"); - } - - dev_info(dev, "Initialized successfully\n"); - return 0; -} - -/* The I2C Driver -- used internally */ -static const struct i2c_device_id htcpld_chip_id[] = { - { "htcpld-chip", 0 }, - { } -}; - -static struct i2c_driver htcpld_chip_driver = { - .driver = { - .name = "htcpld-chip", - }, - .id_table = htcpld_chip_id, -}; - -/* The Core Driver */ -static struct platform_driver htcpld_core_driver = { - .driver = { - .name = "i2c-htcpld", - }, -}; - -static int __init htcpld_core_init(void) -{ - int ret; - - /* Register the I2C Chip driver */ - ret = i2c_add_driver(&htcpld_chip_driver); - if (ret) - return ret; - - /* Probe for our chips */ - return platform_driver_probe(&htcpld_core_driver, htcpld_core_probe); -} -device_initcall(htcpld_core_init); diff --git a/include/linux/htcpld.h b/include/linux/htcpld.h deleted file mode 100644 index 5f8ac9b1d724..000000000000 --- a/include/linux/htcpld.h +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __LINUX_HTCPLD_H -#define __LINUX_HTCPLD_H - -struct htcpld_chip_platform_data { - unsigned int addr; - unsigned int reset; - unsigned int num_gpios; - unsigned int gpio_out_base; - unsigned int gpio_in_base; - unsigned int irq_base; - unsigned int num_irqs; -}; - -struct htcpld_core_platform_data { - unsigned int i2c_adapter_id; - - struct htcpld_chip_platform_data *chip; - unsigned int num_chip; -}; - -#endif /* __LINUX_HTCPLD_H */ -