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[83.9.29.16]) by smtp.gmail.com with ESMTPSA id u28-20020ac243dc000000b004db2978e330sm1194222lfl.258.2023.03.16.04.17.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Mar 2023 04:17:08 -0700 (PDT) From: Konrad Dybcio Date: Thu, 16 Mar 2023 12:16:56 +0100 Subject: [PATCH 1/5] dt-bindings: clock: qcom,gpucc: Fix SM6350 clock names MIME-Version: 1.0 Message-Id: <20230315-topic-lagoon_gpu-v1-1-a74cbec4ecfc@linaro.org> References: <20230315-topic-lagoon_gpu-v1-0-a74cbec4ecfc@linaro.org> In-Reply-To: <20230315-topic-lagoon_gpu-v1-0-a74cbec4ecfc@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , AngeloGioacchino Del Regno Cc: Marijn Suijten , Rob Herring , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1678965426; l=1659; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=bpaAXA5y4g96VwCAJK9chz5FYE16LKwf+GCJo/Dh+04=; b=Jild5AY0GLW3IlK/0sO5nZu7MvhQrlDmN5ABPy6VIRbq5sH0zdDzJyWVgYFZkV1dqSaHbcjDa8ah 60eKja2ND5+/d/+W42zSyRGM0uDlHxgiIq4CiB4Jr8+5kd3WG32y X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-0.2 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_SORBS_HTTP,RCVD_IN_SORBS_SOCKS,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1760523318363366118?= X-GMAIL-MSGID: =?utf-8?q?1760523318363366118?= SM6350 GPUCC uses the same clock names as the rest of the gang, except without a _src suffix. Account for that. Fixes: 7b91b9d8cc6c ("dt-bindings: clock: add SM6350 QCOM Graphics clock bindings") Signed-off-by: Konrad Dybcio --- .../devicetree/bindings/clock/qcom,gpucc.yaml | 29 +++++++++++++++++++--- 1 file changed, 25 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml index db53eb288995..d209060a619d 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml @@ -43,10 +43,8 @@ properties: - description: GPLL0 div branch source clock-names: - items: - - const: bi_tcxo - - const: gcc_gpu_gpll0_clk_src - - const: gcc_gpu_gpll0_div_clk_src + minItems: 3 + maxItems: 3 '#clock-cells': const: 1 @@ -71,6 +69,29 @@ required: additionalProperties: false +allOf: + - if: + properties: + compatible: + items: + - const: qcom,sm6350-gpucc + + then: + properties: + clock-names: + items: + - const: bi_tcxo + - const: gcc_gpu_gpll0_clk + - const: gcc_gpu_gpll0_div_clk + + else: + properties: + clock-names: + items: + - const: bi_tcxo + - const: gcc_gpu_gpll0_clk_src + - const: gcc_gpu_gpll0_div_clk_src + examples: - | #include From patchwork Thu Mar 16 11:16:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 70739 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:604a:0:0:0:0:0 with SMTP id j10csp423364wrt; Thu, 16 Mar 2023 04:23:47 -0700 (PDT) X-Google-Smtp-Source: AK7set9buG4gczD521gRBe+rnfr9xiLMgi4hV3+nYCpZbMBNcus5mptcjPkqOmaV4wmnnmLzTjTz X-Received: by 2002:a17:903:2945:b0:1a0:53f3:3762 with SMTP id li5-20020a170903294500b001a053f33762mr2641165plb.46.1678965827477; Thu, 16 Mar 2023 04:23:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1678965827; cv=none; d=google.com; s=arc-20160816; b=zYfcYtAxWz2QFDhEsM0CWZ63jGuFg/sEJOE/9yyriDyu4baYFiWqZ4oHoiraUR/Bed FNoEIetmEmlW35dPVmnCaG45DYTxK0fSgvKequ/KwllFdfDIJ0e2iIqYO6DS0zj+OYKW ubaxUZ0t8U+GiHEmfvrvbwC+K3xQ0TcNjk1OlU/27wLRlg2K43Aew3VCpO7kE2F10moM psqBRTgN3AGC2gOUVnnWcf3YvYnmlVVkh/qhjyzZzPXLV1e0PlJyT3nQFCd1o7t2NIeJ F8XMa4myoJPgDDQDqGjFUspsUea6zFF1FsQkzU6vz7IDYEWoPj6Ui/bLKr2+30VwArm5 CL7Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=CX609/y3ZMkfT05ayA/5Q69Y3P8LNbyWbrmOTe8ZxUo=; b=mlqk6HEehS6L0PAcTYHWv8vEGBUQ3VYg5rj61Dx78MPpLUek0yN2+bBLLZJ3uMZlWY zjS+f3qntsrKqTMF6JgTrGpWdt3HeyXGgv8diIjZLRqyqbf0BrY16tcW4i8aofRi1qOn foQoBDyYhSBW4Z8tACesHcQ/7sDTqVx+Rk1M4OZVAq0s47pxDXBR3BxbpOY5LZguRoJ6 8u3e7wd+r0byl2g83EYcdvtj47/oAApHFvTcuV3OLKSSg6Dh2LpYiKQN07wOJ2MChAMg bT1guo+ulDOlRmIgoilGP3cuRn7njJeZkREeYQrFr81f1spI6Jjbm1V0qDNhWbFWfitW 6oNg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Ryk34bDd; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[83.9.29.16]) by smtp.gmail.com with ESMTPSA id u28-20020ac243dc000000b004db2978e330sm1194222lfl.258.2023.03.16.04.17.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Mar 2023 04:17:10 -0700 (PDT) From: Konrad Dybcio Date: Thu, 16 Mar 2023 12:16:57 +0100 Subject: [PATCH 2/5] arm64: dts: qcom: sm6350: Add GPUCC node MIME-Version: 1.0 Message-Id: <20230315-topic-lagoon_gpu-v1-2-a74cbec4ecfc@linaro.org> References: <20230315-topic-lagoon_gpu-v1-0-a74cbec4ecfc@linaro.org> In-Reply-To: <20230315-topic-lagoon_gpu-v1-0-a74cbec4ecfc@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , AngeloGioacchino Del Regno Cc: Marijn Suijten , Rob Herring , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , Konrad Dybcio X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1678965426; l=1355; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=T20D47wMamblhuymG4piRjU7EdKqlSdzz5tYbFiNa2w=; b=qHCpq8IzdrchOe9Nka2ARSw2XI8dsUnV0vG4qZ9B79vhLm1Y2OdA9GLcppgj/Ea2IjD8mSL68RjO NGIm8Kc7DgxE3QNAfwdeVvpcUpRPCVwsth7JCOHBK1UYKKIjtmry X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-0.2 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_SORBS_HTTP,RCVD_IN_SORBS_SOCKS,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1760523271267249344?= X-GMAIL-MSGID: =?utf-8?q?1760523271267249344?= From: Konrad Dybcio Add and configure a node for the GPU clock controller. Signed-off-by: Konrad Dybcio Signed-off-by: Konrad Dybcio Reviewed-by: Luca Weiss --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index c46bb6dab6a1..523c7edfa4b3 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -5,6 +5,7 @@ */ #include +#include #include #include #include @@ -1125,6 +1126,20 @@ compute-cb@5 { }; }; + gpucc: clock-controller@3d90000 { + compatible = "qcom,sm6350-gpucc"; + reg = <0 0x03d90000 0 0x9000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK>, + <&gcc GCC_GPU_GPLL0_DIV_CLK>; + clock-names = "bi_tcxo", + "gcc_gpu_gpll0_clk", + "gcc_gpu_gpll0_div_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + mpss: remoteproc@4080000 { compatible = "qcom,sm6350-mpss-pas"; reg = <0x0 0x04080000 0x0 0x4040>; From patchwork Thu Mar 16 11:16:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 70741 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:604a:0:0:0:0:0 with SMTP id j10csp424283wrt; Thu, 16 Mar 2023 04:26:12 -0700 (PDT) X-Google-Smtp-Source: AK7set/mGMhBs0w+JdbcZztRXJxJz+z/ucI9rXSDdE8jw21QLDU5mZk3sHAncc1fDJzPpX50xBil X-Received: by 2002:a17:903:705:b0:19c:a5dd:fadb with SMTP id kk5-20020a170903070500b0019ca5ddfadbmr2567184plb.54.1678965972434; Thu, 16 Mar 2023 04:26:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1678965972; cv=none; d=google.com; s=arc-20160816; b=ywEFDBnFVpTza96q5FhARj0RX9/WjZPWYwoPLEGpIMH95Aa8TmIVZhTGe4PuWWmbOJ 5/GQBWSVW3ymetrQTmEu+jyOutOhjilKn0bDtI6JurWTHuIT8S0bXJq22lHT2Z6VTvhS eQMi4GGtNxDX/ygrNglX0fgKmkhLl5aGIlGCLyHWO2Ati4pJdQmvssoqBH9L/j+Vruka gJjqtwh3qfLCQjkTdnv3zEdkECl6n+jResufIkDM/pV90WrnYp6wxNEe4azD3r7sDUnD RPNZumM7BZv0+5gfWTnH0gfKc59DMB+rtIorXIqAwnlk6Av2DJsnOUTYEfvDQXQTyDvI qwyw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=YYPQdqinhymXQj5uTyuhOZ1fYw2hicDkmhnGZjiMqrM=; b=HxdPjOyH42jgYkQH6pAstICotZs0V8uRU4GJ3rRzUZOPwn+Yam8tOvSJ4aBTAYWfui +TAvpIYZy6pOEPozzjxQ+n+FYKCs7bP0Mp2UkiA5yJzV8UBJ+BiyrRIYsxUYHETXi8Le C7VVTgDPtI6RQ6IHD4Y5gC+yPOdrA40ClSMnfxcsuqBKwYbKRkq+Yk1wNdCFlx9xYo1S 5PShCoj4+5WyFcAtRkyjN4I+m0AedQexbDEuaE+UslkgzTHDVlvz7FX/w6DsPdYC9IzX btJmEj98oheIzGg8Wru2xXlnM8owZcP3jOk24zYv5DbbfAljVUg6aB6LytTqF9Pmm1eE lFEg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=aArFmhoa; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[83.9.29.16]) by smtp.gmail.com with ESMTPSA id u28-20020ac243dc000000b004db2978e330sm1194222lfl.258.2023.03.16.04.17.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Mar 2023 04:17:11 -0700 (PDT) From: Konrad Dybcio Date: Thu, 16 Mar 2023 12:16:58 +0100 Subject: [PATCH 3/5] arm64: dts: qcom: sm6350: Add QFPROM node MIME-Version: 1.0 Message-Id: <20230315-topic-lagoon_gpu-v1-3-a74cbec4ecfc@linaro.org> References: <20230315-topic-lagoon_gpu-v1-0-a74cbec4ecfc@linaro.org> In-Reply-To: <20230315-topic-lagoon_gpu-v1-0-a74cbec4ecfc@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , AngeloGioacchino Del Regno Cc: Marijn Suijten , Rob Herring , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , Konrad Dybcio X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1678965426; l=963; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=j4PNB4+G8/dM10UVcLzfnSLHfKZoes3Hu7z8kNdTYNk=; b=aCZnPj85u8/se75uEUhkWctyNzjU2/Ra7v0a5zk57RGX680lQLtOrnw3OoAMYSJ/+JsQUtaAIbPy XzJhpZBzCPjhiyvXGT6gM5aUV8LebqK2/rseDzPG3lhVJxfgkD/f X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-0.2 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_SORBS_HTTP,RCVD_IN_SORBS_SOCKS,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1760523423238027714?= X-GMAIL-MSGID: =?utf-8?q?1760523423238027714?= From: Konrad Dybcio Add a node for the QFPROM NVMEM hw and define the GPU fuse. Signed-off-by: Konrad Dybcio Signed-off-by: Konrad Dybcio Reviewed-by: Luca Weiss --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 523c7edfa4b3..60b68d305e53 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -637,6 +637,18 @@ ipcc: mailbox@408000 { #mbox-cells = <2>; }; + qfprom: qfprom@784000 { + compatible = "qcom,sm6350-qfprom", "qcom,qfprom"; + reg = <0 0x00784000 0 0x3000>; + #address-cells = <1>; + #size-cells = <1>; + + gpu_speed_bin: gpu_speed_bin@2015 { + reg = <0x2015 0x1>; + bits = <0 8>; + }; + }; + rng: rng@793000 { compatible = "qcom,prng-ee"; reg = <0 0x00793000 0 0x1000>; From patchwork Thu Mar 16 11:16:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 70743 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:604a:0:0:0:0:0 with SMTP id j10csp426720wrt; Thu, 16 Mar 2023 04:31:55 -0700 (PDT) X-Google-Smtp-Source: AK7set+9DEsBPTNLRSHHP0rlmIjNYTPVuIzvgEoAGkB6jUwdax3ErmYxxhUHQyEDCRS0agS2HJHA X-Received: by 2002:a17:903:2310:b0:1a0:7584:f468 with SMTP id d16-20020a170903231000b001a07584f468mr3675942plh.0.1678966315197; Thu, 16 Mar 2023 04:31:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1678966315; cv=none; d=google.com; s=arc-20160816; b=pVheTncCT9fNmmyOhucMW3yd5SWy6sR6GRIsOStPS6lG4YYDu7bK3SJsK06RazQ08w kqDWFK0MC6uF7ObDd3EYbTePvcrbtMrlrqmdtyJg0GCfgtpm4DA6ceMcZln3g3xx4D4R pHHBirDMrF8XOy8IaUMHsMFB4f+krld/kfpAXYJXAt8Fj5JoSab3k4Kh63G4Q2hcriJc oCXDOhB8dHO2cMi3QXguUrzCPyuKFOCcl3OlY4t4Df2CUZaJrX+6E0WPbGo10V3jiC5u 4GOnSaHs7S6SirmptUEf8ylq4nYNBAFW8yXdKl6aJYCdCFjtSVy1S9uzt2/5ruSK66bu oVxg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=sgn5Rzo7pAc2gmOTsd/K9TH2CYoJoK0uHcYeDBOw4do=; b=hrtH/9nqFWxEfm25ol9rBjBYu9BZPp3yunKmzla7H+4tnK/6iv6Qe6WfZwVM5CS2ey 6r4TkY2eBQH8I+7v9srADu/SZKpmfFdcZMXvdixr748uBVvXQ0VNItL9FiBuuwueVSca Qi2LuiniAzh47WWmh6z4cG1TeEHCRHYbGJfiLa0xJNrdgeXM0fWC4t+/XvC+Gpl9Rxz6 bZJhMfW0JFNpZFdnYK+6XIgqGkbg/4yeATxFPLnJfiY4eCHQpGeRzrg5eAn0hQvZ7XcF T0pgaEZFB1hFFmPKkWZzIrGMLOiBkle5MY+5Zjwv1tTxnZHGVRzuN2Asa/s2bhyKFPLC lzUw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rmh7PhiW; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[83.9.29.16]) by smtp.gmail.com with ESMTPSA id u28-20020ac243dc000000b004db2978e330sm1194222lfl.258.2023.03.16.04.17.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Mar 2023 04:17:13 -0700 (PDT) From: Konrad Dybcio Date: Thu, 16 Mar 2023 12:16:59 +0100 Subject: [PATCH 4/5] arm64: dts: qcom: sm6350: Add GPU nodes MIME-Version: 1.0 Message-Id: <20230315-topic-lagoon_gpu-v1-4-a74cbec4ecfc@linaro.org> References: <20230315-topic-lagoon_gpu-v1-0-a74cbec4ecfc@linaro.org> In-Reply-To: <20230315-topic-lagoon_gpu-v1-0-a74cbec4ecfc@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , AngeloGioacchino Del Regno Cc: Marijn Suijten , Rob Herring , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , Konrad Dybcio , Luca Weiss X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1678965426; l=4819; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=JbPANomzx98OqH3bbW/ckEJ9GniS0ZAyl4OszIK8VjY=; b=q8EnwRUIAkOg07OqiaMV5aWHa2/9a8PcMNld4DFAi0BHSrjIzEd6WbwKJgD5CMTCoakRkM4ZGN0/ cmA9feRhCVYh9+CM1lEy8L+8C1qxytmNUAaqDtUr+2ufKQB4/Fu9 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-0.2 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_SORBS_HTTP,RCVD_IN_SORBS_SOCKS,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1760523782877947964?= X-GMAIL-MSGID: =?utf-8?q?1760523782877947964?= From: Konrad Dybcio Add Adreno, GPU SMMU and GMU nodes to hook up everything that the A619 needs to function properly. Co-developed-by: Luca Weiss Signed-off-by: Konrad Dybcio Signed-off-by: Konrad Dybcio Signed-off-by: Luca Weiss --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 140 +++++++++++++++++++++++++++++++++++ 1 file changed, 140 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 60b68d305e53..e967d06b0ad4 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -1138,6 +1138,74 @@ compute-cb@5 { }; }; + gpu: gpu@3d00000 { + compatible = "qcom,adreno-619.0", "qcom,adreno"; + reg = <0 0x03d00000 0 0x40000>, + <0 0x03d9e000 0 0x1000>; + reg-names = "kgsl_3d0_reg_memory", + "cx_mem"; + interrupts = ; + + iommus = <&adreno_smmu 0>; + operating-points-v2 = <&gpu_opp_table>; + qcom,gmu = <&gmu>; + nvmem-cells = <&gpu_speed_bin>; + nvmem-cell-names = "speed_bin"; + + status = "disabled"; + + zap-shader { + memory-region = <&pil_gpu_mem>; + }; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-850000000 { + opp-hz = /bits/ 64 <850000000>; + opp-level = ; + opp-supported-hw = <0x02>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-level = ; + opp-supported-hw = <0x04>; + }; + + opp-650000000 { + opp-hz = /bits/ 64 <650000000>; + opp-level = ; + opp-supported-hw = <0x08>; + }; + + opp-565000000 { + opp-hz = /bits/ 64 <565000000>; + opp-level = ; + opp-supported-hw = <0x10>; + }; + + opp-430000000 { + opp-hz = /bits/ 64 <430000000>; + opp-level = ; + opp-supported-hw = <0xff>; + }; + + opp-355000000 { + opp-hz = /bits/ 64 <355000000>; + opp-level = ; + opp-supported-hw = <0xff>; + }; + + opp-253000000 { + opp-hz = /bits/ 64 <253000000>; + opp-level = ; + opp-supported-hw = <0xff>; + }; + }; + }; + + gpucc: clock-controller@3d90000 { compatible = "qcom,sm6350-gpucc"; reg = <0 0x03d90000 0 0x9000>; @@ -1152,6 +1220,78 @@ gpucc: clock-controller@3d90000 { #power-domain-cells = <1>; }; + adreno_smmu: iommu@3d40000 { + compatible = "qcom,sm6350-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; + reg = <0 0x03d40000 0 0x10000>; + #iommu-cells = <1>; + #global-interrupts = <2>; + interrupts = , + , + , + , + , + , + , + , + , + ; + + clocks = <&gpucc GPU_CC_AHB_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; + clock-names = "ahb", + "bus", + "iface"; + + power-domains = <&gpucc GPU_CX_GDSC>; + }; + + gmu: gmu@3d6a000 { + compatible = "qcom,adreno-gmu-619.0", "qcom,adreno-gmu"; + reg = <0 0x03d6a000 0 0x31000>, + <0 0x0b290000 0 0x10000>, + <0 0x0b490000 0 0x10000>; + reg-names = "gmu", + "gmu_pdc", + "gmu_pdc_seq"; + + interrupts = , + ; + interrupt-names = "hfi", + "gmu"; + + clocks = <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>; + clock-names = "ahb", + "gmu", + "cxo", + "axi", + "memnoc"; + + power-domains = <&gpucc GPU_CX_GDSC>, + <&gpucc GPU_GX_GDSC>; + power-domain-names = "cx", + "gx"; + + iommus = <&adreno_smmu 5>; + + operating-points-v2 = <&gmu_opp_table>; + + status = "disabled"; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-level = ; + }; + }; + }; + mpss: remoteproc@4080000 { compatible = "qcom,sm6350-mpss-pas"; reg = <0x0 0x04080000 0x0 0x4040>; From patchwork Thu Mar 16 11:17:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 70742 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:604a:0:0:0:0:0 with SMTP id j10csp426123wrt; Thu, 16 Mar 2023 04:30:49 -0700 (PDT) X-Google-Smtp-Source: AK7set/2iGKDHlkvSnOmdHGdOOvwGrgLoNWERlQjhAKVFt68Yjq7rgdsnYThQSCUNnW9j5ScMM+c X-Received: by 2002:a17:90b:38d1:b0:237:bf05:40b with SMTP id nn17-20020a17090b38d100b00237bf05040bmr3606941pjb.20.1678966248696; Thu, 16 Mar 2023 04:30:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1678966248; cv=none; d=google.com; s=arc-20160816; b=hwxv72kNKyx6usUlhKuL4MV3TbxCJOzxNbhME2REoIT9NiO2JwG7sbDYVihSYQc5+2 YDJOZeDdNUncJmbPzcUmMaveTpwVLOuqB/1l4zQRVL4gr8h4SPzv/KXgYv+exYyaUHZG YMLzXtmmUU0v53xGDt5Pc5o/9RW9OCj/Hdjh+9bxNsMEHZVVpPa8Z9W+hjYMgCi2uRYR SaBXMtPCGcXIR5tpyHvvg+8EAitQZWZBLYRysO9HFJNSyysL5E6qAGSHsWgWDX9kK1QT NYFmXohfmgFdTF8jEc7nPba7qmuOU/EVPJd99+VXKQifSanaV9V1uQSk57EkXjqg0WDC pYRQ== ARC-Message-Signature: i=1; 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[83.9.29.16]) by smtp.gmail.com with ESMTPSA id u28-20020ac243dc000000b004db2978e330sm1194222lfl.258.2023.03.16.04.17.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Mar 2023 04:17:14 -0700 (PDT) From: Konrad Dybcio Date: Thu, 16 Mar 2023 12:17:00 +0100 Subject: [PATCH 5/5] arm64: dts: qcom: sm6350: Fix ZAP region MIME-Version: 1.0 Message-Id: <20230315-topic-lagoon_gpu-v1-5-a74cbec4ecfc@linaro.org> References: <20230315-topic-lagoon_gpu-v1-0-a74cbec4ecfc@linaro.org> In-Reply-To: <20230315-topic-lagoon_gpu-v1-0-a74cbec4ecfc@linaro.org> To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , AngeloGioacchino Del Regno Cc: Marijn Suijten , Rob Herring , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , Konrad Dybcio X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1678965426; l=1198; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=U/Bw3E38fEF8jRRzaXOryssKT6fka2DSqTWTV4ocpSA=; b=FZq6+bZWyPDPG79SPJXQgWMUALXc7JoCk5eDIYdobDAZMVCQOw9q8wZUWV8Udto2y4Yyubxykc6P 3HZ83basBb+Ua3BceNy+jApWcW2cEL/Tux1dLECNslyXJL3tGFGU X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-0.2 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_SORBS_HTTP,RCVD_IN_SORBS_SOCKS,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1760523713029640439?= X-GMAIL-MSGID: =?utf-8?q?1760523713029640439?= From: Konrad Dybcio The previous ZAP region definition was wrong. Fix it. Note this is not a device-specific fixup, but a fixup to the generic PIL load address. Fixes: 5f82b9cda61e ("arm64: dts: qcom: Add SM6350 device tree") Signed-off-by: Konrad Dybcio Signed-off-by: Konrad Dybcio Reviewed-by: Luca Weiss --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index e967d06b0ad4..3fe4a5fa3021 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -466,11 +466,6 @@ pil_ipa_gsi_mem: memory@8b710000 { no-map; }; - pil_gpu_mem: memory@8b715400 { - reg = <0 0x8b715400 0 0x2000>; - no-map; - }; - pil_modem_mem: memory@8b800000 { reg = <0 0x8b800000 0 0xf800000>; no-map; @@ -491,6 +486,11 @@ removed_region: memory@c0000000 { no-map; }; + pil_gpu_mem: memory@f0d00000 { + reg = <0 0xf0d00000 0 0x1000>; + no-map; + }; + debug_region: memory@ffb00000 { reg = <0 0xffb00000 0 0xc0000>; no-map;