From patchwork Wed Oct 19 14:01:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amjad Ouled-Ameur X-Patchwork-Id: 5593 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp355896wrs; Wed, 19 Oct 2022 07:23:25 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6FQKGNd7l2+oOBUr9GfD696aPVYZ89h6QKEjpswR/+8Ze2It3bbrg3I9YIgLVHGd5PQdFn X-Received: by 2002:a17:906:9752:b0:78d:d2e1:d745 with SMTP id o18-20020a170906975200b0078dd2e1d745mr6881228ejy.452.1666189405463; Wed, 19 Oct 2022 07:23:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666189405; cv=none; d=google.com; s=arc-20160816; b=VZw6HgjnKb/U+2t1jzG5G4kdseYo5eUHaV4oNDy3y2ccVZTL4UkvTZXD+ndBiMKfwZ gH3gEDdmVNvgDLhvdGd+JcGb9hPjq9NOanaSdxEpjYF8WihJBiikxn5vkyARbB2YKUFu 1uOzUc+MiqwPo+aR1oqT7fUTvnYVGD53RYEm89XBzqX0yVXVEYvyGTAUbEbAKNGD8K30 K/FEjyd6/WeCWEIoA0fFRDffdAXVXiO8K/DeaSh/maJcNKkk0bisFbaBPN5PoL+ycYr8 2xjWGqX7GvXTn9J0oiCEKLKmZKTJkfH7n3m8s+jBVArSzex1yljv2DQp2ntQl6FSTnOE wvww== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=xtbDoRjweNPW4Ln3XA0uH8TZxjs8M3GoYCD7q6OX0gg=; b=l1JvNbdOgAHvV3QXAGpHv2DpyqltWpgC9TecSPaYeVbWH8WT62y2IpSafwNSowA60W 36zwTOALxPhK63JxETYew1YXti/mH33X3s69Tg1kUxsTMCKjNHr73kNCD8L2H+5kancI u7c+z8ax7q+67HTABFZO7AZnUDOeO6JuOjtO0FI+Hmz69g1U7wvJO2bXBq2WGNZWu5wH KNLHjJ3WGpCXQ+cZAP5yF2qwUrsqya5nJBJIT4fJ1z/XzMbimox3nUCWfpP1iU7ADdq8 tVqJbGcVJ9HZtxTEs8nnRLo+/Y4aPVycyYkxX5cECbc7PVu9xqW9M7aFGEYKTBMkLO+1 nVGg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20210112.gappssmtp.com header.s=20210112 header.b=pFzXbv7i; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id l18-20020a50c112000000b00459b3e9983esi13862905edf.113.2022.10.19.07.22.59; Wed, 19 Oct 2022 07:23:25 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20210112.gappssmtp.com header.s=20210112 header.b=pFzXbv7i; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230074AbiJSOVa (ORCPT + 99 others); Wed, 19 Oct 2022 10:21:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37982 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232791AbiJSOVK (ORCPT ); Wed, 19 Oct 2022 10:21:10 -0400 Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [IPv6:2a00:1450:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E348A4C61F for ; Wed, 19 Oct 2022 07:04:40 -0700 (PDT) Received: by mail-wr1-x42a.google.com with SMTP id b4so29257079wrs.1 for ; Wed, 19 Oct 2022 07:04:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=xtbDoRjweNPW4Ln3XA0uH8TZxjs8M3GoYCD7q6OX0gg=; b=pFzXbv7iB5TKy65HTPwKNi8Oya6dNVjlMeKCEG7UrRmcI/W8WpO0ouDDkOdT8BW7Fg HKwGZRZTy5zd2embkHjvTncf7YFv2OzUHfzw7wz6O92GFHaPyWhWyhRwMZ6BBGuZjHD6 1t1VV8ZvdTPHDfcObLjZauweQL/2aig1HZ/KpSUYeMjb/8ZKdJ1Wnm1mq9/umctrrj0X dDEfpAUSB6IOT6lVgCuzpHTKdaszY6zoM0LHGXPMeVLboMNGe6I2d2vaBEBSYnSO1fXq V6D3K/kq57dW1QsaXmiozYGmZWeeNi57wPKnd25DgeDG8KVBRz8+ZPzwD8XiKh2eWxxs blXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xtbDoRjweNPW4Ln3XA0uH8TZxjs8M3GoYCD7q6OX0gg=; b=FnSZdqDYeXMyQOcqj9/hqfkL2LHPtyfN3wYFSXn2aF+MeDICrmuaKOkJz5Oof2rGov +eT6tIbSRQr9g4TWN/F2Kqxi8QaCKLoeMRiF27YM9NnOEF+HAy+LSKljeAin+bJABvSk Mz8XI9oVTmH2iyYiMld/bBlciuKjPCI3ZJWzFRe4dhijgBNfeEIcA65wDdQN36/tGfMU m1P5jbojNm7o6oEOQh/cjeERa7Gz2mShQso5fhd9I5ouIv77eVM8Ihn0ozGy3vamP6w2 XKaUtgrqXoXITlkMZuuBTHfK/RzkAjo/e/LSkSzKcYSppas405Rezy0ICWqHpP2okK4l Nf+w== X-Gm-Message-State: ACrzQf09Dn1iicDnBYLwHTWVCLvTK1/oFdeiMAbqerLHbNi0/Yw+N8Wz obwNbBEpsf6B8gLvsWM5uL2ElA== X-Received: by 2002:adf:f001:0:b0:22e:4f85:3abc with SMTP id j1-20020adff001000000b0022e4f853abcmr4942257wro.107.1666188198769; Wed, 19 Oct 2022 07:03:18 -0700 (PDT) Received: from [127.0.1.1] (rtr.23.90.200.126.unyc.it. [23.90.200.126]) by smtp.googlemail.com with ESMTPSA id o5-20020a5d62c5000000b00228cbac7a25sm13998628wrv.64.2022.10.19.07.03.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Oct 2022 07:03:18 -0700 (PDT) From: Amjad Ouled-Ameur Date: Wed, 19 Oct 2022 16:01:03 +0200 Subject: [PATCH v3 1/2] spi: dt-bindings: amlogic, meson-gx-spicc: Add pinctrl names for SPI signal states MIME-Version: 1.0 Message-Id: <20221004-up-aml-fix-spi-v3-1-89de126fd163@baylibre.com> References: <20221004-up-aml-fix-spi-v3-0-89de126fd163@baylibre.com> In-Reply-To: <20221004-up-aml-fix-spi-v3-0-89de126fd163@baylibre.com> To: Mark Brown , Neil Armstrong , Krzysztof Kozlowski , Jerome Brunet , Martin Blumenstingl , Kevin Hilman , Rob Herring Cc: Da Xue , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org, Neil Armstrong , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, Amjad Ouled-Ameur X-Mailer: b4 0.10.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1666188196; l=2316; i=aouledameur@baylibre.com; s=20220920; h=from:subject:message-id; bh=GT6aksNJPuRsH4QN0MrP1Ih2mkD83njM/kpnUgJ63XA=; b=ixcAkOk+adBdqxmgoxXlgXIVeDQnfg8RbvllBQ1SFspcrcB6O+ZI0+0K4uwlL2TcFbxZu3FcKeOF H7ly++vKDGHx+MCSN/UhYp09gxpJlU9dBFr2Z+0tt8yyV6TycVaP X-Developer-Key: i=aouledameur@baylibre.com; a=ed25519; pk=HgYWawSL4qLGPx+RzJ+Cuu+V8Pi/KQnDDm1wjWPMOFE= X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747126222008736647?= X-GMAIL-MSGID: =?utf-8?q?1747126222008736647?= SPI pins of the SPICC Controller in Meson-GX needs to be controlled by pin biais when idle. Therefore define three pinctrl names: - default: SPI pins are controlled by spi function. - idle-high: SCLK pin is pulled-up, but MOSI/MISO are still controlled by spi function. - idle-low: SCLK pin is pulled-down, but MOSI/MISO are still controlled by spi function. Reported-by: Da Xue Signed-off-by: Neil Armstrong Signed-off-by: Amjad Ouled-Ameur --- .../bindings/spi/amlogic,meson-gx-spicc.yaml | 67 ++++++++++++++-------- 1 file changed, 42 insertions(+), 25 deletions(-) diff --git a/Documentation/devicetree/bindings/spi/amlogic,meson-gx-spicc.yaml b/Documentation/devicetree/bindings/spi/amlogic,meson-gx-spicc.yaml index 0c10f7678178..3e47fe7760a8 100644 --- a/Documentation/devicetree/bindings/spi/amlogic,meson-gx-spicc.yaml +++ b/Documentation/devicetree/bindings/spi/amlogic,meson-gx-spicc.yaml @@ -43,31 +43,48 @@ properties: minItems: 1 maxItems: 2 -if: - properties: - compatible: - contains: - enum: - - amlogic,meson-g12a-spicc - -then: - properties: - clocks: - minItems: 2 - - clock-names: - items: - - const: core - - const: pclk - -else: - properties: - clocks: - maxItems: 1 - - clock-names: - items: - - const: core +allOf: + - if: + properties: + compatible: + contains: + enum: + - amlogic,meson-g12a-spicc + + then: + properties: + clocks: + minItems: 2 + + clock-names: + items: + - const: core + - const: pclk + + else: + properties: + clocks: + maxItems: 1 + + clock-names: + items: + - const: core + + - if: + properties: + compatible: + contains: + enum: + - amlogic,meson-gx-spicc + + then: + properties: + pinctrl-names: + minItems: 1 + items: + - const: default + - const: idle-high + - const: idle-low required: - compatible From patchwork Wed Oct 19 14:01:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amjad Ouled-Ameur X-Patchwork-Id: 5595 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp364272wrs; Wed, 19 Oct 2022 07:40:05 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5S5YbzoV5Fd40SgvvmE7mPEXlY577JXvGfFsVA1PprD6I+A/dc2LraQGFowbHReQTtzLGC X-Received: by 2002:a05:6402:c45:b0:442:c549:8e6b with SMTP id cs5-20020a0564020c4500b00442c5498e6bmr7880190edb.123.1666190405617; Wed, 19 Oct 2022 07:40:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666190405; cv=none; d=google.com; s=arc-20160816; b=sYbfUUj/OnPmDTVuovg5NgRX9ruPgKVBALykyoOBpnB5iN93LdoXND08J29b00oNEV UZ+/uua9av3IiOAypedeuAJZLqpUbh47lAssqt6EpKYoKg7OjUF0pMM6Snf+uB3SokdQ U1VVMyKdLh/w7CbZW8kJdOIovBPZUgZAC8aylXdEjkY4yI1bAqZh7KZR0xD3VeZvXbvh NbZbq0mFFbBaVnqKBMh2mZakEiSypDnuIPuGwTpwdB1fDkCXezqUX9DFzKdLtrvSokOq 0XznmTeyHyfO6QuWJIrWS9aYws+txnnmlXpARzko0yjq8oVZvtaKXh7pQnKtbjrR2MID Iw/w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=rZgwfLubP2W/1t0/FaJA376eh/Hnps387U4J2IjbH+Q=; b=xfU9DpL5zYVpxobFkyRnq8Usdifw7TvnxvOMSgqCYRP/IW2vLxc5mExC23UGqifueL 08cP4xOvodRIi6cHpJkD8Zmss0pNrp9eP+6dppf0hTiHbeOsw5hJqwmcSf7gV/ZZo+8V c8xGEUl2NUZhhddHjPX5AcUegqlisjhFW1D29YpKD0TOXm0QdkBpPlKZXrx+Q6MbbMap 1w9fPu8uGhWlXXZXsGNlSMJsoSumymnHXa+ZNlDkvohuTxU2+amKwNpeq+6PikFHgrbj Jq6KgcWXmTm7l5MJF/QNDJMKOjqkKqY/lu+/h/V6Xstjhb6Ora1TXDdehBbOsaKdkzDP f3Uw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20210112.gappssmtp.com header.s=20210112 header.b="u/rHqaVS"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id cf20-20020a170906b2d400b0078043d1e9fbsi10853813ejb.354.2022.10.19.07.39.31; Wed, 19 Oct 2022 07:40:05 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20210112.gappssmtp.com header.s=20210112 header.b="u/rHqaVS"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233664AbiJSOWC (ORCPT + 99 others); Wed, 19 Oct 2022 10:22:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59524 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233409AbiJSOV1 (ORCPT ); Wed, 19 Oct 2022 10:21:27 -0400 Received: from mail-wm1-x329.google.com (mail-wm1-x329.google.com [IPv6:2a00:1450:4864:20::329]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AAEA9138B9C for ; Wed, 19 Oct 2022 07:05:03 -0700 (PDT) Received: by mail-wm1-x329.google.com with SMTP id az22-20020a05600c601600b003c6b72797fdso65281wmb.5 for ; Wed, 19 Oct 2022 07:05:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=rZgwfLubP2W/1t0/FaJA376eh/Hnps387U4J2IjbH+Q=; b=u/rHqaVSXAtf44+agVTaE7rGMxdiAM9mO+71rH0zJ13C+ops+wfxsALrLi/qTcHLo2 Ev9tB/jp7LpRZrpDHe+l83Ad3mBJ2dKF4iB6mppCyruY6ljkZZUK6lCRy7Ing4rcvvER Zj/PzLkyiUQv6AgvOqL2zNCF9C8AoGVdGkNgWTSsWTe00yYumXkM2MceEQazBiKqE3jl KjZzDc8RXzZ4mZcyAV2kNLiHjgklBvH5uBSWHKUc3IosI9qDvLSiwftNVI92bOBCdG/0 8Urw1OrJdT28AjBHu9avIBYu4AkAcdhPIF4Udczs8XDQNxnna8i6A9pc6rQnj5gVoJ7J 5JTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rZgwfLubP2W/1t0/FaJA376eh/Hnps387U4J2IjbH+Q=; b=IXZ9MjLJEKz+4ysZfHtpQoh48oCHoQ//IMj6ixQkj9J1Un1+Bks083z7IUdP/xtjs2 U3XCW/41rQbDhHJp0FysbqWQn1srUQ2vASGfyuOxiDLsf4AJbD5jiAs4ZS/WRgo6T1EP awQcgQP1+lENIBOlkaxLqMc7vwxcWIdzTY4o5Z8jkrfVBdMhHcFIUDxSbZeTJzqZoM0S 4u5ZfiIhfEtaqfwWS1shOqj4raxH+eJaj7ep7YtXAmTa4qZm1OOiMNgEILuiwD82D228 PiTVQx5ogoizIr4i39B4kUCpAoyFW03ZSM4J/hkpwFYHQxois0xupwqvzcf0Uz/Qi7HW IkHw== X-Gm-Message-State: ACrzQf3r3FFDYi4C5IcoenUnYLylb1rpQRRkw/L+x1m2yVCcQ6YUCYK8 LE0r7iwk9WUzBXHl9O7p/1yWgw== X-Received: by 2002:a05:600c:4e47:b0:3c6:fc59:5eff with SMTP id e7-20020a05600c4e4700b003c6fc595effmr6918684wmq.18.1666188199567; Wed, 19 Oct 2022 07:03:19 -0700 (PDT) Received: from [127.0.1.1] (rtr.23.90.200.126.unyc.it. [23.90.200.126]) by smtp.googlemail.com with ESMTPSA id o5-20020a5d62c5000000b00228cbac7a25sm13998628wrv.64.2022.10.19.07.03.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Oct 2022 07:03:19 -0700 (PDT) From: Amjad Ouled-Ameur Date: Wed, 19 Oct 2022 16:01:04 +0200 Subject: [PATCH v3 2/2] spi: meson-spicc: Use pinctrl to drive CLK line when idle MIME-Version: 1.0 Message-Id: <20221004-up-aml-fix-spi-v3-2-89de126fd163@baylibre.com> References: <20221004-up-aml-fix-spi-v3-0-89de126fd163@baylibre.com> In-Reply-To: <20221004-up-aml-fix-spi-v3-0-89de126fd163@baylibre.com> To: Mark Brown , Neil Armstrong , Krzysztof Kozlowski , Jerome Brunet , Martin Blumenstingl , Kevin Hilman , Rob Herring Cc: Da Xue , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org, Neil Armstrong , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, Amjad Ouled-Ameur X-Mailer: b4 0.10.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1666188196; l=4316; i=aouledameur@baylibre.com; s=20220920; h=from:subject:message-id; bh=dN6XmPpYO7Ty0vQSXH4eMp49Nq2iRF2CEqKZcOspWpI=; b=vviwObwJxuPYh/ZZNDCsfx7v9An1mgI8ZqaQQkOEPhpUcxtNrkB4V7dyqhh3eHnJUsX9mrUCOAxn oyRtrThBCRUCQgrksHjC40en6/dPJsjPNI8IfERp46vdxVdELtM6 X-Developer-Key: i=aouledameur@baylibre.com; a=ed25519; pk=HgYWawSL4qLGPx+RzJ+Cuu+V8Pi/KQnDDm1wjWPMOFE= X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747127270523641822?= X-GMAIL-MSGID: =?utf-8?q?1747127270523641822?= Between SPI transactions, all SPI pins are in HiZ state. When using the SS signal from the SPICC controller it's not an issue because when the transaction resumes all pins come back to the right state at the same time as SS. The problem is when we use CS as a GPIO. In fact, between the GPIO CS state change and SPI pins state change from idle, you can have a missing or spurious clock transition. Set a bias on the clock depending on the clock polarity requested before CS goes active, by passing a special "idle-low" and "idle-high" pinctrl state and setting the right state at a start of a message Reported-by: Da Xue Signed-off-by: Neil Armstrong Signed-off-by: Amjad Ouled-Ameur --- arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 14 +++++++++++ drivers/spi/spi-meson-spicc.c | 39 +++++++++++++++++++++++++++++- 2 files changed, 52 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi index c3ac531c4f84..04e9d0f1bde0 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi @@ -429,6 +429,20 @@ mux { }; }; + spi_idle_high_pins: spi-idle-high-pins { + mux { + groups = "spi_sclk"; + bias-pull-up; + }; + }; + + spi_idle_low_pins: spi-idle-low-pins { + mux { + groups = "spi_sclk"; + bias-pull-down; + }; + }; + spi_ss0_pins: spi-ss0 { mux { groups = "spi_ss0"; diff --git a/drivers/spi/spi-meson-spicc.c b/drivers/spi/spi-meson-spicc.c index bad201510a99..ffea38e2339c 100644 --- a/drivers/spi/spi-meson-spicc.c +++ b/drivers/spi/spi-meson-spicc.c @@ -21,6 +21,7 @@ #include #include #include +#include /* * The Meson SPICC controller could support DMA based transfers, but is not @@ -167,6 +168,9 @@ struct meson_spicc_device { unsigned long tx_remain; unsigned long rx_remain; unsigned long xfer_remain; + struct pinctrl *pinctrl; + struct pinctrl_state *pins_idle_high; + struct pinctrl_state *pins_idle_low; }; #define pow2_clk_to_spicc(_div) container_of(_div, struct meson_spicc_device, pow2_div) @@ -175,8 +179,22 @@ static void meson_spicc_oen_enable(struct meson_spicc_device *spicc) { u32 conf; - if (!spicc->data->has_oen) + if (!spicc->data->has_oen) { + /* Try to get pinctrl states for idle high/low */ + spicc->pins_idle_high = pinctrl_lookup_state(spicc->pinctrl, + "idle-high"); + if (IS_ERR(spicc->pins_idle_high)) { + dev_warn(&spicc->pdev->dev, "can't get idle-high pinctrl\n"); + spicc->pins_idle_high = NULL; + } + spicc->pins_idle_low = pinctrl_lookup_state(spicc->pinctrl, + "idle-low"); + if (IS_ERR(spicc->pins_idle_low)) { + dev_warn(&spicc->pdev->dev, "can't get idle-low pinctrl\n"); + spicc->pins_idle_low = NULL; + } return; + } conf = readl_relaxed(spicc->base + SPICC_ENH_CTL0) | SPICC_ENH_MOSI_OEN | SPICC_ENH_CLK_OEN | SPICC_ENH_CS_OEN; @@ -441,6 +459,16 @@ static int meson_spicc_prepare_message(struct spi_master *master, else conf &= ~SPICC_POL; + if (!spicc->data->has_oen) { + if (spi->mode & SPI_CPOL) { + if (spicc->pins_idle_high) + pinctrl_select_state(spicc->pinctrl, spicc->pins_idle_high); + } else { + if (spicc->pins_idle_low) + pinctrl_select_state(spicc->pinctrl, spicc->pins_idle_low); + } + } + if (spi->mode & SPI_CPHA) conf |= SPICC_PHA; else @@ -487,6 +515,9 @@ static int meson_spicc_unprepare_transfer(struct spi_master *master) /* Set default configuration, keeping datarate field */ writel_relaxed(conf, spicc->base + SPICC_CONREG); + if (!spicc->data->has_oen) + pinctrl_select_default_state(&spicc->pdev->dev); + return 0; } @@ -798,6 +829,12 @@ static int meson_spicc_probe(struct platform_device *pdev) goto out_core_clk; } + spicc->pinctrl = devm_pinctrl_get(&pdev->dev); + if (IS_ERR(spicc->pinctrl)) { + ret = PTR_ERR(spicc->pinctrl); + goto out_clk; + } + device_reset_optional(&pdev->dev); master->num_chipselect = 4;