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[2620:137:e000::1:20]) by mx.google.com with ESMTP id nn10-20020a17090b38ca00b0020af213b0d9si133092pjb.13.2022.10.19.07.21.29; Wed, 19 Oct 2022 07:21:42 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=YGAYOVv+; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232651AbiJSOSz (ORCPT + 99 others); Wed, 19 Oct 2022 10:18:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47422 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230080AbiJSOSk (ORCPT ); Wed, 19 Oct 2022 10:18:40 -0400 Received: from mail-pj1-x1034.google.com (mail-pj1-x1034.google.com [IPv6:2607:f8b0:4864:20::1034]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 992081CCCC6 for ; Wed, 19 Oct 2022 07:01:41 -0700 (PDT) Received: by mail-pj1-x1034.google.com with SMTP id pb15so82410pjb.5 for ; Wed, 19 Oct 2022 07:01:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YBJNc8d1DN49dwvNIgcD6LtTNDN4+u1e0rvTArMbSRY=; b=YGAYOVv+brUZd23y7jvKSb64Bb5umVyN2Q3QSeu1MMFEuhjPw2hd8U1Zx8Vsqj0Sd8 vzvgLc83OHECsisUyP9UWZgPnvUSOt/KGIz/h/D6SIS6z9DRQBv0qfRq6tKbYHCS/hYm AFf5CgV2T1wHNeCArE60X4fjJFf7WwCcYzDouX1lzJCEvjpGR4dRZpFM99Dru7lPpiix HyFttEscr3sUOB/T3vMUgzBxl0G/HmbkqvS/HbpeBBWNpSfAaM6lUEDtuLR6duB2dHrl Pj3wiwvBiI8v9iWj3kwfrkJ4Q0qgJhyMtUbrKBUxKPOlsKA9tVYEMKmVHRWTeJST54W1 b0/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YBJNc8d1DN49dwvNIgcD6LtTNDN4+u1e0rvTArMbSRY=; b=ylcyDQ3Kms1vfKzYYAYPV5j2DYhgPkGoQpTOvY3+OrOBcOWIBzeuldNSJz271x1eWV tgEX2sV4PZeuLB16bW+egmVLcfhs9pVDjDWCruICBcZtnuqEvtexSrEenCz+m6HBVPYM AFofX3VC6sKZQePt97OZrUAs5W0Lj2p5T6iZDtOXVWdJtecjid1KK1rCN36zJvbFXTso ajsjPiV4QxseyASWX7tRnudm3JU/upztTBkxeYzHy+jbHiRugv+X/FJ52jMUfLIfGFxZ N81GsFZKZO1ar7ib6kPxvTzIPorLdPvwlWBaXgXUDdxY1VJ9T3Yt7mYCg5Y5JLqRMOZd yIqQ== X-Gm-Message-State: ACrzQf2b4q+YHMtCQrymMaHgZmhHSG4pcXqm+T/I5llRts1XEDx80U1s MXeso/IlRUuiLOmP7yOreAFs X-Received: by 2002:a17:90b:4a84:b0:20d:8953:5ab0 with SMTP id lp4-20020a17090b4a8400b0020d89535ab0mr44983588pjb.48.1666187982638; Wed, 19 Oct 2022 06:59:42 -0700 (PDT) Received: from localhost.localdomain ([117.193.210.93]) by smtp.gmail.com with ESMTPSA id 194-20020a6216cb000000b0053e199aa99bsm11240322pfw.220.2022.10.19.06.59.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Oct 2022 06:59:41 -0700 (PDT) From: Manivannan Sadhasivam To: andersson@kernel.org, viresh.kumar@linaro.org, krzysztof.kozlowski+dt@linaro.org, rafael@kernel.org, robh+dt@kernel.org Cc: johan@kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH 1/4] cpufreq: qcom-hw: Remove un-necessary cpumask_empty() check Date: Wed, 19 Oct 2022 19:29:22 +0530 Message-Id: <20221019135925.366162-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221019135925.366162-1-manivannan.sadhasivam@linaro.org> References: <20221019135925.366162-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747126113580540777?= X-GMAIL-MSGID: =?utf-8?q?1747126113580540777?= CPUFreq core will always set the "policy->cpus" bitmask with the bitfield of the CPU that goes first per domain/policy. So there is no way the "policy->cpus" bitmask will be empty during qcom_cpufreq_hw_cpu_init(). Signed-off-by: Manivannan Sadhasivam --- drivers/cpufreq/qcom-cpufreq-hw.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufreq-hw.c index d5ef3c66c762..a5b3b8d0e164 100644 --- a/drivers/cpufreq/qcom-cpufreq-hw.c +++ b/drivers/cpufreq/qcom-cpufreq-hw.c @@ -552,11 +552,6 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) data->per_core_dcvs = true; qcom_get_related_cpus(index, policy->cpus); - if (cpumask_empty(policy->cpus)) { - dev_err(dev, "Domain-%d failed to get related CPUs\n", index); - ret = -ENOENT; - goto error; - } policy->driver_data = data; policy->dvfs_possible_from_any_cpu = true; From patchwork Wed Oct 19 13:59:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 5586 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp354242wrs; Wed, 19 Oct 2022 07:20:13 -0700 (PDT) X-Google-Smtp-Source: AMsMyM504gWyUkO6KDJJHJulP4Wsiy/Ed+Eee0qTYDqIAGmeZMnTpCVzh1NjFWGxlzOjsau9xyPj X-Received: by 2002:a17:903:2346:b0:183:3e95:6f5d with SMTP id c6-20020a170903234600b001833e956f5dmr8785264plh.165.1666189212800; Wed, 19 Oct 2022 07:20:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666189212; cv=none; d=google.com; s=arc-20160816; b=bDKom14GqYjmMnbzUkKxR9alaKAJXZt6k0VfUZTUT5A7jHMOrQwu6+56qW16Q6l2oB v1h1xWkZ5OotOfnRwNEgnf0WccAPWvtNj8zxdiKwH0DTbcQKHvm0aMN2Pj69vhuC1/No YMhaXlKU294EkfW8CsalEaUfHY/EaT16croHYkwET6auE8rLTO8A2fns6yUiVREkA5qV IYV2Qvif89GPWZw3nvZHTu4qYhl53xIYsKRpFN0c3HntVCGxeEUKipoY47jFG1z5ElEr Q20RtAR+0sTcNy+GN3krwlpde5NUtMsYfeGq+MCBnE0LgyADga0poBAueutCf8BqMyIf KQYw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=+OcwfXiesFKWlB7LNMDAzT3rAd6eUuEjWbfk2IH0mpk=; b=Mk+sbocp/C3WdORqUB/ZJ+sh6EhXyYNZQkjQT3O8TtwtvsyVF2w1+LhKQA048FlMqV APP1kryZP0QKeFQXzh3x4WNVVKH2s20DsxuJTXQA0jmtefihUlhgLMo3DJbRHubDvp2T X4PK+kQDTk29iUDaocyzkZN6Zr8Jrcc/fFsPjGTztN/B6l5k9lPYgQWwHsXFYxRRgnVC 3OoXLK460t4v37TYBgyeT7FkCDBuSx+2ZdrTdb77Tn1EzE80M7euBIfPFc2SfRUHzin9 PG09iuZrtYVAMPdMS6V+DVzbHVMXiov+Sft1EIPGe/QNFCoZnntH/pFLHoGIx8oF0hDE Uhtg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WA4KMdnB; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Document the same in the binding to reflect the actual implementation. CPUFreq HW will become the clock provider and CPU cores will become the clock consumers. The clock index for each CPU core is based on the frequency domain index. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Rob Herring --- .../devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml index cbba8979fe0e..2e0336163ffb 100644 --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml @@ -57,6 +57,9 @@ properties: '#freq-domain-cells': const: 1 + '#clock-cells': + const: 1 + required: - compatible - reg @@ -84,6 +87,7 @@ examples: enable-method = "psci"; next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0>; + clocks = <&cpufreq_hw 0>; L2_0: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -100,6 +104,7 @@ examples: enable-method = "psci"; next-level-cache = <&L2_100>; qcom,freq-domain = <&cpufreq_hw 0>; + clocks = <&cpufreq_hw 0>; L2_100: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -113,6 +118,7 @@ examples: enable-method = "psci"; next-level-cache = <&L2_200>; qcom,freq-domain = <&cpufreq_hw 0>; + clocks = <&cpufreq_hw 0>; L2_200: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -126,6 +132,7 @@ examples: enable-method = "psci"; next-level-cache = <&L2_300>; qcom,freq-domain = <&cpufreq_hw 0>; + clocks = <&cpufreq_hw 0>; L2_300: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -139,6 +146,7 @@ examples: enable-method = "psci"; next-level-cache = <&L2_400>; qcom,freq-domain = <&cpufreq_hw 1>; + clocks = <&cpufreq_hw 1>; L2_400: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -152,6 +160,7 @@ examples: enable-method = "psci"; next-level-cache = <&L2_500>; qcom,freq-domain = <&cpufreq_hw 1>; + clocks = <&cpufreq_hw 1>; L2_500: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -165,6 +174,7 @@ examples: enable-method = "psci"; next-level-cache = <&L2_600>; qcom,freq-domain = <&cpufreq_hw 1>; + clocks = <&cpufreq_hw 1>; L2_600: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -178,6 +188,7 @@ examples: enable-method = "psci"; next-level-cache = <&L2_700>; qcom,freq-domain = <&cpufreq_hw 1>; + clocks = <&cpufreq_hw 1>; L2_700: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -198,6 +209,7 @@ examples: clock-names = "xo", "alternate"; #freq-domain-cells = <1>; + #clock-cells = <1>; }; }; ... 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But this relationship is not represented with the clk framework so far. So, let's make the qcom-cpufreq-hw driver a clock provider. This makes the clock producer/consumer relationship cleaner and is also useful for CPU related frameworks like OPP to know the frequency at which the CPUs are running. The clock frequency provided by the driver is for each CPU policy. We cannot get the frequency of each CPU core because, not all platforms support per-core DCVS feature. Also the frequency supplied by the driver is the actual frequency that comes out of the EPSS/OSM block after the DCVS operation. This frequency is not same as what the CPUFreq framework has set but it is the one that gets supplied to the CPUs after throttling by LMh. Signed-off-by: Manivannan Sadhasivam --- drivers/cpufreq/qcom-cpufreq-hw.c | 67 +++++++++++++++++++++++++++++-- 1 file changed, 63 insertions(+), 4 deletions(-) diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufreq-hw.c index a5b3b8d0e164..4dd710f9fb69 100644 --- a/drivers/cpufreq/qcom-cpufreq-hw.c +++ b/drivers/cpufreq/qcom-cpufreq-hw.c @@ -4,6 +4,7 @@ */ #include +#include #include #include #include @@ -54,6 +55,7 @@ struct qcom_cpufreq_data { bool cancel_throttle; struct delayed_work throttle_work; struct cpufreq_policy *policy; + struct clk_hw cpu_clk; bool per_core_dcvs; }; @@ -482,6 +484,54 @@ static void qcom_cpufreq_hw_lmh_exit(struct qcom_cpufreq_data *data) free_irq(data->throttle_irq, data); } +static unsigned long qcom_cpufreq_hw_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) +{ + struct qcom_cpufreq_data *data = container_of(hw, struct qcom_cpufreq_data, cpu_clk); + + return qcom_lmh_get_throttle_freq(data) / HZ_PER_KHZ; +} + +static const struct clk_ops qcom_cpufreq_hw_clk_ops = { + .recalc_rate = qcom_cpufreq_hw_recalc_rate, +}; + +static int qcom_cpufreq_hw_clk_add(struct qcom_cpufreq_data *data, u32 index) +{ + struct platform_device *pdev = cpufreq_get_driver_data(); + struct device *dev = &pdev->dev; + char *clk_name = devm_kasprintf(dev, GFP_KERNEL, "qcom_cpufreq%d", index); + static struct clk_init_data init = {}; + int ret; + + init.name = clk_name; + init.flags = CLK_GET_RATE_NOCACHE; + init.ops = &qcom_cpufreq_hw_clk_ops; + data->cpu_clk.init = &init; + + ret = clk_hw_register(dev, &data->cpu_clk); + if (ret < 0) { + dev_err(dev, "Failed to register Qcom CPUFreq clock\n"); + return ret; + } + + ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get, &data->cpu_clk); + if (ret < 0) { + dev_err(dev, "Failed to add Qcom CPUFreq clock provider\n"); + clk_hw_unregister(&data->cpu_clk); + } + + return ret; +} + +static void qcom_cpufreq_hw_clk_remove(struct qcom_cpufreq_data *data) +{ + struct platform_device *pdev = cpufreq_get_driver_data(); + struct device *dev = &pdev->dev; + + of_clk_del_provider(dev->of_node); + clk_hw_unregister(&data->cpu_clk); +} + static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) { struct platform_device *pdev = cpufreq_get_driver_data(); @@ -556,19 +606,24 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) policy->driver_data = data; policy->dvfs_possible_from_any_cpu = true; + ret = qcom_cpufreq_hw_clk_add(data, index); + if (ret) { + dev_err(dev, "Domain-%d failed to add CPU clock\n", index); + goto error; + } + ret = qcom_cpufreq_hw_read_lut(cpu_dev, policy); if (ret) { dev_err(dev, "Domain-%d failed to read LUT\n", index); - goto error; + goto clk_remove; } ret = dev_pm_opp_get_opp_count(cpu_dev); if (ret <= 0) { dev_err(cpu_dev, "Failed to add OPPs\n"); ret = -ENODEV; - goto error; + goto clk_remove; } - if (policy_has_boost_freq(policy)) { ret = cpufreq_enable_boost_support(); if (ret) @@ -577,9 +632,12 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy) ret = qcom_cpufreq_hw_lmh_init(policy, index); if (ret) - goto error; + goto clk_remove; return 0; + +clk_remove: + qcom_cpufreq_hw_clk_remove(data); error: kfree(data); unmap_base: @@ -599,6 +657,7 @@ static int qcom_cpufreq_hw_cpu_exit(struct cpufreq_policy *policy) dev_pm_opp_remove_all_dynamic(cpu_dev); dev_pm_opp_of_cpumask_remove_table(policy->related_cpus); qcom_cpufreq_hw_lmh_exit(data); + qcom_cpufreq_hw_clk_remove(data); kfree(policy->freq_table); kfree(data); iounmap(base); From patchwork Wed Oct 19 13:59:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 5590 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp355001wrs; Wed, 19 Oct 2022 07:21:45 -0700 (PDT) X-Google-Smtp-Source: AMsMyM7p3jmAVotV+0XOYK8r8h2Gd+iu9sLqpZhwC/PoLA8KR/ia0f/wjoBulB3bzabXryz8yCdg X-Received: by 2002:a63:fe13:0:b0:452:2b86:50fb with SMTP id p19-20020a63fe13000000b004522b8650fbmr7304959pgh.167.1666189304789; Wed, 19 Oct 2022 07:21:44 -0700 (PDT) ARC-Seal: i=1; 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But this relationship is not represented in DTS so far. So let's make cpufreq node as the clock provider and CPU nodes as the consumers. The clock index for each CPU node is based on the frequency domain index. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 6c18cfca9a34..8f26cf9aad01 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -52,6 +52,7 @@ CPU0: cpu@0 { power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; + clocks = <&cpufreq_hw 0>; L2_0: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -71,6 +72,7 @@ CPU1: cpu@100 { power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; + clocks = <&cpufreq_hw 0>; L2_100: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -87,6 +89,7 @@ CPU2: cpu@200 { power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; + clocks = <&cpufreq_hw 0>; L2_200: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -103,6 +106,7 @@ CPU3: cpu@300 { power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; + clocks = <&cpufreq_hw 0>; L2_300: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -119,6 +123,7 @@ CPU4: cpu@400 { power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; + clocks = <&cpufreq_hw 1>; L2_400: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -135,6 +140,7 @@ CPU5: cpu@500 { power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; + clocks = <&cpufreq_hw 1>; L2_500: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -152,6 +158,7 @@ CPU6: cpu@600 { power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; + clocks = <&cpufreq_hw 1>; L2_600: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -168,6 +175,7 @@ CPU7: cpu@700 { power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 2>; #cooling-cells = <2>; + clocks = <&cpufreq_hw 2>; L2_700: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -3804,6 +3812,7 @@ cpufreq_hw: cpufreq@17d91000 { ; interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; #freq-domain-cells = <1>; + #clock-cells = <1>; }; gem_noc: interconnect@19100000 {