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[2620:137:e000::1:20]) by mx.google.com with ESMTP id u15-20020a170902e80f00b0019f232b202csi186322plg.15.2023.03.16.00.39.19; Thu, 16 Mar 2023 00:39:33 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=reDUKbjX; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230140AbjCPHPf (ORCPT + 99 others); Thu, 16 Mar 2023 03:15:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44924 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230235AbjCPHPT (ORCPT ); Thu, 16 Mar 2023 03:15:19 -0400 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1F3DCAA705; Thu, 16 Mar 2023 00:14:52 -0700 (PDT) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 32G7CfXH086570; Thu, 16 Mar 2023 02:12:41 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1678950761; bh=PpUfaVjVt4iNuG1/XgKubLP9ifTcdNa1nIS4MSP55A0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=reDUKbjXiPiKIIW4sJI5/lfinnnvwnkJMulf/tqmCkFD5V6PbKouGMrmFon3MD7L3 05YvJnhyRtcckpp4VuLeop06AdXSmkX1yX0ligN4aib5p7F4IIrWZNeZqg0h/d+zFq ETlFN5athlckioPBOg6p+wKsYOWaIST7YiYKE3PM= Received: from DFLE111.ent.ti.com (dfle111.ent.ti.com [10.64.6.32]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 32G7Cf90077894 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 16 Mar 2023 02:12:41 -0500 Received: from DFLE110.ent.ti.com (10.64.6.31) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Thu, 16 Mar 2023 02:12:41 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Thu, 16 Mar 2023 02:12:41 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 32G7CeeQ072290; Thu, 16 Mar 2023 02:12:40 -0500 From: Achal Verma To: Tom Joseph , Lorenzo Pieralisi , Rob Herring , Krzysztof Wilczy_ski , Bjorn Helgaas , Vignesh Raghavendra CC: , , , , Achal Verma , Milind Parab , Subject: [PATCH v10 1/5] dt-bindings: PCI: ti,j721e-pci-*: add checks for num-lanes Date: Thu, 16 Mar 2023 12:42:34 +0530 Message-ID: <20230316071238.200992-2-a-verma1@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230316071238.200992-1-a-verma1@ti.com> References: <20230316071238.200992-1-a-verma1@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1760509164481292650?= X-GMAIL-MSGID: =?utf-8?q?1760509164481292650?= From: Matt Ranostay Add num-lanes schema checks based on compatible string on available lanes for that platform. Signed-off-by: Matt Ranostay Signed-off-by: Achal Verma --- .../bindings/pci/ti,j721e-pci-ep.yaml | 27 ++++++++++++++++--- .../bindings/pci/ti,j721e-pci-host.yaml | 27 ++++++++++++++++--- 2 files changed, 48 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml index 10e6eabdff53..32e0c70ed801 100644 --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml @@ -10,9 +10,6 @@ title: TI J721E PCI EP (PCIe Wrapper) maintainers: - Kishon Vijay Abraham I -allOf: - - $ref: "cdns-pcie-ep.yaml#" - properties: compatible: oneOf: @@ -65,6 +62,30 @@ properties: items: - const: link_state +allOf: + - $ref: cdns-pcie-ep.yaml# + - if: + properties: + compatible: + enum: + - ti,am64-pcie-ep + then: + properties: + num-lanes: + const: 1 + + - if: + properties: + compatible: + enum: + - ti,j7200-pcie-ep + - ti,j721e-pcie-ep + then: + properties: + num-lanes: + minimum: 1 + maximum: 2 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml index 3d7aee97353a..2547088304e5 100644 --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml @@ -10,9 +10,6 @@ title: TI J721E PCI Host (PCIe Wrapper) maintainers: - Kishon Vijay Abraham I -allOf: - - $ref: "cdns-pcie-host.yaml#" - properties: compatible: oneOf: @@ -94,6 +91,30 @@ properties: interrupts: maxItems: 1 +allOf: + - $ref: cdns-pcie-host.yaml# + - if: + properties: + compatible: + enum: + - ti,am64-pcie-host + then: + properties: + num-lanes: + const: 1 + + - if: + properties: + compatible: + enum: + - ti,j7200-pcie-host + - ti,j721e-pcie-host + then: + properties: + num-lanes: + minimum: 1 + maximum: 2 + required: - compatible - reg From patchwork Thu Mar 16 07:12:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Achal Verma X-Patchwork-Id: 70608 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:604a:0:0:0:0:0 with SMTP id j10csp334976wrt; Thu, 16 Mar 2023 00:31:43 -0700 (PDT) X-Google-Smtp-Source: AK7set/9ZPZIntuHYKxO4QkJsr0gi+LwY38bO+ZFUVCrgcA9PMzXvoQu8VctJ8E2KyZGdvP9gM8o X-Received: by 2002:a62:1ec4:0:b0:625:f959:bc88 with SMTP id e187-20020a621ec4000000b00625f959bc88mr601346pfe.17.1678951903034; Thu, 16 Mar 2023 00:31:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1678951903; cv=none; d=google.com; s=arc-20160816; b=LdRf8tCzqOOH4+kyEMqN15lJ9sVIkSKkKNQ8Xf/ZkgidMaoCVDovADtYfOiGKrEQtW SI+8U99bNTtXUYXiG0CWym3E0eB3E8bLCHa+2aBv8+TL2yfZt06UjblZLf762GvjCcs0 lr+gWGe9DYgZr4v8JjAblDjo4JG1nv/B0QSJlJyvMT2iBvB8TsAlE6yggDG4IvQh3IjC 7mbTKs6H1nvn831u6ltWvVRLq3MaAjynnkP61CiPIYYsDfRdglgAjVCTF1FRvky8Hm7u 8mFAg2q0q8wYGyNAYkl4UO6JsxAFl7bqiEsxJ66hQLWn1T1l7292PcyRB2cIp1DimfSs ZFhA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=6txK6JhGNmC1mVhE7nu+ujxZBb0FV1uO3fUqV2jp4bY=; b=jlSEJpPzYLrT5NRQTTf778iYnXPk3S0NaS0ED09A5buIUwBFHDSHUsz6yeTshwihxu nmxF4Yfu207R+aUT/VCL/noNjrLS4B4L97B3Y5X1eXea6YbBXz88a8QElc7kZMHZc7y9 eJgTrp6ajFihTWsyydn1K2/2uL68k4STVkoqenpCDz5qR4vByXIEiwoo+oactrsptStz 3yhvZkoOUesr7yaSGGAs+q0lN5EZx5u1VxmWwDWfE5BitoQZ3AsEgYKoavZnUy5sKGGq ySkBg4HoJXyprLi1jRzjJ988KgJ17HhazkrR47x1Nf/pw+g/vnudtioLq84cx0vdkllh THXw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=mroP1u7I; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from out1.vger.email (out1.vger.email. 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Add max_lanes to struct j721e_pcie to allow for detection of this which is needed to calculate the needed bitmask size for the possible lane count. Signed-off-by: Matt Ranostay Signed-off-by: Vignesh Raghavendra Signed-off-by: Achal Verma --- drivers/pci/controller/cadence/pci-j721e.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c index cc83a8925ce0..f4dc2c5abedb 100644 --- a/drivers/pci/controller/cadence/pci-j721e.c +++ b/drivers/pci/controller/cadence/pci-j721e.c @@ -47,8 +47,6 @@ enum link_status { #define GENERATION_SEL_MASK GENMASK(1, 0) -#define MAX_LANES 2 - struct j721e_pcie { struct cdns_pcie *cdns_pcie; struct clk *refclk; @@ -71,6 +69,7 @@ struct j721e_pcie_data { unsigned int quirk_disable_flr:1; u32 linkdown_irq_regfield; unsigned int byte_access_allowed:1; + unsigned int max_lanes; }; static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset) @@ -290,11 +289,13 @@ static const struct j721e_pcie_data j721e_pcie_rc_data = { .quirk_retrain_flag = true, .byte_access_allowed = false, .linkdown_irq_regfield = LINK_DOWN, + .max_lanes = 2, }; static const struct j721e_pcie_data j721e_pcie_ep_data = { .mode = PCI_MODE_EP, .linkdown_irq_regfield = LINK_DOWN, + .max_lanes = 2, }; static const struct j721e_pcie_data j7200_pcie_rc_data = { @@ -302,23 +303,27 @@ static const struct j721e_pcie_data j7200_pcie_rc_data = { .quirk_detect_quiet_flag = true, .linkdown_irq_regfield = J7200_LINK_DOWN, .byte_access_allowed = true, + .max_lanes = 2, }; static const struct j721e_pcie_data j7200_pcie_ep_data = { .mode = PCI_MODE_EP, .quirk_detect_quiet_flag = true, .quirk_disable_flr = true, + .max_lanes = 2, }; static const struct j721e_pcie_data am64_pcie_rc_data = { .mode = PCI_MODE_RC, .linkdown_irq_regfield = J7200_LINK_DOWN, .byte_access_allowed = true, + .max_lanes = 1, }; static const struct j721e_pcie_data am64_pcie_ep_data = { .mode = PCI_MODE_EP, .linkdown_irq_regfield = J7200_LINK_DOWN, + .max_lanes = 1, }; static const struct of_device_id of_j721e_pcie_match[] = { @@ -432,8 +437,10 @@ static int j721e_pcie_probe(struct platform_device *pdev) pcie->user_cfg_base = base; ret = of_property_read_u32(node, "num-lanes", &num_lanes); - if (ret || num_lanes > MAX_LANES) + if (ret || num_lanes > data->max_lanes) { + dev_warn(dev, "num-lanes property not provided or invalid, setting num-lanes to 1\n"); num_lanes = 1; + } pcie->num_lanes = num_lanes; if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48))) From patchwork Thu Mar 16 07:12:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Achal Verma X-Patchwork-Id: 70606 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:604a:0:0:0:0:0 with SMTP id j10csp334801wrt; Thu, 16 Mar 2023 00:31:20 -0700 (PDT) X-Google-Smtp-Source: AK7set98JN3daDbUVs1nOQjjVwPXpugB3uhcyDDamEovBfyqh0kuyfmexUbS8RgKaFPlKEMMDdzh X-Received: by 2002:a05:6102:160d:b0:412:2d61:5785 with SMTP id cu13-20020a056102160d00b004122d615785mr18223079vsb.3.1678951880597; Thu, 16 Mar 2023 00:31:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1678951880; cv=none; d=google.com; s=arc-20160816; b=VikGEY8Y6zOp5V2w5to6Z6/KLTKZUlVqlvBfeLrVoxPi1F63c4+JFiVVVilj0LkVyj fv4G6FVEBao8A6yYKB1tF/PZyuVSjGRUiFKC4zvGVff3oqFAF/zt9uQo0ZxcJdOrletx NS3zRJs1F5/6yVD5RHYQxORFlQ5huMIlk0FOqoiemwwxF5MTJOA3giPxOOvztz9vy2O/ ukFGQR1C3iSK9+1FFV6VXVmBQsANvcJCpMBK8OI/h7I+8oWjOdTgtk5SJ5aEcr4GXc/Z RtfjC0aTU2WOlJACnQxZgsIK12cFFEmUO/TXayEZeyWJrZbr8nUuL5Lmha6XPktrPlJC L9rA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=TISRczCqqClgTnuh9Jgbp4YdFIC7Href1UTZ0gVUQ5I=; b=aW6rDDSH7ePb+dMomEXLEEwvg7j5k8HPf6YlAPEaEupHh/CUX8vpQ0Aa/N0HY9W/vw /dOSDvktqUpnhyJHjmN9ovthkEn9bZ1pYs68UpylXLXvLa5J9/euPHkP/WEdqpiQQxXB p4qromBq/s1BZm5WXpvsbdfZgdiwZhJuGVKt32WrdR29GiUiVgks5KblpzTiQ0kZdLwj sb7LRhMKCFUJlUWxVIcIDtiPdeE0jLQZf8DP8oebb6QtVclNsovJDwZXVERbIm7+G+CR pkWpLaQbUyx7UaTnn4xVw/23b8ESAjDCuYtlxtiNdcXvhTbQlFHnqURYvyBsIJnC0ecc G1MA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=M9rRADnD; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id x7-20020a05610223c700b0041aab766b94si3956130vsr.645.2023.03.16.00.31.06; Thu, 16 Mar 2023 00:31:20 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=M9rRADnD; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229494AbjCPHOf (ORCPT + 99 others); Thu, 16 Mar 2023 03:14:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42068 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230154AbjCPHOU (ORCPT ); Thu, 16 Mar 2023 03:14:20 -0400 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B8D805AB41; Thu, 16 Mar 2023 00:13:53 -0700 (PDT) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 32G7CiMI024713; Thu, 16 Mar 2023 02:12:44 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1678950764; bh=TISRczCqqClgTnuh9Jgbp4YdFIC7Href1UTZ0gVUQ5I=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=M9rRADnDewqbA3YDmtWCOfOy9h/5K28Zxl9MHHy0q29lnvsB/BrBUxK+Vkjq/cQWY 1XuEM7lnCTO6a5qUCRY8WCjOv6rjFkbHjtcm2vP0QpZR+rF4gdBQ8meet1EBpy0lFx 1KBScDnWdNNDeICFw7/Eb6mjAcM9OMfngNBI6yDI= Received: from DLEE110.ent.ti.com (dlee110.ent.ti.com [157.170.170.21]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 32G7Ciim005183 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 16 Mar 2023 02:12:44 -0500 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Thu, 16 Mar 2023 02:12:44 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Thu, 16 Mar 2023 02:12:44 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 32G7ChiY126728; Thu, 16 Mar 2023 02:12:44 -0500 From: Achal Verma To: Tom Joseph , Lorenzo Pieralisi , Rob Herring , Krzysztof Wilczy_ski , Bjorn Helgaas , Vignesh Raghavendra CC: , , , , Achal Verma , Milind Parab , Subject: [PATCH v10 3/5] PCI: j721e: Add PCIe 4x lane selection support Date: Thu, 16 Mar 2023 12:42:36 +0530 Message-ID: <20230316071238.200992-4-a-verma1@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230316071238.200992-1-a-verma1@ti.com> References: <20230316071238.200992-1-a-verma1@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1760508646929388349?= X-GMAIL-MSGID: =?utf-8?q?1760508646929388349?= From: Matt Ranostay Add support for setting of two-bit field that allows selection of 4x lane PCIe which was previously limited to only 2x lanes. Signed-off-by: Matt Ranostay Reviewed-by: Vignesh Raghavendra Reviewed-by: Roger Quadros Signed-off-by: Achal Verma --- drivers/pci/controller/cadence/pci-j721e.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c index f4dc2c5abedb..58dcac9021e4 100644 --- a/drivers/pci/controller/cadence/pci-j721e.c +++ b/drivers/pci/controller/cadence/pci-j721e.c @@ -42,7 +42,6 @@ enum link_status { }; #define J721E_MODE_RC BIT(7) -#define LANE_COUNT_MASK BIT(8) #define LANE_COUNT(n) ((n) << 8) #define GENERATION_SEL_MASK GENMASK(1, 0) @@ -52,6 +51,7 @@ struct j721e_pcie { struct clk *refclk; u32 mode; u32 num_lanes; + u32 max_lanes; void __iomem *user_cfg_base; void __iomem *intd_cfg_base; u32 linkdown_irq_regfield; @@ -205,11 +205,15 @@ static int j721e_pcie_set_lane_count(struct j721e_pcie *pcie, { struct device *dev = pcie->cdns_pcie->dev; u32 lanes = pcie->num_lanes; + u32 mask = BIT(8); u32 val = 0; int ret; + if (pcie->max_lanes == 4) + mask = GENMASK(9, 8); + val = LANE_COUNT(lanes - 1); - ret = regmap_update_bits(syscon, offset, LANE_COUNT_MASK, val); + ret = regmap_update_bits(syscon, offset, mask, val); if (ret) dev_err(dev, "failed to set link count\n"); @@ -441,7 +445,9 @@ static int j721e_pcie_probe(struct platform_device *pdev) dev_warn(dev, "num-lanes property not provided or invalid, setting num-lanes to 1\n"); num_lanes = 1; } + pcie->num_lanes = num_lanes; + pcie->max_lanes = data->max_lanes; if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48))) return -EINVAL; From patchwork Thu Mar 16 07:12:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Achal Verma X-Patchwork-Id: 70603 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:604a:0:0:0:0:0 with SMTP id j10csp332751wrt; Thu, 16 Mar 2023 00:25:41 -0700 (PDT) X-Google-Smtp-Source: AK7set/85LBbYC7nmteWavHEncVnMiG+sfCp3Z5sTXpIatEJNTUKAfmsPwkvAU8XaLVjQrIXJT3/ X-Received: by 2002:a17:90b:1bd0:b0:234:1621:3792 with SMTP id oa16-20020a17090b1bd000b0023416213792mr2906716pjb.4.1678951541177; Thu, 16 Mar 2023 00:25:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1678951541; cv=none; d=google.com; s=arc-20160816; b=1HtG6dBgD8PfrBPqtbGASgF/Ij9peU8LMSV1d2RUUqnsShL+c5ic0DzljkEQCqfujW Qo4ZdGj5gmUh7PTc72d3qJp/0KnKEnCUrqjvDGyApRpXRbc7l7H6+IRs3aFWnrJ66rz1 SXHplQkWQ4lMog7Msi4aJyo3jn43aibX10yNAtzKLtSF3N8D5o1rPzjUmOzFtXFSj7P7 bWAAKScz/3Wlrh7y78cWPpU4C5kYEMpJr+8+K+99XQJklx0D83y9ao9oZQfJtyEsyZnz oFLx4U/B5gwQje+G3X5xirJ0KhiPAA/1LGY4JaO5DdiDcXcyXZcq0P1uG4WbFl3uoAQI HLrg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=/KtIEHYVe129q/U6+XWH0X7x8R+UBCCGDZvXUUhmAPA=; b=H5AmfoUxWSYbNyNtgECSKDzfyjcedPlYZGc9y24+jS5woQvpdZvRhdFct8bP5M25LA 5y3BAtwQf+jG1gZgAOwimegAKuVe9kRnWQ4Isz4nwiuFLQTSWU5dpFjiwRZTQV5hFVRp RZTz7KjDcWodRPjPG9RZ0EhhPmKZXMQqfiPlqca03sElfzf2Q2vxR68xArjUDNEGounc W2H+BMGkjhFL6i7YdzQpN0okaH3HivBhcZiZLyO7+IY9nSPduAW98VRjKujsOdKV5kRW 5F1AFiMWV49XV9+jM2vWIN9CYL52aSOxaakjqmmhEnjOMzuxPPIYuh+qjkU+JCvKGjGh rlGQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=FvNVnpbT; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id mm5-20020a17090b358500b0023d02932015si3668223pjb.40.2023.03.16.00.25.26; Thu, 16 Mar 2023 00:25:41 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=FvNVnpbT; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230096AbjCPHOb (ORCPT + 99 others); Thu, 16 Mar 2023 03:14:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42024 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230061AbjCPHOQ (ORCPT ); Thu, 16 Mar 2023 03:14:16 -0400 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 90B35AF2B8; Thu, 16 Mar 2023 00:13:52 -0700 (PDT) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 32G7CkQ3018063; Thu, 16 Mar 2023 02:12:46 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1678950766; bh=/KtIEHYVe129q/U6+XWH0X7x8R+UBCCGDZvXUUhmAPA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=FvNVnpbTigLo6HFRLt1ywnOKOgEBasJ4FQOdFkQTclbqjEUdBZm4h7WkswfBAmcqR GzH+mE1q7HcKl7O1TbyWczfDowGwvBAEKHMKU6dchn08NtMem2T6nLW62naIdUvttl yNPEMm/LONZSqbGzZAZ5FOc8jDricXvkRP3TYOmU= Received: from DFLE111.ent.ti.com (dfle111.ent.ti.com [10.64.6.32]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 32G7Ckkw058096 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 16 Mar 2023 02:12:46 -0500 Received: from DFLE101.ent.ti.com (10.64.6.22) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Thu, 16 Mar 2023 02:12:45 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Thu, 16 Mar 2023 02:12:45 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 32G7CjlT032375; Thu, 16 Mar 2023 02:12:45 -0500 From: Achal Verma To: Tom Joseph , Lorenzo Pieralisi , Rob Herring , Krzysztof Wilczy_ski , Bjorn Helgaas , Vignesh Raghavendra CC: , , , , Achal Verma , Milind Parab , Subject: [PATCH v10 4/5] dt-bindings: PCI: ti,j721e-pci-*: add j784s4-pci-* compatible strings Date: Thu, 16 Mar 2023 12:42:37 +0530 Message-ID: <20230316071238.200992-5-a-verma1@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230316071238.200992-1-a-verma1@ti.com> References: <20230316071238.200992-1-a-verma1@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1760508290938712175?= X-GMAIL-MSGID: =?utf-8?q?1760508290938712175?= From: Matt Ranostay Add definition for j784s4-pci-ep + j784s4-pci-host devices along with schema checks for num-lanes. Signed-off-by: Matt Ranostay Acked-by: Krzysztof Kozlowski Signed-off-by: Achal Verma --- .../devicetree/bindings/pci/ti,j721e-pci-ep.yaml | 12 ++++++++++++ .../devicetree/bindings/pci/ti,j721e-pci-host.yaml | 12 ++++++++++++ 2 files changed, 24 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml index 32e0c70ed801..d2fbf1f7aa54 100644 --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml @@ -14,6 +14,7 @@ properties: compatible: oneOf: - const: ti,j721e-pcie-ep + - const: ti,j784s4-pcie-ep - description: PCIe EP controller in AM64 items: - const: ti,am64-pcie-ep @@ -86,6 +87,17 @@ allOf: minimum: 1 maximum: 2 + - if: + properties: + compatible: + enum: + - ti,j784s4-pcie-ep + then: + properties: + num-lanes: + minimum: 1 + maximum: 4 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml index 2547088304e5..e41d6f403493 100644 --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml @@ -14,6 +14,7 @@ properties: compatible: oneOf: - const: ti,j721e-pcie-host + - const: ti,j784s4-pcie-host - description: PCIe controller in AM64 items: - const: ti,am64-pcie-host @@ -115,6 +116,17 @@ allOf: minimum: 1 maximum: 2 + - if: + properties: + compatible: + enum: + - ti,j784s4-pcie-host + then: + properties: + num-lanes: + minimum: 1 + maximum: 4 + required: - compatible - reg From patchwork Thu Mar 16 07:12:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Achal Verma X-Patchwork-Id: 70609 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:604a:0:0:0:0:0 with SMTP id j10csp335112wrt; Thu, 16 Mar 2023 00:32:09 -0700 (PDT) X-Google-Smtp-Source: AK7set+kGW0EnszYTJphyqd8v/6B3xkmSPqO3JszWF9t6U/OVau4gxQRb/1+uAVvERqyw++DFhML X-Received: by 2002:a67:fc9a:0:b0:421:5d63:58aa with SMTP id x26-20020a67fc9a000000b004215d6358aamr24427597vsp.18.1678951929045; Thu, 16 Mar 2023 00:32:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1678951929; cv=none; d=google.com; s=arc-20160816; b=RUlL20A2MLMVrPtaZRbqumzz5u6xPEpUihJeaxZzwrGg4SORapSaBQh7dJJzK7G5uX DW+CngeVGnPmo/Yc38aAUCRGD/nxSDW44Z+dp8W+nVJVpMWpdrMVmJCq4dlrBaG/UUt7 2g0WYOueoO7YbT5KZzCMuIxXy07M98BgSM+Xu11zF7I/agv3bGhPjufMkwR/I8vJW31b 3ajahPEtiFUUEiDOKGLeIShaEXTBU9t3EaZuVWSknnlLsDQbEt77+VhcOsxB8DabCPCE 1LNY6zVLpCpJgoL2AbVMb/WR7abEU9JRFChXV31c5XmjixMI/dqdK624oCEOM3SOWCJ+ razQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=GGrsVB2NuWgQ/IDsTg782FJLIK98IZjp/7pCe7Mspxs=; b=OCLdOFHw6GMleXeZ87iyZbHeZCaEy0CQydrKgWJTfig+gSq69T9/BiMkNlkV8Xd5cX nM49NGZTLg8MtyOQj1lXoWsdMPS7zptSTvcAWk5grYJoYo9m8B/bMO37+v0uLm+kJhDU LL69v9fgxPeH6smyAat9CT5zIgsTJKcseirTGwP7x+89pVrV+QHh5+BT7zcicBTbsJw4 71NxvuTm92kz0UAExlVf17Y12Mhe+IDv+5SQtUS8A0fVPoslX9D0ppB0d5NjbaRMm6io mIIdk/tWA5D6WIGzyu2yGAtKXEqAsZFvjCXguU6wa6sL4Lo5fwpIh9unXmPNuuxhbMjv UbhA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=H7oIJQxF; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from out1.vger.email (out1.vger.email. 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Tested-by: Achal Verma Signed-off-by: Matt Ranostay Reviewed-by: Roger Quadros Signed-off-by: Achal Verma --- drivers/pci/controller/cadence/pci-j721e.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c index 58dcac9021e4..cce7b391f931 100644 --- a/drivers/pci/controller/cadence/pci-j721e.c +++ b/drivers/pci/controller/cadence/pci-j721e.c @@ -330,6 +330,20 @@ static const struct j721e_pcie_data am64_pcie_ep_data = { .max_lanes = 1, }; +static const struct j721e_pcie_data j784s4_pcie_rc_data = { + .mode = PCI_MODE_RC, + .quirk_retrain_flag = true, + .byte_access_allowed = false, + .linkdown_irq_regfield = LINK_DOWN, + .max_lanes = 4, +}; + +static const struct j721e_pcie_data j784s4_pcie_ep_data = { + .mode = PCI_MODE_EP, + .linkdown_irq_regfield = LINK_DOWN, + .max_lanes = 4, +}; + static const struct of_device_id of_j721e_pcie_match[] = { { .compatible = "ti,j721e-pcie-host", @@ -355,6 +369,14 @@ static const struct of_device_id of_j721e_pcie_match[] = { .compatible = "ti,am64-pcie-ep", .data = &am64_pcie_ep_data, }, + { + .compatible = "ti,j784s4-pcie-host", + .data = &j784s4_pcie_rc_data, + }, + { + .compatible = "ti,j784s4-pcie-ep", + .data = &j784s4_pcie_ep_data, + }, {}, };