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Thu, 16 Mar 2023 05:34:34 GMT Received: from smtpav06.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id CB85420049; Thu, 16 Mar 2023 05:34:34 +0000 (GMT) Received: from smtpav06.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 508FE20043; Thu, 16 Mar 2023 05:34:33 +0000 (GMT) Received: from [9.200.144.91] (unknown [9.200.144.91]) by smtpav06.fra02v.mail.ibm.com (Postfix) with ESMTP; Thu, 16 Mar 2023 05:34:33 +0000 (GMT) Message-ID: <22e83da3-a81f-dd61-c04b-a39b459a965f@linux.ibm.com> Date: Thu, 16 Mar 2023 13:34:32 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.8.0 Subject: [PATCH-1, rs6000] Put constant into pseudo at expand when it needs two insns [PR86106] To: gcc-patches Cc: Segher Boessenkool , David , "Kewen.Lin" , Peter Bergner Content-Language: en-US X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: ScT0nWzI9beO1hLbVQl-KfWGQAPdTh1M X-Proofpoint-GUID: 7qi5Kbtq-SfNDHcaDtd492p3o8H7HDZX X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-16_03,2023-03-15_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 mlxscore=0 malwarescore=0 spamscore=0 lowpriorityscore=0 suspectscore=0 mlxlogscore=999 bulkscore=0 impostorscore=0 adultscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303150002 definitions=main-2303160046 X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: HAO CHEN GUI via Gcc-patches From: HAO CHEN GUI Reply-To: HAO CHEN GUI Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1760501355700496103?= X-GMAIL-MSGID: =?utf-8?q?1760501355700496103?= Hi, Currently, rs6000 directly expands to 2 insns if an integer constant is the second operand and it needs two insns. For example, addi/addis and ori/oris. It may not benefit when the constant is used for more than 2 times in an extended basic block, just like the case in PR shows. One possible solution is to force the constant in pseudo at expand and let propagation pass and combine pass decide if the pseudo should be replaced with the constant or not by comparing the rtx/insn cost. It generates a constant move if the constant is forced to a pseudo. There is one constant move if it's used only once. The combine pass can combine the constant move and add/ior/xor insn and eliminate the move as the insn cost reduces. There are multiple moves if the constant is used for several times. In an extended basic block, these constant moves are merged to one by propagation pass. The combine pass can't replace the pseudo with the constant as it is no cost saving. In an extreme case, the constant is used twice in an extended basic block. The cost(latency) is unchanged between putting constant in pseudo and generating 2 insns. The dependence of instructions reduces but one more register is used. In other case, it should be always optimal to put constant in a pseudo. This patch changes the expander of integer add and force constant to a pseudo when it needs 2 insn. Also a combine and split pattern is defined. Bootstrapped and tested on powerpc64-linux BE and LE with no regressions. Thanks Gui Haochen ChangeLog 2023-03-14 Haochen Gui gcc/ * config/rs6000/predicates.md (add_2insn_cint_operand): New predicate which returns true when op is a 32-bit but not a 16-bit signed integer constant. * config/rs6000/rs6000.md (add3): Put the second operand into register when it's a constant and need 2 add insns. (*add_2insn): New insn_and_split for 2-insn add. patch.diff diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index a1764018545..09e59a48cd3 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -282,6 +282,13 @@ (define_predicate "s32bit_cint_operand" (and (match_code "const_int") (match_test "(0x80000000 + UINTVAL (op)) >> 32 == 0"))) +;; Return 1 if op is a 32-bit but not 16-bit constant signed integer +(define_predicate "add_2insn_cint_operand" + (and (match_code "const_int") + (and (match_operand 0 "s32bit_cint_operand") + (and (not (match_operand 0 "short_cint_operand")) + (not (match_operand 0 "upper16_cint_operand")))))) + ;; Return 1 if op is a constant 32-bit unsigned (define_predicate "c32bit_cint_operand" (and (match_code "const_int") diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 6011f5bf76a..dba41e3df90 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -1796,12 +1796,44 @@ (define_expand "add3" /* The ordering here is important for the prolog expander. When space is allocated from the stack, adding 'low' first may produce a temporary deallocation (which would be bad). */ - emit_insn (gen_add3 (tmp, operands[1], GEN_INT (rest))); - emit_insn (gen_add3 (operands[0], tmp, GEN_INT (low))); - DONE; + if (!can_create_pseudo_p ()) + { + emit_insn (gen_add3 (tmp, operands[1], GEN_INT (rest))); + emit_insn (gen_add3 (operands[0], tmp, GEN_INT (low))); + DONE; + } + + operands[2] = force_reg (mode, operands[2]); } }) +/* The ordering here is important for the prolog expander. + When space is allocated from the stack, adding 'low' first may + produce a temporary deallocation (which would be bad). */ + +(define_insn_and_split "*add_2insn" + [(set (match_operand:GPR 0 "gpc_reg_operand" "=b") + (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%b") + (match_operand:GPR 2 "add_2insn_cint_operand" "n")))] + "!TARGET_PREFIXED" + "#" + "&& 1" + [(set (match_dup 0) + (plus:GPR (match_dup 1) + (match_dup 3))) + (set (match_dup 0) + (plus:GPR (match_dup 0) + (match_dup 4)))] +{ + HOST_WIDE_INT val = INTVAL (operands[2]); + HOST_WIDE_INT low = sext_hwi (val, 16); + HOST_WIDE_INT rest = trunc_int_for_mode (val - low, mode); + + operands[3] = GEN_INT (rest); + operands[4] = GEN_INT (low); +} + [(set_attr "length" "8")]) + (define_insn "*add3" [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,r,r") (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,b,b")