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[83.9.29.16]) by smtp.gmail.com with ESMTPSA id b8-20020ac25e88000000b004e845a08567sm824678lfq.291.2023.03.15.07.11.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Mar 2023 07:11:25 -0700 (PDT) From: Konrad Dybcio Date: Wed, 15 Mar 2023 15:11:19 +0100 Subject: [PATCH v3 1/7] dt-bindings: interconnect: qcom,msm8998-bwmon: Resolve MSM8998 support MIME-Version: 1.0 Message-Id: <20230304-topic-ddr_bwmon-v3-1-77a050c2fbda@linaro.org> References: <20230304-topic-ddr_bwmon-v3-0-77a050c2fbda@linaro.org> In-Reply-To: <20230304-topic-ddr_bwmon-v3-0-77a050c2fbda@linaro.org> To: Andy Gross , Bjorn Andersson , Krzysztof Kozlowski , Georgi Djakov , Rob Herring , Thara Gopinath , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , Marijn Suijten X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1678889480; l=3198; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=46GX24BwrnA0NyNxXdAtsdOmycpBdNb3M3oef2DCgaI=; b=WWKutA0jBcYE25QwX++BpXSspC7Fp3hZSBClmXDaadptiAxrADsX0C6EleInwHhzoTY6QeHRr0wi ctno1RGrAPxxz5R0JFl7Uhj6Hej8dn8hVdWghI/57tb9b+q51Gx8 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-0.2 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_SORBS_HTTP,RCVD_IN_SORBS_SOCKS,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1760444637664018443?= X-GMAIL-MSGID: =?utf-8?q?1760444637664018443?= BWMONv4 has two sets of registers: one for handling the monitor itself and one called "global" which hosts some sort of a headswitch and an interrupt control register. We did not handle that one before, as on SoCs starting with SDM845 they have been merged into a single contiguous range. To make the qcom,msm8998-bwmon less confusing and in preparation for actual MSM8998 support, describe the global register space and introduce new "qcom,sdm845-cpu-bwmon" compatible while keeping the "qcom,sdm845-bwmon" as a fallback for SoCs with this merged register space scheme. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio --- .../bindings/interconnect/qcom,msm8998-bwmon.yaml | 41 ++++++++++++++++++---- 1 file changed, 34 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml b/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml index 12a0d3ecbabb..5d17bdcfdf70 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml @@ -22,14 +22,14 @@ description: | properties: compatible: oneOf: + - const: qcom,msm8998-bwmon # BWMON v4 - items: - enum: - qcom,sc7280-cpu-bwmon - qcom,sc8280xp-cpu-bwmon - - qcom,sdm845-bwmon + - qcom,sdm845-cpu-bwmon - qcom,sm8550-cpu-bwmon - - const: qcom,msm8998-bwmon - - const: qcom,msm8998-bwmon # BWMON v4 + - const: qcom,sdm845-bwmon # BWMON v4, unified register space - items: - enum: - qcom,sc8280xp-llcc-bwmon @@ -49,9 +49,13 @@ properties: type: object reg: - # BWMON v4 (currently described) and BWMON v5 use one register address - # space. BWMON v2 uses two register spaces - not yet described. - maxItems: 1 + # BWMON v5 uses one register address space, v1-v4 use one or two. + minItems: 1 + maxItems: 2 + + reg-names: + minItems: 1 + maxItems: 2 required: - compatible @@ -63,13 +67,36 @@ required: additionalProperties: false +allOf: + - if: + properties: + compatible: + const: qcom,msm8998-bwmon + then: + properties: + reg: + minItems: 2 + + reg-names: + items: + - const: monitor + - const: global + + else: + properties: + reg: + maxItems: 1 + + reg-names: + maxItems: 1 + examples: - | #include #include pmu@1436400 { - compatible = "qcom,sdm845-bwmon", "qcom,msm8998-bwmon"; + compatible = "qcom,sdm845-cpu-bwmon", "qcom,sdm845-bwmon"; reg = <0x01436400 0x600>; interrupts = ; interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_LLCC 3>; From patchwork Wed Mar 15 14:11:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 70256 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp2366052wrd; Wed, 15 Mar 2023 07:36:35 -0700 (PDT) X-Google-Smtp-Source: AK7set+wfNMq/lnTrXNOYWs8uB/+QlZrDZjxw9PL0oa5rAdpvT6ProP4wXGHlseg0E6Olyt0TIJb X-Received: by 2002:a17:90a:6090:b0:23d:1948:667d with SMTP id z16-20020a17090a609000b0023d1948667dmr8301975pji.35.1678890994721; Wed, 15 Mar 2023 07:36:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1678890994; cv=none; d=google.com; s=arc-20160816; b=JswyXCp0LihBDYeXKA1D7CD6xDzQP0r8KjYRuMLm+jEygcHAqaVhTTwL5CZW6miQTz a6HkfMb0Cnbsi3qT/Cu0syMGBvz+AEZAOoHyG4zLLSPHIVqOdBkI1SmVBdGK96AV6Q6n gm6WUUE087ssncK3JsubhLkMLt2HCMTvna6xg17/cgPYIjsfu+9myEEDWiFLg0OsNKRx 8b6oyLyFFN6YRiyuDNEskTE6urwIRjko4rEqukqVaGmiNMLbMbR+OMjn6g9ZL9ZRAfqb TTJKfWy0S5CtPfGPKOZkvoLmgHv/AzI/u5OveOotHvvr/1U2CA2PnQVhNmWDFPF7bL7d P5ZQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=3GQC372p350UPtIPazu4oAK/bKFzzByhaQ607sxvNsw=; b=CrN6HpWYnoOUeh/dMNo4xP7Hp5LlybjH1vRAkF5rM51hAwD/esw3QICIsGBbtm4BXk +Vv0cI8tKO6ZcLUeylfvbfOHS0R0WTCpyR+Mj3XvLvaRCEIOVfICbMn7KlweLig52Chn KYKU9LSrrsaIxt9YQKUySPj93nTKahHR3hPJa+/zP02AdwHFvkds6GUxRSOTgUb3arMe cZxj8HCxlMVUCMKPmJzr/Y1TCydF1QanuII6RMZCp+XDV0lmSXB2KP+4oThXU2jnftF+ 9wUZccSX5vGXFCOwF+GzfWqxjJrv/2v33ERn3ZH8PcLLwWCx8rw/5u1iPG8jJKm/XUIb htGw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bMCLdOfJ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[83.9.29.16]) by smtp.gmail.com with ESMTPSA id b8-20020ac25e88000000b004e845a08567sm824678lfq.291.2023.03.15.07.11.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Mar 2023 07:11:27 -0700 (PDT) From: Konrad Dybcio Date: Wed, 15 Mar 2023 15:11:20 +0100 Subject: [PATCH v3 2/7] soc: qcom: icc-bwmon: Remove unused struct member MIME-Version: 1.0 Message-Id: <20230304-topic-ddr_bwmon-v3-2-77a050c2fbda@linaro.org> References: <20230304-topic-ddr_bwmon-v3-0-77a050c2fbda@linaro.org> In-Reply-To: <20230304-topic-ddr_bwmon-v3-0-77a050c2fbda@linaro.org> To: Andy Gross , Bjorn Andersson , Krzysztof Kozlowski , Georgi Djakov , Rob Herring , Thara Gopinath , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , Marijn Suijten X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1678889480; l=829; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=GxK3RcvPqvln4dblV3dJH1wiiHqaQgKRfsfh0wbDHFI=; b=IUdpG314IQktpj0Td1iiXq+sbbjJkBs31p8n7U7SlhJh3ZNTYng5PeMJKje6xOBOjPvqSKy7MQgE SY083UvyAnLJYhlQyxXXqSPDcNogGDYi64sglWLpWELQH3mkFn86 X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-0.2 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_SORBS_HTTP,RCVD_IN_SORBS_SOCKS,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1760444804168754893?= X-GMAIL-MSGID: =?utf-8?q?1760444804168754893?= bwmon->regmap was never used, as the regmap for bwmon is registered through devres and accessed through bwmon's regmap_field members. Remove it Fixes: ec63dcd3c863 ("soc: qcom: icc-bwmon: use regmap and prepare for BWMON v5") Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio --- drivers/soc/qcom/icc-bwmon.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/soc/qcom/icc-bwmon.c b/drivers/soc/qcom/icc-bwmon.c index d07be3700db6..d45caf512e2d 100644 --- a/drivers/soc/qcom/icc-bwmon.c +++ b/drivers/soc/qcom/icc-bwmon.c @@ -164,7 +164,6 @@ struct icc_bwmon { const struct icc_bwmon_data *data; int irq; - struct regmap *regmap; struct regmap_field *regs[F_NUM_FIELDS]; unsigned int max_bw_kbps; From patchwork Wed Mar 15 14:11:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 70250 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp2364157wrd; Wed, 15 Mar 2023 07:33:01 -0700 (PDT) X-Google-Smtp-Source: AK7set8zASA4lDG+1XTqw/dUB9Bq1GTb3w2l4ve+Iu7PMHAP55FB7enYobRHn+UrtHy32SDDFbHp X-Received: by 2002:a17:902:ec8a:b0:19e:416e:abf5 with SMTP id x10-20020a170902ec8a00b0019e416eabf5mr2821091plg.34.1678890781597; Wed, 15 Mar 2023 07:33:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1678890781; cv=none; d=google.com; s=arc-20160816; b=tZn6KXuDEy+wo2tV4Vz4wXZn0LN2I0K1Rk+VIfkj6mZqTb2lby4RAqq2TUKIXQPUs+ GtXNIPq0P7RAE8VQweIL2CjxrVqRKWjS9OSfZr+MF1dFZ9WwYI6ZB2tu54S7WsxvVT+p NrJQI7mLZBY6f+vuUXBPAPPA3XNTDQF2vKFaM/VzGLgZi8tXhMENDy5SS+h7glbm/qx/ WHEbsVbrVN/TU4H3WtT7v0fNv97cs2RpGN/aU6Xep2Weaa0EYVORW0dGrRguoDNX7k3s /kkkplme0K1BadLfE4F5XNK/iJ6+YzPKrAMvRw4t6h1Nri6ikCFI/ZDEqR4VdyK97qix ES3g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=3N7Hjcr2PZGVfKJQdXc+HZpWhdde40yz4tbRtMjIzn4=; b=OgoQWyy0LERi4nXH9qWm6RqNJhKeFDr/n4NezDb+etN++rqXnpCnbrsv5CQR5BQf8q ps2d+u2J3XnD9qORP58wi11c2dbWmtOHhZ1heWs6x7/ivdYQh97dsX8+dGGL/nKvQCC7 Lg0zMYRZHf7PYky5JyGO56r/3ixISzNWHgpR7St47QXM9uS7SwoYTVDl5w032P9ncYhK rNrlNtQzsx64hrOampxs9HzQ+4Gad4Qe01gqlmLQZiQGwiISk1scQ/fnewB8kpsyMJHg CQcYdzkt6J28LE9RhnUpfSSjZeff2RBPi4Xuiv4ySSm2TSmJlIOLaC9FF+UL3dVrkMBO EbsQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xWHah0xm; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[83.9.29.16]) by smtp.gmail.com with ESMTPSA id b8-20020ac25e88000000b004e845a08567sm824678lfq.291.2023.03.15.07.11.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Mar 2023 07:11:30 -0700 (PDT) From: Konrad Dybcio Date: Wed, 15 Mar 2023 15:11:21 +0100 Subject: [PATCH v3 3/7] soc: qcom: icc-bwmon: Handle global registers correctly MIME-Version: 1.0 Message-Id: <20230304-topic-ddr_bwmon-v3-3-77a050c2fbda@linaro.org> References: <20230304-topic-ddr_bwmon-v3-0-77a050c2fbda@linaro.org> In-Reply-To: <20230304-topic-ddr_bwmon-v3-0-77a050c2fbda@linaro.org> To: Andy Gross , Bjorn Andersson , Krzysztof Kozlowski , Georgi Djakov , Rob Herring , Thara Gopinath , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , Marijn Suijten X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1678889480; l=15677; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=+E/FiEc3YfiZWKRvWhE0s83huKfmblgyJVvmNE9VGcc=; b=MPAGQUW9Hn2+Y1VtmbmgxsPZrEyIeps4lu8VO+suJiPkAhGBWt2wfTAjYfbEzRp/7UCvmuE3YWik imobrtXbCIjCvT3VEhaWelor1fEyCqL8MP545yd1ucTeR8YSJxvB X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-0.2 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_SORBS_HTTP,RCVD_IN_SORBS_SOCKS,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1760444579941726391?= X-GMAIL-MSGID: =?utf-8?q?1760444579941726391?= The BWMON hardware has two sets of registers: one for the monitor itself and one called "global". It has what seems to be some kind of a head switch and an interrupt control register. It's usually 0x200 in size. On fairly recent SoCs (with the starting point seemingly being moving the OSM programming to the firmware) these two register sets are contiguous and overlapping, like this (on sm8450): /* notice how base.start == global_base.start+0x100 */ reg = <0x90b6400 0x300>, <0x90b6300 0x200>; reg-names = "base", "global_base"; Which led to some confusion and the assumption that since the "interesting" global registers begin right after global_base+0x100, there's no need to map two separate regions and one can simply subtract 0x100 from the offsets. This is however not the case for anything older than SDM845, as the global region can appear in seemingly random spots on the register map. Handle the case where the global registers are mapped separately to allow proper functioning of BWMONv4 on MSM8998 and older. Add specific compatibles for 845, 8280xp, 7280 and 8550 (all of which use the single reg space scheme) to keep backwards compatibility with old DTs. Signed-off-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski --- drivers/soc/qcom/icc-bwmon.c | 230 +++++++++++++++++++++++++++++++++++++++---- 1 file changed, 209 insertions(+), 21 deletions(-) diff --git a/drivers/soc/qcom/icc-bwmon.c b/drivers/soc/qcom/icc-bwmon.c index d45caf512e2d..fd58c5b69897 100644 --- a/drivers/soc/qcom/icc-bwmon.c +++ b/drivers/soc/qcom/icc-bwmon.c @@ -34,14 +34,27 @@ /* Internal sampling clock frequency */ #define HW_TIMER_HZ 19200000 -#define BWMON_V4_GLOBAL_IRQ_CLEAR 0x008 -#define BWMON_V4_GLOBAL_IRQ_ENABLE 0x00c +#define BWMON_V4_GLOBAL_IRQ_CLEAR 0x108 +#define BWMON_V4_GLOBAL_IRQ_ENABLE 0x10c /* * All values here and further are matching regmap fields, so without absolute * register offsets. */ #define BWMON_V4_GLOBAL_IRQ_ENABLE_ENABLE BIT(0) +/* + * Starting with SDM845, the BWMON4 register space has changed a bit: + * the global registers were jammed into the beginning of the monitor region. + * To keep the proper offsets, one would have to map and + * , which is straight up wrong. + * To facilitate for that, while allowing the older, arguably more proper + * implementations to work, offset the global registers by -0x100 to avoid + * having to map half of the global registers twice. + */ +#define BWMON_V4_845_OFFSET 0x100 +#define BWMON_V4_GLOBAL_IRQ_CLEAR_845 (BWMON_V4_GLOBAL_IRQ_CLEAR - BWMON_V4_845_OFFSET) +#define BWMON_V4_GLOBAL_IRQ_ENABLE_845 (BWMON_V4_GLOBAL_IRQ_ENABLE - BWMON_V4_845_OFFSET) + #define BWMON_V4_IRQ_STATUS 0x100 #define BWMON_V4_IRQ_CLEAR 0x108 @@ -118,9 +131,13 @@ #define BWMON_NEEDS_FORCE_CLEAR BIT(1) enum bwmon_fields { + /* Global region fields, keep them at the top */ F_GLOBAL_IRQ_CLEAR, F_GLOBAL_IRQ_ENABLE, - F_IRQ_STATUS, + F_NUM_GLOBAL_FIELDS, + + /* Monitor region fields */ + F_IRQ_STATUS = F_NUM_GLOBAL_FIELDS, F_IRQ_CLEAR, F_IRQ_ENABLE, F_ENABLE, @@ -157,6 +174,9 @@ struct icc_bwmon_data { const struct regmap_config *regmap_cfg; const struct reg_field *regmap_fields; + + const struct regmap_config *global_regmap_cfg; + const struct reg_field *global_regmap_fields; }; struct icc_bwmon { @@ -165,6 +185,7 @@ struct icc_bwmon { int irq; struct regmap_field *regs[F_NUM_FIELDS]; + struct regmap_field *global_regs[F_NUM_GLOBAL_FIELDS]; unsigned int max_bw_kbps; unsigned int min_bw_kbps; @@ -174,8 +195,8 @@ struct icc_bwmon { /* BWMON v4 */ static const struct reg_field msm8998_bwmon_reg_fields[] = { - [F_GLOBAL_IRQ_CLEAR] = REG_FIELD(BWMON_V4_GLOBAL_IRQ_CLEAR, 0, 0), - [F_GLOBAL_IRQ_ENABLE] = REG_FIELD(BWMON_V4_GLOBAL_IRQ_ENABLE, 0, 0), + [F_GLOBAL_IRQ_CLEAR] = {}, + [F_GLOBAL_IRQ_ENABLE] = {}, [F_IRQ_STATUS] = REG_FIELD(BWMON_V4_IRQ_STATUS, 4, 7), [F_IRQ_CLEAR] = REG_FIELD(BWMON_V4_IRQ_CLEAR, 4, 7), [F_IRQ_ENABLE] = REG_FIELD(BWMON_V4_IRQ_ENABLE, 4, 7), @@ -201,7 +222,6 @@ static const struct reg_field msm8998_bwmon_reg_fields[] = { }; static const struct regmap_range msm8998_bwmon_reg_noread_ranges[] = { - regmap_reg_range(BWMON_V4_GLOBAL_IRQ_CLEAR, BWMON_V4_GLOBAL_IRQ_CLEAR), regmap_reg_range(BWMON_V4_IRQ_CLEAR, BWMON_V4_IRQ_CLEAR), regmap_reg_range(BWMON_V4_CLEAR, BWMON_V4_CLEAR), }; @@ -221,16 +241,33 @@ static const struct regmap_access_table msm8998_bwmon_reg_volatile_table = { .n_yes_ranges = ARRAY_SIZE(msm8998_bwmon_reg_volatile_ranges), }; +static const struct reg_field msm8998_bwmon_global_reg_fields[] = { + [F_GLOBAL_IRQ_CLEAR] = REG_FIELD(BWMON_V4_GLOBAL_IRQ_CLEAR, 0, 0), + [F_GLOBAL_IRQ_ENABLE] = REG_FIELD(BWMON_V4_GLOBAL_IRQ_ENABLE, 0, 0), +}; + +static const struct regmap_range msm8998_bwmon_global_reg_noread_ranges[] = { + regmap_reg_range(BWMON_V4_GLOBAL_IRQ_CLEAR, BWMON_V4_GLOBAL_IRQ_CLEAR), +}; + +static const struct regmap_access_table msm8998_bwmon_global_reg_read_table = { + .no_ranges = msm8998_bwmon_global_reg_noread_ranges, + .n_no_ranges = ARRAY_SIZE(msm8998_bwmon_global_reg_noread_ranges), +}; + /* * Fill the cache for non-readable registers only as rest does not really * matter and can be read from the device. */ static const struct reg_default msm8998_bwmon_reg_defaults[] = { - { BWMON_V4_GLOBAL_IRQ_CLEAR, 0x0 }, { BWMON_V4_IRQ_CLEAR, 0x0 }, { BWMON_V4_CLEAR, 0x0 }, }; +static const struct reg_default msm8998_bwmon_global_reg_defaults[] = { + { BWMON_V4_GLOBAL_IRQ_CLEAR, 0x0 }, +}; + static const struct regmap_config msm8998_bwmon_regmap_cfg = { .reg_bits = 32, .reg_stride = 4, @@ -251,6 +288,93 @@ static const struct regmap_config msm8998_bwmon_regmap_cfg = { .cache_type = REGCACHE_RBTREE, }; +static const struct regmap_config msm8998_bwmon_global_regmap_cfg = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + /* + * No concurrent access expected - driver has one interrupt handler, + * regmap is not shared, no driver or user-space API. + */ + .disable_locking = true, + .rd_table = &msm8998_bwmon_global_reg_read_table, + .reg_defaults = msm8998_bwmon_global_reg_defaults, + .num_reg_defaults = ARRAY_SIZE(msm8998_bwmon_global_reg_defaults), + /* + * Cache is necessary for using regmap fields with non-readable + * registers. + */ + .cache_type = REGCACHE_RBTREE, +}; + +static const struct reg_field sdm845_cpu_bwmon_reg_fields[] = { + [F_GLOBAL_IRQ_CLEAR] = REG_FIELD(BWMON_V4_GLOBAL_IRQ_CLEAR_845, 0, 0), + [F_GLOBAL_IRQ_ENABLE] = REG_FIELD(BWMON_V4_GLOBAL_IRQ_ENABLE_845, 0, 0), + [F_IRQ_STATUS] = REG_FIELD(BWMON_V4_IRQ_STATUS, 4, 7), + [F_IRQ_CLEAR] = REG_FIELD(BWMON_V4_IRQ_CLEAR, 4, 7), + [F_IRQ_ENABLE] = REG_FIELD(BWMON_V4_IRQ_ENABLE, 4, 7), + /* F_ENABLE covers entire register to disable other features */ + [F_ENABLE] = REG_FIELD(BWMON_V4_ENABLE, 0, 31), + [F_CLEAR] = REG_FIELD(BWMON_V4_CLEAR, 0, 1), + [F_SAMPLE_WINDOW] = REG_FIELD(BWMON_V4_SAMPLE_WINDOW, 0, 23), + [F_THRESHOLD_HIGH] = REG_FIELD(BWMON_V4_THRESHOLD_HIGH, 0, 11), + [F_THRESHOLD_MED] = REG_FIELD(BWMON_V4_THRESHOLD_MED, 0, 11), + [F_THRESHOLD_LOW] = REG_FIELD(BWMON_V4_THRESHOLD_LOW, 0, 11), + [F_ZONE_ACTIONS_ZONE0] = REG_FIELD(BWMON_V4_ZONE_ACTIONS, 0, 7), + [F_ZONE_ACTIONS_ZONE1] = REG_FIELD(BWMON_V4_ZONE_ACTIONS, 8, 15), + [F_ZONE_ACTIONS_ZONE2] = REG_FIELD(BWMON_V4_ZONE_ACTIONS, 16, 23), + [F_ZONE_ACTIONS_ZONE3] = REG_FIELD(BWMON_V4_ZONE_ACTIONS, 24, 31), + [F_THRESHOLD_COUNT_ZONE0] = REG_FIELD(BWMON_V4_THRESHOLD_COUNT, 0, 7), + [F_THRESHOLD_COUNT_ZONE1] = REG_FIELD(BWMON_V4_THRESHOLD_COUNT, 8, 15), + [F_THRESHOLD_COUNT_ZONE2] = REG_FIELD(BWMON_V4_THRESHOLD_COUNT, 16, 23), + [F_THRESHOLD_COUNT_ZONE3] = REG_FIELD(BWMON_V4_THRESHOLD_COUNT, 24, 31), + [F_ZONE0_MAX] = REG_FIELD(BWMON_V4_ZONE_MAX(0), 0, 11), + [F_ZONE1_MAX] = REG_FIELD(BWMON_V4_ZONE_MAX(1), 0, 11), + [F_ZONE2_MAX] = REG_FIELD(BWMON_V4_ZONE_MAX(2), 0, 11), + [F_ZONE3_MAX] = REG_FIELD(BWMON_V4_ZONE_MAX(3), 0, 11), +}; + +static const struct regmap_range sdm845_cpu_bwmon_reg_noread_ranges[] = { + regmap_reg_range(BWMON_V4_GLOBAL_IRQ_CLEAR_845, BWMON_V4_GLOBAL_IRQ_CLEAR_845), + regmap_reg_range(BWMON_V4_IRQ_CLEAR, BWMON_V4_IRQ_CLEAR), + regmap_reg_range(BWMON_V4_CLEAR, BWMON_V4_CLEAR), +}; + +static const struct regmap_access_table sdm845_cpu_bwmon_reg_read_table = { + .no_ranges = sdm845_cpu_bwmon_reg_noread_ranges, + .n_no_ranges = ARRAY_SIZE(sdm845_cpu_bwmon_reg_noread_ranges), +}; + +/* + * Fill the cache for non-readable registers only as rest does not really + * matter and can be read from the device. + */ +static const struct reg_default sdm845_cpu_bwmon_reg_defaults[] = { + { BWMON_V4_GLOBAL_IRQ_CLEAR_845, 0x0 }, + { BWMON_V4_IRQ_CLEAR, 0x0 }, + { BWMON_V4_CLEAR, 0x0 }, +}; + +static const struct regmap_config sdm845_cpu_bwmon_regmap_cfg = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + /* + * No concurrent access expected - driver has one interrupt handler, + * regmap is not shared, no driver or user-space API. + */ + .disable_locking = true, + .rd_table = &sdm845_cpu_bwmon_reg_read_table, + .volatile_table = &msm8998_bwmon_reg_volatile_table, + .reg_defaults = sdm845_cpu_bwmon_reg_defaults, + .num_reg_defaults = ARRAY_SIZE(sdm845_cpu_bwmon_reg_defaults), + /* + * Cache is necessary for using regmap fields with non-readable + * registers. + */ + .cache_type = REGCACHE_RBTREE, +}; + /* BWMON v5 */ static const struct reg_field sdm845_llcc_bwmon_reg_fields[] = { [F_GLOBAL_IRQ_CLEAR] = {}, @@ -349,6 +473,13 @@ static void bwmon_clear_counters(struct icc_bwmon *bwmon, bool clear_all) static void bwmon_clear_irq(struct icc_bwmon *bwmon) { + struct regmap_field *global_irq_clr; + + if (bwmon->data->global_regmap_fields) + global_irq_clr = bwmon->global_regs[F_GLOBAL_IRQ_CLEAR]; + else + global_irq_clr = bwmon->regs[F_GLOBAL_IRQ_CLEAR]; + /* * Clear zone and global interrupts. The order and barriers are * important. Quoting downstream Qualcomm msm-4.9 tree: @@ -369,15 +500,22 @@ static void bwmon_clear_irq(struct icc_bwmon *bwmon) if (bwmon->data->quirks & BWMON_NEEDS_FORCE_CLEAR) regmap_field_force_write(bwmon->regs[F_IRQ_CLEAR], 0); if (bwmon->data->quirks & BWMON_HAS_GLOBAL_IRQ) - regmap_field_force_write(bwmon->regs[F_GLOBAL_IRQ_CLEAR], + regmap_field_force_write(global_irq_clr, BWMON_V4_GLOBAL_IRQ_ENABLE_ENABLE); } static void bwmon_disable(struct icc_bwmon *bwmon) { + struct regmap_field *global_irq_en; + + if (bwmon->data->global_regmap_fields) + global_irq_en = bwmon->global_regs[F_GLOBAL_IRQ_ENABLE]; + else + global_irq_en = bwmon->regs[F_GLOBAL_IRQ_ENABLE]; + /* Disable interrupts. Strict ordering, see bwmon_clear_irq(). */ if (bwmon->data->quirks & BWMON_HAS_GLOBAL_IRQ) - regmap_field_write(bwmon->regs[F_GLOBAL_IRQ_ENABLE], 0x0); + regmap_field_write(global_irq_en, 0x0); regmap_field_write(bwmon->regs[F_IRQ_ENABLE], 0x0); /* @@ -389,10 +527,18 @@ static void bwmon_disable(struct icc_bwmon *bwmon) static void bwmon_enable(struct icc_bwmon *bwmon, unsigned int irq_enable) { + struct regmap_field *global_irq_en; + + if (bwmon->data->global_regmap_fields) + global_irq_en = bwmon->global_regs[F_GLOBAL_IRQ_ENABLE]; + else + global_irq_en = bwmon->regs[F_GLOBAL_IRQ_ENABLE]; + /* Enable interrupts */ if (bwmon->data->quirks & BWMON_HAS_GLOBAL_IRQ) - regmap_field_write(bwmon->regs[F_GLOBAL_IRQ_ENABLE], + regmap_field_write(global_irq_en, BWMON_V4_GLOBAL_IRQ_ENABLE_ENABLE); + regmap_field_write(bwmon->regs[F_IRQ_ENABLE], irq_enable); /* Enable bwmon */ @@ -555,7 +701,9 @@ static int bwmon_init_regmap(struct platform_device *pdev, struct device *dev = &pdev->dev; void __iomem *base; struct regmap *map; + int ret; + /* Map the monitor base */ base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(base)) return dev_err_probe(dev, PTR_ERR(base), @@ -566,12 +714,35 @@ static int bwmon_init_regmap(struct platform_device *pdev, return dev_err_probe(dev, PTR_ERR(map), "failed to initialize regmap\n"); + BUILD_BUG_ON(ARRAY_SIZE(msm8998_bwmon_global_reg_fields) != F_NUM_GLOBAL_FIELDS); BUILD_BUG_ON(ARRAY_SIZE(msm8998_bwmon_reg_fields) != F_NUM_FIELDS); + BUILD_BUG_ON(ARRAY_SIZE(sdm845_cpu_bwmon_reg_fields) != F_NUM_FIELDS); BUILD_BUG_ON(ARRAY_SIZE(sdm845_llcc_bwmon_reg_fields) != F_NUM_FIELDS); - return devm_regmap_field_bulk_alloc(dev, map, bwmon->regs, + ret = devm_regmap_field_bulk_alloc(dev, map, bwmon->regs, bwmon->data->regmap_fields, F_NUM_FIELDS); + if (ret) + return ret; + + if (bwmon->data->global_regmap_cfg) { + /* Map the global base, if separate */ + base = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(base)) + return dev_err_probe(dev, PTR_ERR(base), + "failed to map bwmon global registers\n"); + + map = devm_regmap_init_mmio(dev, base, bwmon->data->global_regmap_cfg); + if (IS_ERR(map)) + return dev_err_probe(dev, PTR_ERR(map), + "failed to initialize global regmap\n"); + + ret = devm_regmap_field_bulk_alloc(dev, map, bwmon->global_regs, + bwmon->data->global_regmap_fields, + F_NUM_GLOBAL_FIELDS); + } + + return ret; } static int bwmon_probe(struct platform_device *pdev) @@ -644,6 +815,21 @@ static const struct icc_bwmon_data msm8998_bwmon_data = { .quirks = BWMON_HAS_GLOBAL_IRQ, .regmap_fields = msm8998_bwmon_reg_fields, .regmap_cfg = &msm8998_bwmon_regmap_cfg, + .global_regmap_fields = msm8998_bwmon_global_reg_fields, + .global_regmap_cfg = &msm8998_bwmon_global_regmap_cfg, +}; + +static const struct icc_bwmon_data sdm845_cpu_bwmon_data = { + .sample_ms = 4, + .count_unit_kb = 64, + .default_highbw_kbps = 4800 * 1024, /* 4.8 GBps */ + .default_medbw_kbps = 512 * 1024, /* 512 MBps */ + .default_lowbw_kbps = 0, + .zone1_thres_count = 16, + .zone3_thres_count = 1, + .quirks = BWMON_HAS_GLOBAL_IRQ, + .regmap_fields = sdm845_cpu_bwmon_reg_fields, + .regmap_cfg = &sdm845_cpu_bwmon_regmap_cfg, }; static const struct icc_bwmon_data sdm845_llcc_bwmon_data = { @@ -672,16 +858,18 @@ static const struct icc_bwmon_data sc7280_llcc_bwmon_data = { }; static const struct of_device_id bwmon_of_match[] = { - { - .compatible = "qcom,msm8998-bwmon", - .data = &msm8998_bwmon_data - }, { - .compatible = "qcom,sdm845-llcc-bwmon", - .data = &sdm845_llcc_bwmon_data - }, { - .compatible = "qcom,sc7280-llcc-bwmon", - .data = &sc7280_llcc_bwmon_data - }, + /* BWMONv4, separate monitor and global register spaces */ + { .compatible = "qcom,msm8998-bwmon", .data = &msm8998_bwmon_data }, + /* BWMONv4, unified register space */ + { .compatible = "qcom,sdm845-bwmon", .data = &sdm845_cpu_bwmon_data }, + /* BWMONv5 */ + { .compatible = "qcom,sdm845-llcc-bwmon", .data = &sdm845_llcc_bwmon_data }, + { .compatible = "qcom,sc7280-llcc-bwmon", .data = &sc7280_llcc_bwmon_data }, + + /* Compatibles kept for legacy reasons */ + { .compatible = "qcom,sc7280-cpu-bwmon", .data = &sdm845_cpu_bwmon_data }, + { .compatible = "qcom,sc8280xp-cpu-bwmon", .data = &sdm845_cpu_bwmon_data }, + { .compatible = "qcom,sm8550-cpu-bwmon", .data = &sdm845_cpu_bwmon_data }, {} }; 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Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 8f4ab6bd2886..f15fea6cc316 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3533,7 +3533,7 @@ opp-7 { }; pmu@90b6400 { - compatible = "qcom,sc7280-cpu-bwmon", "qcom,msm8998-bwmon"; + compatible = "qcom,sc7280-cpu-bwmon", "qcom,sdm845-bwmon"; reg = <0 0x090b6400 0 0x600>; interrupts = ; From patchwork Wed Mar 15 14:11:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 70247 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp2358290wrd; Wed, 15 Mar 2023 07:21:40 -0700 (PDT) X-Google-Smtp-Source: AK7set8lGJ+8kP2eHjgOcTxv4f+f/gVQjafjrxnfEUSHkqg7mu/sr3E1y+AwKO5Yky1c0NqdPZKT X-Received: by 2002:a17:902:e848:b0:19a:7758:e5e6 with SMTP id t8-20020a170902e84800b0019a7758e5e6mr3169808plg.48.1678890099855; Wed, 15 Mar 2023 07:21:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1678890099; cv=none; d=google.com; s=arc-20160816; b=PbYTQwcJqfgLqZ+Z0UICfEZNE6I9xdlpYCudKf93MS+DuxzRy4O79Z6CET835oXBzd d0MIetjkJXfolntMaOVP4IUfzg2iTHyGJ4zqjP69VqAnz666zbHee8YEJjVfI8xMAelH 24qkuv8zTVT1xLBCsmkw2OYDByMkMuQM1eJry/a+kELBsWcYVhHYUW9sJ5KjA8uuXlbc M5Q4VDbyWkU019IlmE6s6KAsw+9Pbei7MAECTEqJB/7YpvFC+0wabhzzZOlFDi0lo6cN uOSAroslLy9jbySLbqm8kfu9gNONpEYfm9Tq0jRk4AMjCNbbKoWIfuTlkyPNneWTwPp6 APZA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=nqvdp07J1HQLjVavRExVgoZODvgCx91QmPizlq7Sg94=; b=DzOy+Je8GtDgvZQdlWDRIvUaALuM5OPvbmK+hlSIjDvrMw9sbcgPu+Tt0bfgoM0cJw Ckbpq38hYGj6OiSrJy9lxN7wX02GYTUd+dK86Ff8PVLCCAJNbsdflBucsyv1nbO5/glG EGaANgaOYho1hWccvi5Hs2Nfjx6iG9ZH2ezfCSNfT7JnYqsuDKhvXGw2ddg9+ClxQIK4 OmzmxBdmX+ck/+iZOKHJFKKv11bJC3l7faxyK4Axtv9ZSAIW9egRNt5tyiLwl7gUaXa2 oOOBDyO+TSabX5KAGKnmuvwGciV5URxViz9jHKQi6kedyMBLFvHG7MdPewbyzarmB4BE cY3g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="wj+H/ZKx"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[83.9.29.16]) by smtp.gmail.com with ESMTPSA id b8-20020ac25e88000000b004e845a08567sm824678lfq.291.2023.03.15.07.11.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Mar 2023 07:11:34 -0700 (PDT) From: Konrad Dybcio Date: Wed, 15 Mar 2023 15:11:23 +0100 Subject: [PATCH v3 5/7] arm64: dts: qcom: sc8280xp: Use the correct BWMON fallback compatible MIME-Version: 1.0 Message-Id: <20230304-topic-ddr_bwmon-v3-5-77a050c2fbda@linaro.org> References: <20230304-topic-ddr_bwmon-v3-0-77a050c2fbda@linaro.org> In-Reply-To: <20230304-topic-ddr_bwmon-v3-0-77a050c2fbda@linaro.org> To: Andy Gross , Bjorn Andersson , Krzysztof Kozlowski , Georgi Djakov , Rob Herring , Thara Gopinath , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , Marijn Suijten X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1678889480; l=857; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=1DZfsRNhr1OAkCF3p7xVoJYWjPDaei4Vd+17mLHBDz0=; b=sGJ1D/caceEmjC9PDr1xTNrAWwLRHMU5A9DG7ARV3xwKMnXuVMIbV8nLuYpvCG6AFeE54Mr8C0Fq /rrLrJ1ZCJkkEg1yd++oIKpkXcib945I6leZTcr+xO++XLClL0Dl X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-0.2 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_SORBS_HTTP,RCVD_IN_SORBS_SOCKS,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1760443865647454969?= X-GMAIL-MSGID: =?utf-8?q?1760443865647454969?= Use the correct fallback compatible for the BWMONv4 with merged global and monitor register spaces. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 0d02599d8867..131b99bfe771 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -2946,7 +2946,7 @@ opp-12 { }; pmu@90b6400 { - compatible = "qcom,sc8280xp-cpu-bwmon", "qcom,msm8998-bwmon"; + compatible = "qcom,sc8280xp-cpu-bwmon", "qcom,sdm845-bwmon"; reg = <0 0x090b6400 0 0x600>; interrupts = ; From patchwork Wed Mar 15 14:11:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 70245 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp2358107wrd; Wed, 15 Mar 2023 07:21:11 -0700 (PDT) X-Google-Smtp-Source: AK7set8Yn533q1p2fIoirT5z3UUXIcNIo/0xViuNPBgWi+DSQQ4tW+gxd4fOKtruDLUSNcS2CqnZ X-Received: by 2002:aa7:842e:0:b0:5a8:aa77:1835 with SMTP id q14-20020aa7842e000000b005a8aa771835mr34567098pfn.33.1678890071322; Wed, 15 Mar 2023 07:21:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1678890071; cv=none; d=google.com; s=arc-20160816; b=sCBysD0H5Tu1juT/a4gJzQlZBxl3nLLqA3Dos64uvAZ2FV3xiJfw1FqJwBmVbzu0em W1iFx4VCL9iDm8j2YgOUDLivkE6tSJ6ooFoBfeslWjnlnt69ftTZ6Xo5G/0d70gT2J3E wrAbZ0XDnLVxLeh1acl2jGSiu+Y8kwLMsT7mU1entQTs5RKHYIdKfUj7kQNCN2bCFSYC 45pkGvatb5ew82pqZ6ueX8aAju+52bgOPBIJuk/6MginbzFFLzsF8UTpmzYfGEr7hvpc Rp0B6bz7zuQGxQWr/Y4ROYgCUmDUFou5h1ViX24WkfoBF273GhfWigVV3DaJoXv6GQKN XbAA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=IH0ZCvPL/3GU0CeiB2YhHJI9Er8cEK0jH1qxynvAopg=; b=fm3UV6mcfwsG+YiRtGrouMDMNWH4N1059Gi0OE2txKvNX4kJK1BH0QfiPOhrNGQoUK b0Kk6ojNCI733Y7DHYBn5KNMawtAmSUymcEof0syF5MCMiRE2EDId0biREEh5ZRpjGzD FGQIqMugK/k9j152aOFWv0ug0kv+P51pWffnTo7yR8Jv4u+zt9kXOer+B8gmvOYdytQX JPoQyxDhpgq2XvZc/WNXAv7wVPd8yUB+qhu1mK6Rv6mBmwEmyuTuqc1Euy/wImumvZcG zHYpgy2GJccbenOalfC8ZWKeESBBmGGwIBI2iA1o/aigD2qIofOs6TNQB8QqoyMYHb7p Fd5Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PjKAf6X3; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[83.9.29.16]) by smtp.gmail.com with ESMTPSA id b8-20020ac25e88000000b004e845a08567sm824678lfq.291.2023.03.15.07.11.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Mar 2023 07:11:36 -0700 (PDT) From: Konrad Dybcio Date: Wed, 15 Mar 2023 15:11:24 +0100 Subject: [PATCH v3 6/7] arm64: dts: qcom: sdm845: Use the correct BWMON compatible MIME-Version: 1.0 Message-Id: <20230304-topic-ddr_bwmon-v3-6-77a050c2fbda@linaro.org> References: <20230304-topic-ddr_bwmon-v3-0-77a050c2fbda@linaro.org> In-Reply-To: <20230304-topic-ddr_bwmon-v3-0-77a050c2fbda@linaro.org> To: Andy Gross , Bjorn Andersson , Krzysztof Kozlowski , Georgi Djakov , Rob Herring , Thara Gopinath , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , Marijn Suijten X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1678889480; l=954; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=IFc3qKQ/mzYt/DYUL06igVAb6D7fe/8j8f5wmJWco+Y=; b=GX6YCA+EVcASk66NmRcaCbYhYHJGj5/eoBll4XT8Qsp0Cl4XcBcXpzEzdmOzBaiZFF4WvXzWuxWZ oLsT6VFNC89txHmw/qTWlRNtC9Nvc2sw6rx+0aQtBSIBOl2TLwDU X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-0.2 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_SORBS_HTTP,RCVD_IN_SORBS_SOCKS,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1760443835585120925?= X-GMAIL-MSGID: =?utf-8?q?1760443835585120925?= Drop the incorrect msm8998 fallback and use the new qcom,sdm845-cpu-bwmon compatible to distinguish the CPU BWMON found on this platform. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 479859bd8ab3..1f2a97a20ef3 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2241,7 +2241,7 @@ opp-4 { }; pmu@1436400 { - compatible = "qcom,sdm845-bwmon", "qcom,msm8998-bwmon"; + compatible = "qcom,sdm845-cpu-bwmon", "qcom,sdm845-bwmon"; reg = <0 0x01436400 0 0x600>; interrupts = ; interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_LLCC 3>; From patchwork Wed Mar 15 14:11:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 70248 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp2358581wrd; Wed, 15 Mar 2023 07:22:18 -0700 (PDT) X-Google-Smtp-Source: AK7set/PL7Is00O+2zkuL7Z3xVjwMg/f1vahdujhWLWSPkJdH67oQvI8qUZDE3DZYUAcJh4ckGg9 X-Received: by 2002:a05:6a21:9999:b0:d6:97e8:c3ed with SMTP id ve25-20020a056a21999900b000d697e8c3edmr45805pzb.14.1678890138621; Wed, 15 Mar 2023 07:22:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1678890138; cv=none; d=google.com; s=arc-20160816; b=lPLnlrTH+UquSivbgKR7FmmNj5P/xJXQ3LO+zjdSpw02J0sy6oU7hgDFrU94glZ665 iMNqu6//88rOAbpQQQf2zazqWTAQs59LcNeTITwH9NWrAg1LDagRSYry4CaL6zqfMqG/ NOmU5iMRd2RgnZjlIx2Yyy3K++skb9sRf3/BJCJgJmp66ZT9EQ7gXcz0MePHETOsvzqr Xr9KxnY7gDNrbqWE6u7Hq51/bcSxAZCSNSrtb6QgBeCWYTlqzG7FUen3xDi5rYTSFA4Q oXCrhcsvSkJQ/ZPV3OSX6rTzHr06v8W0SIvP24h/6+Gn81+/yYRsOi65DDtL9H0uNVFb KCWA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=NtJ3vFNxN3ulWegLUMLxPGL5fEpN3EwC/SH8BmcFyaA=; b=hnwboR0qZWfq4JmM4ypaf1GyrDwbpybr//Ldcii0FFx0H9XeBGuE9xjKWJL2tfYnL5 eb2dCtypTEZCgjjAsX+rW2YynnDdDBgv45AcHYsDUXgtwMHtYyTHoBDcouxJr9s4lFTS 00SRDgX2lkZQdHHDHDSIBLL8uFMeUCeHRoIZEGcGqBiHD/MuvDZGS7Dk4Dkkn1xb9w15 2X/puFDuUa14piwHOIWAzfuFzRvW0dj/Y2Qv4Z+bvY16I4pw6YGPdCkccGdWWc3nwz63 GWF/LcCFoc7glr1SFrQsIM60dH3jzbnr62uywShRcLwK68HiphkIO8xiXOsu/Aosytc3 g/vw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=r5bmp5Qi; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[83.9.29.16]) by smtp.gmail.com with ESMTPSA id b8-20020ac25e88000000b004e845a08567sm824678lfq.291.2023.03.15.07.11.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Mar 2023 07:11:38 -0700 (PDT) From: Konrad Dybcio Date: Wed, 15 Mar 2023 15:11:25 +0100 Subject: [PATCH v3 7/7] arm64: dts: qcom: sm8550: Use the correct BWMON fallback compatible MIME-Version: 1.0 Message-Id: <20230304-topic-ddr_bwmon-v3-7-77a050c2fbda@linaro.org> References: <20230304-topic-ddr_bwmon-v3-0-77a050c2fbda@linaro.org> In-Reply-To: <20230304-topic-ddr_bwmon-v3-0-77a050c2fbda@linaro.org> To: Andy Gross , Bjorn Andersson , Krzysztof Kozlowski , Georgi Djakov , Rob Herring , Thara Gopinath , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , Marijn Suijten X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1678889480; l=915; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=dMLX1nr86ibogtZfftMqjl+ZEaZVlp2gW/2Ekfh4Qg4=; b=mMcmR4y/gsZjUv2tlyJ0SIklkEDolVPgP57/9+mWsULUFgqpDVqjV7uPqWeWFjPx1kCvQH2+XD4H 91/t24IgDvQwqivh8870zKvltnkQHeHB0FsUya3rbMU+kimWCO0Z X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= X-Spam-Status: No, score=-0.2 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_SORBS_HTTP,RCVD_IN_SORBS_SOCKS,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1760443905828113752?= X-GMAIL-MSGID: =?utf-8?q?1760443905828113752?= Use the correct fallback compatible for the BWMONv4 with merged global and monitor register spaces. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio Reviewed-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 25f51245fe9b..b5488c6822bd 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -3391,7 +3391,7 @@ opp-8 { }; pmu@240b6400 { - compatible = "qcom,sm8550-cpu-bwmon", "qcom,msm8998-bwmon"; + compatible = "qcom,sm8550-cpu-bwmon", "qcom,sdm845-bwmon"; reg = <0 0x240b6400 0 0x600>; interrupts = ; interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>;