From patchwork Wed Mar 15 13:42:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Herve Codina X-Patchwork-Id: 70241 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp2353624wrd; Wed, 15 Mar 2023 07:12:30 -0700 (PDT) X-Google-Smtp-Source: AK7set++Dzvh6Z72oFnJTL0ct+eGaygvsoHRV8SyxD28I4ngC1kFbu6f23jwJs5aVkBbYp1lTZZF X-Received: by 2002:a05:6a20:be28:b0:d6:33af:4842 with SMTP id ge40-20020a056a20be2800b000d633af4842mr1946951pzb.43.1678889550680; Wed, 15 Mar 2023 07:12:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1678889550; cv=none; d=google.com; s=arc-20160816; b=kXs+D8ky+dE02umpVFylf099nmo5k/E9U2UxqyhI/j5Wx27fBx5AAQlIT40rSr8SV5 yOwLD6EpKEd+wmcy7QeGjiiiw/AwMb7NxKqYdIz00oKU0dI4aaWqlHqIQvEu39Zj48Jg Uamqa5xyiTGfF3TR72P8uMH8LvNT8pk5TTDWy03OMcVM2hWlnw9GQ5EnaQGB8lZFoaoE Ia3fRnJldT2ZMQ9WHmKMvRTK+JTfDVJXWxHM3jjJVjuYOkimqf9sCaNTF2RESL/NqFDV Lk37UZgYaMoT6LKJHBu1/nBv9NXM91b8Ti5HQL7MR5o/3og1OwfuoEPfPdLBEZHlGqWa 5kEA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=FFGOza8KtxdlZJDJFifVkkqFS15G5C9LfrRj7KzUGtM=; b=AgBslBuJFrIS3Dvw4I+ejQUCITn1VIREusTwMfeJjYK0MYMLgqAFObOSwzOfMcDzUR xq699iwnrGoajXvPNNBCnSSBEiPoXBIhG+OqEJ9bkYqgoZxpF2Pf8++WxKFkoDpzxQDL KpJ7acJZ7mCYJlqfUfbXmINtrQObPoIi5Y9QLgjGrHuhWdfygYlziAjeK8oCwiJUrqgs 3olqOdXiiBZuifqhPY5cwoF+7xCn3vyRctnsIzqEJt9NLk1wN6Td8ZKtncR3qAYiEiia ZPb6/AMCXmMLelJnYPcd2BJ1cVEpcwS7U/Rhu4pUcnKPfKyhatnJifOHgUmxRlld1ynn 5aYA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@bootlin.com header.s=gm1 header.b=AXxwJ8rx; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=bootlin.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id w8-20020a63f508000000b00502d6998a4asi4937375pgh.458.2023.03.15.07.12.17; Wed, 15 Mar 2023 07:12:30 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@bootlin.com header.s=gm1 header.b=AXxwJ8rx; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=bootlin.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232319AbjCONmu (ORCPT + 99 others); Wed, 15 Mar 2023 09:42:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56960 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231724AbjCONmm (ORCPT ); Wed, 15 Mar 2023 09:42:42 -0400 Received: from relay2-d.mail.gandi.net (relay2-d.mail.gandi.net [217.70.183.194]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D2D908ABC9; Wed, 15 Mar 2023 06:42:40 -0700 (PDT) Received: (Authenticated sender: herve.codina@bootlin.com) by mail.gandi.net (Postfix) with ESMTPA id 5FA2440009; Wed, 15 Mar 2023 13:42:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1678887759; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=FFGOza8KtxdlZJDJFifVkkqFS15G5C9LfrRj7KzUGtM=; b=AXxwJ8rxhJ/yFOlfR/tRmskmlIw7AB6PMrEJQ9m4askK+OQKKrQygPVU1RAOEMgMPlrLRZ npzfSE35hfzda/UBvtaCipg6O0z/jBSm7hOHPBb88JH1W5D8Ok4d13XA9+9qPVp+boirPT U5BEAVq6wxEGwKZPAx6FB7yCw1F122H18ZgO7cR7wLSOMxDPjwaZOwbX3s0N2YDqXjWDJR rJX3XsDsKAFO1lH/A86SMgsgC/j/0KI5/orQ4wpKvIEZjVVKJRJ5NGB3vwtTPZ9iRVy7O+ 64frjMnMATKw7aewR6A2kH8My7a8dTSWwfqSMyrjgDveWZKDA5IXCuJUkvWYcA== From: Herve Codina To: Herve Codina , Rob Herring , Krzysztof Kozlowski , Liam Girdwood , Mark Brown , Derek Kiernan , Dragan Cvetic , Arnd Bergmann , Greg Kroah-Hartman , Jaroslav Kysela , Takashi Iwai Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, alsa-devel@alsa-project.org, Christophe Leroy , Thomas Petazzoni Subject: [PATCH 1/7] dt-bindings: misc: Add the Lantiq PEF2466 E1/T1/J1 framer Date: Wed, 15 Mar 2023 14:42:25 +0100 Message-Id: <20230315134231.233193-2-herve.codina@bootlin.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230315134231.233193-1-herve.codina@bootlin.com> References: <20230315134231.233193-1-herve.codina@bootlin.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1760443289635112792?= X-GMAIL-MSGID: =?utf-8?q?1760443289635112792?= The Lantiq PEF2256 is a framer and line interface component designed to fulfill all required interfacing between an analog E1/T1/J1 line and the digital PCM system highway/H.100 bus. Signed-off-by: Herve Codina --- .../bindings/misc/lantiq,pef2256.yaml | 190 ++++++++++++++++++ 1 file changed, 190 insertions(+) create mode 100644 Documentation/devicetree/bindings/misc/lantiq,pef2256.yaml diff --git a/Documentation/devicetree/bindings/misc/lantiq,pef2256.yaml b/Documentation/devicetree/bindings/misc/lantiq,pef2256.yaml new file mode 100644 index 000000000000..1ba788d06a14 --- /dev/null +++ b/Documentation/devicetree/bindings/misc/lantiq,pef2256.yaml @@ -0,0 +1,190 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/misc/lantiq,pef2256.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Lantiq PEF2256 + +maintainers: + - Herve Codina + +description: + The Lantiq PEF2256, also known as Infineon PEF2256 or FALC256, is a framer and + line interface component designed to fulfill all required interfacing between + an analog E1/T1/J1 line and the digital PCM system highway/H.100 bus. + +properties: + compatible: + const: lantiq,pef2256 + + reg: + maxItems: 1 + + clocks: + items: + - description: Master clock + + clock-names: + items: + - const: mclk + + interrupts: + maxItems: 1 + + reset-gpios: + description: + GPIO used to reset the device. + maxItems: 1 + + pinctrl: + allOf: + - $ref: "/schemas/pinctrl/pinctrl.yaml#" + + patternProperties: + '-pins$': + type: object + allOf: + - $ref: "/schemas/pinctrl/pincfg-node.yaml#" + + properties: + pins: + enum: [ RPA, RPB, RPC, RPD, XPA, XPB, XPC, XPD ] + + function: + enum: [ SYPR, RFM, RFMB, RSIGM, RSIG, DLR, FREEZE, RFSP, LOS, + SYPX, XFMS, XSIG, TCLK, XMFB, XSIGM, DLX, XCLK, XLT, + GPI, GPOH, GPOL ] + + required: + - pins + - function + + lantiq,line-interface: + $ref: /schemas/types.yaml#/definitions/string + enum: [e1, t1j1] + default: e1 + description: | + The line interface type + - e1: E1 line + - t1j1: T1/J1 line + + lantiq,sysclk-rate-hz: + enum: [2048000, 4096000, 8192000, 16384000] + default: 2048000 + description: + Clock rate (Hz) on the system highway. + + lantiq,data-rate-bps: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [2048000, 4096000, 8192000, 16384000] + default: 2048000 + description: + Data rate (bit per seconds) on the system highway. + + lantiq,clock-falling-edge: + $ref: /schemas/types.yaml#/definitions/flag + description: + Data is sent on falling edge of the clock (and received on the rising + edge). If 'clock-falling-edge' is not present, data is sent on the + rising edge (and received on the falling edge). + + lantiq,channel-phase: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3, 4, 5, 6, 7] + default: 0 + description: + The pef2256 delivers a full frame (32 8bit time-slots in E1 and 24 8bit + time-slots 8 8bit signaling in E1/J1) every 125us. This lead to a data + rate of 2048000 bit/s. When lantiq,data-rate-bps is more than 2048000 + bit/s, the data (all 32 8bit) present in the frame are interleave with + unused time-slots. The lantiq,channel-phase property allows to set the + correct alignment of the interleave mechanism. + For instance, suppose lantiq,data-rate-bps = 8192000 (ie 4*2048000), and + lantiq,channel-phase = 2, the interleave schema with unused time-slots + (nu) and used time-slots (XX) for TSi is + nu nu XX nu nu nu XX nu nu nu XX nu + <-- TSi --> <- TSi+1 -> <- TSi+2 -> + With lantiq,data-rate-bps = 8192000, and lantiq,channel-phase = 1, the + interleave schema is + nu XX nu nu nu XX nu nu nu XX nu nu + <-- TSi --> <- TSi+1 -> <- TSi+2 -> + With lantiq,data-rate-bps = 4096000 (ie 2*2048000), and + lantiq,channel-phase = 1, the interleave schema is + nu XX nu XX nu XX + <-- TSi --> <- TSi+1 -> <- TSi+2 -> + + lantiq,subordinate: + $ref: /schemas/types.yaml#/definitions/flag + description: + If present, the pef2256 works in subordinate mode. In this mode it + synchronizes on line interface clock signals. Otherwise, it synchronizes + on internal clocks. + +allOf: + - if: + properties: + lantiq,line-interface: + contains: + const: e1 + then: + properties: + lantiq,frame-format: + $ref: /schemas/types.yaml#/definitions/string + enum: [doubleframe, crc4-multiframe, auto-multiframe] + default: doubleframe + description: | + The E1 line interface frame format + - doubleframe: Doubleframe format + - crc4-multiframe: CRC4 multiframe format + - auto-multiframe: CRC4 multiframe format with interworking + capabilities (ITU-T G.706 Annex B) + + else: + # T1/J1 line + properties: + lantiq,frame-format: + $ref: /schemas/types.yaml#/definitions/string + enum: [4frame, 12frame, 24frame, 72frame] + default: 12frame + description: | + The T1/J1 line interface frame format + - 4frame: 4-frame multiframe format (F4) + - 12frame: 12-frame multiframe format (F12, D3/4) + - 24frame: 24-frame multiframe format (ESF) + - 72frame: 72-frame multiframe format (F72, remote switch mode) + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + +additionalProperties: false + +examples: + - | + #include + pef2256@2000000 { + compatible = "lantiq,pef2256"; + reg = <0x2000000 0xFF>; + interrupts = <8 1>; + interrupt-parent = <&PIC>; + clocks = <&clk_mclk>; + clock-names = "mclk"; + reset-gpios = <&gpio 11 GPIO_ACTIVE_LOW>; + lantiq,sysclk-rate-hz = <8192000>; + lantiq,data-rate-bps = <4096000>; + + pinctrl { + pef2256_rpa_sypr: rpa-pins { + pins = "RPA"; + function = "SYPR"; + }; + pef2256_xpa_sypx: xpa-pins { + pins = "XPA"; + function = "SYPX"; + }; + }; + }; From patchwork Wed Mar 15 13:42:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Herve Codina X-Patchwork-Id: 70236 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp2345042wrd; Wed, 15 Mar 2023 07:00:17 -0700 (PDT) X-Google-Smtp-Source: AK7set8BjdxnJ8037MjGefwuWYC4kEiGxQL9wRi4cpHDF9NpBU8VuOK+9/DdvGtsDIHiLXCYCCAx X-Received: by 2002:a62:4e4d:0:b0:625:53c1:da5b with SMTP id c74-20020a624e4d000000b0062553c1da5bmr6579152pfb.8.1678888816961; Wed, 15 Mar 2023 07:00:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1678888816; cv=none; d=google.com; s=arc-20160816; b=FGLi06uXJ32qtAPAmDM5sCmwTmyoS9uBTntv6akHkcnqtSr8td6EkvDXoTPqmO+rL6 XSgdsQfQ0awKoai8aH34n0DRKZa9olZUTjbhp0oUGmX9QTfv7WqeqWt2eDadjzHXB6bh qduADyAmRVlVpGFJA5GwhJIwQlbuCVS5/n0JeDdiKIZ3YMixYoRCposjkmbum7WVa/zV l647G5fqA5nc+j+mjayaS9U0+4G94VhDfaOTt45H/Dl1LoQnDy5GaON+cbLtpzrCCkq5 Ji0jwTjM0pG2aynVCayO631dk+It7FP5YBBMw3eXkIishXXfDMLBwcduBjLpyfm1Xtlm 3JOw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=6vXyKNCMw+3P5Tr7Y84kv+URQbM+m3tIx7YBvsAwjeI=; b=EwC5XtIdJFY5C2NwWYrQ1GVFgTuX78j+dcU6iw4IRtfaRdwL7o8nNRFAXPwwhUvoRa RNW3/vgh+gOwBO2g/WJghnUx1Wp0wHPRsM77ZsiD+4BZg4Y/7oWzfxHD1YW6LEpUrOBd ZcX+E3bOKiZh9WR8J7NMY4ocuu/etMrKOjnRh+kZV4q8QH3VhpxvXrOME/74ObYMqd1y QFMWJ3pmAG++GPDCg22T3Tn5Xnu9SPvgcQjTuq1Y0XecfUGUU1+WVp1RBImSWUOyf2K5 NUmrp79rqDtg9Pe/bYl9xgKGIjwLTISQU7CcP+8GsfWGr/a+9k0u37Me5l6My1+Xbrzo Rxtw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@bootlin.com header.s=gm1 header.b=PaLTGhDm; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=bootlin.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id w26-20020aa7955a000000b006251fb701a6si4723574pfq.285.2023.03.15.07.00.03; Wed, 15 Mar 2023 07:00:16 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@bootlin.com header.s=gm1 header.b=PaLTGhDm; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=bootlin.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232417AbjCONnE (ORCPT + 99 others); Wed, 15 Mar 2023 09:43:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57044 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229556AbjCONms (ORCPT ); Wed, 15 Mar 2023 09:42:48 -0400 Received: from relay2-d.mail.gandi.net (relay2-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::222]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E2CDC73011; Wed, 15 Mar 2023 06:42:42 -0700 (PDT) Received: (Authenticated sender: herve.codina@bootlin.com) by mail.gandi.net (Postfix) with ESMTPA id B79574000D; Wed, 15 Mar 2023 13:42:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1678887761; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=6vXyKNCMw+3P5Tr7Y84kv+URQbM+m3tIx7YBvsAwjeI=; b=PaLTGhDmTCmzxAIN+TfG5tU6IqNeYKfhcvPx+XO6p0Cu+9e6E+fGh4lmqQjNnG4MeAFqT7 Vzqt5qfHkjJ3RkRkrNceXVnnwaX1vb107DfJKsJRaC81sJwDPneuQgYno4OGqijxlOcjco duAjkgL+CqeSjUtbQYIQZyhQ4mPjywW6qnMSYGnadxQ/y2+kqziCAhJXzXiuHri8DHbx/n yyuhWrhku11NHVUVXyH3NC+IXoTV3+C8AIP89bi1vk/Q4is3D4qM+tuXrtJrewJ8WqrWJc PKvF7hRlE4Fr0Yvx57WqhIKyX0dHf8MdPoRNhK1kPVmQPg+7XK4tnkeHh+Tm3g== From: Herve Codina To: Herve Codina , Rob Herring , Krzysztof Kozlowski , Liam Girdwood , Mark Brown , Derek Kiernan , Dragan Cvetic , Arnd Bergmann , Greg Kroah-Hartman , Jaroslav Kysela , Takashi Iwai Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, alsa-devel@alsa-project.org, Christophe Leroy , Thomas Petazzoni Subject: [PATCH 2/7] drivers: misc: Add support for the Lantiq PEF2256 framer Date: Wed, 15 Mar 2023 14:42:26 +0100 Message-Id: <20230315134231.233193-3-herve.codina@bootlin.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230315134231.233193-1-herve.codina@bootlin.com> References: <20230315134231.233193-1-herve.codina@bootlin.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1760442519865188443?= X-GMAIL-MSGID: =?utf-8?q?1760442519865188443?= The Lantiq PEF2256 is a framer and line interface component designed to fulfill all required interfacing between an analog E1/T1/J1 line and the digital PCM system highway/H.100 bus. Signed-off-by: Herve Codina --- drivers/misc/Kconfig | 16 + drivers/misc/Makefile | 1 + drivers/misc/pef2256.c | 1441 +++++++++++++++++++++++++++++++++++++++ include/linux/pef2256.h | 36 + 4 files changed, 1494 insertions(+) create mode 100644 drivers/misc/pef2256.c create mode 100644 include/linux/pef2256.h diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 433aa4197785..b64f9435a51b 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -376,6 +376,22 @@ config HMC6352 This driver provides support for the Honeywell HMC6352 compass, providing configuration and heading data via sysfs. +config PEF2256 + tristate "Lantiq PEF2256 (FALC56) framer" + select PINCTRL + select PINMUX + select GENERIC_PINCONF + help + This option enables support for the Lantiq PEF2256 framer, also known + as FALC56. This framer and its line interface component is designed + to fulfill all required interfacing between analog E1/T1/J1 lines and + the digital PCM system highway. + + If unsure, say N. + + To compile this driver as a module, choose M here: the + module will be called pef2256. + config DS1682 tristate "Dallas DS1682 Total Elapsed Time Recorder with Alarm" depends on I2C diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 56de43943cd5..a26f044ab9dd 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -35,6 +35,7 @@ obj-$(CONFIG_SENSORS_TSL2550) += tsl2550.o obj-$(CONFIG_DS1682) += ds1682.o obj-$(CONFIG_C2PORT) += c2port/ obj-$(CONFIG_HMC6352) += hmc6352.o +obj-$(CONFIG_PEF2256) += pef2256.o obj-y += eeprom/ obj-y += cb710/ obj-$(CONFIG_VMWARE_BALLOON) += vmw_balloon.o diff --git a/drivers/misc/pef2256.c b/drivers/misc/pef2256.c new file mode 100644 index 000000000000..859b944aba8c --- /dev/null +++ b/drivers/misc/pef2256.c @@ -0,0 +1,1441 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PEF2256 also known as FALC56 driver + * + * Copyright 2023 CS GROUP France + * + * Author: Herve Codina + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PEF2256_CMDR 0x02 /* Command Register */ +#define PEF2256_CMDR_RRES BIT(6) +#define PEF2256_CMDR_XRES BIT(4) +#define PEF2256_CMDR_SRES BIT(0) +#define PEF2256_IMR0 0x14 /* Interrupt Mask Register 0 */ +#define PEF2256_IMR1 0x15 /* Interrupt Mask Register 1 */ +#define PEF2256_IMR2 0x16 /* Interrupt Mask Register 2 */ +#define PEF2256_IMR3 0x17 /* Interrupt Mask Register 3 */ +#define PEF2256_IMR4 0x18 /* Interrupt Mask Register 4 */ +#define PEF2256_IMR5 0x19 /* Interrupt Mask Register 5 */ +#define PEF2256_FMR0 0x1C /* Framer Mode Register 0 */ +#define PEF2256_FMR0_XC_MASK (0x3 << 6) +#define PEF2256_FMR0_XC_NRZ (0x0 << 6) +#define PEF2256_FMR0_XC_CMI (0x1 << 6) +#define PEF2256_FMR0_XC_AMI (0x2 << 6) +#define PEF2256_FMR0_XC_HDB3 (0x3 << 6) +#define PEF2256_FMR0_RC_MASK (0x3 << 4) +#define PEF2256_FMR0_RC_NRZ (0x0 << 4) +#define PEF2256_FMR0_RC_CMI (0x1 << 4) +#define PEF2256_FMR0_RC_AMI (0x2 << 4) +#define PEF2256_FMR0_RC_HDB3 (0x3 << 4) +#define PEF2256_FMR1 0x1D /* Framer Mode Register 1 */ +#define PEF2256_FMR1_XFS BIT(3) +#define PEF2256_FMR1_ECM BIT(2) +/* SSD is defined on 2 bits. The other bit is on SIC1 register */ +#define PEF2256_FMR1_SSD_MASK BIT(1) +#define PEF2256_FMR1_SSD_2048 0 +#define PEF2256_FMR1_SSD_4096 BIT(1) +#define PEF2256_FMR1_SSD_8192 0 +#define PEF2256_FMR1_SSD_16384 BIT(1) +#define PEF2256_FMR2 0x1E /* Framer Mode Register 2 */ +#define PEF2256_FMR2_RFS_MASK (0x3 << 6) +#define PEF2256_FMR2_RFS_DOUBLEFRAME (0x0 << 6) +#define PEF2256_FMR2_RFS_CRC4_MULTIFRAME (0x2 << 6) +#define PEF2256_FMR2_RFS_AUTO_MULTIFRAME (0x3 << 6) +#define PEF2256_FMR2_AXRA BIT(1) +#define PEF2256_LOOP 0x1F /* Channel Loop-Back */ +#define PEF2256_XSW 0x20 /* Transmit Service Word */ +#define PEF2256_XSW_XSIS BIT(7) +#define PEF2256_XSW_XTM BIT(6) +#define PEF2256_XSW_XY_MASK (0x1f << 0) +#define PEF2256_XSW_XY(_v) ((_v) & 0x1f) +#define PEF2256_XSP 0x21 /* Transmit Spare Bits */ +#define PEF2256_XSP_XSIF BIT(2) +#define PEF2256_XC0 0x22 /* Transmit Control 0 */ +#define PEF2256_XC1 0x23 /* Transmit Control 1 */ +#define PEF2256_RC0 0x24 /* Receive Control 0 */ +#define PEF2256_RC0_SWD BIT(7) +#define PEF2256_RC0_ASY4 BIT(6) +#define PEF2256_RC1 0x25 /* Receive Control 1 */ +#define PEF2256_XPM0 0x26 /* Transmit Pulse Mask 0 */ +#define PEF2256_XPM1 0x27 /* Transmit Pulse Mask 1 */ +#define PEF2256_XPM2 0x28 /* Transmit Pulse Mask 2 */ +#define PEF2256_XPM2_XLT BIT(6) +#define PEF2256_TSWM 0x29 /* Transparent Service Word Mask */ +#define PEF2256_LIM0 0x36 /* Line Interface Mode 0 */ +#define PEF2256_2X_LIM0_BIT3 BIT(3) /* v2.x, described as a forced '1' bit */ +#define PEF2256_LIM0_MAS BIT(0) +#define PEF2256_LIM1 0x37 /* Line Interface Mode 1 */ +#define PEF2256_12_LIM1_RIL_MASK (0x7 << 4) +#define PEF2256_12_LIM1_RIL_910 (0x0 << 4) +#define PEF2256_12_LIM1_RIL_740 (0x1 << 4) +#define PEF2256_12_LIM1_RIL_590 (0x2 << 4) +#define PEF2256_12_LIM1_RIL_420 (0x3 << 4) +#define PEF2256_12_LIM1_RIL_320 (0x4 << 4) +#define PEF2256_12_LIM1_RIL_210 (0x5 << 4) +#define PEF2256_12_LIM1_RIL_160 (0x6 << 4) +#define PEF2256_12_LIM1_RIL_100 (0x7 << 4) +#define PEF2256_2X_LIM1_RIL_MASK (0x7 << 4) +#define PEF2256_2X_LIM1_RIL_2250 (0x0 << 4) +#define PEF2256_2X_LIM1_RIL_1100 (0x1 << 4) +#define PEF2256_2X_LIM1_RIL_600 (0x2 << 4) +#define PEF2256_2X_LIM1_RIL_350 (0x3 << 4) +#define PEF2256_2X_LIM1_RIL_210 (0x4 << 4) +#define PEF2256_2X_LIM1_RIL_140 (0x5 << 4) +#define PEF2256_2X_LIM1_RIL_100 (0x6 << 4) +#define PEF2256_2X_LIM1_RIL_50 (0x7 << 4) +#define PEF2256_PCD 0x38 /* Pulse Count Detection */ +#define PEF2256_PCR 0x39 /* Pulse Count Recovery */ +#define PEF2256_LIM2 0x3A /* Line Interface Mode 2 */ +#define PEF2256_LIM2_SLT_MASK (0x3 << 4) +#define PEF2256_LIM2_SLT_THR55 (0x0 << 4) +#define PEF2256_LIM2_SLT_THR67 (0x1 << 4) +#define PEF2256_LIM2_SLT_THR50 (0x2 << 4) +#define PEF2256_LIM2_SLT_THR45 (0x3 << 4) +#define PEF2256_LIM2_ELT BIT(2) +#define PEF2256_SIC1 0x3E /* System Interface Control 1 */ +#define PEF2256_SIC1_SSC_MASK (BIT(7) | BIT(3)) +#define PEF2256_SIC1_SSC_2048 (0) +#define PEF2256_SIC1_SSC_4096 BIT(3) +#define PEF2256_SIC1_SSC_8192 BIT(7) +#define PEF2256_SIC1_SSC_16384 (BIT(7) | BIT(3)) +/* SSD is defined on 2 bits. The other bit is on FMR1 register */ +#define PEF2256_SIC1_SSD_MASK BIT(6) +#define PEF2256_SIC1_SSD_2048 0 +#define PEF2256_SIC1_SSD_4096 0 +#define PEF2256_SIC1_SSD_8192 BIT(6) +#define PEF2256_SIC1_SSD_16384 BIT(6) +#define PEF2256_SIC1_RBS_MASK (0x3 << 4) +#define PEF2256_SIC1_RBS_2FRAMES (0x0 << 4) +#define PEF2256_SIC1_RBS_1FRAME (0x1 << 4) +#define PEF2256_SIC1_RBS_96BITS (0x2 << 4) +#define PEF2256_SIC1_RBS_BYPASS (0x3 << 4) +#define PEF2256_SIC1_XBS_MASK (0x3 << 0) +#define PEF2256_SIC1_XBS_BYPASS (0x0 << 0) +#define PEF2256_SIC1_XBS_1FRAME (0x1 << 0) +#define PEF2256_SIC1_XBS_2FRAMES (0x2 << 0) +#define PEF2256_SIC1_XBS_96BITS (0x3 << 0) +#define PEF2256_SIC2 0x3F /* System Interface Control 2 */ +#define PEF2256_SIC2_SICS_MASK (0x7 << 1) +#define PEF2256_SIC2_SICS(_v) ((_v) << 1) +#define PEF2256_SIC3 0x40 /* System Interface Control 3 */ +#define PEF2256_SIC3_RTRI BIT(5) +#define PEF2256_SIC3_RESX BIT(3) +#define PEF2256_SIC3_RESR BIT(2) +#define PEF2256_CMR1 0x44 /* Clock Mode Register 1 */ +#define PEF2256_CMR1_RS_MASK (0x3 << 4) +#define PEF2256_CMR1_RS_DPLL (0x0 << 4) +#define PEF2256_CMR1_RS_DPLL_LOS_HIGH (0x1 << 4) +#define PEF2256_CMR1_RS_DCOR_2048 (0x2 << 4) +#define PEF2256_CMR1_RS_DCOR_8192 (0x3 << 4) +#define PEF2256_CMR1_DCS BIT(3) +#define PEF2256_CMR2 0x45 /* Clock Mode Register 2 */ +#define PEF2256_CMR2_DCOXC BIT(5) +#define PEF2256_GCR 0x46 /* Global Configuration Register */ +#define PEF2256_GCR_SCI BIT(6) +#define PEF2256_GCR_ECMC BIT(4) +#define PEF2256_PC1 0x80 /* Port Configuration 1 */ +#define PEF2256_PC2 0x81 /* Port Configuration 2 */ +#define PEF2256_PC3 0x82 /* Port Configuration 3 */ +#define PEF2256_PC4 0x83 /* Port Configuration 4 */ +#define PEF2256_12_PC_RPC_MASK (0x7 << 4) +#define PEF2256_12_PC_RPC_SYPR (0x0 << 4) +#define PEF2256_12_PC_RPC_RFM (0x1 << 4) +#define PEF2256_12_PC_RPC_RFMB (0x2 << 4) +#define PEF2256_12_PC_RPC_RSIGM (0x3 << 4) +#define PEF2256_12_PC_RPC_RSIG (0x4 << 4) +#define PEF2256_12_PC_RPC_DLR (0x5 << 4) +#define PEF2256_12_PC_RPC_FREEZE (0x6 << 4) +#define PEF2256_12_PC_RPC_RFSP (0x7 << 4) +#define PEF2256_12_PC_XPC_MASK (0xf << 0) +#define PEF2256_12_PC_XPC_SYPX (0x0 << 0) +#define PEF2256_12_PC_XPC_XFMS (0x1 << 0) +#define PEF2256_12_PC_XPC_XSIG (0x2 << 0) +#define PEF2256_12_PC_XPC_TCLK (0x3 << 0) +#define PEF2256_12_PC_XPC_XMFB (0x4 << 0) +#define PEF2256_12_PC_XPC_XSIGM (0x5 << 0) +#define PEF2256_12_PC_XPC_DLX (0x6 << 0) +#define PEF2256_12_PC_XPC_XCLK (0x7 << 0) +#define PEF2256_12_PC_XPC_XLT (0x8 << 0) +#define PEF2256_2X_PC_RPC_MASK (0xf << 4) +#define PEF2256_2X_PC_RPC_SYPR (0x0 << 4) +#define PEF2256_2X_PC_RPC_RFM (0x1 << 4) +#define PEF2256_2X_PC_RPC_RFMB (0x2 << 4) +#define PEF2256_2X_PC_RPC_RSIGM (0x3 << 4) +#define PEF2256_2X_PC_RPC_RSIG (0x4 << 4) +#define PEF2256_2X_PC_RPC_DLR (0x5 << 4) +#define PEF2256_2X_PC_RPC_FREEZE (0x6 << 4) +#define PEF2256_2X_PC_RPC_RFSP (0x7 << 4) +#define PEF2256_2X_PC_RPC_GPI (0x9 << 4) +#define PEF2256_2X_PC_RPC_GPOH (0xa << 4) +#define PEF2256_2X_PC_RPC_GPOL (0xb << 4) +#define PEF2256_2X_PC_RPC_LOS (0xc << 4) +#define PEF2256_2X_PC_XPC_MASK (0xf << 0) +#define PEF2256_2X_PC_XPC_SYPX (0x0 << 0) +#define PEF2256_2X_PC_XPC_XFMS (0x1 << 0) +#define PEF2256_2X_PC_XPC_XSIG (0x2 << 0) +#define PEF2256_2X_PC_XPC_TCLK (0x3 << 0) +#define PEF2256_2X_PC_XPC_XMFB (0x4 << 0) +#define PEF2256_2X_PC_XPC_XSIGM (0x5 << 0) +#define PEF2256_2X_PC_XPC_DLX (0x6 << 0) +#define PEF2256_2X_PC_XPC_XCLK (0x7 << 0) +#define PEF2256_2X_PC_XPC_XLT (0x8 << 0) +#define PEF2256_2X_PC_XPC_GPI (0x9 << 0) +#define PEF2256_2X_PC_XPC_GPOH (0xa << 0) +#define PEF2256_2X_PC_XPC_GPOL (0xb << 0) +#define PEF2256_PC5 0x84 /* Port Configuration 5 */ +#define PEF2256_PC5_CRP BIT(0) +#define PEF2256_GPC1 0x85 /* Global Port Configuration 1 */ +#define PEF2256_GPC1_CSFP_MASK (0x3 << 5) +#define PEF2256_GPC1_CSFP_SEC_IN_HIGH (0x0 << 5) +#define PEF2256_GPC1_CSFP_SEC_OUT_HIGH (0x1 << 5) +#define PEF2256_GPC1_CSFP_FSC_OUT_HIGH (0x2 << 5) +#define PEF2256_GPC1_CSFP_FSC_OUT_LOW (0x3 << 5) +#define PEF2256_PC6 0x86 /* Port Configuration 6 */ +#define PEF2256_GCM(_n) (0x92 + _n - 1) /* Global Counter Mode n=1..8 */ +#define PEF2256_GCM1 0x92 /* Global Counter Mode 1 */ +#define PEF2256_GCM2 0x93 /* Global Counter Mode 2 */ +#define PEF2256_GCM3 0x94 /* Global Counter Mode 3 */ +#define PEF2256_GCM4 0x95 /* Global Counter Mode 4 */ +#define PEF2256_GCM5 0x96 /* Global Counter Mode 5 */ +#define PEF2256_GCM6 0x97 /* Global Counter Mode 6 */ +#define PEF2256_GCM7 0x98 /* Global Counter Mode 7 */ +#define PEF2256_GCM8 0x99 /* Global Counter Mode 8 */ + +#define PEF2256_VSTR 0x4A /* Version Status Register */ +#define PEF2256_VSTR_VERSION_12 0x00 +#define PEF2256_VSTR_VERSION_21 0x10 +#define PEF2256_VSTR_VERSION_2x 0x05 +#define PEF2256_FRS0 0x4C /* Framer Receive Status 0 */ +#define PEF2256_FRS0_LOS BIT(7) +#define PEF2256_FRS0_AIS BIT(6) +#define PEF2256_ISR(_n) (0x68 + n) /* Interrupt Status Register (n=0..5) */ +#define PEF2256_ISR0 0x68 /* Interrupt Status Register 0 */ +#define PEF2256_ISR1 0x69 /* Interrupt Status Register 1 */ +#define PEF2256_ISR2 0x6A /* Interrupt Status Register 2 */ +#define PEF2256_ISR3 0x6B /* Interrupt Status Register 3 */ +#define PEF2256_ISR4 0x6C /* Interrupt Status Register 4 */ +#define PEF2256_ISR5 0x6D /* Interrupt Status Register 5 */ +#define PEF2256_GIS 0x6E /* Global Interrupt Status */ +#define PEF2256_GIS_ISR(_n) (1<<(n)) +#define PEF2256_WID 0xEC /* Wafer Identification Register */ +#define PEF2256_12_WID_MASK 0x03 +#define PEF2256_12_WID_VERSION_12 0x03 +#define PEF2256_2X_WID_MASK 0xc0 +#define PEF2256_2X_WID_VERSION_21 0x00 +#define PEF2256_2X_WID_VERSION_22 0x40 + +/* IMR2/ISR2 Interrupts */ +#define PEF2256_INT2_AIS BIT(3) +#define PEF2256_INT2_LOS BIT(2) + +enum pef2256_version { + PEF2256_VERSION_UNKNOWN, + PEF2256_VERSION_1_2, + PEF2256_VERSION_2_1, + PEF2256_VERSION_2_2, +}; + +enum pef2256_frame_type { + PEF2256_FRAME_E1_DOUBLEFRAME, + PEF2256_FRAME_E1_CRC4_MULTIFRAME, + PEF2256_FRAME_E1_AUTO_MULTIFRAME, + PEF2256_FRAME_T1J1_4FRAME, + PEF2256_FRAME_T1J1_12FRAME, + PEF2256_FRAME_T1J1_24FRAME, + PEF2256_FRAME_T1J1_72FRAME, +}; + +struct pef2256_pinreg_desc { + int offset; + u8 mask; +}; + +struct pef2256_function_desc { + const char *name; + const char * const*groups; + unsigned int ngroups; + u8 func_val; +}; + +struct pef2256 { + struct device *dev; + void *__iomem regs; + enum pef2256_version version; + spinlock_t lock; + struct clk *mclk; + struct gpio_desc *reset_gpio; + struct { + struct pinctrl_desc pctrl_desc; + const struct pef2256_function_desc *functions; + unsigned int nfunctions; + } pinctrl; + bool is_e1; + u32 sysclk_rate; + u32 data_rate; + bool is_tx_falling_edge; + bool is_subordinate; + enum pef2256_frame_type frame_type; + u8 channel_phase; + bool is_carrier_on; + struct atomic_notifier_head event_notifier_list; +}; + +static inline u8 pef2256_read8(struct pef2256 *pef2256, int offset) +{ + return ioread8(pef2256->regs + offset); +} + +static inline void pef2256_write8(struct pef2256 *pef2256, int offset, u8 val) +{ + iowrite8(val, pef2256->regs + offset); +} + +static inline void pef2256_clrbits8(struct pef2256 *pef2256, int offset, u8 clr) +{ + u8 v; + + v = pef2256_read8(pef2256, offset); + v &= ~clr; + pef2256_write8(pef2256, offset, v); +} + +static inline void pef2256_setbits8(struct pef2256 *pef2256, int offset, u8 set) +{ + u8 v; + + v = pef2256_read8(pef2256, offset); + v |= set; + pef2256_write8(pef2256, offset, v); +} + + +static inline void pef2256_clrsetbits8(struct pef2256 *pef2256, int offset, u8 clr, u8 set) +{ + u8 v; + + v = pef2256_read8(pef2256, offset); + v &= ~clr; + v |= set; + pef2256_write8(pef2256, offset, v); +} + +static enum pef2256_version pef2256_get_version(struct pef2256 *pef2256) +{ + enum pef2256_version version; + const char *version_txt; + u8 vstr, wid; + + vstr = pef2256_read8(pef2256, PEF2256_VSTR); + wid = pef2256_read8(pef2256, PEF2256_WID); + + switch (vstr) { + case PEF2256_VSTR_VERSION_12: + if ((wid & PEF2256_12_WID_MASK) == PEF2256_12_WID_VERSION_12) { + version_txt = "1.2"; + version = PEF2256_VERSION_1_2; + goto end; + } + break; + case PEF2256_VSTR_VERSION_2x: + switch (wid & PEF2256_2X_WID_MASK) { + case PEF2256_2X_WID_VERSION_21: + version_txt = "2.1 (2.x)"; + version = PEF2256_VERSION_2_1; + goto end; + case PEF2256_2X_WID_VERSION_22: + version_txt = "2.2 (2.x)"; + version = PEF2256_VERSION_2_2; + goto end; + default: + break; + } + break; + case PEF2256_VSTR_VERSION_21: + version_txt = "2.1"; + version = PEF2256_VERSION_2_1; + goto end; + default: + break; + } + + dev_err(pef2256->dev, "Unknown version (0x%02x, 0x%02x)\n", vstr, wid); + return PEF2256_VERSION_UNKNOWN; + +end: + dev_info(pef2256->dev, "Version %s detected\n", version_txt); + return version; +} + +static int pef2256_12_setup_gcm(struct pef2256 *pef2256) +{ + static const u8 gcm_1544000[6] = {0xF0, 0x51, 0x00, 0x80, 0x00, 0x15}; + static const u8 gcm_2048000[6] = {0x00, 0x58, 0xD2, 0xC2, 0x00, 0x10}; + static const u8 gcm_8192000[6] = {0x00, 0x58, 0xD2, 0xC2, 0x03, 0x10}; + static const u8 gcm_10000000[6] = {0x90, 0x51, 0x81, 0x8F, 0x04, 0x10}; + static const u8 gcm_12352000[6] = {0xF0, 0x51, 0x00, 0x80, 0x07, 0x15}; + static const u8 gcm_16384000[6] = {0x00, 0x58, 0xD2, 0xC2, 0x07, 0x10}; + unsigned long mclk_rate; + const u8 *gcm; + int i; + + mclk_rate = clk_get_rate(pef2256->mclk); + switch (mclk_rate) { + case 1544000: + gcm = gcm_1544000; + break; + case 2048000: + gcm = gcm_2048000; + break; + case 8192000: + gcm = gcm_8192000; + break; + case 10000000: + gcm = gcm_10000000; + break; + case 12352000: + gcm = gcm_12352000; + break; + case 16384000: + gcm = gcm_16384000; + break; + default: + dev_err(pef2256->dev, "Unsupported v1.2 MCLK rate %lu\n", mclk_rate); + return -EINVAL; + } + for (i = 0; i < 6; i++) + pef2256_write8(pef2256, PEF2256_GCM(i+1), gcm[i]); + + return 0; +} + +static int pef2256_2x_setup_gcm(struct pef2256 *pef2256) +{ + static const u8 gcm_1544000[8] = {0x00, 0x15, 0x00, 0x08, 0x00, 0x3F, 0x9C, 0xDF}; + static const u8 gcm_2048000[8] = {0x00, 0x18, 0xFB, 0x0B, 0x00, 0x2F, 0xDB, 0xDF}; + static const u8 gcm_8192000[8] = {0x00, 0x18, 0xFB, 0x0B, 0x00, 0x0B, 0xDB, 0xDF}; + static const u8 gcm_10000000[8] = {0x40, 0x1B, 0x3D, 0x0A, 0x00, 0x07, 0xC9, 0xDC}; + static const u8 gcm_12352000[8] = {0x00, 0x19, 0x00, 0x08, 0x01, 0x0A, 0x98, 0xDA}; + static const u8 gcm_16384000[8] = {0x00, 0x18, 0xFB, 0x0B, 0x01, 0x0B, 0xDB, 0xDF}; + unsigned long mclk_rate; + const u8 *gcm; + int i; + + mclk_rate = clk_get_rate(pef2256->mclk); + switch (mclk_rate) { + case 1544000: + gcm = gcm_1544000; + break; + case 2048000: + gcm = gcm_2048000; + break; + case 8192000: + gcm = gcm_8192000; + break; + case 10000000: + gcm = gcm_10000000; + break; + case 12352000: + gcm = gcm_12352000; + break; + case 16384000: + gcm = gcm_16384000; + break; + default: + dev_err(pef2256->dev, "Unsupported v2.x MCLK rate %lu\n", mclk_rate); + return -EINVAL; + } + for (i = 0; i < 8; i++) + pef2256_write8(pef2256, PEF2256_GCM(i+1), gcm[i]); + + return 0; +} + +static int pef2256_setup_gcm(struct pef2256 *pef2256) +{ + return (pef2256->version == PEF2256_VERSION_1_2) ? + pef2256_12_setup_gcm(pef2256) : pef2256_2x_setup_gcm(pef2256); +} + +static int pef2256_setup_e1(struct pef2256 *pef2256) +{ + u8 fmr1, fmr2, sic1; + int ret; + + /* Basic setup, Master clocking mode (GCM8..1) */ + ret = pef2256_setup_gcm(pef2256); + if (ret) + return ret; + + /* RCLK output : DPLL clock, DCO-X enabled, DCO-X internal ref clock */ + pef2256_write8(pef2256, PEF2256_CMR1, 0x00); + + /* + * SCLKR selected, SCLKX selected, + * receive synchro pulse sourced by SYPR, + * transmit synchro pulse sourced by SYPX + */ + pef2256_write8(pef2256, PEF2256_CMR2, 0x00); + + /* NRZ coding, no alarm simulation */ + pef2256_write8(pef2256, PEF2256_FMR0, 0x00); + + /* + * E1, frame format, 2 Mbit/s system data rate, no AIS + * transmission to remote end or system interface, payload loop + * off, transmit remote alarm on + */ + fmr1 = 0x00; + fmr2 = PEF2256_FMR2_AXRA; + switch (pef2256->frame_type) { + case PEF2256_FRAME_E1_DOUBLEFRAME: + fmr2 |= PEF2256_FMR2_RFS_DOUBLEFRAME; + break; + case PEF2256_FRAME_E1_CRC4_MULTIFRAME: + fmr1 |= PEF2256_FMR1_XFS; + fmr2 |= PEF2256_FMR2_RFS_CRC4_MULTIFRAME; + break; + case PEF2256_FRAME_E1_AUTO_MULTIFRAME: + fmr1 |= PEF2256_FMR1_XFS; + fmr2 |= PEF2256_FMR2_RFS_AUTO_MULTIFRAME; + break; + default: + dev_err(pef2256->dev, "Unsupported frame type %d\n", pef2256->frame_type); + return -EINVAL; + } + pef2256_write8(pef2256, PEF2256_FMR1, fmr1); + pef2256_write8(pef2256, PEF2256_FMR2, fmr2); + + /* E1 default for the receive slicer threshold */ + pef2256_write8(pef2256, PEF2256_LIM2, PEF2256_LIM2_SLT_THR50); + if (!pef2256->is_subordinate) { + /* SEC input, active high */ + pef2256_write8(pef2256, PEF2256_GPC1, PEF2256_GPC1_CSFP_SEC_IN_HIGH); + } else { + /* Loop-timed */ + pef2256_setbits8(pef2256, PEF2256_LIM2, PEF2256_LIM2_ELT); + /* FSC output, active high */ + pef2256_write8(pef2256, PEF2256_GPC1, PEF2256_GPC1_CSFP_FSC_OUT_HIGH); + } + + /* internal second timer, power on */ + pef2256_write8(pef2256, PEF2256_GCR, 0x00); + + /* + * slave mode, local loop off, mode short-haul + * In v2.x, bit3 is a forced 1 bit in the datasheet -> Need to be set. + */ + if (pef2256->version == PEF2256_VERSION_1_2) + pef2256_write8(pef2256, PEF2256_LIM0, 0x00); + else + pef2256_write8(pef2256, PEF2256_LIM0, PEF2256_2X_LIM0_BIT3); + + /* analog interface selected, remote loop off */ + pef2256_write8(pef2256, PEF2256_LIM1, 0x00); + + /* + * SCLKR, SCLKX, RCLK configured to inputs, + * XFMS active low, CLK1 and CLK2 pin configuration + */ + pef2256_write8(pef2256, PEF2256_PC5, 0x00); + pef2256_write8(pef2256, PEF2256_PC6, 0x00); + + /* + * 2.048 MHz system clocking rate, receive buffer 2 frames, transmit + * buffer bypass, data sampled and transmitted on the falling edge of + * SCLKR/X, automatic freeze signaling, data is active in the first + * channel phase + */ + pef2256_write8(pef2256, PEF2256_SIC1, 0x00); + pef2256_write8(pef2256, PEF2256_SIC2, 0x00); + pef2256_write8(pef2256, PEF2256_SIC3, 0x00); + + /* channel loop-back and single frame mode are disabled */ + pef2256_write8(pef2256, PEF2256_LOOP, 0x00); + + /* all bits of the transmitted service word are cleared */ + pef2256_write8(pef2256, PEF2256_XSW, PEF2256_XSW_XY(0x1F)); + /* CAS disabled and clear spare bit values */ + pef2256_write8(pef2256, PEF2256_XSP, 0x00); + + /* no transparent mode active */ + pef2256_write8(pef2256, PEF2256_TSWM, 0x00); + + /* + * the transmit clock offset is cleared + * the transmit time slot offset is cleared + */ + pef2256_write8(pef2256, PEF2256_XC0, 0x00); + + /* Keep default value for the transmit offset */ + pef2256_write8(pef2256, PEF2256_XC1, 0x9C); + + /* + * transmit pulse mask, default value from datasheet + * transmitter in tristate mode + */ + if (pef2256->version == PEF2256_VERSION_1_2) { + pef2256_write8(pef2256, PEF2256_XPM0, 0x7B); + pef2256_write8(pef2256, PEF2256_XPM1, 0x03); + pef2256_write8(pef2256, PEF2256_XPM2, PEF2256_XPM2_XLT | 0x00); + } else { + pef2256_write8(pef2256, PEF2256_XPM0, 0x9C); + pef2256_write8(pef2256, PEF2256_XPM1, 0x03); + pef2256_write8(pef2256, PEF2256_XPM2, PEF2256_XPM2_XLT | 0x00); + } + + /* "master" mode */ + if (!pef2256->is_subordinate) + pef2256_setbits8(pef2256, PEF2256_LIM0, PEF2256_LIM0_MAS); + + /* transmit line in normal operation */ + pef2256_clrbits8(pef2256, PEF2256_XPM2, PEF2256_XPM2_XLT); + + if (pef2256->version == PEF2256_VERSION_1_2) { + /* receive input threshold = 0,21V */ + pef2256_clrsetbits8(pef2256, PEF2256_LIM1, PEF2256_12_LIM1_RIL_MASK, + PEF2256_12_LIM1_RIL_210); + } else { + /* receive input threshold = 0,21V */ + pef2256_clrsetbits8(pef2256, PEF2256_LIM1, PEF2256_2X_LIM1_RIL_MASK, + PEF2256_2X_LIM1_RIL_210); + } + /* transmit line coding = HDB3 */ + pef2256_clrsetbits8(pef2256, PEF2256_FMR0, PEF2256_FMR0_XC_MASK, + PEF2256_FMR0_XC_HDB3); + + /* receive line coding = HDB3 */ + pef2256_clrsetbits8(pef2256, PEF2256_FMR0, PEF2256_FMR0_RC_MASK, + PEF2256_FMR0_RC_HDB3); + + /* detection of LOS alarm = 176 pulses (ie (10 + 1) * 16) */ + pef2256_write8(pef2256, PEF2256_PCD, 10); + + /* recovery of LOS alarm = 22 pulses (ie 21 + 1) */ + pef2256_write8(pef2256, PEF2256_PCR, 21); + + /* DCO-X center frequency enabled */ + pef2256_setbits8(pef2256, PEF2256_CMR2, PEF2256_CMR2_DCOXC); + + if (pef2256->is_subordinate) { + /* select RCLK source = 2M */ + pef2256_clrsetbits8(pef2256, PEF2256_CMR1, PEF2256_CMR1_RS_MASK, + PEF2256_CMR1_RS_DCOR_2048); + /* disable switching from RCLK to SYNC */ + pef2256_setbits8(pef2256, PEF2256_CMR1, PEF2256_CMR1_DCS); + } + + if (pef2256->version != PEF2256_VERSION_1_2) { + /* during inactive channel phase switch RDO/RSIG into tri-state */ + pef2256_setbits8(pef2256, PEF2256_SIC3, PEF2256_SIC3_RTRI); + } + + if (!pef2256->is_tx_falling_edge) { + /* rising edge sync pulse transmit */ + pef2256_clrsetbits8(pef2256, PEF2256_SIC3, + PEF2256_SIC3_RESR, PEF2256_SIC3_RESX); + } else { + /* rising edge sync pulse receive */ + pef2256_clrsetbits8(pef2256, PEF2256_SIC3, + PEF2256_SIC3_RESX, PEF2256_SIC3_RESR); + } + + /* transmit offset counter (XCO10..0) = 4 */ + pef2256_write8(pef2256, PEF2256_XC0, 0); + pef2256_write8(pef2256, PEF2256_XC1, 4); + /* receive offset counter (RCO10..0) = 4 */ + pef2256_write8(pef2256, PEF2256_RC0, 0); + pef2256_write8(pef2256, PEF2256_RC1, 4); + + /* system clock rate */ + switch (pef2256->sysclk_rate) { + case 2048000: + sic1 = PEF2256_SIC1_SSC_2048; + break; + case 4096000: + sic1 = PEF2256_SIC1_SSC_4096; + break; + case 8192000: + sic1 = PEF2256_SIC1_SSC_8192; + break; + case 16384000: + sic1 = PEF2256_SIC1_SSC_16384; + break; + default: + dev_err(pef2256->dev, "Unsupported sysclk rate %u\n", pef2256->sysclk_rate); + return -EINVAL; + } + pef2256_clrsetbits8(pef2256, PEF2256_SIC1, PEF2256_SIC1_SSC_MASK, sic1); + + /* data clock rate */ + switch (pef2256->data_rate) { + case 2048000: + fmr1 = PEF2256_FMR1_SSD_2048; + sic1 = PEF2256_SIC1_SSD_2048; + break; + case 4096000: + fmr1 = PEF2256_FMR1_SSD_4096; + sic1 = PEF2256_SIC1_SSD_4096; + break; + case 8192000: + fmr1 = PEF2256_FMR1_SSD_8192; + sic1 = PEF2256_SIC1_SSD_8192; + break; + case 16384000: + fmr1 = PEF2256_FMR1_SSD_16384; + sic1 = PEF2256_SIC1_SSD_16384; + break; + default: + dev_err(pef2256->dev, "Unsupported data rate %u\n", pef2256->data_rate); + return -EINVAL; + } + pef2256_clrsetbits8(pef2256, PEF2256_FMR1, PEF2256_FMR1_SSD_MASK, fmr1); + pef2256_clrsetbits8(pef2256, PEF2256_SIC1, PEF2256_SIC1_SSD_MASK, sic1); + + /* channel phase */ + pef2256_clrsetbits8(pef2256, PEF2256_SIC2, PEF2256_SIC2_SICS_MASK, + PEF2256_SIC2_SICS(pef2256->channel_phase)); + + if (pef2256->is_subordinate) { + /* transmit buffer size = 2 frames */ + pef2256_clrsetbits8(pef2256, PEF2256_SIC1, PEF2256_SIC1_XBS_MASK, + PEF2256_SIC1_XBS_2FRAMES); + /* transmit transparent mode */ + pef2256_setbits8(pef2256, PEF2256_XSW, PEF2256_XSW_XTM); + } + + /* error counter latched every 1s */ + pef2256_setbits8(pef2256, PEF2256_FMR1, PEF2256_FMR1_ECM); + /* error counter mode COFA */ + pef2256_setbits8(pef2256, PEF2256_GCR, PEF2256_GCR_ECMC); + /* errors in service words have no influence */ + pef2256_setbits8(pef2256, PEF2256_RC0, PEF2256_RC0_SWD); + /* 4 consecutive incorrect FAS causes loss of sync */ + pef2256_setbits8(pef2256, PEF2256_RC0, PEF2256_RC0_ASY4); + /* Si-Bit, Spare bit For International, FAS word */ + pef2256_setbits8(pef2256, PEF2256_XSW, PEF2256_XSW_XSIS); + pef2256_setbits8(pef2256, PEF2256_XSP, PEF2256_XSP_XSIF); + + /* port RCLK is output */ + pef2256_setbits8(pef2256, PEF2256_PC5, PEF2256_PC5_CRP); + /* status changed interrupt at both up and down */ + pef2256_setbits8(pef2256, PEF2256_GCR, PEF2256_GCR_SCI); + + /* Clear any ISR2 pending interrupts and unmask needed interrupts */ + pef2256_read8(pef2256, PEF2256_ISR2); + pef2256_clrbits8(pef2256, PEF2256_IMR2, PEF2256_INT2_LOS | PEF2256_INT2_AIS); + + /* reset lines */ + pef2256_write8(pef2256, PEF2256_CMDR, PEF2256_CMDR_RRES | PEF2256_CMDR_XRES); + return 0; +} + +static int pef2256_setup(struct pef2256 *pef2256) +{ + if (!pef2256->is_e1) { + dev_err(pef2256->dev, "Only E1 line is currently supported\n"); + return -EOPNOTSUPP; + } + + return pef2256_setup_e1(pef2256); +} + + + +static void pef2256_isr_default_handler(struct pef2256 *pef2256, u8 nbr, u8 isr) +{ + dev_warn(pef2256->dev, "ISR%u: 0x%02x not handled\n", nbr, isr); +} + +static bool pef2256_is_carrier_on(struct pef2256 *pef2256) +{ + u8 frs0; + + frs0 = pef2256_read8(pef2256, PEF2256_FRS0); + return !(frs0 & (PEF2256_FRS0_LOS | PEF2256_FRS0_AIS)); +} + +static void pef2256_isr2_handler(struct pef2256 *pef2256, u8 nbr, u8 isr) +{ + bool is_changed = false; + unsigned long flags; + bool is_carrier_on; + + if (isr & (PEF2256_INT2_LOS | PEF2256_INT2_AIS)) { + + spin_lock_irqsave(&pef2256->lock, flags); + is_carrier_on = pef2256_is_carrier_on(pef2256); + if (is_carrier_on != pef2256->is_carrier_on) { + pef2256->is_carrier_on = is_carrier_on; + is_changed = true; + } + spin_unlock_irqrestore(&pef2256->lock, flags); + + if (is_changed) + atomic_notifier_call_chain(&pef2256->event_notifier_list, + PEF2256_EVENT_CARRIER, NULL); + } +} + +static irqreturn_t pef2256_irq_handler(int irq, void *priv) +{ + void (*pef2256_isr_handler[])(struct pef2256 *, u8, u8) = { + [0] = pef2256_isr_default_handler, + [1] = pef2256_isr_default_handler, + [2] = pef2256_isr2_handler, + [3] = pef2256_isr_default_handler, + [4] = pef2256_isr_default_handler, + [5] = pef2256_isr_default_handler + }; + struct pef2256 *pef2256 = (struct pef2256 *)priv; + u8 gis; + u8 isr; + u8 n; + + gis = pef2256_read8(pef2256, PEF2256_GIS); + + for (n = 0; n < ARRAY_SIZE(pef2256_isr_handler) ; n++) { + if (gis & PEF2256_GIS_ISR(n)) { + isr = pef2256_read8(pef2256, PEF2256_ISR(n)); + pef2256_isr_handler[n](pef2256, n, isr); + } + } + + return IRQ_HANDLED; +} + +static int pef2256_check_rates(struct pef2256 *pef2256, unsigned long sysclk_rate, + unsigned long data_rate) +{ + unsigned long rate; + + switch (sysclk_rate) { + case 2048000: + case 4096000: + case 8192000: + case 16384000: + break; + default: + dev_err(pef2256->dev, "Unsupported system clock rate %lu\n", sysclk_rate); + return -EINVAL; + } + + for (rate = data_rate; rate <= data_rate * 4; rate *= 2) { + if (rate == sysclk_rate) + return 0; + } + dev_err(pef2256->dev, "Unsupported data rate %lu with system clock rate %lu\n", + data_rate, sysclk_rate); + return -EINVAL; +} + +static int pef2556_of_parse(struct pef2256 *pef2256, struct device_node *np) +{ + const char *str; + int ret; + + str = "e1"; + ret = of_property_read_string(np, "lantiq,line-interface", &str); + if (ret && ret != -EINVAL) { + dev_err(pef2256->dev, "%pOF: failed to read lantiq,line-interface\n", + np); + return ret; + } + if (!strcmp(str, "e1")) { + pef2256->is_e1 = true; + } else if (!strcmp(str, "t1j1")) { + pef2256->is_e1 = false; + } else { + dev_err(pef2256->dev, "%pOF: Invalid lantiq,line-interface (%s)\n", + np, str); + return -EINVAL; + } + dev_dbg(pef2256->dev, "config: %s line\n", pef2256->is_e1 ? "E1" : "T1/J1"); + + pef2256->sysclk_rate = 2048000; + ret = of_property_read_u32(np, "lantiq,sysclk-rate-hz", &pef2256->sysclk_rate); + if (ret && ret != -EINVAL) { + dev_err(pef2256->dev, "%pOF: failed to read lantiq,sysclk-rate-hz\n", np); + return ret; + } + dev_dbg(pef2256->dev, "config: sysclk %u Hz\n", pef2256->sysclk_rate); + + pef2256->data_rate = 2048000; + ret = of_property_read_u32(np, "lantiq,data-rate-bps", &pef2256->data_rate); + if (ret && ret != -EINVAL) { + dev_err(pef2256->dev, "%pOF: failed to read lantiq,data-rate-bps\n", np); + return ret; + } + dev_dbg(pef2256->dev, "config: data rate %u bps\n", pef2256->data_rate); + + ret = pef2256_check_rates(pef2256, pef2256->sysclk_rate, pef2256->data_rate); + if (ret) + return ret; + + pef2256->is_tx_falling_edge = of_property_read_bool(np, "lantiq,clock-falling-edge"); + dev_dbg(pef2256->dev, "config: tx on %s edge\n", + pef2256->is_tx_falling_edge ? "falling" : "rising"); + + pef2256->is_subordinate = of_property_read_bool(np, "lantiq,subordinate"); + dev_dbg(pef2256->dev, "config: subordinate %s\n", + pef2256->is_subordinate ? "on" : "off"); + + str = pef2256->is_e1 ? "doubleframe" : "12frame"; + ret = of_property_read_string(np, "lantiq,frame-format", &str); + if (ret && ret != -EINVAL) { + dev_err(pef2256->dev, "%pOF: failed to read lantiq,frame-format\n", + np); + return ret; + } + if (pef2256->is_e1) { + if (!strcmp(str, "doubleframe")) { + pef2256->frame_type = PEF2256_FRAME_E1_DOUBLEFRAME; + } else if (!strcmp(str, "crc4-multiframe")) { + pef2256->frame_type = PEF2256_FRAME_E1_CRC4_MULTIFRAME; + } else if (!strcmp(str, "auto-multiframe")) { + pef2256->frame_type = PEF2256_FRAME_E1_AUTO_MULTIFRAME; + } else { + dev_err(pef2256->dev, "%pOF: Invalid lantiq,frame-format (%s)\n", + np, str); + return -EINVAL; + } + } else { + if (!strcmp(str, "4frame")) { + pef2256->frame_type = PEF2256_FRAME_T1J1_4FRAME; + } else if (!strcmp(str, "12frame")) { + pef2256->frame_type = PEF2256_FRAME_T1J1_12FRAME; + } else if (!strcmp(str, "24frame")) { + pef2256->frame_type = PEF2256_FRAME_T1J1_24FRAME; + } else if (!strcmp(str, "72frame")) { + pef2256->frame_type = PEF2256_FRAME_T1J1_72FRAME; + } else { + dev_err(pef2256->dev, "%pOF: Invalid lantiq,frame-format (%s)\n", + np, str); + return -EINVAL; + } + } + dev_dbg(pef2256->dev, "config: frame type %d\n", pef2256->frame_type); + + pef2256->channel_phase = 0; + ret = of_property_read_u8(np, "lantiq,channel-phase", &pef2256->channel_phase); + if (ret && ret != -EINVAL) { + dev_err(pef2256->dev, "%pOF: failed to read lantiq,channel-phase\n", + np); + return ret; + } + if (pef2256->channel_phase >= pef2256->sysclk_rate / pef2256->data_rate) { + dev_err(pef2256->dev, "%pOF: Invalid lantiq,channel-phase %u\n", + np, pef2256->channel_phase); + return -EINVAL; + } + dev_dbg(pef2256->dev, "config: channel phase %u\n", pef2256->channel_phase); + + return 0; +} + +static int pef2256_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct pef2256 *pef2256 = pinctrl_dev_get_drvdata(pctldev); + + /* We map 1 group <-> 1 pin */ + return pef2256->pinctrl.pctrl_desc.npins; +} + +static const char *pef2256_get_group_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + struct pef2256 *pef2256 = pinctrl_dev_get_drvdata(pctldev); + + /* We map 1 group <-> 1 pin */ + return pef2256->pinctrl.pctrl_desc.pins[selector].name; +} + +static int pef2256_get_group_pins(struct pinctrl_dev *pctldev, unsigned int selector, + const unsigned int **pins, + unsigned int *num_pins) +{ + struct pef2256 *pef2256 = pinctrl_dev_get_drvdata(pctldev); + + /* We map 1 group <-> 1 pin */ + *pins = &pef2256->pinctrl.pctrl_desc.pins[selector].number; + *num_pins = 1; + + return 0; +} + +static const struct pinctrl_ops pef2256_pctlops = { + .get_groups_count = pef2256_get_groups_count, + .get_group_name = pef2256_get_group_name, + .get_group_pins = pef2256_get_group_pins, + .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, + .dt_free_map = pinconf_generic_dt_free_map, +}; + +static int pef2256_get_functions_count(struct pinctrl_dev *pctldev) +{ + struct pef2256 *pef2256 = pinctrl_dev_get_drvdata(pctldev); + + return pef2256->pinctrl.nfunctions; +} + +static const char *pef2256_get_function_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + struct pef2256 *pef2256 = pinctrl_dev_get_drvdata(pctldev); + + return pef2256->pinctrl.functions[selector].name; +} + + +static int pef2256_get_function_groups(struct pinctrl_dev *pctldev, unsigned int selector, + const char * const **groups, + unsigned * const num_groups) +{ + struct pef2256 *pef2256 = pinctrl_dev_get_drvdata(pctldev); + + *groups = pef2256->pinctrl.functions[selector].groups; + *num_groups = pef2256->pinctrl.functions[selector].ngroups; + return 0; +} + +static int pef2256_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector, + unsigned int group_selector) +{ + struct pef2256 *pef2256 = pinctrl_dev_get_drvdata(pctldev); + const struct pef2256_pinreg_desc *pinreg_desc; + u8 func_val; + + dev_dbg(pef2256->dev, "set %s to %s function\n", + pef2256->pinctrl.pctrl_desc.pins[group_selector].name, + pef2256->pinctrl.functions[func_selector].name); + + /* We map 1 group <-> 1 pin */ + pinreg_desc = pef2256->pinctrl.pctrl_desc.pins[group_selector].drv_data; + func_val = pef2256->pinctrl.functions[func_selector].func_val; + + pef2256_clrsetbits8(pef2256, pinreg_desc->offset, pinreg_desc->mask, + func_val & pinreg_desc->mask); + + return 0; +} + +static const struct pinmux_ops pef2256_pmxops = { + .get_functions_count = pef2256_get_functions_count, + .get_function_name = pef2256_get_function_name, + .get_function_groups = pef2256_get_function_groups, + .set_mux = pef2256_set_mux, +}; + +#define PEF2256_PINCTRL_PIN(_number, _name, _offset, _mask) { \ + .number = _number, \ + .name = _name, \ + .drv_data = &(struct pef2256_pinreg_desc) { \ + .offset = _offset, \ + .mask = _mask, \ + }, \ +} + +static const struct pinctrl_pin_desc const pef2256_v12_pins[] = { + PEF2256_PINCTRL_PIN(0, "RPA", PEF2256_PC1, PEF2256_12_PC_RPC_MASK), + PEF2256_PINCTRL_PIN(1, "RPB", PEF2256_PC2, PEF2256_12_PC_RPC_MASK), + PEF2256_PINCTRL_PIN(2, "RPC", PEF2256_PC3, PEF2256_12_PC_RPC_MASK), + PEF2256_PINCTRL_PIN(3, "RPD", PEF2256_PC4, PEF2256_12_PC_RPC_MASK), + PEF2256_PINCTRL_PIN(4, "XPA", PEF2256_PC1, PEF2256_12_PC_XPC_MASK), + PEF2256_PINCTRL_PIN(5, "XPB", PEF2256_PC2, PEF2256_12_PC_XPC_MASK), + PEF2256_PINCTRL_PIN(6, "XPC", PEF2256_PC3, PEF2256_12_PC_XPC_MASK), + PEF2256_PINCTRL_PIN(7, "XPD", PEF2256_PC4, PEF2256_12_PC_XPC_MASK), +}; + +static const struct pinctrl_pin_desc const pef2256_v2x_pins[] = { + PEF2256_PINCTRL_PIN(0, "RPA", PEF2256_PC1, PEF2256_2X_PC_RPC_MASK), + PEF2256_PINCTRL_PIN(1, "RPB", PEF2256_PC2, PEF2256_2X_PC_RPC_MASK), + PEF2256_PINCTRL_PIN(2, "RPC", PEF2256_PC3, PEF2256_2X_PC_RPC_MASK), + PEF2256_PINCTRL_PIN(3, "RPD", PEF2256_PC4, PEF2256_2X_PC_RPC_MASK), + PEF2256_PINCTRL_PIN(4, "XPA", PEF2256_PC1, PEF2256_2X_PC_XPC_MASK), + PEF2256_PINCTRL_PIN(5, "XPB", PEF2256_PC2, PEF2256_2X_PC_XPC_MASK), + PEF2256_PINCTRL_PIN(6, "XPC", PEF2256_PC3, PEF2256_2X_PC_XPC_MASK), + PEF2256_PINCTRL_PIN(7, "XPD", PEF2256_PC4, PEF2256_2X_PC_XPC_MASK), +}; + +static const char *const pef2256_rp_groups[] = { "RPA", "RPB", "RPC", "RPD" }; +static const char *const pef2256_xp_groups[] = { "XPA", "XPB", "XPC", "XPD" }; +static const char *const pef2256_all_groups[] = { "RPA", "RPB", "RPC", "RPD", + "XPA", "XPB", "XPC", "XPD" }; + +#define PEF2256_FUNCTION(_name, _func_val, _groups) { \ + .name = _name, \ + .groups = _groups, \ + .ngroups = ARRAY_SIZE(_groups), \ + .func_val = _func_val, \ +} + +static const struct pef2256_function_desc pef2256_v2x_functions[] = { + PEF2256_FUNCTION("SYPR", PEF2256_2X_PC_RPC_SYPR, pef2256_rp_groups), + PEF2256_FUNCTION("RFM", PEF2256_2X_PC_RPC_RFM, pef2256_rp_groups), + PEF2256_FUNCTION("RFMB", PEF2256_2X_PC_RPC_RFMB, pef2256_rp_groups), + PEF2256_FUNCTION("RSIGM", PEF2256_2X_PC_RPC_RSIGM, pef2256_rp_groups), + PEF2256_FUNCTION("RSIG", PEF2256_2X_PC_RPC_RSIG, pef2256_rp_groups), + PEF2256_FUNCTION("DLR", PEF2256_2X_PC_RPC_DLR, pef2256_rp_groups), + PEF2256_FUNCTION("FREEZE", PEF2256_2X_PC_RPC_FREEZE, pef2256_rp_groups), + PEF2256_FUNCTION("RFSP", PEF2256_2X_PC_RPC_RFSP, pef2256_rp_groups), + PEF2256_FUNCTION("LOS", PEF2256_2X_PC_RPC_LOS, pef2256_rp_groups), + + PEF2256_FUNCTION("SYPX", PEF2256_2X_PC_XPC_SYPX, pef2256_xp_groups), + PEF2256_FUNCTION("XFMS", PEF2256_2X_PC_XPC_XFMS, pef2256_xp_groups), + PEF2256_FUNCTION("XSIG", PEF2256_2X_PC_XPC_XSIG, pef2256_xp_groups), + PEF2256_FUNCTION("TCLK", PEF2256_2X_PC_XPC_TCLK, pef2256_xp_groups), + PEF2256_FUNCTION("XMFB", PEF2256_2X_PC_XPC_XMFB, pef2256_xp_groups), + PEF2256_FUNCTION("XSIGM", PEF2256_2X_PC_XPC_XSIGM, pef2256_xp_groups), + PEF2256_FUNCTION("DLX", PEF2256_2X_PC_XPC_DLX, pef2256_xp_groups), + PEF2256_FUNCTION("XCLK", PEF2256_2X_PC_XPC_XCLK, pef2256_xp_groups), + PEF2256_FUNCTION("XLT", PEF2256_2X_PC_XPC_XLT, pef2256_xp_groups), + + PEF2256_FUNCTION("GPI", PEF2256_2X_PC_RPC_GPI | PEF2256_2X_PC_XPC_GPI, + pef2256_all_groups), + PEF2256_FUNCTION("GPOH", PEF2256_2X_PC_RPC_GPOH | PEF2256_2X_PC_XPC_GPOH, + pef2256_all_groups), + PEF2256_FUNCTION("GPOL", PEF2256_2X_PC_RPC_GPOL | PEF2256_2X_PC_XPC_GPOL, + pef2256_all_groups), +}; + +static const struct pef2256_function_desc pef2256_v12_functions[] = { + PEF2256_FUNCTION("SYPR", PEF2256_12_PC_RPC_SYPR, pef2256_rp_groups), + PEF2256_FUNCTION("RFM", PEF2256_12_PC_RPC_RFM, pef2256_rp_groups), + PEF2256_FUNCTION("RFMB", PEF2256_12_PC_RPC_RFMB, pef2256_rp_groups), + PEF2256_FUNCTION("RSIGM", PEF2256_12_PC_RPC_RSIGM, pef2256_rp_groups), + PEF2256_FUNCTION("RSIG", PEF2256_12_PC_RPC_RSIG, pef2256_rp_groups), + PEF2256_FUNCTION("DLR", PEF2256_12_PC_RPC_DLR, pef2256_rp_groups), + PEF2256_FUNCTION("FREEZE", PEF2256_12_PC_RPC_FREEZE, pef2256_rp_groups), + PEF2256_FUNCTION("RFSP", PEF2256_12_PC_RPC_RFSP, pef2256_rp_groups), + + PEF2256_FUNCTION("SYPX", PEF2256_12_PC_XPC_SYPX, pef2256_xp_groups), + PEF2256_FUNCTION("XFMS", PEF2256_12_PC_XPC_XFMS, pef2256_xp_groups), + PEF2256_FUNCTION("XSIG", PEF2256_12_PC_XPC_XSIG, pef2256_xp_groups), + PEF2256_FUNCTION("TCLK", PEF2256_12_PC_XPC_TCLK, pef2256_xp_groups), + PEF2256_FUNCTION("XMFB", PEF2256_12_PC_XPC_XMFB, pef2256_xp_groups), + PEF2256_FUNCTION("XSIGM", PEF2256_12_PC_XPC_XSIGM, pef2256_xp_groups), + PEF2256_FUNCTION("DLX", PEF2256_12_PC_XPC_DLX, pef2256_xp_groups), + PEF2256_FUNCTION("XCLK", PEF2256_12_PC_XPC_XCLK, pef2256_xp_groups), + PEF2256_FUNCTION("XLT", PEF2256_12_PC_XPC_XLT, pef2256_xp_groups), +}; + + +static int pef2256_register_pinctrl(struct pef2256 *pef2256) +{ + struct pinctrl_dev *pctrl; + + pef2256->pinctrl.pctrl_desc.name = dev_name(pef2256->dev); + pef2256->pinctrl.pctrl_desc.owner = THIS_MODULE; + pef2256->pinctrl.pctrl_desc.pctlops = &pef2256_pctlops; + pef2256->pinctrl.pctrl_desc.pmxops = &pef2256_pmxops; + if (pef2256->version == PEF2256_VERSION_1_2) { + pef2256->pinctrl.pctrl_desc.pins = pef2256_v12_pins; + pef2256->pinctrl.pctrl_desc.npins = ARRAY_SIZE(pef2256_v12_pins); + pef2256->pinctrl.functions = pef2256_v12_functions; + pef2256->pinctrl.nfunctions = ARRAY_SIZE(pef2256_v12_functions); + } else { + pef2256->pinctrl.pctrl_desc.pins = pef2256_v2x_pins; + pef2256->pinctrl.pctrl_desc.npins = ARRAY_SIZE(pef2256_v2x_pins); + pef2256->pinctrl.functions = pef2256_v2x_functions; + pef2256->pinctrl.nfunctions = ARRAY_SIZE(pef2256_v2x_functions); + } + + + pctrl = devm_pinctrl_register(pef2256->dev, &pef2256->pinctrl.pctrl_desc, pef2256); + if (IS_ERR(pctrl)) { + dev_err(pef2256->dev, "pinctrl driver registration failed\n"); + return PTR_ERR(pctrl); + } + + return 0; +} + +static void pef2256_reset_pinmux(struct pef2256 *pef2256) +{ + u8 val; + /* + * Reset values cannot be used. + * They define the SYPR/SYPX pin mux for all the RPx and XPx pins and + * Only one pin can be muxed to SYPR and one pin can be muxed to SYPX. + * Choose here an other reset value. + */ + if (pef2256->version == PEF2256_VERSION_1_2) + val = PEF2256_12_PC_XPC_XCLK | PEF2256_12_PC_RPC_RFSP; + else + val = PEF2256_2X_PC_XPC_GPI | PEF2256_2X_PC_RPC_GPI; + + pef2256_write8(pef2256, PEF2256_PC1, val); + pef2256_write8(pef2256, PEF2256_PC2, val); + pef2256_write8(pef2256, PEF2256_PC3, val); + pef2256_write8(pef2256, PEF2256_PC4, val); +} + +static ssize_t subordinate_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct pef2256 *pef2256 = dev_get_drvdata(dev); + + return sysfs_emit(buf, "%d\n", pef2256->is_subordinate); +} + +static ssize_t subordinate_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + struct pef2256 *pef2256 = dev_get_drvdata(dev); + int ret; + + if (strtobool(buf, &pef2256->is_subordinate) < 0) + return -EINVAL; + + ret = pef2256_setup(pef2256); + if (ret) + return ret; + + return count; +} + +static DEVICE_ATTR_RW(subordinate); + +static const struct attribute_group pef2256_attribute_group = { + .attrs = (struct attribute *[]) { + &dev_attr_subordinate.attr, + NULL, + }, +}; + +static int pef2256_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + struct pef2256 *pef2256; + int ret; + int irq; + + pef2256 = devm_kzalloc(&pdev->dev, sizeof(*pef2256), GFP_KERNEL); + if (!pef2256) + return -ENOMEM; + + pef2256->dev = &pdev->dev; + spin_lock_init(&pef2256->lock); + ATOMIC_INIT_NOTIFIER_HEAD(&pef2256->event_notifier_list); + + pef2256->regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(pef2256->regs)) + return PTR_ERR(pef2256->regs); + + pef2256->mclk = devm_clk_get_enabled(&pdev->dev, "mclk"); + if (IS_ERR(pef2256->mclk)) + return PTR_ERR(pef2256->mclk); + dev_dbg(pef2256->dev, "mclk %lu Hz\n", clk_get_rate(pef2256->mclk)); + + /* Reset the component. The MCLK clock must be active during reset */ + pef2256->reset_gpio = devm_gpiod_get_optional(&pdev->dev, "reset", GPIOD_OUT_LOW); + if (IS_ERR(pef2256->reset_gpio)) + return PTR_ERR(pef2256->reset_gpio); + if (pef2256->reset_gpio) { + gpiod_set_value_cansleep(pef2256->reset_gpio, 1); + udelay(10); + gpiod_set_value_cansleep(pef2256->reset_gpio, 0); + udelay(10); + } + + pef2256->version = pef2256_get_version(pef2256); + if (pef2256->version == PEF2256_VERSION_UNKNOWN) + return -ENODEV; + + ret = pef2556_of_parse(pef2256, np); + if (ret) + return ret; + + /* Disable interrupts */ + pef2256_write8(pef2256, PEF2256_IMR0, 0xff); + pef2256_write8(pef2256, PEF2256_IMR1, 0xff); + pef2256_write8(pef2256, PEF2256_IMR2, 0xff); + pef2256_write8(pef2256, PEF2256_IMR3, 0xff); + pef2256_write8(pef2256, PEF2256_IMR4, 0xff); + pef2256_write8(pef2256, PEF2256_IMR5, 0xff); + + /* Clear any pending interrupts */ + pef2256_read8(pef2256, PEF2256_ISR0); + pef2256_read8(pef2256, PEF2256_ISR1); + pef2256_read8(pef2256, PEF2256_ISR2); + pef2256_read8(pef2256, PEF2256_ISR3); + pef2256_read8(pef2256, PEF2256_ISR4); + pef2256_read8(pef2256, PEF2256_ISR5); + + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + ret = devm_request_irq(pef2256->dev, irq, pef2256_irq_handler, 0, "pef2256", pef2256); + if (ret < 0) + return ret; + + pef2256_reset_pinmux(pef2256); + ret = pef2256_register_pinctrl(pef2256); + if (ret) + return ret; + + /* + * We are going to reset the E1 lines during setup() call and the ISR2 + * interrupt used to detect the carrier state changed is masked. + * It is time to initialize our internal carrier state flag. + */ + pef2256->is_carrier_on = false; + + ret = pef2256_setup(pef2256); + if (ret) + return ret; + + platform_set_drvdata(pdev, pef2256); + + ret = sysfs_create_group(&pef2256->dev->kobj, &pef2256_attribute_group); + if (ret < 0) { + dev_err(pef2256->dev, "sysfs registration failed (%d)\n", ret); + platform_set_drvdata(pdev, NULL); + return ret; + } + + return 0; +} + +static int pef2256_remove(struct platform_device *pdev) +{ + struct pef2256 *pef2256 = platform_get_drvdata(pdev); + + /* Disable interrupts */ + pef2256_write8(pef2256, PEF2256_IMR0, 0xff); + pef2256_write8(pef2256, PEF2256_IMR1, 0xff); + pef2256_write8(pef2256, PEF2256_IMR2, 0xff); + pef2256_write8(pef2256, PEF2256_IMR3, 0xff); + pef2256_write8(pef2256, PEF2256_IMR4, 0xff); + pef2256_write8(pef2256, PEF2256_IMR5, 0xff); + + sysfs_remove_group(&pef2256->dev->kobj, &pef2256_attribute_group); + + return 0; +} + +static const struct of_device_id pef2256_id_table[] = { + { .compatible = "lantiq,pef2256" }, + {} /* sentinel */ +}; +MODULE_DEVICE_TABLE(of, pef2256_id_table); + +static struct platform_driver pef2256_driver = { + .driver = { + .name = "lantiq-pef2256", + .of_match_table = of_match_ptr(pef2256_id_table), + }, + .probe = pef2256_probe, + .remove = pef2256_remove, +}; +module_platform_driver(pef2256_driver); + +struct pef2256 *pef2256_get_byphandle(struct device_node *np, const char *phandle_name) +{ + struct device_node *pef2256_np; + struct platform_device *pdev; + struct pef2256 *pef2256; + + pef2256_np = of_parse_phandle(np, phandle_name, 0); + if (!pef2256_np) + return ERR_PTR(-EINVAL); + + if (!of_match_node(pef2256_driver.driver.of_match_table, pef2256_np)) { + of_node_put(pef2256_np); + return ERR_PTR(-EINVAL); + } + + pdev = of_find_device_by_node(pef2256_np); + of_node_put(pef2256_np); + if (!pdev) + return ERR_PTR(-ENODEV); + + pef2256 = platform_get_drvdata(pdev); + if (!pef2256) { + platform_device_put(pdev); + return ERR_PTR(-EPROBE_DEFER); + } + + return pef2256; +} +EXPORT_SYMBOL(pef2256_get_byphandle); + +void pef2256_put(struct pef2256 *pef2256) +{ + put_device(pef2256->dev); +} +EXPORT_SYMBOL(pef2256_put); + +static void devm_pef2256_release(struct device *dev, void *res) +{ + struct pef2256 **pef2256 = res; + + pef2256_put(*pef2256); +} + +struct pef2256 *devm_pef2256_get_byphandle(struct device *dev, struct device_node *np, + const char *phandle_name) +{ + struct pef2256 *pef2256; + struct pef2256 **dr; + + dr = devres_alloc(devm_pef2256_release, sizeof(*dr), GFP_KERNEL); + if (!dr) + return ERR_PTR(-ENOMEM); + + pef2256 = pef2256_get_byphandle(np, phandle_name); + if (!IS_ERR(pef2256)) { + *dr = pef2256; + devres_add(dev, dr); + } else { + devres_free(dr); + } + + return pef2256; +} +EXPORT_SYMBOL(devm_pef2256_get_byphandle); + +int pef2256_register_event_notifier(struct pef2256 *pef2256, struct notifier_block *nb) +{ + return atomic_notifier_chain_register(&pef2256->event_notifier_list, nb); +} +EXPORT_SYMBOL_GPL(pef2256_register_event_notifier); + +int pef2256_unregister_event_notifier(struct pef2256 *pef2256, struct notifier_block *nb) +{ + return atomic_notifier_chain_unregister(&pef2256->event_notifier_list, nb); +} +EXPORT_SYMBOL_GPL(pef2256_unregister_event_notifier); + +bool pef2256_get_carrier(struct pef2256 *pef2256) +{ + unsigned long flags; + bool is_carrier_on; + + spin_lock_irqsave(&pef2256->lock, flags); + is_carrier_on = pef2256->is_carrier_on; + spin_unlock_irqrestore(&pef2256->lock, flags); + + return is_carrier_on; +} +EXPORT_SYMBOL_GPL(pef2256_get_carrier); + +MODULE_AUTHOR("Herve Codina "); +MODULE_DESCRIPTION("PEF2256 driver"); +MODULE_LICENSE("GPL"); diff --git a/include/linux/pef2256.h b/include/linux/pef2256.h new file mode 100644 index 000000000000..6c8d173595b1 --- /dev/null +++ b/include/linux/pef2256.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * PEF2256 management + * + * Copyright 2023 CS GROUP France + * + * Author: Herve Codina + */ +#ifndef __PEF2256_H__ +#define __PEF2256_H__ + +#include + +struct pef2256; +struct device_node; +struct device; +struct notifier_block; + +struct pef2256 *pef2256_get_byphandle(struct device_node *np, const char *phandle_name); +void pef2256_put(struct pef2256 *pef2256); +struct pef2256 *devm_pef2256_get_byphandle(struct device *dev, struct device_node *np, + const char *phandle_name); + + +enum pef2256_event { + PEF2256_EVENT_CARRIER, /* Carrier state changed */ +}; + +/* The nb.notifier_call function registered must not sleep */ +int pef2256_register_event_notifier(struct pef2256 *pef2256, struct notifier_block *nb); +int pef2256_unregister_event_notifier(struct pef2256 *pef2256, struct notifier_block *nb); + +/* Retrieve carrier state. true: carrier on, false: carrier off */ +bool pef2256_get_carrier(struct pef2256 *pef2256); + +#endif /* __PEF2256_H__ */ From patchwork Wed Mar 15 13:42:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Herve Codina X-Patchwork-Id: 70234 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp2342585wrd; Wed, 15 Mar 2023 06:54:55 -0700 (PDT) X-Google-Smtp-Source: AK7set+YnrKWZ3p+v8ChQCsG8Eo4V9249uROKfBl6+c6+mbMTQ/IBgXfkHMgDpj0mpwtXd4whLgE X-Received: by 2002:a17:903:410a:b0:19f:2b42:5d01 with SMTP id r10-20020a170903410a00b0019f2b425d01mr2331784pld.9.1678888494711; Wed, 15 Mar 2023 06:54:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1678888494; cv=none; d=google.com; s=arc-20160816; b=sGMBlHFBzG2GtNceTC/nAwW06tna6gccKYvBP06jg7+a7ui3eOvU/kXCLUTt+Jf184 wbvq0viRyE+JTjv7VyRtQR1D3MW9pYclkaDABW9rxp4xwKQiF2PVZrfCcW4EmBQtORNy 4BHd+5xkZPe37fFE10R46pPSvw6Zd79mGCH06gUjPlhb7Hrb8RUMrAeU11w+8Qn0dZLT 0/RMHrR1eF4NPCpidbcMC8DYlpr0cwFr1Fmw6HWbkmB6R7uS5PRSBs2MTNUqCfiG3nDQ +fleatP4kvgETlyO+ostvXacUDRDuot8KBQ86AtqxPD5vVOk+1xGxLkbYKhHmh3/nTG5 8yPw== ARC-Message-Signature: i=1; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id g36-20020a631124000000b0050bc66eea60si4860094pgl.192.2023.03.15.06.54.41; Wed, 15 Mar 2023 06:54:54 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@bootlin.com header.s=gm1 header.b=Z5VllREu; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=bootlin.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232409AbjCONm7 (ORCPT + 99 others); Wed, 15 Mar 2023 09:42:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56990 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231667AbjCONmp (ORCPT ); Wed, 15 Mar 2023 09:42:45 -0400 Received: from relay2-d.mail.gandi.net (relay2-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::222]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5770D89F0B; Wed, 15 Mar 2023 06:42:44 -0700 (PDT) Received: (Authenticated sender: herve.codina@bootlin.com) by mail.gandi.net (Postfix) with ESMTPA id 7CE0240016; Wed, 15 Mar 2023 13:42:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1678887762; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ErIeGZOdBC0SggTn7/aNvCYajOT8ftQ+YUi6Mg1r8hk=; b=Z5VllREub8q03kyXMToln2CZgjEQsHhknoySCVz3SVeEJlubW9XbLJgNKsShbjLXTygxUz gLMo5OgIh8LdLY5f/ybH7ELQ+tJRPU+JEmegMOpgqKYy+PnrR5Yk46HZ531k0BUug+QsaN B68pZdiG/sh0KyYxn3bobQe6yvFFaQqoPBj+Q9uzDCiPbpDqveXrwv1iLLwkXeDU7Ofxuq BMsO0KQVgzyYOGbnwwUnmta60ycSNFLAPp1qqFd2/kR0EvFc4cC1oEht8U0O46azIAsgbn y8ty+tCryuEVuhSZMnXAnraiE1YVKnfimGW3/lvWfBBotXFCB4mBl58npwoPrw== From: Herve Codina To: Herve Codina , Rob Herring , Krzysztof Kozlowski , Liam Girdwood , Mark Brown , Derek Kiernan , Dragan Cvetic , Arnd Bergmann , Greg Kroah-Hartman , Jaroslav Kysela , Takashi Iwai Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, alsa-devel@alsa-project.org, Christophe Leroy , Thomas Petazzoni Subject: [PATCH 3/7] Documentation: sysfs: Document the Lantiq PEF2256 sysfs entry Date: Wed, 15 Mar 2023 14:42:27 +0100 Message-Id: <20230315134231.233193-4-herve.codina@bootlin.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230315134231.233193-1-herve.codina@bootlin.com> References: <20230315134231.233193-1-herve.codina@bootlin.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1760442182192223646?= X-GMAIL-MSGID: =?utf-8?q?1760442182192223646?= Document the "subordinate" sysfs attribute exposed by the pef2256 driver. Signed-off-by: Herve Codina --- .../ABI/testing/sysfs-bus-platform-devices-pef2256 | 10 ++++++++++ 1 file changed, 10 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-bus-platform-devices-pef2256 diff --git a/Documentation/ABI/testing/sysfs-bus-platform-devices-pef2256 b/Documentation/ABI/testing/sysfs-bus-platform-devices-pef2256 new file mode 100644 index 000000000000..b2343b3b6e84 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-bus-platform-devices-pef2256 @@ -0,0 +1,10 @@ +What: /sys/bus/platform/devices/*.pef2256/subordinate +KernelVersion: 6.4 +Contact: Herve Codina +Description: + (RW) Controls whether the PEF2256 works as subordinate or main + device mode. + - 0 : main device mode + - 1 : subordinate mode + In subordinate device mode it synchronizes on line interface + clock signals. Otherwise, it synchronizes on internal clocks. From patchwork Wed Mar 15 13:42:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Herve Codina X-Patchwork-Id: 70238 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp2347597wrd; Wed, 15 Mar 2023 07:03:21 -0700 (PDT) X-Google-Smtp-Source: AK7set8EGXJ90GkznO9QkkjciTuLW4jBsbfGVPH38J/WkJdvBtjmni697jYTiJAa5z73Gl3ei91o X-Received: by 2002:a05:6a20:5489:b0:cc:120c:b259 with SMTP id i9-20020a056a20548900b000cc120cb259mr52581810pzk.39.1678889000939; Wed, 15 Mar 2023 07:03:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1678889000; cv=none; d=google.com; s=arc-20160816; b=GkzIQlRUo+MkYnkS2oZWviMrFchCAUe28+lh+uPFyLwD005oaT8FKYmrn1RnnGQiVe IgkGrL/Gvz0MB/ddNgYu9UPP1iTzWtTMMHU6imsHSqi8eaOqkuF28KG0bqxw7oecdKQP rqOkk+sSa8b2vyD/DL+j7fL7aO11sPq57cfy7mcPmYbI8j1K9YsvDu/P6EM5f6BANo6D uJ1nNxlhA0Aba+ytF6RiZ6CS0GHpJeiJS7eRtYDuVyIrjtEQIDBBjBBxqyE0TcBgiI0i uT096zDLvRjpMu40/yerq0YPcuTpQONpKorE0Jrdd2dK5KRpVlM4S+Olve7lJQtyXORZ 0F+w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=0YBlfkWN4uRgoK2zQn1smyULeh9+sx/f01ppPsRKAF4=; b=jDOJd7rdv91UuERQDuf4gDf9yB/g5p0IlYj/JIHSYqZ8coUyEljGG8EuKJzFtrcOz1 U8cISl3boHLib1Dg1gwktKEpTHwIetZ19ry+BdB4TwOasKuUZ7aHv3B+kcoqtLujitgF vTACb1DAtRSweNvn8pKzispf/MNwsLooO85Mo9BFGQZZ3IIeOL5PHFQ81IcAlWQzIj8P XrQjDwtPvlJlXsFEULU7WWFmELGmeSDY4hpcfE4fo6wyrQVzrHLY+ooXP751GWMh8xHU mwffWDJmceQBs8//G1wQlL/6E0HtNXnpdqL8KCoL/0Z11AXFyaCrXxplaw5MpaMgvNKh wm6w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@bootlin.com header.s=gm1 header.b=OtOHDu0i; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=bootlin.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id w27-20020a63475b000000b0047711269d75si4885221pgk.516.2023.03.15.07.03.07; Wed, 15 Mar 2023 07:03:20 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@bootlin.com header.s=gm1 header.b=OtOHDu0i; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=bootlin.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230176AbjCONnI (ORCPT + 99 others); Wed, 15 Mar 2023 09:43:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57020 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232138AbjCONms (ORCPT ); Wed, 15 Mar 2023 09:42:48 -0400 Received: from relay2-d.mail.gandi.net (relay2-d.mail.gandi.net [217.70.183.194]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8E95B8C97A; Wed, 15 Mar 2023 06:42:45 -0700 (PDT) Received: (Authenticated sender: herve.codina@bootlin.com) by mail.gandi.net (Postfix) with ESMTPA id 1163E40007; Wed, 15 Mar 2023 13:42:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1678887764; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=0YBlfkWN4uRgoK2zQn1smyULeh9+sx/f01ppPsRKAF4=; b=OtOHDu0irUG+ua7dX+nyKl7VYZNAhl/6cIYtsR7P0j7zjxfblyTd6dvHd83R0oswHcPZL9 ZkQI1zwNPDtlgLeU+Z/SJqrDW3TWVgZ+T57vA2Hhd1BiOeCinaEdPBjRCkG2Ht14HSDKef Zl2YIrwFOcinxuWZN/sT728U3057ahrjTCCCRkG7h/pMcvVMjEIesdcr39Tk478FbgZ/o7 YFw2eHNFN9E67hS4+ruMA0t9K7GhkwCL22KgeyHR6VSXed9JnovG6+Fy0FgomxhOd+Lox1 JOt23rHieiZYSshG3vnE3PvOXL4eXZxYfC6+7t2qxQkLkFt1joPfIvt8fsHL8A== From: Herve Codina To: Herve Codina , Rob Herring , Krzysztof Kozlowski , Liam Girdwood , Mark Brown , Derek Kiernan , Dragan Cvetic , Arnd Bergmann , Greg Kroah-Hartman , Jaroslav Kysela , Takashi Iwai Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, alsa-devel@alsa-project.org, Christophe Leroy , Thomas Petazzoni Subject: [PATCH 4/7] MAINTAINERS: Add the Lantiq PEF2256 driver entry Date: Wed, 15 Mar 2023 14:42:28 +0100 Message-Id: <20230315134231.233193-5-herve.codina@bootlin.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230315134231.233193-1-herve.codina@bootlin.com> References: <20230315134231.233193-1-herve.codina@bootlin.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1760442712878389740?= X-GMAIL-MSGID: =?utf-8?q?1760442712878389740?= After contributing the driver, add myself as the maintainer for the Lantiq PEF2256 driver. Signed-off-by: Herve Codina --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index fcb69242cd19..b258498aa8ac 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11651,6 +11651,14 @@ S: Maintained F: arch/mips/lantiq F: drivers/soc/lantiq +LANTIQ PEF2256 DRIVER +M: Herve Codina +S: Maintained +F: Documentation/ABI/testing/sysfs-bus-platform-devices-pef2256 +F: Documentation/devicetree/bindings/misc/lantiq,pef2256.yaml +F: drivers/misc/pef2256.c +F: include/linux/pef2256.h + LASI 53c700 driver for PARISC M: "James E.J. Bottomley" L: linux-scsi@vger.kernel.org From patchwork Wed Mar 15 13:42:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Herve Codina X-Patchwork-Id: 70237 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp2347160wrd; Wed, 15 Mar 2023 07:02:51 -0700 (PDT) X-Google-Smtp-Source: AK7set+k8M6yCilN+8tlsOjj+5eAhp6J/e73/Aspkvu/+/XDwCegd7A3YtUXwIHZXoP0selIvmf4 X-Received: by 2002:a05:6a21:338b:b0:cc:606a:4349 with SMTP id yy11-20020a056a21338b00b000cc606a4349mr11221pzb.8.1678888970853; Wed, 15 Mar 2023 07:02:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1678888970; cv=none; d=google.com; s=arc-20160816; b=afXoMOYFDL+6iNsTvz1ujb8uxoF8+mAwCVMe7xP+g4vopPu2ROv6RQd4kb8gwjDPc8 gZA26ejUKUQPDWaUK+e6N3gLI7msyj7TuC1RuEx+DbeFrfd6PFE/EpCH4QQFSFrixbhH YLvFHjYFXtecDhBAnqVM9QK6k9fmJAWLov7j7dY0fh6rALnPGOFo3R+q/8Ldpl9AbyG0 qsduOAcStKkrnw/MMpBLM+ID40QtpDZh6cuWC7iqb3ePt+UtRNEdsywqGSwYzsMbaTMT DUX2sn4cm7FGLk7szQp0BOzSAsDvbAkCVQ4jPdWoP8Q7VFuoI3acILBQpgakCRgs0I9G aXDA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=nSK6QmzgFgboixiIAQGzqWb/rCb1DitwrXgQXi+UVkQ=; b=RzqbeJERFP/3l7IFT0uNn5jEQinJE+9pCGBvXkvGudTUb2UdDXBIazuv5opfFOTbWT ctOsiGm/MWXnVFaHhYPtDeNIyuiWf7yoS0oXxDTFHLurWs6dpPHHI1uwtPHivMPSTt/N Ovt5vH1GGCpxp1sT4J72EsA3bdOhbq2bX2VIssxwYinQ6DZfyY0SjwMjpKN82dilcYBW N9wAM5e7eXj673eWwT2VMx7FAN9utKW9ghLZ6fH+3KAElGP1o0GOh32CoZ8QVnkj2Tox 4D/p9oOMraxGevyoo5ggNSbriIGnd0BX5wBsYONB68OZEUuuE3All82EySoU1wPpSIpc nz8w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@bootlin.com header.s=gm1 header.b=BRLGgg+d; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=bootlin.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id w27-20020a63475b000000b0047711269d75si4885221pgk.516.2023.03.15.07.02.36; Wed, 15 Mar 2023 07:02:50 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@bootlin.com header.s=gm1 header.b=BRLGgg+d; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=bootlin.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232504AbjCONnS (ORCPT + 99 others); Wed, 15 Mar 2023 09:43:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57048 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231848AbjCONms (ORCPT ); Wed, 15 Mar 2023 09:42:48 -0400 Received: from relay2-d.mail.gandi.net (relay2-d.mail.gandi.net [217.70.183.194]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 169698EA3B; Wed, 15 Mar 2023 06:42:46 -0700 (PDT) Received: (Authenticated sender: herve.codina@bootlin.com) by mail.gandi.net (Postfix) with ESMTPA id 774C640004; Wed, 15 Mar 2023 13:42:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1678887765; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=nSK6QmzgFgboixiIAQGzqWb/rCb1DitwrXgQXi+UVkQ=; b=BRLGgg+d1mebPDYbuEfKpLaT3Gaa7+FVrT/MFfJaKNsKHljpx9AktNDEsYo4Wat28bPvu7 upAw0DINnnx7y31brXY2IqqWJ7AqtEVStzfa7JpU4RxUrp/D8hIxjNZl5CEmn0pfXUQBwv KZKZriRkwtu0E3JsH5rGIN1l8JFV22Lv7ziO5kXwz77dIESwF+JrnMgmx277EUMZtbRBUI +FD+CtMrZUBUbiwbwPA64yNxPWFhJVS2C4zIAWa4KdpAcZ5zarFUe+gbqvWMZHtJVpPuZz oZea7nyYkNu4Zw7TFlydTbk11+UlWqIZ6EAORyoDWnhwnD4AikYJ7BY2JfpcCA== From: Herve Codina To: Herve Codina , Rob Herring , Krzysztof Kozlowski , Liam Girdwood , Mark Brown , Derek Kiernan , Dragan Cvetic , Arnd Bergmann , Greg Kroah-Hartman , Jaroslav Kysela , Takashi Iwai Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, alsa-devel@alsa-project.org, Christophe Leroy , Thomas Petazzoni Subject: [PATCH 5/7] dt-bindings: sound: Add support for the Lantiq PEF2256 codec Date: Wed, 15 Mar 2023 14:42:29 +0100 Message-Id: <20230315134231.233193-6-herve.codina@bootlin.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230315134231.233193-1-herve.codina@bootlin.com> References: <20230315134231.233193-1-herve.codina@bootlin.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1760442681641884333?= X-GMAIL-MSGID: =?utf-8?q?1760442681641884333?= The Lantiq PEF2256, also known as Infineon PEF2256 or FALC256, is a framer and line interface component designed to fulfill all required interfacing between an analog E1/T1/J1 line and the digital PCM system highway/H.100 bus. The codec support allows to use some of the PCM system highway time-slots as audio channels to transport audio data over the E1/T1/J1 lines. Signed-off-by: Herve Codina --- .../bindings/sound/lantiq,pef2256-codec.yaml | 57 +++++++++++++++++++ 1 file changed, 57 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/lantiq,pef2256-codec.yaml diff --git a/Documentation/devicetree/bindings/sound/lantiq,pef2256-codec.yaml b/Documentation/devicetree/bindings/sound/lantiq,pef2256-codec.yaml new file mode 100644 index 000000000000..acba3a0ccd1b --- /dev/null +++ b/Documentation/devicetree/bindings/sound/lantiq,pef2256-codec.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/lantiq,pef2256-codec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Lantiq PEF2256 codec device + +maintainers: + - Herve Codina + +description: | + Codec support for PEF2256. + + The Lantiq PEF2256, also known as Infineon PEF2256 or FALC256, is a framer and + line interface component designed to fulfill all required interfacing between + an analog E1/T1/J1 line and the digital PCM system highway/H.100 bus. + + The codec support allows to use some of the PCM system highway time-slots as + audio channels to transport audio data over the E1/T1/J1 lines. + + The time-slots used by the codec must be set and so, the properties + 'dai-tdm-slot-num', 'dai-tdm-slot-width', 'dai-tdm-slot-tx-mask' and + 'dai-tdm-slot-rx-mask' must be present in the ALSA sound card node for + sub-nodes that involve the codec. The codec uses 8bit time-slots. + 'dai-tdm-tdm-slot-with' must be set to 8. + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + - $ref: dai-common.yaml# + +properties: + compatible: + const: lantiq,pef2256-codec + + lantiq,pef2256: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle to the PEF2256 + + '#sound-dai-cells': + const: 0 + +required: + - compatible + - lantiq,pef2256 + - '#sound-dai-cells' + +unevaluatedProperties: false + +examples: + - | + audio-codec { + compatible = "lantiq,pef2256-codec"; + lantiq,pef2256 = <&pef2256>; + #sound-dai-cells = <0>; + }; From patchwork Wed Mar 15 13:42:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Herve Codina X-Patchwork-Id: 70231 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp2341781wrd; Wed, 15 Mar 2023 06:53:03 -0700 (PDT) X-Google-Smtp-Source: AK7set8M02gR8g5lnQPizboZqKn0/0f+KUBrvMHbvG/uzEASvSYtB4g/VdUfcj6n//FXxlP3oqHL X-Received: by 2002:a05:6a20:3d82:b0:cd:1808:87c7 with SMTP id s2-20020a056a203d8200b000cd180887c7mr47938510pzi.15.1678888382766; Wed, 15 Mar 2023 06:53:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1678888382; cv=none; d=google.com; s=arc-20160816; b=epCPOQ+XAkH0Sz9ZFPnCicA8Nmym28H2PPKNwQqEcDP6Si1fjYT7Lq3g5Nz/uNdnp3 AyclWypc4bbWUF/y/OAPZcFwPtPCLURr7iKktUOcjFSB3chPYxikOJZ4HaENvczt1m8v kCLY35KqUUYue578+L3xIrt8vrd+qxUhOkS2Tfbe4G8dEQDmrgRdTDzy39cKD7rg2NA9 yYiP6KmWj3G8iyqyTuBuL7HYeJm+VEcF/hFHrBl2cSQ5X0EJIoXfSs8Yq4NsNZJcsd5m h1PvtNZreriDvsN8xb8zDaztS9GfArNXjE8fOUvBmaFtin9uEwprx+8bsSDdgy0Hcw2f 6xNQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=jFTga6H8v4jCHKSa95S6ahlZ49X3KutAxMtq/OnPXY0=; b=cSaQpaPUCr0drfDZCc7I3kjtoJONuT6feoHHUv1wfxzXsuoGZS0g2LGuBppIteKbeR rwfnXJ4UDOfLgu6aOhT+Xm4Q2djL9pzGRIgBjkSrtnOt6zoNZB3t/YvihlTppNtgsxBf l6xTA88pBlOzW6awNcnKnRAJnOTUNmJVrI/g21g5i/Ois/Srw6jQ2Bou9h09FGYwJFEC pAYZN7ssURKFHA5WxrP6pmya7uWiD0u5TnlnujyiNYlWOJfky3zP1sJ5JTD8ySIBmlza git9saJ6xah4Kv+VRLwETUaeaneKNalkhrIZfH80jC7B03+PROcMW9rs+AMv9dHYjEQK t2Rg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@bootlin.com header.s=gm1 header.b=hCeuHm42; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=bootlin.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id k2-20020a635a42000000b00502e7159b0fsi4970094pgm.175.2023.03.15.06.52.44; Wed, 15 Mar 2023 06:53:02 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@bootlin.com header.s=gm1 header.b=hCeuHm42; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=bootlin.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232558AbjCONnW (ORCPT + 99 others); Wed, 15 Mar 2023 09:43:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57084 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231724AbjCONmv (ORCPT ); Wed, 15 Mar 2023 09:42:51 -0400 Received: from relay2-d.mail.gandi.net (relay2-d.mail.gandi.net [217.70.183.194]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6FEB0898EE; Wed, 15 Mar 2023 06:42:48 -0700 (PDT) Received: (Authenticated sender: herve.codina@bootlin.com) by mail.gandi.net (Postfix) with ESMTPA id E97FD40012; Wed, 15 Mar 2023 13:42:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1678887767; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=jFTga6H8v4jCHKSa95S6ahlZ49X3KutAxMtq/OnPXY0=; b=hCeuHm42tDKoqCuoTj22g8Z+vhzTo9opWMlXNLN1h6mdKlliFkLqIqCo37glsJ09ObS/Hc UYTfBRbCoiAVKTxlWOQ4VoOGwAzLPtj7YsOi2lpXwXgzlGZtw3/vpZ1neEDJzoFj6YFXPk wgIqEOI2xr1r36M3CLdcuuy6gd8SCRPxrcOgwh9p99yixV+2kRFmWYN5v2mllYMSEIZGVv VyNbZs6mfGkg7IAOrlIxIxPXEtUi2JCRr+t594lo3+axar8+rtwwoH76b5OJDjLEDrlSLy H6AXxg6nMTxrC7fKMVYQQXmYJ698MaLLuZT8DOnv2IQCUqzho1aUuRVANSJ/mw== From: Herve Codina To: Herve Codina , Rob Herring , Krzysztof Kozlowski , Liam Girdwood , Mark Brown , Derek Kiernan , Dragan Cvetic , Arnd Bergmann , Greg Kroah-Hartman , Jaroslav Kysela , Takashi Iwai Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, alsa-devel@alsa-project.org, Christophe Leroy , Thomas Petazzoni Subject: [PATCH 6/7] ASoC: codecs: Add support for the Lantiq PEF2256 codec Date: Wed, 15 Mar 2023 14:42:30 +0100 Message-Id: <20230315134231.233193-7-herve.codina@bootlin.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230315134231.233193-1-herve.codina@bootlin.com> References: <20230315134231.233193-1-herve.codina@bootlin.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1760442064747431225?= X-GMAIL-MSGID: =?utf-8?q?1760442064747431225?= The Lantiq PEF2256, also known as Infineon PEF2256 or FALC256, is a framer and line interface component designed to fulfill all required interfacing between an analog E1/T1/J1 line and the digital PCM system highway/H.100 bus. The codec support allows to use some of the PCM system highway time-slots as audio channels to transport audio data over the E1/T1/J1 lines. It provides also line carrier detection events reported through the ALSA jack detection feature. Signed-off-by: Herve Codina --- sound/soc/codecs/Kconfig | 14 ++ sound/soc/codecs/Makefile | 2 + sound/soc/codecs/pef2256-codec.c | 395 +++++++++++++++++++++++++++++++ 3 files changed, 411 insertions(+) create mode 100644 sound/soc/codecs/pef2256-codec.c diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index 0be061953e9a..bec4f9200072 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -168,6 +168,7 @@ config SND_SOC_ALL_CODECS imply SND_SOC_PCM512x_I2C imply SND_SOC_PCM512x_SPI imply SND_SOC_PEB2466 + imply SND_SOC_PEF2256 imply SND_SOC_RK3328 imply SND_SOC_RK817 imply SND_SOC_RT274 @@ -1252,6 +1253,19 @@ config SND_SOC_PEB2466 To compile this driver as a module, choose M here: the module will be called snd-soc-peb2466. +config SND_SOC_PEF2256 + tristate "Lantiq PEF2256 codec" + depends on PEF2256 + help + Enable support for the Lantiq PEF2256 (FALC56) codec. + The PEF2256 is a framer and line interface between analog E1/T1/J1 + line and a digital PCM bus. + This codec allows to use some of the time slots available on the + PEF2256 PCM bus to transport some audio data. + + To compile this driver as a module, choose M here: the module + will be called snd-soc-pef2256. + config SND_SOC_RK3328 tristate "Rockchip RK3328 audio CODEC" select REGMAP_MMIO diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile index 20b388b77f1f..11bd66d46f7b 100644 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile @@ -188,6 +188,7 @@ snd-soc-pcm512x-objs := pcm512x.o snd-soc-pcm512x-i2c-objs := pcm512x-i2c.o snd-soc-pcm512x-spi-objs := pcm512x-spi.o snd-soc-peb2466-objs := peb2466.o +snd-soc-pef2256-objs := pef2256-codec.o snd-soc-rk3328-objs := rk3328_codec.o snd-soc-rk817-objs := rk817_codec.o snd-soc-rl6231-objs := rl6231.o @@ -551,6 +552,7 @@ obj-$(CONFIG_SND_SOC_PCM512x) += snd-soc-pcm512x.o obj-$(CONFIG_SND_SOC_PCM512x_I2C) += snd-soc-pcm512x-i2c.o obj-$(CONFIG_SND_SOC_PCM512x_SPI) += snd-soc-pcm512x-spi.o obj-$(CONFIG_SND_SOC_PEB2466) += snd-soc-peb2466.o +obj-$(CONFIG_SND_SOC_PEF2256) += snd-soc-pef2256.o obj-$(CONFIG_SND_SOC_RK3328) += snd-soc-rk3328.o obj-$(CONFIG_SND_SOC_RK817) += snd-soc-rk817.o obj-$(CONFIG_SND_SOC_RL6231) += snd-soc-rl6231.o diff --git a/sound/soc/codecs/pef2256-codec.c b/sound/soc/codecs/pef2256-codec.c new file mode 100644 index 000000000000..08ed54c7bd56 --- /dev/null +++ b/sound/soc/codecs/pef2256-codec.c @@ -0,0 +1,395 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// pef2256.c -- Lantiq PEF2256 ALSA SoC driver +// +// Copyright 2023 CS GROUP France +// +// Author: Herve Codina + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PEF2256_NB_CHANNEL 32 +#define PEF2256_JACK_MASK (SND_JACK_LINEIN | SND_JACK_LINEOUT) + +struct pef2256_codec { + struct pef2256 *pef2256; + struct device *dev; + struct snd_soc_jack jack; + struct notifier_block nb; + struct work_struct carrier_work; + int max_chan_playback; + int max_chan_capture; +}; + +static int pef2256_dai_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, + unsigned int rx_mask, int slots, int width) +{ + struct pef2256_codec *pef2256 = snd_soc_component_get_drvdata(dai->component); + + switch (width) { + case 0: + /* Not set -> default 8 */ + case 8: + break; + default: + dev_err(dai->dev, "tdm slot width %d not supported\n", width); + return -EINVAL; + } + + pef2256->max_chan_playback = hweight32(tx_mask); + if (pef2256->max_chan_playback > PEF2256_NB_CHANNEL) { + dev_err(dai->dev, "too much tx slots defined (mask = 0x%x) support max %d\n", + tx_mask, PEF2256_NB_CHANNEL); + return -EINVAL; + } + + pef2256->max_chan_capture = hweight32(rx_mask); + if (pef2256->max_chan_capture > PEF2256_NB_CHANNEL) { + dev_err(dai->dev, "too much rx slots defined (mask = 0x%x) support max %d\n", + rx_mask, PEF2256_NB_CHANNEL); + return -EINVAL; + } + + return 0; +} + +/* + * The constraints for format/channel is to match with the number of 8bit + * time-slots available. + */ +static int pef2256_dai_hw_rule_channels_by_format(struct snd_soc_dai *dai, + struct snd_pcm_hw_params *params, + unsigned int nb_ts) +{ + struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); + snd_pcm_format_t format = params_format(params); + struct snd_interval ch = {0}; + + switch (snd_pcm_format_physical_width(format)) { + case 8: + ch.max = nb_ts; + break; + case 16: + ch.max = nb_ts/2; + break; + case 32: + ch.max = nb_ts/4; + break; + case 64: + ch.max = nb_ts/8; + break; + default: + dev_err(dai->dev, "format physical width %u not supported\n", + snd_pcm_format_physical_width(format)); + return -EINVAL; + } + + ch.min = ch.max ? 1 : 0; + + return snd_interval_refine(c, &ch); +} + +static int pef2256_dai_hw_rule_playback_channels_by_format(struct snd_pcm_hw_params *params, + struct snd_pcm_hw_rule *rule) +{ + struct snd_soc_dai *dai = rule->private; + struct pef2256_codec *pef2256 = snd_soc_component_get_drvdata(dai->component); + + return pef2256_dai_hw_rule_channels_by_format(dai, params, pef2256->max_chan_playback); +} + +static int pef2256_dai_hw_rule_capture_channels_by_format(struct snd_pcm_hw_params *params, + struct snd_pcm_hw_rule *rule) +{ + struct snd_soc_dai *dai = rule->private; + struct pef2256_codec *pef2256 = snd_soc_component_get_drvdata(dai->component); + + return pef2256_dai_hw_rule_channels_by_format(dai, params, pef2256->max_chan_capture); +} + +static int pef2256_dai_hw_rule_format_by_channels(struct snd_soc_dai *dai, + struct snd_pcm_hw_params *params, + unsigned int nb_ts) +{ + struct snd_mask *f_old = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT); + unsigned int channels = params_channels(params); + unsigned int slot_width; + struct snd_mask f_new; + unsigned int i; + + if (!channels || channels > nb_ts) { + dev_err(dai->dev, "channels %u not supported\n", nb_ts); + return -EINVAL; + } + + slot_width = (nb_ts / channels) * 8; + + snd_mask_none(&f_new); + for (i = 0; i <= SNDRV_PCM_FORMAT_LAST; i++) { + if (snd_mask_test(f_old, i)) { + if (snd_pcm_format_physical_width(i) <= slot_width) + snd_mask_set(&f_new, i); + } + } + + return snd_mask_refine(f_old, &f_new); +} + +static int pef2256_dai_hw_rule_playback_format_by_channels(struct snd_pcm_hw_params *params, + struct snd_pcm_hw_rule *rule) +{ + struct snd_soc_dai *dai = rule->private; + struct pef2256_codec *pef2256 = snd_soc_component_get_drvdata(dai->component); + + return pef2256_dai_hw_rule_format_by_channels(dai, params, pef2256->max_chan_playback); +} + +static int pef2256_dai_hw_rule_capture_format_by_channels(struct snd_pcm_hw_params *params, + struct snd_pcm_hw_rule *rule) +{ + struct snd_soc_dai *dai = rule->private; + struct pef2256_codec *pef2256 = snd_soc_component_get_drvdata(dai->component); + + return pef2256_dai_hw_rule_format_by_channels(dai, params, pef2256->max_chan_capture); +} + +static u64 pef2256_formats(u8 nb_ts) +{ + u64 formats; + unsigned int chan_width; + unsigned int format_width; + int i; + + if (!nb_ts) + return 0; + + formats = 0; + chan_width = nb_ts * 8; + for (i = 0; i <= SNDRV_PCM_FORMAT_LAST; i++) { + /* Support physical width multiple of 8bit */ + format_width = snd_pcm_format_physical_width(i); + if (format_width == 0 || format_width % 8) + continue; + + /* + * And support physical width that can fit N times in the + * channel + */ + if (format_width > chan_width || chan_width % format_width) + continue; + + formats |= (1ULL << i); + } + return formats; +} + +static int pef2256_dai_startup(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct pef2256_codec *pef2256 = snd_soc_component_get_drvdata(dai->component); + snd_pcm_hw_rule_func_t hw_rule_channels_by_format; + snd_pcm_hw_rule_func_t hw_rule_format_by_channels; + unsigned int frame_bits; + u64 format; + int ret; + + if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { + format = pef2256_formats(pef2256->max_chan_capture); + hw_rule_channels_by_format = pef2256_dai_hw_rule_capture_channels_by_format; + hw_rule_format_by_channels = pef2256_dai_hw_rule_capture_format_by_channels; + frame_bits = pef2256->max_chan_capture * 8; + } else { + format = pef2256_formats(pef2256->max_chan_playback); + hw_rule_channels_by_format = pef2256_dai_hw_rule_playback_channels_by_format; + hw_rule_format_by_channels = pef2256_dai_hw_rule_playback_format_by_channels; + frame_bits = pef2256->max_chan_playback * 8; + } + + ret = snd_pcm_hw_constraint_mask64(substream->runtime, + SNDRV_PCM_HW_PARAM_FORMAT, format); + if (ret) { + dev_err(dai->dev, "Failed to add format constraint (%d)\n", ret); + return ret; + } + + ret = snd_pcm_hw_rule_add(substream->runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, + hw_rule_channels_by_format, dai, + SNDRV_PCM_HW_PARAM_FORMAT, -1); + if (ret) { + dev_err(dai->dev, "Failed to add channels rule (%d)\n", ret); + return ret; + } + + ret = snd_pcm_hw_rule_add(substream->runtime, 0, SNDRV_PCM_HW_PARAM_FORMAT, + hw_rule_format_by_channels, dai, + SNDRV_PCM_HW_PARAM_CHANNELS, -1); + if (ret) { + dev_err(dai->dev, "Failed to add format rule (%d)\n", ret); + return ret; + } + + ret = snd_pcm_hw_constraint_single(substream->runtime, + SNDRV_PCM_HW_PARAM_FRAME_BITS, + frame_bits); + if (ret < 0) { + dev_err(dai->dev, "Failed to add frame_bits constraint (%d)\n", ret); + return ret; + } + + return 0; +} + +static u64 pef2256_dai_formats[] = { + SND_SOC_POSSIBLE_DAIFMT_DSP_B, +}; + +static const struct snd_soc_dai_ops pef2256_dai_ops = { + .startup = pef2256_dai_startup, + .set_tdm_slot = pef2256_dai_set_tdm_slot, + .auto_selectable_formats = pef2256_dai_formats, + .num_auto_selectable_formats = ARRAY_SIZE(pef2256_dai_formats), +}; + +static struct snd_soc_dai_driver pef2256_dai_driver = { + .name = "pef2256", + .playback = { + .stream_name = "Playback", + .channels_min = 1, + .channels_max = PEF2256_NB_CHANNEL, + .rates = SNDRV_PCM_RATE_8000, + .formats = U64_MAX, /* Will be refined on DAI .startup() */ + }, + .capture = { + .stream_name = "Capture", + .channels_min = 1, + .channels_max = PEF2256_NB_CHANNEL, + .rates = SNDRV_PCM_RATE_8000, + .formats = U64_MAX, /* Will be refined on DAI .startup() */ + }, + .ops = &pef2256_dai_ops, +}; + +static void pef2256_carrier_work(struct work_struct *work) +{ + struct pef2256_codec *pef2256 = container_of(work, struct pef2256_codec, carrier_work); + int status; + + status = pef2256_get_carrier(pef2256->pef2256) ? PEF2256_JACK_MASK : 0; + snd_soc_jack_report(&pef2256->jack, status, PEF2256_JACK_MASK); +} + +static int pef2256_carrier_notifier(struct notifier_block *nb, unsigned long action, + void *data) +{ + struct pef2256_codec *pef2256 = container_of(nb, struct pef2256_codec, nb); + + switch (action) { + case PEF2256_EVENT_CARRIER: + queue_work(system_power_efficient_wq, &pef2256->carrier_work); + break; + default: + return NOTIFY_DONE; + } + + return NOTIFY_OK; +} + +static int pef2256_component_probe(struct snd_soc_component *component) +{ + struct pef2256_codec *pef2256 = snd_soc_component_get_drvdata(component); + char *name; + int ret; + + INIT_WORK(&pef2256->carrier_work, pef2256_carrier_work); + + name = "carrier"; + if (component->name_prefix) { + name = kasprintf(GFP_KERNEL, "%s carrier", component->name_prefix); + if (!name) + return -ENOMEM; + } + + ret = snd_soc_card_jack_new(component->card, name, PEF2256_JACK_MASK, &pef2256->jack); + if (component->name_prefix) + kfree(name); /* A copy is done by snd_soc_card_jack_new */ + if (ret) { + dev_err(component->dev, "Cannot create jack\n"); + return ret; + } + + pef2256->nb.notifier_call = pef2256_carrier_notifier; + ret = pef2256_register_event_notifier(pef2256->pef2256, &pef2256->nb); + if (ret) { + dev_err(component->dev, "Cannot register event notifier\n"); + return ret; + } + + /* Queue work to set the initial value */ + queue_work(system_power_efficient_wq, &pef2256->carrier_work); + + return 0; +} + +static void pef2256_component_remove(struct snd_soc_component *component) +{ + struct pef2256_codec *pef2256 = snd_soc_component_get_drvdata(component); + + pef2256_unregister_event_notifier(pef2256->pef2256, &pef2256->nb); + cancel_work_sync(&pef2256->carrier_work); +} + +static const struct snd_soc_component_driver pef2256_component_driver = { + .probe = pef2256_component_probe, + .remove = pef2256_component_remove, + .endianness = 1, +}; + +static int pef2256_codec_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + struct pef2256_codec *pef2256; + + pef2256 = devm_kzalloc(&pdev->dev, sizeof(*pef2256), GFP_KERNEL); + if (!pef2256) + return -ENOMEM; + + pef2256->dev = &pdev->dev; + + pef2256->pef2256 = devm_pef2256_get_byphandle(&pdev->dev, np, "lantiq,pef2256"); + if (IS_ERR(pef2256->pef2256)) + return dev_err_probe(&pdev->dev, PTR_ERR(pef2256->pef2256), + "get pef2256 failed\n"); + + platform_set_drvdata(pdev, pef2256); + + return devm_snd_soc_register_component(&pdev->dev, &pef2256_component_driver, + &pef2256_dai_driver, 1); +} + +static const struct of_device_id pef2256_codec_of_match[] = { + { .compatible = "lantiq,pef2256-codec" }, + {} /* sentinel */ +}; +MODULE_DEVICE_TABLE(of, pef2256_codec_of_match); + +static struct platform_driver pef2256_codec_driver = { + .driver = { + .name = "lantiq-pef2256-codec", + .of_match_table = of_match_ptr(pef2256_codec_of_match), + }, + .probe = pef2256_codec_probe, +}; +module_platform_driver(pef2256_codec_driver); + +MODULE_AUTHOR("Herve Codina "); +MODULE_DESCRIPTION("PEF2256 ALSA SoC driver"); +MODULE_LICENSE("GPL"); From patchwork Wed Mar 15 13:42:31 2023 Content-Type: text/plain; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id t3-20020a170902bc4300b0019e4bf48149si5326079plz.400.2023.03.15.06.52.56; Wed, 15 Mar 2023 06:53:14 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@bootlin.com header.s=gm1 header.b="UCbgN/TT"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=bootlin.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231428AbjCONn1 (ORCPT + 99 others); Wed, 15 Mar 2023 09:43:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57088 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232377AbjCONmw (ORCPT ); Wed, 15 Mar 2023 09:42:52 -0400 Received: from relay2-d.mail.gandi.net (relay2-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::222]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 34CD18EA3B; Wed, 15 Mar 2023 06:42:50 -0700 (PDT) Received: (Authenticated sender: herve.codina@bootlin.com) by mail.gandi.net (Postfix) with ESMTPA id 57D2740009; Wed, 15 Mar 2023 13:42:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1678887768; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=DV4CC5O5iyRa+8OQdtxcgwDs8G2cCnQDmrmdt77V24E=; b=UCbgN/TTtdKV/9x8toXtsODqKW0O040mbJ9e/phujjg/Qc+3nYDRI99siod/Tu9ZcK8hZD iYBqUY7ePJgaGyROhbCesrw0CsU0DG9qZt3XyONF+/6KkCVI7hegBXoS4seKuiphZc8zqr VJi2j9xVRYyRYeM8sBX7GHyUFj7bdBoLBz65A/RvAx13Uzn9/Ahbu89I163QhpxxQ4YaN5 3CUm0DvwoFocoKE8yCgpIWbN+vnqHmW6JaM4VUEuZrGRhrN8VEbFVD6Zgy6Qlh2LZ44jkA vl937cZXH16OQLXz6RvyWU7dF3I8AQvBf5Fykoa0/Fjc8uTZxvxzuTCakr7R+Q== From: Herve Codina To: Herve Codina , Rob Herring , Krzysztof Kozlowski , Liam Girdwood , Mark Brown , Derek Kiernan , Dragan Cvetic , Arnd Bergmann , Greg Kroah-Hartman , Jaroslav Kysela , Takashi Iwai Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, alsa-devel@alsa-project.org, Christophe Leroy , Thomas Petazzoni Subject: [PATCH 7/7] MAINTAINERS: Add the Lantiq PEF2256 ASoC codec entry Date: Wed, 15 Mar 2023 14:42:31 +0100 Message-Id: <20230315134231.233193-8-herve.codina@bootlin.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230315134231.233193-1-herve.codina@bootlin.com> References: <20230315134231.233193-1-herve.codina@bootlin.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1760442077350369171?= X-GMAIL-MSGID: =?utf-8?q?1760442077350369171?= After contributing the codec, add myself as the maintainer for the Lantiq PEF2256 codec. Signed-off-by: Herve Codina --- MAINTAINERS | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index b258498aa8ac..81c17580b402 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11651,6 +11651,13 @@ S: Maintained F: arch/mips/lantiq F: drivers/soc/lantiq +LANTIQ PEF2256 ASoC CODEC +M: Herve Codina +L: alsa-devel@alsa-project.org (moderated for non-subscribers) +S: Maintained +F: Documentation/devicetree/bindings/sound/lantiq,pef2256-codec.yaml +F: sound/soc/codecs/pef2256-codec.c + LANTIQ PEF2256 DRIVER M: Herve Codina S: Maintained