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[2620:137:e000::1:20]) by mx.google.com with ESMTP id dz10-20020a0564021d4a00b00457f138ed4asi15851762edb.378.2022.10.19.06.12.54; Wed, 19 Oct 2022 06:13:23 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=A50WR6gp; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232182AbiJSNKr (ORCPT + 99 others); Wed, 19 Oct 2022 09:10:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60532 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233017AbiJSNJ4 (ORCPT ); Wed, 19 Oct 2022 09:09:56 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 883318E735; Wed, 19 Oct 2022 05:55:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1666184104; x=1697720104; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=eAJHzmzMTNBBml1IsEoRlVhesYoAxbHDrFN9XFoP2BA=; b=A50WR6gprjTtjMr4xhNM/NXBdah8jy4iC8qzQ7f6J+p6bgy7YGMJ/VCa hRntY9GLgKIjlE+hb4u9HjjiopoCfWEhzw4JzdoShDG6sE2bvNNZhsKiF cvLx9E22+W+6XuHVhnbGRRaaXWZ0tjGVu393CGpv00va6rNcip6qNi4ld NB/7rcXDEwvBNkPKayElXT9P+NUyNVlgXiAeZBzV/BnTpLsBz5YqammhN kQKrvVmf7Zb7nVvpDbVvx3xEQwz3IM2+sB/bOWSUPTpBnav4nPPj5sJoR Ir65Bx6o3q2p3mdi6PtdILb3z5ua3qfo5R5S5aOCalryFxBVour+0n0+V A==; X-IronPort-AV: E=Sophos;i="5.95,196,1661842800"; d="scan'208";a="185504900" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 19 Oct 2022 05:53:33 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Wed, 19 Oct 2022 05:53:20 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Wed, 19 Oct 2022 05:53:18 -0700 From: Conor Dooley To: CC: , , , , , , , , , , , Atish Patra Subject: [PATCH 5.10 1/2] arm64: topology: move store_cpu_topology() to shared code Date: Wed, 19 Oct 2022 13:53:02 +0100 Message-ID: <20221019125303.2845522-1-conor.dooley@microchip.com> X-Mailer: git-send-email 2.38.0 MIME-Version: 1.0 X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747121773114895455?= X-GMAIL-MSGID: =?utf-8?q?1747121815485989605?= commit 456797da792fa7cbf6698febf275fe9b36691f78 upstream. arm64's method of defining a default cpu topology requires only minimal changes to apply to RISC-V also. The current arm64 implementation exits early in a uniprocessor configuration by reading MPIDR & claiming that uniprocessor can rely on the default values. This is appears to be a hangover from prior to '3102bc0e6ac7 ("arm64: topology: Stop using MPIDR for topology information")', because the current code just assigns default values for multiprocessor systems. With the MPIDR references removed, store_cpu_topolgy() can be moved to the common arch_topology code. Reviewed-by: Sudeep Holla Acked-by: Catalin Marinas Reviewed-by: Atish Patra Signed-off-by: Conor Dooley --- arch/arm64/kernel/topology.c | 40 ------------------------------------ drivers/base/arch_topology.c | 19 +++++++++++++++++ 2 files changed, 19 insertions(+), 40 deletions(-) diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c index 4358bc319306..f35af19b7055 100644 --- a/arch/arm64/kernel/topology.c +++ b/arch/arm64/kernel/topology.c @@ -22,46 +22,6 @@ #include #include -void store_cpu_topology(unsigned int cpuid) -{ - struct cpu_topology *cpuid_topo = &cpu_topology[cpuid]; - u64 mpidr; - - if (cpuid_topo->package_id != -1) - goto topology_populated; - - mpidr = read_cpuid_mpidr(); - - /* Uniprocessor systems can rely on default topology values */ - if (mpidr & MPIDR_UP_BITMASK) - return; - - /* - * This would be the place to create cpu topology based on MPIDR. - * - * However, it cannot be trusted to depict the actual topology; some - * pieces of the architecture enforce an artificial cap on Aff0 values - * (e.g. GICv3's ICC_SGI1R_EL1 limits it to 15), leading to an - * artificial cycling of Aff1, Aff2 and Aff3 values. IOW, these end up - * having absolutely no relationship to the actual underlying system - * topology, and cannot be reasonably used as core / package ID. - * - * If the MT bit is set, Aff0 *could* be used to define a thread ID, but - * we still wouldn't be able to obtain a sane core ID. This means we - * need to entirely ignore MPIDR for any topology deduction. - */ - cpuid_topo->thread_id = -1; - cpuid_topo->core_id = cpuid; - cpuid_topo->package_id = cpu_to_node(cpuid); - - pr_debug("CPU%u: cluster %d core %d thread %d mpidr %#016llx\n", - cpuid, cpuid_topo->package_id, cpuid_topo->core_id, - cpuid_topo->thread_id, mpidr); - -topology_populated: - update_siblings_masks(cpuid); -} - #ifdef CONFIG_ACPI static bool __init acpi_cpu_is_threaded(int cpu) { diff --git a/drivers/base/arch_topology.c b/drivers/base/arch_topology.c index 8272a3a002a3..51647926e605 100644 --- a/drivers/base/arch_topology.c +++ b/drivers/base/arch_topology.c @@ -596,4 +596,23 @@ void __init init_cpu_topology(void) else if (of_have_populated_dt() && parse_dt_topology()) reset_cpu_topology(); } + +void store_cpu_topology(unsigned int cpuid) +{ + struct cpu_topology *cpuid_topo = &cpu_topology[cpuid]; + + if (cpuid_topo->package_id != -1) + goto topology_populated; + + cpuid_topo->thread_id = -1; + cpuid_topo->core_id = cpuid; + cpuid_topo->package_id = cpu_to_node(cpuid); + + pr_debug("CPU%u: package %d core %d thread %d\n", + cpuid, cpuid_topo->package_id, cpuid_topo->core_id, + cpuid_topo->thread_id); + +topology_populated: + update_siblings_masks(cpuid); +} #endif From patchwork Wed Oct 19 12:53:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 5430 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp319647wrs; Wed, 19 Oct 2022 06:13:24 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4gIqmcCoQVga77tdv2tVdqABGeuBsonKfH54E2pIlJkcMfif8jZK1EFWrUdqzQCO+mk+Cq X-Received: by 2002:a17:907:94cf:b0:78d:38cd:afcf with SMTP id dn15-20020a17090794cf00b0078d38cdafcfmr6748406ejc.229.1666185204194; Wed, 19 Oct 2022 06:13:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666185204; cv=none; d=google.com; s=arc-20160816; b=uHeyLaju1KaNZWHLBsE8SS4ILMK5frNiapt6zV9hSiC5DZW157BoQFdgdYA+/uYzcS l1plSaMVhZQIw3sE2/SbCW5U31L76zSANyvMSPiGRLNmuc/m0TanZmFgFDHSwNlcBniK yoceBqc3aZcWeaDB0cIwcoCb4IV6mf1e+c+us9AU8ylEFOOaK0vNBcklPzV6D86jGbJO q7/BCePmuHlKLAuuhl7Z6QOdF3py1PKYHPEAU9n0JEnmeHEVas3THVWjDFFW1mQCtyG7 aYDKUJSMFqO0nSiXlZtWIbkSH4YsMq/jRI44SJLbO03JNlKjp/wWKMavB/KUyaH0q3LN GCzA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=GDz04Ar5zo/nsxH/1Khg3VNb3DM+lonXF/onvVcmYoU=; b=FjfasHMzV1FkP5rxY/VE8jwmpHm5JUT62PirZIC/tBzNS5AR1goOcSan5rG0G2fVKM pUuum68FDbYW6Zkgm1nGHxnJL4PmEaSFtl2djCrr1xl0unMmhcE+D8/Wh39H6ifoWLw3 2To7kqdRAKyb097mKwRGLsb7uSM+9udyzcavCuU9qkk98tPwjOSDShD0hmtzY7sH2Khb hxNgFWsIo/s00x4al1LvcEa0oWJITW/QUw4s4xpZXhp2XsTURGO7kb8AIPvY5ecrzn4X yYzVDVIusAP2sYkUBOrft0GmJj/R+IqYWCRzzJ4QucVGSegbhMSk+hPYGktHlWpdWP/g cbfw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=kF9ta+x1; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id m14-20020a056402510e00b0045dc25bb7easi6204510edd.555.2022.10.19.06.12.56; Wed, 19 Oct 2022 06:13:24 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=kF9ta+x1; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231145AbiJSNKb (ORCPT + 99 others); Wed, 19 Oct 2022 09:10:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42834 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232728AbiJSNJm (ORCPT ); Wed, 19 Oct 2022 09:09:42 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 158483C151; Wed, 19 Oct 2022 05:54:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1666184087; x=1697720087; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=7nRf7HpxMobG7tiEk47jyd5TdB9jkpmn4TMYC/GrBxo=; b=kF9ta+x1WnAiEXygYvMRuXHrCN2NCqcEM1p41a4Y/5yH/u2nuxr+yBKd epoyTV27AlgqgRr31J3ebcHnXBW1Dl2wiqgNvQwZ77n6uIehc0REZluE7 6aIFitQe2v/08CjpmVTUGHDauTqwg2sBbCV0+9NwD2UvFerF0VCi3jLWu /a9joFziU4rlJ6taZE/tfIm7Ya6xIA5ul9vNuuyu1tp8svc3aoH9+QSED HteZp502xs4CW2pUF05mJb8Hxv9OIWZ/H1dqxqPZZhVlpo7guNXgzGzwQ L7VS+DUN2KyHal2LBzFFwZW04u3lSGY0/lrCmZxBK5c8XBkU3c4qyM2z/ w==; X-IronPort-AV: E=Sophos;i="5.95,196,1661842800"; d="scan'208";a="185504889" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 19 Oct 2022 05:53:31 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Wed, 19 Oct 2022 05:53:31 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Wed, 19 Oct 2022 05:53:29 -0700 From: Conor Dooley To: CC: , , , , , , , , , , , Atish Patra Subject: [PATCH 5.10 2/2] riscv: topology: fix default topology reporting Date: Wed, 19 Oct 2022 13:53:03 +0100 Message-ID: <20221019125303.2845522-2-conor.dooley@microchip.com> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221019125303.2845522-1-conor.dooley@microchip.com> References: <20221019125303.2845522-1-conor.dooley@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747121816313737343?= X-GMAIL-MSGID: =?utf-8?q?1747121816313737343?= commit fbd92809997a391f28075f1c8b5ee314c225557c upstream. RISC-V has no sane defaults to fall back on where there is no cpu-map in the devicetree. Without sane defaults, the package, core and thread IDs are all set to -1. This causes user-visible inaccuracies for tools like hwloc/lstopo which rely on the sysfs cpu topology files to detect a system's topology. On a PolarFire SoC, which should have 4 harts with a thread each, lstopo currently reports: Machine (793MB total) Package L#0 NUMANode L#0 (P#0 793MB) Core L#0 L1d L#0 (32KB) + L1i L#0 (32KB) + PU L#0 (P#0) L1d L#1 (32KB) + L1i L#1 (32KB) + PU L#1 (P#1) L1d L#2 (32KB) + L1i L#2 (32KB) + PU L#2 (P#2) L1d L#3 (32KB) + L1i L#3 (32KB) + PU L#3 (P#3) Adding calls to store_cpu_topology() in {boot,smp} hart bringup code results in the correct topolgy being reported: Machine (793MB total) Package L#0 NUMANode L#0 (P#0 793MB) L1d L#0 (32KB) + L1i L#0 (32KB) + Core L#0 + PU L#0 (P#0) L1d L#1 (32KB) + L1i L#1 (32KB) + Core L#1 + PU L#1 (P#1) L1d L#2 (32KB) + L1i L#2 (32KB) + Core L#2 + PU L#2 (P#2) L1d L#3 (32KB) + L1i L#3 (32KB) + Core L#3 + PU L#3 (P#3) CC: stable@vger.kernel.org # 456797da792f: arm64: topology: move store_cpu_topology() to shared code Fixes: 03f11f03dbfe ("RISC-V: Parse cpu topology during boot.") Reported-by: Brice Goglin Link: https://github.com/open-mpi/hwloc/issues/536 Reviewed-by: Sudeep Holla Reviewed-by: Atish Patra Signed-off-by: Conor Dooley --- I just resolved the conflicts, which was mainly removing mentions of NUMA. Tested in QEMU only. --- arch/riscv/Kconfig | 2 +- arch/riscv/kernel/smpboot.c | 4 +++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 1b894c327578..557c4a8c4087 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -35,7 +35,7 @@ config RISCV select CLINT_TIMER if !MMU select COMMON_CLK select EDAC_SUPPORT - select GENERIC_ARCH_TOPOLOGY if SMP + select GENERIC_ARCH_TOPOLOGY select GENERIC_ATOMIC64 if !64BIT select GENERIC_CLOCKEVENTS select GENERIC_EARLY_IOREMAP diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c index 0b04e0eae3ab..0e0aed380e28 100644 --- a/arch/riscv/kernel/smpboot.c +++ b/arch/riscv/kernel/smpboot.c @@ -46,6 +46,8 @@ void __init smp_prepare_cpus(unsigned int max_cpus) int cpuid; int ret; + store_cpu_topology(smp_processor_id()); + /* This covers non-smp usecase mandated by "nosmp" option */ if (max_cpus == 0) return; @@ -152,8 +154,8 @@ asmlinkage __visible void smp_callin(void) mmgrab(mm); current->active_mm = mm; + store_cpu_topology(curr_cpuid); notify_cpu_starting(curr_cpuid); - update_siblings_masks(curr_cpuid); set_cpu_online(curr_cpuid, 1); /*