From patchwork Wed Oct 19 12:52:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 5427 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp319257wrs; Wed, 19 Oct 2022 06:12:43 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5MNsaiga3I4fZKwxh9srBh1AczUaNL0pZNt2idoUjaD4fw071+Au3b9a0uBU55zidYGa6O X-Received: by 2002:a17:907:2da6:b0:78d:3cf1:9132 with SMTP id gt38-20020a1709072da600b0078d3cf19132mr6657935ejc.299.1666185162723; Wed, 19 Oct 2022 06:12:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666185162; cv=none; d=google.com; s=arc-20160816; b=XlTqT47QgYpq0n5RSxNLqSDSBOzGaRukdbbr63iaFQT4xb8FhZ0md73kaHzT7+QfDs FCGuQw6X5Z7zF/q+qBAS1PeebJST8wFV9IGbKz84tgFOGt9SxPduE25UoOw38RzvVKDX OIXDxjoXAfacjbPlhu9DxbnR++3uf2M1un4rlNVftLv95LkGW45UD9fDXVvnlQZJSRJv +04dVsbera3tAt48J84N1UPx8SgvtlZvvA6BeKltj90dUG44tk28YuVpU+rG4cta5Enf iPDRNRAersD7QnmKur6iz7HXBbkGdKxU+6zETb+Uk+htEt2p2CA2NfioVu8VPnS8QNsR aZYQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=XXn3y8KnHeX8Is9alHcywIXVDRZwIr6TjOS2xcB5atg=; b=dTHTS5CUNnonlltlbHhvN8y3jcMuLSSzPvMW6zOl/F9B5PzQjGs0wY2k0P4zIc5F3x +11SL8mwqyyTStmA/YXUSimL9/NqzwrQBZt+LTEnxPGHThWPBiZZhm/QS/Rr1EXnFO8G rYVSQZudiS7s/OCqkZ2Dn9mEo3e33fLT0SOnAvCHtWfuskTZRKrJGxJmiagBK8dxyHIU H4+NLyNUKcZYceRF5xFZLarUqhNV/L3B0l9pTSySfLnxoDo18ZlhfW10EHRHgGcD1C74 b5UvqHJZHs1Nqr3SumfXcwPI6RRTw7YCi4VRYrDKwIjSY4Si08MlU2oi4qGXHN9ShjRR SRMQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=hU9cRblH; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id t9-20020aa7db09000000b0045ca3642c4esi11965078eds.145.2022.10.19.06.11.57; Wed, 19 Oct 2022 06:12:42 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=hU9cRblH; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233014AbiJSNJx (ORCPT + 99 others); Wed, 19 Oct 2022 09:09:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43560 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231522AbiJSNJ3 (ORCPT ); Wed, 19 Oct 2022 09:09:29 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EAC8022530; Wed, 19 Oct 2022 05:54:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1666184077; x=1697720077; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=EbfoJoZkMkYyZLm3EYzvXahKcHMzK1vKqL4Mx9vLb6w=; b=hU9cRblHfi4VjUS86tUclSLf4I3/cPe0n1DSr2jlA+Vhm9gTJ4nI2R+N yC4oPKd3RytVhBRDmp2PG5IOc1EbBJtNoAQf6/Mbse7DLoKWGUHmqBePg sKV4vqwojONnlMsTnQFkvbARJS3gYkxeeGIgBDIeIyi9p2YXxyZR95ezR 4POGFY3Eiux3+Juvg04gPTd+fNYmH6xuk/uzfekXrErDt1YzjMJuGjUwa yWzQR1D1rxJDkl8hhgy4WpC+axpdvd8e43NKxBRsgiNoT+ynq/mY0tvTM OmRqmQMTN2uad4/KGV0OdjDhGjTfINPgf9uLhIo5JqXpa3rCER7OM7FmJ A==; X-IronPort-AV: E=Sophos;i="5.95,196,1661842800"; d="scan'208";a="179546648" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 19 Oct 2022 05:53:03 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Wed, 19 Oct 2022 05:53:01 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Wed, 19 Oct 2022 05:52:59 -0700 From: Conor Dooley To: CC: , , , , , , , , , , , Atish Patra Subject: [PATCH 5.4 1/2] arm64: topology: move store_cpu_topology() to shared code Date: Wed, 19 Oct 2022 13:52:09 +0100 Message-ID: <20221019125209.2844943-1-conor.dooley@microchip.com> X-Mailer: git-send-email 2.38.0 MIME-Version: 1.0 X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747121773114895455?= X-GMAIL-MSGID: =?utf-8?q?1747121773114895455?= commit 456797da792fa7cbf6698febf275fe9b36691f78 upstream. arm64's method of defining a default cpu topology requires only minimal changes to apply to RISC-V also. The current arm64 implementation exits early in a uniprocessor configuration by reading MPIDR & claiming that uniprocessor can rely on the default values. This is appears to be a hangover from prior to '3102bc0e6ac7 ("arm64: topology: Stop using MPIDR for topology information")', because the current code just assigns default values for multiprocessor systems. With the MPIDR references removed, store_cpu_topolgy() can be moved to the common arch_topology code. Reviewed-by: Sudeep Holla Acked-by: Catalin Marinas Reviewed-by: Atish Patra Signed-off-by: Conor Dooley --- arch/arm64/kernel/topology.c | 40 ------------------------------------ drivers/base/arch_topology.c | 19 +++++++++++++++++ 2 files changed, 19 insertions(+), 40 deletions(-) diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c index 113903db666c..3d3a673c6704 100644 --- a/arch/arm64/kernel/topology.c +++ b/arch/arm64/kernel/topology.c @@ -21,46 +21,6 @@ #include #include -void store_cpu_topology(unsigned int cpuid) -{ - struct cpu_topology *cpuid_topo = &cpu_topology[cpuid]; - u64 mpidr; - - if (cpuid_topo->package_id != -1) - goto topology_populated; - - mpidr = read_cpuid_mpidr(); - - /* Uniprocessor systems can rely on default topology values */ - if (mpidr & MPIDR_UP_BITMASK) - return; - - /* - * This would be the place to create cpu topology based on MPIDR. - * - * However, it cannot be trusted to depict the actual topology; some - * pieces of the architecture enforce an artificial cap on Aff0 values - * (e.g. GICv3's ICC_SGI1R_EL1 limits it to 15), leading to an - * artificial cycling of Aff1, Aff2 and Aff3 values. IOW, these end up - * having absolutely no relationship to the actual underlying system - * topology, and cannot be reasonably used as core / package ID. - * - * If the MT bit is set, Aff0 *could* be used to define a thread ID, but - * we still wouldn't be able to obtain a sane core ID. This means we - * need to entirely ignore MPIDR for any topology deduction. - */ - cpuid_topo->thread_id = -1; - cpuid_topo->core_id = cpuid; - cpuid_topo->package_id = cpu_to_node(cpuid); - - pr_debug("CPU%u: cluster %d core %d thread %d mpidr %#016llx\n", - cpuid, cpuid_topo->package_id, cpuid_topo->core_id, - cpuid_topo->thread_id, mpidr); - -topology_populated: - update_siblings_masks(cpuid); -} - #ifdef CONFIG_ACPI static bool __init acpi_cpu_is_threaded(int cpu) { diff --git a/drivers/base/arch_topology.c b/drivers/base/arch_topology.c index 503404f3280e..0dfe20d18b8d 100644 --- a/drivers/base/arch_topology.c +++ b/drivers/base/arch_topology.c @@ -538,4 +538,23 @@ void __init init_cpu_topology(void) else if (of_have_populated_dt() && parse_dt_topology()) reset_cpu_topology(); } + +void store_cpu_topology(unsigned int cpuid) +{ + struct cpu_topology *cpuid_topo = &cpu_topology[cpuid]; + + if (cpuid_topo->package_id != -1) + goto topology_populated; + + cpuid_topo->thread_id = -1; + cpuid_topo->core_id = cpuid; + cpuid_topo->package_id = cpu_to_node(cpuid); + + pr_debug("CPU%u: package %d core %d thread %d\n", + cpuid, cpuid_topo->package_id, cpuid_topo->core_id, + cpuid_topo->thread_id); + +topology_populated: + update_siblings_masks(cpuid); +} #endif From patchwork Wed Oct 19 12:52:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 5426 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp319225wrs; Wed, 19 Oct 2022 06:12:38 -0700 (PDT) X-Google-Smtp-Source: AMsMyM7+2e+bOFxfZQ07LPbPuRtJEvTUAYSPqeUAu6mZIAFILysjERgdW9wbLmVTF2m06YxHaO/M X-Received: by 2002:a05:6402:5cb:b0:452:e416:2bc4 with SMTP id n11-20020a05640205cb00b00452e4162bc4mr7274759edx.114.1666185158205; Wed, 19 Oct 2022 06:12:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666185158; cv=none; d=google.com; s=arc-20160816; b=bwEF1ar6C6r7PYM4JgFvbWMKMrKGSw1cYStYjUFS80YpmMyAuNXC+5XxnBLvdEjjGR nudpTjKkOIITR0XN6nwPNmuF5dgq1GpD0Fcvmns8P8vKWOlFH4DApvoS0J9AEIcJcVrF gyvJApfmHy4A600DRtOM1XfcP/nl9iyNpQ/AM+D9YmAYCIxFj+sSyIlbInAsesG8I3xY 7XGCVomXjSZEn+wSgtdhBOaAUYt0bS+T7QKrjYF5LHQm6T8cnMvdgSBjEQfJ/6UxJZX8 5oumGZch02nn4L1VcFEHL3grTr9mMhi3P8wmiiEyw6ilnpSUVAJl9bCwcN8hyA+iobaY DNEg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=l6sbUl0I5wjTcpbTLH2xC/loAR0V2wacryO5oFbYOzY=; b=mGt8CTyFzKDq6WiLcs74PknkeMoMOGNgDuOjV9mgZABEgjS/LPA3xCYl2WCd0hP/y/ /ZQO2/s93FeNydmLdFrG9eMbmHIhJ2GLjs3bbg865znoHB4W1+Nr02+GSh0XPSTEVoHN AUowb2qXb7aJENCuMbUsQTlG5bnCwL7k7Iqqcx68khoh1hQM7T8pk3e6lRZr+4AqlU2s LW06ivqbtZl+L7bnS3Nggp4ibElIxDylpV7J1LeCd16+vyxmOekaFXVGDybPaC4U4cDH 3ZMYirqGoRL476LDIQZgan/uATwYM2EYcd3KSpLWST9jiy1FYHczfCklkFVMsJodsv/b yV5w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b="zLB/5yw9"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id gs41-20020a1709072d2900b007392f9ad702si15903434ejc.741.2022.10.19.06.11.51; Wed, 19 Oct 2022 06:12:38 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b="zLB/5yw9"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231139AbiJSNJn (ORCPT + 99 others); Wed, 19 Oct 2022 09:09:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43048 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233672AbiJSNJV (ORCPT ); Wed, 19 Oct 2022 09:09:21 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EC7A8178A3; Wed, 19 Oct 2022 05:54:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1666184073; x=1697720073; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=6FLn9g71meNjs0yGLrKpiiiXP87EXkFC9cg0BIrfPWM=; b=zLB/5yw9v+AHtwoz47PI9g7uF1uY7F867ZBfZaiIbwpmMhI+W3aylp9W t3FwcNlrp+vtFsagf8UGpDN6b3uNnfHcXQGDB/a1QFmF56sKHrvOywZHC JsqBAV8NOfpolHxUHizqHCv1vdJl1zJxenHIZhHIg0FOvevz1KRNRwSgP zXm9KcHFWM+JHPZnJdSac3vFYrKnuUBTEnj9ZicGiLEnkGOFMViHgiI89 f0NzWMd4oxrFqLfHeB1Avvm40auTHYTC7jsOivIDZkzFLLvzQoalmnnO8 ZoLu/82r/09NV6ze3+o/beBCfRTwA4kdmqc7m265cItOh4/9TGpU+AVa0 Q==; X-IronPort-AV: E=Sophos;i="5.95,196,1661842800"; d="scan'208";a="185397545" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 19 Oct 2022 05:53:06 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Wed, 19 Oct 2022 05:53:04 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Wed, 19 Oct 2022 05:53:02 -0700 From: Conor Dooley To: CC: , , , , , , , , , , , Atish Patra Subject: [PATCH 5.4 2/2] riscv: topology: fix default topology reporting Date: Wed, 19 Oct 2022 13:52:10 +0100 Message-ID: <20221019125209.2844943-2-conor.dooley@microchip.com> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221019125209.2844943-1-conor.dooley@microchip.com> References: <20221019125209.2844943-1-conor.dooley@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747121768826866536?= X-GMAIL-MSGID: =?utf-8?q?1747121768826866536?= commit fbd92809997a391f28075f1c8b5ee314c225557c upstream. RISC-V has no sane defaults to fall back on where there is no cpu-map in the devicetree. Without sane defaults, the package, core and thread IDs are all set to -1. This causes user-visible inaccuracies for tools like hwloc/lstopo which rely on the sysfs cpu topology files to detect a system's topology. On a PolarFire SoC, which should have 4 harts with a thread each, lstopo currently reports: Machine (793MB total) Package L#0 NUMANode L#0 (P#0 793MB) Core L#0 L1d L#0 (32KB) + L1i L#0 (32KB) + PU L#0 (P#0) L1d L#1 (32KB) + L1i L#1 (32KB) + PU L#1 (P#1) L1d L#2 (32KB) + L1i L#2 (32KB) + PU L#2 (P#2) L1d L#3 (32KB) + L1i L#3 (32KB) + PU L#3 (P#3) Adding calls to store_cpu_topology() in {boot,smp} hart bringup code results in the correct topolgy being reported: Machine (793MB total) Package L#0 NUMANode L#0 (P#0 793MB) L1d L#0 (32KB) + L1i L#0 (32KB) + Core L#0 + PU L#0 (P#0) L1d L#1 (32KB) + L1i L#1 (32KB) + Core L#1 + PU L#1 (P#1) L1d L#2 (32KB) + L1i L#2 (32KB) + Core L#2 + PU L#2 (P#2) L1d L#3 (32KB) + L1i L#3 (32KB) + Core L#3 + PU L#3 (P#3) CC: stable@vger.kernel.org # 456797da792f: arm64: topology: move store_cpu_topology() to shared code Fixes: 03f11f03dbfe ("RISC-V: Parse cpu topology during boot.") Reported-by: Brice Goglin Link: https://github.com/open-mpi/hwloc/issues/536 Reviewed-by: Sudeep Holla Reviewed-by: Atish Patra Signed-off-by: Conor Dooley --- I just resolved the conflicts. Tested in QEMU only. SMP doesn't seem to work in 5.4, using the same command that works for 5.10. --- arch/riscv/Kconfig | 2 +- arch/riscv/kernel/smpboot.c | 4 +++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index b21549a34447..e0a77af5c130 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -51,7 +51,7 @@ config RISCV select PCI_MSI if PCI select RISCV_TIMER select GENERIC_IRQ_MULTI_HANDLER - select GENERIC_ARCH_TOPOLOGY if SMP + select GENERIC_ARCH_TOPOLOGY select ARCH_HAS_PTE_SPECIAL select ARCH_HAS_MMIOWB select HAVE_EBPF_JIT if 64BIT diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c index 261f4087cc39..0576a6b2bcc5 100644 --- a/arch/riscv/kernel/smpboot.c +++ b/arch/riscv/kernel/smpboot.c @@ -46,6 +46,8 @@ void __init smp_prepare_cpus(unsigned int max_cpus) { int cpuid; + store_cpu_topology(smp_processor_id()); + /* This covers non-smp usecase mandated by "nosmp" option */ if (max_cpus == 0) return; @@ -142,8 +144,8 @@ asmlinkage __visible void __init smp_callin(void) current->active_mm = mm; trap_init(); + store_cpu_topology(smp_processor_id()); notify_cpu_starting(smp_processor_id()); - update_siblings_masks(smp_processor_id()); set_cpu_online(smp_processor_id(), 1); /* * Remote TLB flushes are ignored while the CPU is offline, so emit