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([172.25.112.68]) by fmsmga008.fm.intel.com with ESMTP; 19 Oct 2022 03:13:31 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, brgerst@gmail.com, chang.seok.bae@intel.com Subject: [PATCH v4 1/5] x86/cpufeature: add the cpu feature bit for LKGS Date: Wed, 19 Oct 2022 02:50:31 -0700 Message-Id: <20221019095035.10823-2-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221019095035.10823-1-xin3.li@intel.com> References: <20221019095035.10823-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747117445671596588?= X-GMAIL-MSGID: =?utf-8?q?1747117445671596588?= From: "H. Peter Anvin (Intel)" Add the CPU feature bit for LKGS (Load "Kernel" GS). LKGS instruction is introduced with Intel FRED (flexible return and event delivery) specificaton https://cdrdv2.intel.com/v1/dl/getContent/678938. LKGS behaves like the MOV to GS instruction except that it loads the base address into the IA32_KERNEL_GS_BASE MSR instead of the GS segment’s descriptor cache, which is exactly what Linux kernel does to load a user level GS base. Thus, with LKGS, there is no need to SWAPGS away from the kernel GS base. Signed-off-by: H. Peter Anvin (Intel) Signed-off-by: Xin Li --- Change since V2: * add "" not to show "lkgs" in /proc/cpuinfo (Chang S. Bae). --- arch/x86/include/asm/cpufeatures.h | 1 + tools/arch/x86/include/asm/cpufeatures.h | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index b71f4f2ecdd5..3dc1a48c2796 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -308,6 +308,7 @@ /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */ #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */ #define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instructions */ +#define X86_FEATURE_LKGS (12*32+ 18) /* "" Load "kernel" (userspace) gs */ /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */ #define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */ diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/include/asm/cpufeatures.h index ef4775c6db01..9d45071d1730 100644 --- a/tools/arch/x86/include/asm/cpufeatures.h +++ b/tools/arch/x86/include/asm/cpufeatures.h @@ -308,6 +308,7 @@ /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */ #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */ #define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instructions */ +#define X86_FEATURE_LKGS (12*32+ 18) /* "" Load "kernel" (userspace) gs */ /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */ #define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */ From patchwork Wed Oct 19 09:50:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 5310 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp284110wrs; Wed, 19 Oct 2022 05:05:41 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4aEb5/ChQwgpLGFQZe+VItlcReVexX8qq84DlAnpFCZjhruxAK4uPLMsyzcJo1wbzD/qWL X-Received: by 2002:a17:903:1cc:b0:185:45e8:221d with SMTP id e12-20020a17090301cc00b0018545e8221dmr7992404plh.17.1666181141433; Wed, 19 Oct 2022 05:05:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666181141; cv=none; d=google.com; s=arc-20160816; b=ydYvlCegnnPubHIoDhop3u/s7NFeEmR7XrsQorJsmthl4b9iGFfQhnpkfzxRzam1TC 3xq2jD1CFwr33zNkVjJaBb301duVCglsXCdoVMRs6KJsbJX8sxeV+oYIl3+yXYyQSQRP P6B8mkSz1kwD7YcjGxKUaxueArL5UhiZK5y9mw+dX2oGQnCx9bm7PHPotvgyKc2CgyVe stzx01YTU8pfAoF9DLPPetsHHmpZSMuRp57lMs6lPrU8TkE2KDWXl9uH+lFP2ArTPrby CzsrDsh31XnhlBXMG8xG2eHFDt4BaEdMCbQSS6k7C4DdnWvikzEL8NF0OECTlTOTq10C dZWw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=+3L/zBhMiW903xYBCmWze24Rs8tywihmXNz1C+Zm5Es=; b=Grl9oeWpNnnusa1QdjOLtsYUrmYcEFMPzHUujc/86NOaaJ9CM+mFD0T+XNm0QJ35ja h8RpgGQHe/PqSAuWBVml2yOutgbeJ4MLUH5SzjzOXdOp2Vnm722s5xKhjbmfkVW4r1Lj ke458DTH18g1EndtO2ks22yo1yuKXfVU2r9AhNtVX9RScYMsm9EGGuinwJysBpET/LVZ r2eNbX4ftAOFMTxz07zzgRhZt3yAQ/F02ef90OkDMseA8Tzry3ox9WfG/G0yDsFswBiT hwtI1iJzCSaxoTFJTJASOhrUHEIrexZVEvE6eoe7D3GP6uNv1xYKobtYJ6uTrg8/bMec XcXQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=DwhpCYb0; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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([172.25.112.68]) by fmsmga008.fm.intel.com with ESMTP; 19 Oct 2022 03:13:32 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, brgerst@gmail.com, chang.seok.bae@intel.com Subject: [PATCH v4 2/5] x86/opcode: add the LKGS instruction to x86-opcode-map Date: Wed, 19 Oct 2022 02:50:32 -0700 Message-Id: <20221019095035.10823-3-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221019095035.10823-1-xin3.li@intel.com> References: <20221019095035.10823-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747117556133967278?= X-GMAIL-MSGID: =?utf-8?q?1747117556133967278?= From: "H. Peter Anvin (Intel)" Add the instruction opcode used by LKGS. Opcode number is per public FRED draft spec v3.0 https://cdrdv2.intel.com/v1/dl/getContent/678938. Signed-off-by: H. Peter Anvin (Intel) Signed-off-by: Xin Li --- arch/x86/lib/x86-opcode-map.txt | 1 + tools/arch/x86/lib/x86-opcode-map.txt | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/x86/lib/x86-opcode-map.txt b/arch/x86/lib/x86-opcode-map.txt index d12d1358f96d..5168ee0360b2 100644 --- a/arch/x86/lib/x86-opcode-map.txt +++ b/arch/x86/lib/x86-opcode-map.txt @@ -1047,6 +1047,7 @@ GrpTable: Grp6 3: LTR Ew 4: VERR Ew 5: VERW Ew +6: LKGS Ew (F2) EndTable GrpTable: Grp7 diff --git a/tools/arch/x86/lib/x86-opcode-map.txt b/tools/arch/x86/lib/x86-opcode-map.txt index d12d1358f96d..5168ee0360b2 100644 --- a/tools/arch/x86/lib/x86-opcode-map.txt +++ b/tools/arch/x86/lib/x86-opcode-map.txt @@ -1047,6 +1047,7 @@ GrpTable: Grp6 3: LTR Ew 4: VERR Ew 5: VERW Ew +6: LKGS Ew (F2) EndTable GrpTable: Grp7 From patchwork Wed Oct 19 09:50:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 5308 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp283806wrs; Wed, 19 Oct 2022 05:05:14 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5Ctipuuqr3ttXDg2pd5WdiP/1gC+HhVAvtP5rML45XJTDkYRSVQv0DIjKTm/pP3g8XodSj X-Received: by 2002:a17:90b:380d:b0:20d:8a42:1d74 with SMTP id mq13-20020a17090b380d00b0020d8a421d74mr9575404pjb.223.1666181114342; Wed, 19 Oct 2022 05:05:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666181114; cv=none; d=google.com; s=arc-20160816; b=z9JUQrYdOvD3UzXpxGgFWHLw9u6k8o47jNUyJU3BaeyYe/fJHhnOcTBfnhCY127kNu Hg6yJB6OPy/P6J3fzQUAGPyfpayxDHs1Hwv7FYHbERPtBMggxzcwercwNp0bA89dZCiX 1TODR+rDCMccm/A0ccfVw+tuDZDJolNDQ0Ej9r4nP8DrmZfe7iCb1/LejNOar167FVT2 wEbA/ruCsgzw4Hwg3f6M9VWIu2gMhJVPg1aY/sbOcxNwbkClJOriyk+sF0RpyDcl21yR 4kUUnYcvCMZPrg5adzvSIIiECoIjCQoxu6YbzxLgn1qqekhNO4tIH7o+V9NujkfQunoo bBqA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Y0zyNmAYzT3ri+4nefmoVJ0xInwrkHd8fCwz/8mxmhE=; b=iaTGRrd1nflUTs5GtILLGtEahb/5CX+hqY2hiCrXzpa/I4icIKTszLJ1l8de0Tpsbt Nnaen1aOpTUT/zGK6q1L5gKIClo4QR0c5/SsZoKb6UE2Rx9c9Oq8XpM0b3+OVwen1fxQ N1vfbJfUJxwZWGUe8VE9qQsZ849mOHWN4B1ivKkue7Y2c/q7cS24bLiRKO2wccbjvic3 k6436YGxPJeQJm1Xdn1W+SsXyMfBEPrkIb7XWMHOelrIZ7e/pCOfpgB2Q7USL/Ve91Go m3W2jvMNmrAp+jwfXMCcJ6SAvceHYyeG7yNCnnPxl+MoJbjztd0EctQOgMzVIxjsuOtC Fwsg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=h0aAip2J; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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([172.25.112.68]) by fmsmga008.fm.intel.com with ESMTP; 19 Oct 2022 03:13:32 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, brgerst@gmail.com, chang.seok.bae@intel.com Subject: [PATCH v4 3/5] x86/gsseg: make asm_load_gs_index() take an u16 Date: Wed, 19 Oct 2022 02:50:33 -0700 Message-Id: <20221019095035.10823-4-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221019095035.10823-1-xin3.li@intel.com> References: <20221019095035.10823-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747117527937028894?= X-GMAIL-MSGID: =?utf-8?q?1747117527937028894?= From: "H. Peter Anvin (Intel)" Let gcc know that only the low 16 bits of load_gs_index() argument actually matter. It might allow it to create slightly better code. However, do not propagate this into the prototypes of functions that end up being paravirtualized, to avoid unnecessary changes. Signed-off-by: H. Peter Anvin (Intel) Signed-off-by: Xin Li --- arch/x86/entry/entry_64.S | 2 +- arch/x86/include/asm/special_insns.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/entry/entry_64.S b/arch/x86/entry/entry_64.S index 9953d966d124..e0c48998d2fb 100644 --- a/arch/x86/entry/entry_64.S +++ b/arch/x86/entry/entry_64.S @@ -779,7 +779,7 @@ _ASM_NOKPROBE(common_interrupt_return) /* * Reload gs selector with exception handling - * edi: new selector + * di: new selector * * Is in entry.text as it shouldn't be instrumented. */ diff --git a/arch/x86/include/asm/special_insns.h b/arch/x86/include/asm/special_insns.h index 35f709f619fb..a71d0e8d4684 100644 --- a/arch/x86/include/asm/special_insns.h +++ b/arch/x86/include/asm/special_insns.h @@ -120,7 +120,7 @@ static inline void native_wbinvd(void) asm volatile("wbinvd": : :"memory"); } -extern asmlinkage void asm_load_gs_index(unsigned int selector); +extern asmlinkage void asm_load_gs_index(u16 selector); static inline void native_load_gs_index(unsigned int selector) { From patchwork Wed Oct 19 09:50:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 5312 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp284362wrs; Wed, 19 Oct 2022 05:06:03 -0700 (PDT) X-Google-Smtp-Source: AMsMyM7bh0YD2Q+dUqzFYi6ESdQVOvsmLZqIIg67YJHy71x0osyK+061YnxTER43XCV1RcLfV4O+ X-Received: by 2002:a17:90b:4a49:b0:20d:5099:f5cc with SMTP id lb9-20020a17090b4a4900b0020d5099f5ccmr9187886pjb.137.1666181152439; Wed, 19 Oct 2022 05:05:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666181152; cv=none; d=google.com; s=arc-20160816; b=Wnqr+q5X5MR2+bSqQBSHnKpx8+hi4Z9wvz+ogwcerpy0/q61yb/6Q/ZMddMIGsXnEl e6tkn+sD5zjwnUCADxuq1IfBTR4aDsKkIaVMTNDk2X6LkY4GJaHLMD5kzebL33atAzO5 NUMpoN8orgfQB6UFvbKCRloa80GP3+UyYgIHgKKjEvjnyE4GY0lLu3uJjEdzvNW9fleI vfP27aL3RDb14K9IxgDOHB0aLLIyuwWWpB0qNJGw54Ta4h16TZqqLmy6owwq6Aat45TG Ck4VGHZmT9T2TUYAUWpoWdVoGeXuXDBUaEEw8Jh8i0Q+0LkZ6ExwLJBxG+6JJVGMM4r6 4gWA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=B1/bKgLO1zn8qG0TcKZhJiT7VIXXp1YNTY7nenPzEwk=; b=xDD4Rik7/m9HHelTrJXOAEXz36x5FIyIGvHGn6mxBa/F5nWpcl55fH2+7EY+dnDCNM HhrZmHlMaiUQSYJCILDsHRqfuyb3JpUVw6Z9SuQzHDvXprsRXUnwYNtKbvvNVKr+5cLe 5ZfGL3fTXPMWKSUDFCTM/nMUKAUz0hIi86AQ6YVEdZBFJnQ8pV8wz1pSsbfyKFUJi7+r OllA1mVoapvlir9Sj6ey+uJLWKkYdFES/aBJN8/5VSxShEpM0K2UQqEjWsABwATuwjGb o0/yReFJTmcI46sEcA7IR9CM/NVTtvDUvb3LVq2BFk7OjiofAX2RIqDZ2Czyej+gIb/R 7yBg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=MbNhhzPC; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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([172.25.112.68]) by fmsmga008.fm.intel.com with ESMTP; 19 Oct 2022 03:13:32 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, brgerst@gmail.com, chang.seok.bae@intel.com Subject: [PATCH v4 4/5] x86/gsseg: move load_gs_index() to its own new header file Date: Wed, 19 Oct 2022 02:50:34 -0700 Message-Id: <20221019095035.10823-5-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221019095035.10823-1-xin3.li@intel.com> References: <20221019095035.10823-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747117567992547081?= X-GMAIL-MSGID: =?utf-8?q?1747117567992547081?= From: "H. Peter Anvin (Intel)" GS is a special segment on x86_64, move load_gs_index() to its own new header file. Signed-off-by: H. Peter Anvin (Intel) Signed-off-by: Xin Li --- arch/x86/ia32/ia32_signal.c | 1 + arch/x86/include/asm/gsseg.h | 41 ++++++++++++++++++++++++++++ arch/x86/include/asm/mmu_context.h | 1 + arch/x86/include/asm/special_insns.h | 21 -------------- arch/x86/kernel/paravirt.c | 1 + arch/x86/kernel/tls.c | 1 + 6 files changed, 45 insertions(+), 21 deletions(-) create mode 100644 arch/x86/include/asm/gsseg.h diff --git a/arch/x86/ia32/ia32_signal.c b/arch/x86/ia32/ia32_signal.c index c9c3859322fa..14c739303099 100644 --- a/arch/x86/ia32/ia32_signal.c +++ b/arch/x86/ia32/ia32_signal.c @@ -34,6 +34,7 @@ #include #include #include +#include static inline void reload_segments(struct sigcontext_32 *sc) { diff --git a/arch/x86/include/asm/gsseg.h b/arch/x86/include/asm/gsseg.h new file mode 100644 index 000000000000..d15577c39e8d --- /dev/null +++ b/arch/x86/include/asm/gsseg.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef _ASM_X86_GSSEG_H +#define _ASM_X86_GSSEG_H + +#include + +#include +#include +#include +#include +#include + +#ifdef CONFIG_X86_64 + +extern asmlinkage void asm_load_gs_index(u16 selector); + +static inline void native_load_gs_index(unsigned int selector) +{ + unsigned long flags; + + local_irq_save(flags); + asm_load_gs_index(selector); + local_irq_restore(flags); +} + +#endif /* CONFIG_X86_64 */ + +#ifndef CONFIG_PARAVIRT_XXL + +static inline void load_gs_index(unsigned int selector) +{ +#ifdef CONFIG_X86_64 + native_load_gs_index(selector); +#else + loadsegment(gs, selector); +#endif +} + +#endif /* CONFIG_PARAVIRT_XXL */ + +#endif /* _ASM_X86_GSSEG_H */ diff --git a/arch/x86/include/asm/mmu_context.h b/arch/x86/include/asm/mmu_context.h index b8d40ddeab00..e01aa74a6de7 100644 --- a/arch/x86/include/asm/mmu_context.h +++ b/arch/x86/include/asm/mmu_context.h @@ -12,6 +12,7 @@ #include #include #include +#include extern atomic64_t last_mm_ctx_id; diff --git a/arch/x86/include/asm/special_insns.h b/arch/x86/include/asm/special_insns.h index a71d0e8d4684..cfd9499b617c 100644 --- a/arch/x86/include/asm/special_insns.h +++ b/arch/x86/include/asm/special_insns.h @@ -120,17 +120,6 @@ static inline void native_wbinvd(void) asm volatile("wbinvd": : :"memory"); } -extern asmlinkage void asm_load_gs_index(u16 selector); - -static inline void native_load_gs_index(unsigned int selector) -{ - unsigned long flags; - - local_irq_save(flags); - asm_load_gs_index(selector); - local_irq_restore(flags); -} - static inline unsigned long __read_cr4(void) { return native_read_cr4(); @@ -184,16 +173,6 @@ static inline void wbinvd(void) native_wbinvd(); } - -static inline void load_gs_index(unsigned int selector) -{ -#ifdef CONFIG_X86_64 - native_load_gs_index(selector); -#else - loadsegment(gs, selector); -#endif -} - #endif /* CONFIG_PARAVIRT_XXL */ static inline void clflush(volatile void *__p) diff --git a/arch/x86/kernel/paravirt.c b/arch/x86/kernel/paravirt.c index 7ca2d46c08cc..00f6a92551d2 100644 --- a/arch/x86/kernel/paravirt.c +++ b/arch/x86/kernel/paravirt.c @@ -32,6 +32,7 @@ #include #include #include +#include /* * nop stub, which must not clobber anything *including the stack* to diff --git a/arch/x86/kernel/tls.c b/arch/x86/kernel/tls.c index 3c883e064242..3ffbab0081f4 100644 --- a/arch/x86/kernel/tls.c +++ b/arch/x86/kernel/tls.c @@ -12,6 +12,7 @@ #include #include #include +#include #include "tls.h" From patchwork Wed Oct 19 09:50:35 2022 Content-Type: text/plain; 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([172.25.112.68]) by fmsmga008.fm.intel.com with ESMTP; 19 Oct 2022 03:13:32 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, brgerst@gmail.com, chang.seok.bae@intel.com Subject: [PATCH v4 5/5] x86/gsseg: use the LKGS instruction if available for load_gs_index() Date: Wed, 19 Oct 2022 02:50:35 -0700 Message-Id: <20221019095035.10823-6-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221019095035.10823-1-xin3.li@intel.com> References: <20221019095035.10823-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747117636384414497?= X-GMAIL-MSGID: =?utf-8?q?1747117636384414497?= From: "H. Peter Anvin (Intel)" The LKGS instruction atomically loads a segment descriptor into the %gs descriptor registers, *except* that %gs.base is unchanged, and the base is instead loaded into MSR_IA32_KERNEL_GS_BASE, which is exactly what we want this function to do. Signed-off-by: H. Peter Anvin (Intel) Signed-off-by: Peter Zijlstra (Intel) Signed-off-by: Brian Gerst Signed-off-by: Xin Li --- Changes since v3: * We want less ASM not more, thus keep local_irq_save/restore() inside native_load_gs_index() (Thomas Gleixner). * For paravirt enabled kernels, initialize pv_ops.cpu.load_gs_index to native_lkgs (Thomas Gleixner). Changes since V2: * Mark DI as input and output (+D) as in V1, since the exception handler modifies it (Brian Gerst). Changes since V1: * Use EX_TYPE_ZERO_REG instead of fixup code in the obsolete .fixup code section (Peter Zijlstra). * Add a comment that states the LKGS_DI macro will be repalced with "lkgs %di" once the binutils support the LKGS instruction (Peter Zijlstra). --- arch/x86/include/asm/gsseg.h | 33 +++++++++++++++++++++++++++++---- arch/x86/kernel/cpu/common.c | 1 + 2 files changed, 30 insertions(+), 4 deletions(-) diff --git a/arch/x86/include/asm/gsseg.h b/arch/x86/include/asm/gsseg.h index d15577c39e8d..ab6a595cea70 100644 --- a/arch/x86/include/asm/gsseg.h +++ b/arch/x86/include/asm/gsseg.h @@ -14,17 +14,42 @@ extern asmlinkage void asm_load_gs_index(u16 selector); +/* Replace with "lkgs %di" once binutils support LKGS instruction */ +#define LKGS_DI _ASM_BYTES(0xf2,0x0f,0x00,0xf7) + +static inline void native_lkgs(unsigned int selector) +{ + u16 sel = selector; + asm_inline volatile("1: " LKGS_DI + _ASM_EXTABLE_TYPE_REG(1b, 1b, EX_TYPE_ZERO_REG, %k[sel]) + : [sel] "+D" (sel)); +} + static inline void native_load_gs_index(unsigned int selector) { - unsigned long flags; + if (cpu_feature_enabled(X86_FEATURE_LKGS)) { + native_lkgs(selector); + } else { + unsigned long flags; - local_irq_save(flags); - asm_load_gs_index(selector); - local_irq_restore(flags); + local_irq_save(flags); + asm_load_gs_index(selector); + local_irq_restore(flags); + } } #endif /* CONFIG_X86_64 */ +static inline void __init lkgs_init(void) +{ +#ifdef CONFIG_PARAVIRT_XXL +#ifdef CONFIG_X86_64 + if (cpu_feature_enabled(X86_FEATURE_LKGS)) + pv_ops.cpu.load_gs_index = native_lkgs; +#endif +#endif +} + #ifndef CONFIG_PARAVIRT_XXL static inline void load_gs_index(unsigned int selector) diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 3e508f239098..d6eb4f60b47d 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1939,6 +1939,7 @@ void __init identify_boot_cpu(void) setup_cr_pinning(); tsx_init(); + lkgs_init(); } void identify_secondary_cpu(struct cpuinfo_x86 *c)