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[8.43.85.97]) by mx.google.com with ESMTPS id j4-20020a17090686c400b008d47cd2ee00si1301899ejy.290.2023.03.13.19.24.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Mar 2023 19:24:15 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 135023858430 for ; Tue, 14 Mar 2023 02:24:09 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbguseast2.qq.com (smtpbguseast2.qq.com [54.204.34.130]) by sourceware.org (Postfix) with ESMTPS id 127793858D32 for ; Tue, 14 Mar 2023 02:23:39 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 127793858D32 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp68t1678760614twz0f3i6 Received: from rios-cad5.localdomain ( [58.60.1.11]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 14 Mar 2023 10:23:33 +0800 (CST) X-QQ-SSF: 01400000000000E0N000000A0000000 X-QQ-FEAT: k0mQ4ihyJQOBD/vOCC7azdt/8I3mqkp7iZ6cYQV5wv5FY0KGYSJ/DAXfM60zM iWaQHsNUnaNfnoCwdXTX4AO4JbsfOE8fcQslDkfuWVpJ8dJW3quQCYn0qel4lPcWVIrXLdo yI5fL0ci/H1um+ZtI03NNsMSm/eDIW+5KoI5hiJ9baeCr5PgVv/NRwKJ7L5rSIU0LKxaPxh 3n+GYH2FnhDXoToRrrnyC5pAEKSU6/EgeaPXP3k0uznojhVtEFGsPu11EVr4TS2BoFDkluN mbt72+FXo0jsvffF7wR+SwR+EkkKEmDN8ovMWqWsdyRZJJ2s22aHAa00qsNRkvDYnbtdHnn 8hxqvMQoGdV7UPOacyNFoZ+dJ+kIV5BRLGUWEjl+0bmzS61IQ0MFf6Dtm6EKhtDeUc4s9GU exhQZ6gskPI= X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Ju-Zhe Zhong , kito-cheng Subject: [PATCH] RISC-V: Fix bugs of ternary integer and floating-point ternary intrinsics. Date: Tue, 14 Mar 2023 10:23:31 +0800 Message-Id: <20230314022331.105558-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-12.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1760308132665087462?= X-GMAIL-MSGID: =?utf-8?q?1760308132665087462?= From: Ju-Zhe Zhong Co-authored-by: kito-cheng Co-authored-by: kito-cheng This patch is fixing the bugs reported by @kito. // vnmsub.vx vd, rs1, vs2, vm # vd[i] = -(x[rs1] * vd[i]) + vs2[i] // vd = -(vb * a) + vc // = -(3 * 1) + 10 // = 7 // GCC wrongly optmize this pattern to `3 - 10` due to we write wrong RTL // pattern. // vd = (3 * 1) - 10 // = 3 - 10 // = -7 // NOTE: GCC optimized (vb * a) - vc to vb - vc Signed-off-by: Ju-Zhe Zhong Co-authored-by: kito-cheng Co-authored-by: kito-cheng gcc/ChangeLog: * config/riscv/vector.md: Correct ternary patterns. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/bug-3.c: New test. * gcc.target/riscv/rvv/base/bug-4.c: New test. * gcc.target/riscv/rvv/base/bug-5.c: New test. --- gcc/config/riscv/vector.md | 80 +++++++++---------- .../gcc.target/riscv/rvv/base/bug-3.c | 22 +++++ .../gcc.target/riscv/rvv/base/bug-4.c | 22 +++++ .../gcc.target/riscv/rvv/base/bug-5.c | 22 +++++ 4 files changed, 106 insertions(+), 40 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/bug-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/bug-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/bug-5.c diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 5f765cdbacb..27c5cccb451 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -4160,10 +4160,10 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (plus_minus:VI + (match_operand:VI 4 "register_operand") (mult:VI (match_operand:VI 2 "register_operand") - (match_operand:VI 3 "register_operand")) - (match_operand:VI 4 "register_operand")) + (match_operand:VI 3 "register_operand"))) (match_operand:VI 5 "register_operand")))] "TARGET_VECTOR" { @@ -4185,10 +4185,10 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (plus_minus:VI + (match_operand:VI 4 "register_operand" " vr, vr, vr") (mult:VI (match_operand:VI 2 "register_operand" " 0, 0, vr") - (match_operand:VI 3 "register_operand" " vr, vr, vr")) - (match_operand:VI 4 "register_operand" " vr, vr, vr")) + (match_operand:VI 3 "register_operand" " vr, vr, vr"))) (match_dup 2)))] "TARGET_VECTOR" "@ @@ -4215,10 +4215,10 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (plus_minus:VI + (match_operand:VI 4 "register_operand" " 0, 0, vr") (mult:VI (match_operand:VI 2 "register_operand" " vr, vr, vr") - (match_operand:VI 3 "register_operand" " vr, vr, vr")) - (match_operand:VI 4 "register_operand" " 0, 0, vr")) + (match_operand:VI 3 "register_operand" " vr, vr, vr"))) (match_dup 4)))] "TARGET_VECTOR" "@ @@ -4245,10 +4245,10 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (plus_minus:VI + (match_operand:VI 4 "vector_arith_operand" " vr, vi, vr, vr, vr") (mult:VI (match_operand:VI 2 "register_operand" " vr, vr, vi, vr, vr") - (match_operand:VI 3 "register_operand" " vr, vr, vr, vi, vr")) - (match_operand:VI 4 "vector_arith_operand" " vr, vi, vr, vr, vr")) + (match_operand:VI 3 "register_operand" " vr, vr, vr, vi, vr"))) (match_operand:VI 5 "register_operand" " 0, vr, vr, vr, vr")))] "TARGET_VECTOR && !rtx_equal_p (operands[2], operands[5]) @@ -4296,11 +4296,11 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (plus_minus:VI_QHS + (match_operand:VI_QHS 4 "register_operand") (mult:VI_QHS (vec_duplicate:VI_QHS (match_operand: 2 "reg_or_int_operand")) - (match_operand:VI_QHS 3 "register_operand")) - (match_operand:VI_QHS 4 "register_operand")) + (match_operand:VI_QHS 3 "register_operand"))) (match_operand:VI_QHS 5 "register_operand")))] "TARGET_VECTOR" { @@ -4319,11 +4319,11 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (plus_minus:VI + (match_operand:VI 4 "register_operand" " vr, vr, vr") (mult:VI (vec_duplicate:VI (match_operand: 2 "register_operand" " r, r, vr")) - (match_operand:VI 3 "register_operand" " 0, 0, vr")) - (match_operand:VI 4 "register_operand" " vr, vr, vr")) + (match_operand:VI 3 "register_operand" " 0, 0, vr"))) (match_dup 3)))] "TARGET_VECTOR" "@ @@ -4350,11 +4350,11 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (plus_minus:VI + (match_operand:VI 4 "register_operand" " 0, 0, vr") (mult:VI (vec_duplicate:VI (match_operand: 2 "register_operand" " r, r, vr")) - (match_operand:VI 3 "register_operand" " vr, vr, vr")) - (match_operand:VI 4 "register_operand" " 0, 0, vr")) + (match_operand:VI 3 "register_operand" " vr, vr, vr"))) (match_dup 4)))] "TARGET_VECTOR" "@ @@ -4381,11 +4381,11 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (plus_minus:VI + (match_operand:VI 4 "vector_arith_operand" " vr, vi, vr, vr") (mult:VI (vec_duplicate:VI (match_operand: 2 "register_operand" " r, r, r, r")) - (match_operand:VI 3 "register_operand" " vr, vr, vi, vr")) - (match_operand:VI 4 "vector_arith_operand" " vr, vi, vr, vr")) + (match_operand:VI 3 "register_operand" " vr, vr, vi, vr"))) (match_operand:VI 5 "register_operand" " 0, vr, vr, vr")))] "TARGET_VECTOR && !rtx_equal_p (operands[3], operands[5]) @@ -4428,11 +4428,11 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (plus_minus:VI_D + (match_operand:VI_D 4 "register_operand") (mult:VI_D (vec_duplicate:VI_D (match_operand: 2 "reg_or_int_operand")) - (match_operand:VI_D 3 "register_operand")) - (match_operand:VI_D 4 "register_operand")) + (match_operand:VI_D 3 "register_operand"))) (match_operand:VI_D 5 "register_operand")))] "TARGET_VECTOR" { @@ -4463,12 +4463,12 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (plus_minus:VI_D + (match_operand:VI_D 4 "register_operand" " vr, vr, vr") (mult:VI_D (vec_duplicate:VI_D (sign_extend: (match_operand: 2 "register_operand" " r, r, vr"))) - (match_operand:VI_D 3 "register_operand" " 0, 0, vr")) - (match_operand:VI_D 4 "register_operand" " vr, vr, vr")) + (match_operand:VI_D 3 "register_operand" " 0, 0, vr"))) (match_dup 3)))] "TARGET_VECTOR" "@ @@ -4495,12 +4495,12 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (plus_minus:VI_D + (match_operand:VI_D 4 "register_operand" " 0, 0, vr") (mult:VI_D (vec_duplicate:VI_D (sign_extend: (match_operand: 2 "register_operand" " r, r, vr"))) - (match_operand:VI_D 3 "register_operand" " vr, vr, vr")) - (match_operand:VI_D 4 "register_operand" " 0, 0, vr")) + (match_operand:VI_D 3 "register_operand" " vr, vr, vr"))) (match_dup 4)))] "TARGET_VECTOR" "@ @@ -4527,12 +4527,12 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (plus_minus:VI_D + (match_operand:VI_D 4 "vector_arith_operand" " vr, vr, vr, vr") (mult:VI_D (vec_duplicate:VI_D (sign_extend: (match_operand: 2 "register_operand" " r, r, r, r"))) - (match_operand:VI_D 3 "register_operand" " vr, vr, vr, vr")) - (match_operand:VI_D 4 "vector_arith_operand" " vr, vr, vr, vr")) + (match_operand:VI_D 3 "register_operand" " vr, vr, vr, vr"))) (match_operand:VI_D 5 "register_operand" " 0, vr, vr, vr")))] "TARGET_VECTOR && !rtx_equal_p (operands[3], operands[5]) @@ -5033,10 +5033,10 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (plus_minus:VF + (match_operand:VF 4 "register_operand") (mult:VF (match_operand:VF 2 "register_operand") - (match_operand:VF 3 "register_operand")) - (match_operand:VF 4 "register_operand")) + (match_operand:VF 3 "register_operand"))) (match_operand:VF 5 "register_operand")))] "TARGET_VECTOR" { @@ -5058,10 +5058,10 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (plus_minus:VF + (match_operand:VF 4 "register_operand" " vr, vr, vr") (mult:VF (match_operand:VF 2 "register_operand" " 0, 0, vr") - (match_operand:VF 3 "register_operand" " vr, vr, vr")) - (match_operand:VF 4 "register_operand" " vr, vr, vr")) + (match_operand:VF 3 "register_operand" " vr, vr, vr"))) (match_dup 2)))] "TARGET_VECTOR" "@ @@ -5088,10 +5088,10 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (plus_minus:VF + (match_operand:VF 4 "register_operand" " 0, 0, vr") (mult:VF (match_operand:VF 2 "register_operand" " vr, vr, vr") - (match_operand:VF 3 "register_operand" " vr, vr, vr")) - (match_operand:VF 4 "register_operand" " 0, 0, vr")) + (match_operand:VF 3 "register_operand" " vr, vr, vr"))) (match_dup 4)))] "TARGET_VECTOR" "@ @@ -5118,10 +5118,10 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (plus_minus:VF + (match_operand:VF 4 "vector_arith_operand" " vr, vr") (mult:VF (match_operand:VF 2 "register_operand" " vr, vr") - (match_operand:VF 3 "register_operand" " vr, vr")) - (match_operand:VF 4 "vector_arith_operand" " vr, vr")) + (match_operand:VF 3 "register_operand" " vr, vr"))) (match_operand:VF 5 "register_operand" " 0, vr")))] "TARGET_VECTOR && !rtx_equal_p (operands[2], operands[5]) @@ -5153,11 +5153,11 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (plus_minus:VF + (match_operand:VF 4 "register_operand") (mult:VF (vec_duplicate:VF (match_operand: 2 "register_operand")) - (match_operand:VF 3 "register_operand")) - (match_operand:VF 4 "register_operand")) + (match_operand:VF 3 "register_operand"))) (match_operand:VF 5 "register_operand")))] "TARGET_VECTOR" {}) @@ -5174,11 +5174,11 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (plus_minus:VF + (match_operand:VF 4 "register_operand" " vr, vr, vr") (mult:VF (vec_duplicate:VF (match_operand: 2 "register_operand" " f, f, vr")) - (match_operand:VF 3 "register_operand" " 0, 0, vr")) - (match_operand:VF 4 "register_operand" " vr, vr, vr")) + (match_operand:VF 3 "register_operand" " 0, 0, vr"))) (match_dup 3)))] "TARGET_VECTOR" "@ @@ -5205,11 +5205,11 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (plus_minus:VF + (match_operand:VF 4 "register_operand" " 0, 0, vr") (mult:VF (vec_duplicate:VF (match_operand: 2 "register_operand" " f, f, vr")) - (match_operand:VF 3 "register_operand" " vr, vr, vr")) - (match_operand:VF 4 "register_operand" " 0, 0, vr")) + (match_operand:VF 3 "register_operand" " vr, vr, vr"))) (match_dup 4)))] "TARGET_VECTOR" "@ @@ -5236,11 +5236,11 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (plus_minus:VF + (match_operand:VF 4 "vector_arith_operand" " vr, vr") (mult:VF (vec_duplicate:VF (match_operand: 2 "register_operand" " f, f")) - (match_operand:VF 3 "register_operand" " vr, vr")) - (match_operand:VF 4 "vector_arith_operand" " vr, vr")) + (match_operand:VF 3 "register_operand" " vr, vr"))) (match_operand:VF 5 "register_operand" " 0, vr")))] "TARGET_VECTOR && !rtx_equal_p (operands[3], operands[5]) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-3.c new file mode 100644 index 00000000000..35b76892598 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-3.c @@ -0,0 +1,22 @@ +/* { dg-do run } */ +/* { dg-options "-O2" } */ + +#include "riscv_vector.h" +#include + +int main() +{ + int32_t a = 1; + int32_t b[1] = {3}; + int32_t c[1] = {10}; + int32_t d[1] = {0}; + vint32m1_t vb = __riscv_vle32_v_i32m1 (b, 1); + vint32m1_t vc = __riscv_vle32_v_i32m1 (c, 1); + vint32m1_t vd = __riscv_vnmsub_vx_i32m1 (vb, a, vc, 1); + __riscv_vse32_v_i32m1 (d, vd, 1); + if (d[0] != 7){ + printf("d[0] should be 7, but got %d\n", d[0]); + __builtin_abort (); + } + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-4.c new file mode 100644 index 00000000000..62dd3f50e44 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-4.c @@ -0,0 +1,22 @@ +/* { dg-do run } */ +/* { dg-options "-O2" } */ + +#include "riscv_vector.h" +#include + +int main() +{ + float a = 1.0; + float b[1] = {3.0}; + float c[1] = {10.0}; + float d[1] = {0.0}; + vfloat32m1_t vb = __riscv_vle32_v_f32m1 (b, 1); + vfloat32m1_t vc = __riscv_vle32_v_f32m1 (c, 1); + vfloat32m1_t vd = __riscv_vfnmsub_vf_f32m1 (vb, a, vc, 1); + __riscv_vse32_v_f32m1 (d, vd, 1); + if (d[0] != 7.0){ + printf("d[0] should be 7.0, but got %f\n", d[0]); + __builtin_abort (); + } + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/bug-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-5.c new file mode 100644 index 00000000000..e43f85a0730 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/bug-5.c @@ -0,0 +1,22 @@ +/* { dg-do run } */ +/* { dg-options "-O2" } */ + +#include "riscv_vector.h" +#include + +int main() +{ + float a = 1.0; + float b[1] = {3.0}; + float c[1] = {10.0}; + float d[1] = {0.0}; + vfloat32m1_t vb = __riscv_vle32_v_f32m1 (b, 1); + vfloat32m1_t vc = __riscv_vle32_v_f32m1 (c, 1); + vfloat32m1_t vd = __riscv_vfmsub_vf_f32m1 (vb, a, vc, 1); + __riscv_vse32_v_f32m1 (d, vd, 1); + if (d[0] != -7.0){ + printf("d[0] should be -7.0, but got %f\n", d[0]); + __builtin_abort (); + } + return 0; +}