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([172.25.112.68]) by orsmga005.jf.intel.com with ESMTP; 19 Oct 2022 03:46:20 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, brgerst@gmail.com, chang.seok.bae@intel.com Subject: [PATCH v4 1/5] x86/cpufeature: add the cpu feature bit for LKGS Date: Wed, 19 Oct 2022 03:23:06 -0700 Message-Id: <20221019102310.1543-2-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221019102310.1543-1-xin3.li@intel.com> References: <20221019102310.1543-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747114992093709663?= X-GMAIL-MSGID: =?utf-8?q?1747114992093709663?= From: "H. Peter Anvin (Intel)" Add the CPU feature bit for LKGS (Load "Kernel" GS). LKGS instruction is introduced with Intel FRED (flexible return and event delivery) specificaton https://cdrdv2.intel.com/v1/dl/getContent/678938. LKGS behaves like the MOV to GS instruction except that it loads the base address into the IA32_KERNEL_GS_BASE MSR instead of the GS segment’s descriptor cache, which is exactly what Linux kernel does to load a user level GS base. Thus, with LKGS, there is no need to SWAPGS away from the kernel GS base. Signed-off-by: H. Peter Anvin (Intel) Signed-off-by: Xin Li --- Change since V2: * add "" not to show "lkgs" in /proc/cpuinfo (Chang S. Bae). --- arch/x86/include/asm/cpufeatures.h | 1 + tools/arch/x86/include/asm/cpufeatures.h | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index b71f4f2ecdd5..3dc1a48c2796 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -308,6 +308,7 @@ /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */ #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */ #define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instructions */ +#define X86_FEATURE_LKGS (12*32+ 18) /* "" Load "kernel" (userspace) gs */ /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */ #define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */ diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/include/asm/cpufeatures.h index ef4775c6db01..9d45071d1730 100644 --- a/tools/arch/x86/include/asm/cpufeatures.h +++ b/tools/arch/x86/include/asm/cpufeatures.h @@ -308,6 +308,7 @@ /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */ #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */ #define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instructions */ +#define X86_FEATURE_LKGS (12*32+ 18) /* "" Load "kernel" (userspace) gs */ /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */ #define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */ From patchwork Wed Oct 19 10:23:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 5235 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp266901wrs; Wed, 19 Oct 2022 04:25:55 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5corrL/4gN4m/t90SyMdgFt/3izQqci0MHUIjBY+/NeO5uUJ6NFAPZu10U53ACG1Z8aFRO X-Received: by 2002:a17:90a:d914:b0:20a:a3e7:616f with SMTP id c20-20020a17090ad91400b0020aa3e7616fmr9314572pjv.108.1666178755190; Wed, 19 Oct 2022 04:25:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666178755; cv=none; d=google.com; s=arc-20160816; b=dKtx2wFPcTfnQAxsfCFqV/p5XxQXctgwl1EWWVfz2/lqM0krQvRNzZjULRhk8Pu7fp o88FX6hHauZx97rS580bjQXdzm22i77lZapztQ0ZIB1Erj6AQqdyEhJN+z9p9q8WhjEU smbcbkkGFcentFhkuHOdQYeRF+zyEfUIUm65TUTccw+Pqs1yfAruLfXvH1aCEz61XRqO J0U0a5aatf69bPF+LXZvKdPKDxleHOKImJc3ohy/kQ+lWe4AyJc90W+gK71Ubdcp629D vMROjps7n28lAkcX3lL5isSXeCcXzxR7xUOqeenarLmLeEEhCLvPfuh/ZwvN6EKmFiEG FA7Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=+3L/zBhMiW903xYBCmWze24Rs8tywihmXNz1C+Zm5Es=; b=DzegdFaOalhFU+n0uHc7eM4fpBXth1FUL36616YwfPW80oZgfHtY77NMkIgcCGni4k yeAG+yE9Q4v65bUWBuJIFNF+cU0fkwb8CEam3yxUZiPJE/0mGT+rvEL+0AGbTkrnm5hf MY/1FT8yTbXUb0w6WGrzaXc96ryR6zYhMxgmZm7882+tmnYXqX7ZYFg9br/OZbHYKzbf HZa36RMJ5tfhJxmkFdHVgB5sN0R6AenLROfaux/5o+axRc1BcuJbFvqHRtUjef45ssyY oSYnEY2j5c6SwLRMNjtoDcVCSitgGpJzlLYT8aCcJalQ8Rj/L98idn0Vr/u+KPW+fMjB 0koQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=MeEXRtd+; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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([172.25.112.68]) by orsmga005.jf.intel.com with ESMTP; 19 Oct 2022 03:46:20 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, brgerst@gmail.com, chang.seok.bae@intel.com Subject: [PATCH v4 2/5] x86/opcode: add the LKGS instruction to x86-opcode-map Date: Wed, 19 Oct 2022 03:23:07 -0700 Message-Id: <20221019102310.1543-3-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221019102310.1543-1-xin3.li@intel.com> References: <20221019102310.1543-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747115054356056462?= X-GMAIL-MSGID: =?utf-8?q?1747115054356056462?= From: "H. Peter Anvin (Intel)" Add the instruction opcode used by LKGS. Opcode number is per public FRED draft spec v3.0 https://cdrdv2.intel.com/v1/dl/getContent/678938. Signed-off-by: H. Peter Anvin (Intel) Signed-off-by: Xin Li --- arch/x86/lib/x86-opcode-map.txt | 1 + tools/arch/x86/lib/x86-opcode-map.txt | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/x86/lib/x86-opcode-map.txt b/arch/x86/lib/x86-opcode-map.txt index d12d1358f96d..5168ee0360b2 100644 --- a/arch/x86/lib/x86-opcode-map.txt +++ b/arch/x86/lib/x86-opcode-map.txt @@ -1047,6 +1047,7 @@ GrpTable: Grp6 3: LTR Ew 4: VERR Ew 5: VERW Ew +6: LKGS Ew (F2) EndTable GrpTable: Grp7 diff --git a/tools/arch/x86/lib/x86-opcode-map.txt b/tools/arch/x86/lib/x86-opcode-map.txt index d12d1358f96d..5168ee0360b2 100644 --- a/tools/arch/x86/lib/x86-opcode-map.txt +++ b/tools/arch/x86/lib/x86-opcode-map.txt @@ -1047,6 +1047,7 @@ GrpTable: Grp6 3: LTR Ew 4: VERR Ew 5: VERW Ew +6: LKGS Ew (F2) EndTable GrpTable: Grp7 From patchwork Wed Oct 19 10:23:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 5236 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp267046wrs; Wed, 19 Oct 2022 04:26:16 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6xPiT4iuHDRJl31PJNxPBwp8AA0k2LX2nGPlsI24rhU7OhBZR2f7rDJNFyjawODQ/r1b59 X-Received: by 2002:a17:903:11c7:b0:178:af17:e93e with SMTP id q7-20020a17090311c700b00178af17e93emr7879240plh.78.1666178776366; Wed, 19 Oct 2022 04:26:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666178776; cv=none; d=google.com; s=arc-20160816; b=ZeW9MIgA9AgtxM1OKLntrcIRix6lyyjZhPfxkWdKXKmA33h2TjJLoOAHRGnR9aOWNM PfQOgmzQAC1OSKIVCKD8wT0xwkhru1z1vJMKJ37512WhKdzEAksEhH6QCpD0KyrosMD2 bzEyKp37c1W29LbsPF8hsnix7/Jfdeb8q1yE5zlnBhh7x3xdNtXpnTSkkJM3/zLCQOAj NU//41N4qbHYlWt4GwCNESot1MShUud/F77ALp+cMwsiXzkuFGDtL98AYgqW0fnKHFD2 wOPmbY42n8gAu26W/Ja83zXzbpAlaxx8kVSuFcmAxqfuB145yjZQv1e8ORUi/Mn/jAAx 18+w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Y0zyNmAYzT3ri+4nefmoVJ0xInwrkHd8fCwz/8mxmhE=; b=Nxb6V4IJPT8DIs5XN4s27oWhyAl4rJZerbfuhwMVVql61GhASkquxO3VzEuZxVUY08 gybPl4mdhEFghcEVCo5romuOfb883pFTfEngN0218eCYj9Je4BSVJcmPM/hQ4mwRy66S zrGoUpnVo2y3kVAKO5/j0ETJaYR5r+1sbXfQP/U6lS0b2BNH3kkxnVScVxPFvv+R8L7U cLIawflw7LueUV5wpTLAjbuahyVbXGkEk2FWys2/d4RPMtAHWYHlr6z1u5Mw03MX0Odb 12f/Ad1BYpN/W6kjWmfqBk1wMuUsi/etm24dQkZvJkJoAbtixpUVUHcL7OwKO1DP61yK oitA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=UQuPoghW; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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([172.25.112.68]) by orsmga005.jf.intel.com with ESMTP; 19 Oct 2022 03:46:21 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, brgerst@gmail.com, chang.seok.bae@intel.com Subject: [PATCH v4 3/5] x86/gsseg: make asm_load_gs_index() take an u16 Date: Wed, 19 Oct 2022 03:23:08 -0700 Message-Id: <20221019102310.1543-4-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221019102310.1543-1-xin3.li@intel.com> References: <20221019102310.1543-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747115076438700148?= X-GMAIL-MSGID: =?utf-8?q?1747115076438700148?= From: "H. Peter Anvin (Intel)" Let gcc know that only the low 16 bits of load_gs_index() argument actually matter. It might allow it to create slightly better code. However, do not propagate this into the prototypes of functions that end up being paravirtualized, to avoid unnecessary changes. Signed-off-by: H. Peter Anvin (Intel) Signed-off-by: Xin Li --- arch/x86/entry/entry_64.S | 2 +- arch/x86/include/asm/special_insns.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/entry/entry_64.S b/arch/x86/entry/entry_64.S index 9953d966d124..e0c48998d2fb 100644 --- a/arch/x86/entry/entry_64.S +++ b/arch/x86/entry/entry_64.S @@ -779,7 +779,7 @@ _ASM_NOKPROBE(common_interrupt_return) /* * Reload gs selector with exception handling - * edi: new selector + * di: new selector * * Is in entry.text as it shouldn't be instrumented. */ diff --git a/arch/x86/include/asm/special_insns.h b/arch/x86/include/asm/special_insns.h index 35f709f619fb..a71d0e8d4684 100644 --- a/arch/x86/include/asm/special_insns.h +++ b/arch/x86/include/asm/special_insns.h @@ -120,7 +120,7 @@ static inline void native_wbinvd(void) asm volatile("wbinvd": : :"memory"); } -extern asmlinkage void asm_load_gs_index(unsigned int selector); +extern asmlinkage void asm_load_gs_index(u16 selector); static inline void native_load_gs_index(unsigned int selector) { From patchwork Wed Oct 19 10:23:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Xin3" X-Patchwork-Id: 5238 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp267332wrs; Wed, 19 Oct 2022 04:26:58 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5uFSk15XD/h2Ls3tpHarSktOuL3lHov/E/NmFJd7LWUbUayxriaZ/UHu/vbYxiLL8En5Np X-Received: by 2002:a17:902:aa8b:b0:178:8f1d:6936 with SMTP id d11-20020a170902aa8b00b001788f1d6936mr7990197plr.168.1666178817865; Wed, 19 Oct 2022 04:26:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666178817; cv=none; d=google.com; s=arc-20160816; b=StQo3n/495xz3iFKLThnzSi35HU0h5FURPtOvji3gd6WxXbXyM6LAViV2QqZ4L/V4c 0G7deu2982vg4d07mIqcGSVyVCfAFj+Uyknf0tyTs8W+sRfFg0DeNXA0E63XLDnEjvPF V+RqrKXgNfde5Wq4UDHHS4Ot6O2FcNnohXwPaNA1k4VYUw3CWRGkhWgDn4OuqvhZO4j9 G2gksoOTge9a9xNhbDGZ8bHLh11qPWl+1DVkzvxZRj5dib37hCD+W6+EPepU4+WqpsXt 1KwAe42mJvWA2Q3i49JyrxC2h9Q+hxJqz1jjUa0D/V7Lz5Vp08CZpO46F1aEChbc+ciB ihQw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=B1/bKgLO1zn8qG0TcKZhJiT7VIXXp1YNTY7nenPzEwk=; b=VqPUU2oxQnNNF5bK0I+iI3bxQl9GPhzNfADmuBj+xB9vsVJZ13y0dhi99EhKgyblTN YyBI4DVdgWnd7sdGPCLELpuEKMXsF5CJ1os9vpwigjvceVt3mkV3docMtLTKOi+UZ4ej yrMFAeDIT1N9r6RnH6bLnnkyqfq5VHKImqyV8xSI4k0Popae7LcKcvrWVlGT1stivjWR daxX6OjJmQYgzSx0l3WmQ+KbnOeqWhCIHZ9HemsZprx93Px/r2LG8Zd48SOhnU+2pDK8 Qk2J4CKUWCXkZSWEY2j5PsR5Abcn76uRBNA6VMfYOo7ie5Vopj+suv+8vbnMvNVA8N7O KDyg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=XwYLXZkp; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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([172.25.112.68]) by orsmga005.jf.intel.com with ESMTP; 19 Oct 2022 03:46:21 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, brgerst@gmail.com, chang.seok.bae@intel.com Subject: [PATCH v4 4/5] x86/gsseg: move load_gs_index() to its own new header file Date: Wed, 19 Oct 2022 03:23:09 -0700 Message-Id: <20221019102310.1543-5-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221019102310.1543-1-xin3.li@intel.com> References: <20221019102310.1543-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747115120150961451?= X-GMAIL-MSGID: =?utf-8?q?1747115120150961451?= From: "H. Peter Anvin (Intel)" GS is a special segment on x86_64, move load_gs_index() to its own new header file. Signed-off-by: H. Peter Anvin (Intel) Signed-off-by: Xin Li --- arch/x86/ia32/ia32_signal.c | 1 + arch/x86/include/asm/gsseg.h | 41 ++++++++++++++++++++++++++++ arch/x86/include/asm/mmu_context.h | 1 + arch/x86/include/asm/special_insns.h | 21 -------------- arch/x86/kernel/paravirt.c | 1 + arch/x86/kernel/tls.c | 1 + 6 files changed, 45 insertions(+), 21 deletions(-) create mode 100644 arch/x86/include/asm/gsseg.h diff --git a/arch/x86/ia32/ia32_signal.c b/arch/x86/ia32/ia32_signal.c index c9c3859322fa..14c739303099 100644 --- a/arch/x86/ia32/ia32_signal.c +++ b/arch/x86/ia32/ia32_signal.c @@ -34,6 +34,7 @@ #include #include #include +#include static inline void reload_segments(struct sigcontext_32 *sc) { diff --git a/arch/x86/include/asm/gsseg.h b/arch/x86/include/asm/gsseg.h new file mode 100644 index 000000000000..d15577c39e8d --- /dev/null +++ b/arch/x86/include/asm/gsseg.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef _ASM_X86_GSSEG_H +#define _ASM_X86_GSSEG_H + +#include + +#include +#include +#include +#include +#include + +#ifdef CONFIG_X86_64 + +extern asmlinkage void asm_load_gs_index(u16 selector); + +static inline void native_load_gs_index(unsigned int selector) +{ + unsigned long flags; + + local_irq_save(flags); + asm_load_gs_index(selector); + local_irq_restore(flags); +} + +#endif /* CONFIG_X86_64 */ + +#ifndef CONFIG_PARAVIRT_XXL + +static inline void load_gs_index(unsigned int selector) +{ +#ifdef CONFIG_X86_64 + native_load_gs_index(selector); +#else + loadsegment(gs, selector); +#endif +} + +#endif /* CONFIG_PARAVIRT_XXL */ + +#endif /* _ASM_X86_GSSEG_H */ diff --git a/arch/x86/include/asm/mmu_context.h b/arch/x86/include/asm/mmu_context.h index b8d40ddeab00..e01aa74a6de7 100644 --- a/arch/x86/include/asm/mmu_context.h +++ b/arch/x86/include/asm/mmu_context.h @@ -12,6 +12,7 @@ #include #include #include +#include extern atomic64_t last_mm_ctx_id; diff --git a/arch/x86/include/asm/special_insns.h b/arch/x86/include/asm/special_insns.h index a71d0e8d4684..cfd9499b617c 100644 --- a/arch/x86/include/asm/special_insns.h +++ b/arch/x86/include/asm/special_insns.h @@ -120,17 +120,6 @@ static inline void native_wbinvd(void) asm volatile("wbinvd": : :"memory"); } -extern asmlinkage void asm_load_gs_index(u16 selector); - -static inline void native_load_gs_index(unsigned int selector) -{ - unsigned long flags; - - local_irq_save(flags); - asm_load_gs_index(selector); - local_irq_restore(flags); -} - static inline unsigned long __read_cr4(void) { return native_read_cr4(); @@ -184,16 +173,6 @@ static inline void wbinvd(void) native_wbinvd(); } - -static inline void load_gs_index(unsigned int selector) -{ -#ifdef CONFIG_X86_64 - native_load_gs_index(selector); -#else - loadsegment(gs, selector); -#endif -} - #endif /* CONFIG_PARAVIRT_XXL */ static inline void clflush(volatile void *__p) diff --git a/arch/x86/kernel/paravirt.c b/arch/x86/kernel/paravirt.c index 7ca2d46c08cc..00f6a92551d2 100644 --- a/arch/x86/kernel/paravirt.c +++ b/arch/x86/kernel/paravirt.c @@ -32,6 +32,7 @@ #include #include #include +#include /* * nop stub, which must not clobber anything *including the stack* to diff --git a/arch/x86/kernel/tls.c b/arch/x86/kernel/tls.c index 3c883e064242..3ffbab0081f4 100644 --- a/arch/x86/kernel/tls.c +++ b/arch/x86/kernel/tls.c @@ -12,6 +12,7 @@ #include #include #include +#include #include "tls.h" From patchwork Wed Oct 19 10:23:10 2022 Content-Type: text/plain; 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([172.25.112.68]) by orsmga005.jf.intel.com with ESMTP; 19 Oct 2022 03:46:22 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, brgerst@gmail.com, chang.seok.bae@intel.com Subject: [PATCH v4 5/5] x86/gsseg: use the LKGS instruction if available for load_gs_index() Date: Wed, 19 Oct 2022 03:23:10 -0700 Message-Id: <20221019102310.1543-6-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221019102310.1543-1-xin3.li@intel.com> References: <20221019102310.1543-1-xin3.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747115023716424767?= X-GMAIL-MSGID: =?utf-8?q?1747115023716424767?= From: "H. Peter Anvin (Intel)" The LKGS instruction atomically loads a segment descriptor into the %gs descriptor registers, *except* that %gs.base is unchanged, and the base is instead loaded into MSR_IA32_KERNEL_GS_BASE, which is exactly what we want this function to do. Signed-off-by: H. Peter Anvin (Intel) Signed-off-by: Peter Zijlstra (Intel) Signed-off-by: Brian Gerst Signed-off-by: Xin Li --- Changes since v3: * We want less ASM not more, thus keep local_irq_save/restore() inside native_load_gs_index() (Thomas Gleixner). * For paravirt enabled kernels, initialize pv_ops.cpu.load_gs_index to native_lkgs (Thomas Gleixner). Changes since V2: * Mark DI as input and output (+D) as in V1, since the exception handler modifies it (Brian Gerst). Changes since V1: * Use EX_TYPE_ZERO_REG instead of fixup code in the obsolete .fixup code section (Peter Zijlstra). * Add a comment that states the LKGS_DI macro will be repalced with "lkgs %di" once the binutils support the LKGS instruction (Peter Zijlstra). --- arch/x86/include/asm/gsseg.h | 33 +++++++++++++++++++++++++++++---- arch/x86/kernel/cpu/common.c | 1 + 2 files changed, 30 insertions(+), 4 deletions(-) diff --git a/arch/x86/include/asm/gsseg.h b/arch/x86/include/asm/gsseg.h index d15577c39e8d..ab6a595cea70 100644 --- a/arch/x86/include/asm/gsseg.h +++ b/arch/x86/include/asm/gsseg.h @@ -14,17 +14,42 @@ extern asmlinkage void asm_load_gs_index(u16 selector); +/* Replace with "lkgs %di" once binutils support LKGS instruction */ +#define LKGS_DI _ASM_BYTES(0xf2,0x0f,0x00,0xf7) + +static inline void native_lkgs(unsigned int selector) +{ + u16 sel = selector; + asm_inline volatile("1: " LKGS_DI + _ASM_EXTABLE_TYPE_REG(1b, 1b, EX_TYPE_ZERO_REG, %k[sel]) + : [sel] "+D" (sel)); +} + static inline void native_load_gs_index(unsigned int selector) { - unsigned long flags; + if (cpu_feature_enabled(X86_FEATURE_LKGS)) { + native_lkgs(selector); + } else { + unsigned long flags; - local_irq_save(flags); - asm_load_gs_index(selector); - local_irq_restore(flags); + local_irq_save(flags); + asm_load_gs_index(selector); + local_irq_restore(flags); + } } #endif /* CONFIG_X86_64 */ +static inline void __init lkgs_init(void) +{ +#ifdef CONFIG_PARAVIRT_XXL +#ifdef CONFIG_X86_64 + if (cpu_feature_enabled(X86_FEATURE_LKGS)) + pv_ops.cpu.load_gs_index = native_lkgs; +#endif +#endif +} + #ifndef CONFIG_PARAVIRT_XXL static inline void load_gs_index(unsigned int selector) diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 3e508f239098..d6eb4f60b47d 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1939,6 +1939,7 @@ void __init identify_boot_cpu(void) setup_cr_pinning(); tsx_init(); + lkgs_init(); } void identify_secondary_cpu(struct cpuinfo_x86 *c)