From patchwork Mon Mar 13 09:05:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "juzhe.zhong@rivai.ai" X-Patchwork-Id: 68697 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp1075098wrd; Mon, 13 Mar 2023 02:06:39 -0700 (PDT) X-Google-Smtp-Source: AK7set/kMKSGHl2qcb7aDztMiUog5BfSaMmoLlp/o5g3EDWhMu8QzWLqzRhAVrqUbdjDVtbu/FtQ X-Received: by 2002:aa7:d688:0:b0:4fc:7201:6e2 with SMTP id d8-20020aa7d688000000b004fc720106e2mr2483737edr.34.1678698399166; Mon, 13 Mar 2023 02:06:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1678698399; cv=none; d=google.com; s=arc-20160816; b=uD3gOOs1bJnRc0Uk/1fTXKnvvMXsIeSbXGGMSMQrrmIsWoehDHtZWw/WVdA6Ygxb87 kwkZ6ZN+dokhlHumpBoFcK+l8heGEeRQf/O7cJSestZhobJF7UCeL8pzEUghv9Ad7Vq7 fu7WfsIOi2cS2PF7rl5AQ21ps4t6P0aYCmuubw38sxfbK8HgCch7Eg5EaFnKPGj76YB9 DizhN3VtS6pw4/k8rgPnxxQMcVh/90xEuMDN0bOeax8Cd2GNF4q97uOgUHhzPxZXHOrO TU+IDFsnkw/Pr0QX2nD2oPn4VyPLukB15Sx9Zvk8ml2UxxOKcTx+WI4h2fNyCQ1ktebl CtUQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:feedback-id :content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:dmarc-filter:delivered-to; bh=d4llUofPc911bDXFxY/O6Y2O4xCU/J7OsdB3W3r7hzw=; b=qsiGnPNYcDvo5OGT27k/5haAlgY3zGTxLu3U0T0USwMeOVRILrs89e+ZF518ZIfjFd 32qo31P9XG7WGCKGXzDigv81F2jDhi0DV6HIzgkd70AG6GtgulbWiWal+2zwkNm3G+17 9Cn/aZygKToIvqY8nbUMtSqmK0jLPFTlhqzbkITbEZxjpaR/IrhwKdNN1fbiBh9BPJGx Beg0lT4b4RQeCARJAnCC1r2isM7pP/UzrD/IXssFBBCsYEw6sDc1f63RslrBR/uGY9hy lXDpNdQ2WPO2wjSXFMFh1YhCjweuPyDLxwwFGyjlYrPFOxvT+W1uHi5KDQ8TUMPBSi66 qXNg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id a21-20020aa7d915000000b004acbebbb1c1si7275533edr.262.2023.03.13.02.06.38 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Mar 2023 02:06:39 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 19A833858C2D for ; Mon, 13 Mar 2023 09:06:19 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbg153.qq.com (smtpbg153.qq.com [13.245.218.24]) by sourceware.org (Postfix) with ESMTPS id 562883858436 for ; Mon, 13 Mar 2023 09:05:49 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 562883858436 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp77t1678698342tvjo10u0 Received: from rios-cad5.localdomain ( [58.60.1.11]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 13 Mar 2023 17:05:41 +0800 (CST) X-QQ-SSF: 01400000000000E0N000000A0000000 X-QQ-FEAT: CR3LFp2JE4kkkmTSoMmuGj1m1HVIllTZCfGxcYBYlR1k/Tsr7VKzZzojwnHOm CM0ZLvQzSsEB5dXc57jgbQMi/A7XGil9uapdvSAUvCQE4oq/7QESIC8+IEsVdnBWQFTSg/U zkoHi7AVyhnHOqTVOWrAVkWltTr1g/flFx2epX3pm5lS6uZdwZSR1P5jch5Hbct6RkWBC/f TKr5QRsZl6XVAsdbnSaDyXTrobKltGlc6+BPn4Izrxq/4yde6GAQHGrMypEuGWo1TklgLAo XxMUFOKWjFTVlzhEON4TeX+RBQ7L72hZ4p8l9ycYZ8NGq/v77LnqJszAhCgXOvYz1D9Pzxh MrkMO91hpI8cX1wwHgcuhd2o3bG2ESrQPDuWs/gjgl7JICHKMjEhH/fPIT2izOFw+yKUp8L SmhwtKvrH5lH80DXDSAsDg== X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Refine reduction RA constraint according to RVV ISA Date: Mon, 13 Mar 2023 17:05:40 +0800 Message-Id: <20230313090540.335536-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-12.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1760242852599766866?= X-GMAIL-MSGID: =?utf-8?q?1760242852599766866?= From: Ju-Zhe Zhong According to RVV ISA: 14. Vector Reduction Operations "The destination vector register can overlap the source operands, including the mask register." gcc/ChangeLog: * config/riscv/vector.md: Refine RA constraint. --- gcc/config/riscv/vector.md | 96 +++++++++++++++++++------------------- 1 file changed, 48 insertions(+), 48 deletions(-) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 4ea74372de5..75336b1a515 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -6259,44 +6259,44 @@ ;; For example, The LMUL = 1 corresponding mode of VNx16QImode is VNx4QImode ;; for -march=rv*zve32* wheras VNx8QImode for -march=rv*zve64* (define_insn "@pred_reduc_" - [(set (match_operand: 0 "register_operand" "=vd, vd, vr, vr") + [(set (match_operand: 0 "register_operand" "=vr, vr") (unspec: [(unspec: - [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1,Wc1") - (match_operand 5 "vector_length_operand" " rK, rK, rK, rK") - (match_operand 6 "const_int_operand" " i, i, i, i") - (match_operand 7 "const_int_operand" " i, i, i, i") + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 5 "vector_length_operand" " rK, rK") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (any_reduc:VI (vec_duplicate:VI (vec_select: - (match_operand: 4 "register_operand" " vr, vr, vr, vr") + (match_operand: 4 "register_operand" " vr, vr") (parallel [(const_int 0)]))) - (match_operand:VI 3 "register_operand" " vr, vr, vr, vr")) - (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0")] UNSPEC_REDUC))] + (match_operand:VI 3 "register_operand" " vr, vr")) + (match_operand: 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))] "TARGET_VECTOR && TARGET_MIN_VLEN > 32" "vred.vs\t%0,%3,%4%p1" [(set_attr "type" "vired") (set_attr "mode" "")]) (define_insn "@pred_reduc_" - [(set (match_operand: 0 "register_operand" "=vd, vd, vr, vr") + [(set (match_operand: 0 "register_operand" "=vr, vr") (unspec: [(unspec: - [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1,Wc1") - (match_operand 5 "vector_length_operand" " rK, rK, rK, rK") - (match_operand 6 "const_int_operand" " i, i, i, i") - (match_operand 7 "const_int_operand" " i, i, i, i") + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 5 "vector_length_operand" " rK, rK") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (any_reduc:VI_ZVE32 (vec_duplicate:VI_ZVE32 (vec_select: - (match_operand: 4 "register_operand" " vr, vr, vr, vr") + (match_operand: 4 "register_operand" " vr, vr") (parallel [(const_int 0)]))) - (match_operand:VI_ZVE32 3 "register_operand" " vr, vr, vr, vr")) - (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0")] UNSPEC_REDUC))] + (match_operand:VI_ZVE32 3 "register_operand" " vr, vr")) + (match_operand: 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))] "TARGET_VECTOR && TARGET_MIN_VLEN == 32" "vred.vs\t%0,%3,%4%p1" [(set_attr "type" "vired") @@ -6339,90 +6339,90 @@ (set_attr "mode" "")]) (define_insn "@pred_reduc_" - [(set (match_operand: 0 "register_operand" "=vd, vd, vr, vr") + [(set (match_operand: 0 "register_operand" "=vr, vr") (unspec: [(unspec: - [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1,Wc1") - (match_operand 5 "vector_length_operand" " rK, rK, rK, rK") - (match_operand 6 "const_int_operand" " i, i, i, i") - (match_operand 7 "const_int_operand" " i, i, i, i") + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 5 "vector_length_operand" " rK, rK") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (any_freduc:VF (vec_duplicate:VF (vec_select: - (match_operand: 4 "register_operand" " vr, vr, vr, vr") + (match_operand: 4 "register_operand" " vr, vr") (parallel [(const_int 0)]))) - (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")) - (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0")] UNSPEC_REDUC))] + (match_operand:VF 3 "register_operand" " vr, vr")) + (match_operand: 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))] "TARGET_VECTOR && TARGET_MIN_VLEN > 32" "vfred.vs\t%0,%3,%4%p1" [(set_attr "type" "vfredu") (set_attr "mode" "")]) (define_insn "@pred_reduc_" - [(set (match_operand: 0 "register_operand" "=vd, vd, vr, vr") + [(set (match_operand: 0 "register_operand" "=vr, vr") (unspec: [(unspec: - [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1,Wc1") - (match_operand 5 "vector_length_operand" " rK, rK, rK, rK") - (match_operand 6 "const_int_operand" " i, i, i, i") - (match_operand 7 "const_int_operand" " i, i, i, i") + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 5 "vector_length_operand" " rK, rK") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (any_freduc:VF_ZVE32 (vec_duplicate:VF_ZVE32 (vec_select: - (match_operand: 4 "register_operand" " vr, vr, vr, vr") + (match_operand: 4 "register_operand" " vr, vr") (parallel [(const_int 0)]))) - (match_operand:VF_ZVE32 3 "register_operand" " vr, vr, vr, vr")) - (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0")] UNSPEC_REDUC))] + (match_operand:VF_ZVE32 3 "register_operand" " vr, vr")) + (match_operand: 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))] "TARGET_VECTOR && TARGET_MIN_VLEN == 32" "vfred.vs\t%0,%3,%4%p1" [(set_attr "type" "vfredu") (set_attr "mode" "")]) (define_insn "@pred_reduc_plus" - [(set (match_operand: 0 "register_operand" "=vd, vd, vr, vr") + [(set (match_operand: 0 "register_operand" "=vr, vr") (unspec: [(unspec: [(unspec: - [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1,Wc1") - (match_operand 5 "vector_length_operand" " rK, rK, rK, rK") - (match_operand 6 "const_int_operand" " i, i, i, i") - (match_operand 7 "const_int_operand" " i, i, i, i") + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 5 "vector_length_operand" " rK, rK") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (plus:VF (vec_duplicate:VF (vec_select: - (match_operand: 4 "register_operand" " vr, vr, vr, vr") + (match_operand: 4 "register_operand" " vr, vr") (parallel [(const_int 0)]))) - (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")) - (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0")] UNSPEC_REDUC)] ORDER))] + (match_operand:VF 3 "register_operand" " vr, vr")) + (match_operand: 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC)] ORDER))] "TARGET_VECTOR && TARGET_MIN_VLEN > 32" "vfredsum.vs\t%0,%3,%4%p1" [(set_attr "type" "vfred") (set_attr "mode" "")]) (define_insn "@pred_reduc_plus" - [(set (match_operand: 0 "register_operand" "=vd, vd, vr, vr") + [(set (match_operand: 0 "register_operand" "=vr, vr") (unspec: [(unspec: [(unspec: - [(match_operand: 1 "vector_mask_operand" " vm, vm,Wc1,Wc1") - (match_operand 5 "vector_length_operand" " rK, rK, rK, rK") - (match_operand 6 "const_int_operand" " i, i, i, i") - (match_operand 7 "const_int_operand" " i, i, i, i") + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 5 "vector_length_operand" " rK, rK") + (match_operand 6 "const_int_operand" " i, i") + (match_operand 7 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (plus:VF_ZVE32 (vec_duplicate:VF_ZVE32 (vec_select: - (match_operand: 4 "register_operand" " vr, vr, vr, vr") + (match_operand: 4 "register_operand" " vr, vr") (parallel [(const_int 0)]))) - (match_operand:VF_ZVE32 3 "register_operand" " vr, vr, vr, vr")) - (match_operand: 2 "vector_merge_operand" " vu, 0, vu, 0")] UNSPEC_REDUC)] ORDER))] + (match_operand:VF_ZVE32 3 "register_operand" " vr, vr")) + (match_operand: 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC)] ORDER))] "TARGET_VECTOR && TARGET_MIN_VLEN == 32" "vfredsum.vs\t%0,%3,%4%p1" [(set_attr "type" "vfred")