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Mon, 13 Mar 2023 08:02:06 +0000 (GMT) From: Thomas Richter To: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, acme@kernel.org, sumanthk@linux.ibm.com Cc: svens@linux.ibm.com, gor@linux.ibm.com, hca@linux.ibm.com, Thomas Richter Subject: [PATCH 1/6] tools/perf/json: Add common metrics for s390 Date: Mon, 13 Mar 2023 09:01:56 +0100 Message-Id: <20230313080201.2440201-1-tmricht@linux.ibm.com> X-Mailer: git-send-email 2.37.2 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: l3efZP7XxXzcOHKReJtlnggfpeZEis1L X-Proofpoint-ORIG-GUID: l3efZP7XxXzcOHKReJtlnggfpeZEis1L X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-12_10,2023-03-10_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 bulkscore=0 malwarescore=0 suspectscore=0 priorityscore=1501 mlxscore=0 clxscore=1015 lowpriorityscore=0 mlxlogscore=999 phishscore=0 spamscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2303130065 X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1760239900909087673?= X-GMAIL-MSGID: =?utf-8?q?1760239900909087673?= Add 3 metrics for s390 machines: - Cycles per instruction: Amount of CPU cycles used per instructions, named cpi. - Problem state ratio: Ratio of instructions executed in problem state compared to total number of instructions, named prbstate. - Level one instruction and data cache misses per 100 instructions, named l1mp. For details about the formulas see this documentation: https://www.ibm.com/support/pages/system/files/inline-files/CPU%20MF%20Formulas%20including%20z16%20-%20May%202022_1.pdf Outpuf after: # ./perf stat -M cpi -- dd if=/dev/zero of=/dev/null bs=1M count=10K 10240+0 records in 10240+0 records out 10737418240 bytes (11 GB, 10 GiB) copied, 1.30151 s, 8.2 GB/s Performance counter stats for 'dd if=/dev/zero of=/dev/null .....': 6,779,778,802 CPU_CYCLES # 1.96 cpi 3,461,975,090 INSTRUCTIONS 1.306873021 seconds time elapsed 0.001034000 seconds user 1.305677000 seconds sys # Signed-off-by: Thomas Richter Acked-By: Sumanth Korikkar Acked-by: Ian Rogers --- .../pmu-events/arch/s390/cf_z13/transaction.json | 15 +++++++++++++++ .../pmu-events/arch/s390/cf_z14/transaction.json | 15 +++++++++++++++ .../pmu-events/arch/s390/cf_z15/transaction.json | 15 +++++++++++++++ .../pmu-events/arch/s390/cf_z16/transaction.json | 15 +++++++++++++++ 4 files changed, 60 insertions(+) diff --git a/tools/perf/pmu-events/arch/s390/cf_z13/transaction.json b/tools/perf/pmu-events/arch/s390/cf_z13/transaction.json index 1a0034f79f73..86bf83b4504e 100644 --- a/tools/perf/pmu-events/arch/s390/cf_z13/transaction.json +++ b/tools/perf/pmu-events/arch/s390/cf_z13/transaction.json @@ -3,5 +3,20 @@ "BriefDescription": "Transaction count", "MetricName": "transaction", "MetricExpr": "TX_C_TEND + TX_NC_TEND + TX_NC_TABORT + TX_C_TABORT_SPECIAL + TX_C_TABORT_NO_SPECIAL" + }, + { + "BriefDescription": "Cycles per Instruction", + "MetricName": "cpi", + "MetricExpr": "CPU_CYCLES / INSTRUCTIONS" + }, + { + "BriefDescription": "Problem State Instruction Ratio", + "MetricName": "prbstate", + "MetricExpr": "(PROBLEM_STATE_INSTRUCTIONS / INSTRUCTIONS) * 100" + }, + { + "BriefDescription": "Level One Miss per 100 Instructions", + "MetricName": "l1mp", + "MetricExpr": "((L1I_DIR_WRITES + L1D_DIR_WRITES) / INSTRUCTIONS) * 100" } ] diff --git a/tools/perf/pmu-events/arch/s390/cf_z14/transaction.json b/tools/perf/pmu-events/arch/s390/cf_z14/transaction.json index 1a0034f79f73..86bf83b4504e 100644 --- a/tools/perf/pmu-events/arch/s390/cf_z14/transaction.json +++ b/tools/perf/pmu-events/arch/s390/cf_z14/transaction.json @@ -3,5 +3,20 @@ "BriefDescription": "Transaction count", "MetricName": "transaction", "MetricExpr": "TX_C_TEND + TX_NC_TEND + TX_NC_TABORT + TX_C_TABORT_SPECIAL + TX_C_TABORT_NO_SPECIAL" + }, + { + "BriefDescription": "Cycles per Instruction", + "MetricName": "cpi", + "MetricExpr": "CPU_CYCLES / INSTRUCTIONS" + }, + { + "BriefDescription": "Problem State Instruction Ratio", + "MetricName": "prbstate", + "MetricExpr": "(PROBLEM_STATE_INSTRUCTIONS / INSTRUCTIONS) * 100" + }, + { + "BriefDescription": "Level One Miss per 100 Instructions", + "MetricName": "l1mp", + "MetricExpr": "((L1I_DIR_WRITES + L1D_DIR_WRITES) / INSTRUCTIONS) * 100" } ] diff --git a/tools/perf/pmu-events/arch/s390/cf_z15/transaction.json b/tools/perf/pmu-events/arch/s390/cf_z15/transaction.json index 1a0034f79f73..86bf83b4504e 100644 --- a/tools/perf/pmu-events/arch/s390/cf_z15/transaction.json +++ b/tools/perf/pmu-events/arch/s390/cf_z15/transaction.json @@ -3,5 +3,20 @@ "BriefDescription": "Transaction count", "MetricName": "transaction", "MetricExpr": "TX_C_TEND + TX_NC_TEND + TX_NC_TABORT + TX_C_TABORT_SPECIAL + TX_C_TABORT_NO_SPECIAL" + }, + { + "BriefDescription": "Cycles per Instruction", + "MetricName": "cpi", + "MetricExpr": "CPU_CYCLES / INSTRUCTIONS" + }, + { + "BriefDescription": "Problem State Instruction Ratio", + "MetricName": "prbstate", + "MetricExpr": "(PROBLEM_STATE_INSTRUCTIONS / INSTRUCTIONS) * 100" + }, + { + "BriefDescription": "Level One Miss per 100 Instructions", + "MetricName": "l1mp", + "MetricExpr": "((L1I_DIR_WRITES + L1D_DIR_WRITES) / INSTRUCTIONS) * 100" } ] diff --git a/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json b/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json index 1a0034f79f73..86bf83b4504e 100644 --- a/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json +++ b/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json @@ -3,5 +3,20 @@ "BriefDescription": "Transaction count", "MetricName": "transaction", "MetricExpr": "TX_C_TEND + TX_NC_TEND + TX_NC_TABORT + TX_C_TABORT_SPECIAL + TX_C_TABORT_NO_SPECIAL" + }, + { + "BriefDescription": "Cycles per Instruction", + "MetricName": "cpi", + "MetricExpr": "CPU_CYCLES / INSTRUCTIONS" + }, + { + "BriefDescription": "Problem State Instruction Ratio", + "MetricName": "prbstate", + "MetricExpr": "(PROBLEM_STATE_INSTRUCTIONS / INSTRUCTIONS) * 100" + }, + { + "BriefDescription": "Level One Miss per 100 Instructions", + "MetricName": "l1mp", + "MetricExpr": "((L1I_DIR_WRITES + L1D_DIR_WRITES) / INSTRUCTIONS) * 100" } ] From patchwork Mon Mar 13 08:01:57 2023 Content-Type: text/plain; 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IMSVA (Postfix) with ESMTP id D27D82052D; Mon, 13 Mar 2023 08:02:08 +0000 (GMT) Received: from smtpav05.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 94BF72052A; Mon, 13 Mar 2023 08:02:08 +0000 (GMT) Received: from tuxmaker.boeblingen.de.ibm.com (unknown [9.152.85.9]) by smtpav05.fra02v.mail.ibm.com (Postfix) with ESMTP; Mon, 13 Mar 2023 08:02:08 +0000 (GMT) From: Thomas Richter To: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, acme@kernel.org, sumanthk@linux.ibm.com Cc: svens@linux.ibm.com, gor@linux.ibm.com, hca@linux.ibm.com, Thomas Richter Subject: [PATCH 2/6] tools/perf/json: Add cache metrics for s390 z16 Date: Mon, 13 Mar 2023 09:01:57 +0100 Message-Id: <20230313080201.2440201-2-tmricht@linux.ibm.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230313080201.2440201-1-tmricht@linux.ibm.com> References: <20230313080201.2440201-1-tmricht@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-GUID: li-TVPCnnInWhQ01U3kFCCV1xStTjp0a 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=?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1760241627178150274?= X-GMAIL-MSGID: =?utf-8?q?1760241627178150274?= Add metrics for s390 z16 - Percentage sourced from Level 2 cache - Percentage sourced from Level 3 on same chip cache - Percentage sourced from Level 4 Local cache on same book - Percentage sourced from Level 4 Remote cache on different book - Percentage sourced from memory For details about the formulas see this documentation: https://www.ibm.com/support/pages/system/files/inline-files/CPU%20MF%20Formulas%20including%20z16%20-%20May%202022_1.pdf Outpuf after: # ./perf stat -M l4rp -- dd if=/dev/zero of=/dev/null bs=10M count=10K .... dd output deleted Performance counter stats for 'dd if=/dev/zero of=/dev/null bs=10M count=10K': 0 IDCW_OFF_DRAWER_CHIP_HIT # 0.00 l4rp 431,866 L1I_DIR_WRITES 2,395 IDCW_OFF_DRAWER_IV 0 ICW_OFF_DRAWER 0 IDCW_OFF_DRAWER_DRAWER_HIT 1,437 DCW_OFF_DRAWER 425,960,793 L1D_DIR_WRITES 12.165030699 seconds time elapsed 0.001037000 seconds user 12.162140000 seconds sys # Signed-off-by: Thomas Richter Acked-By: Sumanth Korikkar Acked-by: Ian Rogers Acked-by: Ian Rogers --- .../arch/s390/cf_z16/transaction.json | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json b/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json index 86bf83b4504e..dde0735a7d22 100644 --- a/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json +++ b/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json @@ -18,5 +18,30 @@ "BriefDescription": "Level One Miss per 100 Instructions", "MetricName": "l1mp", "MetricExpr": "((L1I_DIR_WRITES + L1D_DIR_WRITES) / INSTRUCTIONS) * 100" + }, + { + "BriefDescription": "Percentage sourced from Level 2 cache", + "MetricName": "l2p", + "MetricExpr": "((DCW_REQ + DCW_REQ_IV + ICW_REQ + ICW_REQ_IV) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" + }, + { + "BriefDescription": "Percentage sourced from Level 3 on same chip cache", + "MetricName": "l3p", + "MetricExpr": "((DCW_REQ_CHIP_HIT + DCW_ON_CHIP + DCW_ON_CHIP_IV + DCW_ON_CHIP_CHIP_HIT + ICW_REQ_CHIP_HIT + ICW_ON_CHIP + ICW_ON_CHIP_IV + ICW_ON_CHIP_CHIP_HIT) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" + }, + { + "BriefDescription": "Percentage sourced from Level 4 Local cache on same book", + "MetricName": "l4lp", + "MetricExpr": "((DCW_REQ_DRAWER_HIT + DCW_ON_CHIP_DRAWER_HIT + DCW_ON_MODULE + DCW_ON_DRAWER + IDCW_ON_MODULE_IV + IDCW_ON_MODULE_CHIP_HIT + IDCW_ON_MODULE_DRAWER_HIT + IDCW_ON_DRAWER_IV + IDCW_ON_DRAWER_CHIP_HIT + IDCW_ON_DRAWER_DRAWER_HIT + ICW_REQ_DRAWER_HIT + ICW_ON_CHIP_DRAWER_HIT + ICW_ON_MODULE + ICW_ON_DRAWER) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" + }, + { + "BriefDescription": "Percentage sourced from Level 4 Remote cache on different book", + "MetricName": "l4rp", + "MetricExpr": "((DCW_OFF_DRAWER + IDCW_OFF_DRAWER_IV + IDCW_OFF_DRAWER_CHIP_HIT + IDCW_OFF_DRAWER_DRAWER_HIT + ICW_OFF_DRAWER) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" + }, + { + "BriefDescription": "Percentage sourced from memory", + "MetricName": "memp", + "MetricExpr": "((DCW_ON_CHIP_MEMORY + DCW_ON_MODULE_MEMORY + DCW_ON_DRAWER_MEMORY + DCW_OFF_DRAWER_MEMORY + ICW_ON_CHIP_MEMORY + ICW_ON_MODULE_MEMORY + ICW_ON_DRAWER_MEMORY + ICW_OFF_DRAWER_MEMORY) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" } ] From patchwork Mon Mar 13 08:01:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Richter X-Patchwork-Id: 68687 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp1069091wrd; Mon, 13 Mar 2023 01:47:12 -0700 (PDT) X-Google-Smtp-Source: AK7set/nq1oXYKpbTEzkkW7o3rpVSrlegubBckLg08ekyHZyGhqNlJTHFqIq+zjl8A+g2yCA4BWf X-Received: by 2002:a05:6a20:4422:b0:cd:bd86:318e with SMTP id ce34-20020a056a20442200b000cdbd86318emr43519449pzb.26.1678697232319; Mon, 13 Mar 2023 01:47:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1678697232; cv=none; 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id 2E67D2053F; Mon, 13 Mar 2023 08:02:10 +0000 (GMT) Received: from smtpav05.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id E436F20534; Mon, 13 Mar 2023 08:02:09 +0000 (GMT) Received: from tuxmaker.boeblingen.de.ibm.com (unknown [9.152.85.9]) by smtpav05.fra02v.mail.ibm.com (Postfix) with ESMTP; Mon, 13 Mar 2023 08:02:09 +0000 (GMT) From: Thomas Richter To: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, acme@kernel.org, sumanthk@linux.ibm.com Cc: svens@linux.ibm.com, gor@linux.ibm.com, hca@linux.ibm.com, Thomas Richter Subject: [PATCH 3/6] tools/perf/json: Add cache metrics for s390 z15 Date: Mon, 13 Mar 2023 09:01:58 +0100 Message-Id: <20230313080201.2440201-3-tmricht@linux.ibm.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230313080201.2440201-1-tmricht@linux.ibm.com> References: <20230313080201.2440201-1-tmricht@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-GUID: xA_juDxz_0SYpn1aVeZj86sAtV8UsHTq X-Proofpoint-ORIG-GUID: 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=?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1760241628708454209?= X-GMAIL-MSGID: =?utf-8?q?1760241628708454209?= Add metrics for s390 z15 - Percentage sourced from Level 2 cache - Percentage sourced from Level 3 on same chip cache - Percentage sourced from Level 4 Local cache on same book - Percentage sourced from Level 4 Remote cache on different book - Percentage sourced from memory For details about the formulas see this documentation: https://www.ibm.com/support/pages/system/files/inline-files/CPU%20MF%20Formulas%20including%20z16%20-%20May%202022_1.pdf Outpuf after: # ./perf stat -M l4rp -- find / .... find output deleted Performance counter stats for 'find /': 5 L1I_OFFDRAWER_L4_SOURCED_WRITES # 0.01 l4rp 187 L1D_OFFDRAWER_L4_SOURCED_WRITES 0 L1I_OFFDRAWER_L3_SOURCED_WRITES 231,333,165 L1I_DIR_WRITES 3,303 L1D_OFFDRAWER_L3_SOURCED_WRITES 47,461 L1D_OFFDRAWER_L3_SOURCED_WRITES_IV 0 L1I_OFFDRAWER_L3_SOURCED_WRITES_IV 126,706,244 L1D_DIR_WRITES 27.870355461 seconds time elapsed 0.521562000 seconds user 12.494503000 seconds sys # Signed-off-by: Thomas Richter Acked-By: Sumanth Korikkar --- .../arch/s390/cf_z15/transaction.json | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/tools/perf/pmu-events/arch/s390/cf_z15/transaction.json b/tools/perf/pmu-events/arch/s390/cf_z15/transaction.json index 86bf83b4504e..cca237bdb7ba 100644 --- a/tools/perf/pmu-events/arch/s390/cf_z15/transaction.json +++ b/tools/perf/pmu-events/arch/s390/cf_z15/transaction.json @@ -18,5 +18,30 @@ "BriefDescription": "Level One Miss per 100 Instructions", "MetricName": "l1mp", "MetricExpr": "((L1I_DIR_WRITES + L1D_DIR_WRITES) / INSTRUCTIONS) * 100" + }, + { + "BriefDescription": "Percentage sourced from Level 2 cache", + "MetricName": "l2p", + "MetricExpr": "((L1D_L2D_SOURCED_WRITES + L1I_L2I_SOURCED_WRITES) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" + }, + { + "BriefDescription": "Percentage sourced from Level 3 on same chip cache", + "MetricName": "l3p", + "MetricExpr": "((L1D_ONCHIP_L3_SOURCED_WRITES + L1D_ONCHIP_L3_SOURCED_WRITES_IV + L1I_ONCHIP_L3_SOURCED_WRITES + L1I_ONCHIP_L3_SOURCED_WRITES_IV) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" + }, + { + "BriefDescription": "Percentage sourced from Level 4 Local cache on same book", + "MetricName": "l4lp", + "MetricExpr": "((L1D_ONCLUSTER_L3_SOURCED_WRITES + L1D_ONCLUSTER_L3_SOURCED_WRITES_IV + L1D_ONDRAWER_L4_SOURCED_WRITES + L1I_ONCLUSTER_L3_SOURCED_WRITES + L1I_ONCLUSTER_L3_SOURCED_WRITES_IV + L1I_ONDRAWER_L4_SOURCED_WRITES + L1D_OFFCLUSTER_L3_SOURCED_WRITES + L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV + L1D_ONCHIP_L3_SOURCED_WRITES_RO + L1I_OFFCLUSTER_L3_SOURCED_WRITES + L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" + }, + { + "BriefDescription": "Percentage sourced from Level 4 Remote cache on different book", + "MetricName": "l4rp", + "MetricExpr": "((L1D_OFFDRAWER_L3_SOURCED_WRITES + L1D_OFFDRAWER_L3_SOURCED_WRITES_IV + L1D_OFFDRAWER_L4_SOURCED_WRITES + L1I_OFFDRAWER_L3_SOURCED_WRITES + L1I_OFFDRAWER_L3_SOURCED_WRITES_IV + L1I_OFFDRAWER_L4_SOURCED_WRITES) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" + }, + { + "BriefDescription": "Percentage sourced from memory", + "MetricName": "memp", + "MetricExpr": "((L1D_ONCHIP_MEMORY_SOURCED_WRITES + L1D_ONCLUSTER_MEMORY_SOURCED_WRITES + L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES + L1D_OFFDRAWER_MEMORY_SOURCED_WRITES + L1I_ONCHIP_MEMORY_SOURCED_WRITES + L1I_ONCLUSTER_MEMORY_SOURCED_WRITES + L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES + L1I_OFFDRAWER_MEMORY_SOURCED_WRITES) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" } ] From patchwork Mon Mar 13 08:01:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Richter X-Patchwork-Id: 68673 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp1059576wrd; Mon, 13 Mar 2023 01:17:27 -0700 (PDT) X-Google-Smtp-Source: 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IMSVA (Postfix) with ESMTP id 9CF6020546; Mon, 13 Mar 2023 08:02:12 +0000 (GMT) Received: from smtpav05.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 5EDB72054B; Mon, 13 Mar 2023 08:02:12 +0000 (GMT) Received: from tuxmaker.boeblingen.de.ibm.com (unknown [9.152.85.9]) by smtpav05.fra02v.mail.ibm.com (Postfix) with ESMTP; Mon, 13 Mar 2023 08:02:12 +0000 (GMT) From: Thomas Richter To: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, acme@kernel.org, sumanthk@linux.ibm.com Cc: svens@linux.ibm.com, gor@linux.ibm.com, hca@linux.ibm.com, Thomas Richter Subject: [PATCH 4/6] tools/perf/json: Add cache metrics for s390 z14 Date: Mon, 13 Mar 2023 09:01:59 +0100 Message-Id: <20230313080201.2440201-4-tmricht@linux.ibm.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230313080201.2440201-1-tmricht@linux.ibm.com> References: <20230313080201.2440201-1-tmricht@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-GUID: 31u_9OUofeteGZtpiA0VG6UQ-L1nwPXX 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=?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1760239757455392533?= X-GMAIL-MSGID: =?utf-8?q?1760239757455392533?= Add metrics for s390 z14 - Percentage sourced from Level 2 cache - Percentage sourced from Level 3 on same chip cache - Percentage sourced from Level 4 Local cache on same book - Percentage sourced from Level 4 Remote cache on different book - Percentage sourced from memory For details about the formulas see this documentation: https://www.ibm.com/support/pages/system/files/inline-files/CPU%20MF%20Formulas%20including%20z16%20-%20May%202022_1.pdf Outpuf after: # ./perf stat -M l4rp -- find / .... find output deleted Performance counter stats for 'find /': 0 L1I_OFFDRAWER_L4_SOURCED_WRITES # 0.01 l4rp 84 L1D_OFFDRAWER_L4_SOURCED_WRITES 0 L1I_OFFDRAWER_L3_SOURCED_WRITES 71,535,353 L1I_DIR_WRITES 219 L1D_OFFDRAWER_L3_SOURCED_WRITES 16,436 L1D_OFFDRAWER_L3_SOURCED_WRITES_IV 0 L1I_OFFDRAWER_L3_SOURCED_WRITES_IV 46,343,940 L1D_DIR_WRITES 10.530805537 seconds time elapsed 0.774396000 seconds user 1.602714000 seconds sys # Signed-off-by: Thomas Richter Acked-By: Sumanth Korikkar --- .../arch/s390/cf_z14/transaction.json | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/tools/perf/pmu-events/arch/s390/cf_z14/transaction.json b/tools/perf/pmu-events/arch/s390/cf_z14/transaction.json index 86bf83b4504e..cca237bdb7ba 100644 --- a/tools/perf/pmu-events/arch/s390/cf_z14/transaction.json +++ b/tools/perf/pmu-events/arch/s390/cf_z14/transaction.json @@ -18,5 +18,30 @@ "BriefDescription": "Level One Miss per 100 Instructions", "MetricName": "l1mp", "MetricExpr": "((L1I_DIR_WRITES + L1D_DIR_WRITES) / INSTRUCTIONS) * 100" + }, + { + "BriefDescription": "Percentage sourced from Level 2 cache", + "MetricName": "l2p", + "MetricExpr": "((L1D_L2D_SOURCED_WRITES + L1I_L2I_SOURCED_WRITES) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" + }, + { + "BriefDescription": "Percentage sourced from Level 3 on same chip cache", + "MetricName": "l3p", + "MetricExpr": "((L1D_ONCHIP_L3_SOURCED_WRITES + L1D_ONCHIP_L3_SOURCED_WRITES_IV + L1I_ONCHIP_L3_SOURCED_WRITES + L1I_ONCHIP_L3_SOURCED_WRITES_IV) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" + }, + { + "BriefDescription": "Percentage sourced from Level 4 Local cache on same book", + "MetricName": "l4lp", + "MetricExpr": "((L1D_ONCLUSTER_L3_SOURCED_WRITES + L1D_ONCLUSTER_L3_SOURCED_WRITES_IV + L1D_ONDRAWER_L4_SOURCED_WRITES + L1I_ONCLUSTER_L3_SOURCED_WRITES + L1I_ONCLUSTER_L3_SOURCED_WRITES_IV + L1I_ONDRAWER_L4_SOURCED_WRITES + L1D_OFFCLUSTER_L3_SOURCED_WRITES + L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV + L1D_ONCHIP_L3_SOURCED_WRITES_RO + L1I_OFFCLUSTER_L3_SOURCED_WRITES + L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" + }, + { + "BriefDescription": "Percentage sourced from Level 4 Remote cache on different book", + "MetricName": "l4rp", + "MetricExpr": "((L1D_OFFDRAWER_L3_SOURCED_WRITES + L1D_OFFDRAWER_L3_SOURCED_WRITES_IV + L1D_OFFDRAWER_L4_SOURCED_WRITES + L1I_OFFDRAWER_L3_SOURCED_WRITES + L1I_OFFDRAWER_L3_SOURCED_WRITES_IV + L1I_OFFDRAWER_L4_SOURCED_WRITES) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" + }, + { + "BriefDescription": "Percentage sourced from memory", + "MetricName": "memp", + "MetricExpr": "((L1D_ONCHIP_MEMORY_SOURCED_WRITES + L1D_ONCLUSTER_MEMORY_SOURCED_WRITES + L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES + L1D_OFFDRAWER_MEMORY_SOURCED_WRITES + L1I_ONCHIP_MEMORY_SOURCED_WRITES + L1I_ONCLUSTER_MEMORY_SOURCED_WRITES + L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES + L1I_OFFDRAWER_MEMORY_SOURCED_WRITES) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" } ] From patchwork Mon Mar 13 08:02:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Richter X-Patchwork-Id: 68683 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp1062918wrd; Mon, 13 Mar 2023 01:28:10 -0700 (PDT) X-Google-Smtp-Source: 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(Postfix) with ESMTP id 421E32054B; Mon, 13 Mar 2023 08:02:14 +0000 (GMT) Received: from smtpav05.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 0422A2052E; Mon, 13 Mar 2023 08:02:14 +0000 (GMT) Received: from tuxmaker.boeblingen.de.ibm.com (unknown [9.152.85.9]) by smtpav05.fra02v.mail.ibm.com (Postfix) with ESMTP; Mon, 13 Mar 2023 08:02:13 +0000 (GMT) From: Thomas Richter To: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, acme@kernel.org, sumanthk@linux.ibm.com Cc: svens@linux.ibm.com, gor@linux.ibm.com, hca@linux.ibm.com, Thomas Richter Subject: [PATCH 5/6] tools/perf/json: Add cache metrics for s390 z13 Date: Mon, 13 Mar 2023 09:02:00 +0100 Message-Id: <20230313080201.2440201-5-tmricht@linux.ibm.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230313080201.2440201-1-tmricht@linux.ibm.com> References: <20230313080201.2440201-1-tmricht@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-GUID: e1VabvnOg-tt-Co4jn8TyA9UTPtYJ7Tj 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X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1760240431721264200?= X-GMAIL-MSGID: =?utf-8?q?1760240431721264200?= Add metrics for s390 z13 - Percentage sourced from Level 2 cache - Percentage sourced from Level 3 on same chip cache - Percentage sourced from Level 4 Local cache on same book - Percentage sourced from Level 4 Remote cache on different book - Percentage sourced from memory For details about the formulas see this documentation: https://www.ibm.com/support/pages/system/files/inline-files/CPU%20MF%20Formulas%20including%20z16%20-%20May%202022_1.pdf Output after: # ./perf stat -M l4rp -- find / ...find output deleted Performance counter stats for 'find /': 2 L1I_OFFDRAWER_SCOL_L4_SOURCED_WRITES # 0.02 l4rp 252 L1D_ONDRAWER_L4_SOURCED_WRITES 3,465 L1D_ONDRAWER_L3_SOURCED_WRITES_IV 80 L1D_OFFDRAWER_SCOL_L4_SOURCED_WRITES 761 L1D_ONDRAWER_L3_SOURCED_WRITES 0 L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES 131,817,067 L1I_DIR_WRITES 1 L1I_OFFDRAWER_FCOL_L4_SOURCED_WRITES 447 L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES 22 L1D_OFFDRAWER_FCOL_L4_SOURCED_WRITES 7 L1I_ONDRAWER_L4_SOURCED_WRITES 0 L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES 1,071 L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES 3 L1I_ONDRAWER_L3_SOURCED_WRITES 13,352 L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV 15,252 L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV 0 L1I_ONDRAWER_L3_SOURCED_WRITES_IV 0 L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV 57,431,083 L1D_DIR_WRITES 0 L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV 15.386502874 seconds time elapsed 0.647348000 seconds user 3.537041000 seconds sys # Signed-off-by: Thomas Richter Acked-By: Sumanth Korikkar --- .../arch/s390/cf_z13/transaction.json | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/tools/perf/pmu-events/arch/s390/cf_z13/transaction.json b/tools/perf/pmu-events/arch/s390/cf_z13/transaction.json index 86bf83b4504e..71e2c7fa734c 100644 --- a/tools/perf/pmu-events/arch/s390/cf_z13/transaction.json +++ b/tools/perf/pmu-events/arch/s390/cf_z13/transaction.json @@ -18,5 +18,30 @@ "BriefDescription": "Level One Miss per 100 Instructions", "MetricName": "l1mp", "MetricExpr": "((L1I_DIR_WRITES + L1D_DIR_WRITES) / INSTRUCTIONS) * 100" + }, + { + "BriefDescription": "Percentage sourced from Level 2 cache", + "MetricName": "l2p", + "MetricExpr": "((L1D_L2D_SOURCED_WRITES + L1I_L2I_SOURCED_WRITES) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" + }, + { + "BriefDescription": "Percentage sourced from Level 3 on same chip cache", + "MetricName": "l3p", + "MetricExpr": "((L1D_ONCHIP_L3_SOURCED_WRITES + L1D_ONCHIP_L3_SOURCED_WRITES_IV + L1I_ONCHIP_L3_SOURCED_WRITES + L1I_ONCHIP_L3_SOURCED_WRITES_IV) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" + }, + { + "BriefDescription": "Percentage sourced from Level 4 Local cache on same book", + "MetricName": "l4lp", + "MetricExpr": "((L1D_ONNODE_L4_SOURCED_WRITES + L1D_ONNODE_L3_SOURCED_WRITES_IV + L1D_ONNODE_L3_SOURCED_WRITES + L1I_ONNODE_L4_SOURCED_WRITES + L1I_ONNODE_L3_SOURCED_WRITES_IV + L1I_ONNODE_L3_SOURCED_WRITES) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" + }, + { + "BriefDescription": "Percentage sourced from Level 4 Remote cache on different book", + "MetricName": "l4rp", + "MetricExpr": "((L1D_ONDRAWER_L4_SOURCED_WRITES + L1D_ONDRAWER_L3_SOURCED_WRITES_IV + L1D_ONDRAWER_L3_SOURCED_WRITES + L1D_OFFDRAWER_SCOL_L4_SOURCED_WRITES + L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV + L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES + L1D_OFFDRAWER_FCOL_L4_SOURCED_WRITES + L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV + L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES + L1I_ONDRAWER_L4_SOURCED_WRITES + L1I_ONDRAWER_L3_SOURCED_WRITES_IV + L1I_ONDRAWER_L3_SOURCED_WRITES + L1I_OFFDRAWER_SCOL_L4_SOURCED_WRITES + L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV + L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES + L1I_OFFDRAWER_FCOL_L4_SOURCED_WRITES + L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV + L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" + }, + { + "BriefDescription": "Percentage sourced from memory", + "MetricName": "memp", + "MetricExpr": "((L1D_ONNODE_MEM_SOURCED_WRITES + L1D_ONDRAWER_MEM_SOURCED_WRITES + L1D_OFFDRAWER_MEM_SOURCED_WRITES + L1D_ONCHIP_MEM_SOURCED_WRITES + L1I_ONNODE_MEM_SOURCED_WRITES + L1I_ONDRAWER_MEM_SOURCED_WRITES + L1I_OFFDRAWER_MEM_SOURCED_WRITES + L1I_ONCHIP_MEM_SOURCED_WRITES) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" } ] From patchwork Mon Mar 13 08:02:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Richter X-Patchwork-Id: 68691 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp1072346wrd; Mon, 13 Mar 2023 01:59:47 -0700 (PDT) X-Google-Smtp-Source: AK7set/WwY6xVj/5sxXWzWM3sAD5TZzGrmv55H05BjOLIXIbvuDT9idzoN/TfwPg/eISN16hmk/T X-Received: by 2002:a05:6a20:8e28:b0:cd:7fcf:11a6 with SMTP id y40-20020a056a208e2800b000cd7fcf11a6mr34837854pzj.48.1678697987286; Mon, 13 Mar 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IMSVA (Postfix) with ESMTP id 63D842054F; Mon, 13 Mar 2023 08:02:15 +0000 (GMT) Received: from smtpav05.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 20D1620547; Mon, 13 Mar 2023 08:02:15 +0000 (GMT) Received: from tuxmaker.boeblingen.de.ibm.com (unknown [9.152.85.9]) by smtpav05.fra02v.mail.ibm.com (Postfix) with ESMTP; Mon, 13 Mar 2023 08:02:15 +0000 (GMT) From: Thomas Richter To: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, acme@kernel.org, sumanthk@linux.ibm.com Cc: svens@linux.ibm.com, gor@linux.ibm.com, hca@linux.ibm.com, Thomas Richter Subject: [PATCH 6/6] tools/perf/json: Add metric for tlb and cache s390 Date: Mon, 13 Mar 2023 09:02:01 +0100 Message-Id: <20230313080201.2440201-6-tmricht@linux.ibm.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230313080201.2440201-1-tmricht@linux.ibm.com> References: <20230313080201.2440201-1-tmricht@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-GUID: Lt20Sa2K532UG0M9Ww18QPcqVUsOnQo_ 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=?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1760242420907592485?= X-GMAIL-MSGID: =?utf-8?q?1760242420907592485?= Add metrics for tlb and cache statistics: - finite_cpi: Cycles per Instructions from Finite cache/memory - est_cpi: Estimated Instruction Complexity CPI infinite Level 1 - scpl1m: Estimated Sourcing Cycles per Level 1 Miss - tlb_percent: Estimated TLB CPU percentage of Total CPU - tlb_miss: Estimated Cycles per TLB Miss For details about the formulas see this documentation: https://www.ibm.com/support/pages/system/files/inline-files/CPU%20MF%20Formulas%20including%20z16%20-%20May%202022_1.pdf Output after: # ./perf stat -M tlb_miss -- dd if=/dev/zero of=/dev/null bs=1M count=10K ... dd output removed Performance counter stats for 'dd if=/dev/zero of=/dev/null bs=1M count=10K': 667,726 DTLB2_MISSES # 440.96 tlb_miss 198 ITLB2_WRITES 795,170,260 L1C_TLB2_MISSES 9,478 ITLB2_MISSES 820 DTLB2_WRITES 1,197,126,869 L1D_PENALTY_CYCLES 2,457,447 L1I_PENALTY_CYCLES 1.249342187 seconds time elapsed 0.001030000 seconds user 1.248105000 seconds sys # Signed-off-by: Thomas Richter Acked-By: Sumanth Korikkar --- .../arch/s390/cf_z13/transaction.json | 30 +++++++++++++++++++ .../arch/s390/cf_z14/transaction.json | 25 ++++++++++++++++ .../arch/s390/cf_z15/transaction.json | 25 ++++++++++++++++ .../arch/s390/cf_z16/transaction.json | 25 ++++++++++++++++ 4 files changed, 105 insertions(+) diff --git a/tools/perf/pmu-events/arch/s390/cf_z13/transaction.json b/tools/perf/pmu-events/arch/s390/cf_z13/transaction.json index 71e2c7fa734c..b941a7212a4d 100644 --- a/tools/perf/pmu-events/arch/s390/cf_z13/transaction.json +++ b/tools/perf/pmu-events/arch/s390/cf_z13/transaction.json @@ -43,5 +43,35 @@ "BriefDescription": "Percentage sourced from memory", "MetricName": "memp", "MetricExpr": "((L1D_ONNODE_MEM_SOURCED_WRITES + L1D_ONDRAWER_MEM_SOURCED_WRITES + L1D_OFFDRAWER_MEM_SOURCED_WRITES + L1D_ONCHIP_MEM_SOURCED_WRITES + L1I_ONNODE_MEM_SOURCED_WRITES + L1I_ONDRAWER_MEM_SOURCED_WRITES + L1I_OFFDRAWER_MEM_SOURCED_WRITES + L1I_ONCHIP_MEM_SOURCED_WRITES) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" + }, + { + "BriefDescription": "Cycles per Instructions from Finite cache/memory", + "MetricName": "finite_cpi", + "MetricExpr": "L1C_TLB1_MISSES / INSTRUCTIONS" + }, + { + "BriefDescription": "Estimated Instruction Complexity CPI infinite Level 1", + "MetricName": "est_cpi", + "MetricExpr": "(CPU_CYCLES / INSTRUCTIONS) - (L1C_TLB1_MISSES / INSTRUCTIONS)" + }, + { + "BriefDescription": "Estimated Sourcing Cycles per Level 1 Miss", + "MetricName": "scpl1m", + "MetricExpr": "L1C_TLB1_MISSES / (L1I_DIR_WRITES + L1D_DIR_WRITES)" + }, + { + "BriefDescription": "Estimated TLB CPU percentage of Total CPU", + "MetricName": "tlb_percent", + "MetricExpr": "((DTLB1_MISSES + ITLB1_MISSES) / CPU_CYCLES) * (L1C_TLB1_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES)) * 100" + }, + { + "BriefDescription": "Estimated Cycles per TLB Miss", + "MetricName": "tlb_miss", + "MetricExpr": "((DTLB1_MISSES + ITLB1_MISSES) / (DTLB1_WRITES + ITLB1_WRITES)) * (L1C_TLB1_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES))" + }, + { + "BriefDescription": "Page Table Entry misses", + "MetricName": "pte_miss", + "MetricExpr": "(TLB2_PTE_WRITES / (DTLB1_WRITES + ITLB1_WRITES)) * 100" } ] diff --git a/tools/perf/pmu-events/arch/s390/cf_z14/transaction.json b/tools/perf/pmu-events/arch/s390/cf_z14/transaction.json index cca237bdb7ba..ce814ea93396 100644 --- a/tools/perf/pmu-events/arch/s390/cf_z14/transaction.json +++ b/tools/perf/pmu-events/arch/s390/cf_z14/transaction.json @@ -43,5 +43,30 @@ "BriefDescription": "Percentage sourced from memory", "MetricName": "memp", "MetricExpr": "((L1D_ONCHIP_MEMORY_SOURCED_WRITES + L1D_ONCLUSTER_MEMORY_SOURCED_WRITES + L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES + L1D_OFFDRAWER_MEMORY_SOURCED_WRITES + L1I_ONCHIP_MEMORY_SOURCED_WRITES + L1I_ONCLUSTER_MEMORY_SOURCED_WRITES + L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES + L1I_OFFDRAWER_MEMORY_SOURCED_WRITES) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" + }, + { + "BriefDescription": "Cycles per Instructions from Finite cache/memory", + "MetricName": "finite_cpi", + "MetricExpr": "L1C_TLB2_MISSES / INSTRUCTIONS" + }, + { + "BriefDescription": "Estimated Instruction Complexity CPI infinite Level 1", + "MetricName": "est_cpi", + "MetricExpr": "(CPU_CYCLES / INSTRUCTIONS) - (L1C_TLB2_MISSES / INSTRUCTIONS)" + }, + { + "BriefDescription": "Estimated Sourcing Cycles per Level 1 Miss", + "MetricName": "scpl1m", + "MetricExpr": "L1C_TLB2_MISSES / (L1I_DIR_WRITES + L1D_DIR_WRITES)" + }, + { + "BriefDescription": "Estimated TLB CPU percentage of Total CPU", + "MetricName": "tlb_percent", + "MetricExpr": "((DTLB2_MISSES + ITLB2_MISSES) / CPU_CYCLES) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES)) * 100" + }, + { + "BriefDescription": "Estimated Cycles per TLB Miss", + "MetricName": "tlb_miss", + "MetricExpr": "((DTLB2_MISSES + ITLB2_MISSES) / (DTLB2_WRITES + ITLB2_WRITES)) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES))" } ] diff --git a/tools/perf/pmu-events/arch/s390/cf_z15/transaction.json b/tools/perf/pmu-events/arch/s390/cf_z15/transaction.json index cca237bdb7ba..ce814ea93396 100644 --- a/tools/perf/pmu-events/arch/s390/cf_z15/transaction.json +++ b/tools/perf/pmu-events/arch/s390/cf_z15/transaction.json @@ -43,5 +43,30 @@ "BriefDescription": "Percentage sourced from memory", "MetricName": "memp", "MetricExpr": "((L1D_ONCHIP_MEMORY_SOURCED_WRITES + L1D_ONCLUSTER_MEMORY_SOURCED_WRITES + L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES + L1D_OFFDRAWER_MEMORY_SOURCED_WRITES + L1I_ONCHIP_MEMORY_SOURCED_WRITES + L1I_ONCLUSTER_MEMORY_SOURCED_WRITES + L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES + L1I_OFFDRAWER_MEMORY_SOURCED_WRITES) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" + }, + { + "BriefDescription": "Cycles per Instructions from Finite cache/memory", + "MetricName": "finite_cpi", + "MetricExpr": "L1C_TLB2_MISSES / INSTRUCTIONS" + }, + { + "BriefDescription": "Estimated Instruction Complexity CPI infinite Level 1", + "MetricName": "est_cpi", + "MetricExpr": "(CPU_CYCLES / INSTRUCTIONS) - (L1C_TLB2_MISSES / INSTRUCTIONS)" + }, + { + "BriefDescription": "Estimated Sourcing Cycles per Level 1 Miss", + "MetricName": "scpl1m", + "MetricExpr": "L1C_TLB2_MISSES / (L1I_DIR_WRITES + L1D_DIR_WRITES)" + }, + { + "BriefDescription": "Estimated TLB CPU percentage of Total CPU", + "MetricName": "tlb_percent", + "MetricExpr": "((DTLB2_MISSES + ITLB2_MISSES) / CPU_CYCLES) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES)) * 100" + }, + { + "BriefDescription": "Estimated Cycles per TLB Miss", + "MetricName": "tlb_miss", + "MetricExpr": "((DTLB2_MISSES + ITLB2_MISSES) / (DTLB2_WRITES + ITLB2_WRITES)) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES))" } ] diff --git a/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json b/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json index dde0735a7d22..ec2ff78e2b5f 100644 --- a/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json +++ b/tools/perf/pmu-events/arch/s390/cf_z16/transaction.json @@ -43,5 +43,30 @@ "BriefDescription": "Percentage sourced from memory", "MetricName": "memp", "MetricExpr": "((DCW_ON_CHIP_MEMORY + DCW_ON_MODULE_MEMORY + DCW_ON_DRAWER_MEMORY + DCW_OFF_DRAWER_MEMORY + ICW_ON_CHIP_MEMORY + ICW_ON_MODULE_MEMORY + ICW_ON_DRAWER_MEMORY + ICW_OFF_DRAWER_MEMORY) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100" + }, + { + "BriefDescription": "Cycles per Instructions from Finite cache/memory", + "MetricName": "finite_cpi", + "MetricExpr": "L1C_TLB2_MISSES / INSTRUCTIONS" + }, + { + "BriefDescription": "Estimated Instruction Complexity CPI infinite Level 1", + "MetricName": "est_cpi", + "MetricExpr": "(CPU_CYCLES / INSTRUCTIONS) - (L1C_TLB2_MISSES / INSTRUCTIONS)" + }, + { + "BriefDescription": "Estimated Sourcing Cycles per Level 1 Miss", + "MetricName": "scpl1m", + "MetricExpr": "L1C_TLB2_MISSES / (L1I_DIR_WRITES + L1D_DIR_WRITES)" + }, + { + "BriefDescription": "Estimated TLB CPU percentage of Total CPU", + "MetricName": "tlb_percent", + "MetricExpr": "((DTLB2_MISSES + ITLB2_MISSES) / CPU_CYCLES) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES)) * 100" + }, + { + "BriefDescription": "Estimated Cycles per TLB Miss", + "MetricName": "tlb_miss", + "MetricExpr": "((DTLB2_MISSES + ITLB2_MISSES) / (DTLB2_WRITES + ITLB2_WRITES)) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES))" } ]