From patchwork Mon Mar 13 07:13:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Komal Bajaj X-Patchwork-Id: 68643 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp1041685wrd; Mon, 13 Mar 2023 00:16:44 -0700 (PDT) X-Google-Smtp-Source: AK7set+y6OMM+2NOUD69cuYtwy8/df9Hrv1RzNuKCKlroT3chQsI8KHywY/xYqCWA7rrzE/ilmTo X-Received: by 2002:a62:546:0:b0:5a8:c3ec:e24e with SMTP id 67-20020a620546000000b005a8c3ece24emr23150389pff.4.1678691804013; Mon, 13 Mar 2023 00:16:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1678691803; cv=none; d=google.com; s=arc-20160816; b=xkO1+hh6taxbxypv5/KD2K+143NiwDATrNueT5cvDLkaPZfPVVdXvLo0QmH1lBUgfB gXf4xKNIVCOX1ryKY1LXSDUWJXAExYdUhTdkaJrddqQRJ6wVsPs64bD+aHMhFdHNVAnj EXXC4aREu2fJOmbsQ075CCMiZ6/V1anPY/n77SI4GU1mK34t6KON+LEH+PQniKeSBmeF NfmgGC5PFnoumeZYXkt28Y8LwDhqvhd4YYjbzNawQ+tVd/N3tGT3kLWImn3OfVER3R5l l8zSCfxPZyRBJDKfB9CXiHDLGlOgtI9mUK3o6tDPkvTzMFs2SAWUU1W4VRkj+G7+mj94 4xYg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=arWtPEA0bcJXqwG62AWlaCRZSxo1cNJCkmPGoarEGKM=; b=D/UtFzAGwBnW/JcyyNd9jrlSiRjG1KGsG3fR/SIwwXJAIkAOfloS/gYGXSR33zHldn NzELUIWTfXCdekLCLptLl7rkfLKt4cOionkeRz5hPlPMw4oirL5OM0Y2jyqbkLxI+Nq5 T7bFLudGN5SYFyq7TPK+xwdeX/VVfx57M/uu4WFOo/bFEZ+Amf63RHV2iJ2Pyr/NGC0G OvGaPTxbFT+74VzxnsrpKwo3vxrQNuK+gInSHBsLXctXREahiQ3vGqx8Wh2rllTOtKYJ nWU8HskMN5inOxu0KjNH+2krY8CpJ3TXHGHZNs/nUIhW1tIqiMoQ5BpfnQu/YFS75RKO ELhQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=MgCqYDAb; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id a26-20020a65655a000000b004fc25858c33si383397pgw.506.2023.03.13.00.16.30; Mon, 13 Mar 2023 00:16:43 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=MgCqYDAb; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229933AbjCMHOZ (ORCPT + 99 others); Mon, 13 Mar 2023 03:14:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55406 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229919AbjCMHOS (ORCPT ); Mon, 13 Mar 2023 03:14:18 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0E8CC135; Mon, 13 Mar 2023 00:14:15 -0700 (PDT) Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 32D6lMfd026416; Mon, 13 Mar 2023 07:13:48 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=qcppdkim1; bh=arWtPEA0bcJXqwG62AWlaCRZSxo1cNJCkmPGoarEGKM=; b=MgCqYDAbWCz+WOxBkDEghkmo3XPaFljZ1kFuoT6Sx51bG2vu0nw0GxEkKcaIt39pJtsH foxJL2gDnjZ3AXPmVJZ1zeXp2BiZBS4bMdYoSdKYU9o1r47JTpvef1JHqaHYscQ52xxI NNRJbDOvdyFoa+FXQQagcU3qkOZnSOHRY1f9S76MWmdwdzHeRxCDaub6qwh92Cx34txk 0FLBqjnGQHheLj6CsWsd2ZHRQWWk174Fe4Yl5CTUmSiYH8XaIG3V6POTOOwOcCtKEceH yhed6mV5aUUV1wdnW5sMW6I5DViEXGcU4tb+XDCfeyVoOhlFQdbVw9CiSd1oIiV9BIgB jw== Received: from apblrppmta01.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3p8hr2m0f0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 13 Mar 2023 07:13:47 +0000 Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 32D7Dils032123; Mon, 13 Mar 2023 07:13:44 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 3p8jqkkykb-1; Mon, 13 Mar 2023 07:13:44 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 32D7DiRs032114; Mon, 13 Mar 2023 07:13:44 GMT Received: from kbajaj-linux.qualcomm.com (kbajaj-linux.qualcomm.com [10.214.66.129]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 32D7DiSv032113; Mon, 13 Mar 2023 07:13:44 +0000 Received: from kbajaj-linux.qualcomm.com (localhost [127.0.0.1]) by kbajaj-linux.qualcomm.com (Postfix) with ESMTP id A384FD8; Mon, 13 Mar 2023 12:43:43 +0530 (IST) From: Komal Bajaj To: Rob Herring , Bjorn Andersson , Konrad Dybcio , Abel Vesa , Rishabh Bhatnagar , Prakash Ranjan , Krzysztof Kozlowski , Andy Gross Cc: Komal Bajaj , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH 1/5] soc: qcom: llcc: Refactor llcc driver to support multiple configuration Date: Mon, 13 Mar 2023 12:43:21 +0530 Message-Id: <20230313071325.21605-2-quic_kbajaj@quicinc.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230313071325.21605-1-quic_kbajaj@quicinc.com> References: <20230313071325.21605-1-quic_kbajaj@quicinc.com> MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 9WYrD_pm8AlTCFZlDNk2o9LvuOp6fs8T X-Proofpoint-GUID: 9WYrD_pm8AlTCFZlDNk2o9LvuOp6fs8T X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-12_10,2023-03-10_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 phishscore=0 adultscore=0 priorityscore=1501 clxscore=1015 impostorscore=0 spamscore=0 bulkscore=0 suspectscore=0 mlxlogscore=999 malwarescore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2303130058 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1760235937092506596?= X-GMAIL-MSGID: =?utf-8?q?1760235937092506596?= Refactor driver to support multiple configuration for llcc on a target. Signed-off-by: Komal Bajaj --- drivers/soc/qcom/llcc-qcom.c | 191 ++++++++++++++++++++--------------- 1 file changed, 112 insertions(+), 79 deletions(-) diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 23ce2f78c4ed..00699a0c047e 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -416,92 +416,125 @@ static const u32 llcc_v2_1_reg_offset[] = { [LLCC_COMMON_STATUS0] = 0x0003400c, }; -static const struct qcom_llcc_config sc7180_cfg = { - .sct_data = sc7180_data, - .size = ARRAY_SIZE(sc7180_data), - .need_llcc_cfg = true, - .reg_offset = llcc_v1_reg_offset, - .edac_reg_offset = &llcc_v1_edac_reg_offset, +static const struct qcom_llcc_config sc7180_cfg[] = { + { + .sct_data = sc7180_data, + .size = ARRAY_SIZE(sc7180_data), + .need_llcc_cfg = true, + .reg_offset = llcc_v1_reg_offset, + .edac_reg_offset = &llcc_v1_edac_reg_offset, + }, + { }, }; -static const struct qcom_llcc_config sc7280_cfg = { - .sct_data = sc7280_data, - .size = ARRAY_SIZE(sc7280_data), - .need_llcc_cfg = true, - .reg_offset = llcc_v1_reg_offset, - .edac_reg_offset = &llcc_v1_edac_reg_offset, +static const struct qcom_llcc_config sc7280_cfg[] = { + { + .sct_data = sc7280_data, + .size = ARRAY_SIZE(sc7280_data), + .need_llcc_cfg = true, + .reg_offset = llcc_v1_reg_offset, + .edac_reg_offset = &llcc_v1_edac_reg_offset, + }, + { }, }; -static const struct qcom_llcc_config sc8180x_cfg = { - .sct_data = sc8180x_data, - .size = ARRAY_SIZE(sc8180x_data), - .need_llcc_cfg = true, - .reg_offset = llcc_v1_reg_offset, - .edac_reg_offset = &llcc_v1_edac_reg_offset, +static const struct qcom_llcc_config sc8180x_cfg[] = { + { + .sct_data = sc8180x_data, + .size = ARRAY_SIZE(sc8180x_data), + .need_llcc_cfg = true, + .reg_offset = llcc_v1_reg_offset, + .edac_reg_offset = &llcc_v1_edac_reg_offset, + }, + { }, }; -static const struct qcom_llcc_config sc8280xp_cfg = { - .sct_data = sc8280xp_data, - .size = ARRAY_SIZE(sc8280xp_data), - .need_llcc_cfg = true, - .reg_offset = llcc_v1_reg_offset, - .edac_reg_offset = &llcc_v1_edac_reg_offset, +static const struct qcom_llcc_config sc8280xp_cfg[] = { + { + .sct_data = sc8280xp_data, + .size = ARRAY_SIZE(sc8280xp_data), + .need_llcc_cfg = true, + .reg_offset = llcc_v1_reg_offset, + .edac_reg_offset = &llcc_v1_edac_reg_offset, + }, + { }, }; -static const struct qcom_llcc_config sdm845_cfg = { - .sct_data = sdm845_data, - .size = ARRAY_SIZE(sdm845_data), - .need_llcc_cfg = false, - .reg_offset = llcc_v1_reg_offset, - .edac_reg_offset = &llcc_v1_edac_reg_offset, +static const struct qcom_llcc_config sdm845_cfg[] = { + { + .sct_data = sdm845_data, + .size = ARRAY_SIZE(sdm845_data), + .need_llcc_cfg = false, + .reg_offset = llcc_v1_reg_offset, + .edac_reg_offset = &llcc_v1_edac_reg_offset, + }, + { }, }; -static const struct qcom_llcc_config sm6350_cfg = { - .sct_data = sm6350_data, - .size = ARRAY_SIZE(sm6350_data), - .need_llcc_cfg = true, - .reg_offset = llcc_v1_reg_offset, - .edac_reg_offset = &llcc_v1_edac_reg_offset, +static const struct qcom_llcc_config sm6350_cfg[] = { + { + .sct_data = sm6350_data, + .size = ARRAY_SIZE(sm6350_data), + .need_llcc_cfg = true, + .reg_offset = llcc_v1_reg_offset, + .edac_reg_offset = &llcc_v1_edac_reg_offset, + }, + { }, }; -static const struct qcom_llcc_config sm8150_cfg = { - .sct_data = sm8150_data, - .size = ARRAY_SIZE(sm8150_data), - .need_llcc_cfg = true, - .reg_offset = llcc_v1_reg_offset, - .edac_reg_offset = &llcc_v1_edac_reg_offset, +static const struct qcom_llcc_config sm8150_cfg[] = { + { + .sct_data = sm8150_data, + .size = ARRAY_SIZE(sm8150_data), + .need_llcc_cfg = true, + .reg_offset = llcc_v1_reg_offset, + .edac_reg_offset = &llcc_v1_edac_reg_offset, + }, + { }, }; -static const struct qcom_llcc_config sm8250_cfg = { - .sct_data = sm8250_data, - .size = ARRAY_SIZE(sm8250_data), - .need_llcc_cfg = true, - .reg_offset = llcc_v1_reg_offset, - .edac_reg_offset = &llcc_v1_edac_reg_offset, +static const struct qcom_llcc_config sm8250_cfg[] = { + { + .sct_data = sm8250_data, + .size = ARRAY_SIZE(sm8250_data), + .need_llcc_cfg = true, + .reg_offset = llcc_v1_reg_offset, + .edac_reg_offset = &llcc_v1_edac_reg_offset, + }, + { }, }; -static const struct qcom_llcc_config sm8350_cfg = { - .sct_data = sm8350_data, - .size = ARRAY_SIZE(sm8350_data), - .need_llcc_cfg = true, - .reg_offset = llcc_v1_reg_offset, - .edac_reg_offset = &llcc_v1_edac_reg_offset, +static const struct qcom_llcc_config sm8350_cfg[] = { + { + .sct_data = sm8350_data, + .size = ARRAY_SIZE(sm8350_data), + .need_llcc_cfg = true, + .reg_offset = llcc_v1_reg_offset, + .edac_reg_offset = &llcc_v1_edac_reg_offset, + }, + { }, }; -static const struct qcom_llcc_config sm8450_cfg = { - .sct_data = sm8450_data, - .size = ARRAY_SIZE(sm8450_data), - .need_llcc_cfg = true, - .reg_offset = llcc_v2_1_reg_offset, - .edac_reg_offset = &llcc_v2_1_edac_reg_offset, +static const struct qcom_llcc_config sm8450_cfg[] = { + { + .sct_data = sm8450_data, + .size = ARRAY_SIZE(sm8450_data), + .need_llcc_cfg = true, + .reg_offset = llcc_v2_1_reg_offset, + .edac_reg_offset = &llcc_v2_1_edac_reg_offset, + }, + { }, }; -static const struct qcom_llcc_config sm8550_cfg = { - .sct_data = sm8550_data, - .size = ARRAY_SIZE(sm8550_data), - .need_llcc_cfg = true, - .reg_offset = llcc_v2_1_reg_offset, - .edac_reg_offset = &llcc_v2_1_edac_reg_offset, +static const struct qcom_llcc_config sm8550_cfg[] = { + { + .sct_data = sm8550_data, + .size = ARRAY_SIZE(sm8550_data), + .need_llcc_cfg = true, + .reg_offset = llcc_v2_1_reg_offset, + .edac_reg_offset = &llcc_v2_1_edac_reg_offset, + }, + { }, }; static struct llcc_drv_data *drv_data = (void *) -EPROBE_DEFER; @@ -966,8 +999,8 @@ static int qcom_llcc_probe(struct platform_device *pdev) num_banks >>= LLCC_LB_CNT_SHIFT; drv_data->num_banks = num_banks; - llcc_cfg = cfg->sct_data; - sz = cfg->size; + llcc_cfg = cfg[0].sct_data; + sz = cfg[0].size; for (i = 0; i < sz; i++) if (llcc_cfg[i].slice_id > drv_data->max_slices) @@ -1016,17 +1049,17 @@ static int qcom_llcc_probe(struct platform_device *pdev) } static const struct of_device_id qcom_llcc_of_match[] = { - { .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfg }, - { .compatible = "qcom,sc7280-llcc", .data = &sc7280_cfg }, - { .compatible = "qcom,sc8180x-llcc", .data = &sc8180x_cfg }, - { .compatible = "qcom,sc8280xp-llcc", .data = &sc8280xp_cfg }, - { .compatible = "qcom,sdm845-llcc", .data = &sdm845_cfg }, - { .compatible = "qcom,sm6350-llcc", .data = &sm6350_cfg }, - { .compatible = "qcom,sm8150-llcc", .data = &sm8150_cfg }, - { .compatible = "qcom,sm8250-llcc", .data = &sm8250_cfg }, - { .compatible = "qcom,sm8350-llcc", .data = &sm8350_cfg }, - { .compatible = "qcom,sm8450-llcc", .data = &sm8450_cfg }, - { .compatible = "qcom,sm8550-llcc", .data = &sm8550_cfg }, + { .compatible = "qcom,sc7180-llcc", .data = sc7180_cfg }, + { .compatible = "qcom,sc7280-llcc", .data = sc7280_cfg }, + { .compatible = "qcom,sc8180x-llcc", .data = sc8180x_cfg }, + { .compatible = "qcom,sc8280xp-llcc", .data = sc8280xp_cfg }, + { .compatible = "qcom,sdm845-llcc", .data = sdm845_cfg }, + { .compatible = "qcom,sm6350-llcc", .data = sm6350_cfg }, + { .compatible = "qcom,sm8150-llcc", .data = sm8150_cfg }, + { .compatible = "qcom,sm8250-llcc", .data = sm8250_cfg }, + { .compatible = "qcom,sm8350-llcc", .data = sm8350_cfg }, + { .compatible = "qcom,sm8450-llcc", .data = sm8450_cfg }, + { .compatible = "qcom,sm8550-llcc", .data = sm8550_cfg }, { } }; MODULE_DEVICE_TABLE(of, qcom_llcc_of_match); From patchwork Mon Mar 13 07:13:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Komal Bajaj X-Patchwork-Id: 68645 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp1041845wrd; Mon, 13 Mar 2023 00:17:17 -0700 (PDT) X-Google-Smtp-Source: AK7set8owsTPUveccu5ID3ECqryFRCNXFEvCXxQJopm1pO/4C6JlrbgSyz75U+pgoAy10Q9txGH8 X-Received: by 2002:a05:6a20:7d86:b0:cd:6f68:98d6 with SMTP id v6-20020a056a207d8600b000cd6f6898d6mr42211428pzj.0.1678691837455; Mon, 13 Mar 2023 00:17:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1678691837; cv=none; d=google.com; s=arc-20160816; b=XkY5BYydKO9fcMOJTJR9AkyEfYPpZ0t0Bz7YHaBebx0xxy4vSGe13/UqPzRrAw7dUl 5BH2VtuMseNxW5tFVzudF02g8W4+eleY83uniD7+5lCqusCYZNjiYuq3Id7KXEGZpqYT XLbC4c0xqwsIEWDRX6H2rQnyT2m2CvA+0uqX9uy1jqHCk7amzPO2laPA30i4UiiROC8O gW0itm7SoyrTOs3j4xmfJibwfhipVHdNK8wWLIpaUwkyii3rklGb5ClRRHUqg9ran0W1 IvA/km1ZMjFotxMjZIHLmBaLLMseqJCB7hP5v2a+UcPmSCOgJjHSdA9B4pnONCv7ziWI dGhQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=GSBLp78dcLJUo81PqS68p2voIQ9C1DQmMhPbqlXQWgs=; b=KFcYSv4PUKrvG3EA3Ic/UPIf8DryEfTD/TBTREEHwwBNZE4ucNMg49D5aLLPq1vHCz yLjwOY3u4OVeMDDOCHiW6Am3tYSMd3W7Db1LMwQ8guyR8ojfachbQhNdrFLWGsUNv5iG peDlI8WsVSaX/n3eU6rjoHc/nxYM7ew6l4WKPWbfxVO7oRCmXkdEHTE4UxpuSY8I4nR4 dYh+AaQYjwDB6umPAhbC2epA7ahGdovy22HYVmiX0pJkoyt+Zjwf7bYYcLSWh1f9625T QJNdigNuJFrgrZWsBQpbu4sk3W5pWxLFuAyG1jbv7xotHjuJYXZ3PiHBhLmdNvbmYm24 BtyQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b="T/pAhjUl"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id x27-20020aa7957b000000b00593c99a9c87si5838137pfq.348.2023.03.13.00.17.02; Mon, 13 Mar 2023 00:17:17 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b="T/pAhjUl"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229998AbjCMHOj (ORCPT + 99 others); Mon, 13 Mar 2023 03:14:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55884 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229964AbjCMHO1 (ORCPT ); Mon, 13 Mar 2023 03:14:27 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 93D9C34C16; Mon, 13 Mar 2023 00:14:21 -0700 (PDT) Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 32D1od7Q022374; Mon, 13 Mar 2023 07:13:50 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=qcppdkim1; bh=GSBLp78dcLJUo81PqS68p2voIQ9C1DQmMhPbqlXQWgs=; b=T/pAhjUlJlIlhKChNCUWRZyikIVp7yQZkvhUjIz1QY19S8wFtb84Yeq8h6MoS8wZ8Jsx ycclMRud5Wib6ti3rK54aQw/7HVJlpDeFwj6oKs06iZTdVH2iimYi7wii7JDmdzmiqfb phdtr4YY1gKhXZksiLBgVKiOp48eYDpIuov69XgbRTcUp27Q+npE/+lhUm1MSBoOfHsg 5flMg0t+FWk9jBTX2h0WCA1Dy68LBj0e3NA2l0bJ35mdA+rysJ+RJtaSgx8FTMM4bHFg sJEPlbRbJX+UIVqbm3rASJyUl+K4FvILelrOdWvpDIlNX5z8BdKdYXs4/7VJ/1pH2i5E iQ== Received: from apblrppmta01.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3p8hvbm4dj-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 13 Mar 2023 07:13:50 +0000 Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 32D7Dk6Z032134; Mon, 13 Mar 2023 07:13:46 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 3p8jqkkykk-1; Mon, 13 Mar 2023 07:13:46 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 32D7DkAH032129; Mon, 13 Mar 2023 07:13:46 GMT Received: from kbajaj-linux.qualcomm.com (kbajaj-linux.qualcomm.com [10.214.66.129]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 32D7Dkbe032128; Mon, 13 Mar 2023 07:13:46 +0000 Received: from kbajaj-linux.qualcomm.com (localhost [127.0.0.1]) by kbajaj-linux.qualcomm.com (Postfix) with ESMTP id 7CDB2D8; Mon, 13 Mar 2023 12:43:45 +0530 (IST) From: Komal Bajaj To: Rob Herring , Bjorn Andersson , Konrad Dybcio , Abel Vesa , Rishabh Bhatnagar , Prakash Ranjan , Krzysztof Kozlowski , Andy Gross Cc: Komal Bajaj , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH 2/5] dt-bindings: arm: msm: Add bindings for multi channel DDR in LLCC Date: Mon, 13 Mar 2023 12:43:22 +0530 Message-Id: <20230313071325.21605-3-quic_kbajaj@quicinc.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230313071325.21605-1-quic_kbajaj@quicinc.com> References: <20230313071325.21605-1-quic_kbajaj@quicinc.com> MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: SPsFs1G7o34ancrk3rg1eb27d_pV-KjU X-Proofpoint-GUID: SPsFs1G7o34ancrk3rg1eb27d_pV-KjU X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-12_10,2023-03-10_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 bulkscore=0 phishscore=0 clxscore=1015 adultscore=0 malwarescore=0 lowpriorityscore=0 priorityscore=1501 mlxlogscore=880 spamscore=0 impostorscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2303130058 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1760235972059482778?= X-GMAIL-MSGID: =?utf-8?q?1760235972059482778?= Add description for additional nodes needed to support mulitple channel DDR configurations in LLCC. Signed-off-by: Komal Bajaj --- Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml index 38efcad56dbd..9a4a76caf490 100644 --- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml @@ -37,15 +37,24 @@ properties: items: - description: LLCC base register region - description: LLCC broadcast base register region + - description: Feature register to decide which LLCC configuration + to use, this is optional reg-names: items: - const: llcc_base - const: llcc_broadcast_base + - const: multi_channel_register interrupts: maxItems: 1 + multi-ch-bit-off: + items: + - description: Specifies the offset in bits into the multi_channel_register + and the number of bits used to decide which LLCC configuration + to use + required: - compatible - reg From patchwork Mon Mar 13 07:13:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Komal Bajaj X-Patchwork-Id: 68644 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp1041736wrd; Mon, 13 Mar 2023 00:16:55 -0700 (PDT) X-Google-Smtp-Source: AK7set/UdRwX0k2bIKRoJltIdj+G0bWj0KaQQZQlAS2FFCOdeKe7HY/i8hUEzF9WRvXPiIK+nahE X-Received: by 2002:a05:6a21:6da9:b0:c7:73ad:1071 with SMTP id wl41-20020a056a216da900b000c773ad1071mr37511496pzb.14.1678691815385; Mon, 13 Mar 2023 00:16:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1678691815; cv=none; d=google.com; s=arc-20160816; b=PS2OoYYS3M8Rg2tM8vcILFMvkVDaitcZPBVs1hyihxgDBuMYOppoUKcQ6xTZQeGFFA nfBnbg3jU6G2eJNectGBfrkUJA7B9KU6EuN2ZjQWbmvP/G7YZO6qMiULBNE0S6AcFmwq yWZdwG55VUPWOIO5AaquD/5jQLdLdQm8R6trUH0wQW1/YY0Y/3U5CofySwykz7DO0+OV zyZjoLSmqUt6Tnpf9zZjhK3AbliTSCdhtNELEBR3c+JQ9m76Zx/g75vaY8rK+Alzurln J/C/ooXnx+AF1yinVq6UF1w5emgjg0ymHbNQKv6QLtmXmYaKtvsYMsGDndDkvgdxOuaj AMew== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=oKssoe7bYKrxW+GfKOP2L8FXlwSL+Mk+Ar8Hss8Pzeg=; b=z8PUxmpLyK5XJ2N014YrpJhLA8eSVb9tzRz6f1b4KpZf99BygItCAIwQQfPCZ+HTor MbSPZHooDpxaKi6XYt1hNySI7f6vlY5+is5d3myUNuNwAjXcYcY4c5fTv7dyZTUYo/2q GlRH4pi2JhrMo2eYVcG5dPoyleHZqvOQiw2jrNWjCd3vD+UBdE0sW2yjGlDR/EcJt3e/ dMyO4lqljsxjbhzbw5UsBsBIYUxneYwhrnFLUwxhgXAmI7dBGOelIW8yG7sQqOYReMAE +I6Bqpv/WyGpIb+KEctZNcfSTfCHUNnpU3cjRcn8MjBCLRTP5PjsbgHJQm8EKszInHGS eYcg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b="hnpDOq/D"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id o18-20020a63f152000000b005037c23ffb4si5940021pgk.571.2023.03.13.00.16.41; Mon, 13 Mar 2023 00:16:55 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b="hnpDOq/D"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229997AbjCMHO3 (ORCPT + 99 others); Mon, 13 Mar 2023 03:14:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55408 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229842AbjCMHOV (ORCPT ); Mon, 13 Mar 2023 03:14:21 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E1DDE35246; Mon, 13 Mar 2023 00:14:18 -0700 (PDT) Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 32D0H5W3019857; Mon, 13 Mar 2023 07:13:51 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=qcppdkim1; bh=oKssoe7bYKrxW+GfKOP2L8FXlwSL+Mk+Ar8Hss8Pzeg=; b=hnpDOq/D+B9WvrdyidddPcRBtjF0IIzXt/xawhl1U3H9H7KwvLWBVG5VbIjEWTr30wEu E1JOpbJ8Te3teqPiATcEs9TkAFlPSmbDVU1kRi5TV+TOCE7ozHkejUGCx4shVi7EkgKq OOTIjFFb17ZBFqSQF7lZQhS4rEXV7fngbJ2lLsnEjWczeHyoK7eoNebN0PgVwlzobR7X pOVvcrL8Wql0nxj4mNK3qw4W0RIv2uSEpI+TaT8T4W61Ro5FmtUgW6c100GZsQiQYy2p tVYwm7wE9RSJPYHhyWheysqCzdK5amczTPDpkbvgbU3QyoRMjFA742zyrb1D4YAMppw4 Xg== Received: from apblrppmta01.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3p8hr2m0f4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 13 Mar 2023 07:13:51 +0000 Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 32D7DmSK032155; Mon, 13 Mar 2023 07:13:48 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 3p8jqkkykv-1; Mon, 13 Mar 2023 07:13:48 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 32D7DmkS032147; Mon, 13 Mar 2023 07:13:48 GMT Received: from kbajaj-linux.qualcomm.com (kbajaj-linux.qualcomm.com [10.214.66.129]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 32D7Dm0S032146; Mon, 13 Mar 2023 07:13:48 +0000 Received: from kbajaj-linux.qualcomm.com (localhost [127.0.0.1]) by kbajaj-linux.qualcomm.com (Postfix) with ESMTP id 619CED8; Mon, 13 Mar 2023 12:43:47 +0530 (IST) From: Komal Bajaj To: Rob Herring , Bjorn Andersson , Konrad Dybcio , Abel Vesa , Rishabh Bhatnagar , Prakash Ranjan , Krzysztof Kozlowski , Andy Gross Cc: Komal Bajaj , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH 3/5] dt-bindings: arm: msm: Add LLCC compatible for QDU1000/QRU1000 Date: Mon, 13 Mar 2023 12:43:23 +0530 Message-Id: <20230313071325.21605-4-quic_kbajaj@quicinc.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230313071325.21605-1-quic_kbajaj@quicinc.com> References: <20230313071325.21605-1-quic_kbajaj@quicinc.com> MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: gz5Is2LkSwcOfmIHzI7YEUPjhh2Ek86Y X-Proofpoint-GUID: gz5Is2LkSwcOfmIHzI7YEUPjhh2Ek86Y X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-12_10,2023-03-10_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 phishscore=0 adultscore=0 priorityscore=1501 clxscore=1015 impostorscore=0 spamscore=0 bulkscore=0 suspectscore=0 mlxlogscore=769 malwarescore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2303130058 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1760235948541557278?= X-GMAIL-MSGID: =?utf-8?q?1760235948541557278?= Add LLCC compatible for QDU1000/QRU1000 SoCs. Signed-off-by: Komal Bajaj --- Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml index 9a4a76caf490..afb1b84907e0 100644 --- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml @@ -32,6 +32,7 @@ properties: - qcom,sm8350-llcc - qcom,sm8450-llcc - qcom,sm8550-llcc + - qcom,qdu1000-llcc reg: items: From patchwork Mon Mar 13 07:13:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Komal Bajaj X-Patchwork-Id: 68647 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp1041913wrd; Mon, 13 Mar 2023 00:17:30 -0700 (PDT) X-Google-Smtp-Source: AK7set9GrvH1OnX5NGq6M6NZWBYjiWf2L4vNCTxZolEiz3JzNJV9b22j8/8ggBgHymbd15QnxtYw X-Received: by 2002:a17:90a:bc85:b0:237:aade:444 with SMTP id x5-20020a17090abc8500b00237aade0444mr33171400pjr.42.1678691850240; Mon, 13 Mar 2023 00:17:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1678691850; cv=none; d=google.com; s=arc-20160816; b=mmVopOHJ8IBUDqgHau+DzdHetvrLseEJe+ANv34YDOKmE7TCu8cmZ2Grw0dFXsZwUg F7rBhrLmwQ3n0MwkRHGNBzPYejXuYBHNZS8qCCxTp+tx9bU4R335ONEKwLlW6wxuSqPg gfj/y/ulmqHzXAQjrCX+bE+ImM3dZyyLCOVtmP4BjwNBfMVY0diEBIwh/DKJrbFWOgnv 1bMAmX0GbU8lY1KPc67G8BK+Yu7o0tEj5+qxiMa4BI+4kZV+4P7qHI04q3GZj1dBnJMB Kz9NByHuTA3BEr3+z/NMPCBcENmveIhQVwzM3zdZf1pmuS00PgkV7469lGwvBaRUA1Kq ETjg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=PsVrBKdM/JhYSf1jgy6wK+sv0ULCM3EIwVlOEFeyaDM=; b=rKtlvHStXg/06PrMhSEbawbeAisPPIa+x5V8HPc2mjf1cDg2IsF9DPIAOsoCXdsASO bt9EQTVsI9OadiSVAkvlXn5m8r2pXQPIsftDb0x6OkE9Rdm/rn8YMLNkpYNnjchnVY9b f3hvaMVl5Ul04byW9EAY145iqGal6tynYhl9QhhS8u8akDIpOtt529VmkBRkjBN7IWh4 YmCqS1SfKsOKOEctXN6Xs22w4ADAwI4e1rWnoOMlHvNp9Ckyl9azmyRnAU4HX9gCnm87 KpbVgMEA0BqVEjej/+Dx+6QrbUNzSf4o8zjjluAdsft2zRySAGwczkKt2iSTW3nq1YgY cWAQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=lOgZqGC3; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id ks3-20020a170903084300b001a055028d22si495590plb.334.2023.03.13.00.17.15; Mon, 13 Mar 2023 00:17:30 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=lOgZqGC3; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229831AbjCMHO4 (ORCPT + 99 others); Mon, 13 Mar 2023 03:14:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55570 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230017AbjCMHOd (ORCPT ); Mon, 13 Mar 2023 03:14:33 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2294B360A8; Mon, 13 Mar 2023 00:14:23 -0700 (PDT) Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 32D4qSJg000599; Mon, 13 Mar 2023 07:13:53 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=qcppdkim1; bh=PsVrBKdM/JhYSf1jgy6wK+sv0ULCM3EIwVlOEFeyaDM=; b=lOgZqGC3mvY9ScRgdvI8hgVT8kAUv2a0tYwVqpXq3E6zbO7ikhNGIpeEUx44UwzQpHqP PhXKZ2o3mtGIWxp/N38g9H5YyAI88vqbZssOag2TvaoZzC/dKoyYXa6qshq1AocpIsg3 8u9wzRGtw2z6mt4hqzt0JkwvuDQfrbM3steqYFMlNnmFvsU5xHQWvVMmje42E1rH9ugw K7onXzw/L1bG560Ed++r8A5klJxRU8Wr7qzyd2MSUKf/GHg30PvAC1cfvRGZTrL6R1ry qsKjnj3HyAVT/Z4r3+ADfx1FxUMqZRLhI6SL7kXiWOIzuYMbdAyPOECy7Gu74Y+akKql rA== Received: from apblrppmta01.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3p8gnq42hv-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 13 Mar 2023 07:13:53 +0000 Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 32D7DoaS032170; Mon, 13 Mar 2023 07:13:50 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 3p8jqkkym3-1; Mon, 13 Mar 2023 07:13:50 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 32D7DfF3032092; Mon, 13 Mar 2023 07:13:50 GMT Received: from kbajaj-linux.qualcomm.com (kbajaj-linux.qualcomm.com [10.214.66.129]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 32D7Dofw032164; Mon, 13 Mar 2023 07:13:50 +0000 Received: from kbajaj-linux.qualcomm.com (localhost [127.0.0.1]) by kbajaj-linux.qualcomm.com (Postfix) with ESMTP id 3E506D8; Mon, 13 Mar 2023 12:43:49 +0530 (IST) From: Komal Bajaj To: Rob Herring , Bjorn Andersson , Konrad Dybcio , Abel Vesa , Rishabh Bhatnagar , Prakash Ranjan , Krzysztof Kozlowski , Andy Gross Cc: Komal Bajaj , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH 4/5] soc: qcom: Add LLCC support for multi channel DDR Date: Mon, 13 Mar 2023 12:43:24 +0530 Message-Id: <20230313071325.21605-5-quic_kbajaj@quicinc.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230313071325.21605-1-quic_kbajaj@quicinc.com> References: <20230313071325.21605-1-quic_kbajaj@quicinc.com> MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: rpXNHzAvefbvs2akCBvHgDkYg4FIBGLL X-Proofpoint-ORIG-GUID: rpXNHzAvefbvs2akCBvHgDkYg4FIBGLL X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-12_10,2023-03-10_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 bulkscore=0 mlxlogscore=999 spamscore=0 phishscore=0 suspectscore=0 lowpriorityscore=0 priorityscore=1501 adultscore=0 impostorscore=0 clxscore=1015 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2303130058 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1760235985086084972?= X-GMAIL-MSGID: =?utf-8?q?1760235985086084972?= Add LLCC support for multi channel DDR configurations based off of a feature register. Signed-off-by: Komal Bajaj --- drivers/soc/qcom/llcc-qcom.c | 56 ++++++++++++++++++++++++++++-- include/linux/soc/qcom/llcc-qcom.h | 2 ++ 2 files changed, 55 insertions(+), 3 deletions(-) diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 00699a0c047e..696f1f46dd61 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #define ACTIVATE BIT(0) @@ -924,6 +925,40 @@ static int qcom_llcc_cfg_program(struct platform_device *pdev, return ret; } +static int qcom_llcc_get_cfg_index(struct platform_device *pdev, u32 *cfg_index) +{ + struct device *dev = &pdev->dev; + struct resource *ch_res = NULL; + + u32 ch_reg_sz; + u32 ch_reg_off; + u32 val; + int ret = 0; + + ch_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "multi_channel_register"); + if (ch_res) { + if (of_property_read_u32(dev->of_node, "multi-ch-bit-off", &ch_reg_off)) { + dev_err(&pdev->dev, + "Couldn't get offset for multi channel feature register\n"); + return -ENODEV; + } + if (of_property_read_u32_index(dev->of_node, "multi-ch-bit-off", 1, &ch_reg_sz)) { + dev_err(&pdev->dev, + "Couldn't get size of multi channel feature register\n"); + return -ENODEV; + } + + if (qcom_scm_io_readl(ch_res->start, &val)) { + dev_err(&pdev->dev, "Couldn't access multi channel feature register\n"); + ret = -EINVAL; + } + *cfg_index = (val >> ch_reg_off) & ((1 << ch_reg_sz) - 1); + } else + *cfg_index = 0; + + return ret; +} + static int qcom_llcc_remove(struct platform_device *pdev) { /* Set the global pointer to a error code to avoid referencing it */ @@ -956,10 +991,13 @@ static int qcom_llcc_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; int ret, i; struct platform_device *llcc_edac; - const struct qcom_llcc_config *cfg; + const struct qcom_llcc_config *cfg, *entry; const struct llcc_slice_config *llcc_cfg; + u32 sz; + u32 cfg_index; u32 version; + u32 no_of_entries = 0; drv_data = devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL); if (!drv_data) { @@ -999,8 +1037,20 @@ static int qcom_llcc_probe(struct platform_device *pdev) num_banks >>= LLCC_LB_CNT_SHIFT; drv_data->num_banks = num_banks; - llcc_cfg = cfg[0].sct_data; - sz = cfg[0].size; + ret = qcom_llcc_get_cfg_index(pdev, &cfg_index); + if (ret) + goto err; + + for (entry = cfg; entry->sct_data; entry++, no_of_entries++) + ; + if (cfg_index >= no_of_entries) { + ret = -EINVAL; + goto err; + } + + drv_data->cfg_index = cfg_index; + llcc_cfg = cfg[cfg_index].sct_data; + sz = cfg[cfg_index].size; for (i = 0; i < sz; i++) if (llcc_cfg[i].slice_id > drv_data->max_slices) diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h index ad1fd718169d..225891a02f5d 100644 --- a/include/linux/soc/qcom/llcc-qcom.h +++ b/include/linux/soc/qcom/llcc-qcom.h @@ -125,6 +125,7 @@ struct llcc_edac_reg_offset { * @cfg: pointer to the data structure for slice configuration * @edac_reg_offset: Offset of the LLCC EDAC registers * @lock: mutex associated with each slice + * @cfg_index: index of config table if multiple configs present for a target * @cfg_size: size of the config data table * @max_slices: max slices as read from device tree * @num_banks: Number of llcc banks @@ -139,6 +140,7 @@ struct llcc_drv_data { const struct llcc_slice_config *cfg; const struct llcc_edac_reg_offset *edac_reg_offset; struct mutex lock; + u32 cfg_index; u32 cfg_size; u32 max_slices; u32 num_banks; From patchwork Mon Mar 13 07:13:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Komal Bajaj X-Patchwork-Id: 68646 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp1041852wrd; Mon, 13 Mar 2023 00:17:20 -0700 (PDT) X-Google-Smtp-Source: AK7set8sC92iA509ervQkV1ByqDg89qG0OSPnHk9+DGraDX75RxqWrO70GGtPVQv8JVagQOr1eSA X-Received: by 2002:a05:6a20:4c1f:b0:cd:80c:677f with SMTP id fm31-20020a056a204c1f00b000cd080c677fmr26894880pzb.31.1678691839790; Mon, 13 Mar 2023 00:17:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1678691839; cv=none; d=google.com; s=arc-20160816; b=yPFYCJHVb0npWjIHl5MOhW+vTwclgXUkYC1bV7dao92xDiXnXyIsPiyLCjnXbWgM6v 4Hdmjxt6BocofilY01SkeoczrCDOT9JqOEay8x+kXHWIilNCRfM1EO1nAgFz1//+CAvd u4KiSWfjGuF668O2d9BV1sgdLPYcaMbqF4bsFXY0VKJyWSUACeAjd7F42XNgbt2ih67y 93FYmSkIxfxt/0wiZiwgK5qbPAQc7LYfkLX27gf3/ZVATKe/kUkWktbBgETPLVMKHfa4 BPwxEQrfTJKpgmxnhK1kmXn93w0PA7JuKt8EfhhT9zDkJX3QnAQQjCWim+hTVNA8dr2w jOTA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=NUiZjjIrTP5ZgkkmZU3onne1lk3VLupFYt6bYLSlRSg=; b=EVAcmmzdck7OaHaxE3W5aJsZNkXCU1kvUNk1XJ9Tn3inMrmuyhRNrqjMXstZ4TNOMg eVoImw/KwXM0Lz873vwW6HzB9NLpiwPJk/BnlE0zDs9c4xzoQ2LKwdT6BNSseclb935w H210ok+vJb35p5yI6D5EltIiXaxx2tchUDuHWAr4zGR8+FgfOfLZn7LuP6bX38MNZanH q15A1T2e0mBlMbs0aNDKGDsnhSl4ABTVP22ProHuqdEXPSrHTEKYbl0QGFFoxZiFMSR/ /CNrzJ6tZEpk3uQRjJRZ0etSvyS5aV15OJHzNVZ7DA4wpHKsDPyGCUE9rOE4OKi2G57Z jVrA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=PpFXvsYU; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id 20-20020aa79254000000b00593b8c172d8si5661891pfp.200.2023.03.13.00.17.05; Mon, 13 Mar 2023 00:17:19 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=PpFXvsYU; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230038AbjCMHOp (ORCPT + 99 others); Mon, 13 Mar 2023 03:14:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55986 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229988AbjCMHO2 (ORCPT ); Mon, 13 Mar 2023 03:14:28 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D386134F7D; Mon, 13 Mar 2023 00:14:21 -0700 (PDT) Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 32D4k1cr003214; Mon, 13 Mar 2023 07:13:56 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=qcppdkim1; bh=NUiZjjIrTP5ZgkkmZU3onne1lk3VLupFYt6bYLSlRSg=; b=PpFXvsYUbKsBg/JNqXEG0NE62zEVTZVf/DGzhLR4guw5+S13yA25OI2k+36FoUh6dP5Z w6Xf3CE1+OfNHOq1gLYn2AAVfudIxKgNhLllFUEP/Rchz9pySSfm30Rw//8u2Ly/3saC VIaeaPfOG2uaMYEaIOYWJtGXhR+mr4jSUqknMSQPD3kqH6cQbB93iiZ+dJMSci83OXjP nuNuSwEM1P6wbvkpcQVzPvoh8OMsV5er7viNXzNFVPdPgf+khJlNfBk4hKGlRc00qxK8 xqJWzBIFglhEMfS7lNZjd5JAcb5JprxOXEbVR/o/nsZmU1LR0ePTijLDbCuEoF8VSVpO cA== Received: from apblrppmta01.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3p8fbncd6x-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 13 Mar 2023 07:13:55 +0000 Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 32D7DqCS032189; Mon, 13 Mar 2023 07:13:52 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 3p8jqkkymb-1; Mon, 13 Mar 2023 07:13:52 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 32D7DqiI032184; Mon, 13 Mar 2023 07:13:52 GMT Received: from kbajaj-linux.qualcomm.com (kbajaj-linux.qualcomm.com [10.214.66.129]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 32D7DpWk032183; Mon, 13 Mar 2023 07:13:52 +0000 Received: from kbajaj-linux.qualcomm.com (localhost [127.0.0.1]) by kbajaj-linux.qualcomm.com (Postfix) with ESMTP id 1AE17D8; Mon, 13 Mar 2023 12:43:51 +0530 (IST) From: Komal Bajaj To: Rob Herring , Bjorn Andersson , Konrad Dybcio , Abel Vesa , Rishabh Bhatnagar , Prakash Ranjan , Krzysztof Kozlowski , Andy Gross Cc: Komal Bajaj , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: [PATCH 5/5] soc: qcom: llcc: Add QDU1000 and QRU1000 LLCC support Date: Mon, 13 Mar 2023 12:43:25 +0530 Message-Id: <20230313071325.21605-6-quic_kbajaj@quicinc.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230313071325.21605-1-quic_kbajaj@quicinc.com> References: <20230313071325.21605-1-quic_kbajaj@quicinc.com> MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: HXhlDz34mRU-r-llx61NRfpGSnW4Aygm X-Proofpoint-GUID: HXhlDz34mRU-r-llx61NRfpGSnW4Aygm X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-12_10,2023-03-10_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 malwarescore=0 spamscore=0 impostorscore=0 mlxlogscore=999 clxscore=1015 priorityscore=1501 mlxscore=0 phishscore=0 adultscore=0 lowpriorityscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2303130058 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1760235974555436861?= X-GMAIL-MSGID: =?utf-8?q?1760235974555436861?= Add LLCC configuration data for QDU1000 and QRU1000 SoCs and updating macro name for LLCC_DRE to LLCC_ECC as per the latest specification. Signed-off-by: Komal Bajaj --- drivers/soc/qcom/llcc-qcom.c | 65 +++++++++++++++++++++++++++++- include/linux/soc/qcom/llcc-qcom.h | 2 +- 2 files changed, 65 insertions(+), 2 deletions(-) diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 696f1f46dd61..c2c05fcf1f7b 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -188,7 +188,7 @@ static const struct llcc_slice_config sc8280xp_data[] = { { LLCC_MMUHWT, 13, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, { LLCC_DISP, 16, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, { LLCC_AUDHW, 22, 2048, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, - { LLCC_DRE, 26, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, + { LLCC_ECC, 26, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, { LLCC_CVP, 28, 512, 3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, { LLCC_APTCM, 30, 1024, 3, 1, 0x0, 0x1, 1, 0, 0, 1, 0, 0 }, { LLCC_WRCACHE, 31, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, @@ -351,6 +351,36 @@ static const struct llcc_slice_config sm8550_data[] = { {LLCC_VIDVSP, 28, 256, 4, 1, 0xFFFFFF, 0x0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, }; +static const struct llcc_slice_config qdu1000_data_2ch[] = { + {LLCC_MDMHPGRW, 7, 512, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, + {LLCC_MODHW, 9, 256, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, + {LLCC_MDMPNG, 21, 256, 0, 1, 0x3, 0x0, 0, 0, 0, 1, 0, 0, 0 }, + {LLCC_ECC, 26, 512, 3, 1, 0xFFC, 0x0, 0, 0, 0, 0, 1, 0, 0 }, + {LLCC_MODPE, 29, 256, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, + {LLCC_APTCM, 30, 256, 3, 1, 0x0, 0xC, 1, 0, 0, 1, 0, 0, 0 }, + {LLCC_WRCACHE, 31, 128, 1, 1, 0x3, 0x0, 0, 0, 0, 0, 1, 0, 0 }, +}; + +static const struct llcc_slice_config qdu1000_data_4ch[] = { + {LLCC_MDMHPGRW, 7, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, + {LLCC_MODHW, 9, 512, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, + {LLCC_MDMPNG, 21, 512, 0, 1, 0x3, 0x0, 0, 0, 0, 1, 0, 0, 0 }, + {LLCC_ECC, 26, 1024, 3, 1, 0xFFC, 0x0, 0, 0, 0, 0, 1, 0, 0 }, + {LLCC_MODPE, 29, 512, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, + {LLCC_APTCM, 30, 512, 3, 1, 0x0, 0xC, 1, 0, 0, 1, 0, 0, 0 }, + {LLCC_WRCACHE, 31, 256, 1, 1, 0x3, 0x0, 0, 0, 0, 0, 1, 0, 0 }, +}; + +static const struct llcc_slice_config qdu1000_data_8ch[] = { + {LLCC_MDMHPGRW, 7, 2048, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, + {LLCC_MODHW, 9, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, + {LLCC_MDMPNG, 21, 1024, 0, 1, 0x3, 0x0, 0, 0, 0, 1, 0, 0, 0 }, + {LLCC_ECC, 26, 2048, 3, 1, 0xFFC, 0x0, 0, 0, 0, 0, 1, 0, 0 }, + {LLCC_MODPE, 29, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0, 0, 0 }, + {LLCC_APTCM, 30, 1024, 3, 1, 0x0, 0xC, 1, 0, 0, 1, 0, 0, 0 }, + {LLCC_WRCACHE, 31, 512, 1, 1, 0x3, 0x0, 0, 0, 0, 0, 1, 0, 0 }, +}; + static const struct llcc_edac_reg_offset llcc_v1_edac_reg_offset = { .trp_ecc_error_status0 = 0x20344, .trp_ecc_error_status1 = 0x20348, @@ -538,6 +568,38 @@ static const struct qcom_llcc_config sm8550_cfg[] = { { }, }; +static const struct qcom_llcc_config qdu1000_cfg[] = { + { + .sct_data = qdu1000_data_8ch, + .size = ARRAY_SIZE(qdu1000_data_8ch), + .need_llcc_cfg = true, + .reg_offset = llcc_v2_1_reg_offset, + .edac_reg_offset = &llcc_v2_1_edac_reg_offset, + }, + { + .sct_data = qdu1000_data_4ch, + .size = ARRAY_SIZE(qdu1000_data_4ch), + .need_llcc_cfg = true, + .reg_offset = llcc_v2_1_reg_offset, + .edac_reg_offset = &llcc_v2_1_edac_reg_offset, + }, + { + .sct_data = qdu1000_data_4ch, + .size = ARRAY_SIZE(qdu1000_data_4ch), + .need_llcc_cfg = true, + .reg_offset = llcc_v2_1_reg_offset, + .edac_reg_offset = &llcc_v2_1_edac_reg_offset, + }, + { + .sct_data = qdu1000_data_2ch, + .size = ARRAY_SIZE(qdu1000_data_2ch), + .need_llcc_cfg = true, + .reg_offset = llcc_v2_1_reg_offset, + .edac_reg_offset = &llcc_v2_1_edac_reg_offset, + }, + { }, +}; + static struct llcc_drv_data *drv_data = (void *) -EPROBE_DEFER; /** @@ -1110,6 +1172,7 @@ static const struct of_device_id qcom_llcc_of_match[] = { { .compatible = "qcom,sm8350-llcc", .data = sm8350_cfg }, { .compatible = "qcom,sm8450-llcc", .data = sm8450_cfg }, { .compatible = "qcom,sm8550-llcc", .data = sm8550_cfg }, + { .compatible = "qcom,qdu1000-llcc", .data = qdu1000_cfg}, { } }; MODULE_DEVICE_TABLE(of, qcom_llcc_of_match); diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h index 225891a02f5d..150b2836c8b9 100644 --- a/include/linux/soc/qcom/llcc-qcom.h +++ b/include/linux/soc/qcom/llcc-qcom.h @@ -30,7 +30,7 @@ #define LLCC_NPU 23 #define LLCC_WLHW 24 #define LLCC_PIMEM 25 -#define LLCC_DRE 26 +#define LLCC_ECC 26 #define LLCC_CVP 28 #define LLCC_MODPE 29 #define LLCC_APTCM 30