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Suggested-by: Bjorn Andersson Signed-off-by: Krishna Kurapati --- .../devicetree/bindings/usb/snps,dwc3.yaml | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml index be36956af53b..96701eb5a17c 100644 --- a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml +++ b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml @@ -81,15 +81,16 @@ properties: phys: minItems: 1 - maxItems: 2 + maxItems: 8 phy-names: minItems: 1 - maxItems: 2 - items: - enum: - - usb2-phy - - usb3-phy + maxItems: 8 + oneOf: + - items: + enum: [ usb2-phy, usb3-phy ] + - items: + pattern: "^usb[23]-port[0-3]$" power-domains: description: From patchwork Fri Mar 10 16:34:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Kurapati X-Patchwork-Id: 67571 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp980405wrd; Fri, 10 Mar 2023 08:52:58 -0800 (PST) X-Google-Smtp-Source: AK7set/cHun5DXGBTg591H8dUzpv2RyFplKxS3bwHof0ZNhVMl9BiaNWUrmmTSUHvi/q/WoGy0rg X-Received: by 2002:a05:6a20:3d0b:b0:c9:9312:5f1d with SMTP id y11-20020a056a203d0b00b000c993125f1dmr34616676pzi.4.1678467178065; Fri, 10 Mar 2023 08:52:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1678467178; cv=none; d=google.com; s=arc-20160816; b=uV4QHngy6tKfhqtq8QIAypbrz34KJQh0PWNr7D6as/OkISVPLqZ11m8bhsTZFmur8i URpZjkHJ8Y4Bm7zE62WGiuTAqatyRm8auc45cAHYwQLwJmwbgGHNbeBLjECVlUo8h6Xc s36YS2vf2ZwAw335dVIB4v4rHJspO6tanNrjtwB121mgT7kC+3DlWRA8h9IG6ZUxNkrv 31BO4w28iGsACQB8Kljt6FTe/gH1pq0RmN1kwwhVWGBuR8fR0kAGya+xOdG8G4vhO6yC TG93RqItEuq1dALdoZfchC1UFOVfRJyviG0n03Og9BEk4fBFleRyF9KleiWaNbAnBULz +m/A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=GD0GBOWSy1Lo2I8vj4R9ejMOUZ8Vuu12h4M1yNOA7yE=; b=POZ3LAS8ExeQfufpjRsGaC37WPMUFaAzS+gEcS545fGue/XKi6n7PmWIEpm/nTbwZs aVYHa37gbDoYaObVCnSgDw1SOZZWLA+8b2GNXc2E3hfuaQ5HnvZkVxxYju+vcrBapcme 6BE9N+yK6qiAg/IbmwAMgjy4iz6RDxpU7vBZbEfwL8SDo4uXBFFAZSHdNB2Z0A2NtmRj tFQka5UttyTBvm0potEksw+vlrq+RE0Prfra9rFZecSaezZwi5WYkeutTYZA+iuifon3 dvH6tDudNSpzHp+J+cjpe30LUAMWr9mdLaxYY3Yq8XGjzb8ei8pb287+TFALLGpUXoyq GMlQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=NqdkcLbb; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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Temporarily map XHCI address space for host-only controllers and parse XHCI Extended Capabilities registers to read number of physical usb ports connected to the multiport controller (presuming each port is at least HS capable) and extract info on how many of these ports are Super Speed capable. Signed-off-by: Krishna Kurapati --- drivers/usb/dwc3/core.c | 75 +++++++++++++++++++++++++++++++++++++++++ drivers/usb/dwc3/core.h | 9 +++++ 2 files changed, 84 insertions(+) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 476b63618511..076c0f8a4441 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -37,6 +37,7 @@ #include "core.h" #include "gadget.h" #include "io.h" +#include "../host/xhci.h" #include "debug.h" @@ -1750,6 +1751,65 @@ static struct extcon_dev *dwc3_get_extcon(struct dwc3 *dwc) return edev; } +static int dwc3_read_port_info(struct dwc3 *dwc, struct resource *res) +{ + void __iomem *regs; + struct resource dwc_res; + u32 offset; + u32 temp; + u8 major_revision; + int ret = 0; + + /* + * Remap xHCI address space to access XHCI ext cap regs, + * since it is needed to get port info. + */ + dwc_res = *res; + dwc_res.start += 0; + dwc_res.end = dwc->xhci_resources[0].start + + DWC3_XHCI_REGS_END; + + regs = ioremap(dwc_res.start, resource_size(&dwc_res)); + if (IS_ERR(regs)) + return PTR_ERR(regs); + + offset = xhci_find_next_ext_cap(regs, 0, + XHCI_EXT_CAPS_PROTOCOL); + while (offset) { + temp = readl(regs + offset); + major_revision = XHCI_EXT_PORT_MAJOR(temp); + + temp = readl(regs + offset + 0x08); + if (major_revision == 0x03) { + dwc->num_ss_ports += XHCI_EXT_PORT_COUNT(temp); + } else if (major_revision <= 0x02) { + dwc->num_ports += XHCI_EXT_PORT_COUNT(temp); + } else { + dev_err(dwc->dev, "port revision seems wrong\n"); + ret = -EINVAL; + goto unmap_reg; + } + + offset = xhci_find_next_ext_cap(regs, offset, + XHCI_EXT_CAPS_PROTOCOL); + } + + temp = readl(regs + DWC3_XHCI_HCSPARAMS1); + if (HCS_MAX_PORTS(temp) != (dwc->num_ss_ports + dwc->num_ports)) { + dev_err(dwc->dev, "inconsistency in port info\n"); + ret = -EINVAL; + goto unmap_reg; + } + + dev_info(dwc->dev, + "num-ports: %d ss-capable: %d\n", dwc->num_ports, dwc->num_ss_ports); + +unmap_reg: + iounmap(regs); + return ret; +} + static int dwc3_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -1757,6 +1817,7 @@ static int dwc3_probe(struct platform_device *pdev) struct dwc3 *dwc; int ret; + unsigned int hw_mode; void __iomem *regs; @@ -1880,6 +1941,20 @@ static int dwc3_probe(struct platform_device *pdev) goto disable_clks; } + /* + * Currently DWC3 controllers that are host-only capable + * support Multiport. + */ + hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); + if (hw_mode == DWC3_GHWPARAMS0_MODE_HOST) { + ret = dwc3_read_port_info(dwc, res); + if (ret) + goto disable_clks; + } else { + dwc->num_ports = 1; + dwc->num_ss_ports = 1; + } + spin_lock_init(&dwc->lock); mutex_init(&dwc->mutex); diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 582ebd9cf9c2..74386d6a0277 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -35,6 +35,9 @@ #define DWC3_MSG_MAX 500 +/* XHCI Reg constants */ +#define DWC3_XHCI_HCSPARAMS1 0x04 + /* Global constants */ #define DWC3_PULL_UP_TIMEOUT 500 /* ms */ #define DWC3_BOUNCE_SIZE 1024 /* size of a superspeed bulk */ @@ -1023,6 +1026,10 @@ struct dwc3_scratchpad_array { * @usb_psy: pointer to power supply interface. * @usb2_phy: pointer to USB2 PHY * @usb3_phy: pointer to USB3 PHY + * @num_ports: Indicates the number of physical USB ports present on HW + * presuming each port is at least HS capable + * @num_ss_ports: Indicates the number of USB ports present on HW that are + * SS Capable * @usb2_generic_phy: pointer to USB2 PHY * @usb3_generic_phy: pointer to USB3 PHY * @phys_ready: flag to indicate that PHYs are ready @@ -1158,6 +1165,8 @@ struct dwc3 { struct usb_phy *usb2_phy; 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Trying to setup them up during core_init leads to a crash. For DRD/Peripheral supported controllers, event buffer setup is done again in gadget_pullup. Skip setup or cleanup of event buffers if controller is host-only capable. Signed-off-by: Krishna Kurapati --- drivers/usb/dwc3/core.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 076c0f8a4441..1ca9fa40a66e 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -840,7 +840,11 @@ static void dwc3_clk_disable(struct dwc3 *dwc) static void dwc3_core_exit(struct dwc3 *dwc) { - dwc3_event_buffers_cleanup(dwc); + unsigned int hw_mode; + + hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); + if (hw_mode != DWC3_GHWPARAMS0_MODE_HOST) + dwc3_event_buffers_cleanup(dwc); usb_phy_set_suspend(dwc->usb2_phy, 1); usb_phy_set_suspend(dwc->usb3_phy, 1); @@ -1177,10 +1181,12 @@ static int dwc3_core_init(struct dwc3 *dwc) if (ret < 0) goto err3; - ret = dwc3_event_buffers_setup(dwc); - if (ret) { - dev_err(dwc->dev, "failed to setup event buffers\n"); - goto err4; + if (hw_mode != DWC3_GHWPARAMS0_MODE_HOST) { + ret = dwc3_event_buffers_setup(dwc); + if (ret) { + dev_err(dwc->dev, "failed to setup event buffers\n"); + goto err4; + } } /* @@ -2008,7 +2014,9 @@ static int dwc3_probe(struct platform_device *pdev) err5: dwc3_debugfs_exit(dwc); - dwc3_event_buffers_cleanup(dwc); + + if (hw_mode != DWC3_GHWPARAMS0_MODE_HOST) + dwc3_event_buffers_cleanup(dwc); usb_phy_set_suspend(dwc->usb2_phy, 1); usb_phy_set_suspend(dwc->usb3_phy, 1); From patchwork Fri Mar 10 16:34:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Kurapati X-Patchwork-Id: 67553 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp974296wrd; Fri, 10 Mar 2023 08:40:28 -0800 (PST) X-Google-Smtp-Source: AK7set8D5qBuL2QYQZ9xRPxsX2LQ3u0bt2UboACcK3wJL9d2U9H9yENDDLt3njUzN5vnjCJ4PxaL X-Received: by 2002:a05:6a20:12ce:b0:cc:b73a:1079 with SMTP id v14-20020a056a2012ce00b000ccb73a1079mr29413675pzg.62.1678466427867; Fri, 10 Mar 2023 08:40:27 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1678466427; cv=none; d=google.com; s=arc-20160816; b=Kt0iSBVvN/sI8J/5zrVrW15FEZRw8QtuVyNgb/mcIME8jHaqgyuN2Dj+cvdLO/ZtDs aj0Lbew/A3r/9ttlK/C3dn2fG1g0Kw7BKzXDgSmABqdIOdd9T/xyRZuiNrlB+PMWpwwO MxXomVzXCoRsoiaoew/k8v5KeQw5rkPTHU42Zf0/Hw28Fl2HfySP/UL9iVNEbaJlYdOs 0AclR1CZ6K304pgLC4Ta8tb1iCAVclNfMttPMRX38MurUO4jGcaopJjo7c5QsbZMcJYM COqNN1lrrGX+8sTHJyo0XZiUYqss2NsNbaH+VmRdCpc9ma0MlYHBB0k4UJvaYGi+vpcO rhig== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=gNJgD8+kKGyr/xNT7x2Nvn4FL+TStJnSt6aGX4mRq/4=; b=QhalnYyo8j92CekXPhNwZ01sOZ6C4Bq2PK4syt9kGspr5OtA5vvmcP00RQCjz1JZft yV3taOXGXO1J+B+ZcZlkQTLRDFfjHv0CUJoNah5au0Ju4+OHR55Wkd3xpnlkgTomHR8c rHiFxjwnSJV6sHLqx+8KNl6nNFSHuuEHClr9XR4S1aINqMCtGFNe91zvDeysEjOj8G4G czxsE89zijYt5VI/sRmlscQ9Sj9kqdjYTLVMwK56OTPier3HrJ2wR2yUhpnCvrZw/7Fl 7rqM8Mhk5etbwyhjbTNL9DFa+caMsl9hd/KJyl6H12E8v9DudMXCgO1NC4lpSzgAMu6u /FEQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=LGTuue+P; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id x184-20020a6386c1000000b005030a000860si171586pgd.602.2023.03.10.08.40.14; Fri, 10 Mar 2023 08:40:27 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=LGTuue+P; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231710AbjCJQhq (ORCPT + 99 others); Fri, 10 Mar 2023 11:37:46 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39244 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229846AbjCJQhQ (ORCPT ); Fri, 10 Mar 2023 11:37:16 -0500 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F051228E42; Fri, 10 Mar 2023 08:35:14 -0800 (PST) Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 32AEj8nG007296; Fri, 10 Mar 2023 16:35:03 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=gNJgD8+kKGyr/xNT7x2Nvn4FL+TStJnSt6aGX4mRq/4=; b=LGTuue+PdRvz2pAf6QncMu7VjaEzM1sbptPQh27UfnmU6l+0fWWbWwYhmQrsTh/MTm88 z8RDM+jpfH2tl8sS7Pucb45PtYTZEVr/kFl5kTZsLULh5Q+AS9llfyEthtLUiIO7xXxJ HFFMklUZOmpsVfAaxtxUUXl7kIdgs/Z77r9/bDYCO06DQeV1Zgx3XLSb+fGp1kllPkBR PPz+AsE+1WMdbUYuCJZioOm1/ppuxychBXyvDTrx9DPwJSHJf8AkjYIDIQP1fRUjnMnv B7KOSBO/tZUfB/ddeNt8RrIv2qLmuwN4Lwd3gzth5XiVCE1/VoNfT4solfe/MgISMTeI yg== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3p85rhrc9j-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 10 Mar 2023 16:35:02 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 32AGZ1cd030226 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 10 Mar 2023 16:35:01 GMT Received: from hu-kriskura-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Fri, 10 Mar 2023 08:34:55 -0800 From: Krishna Kurapati To: Thinh Nguyen , Greg Kroah-Hartman , Philipp Zabel , "Andy Gross" , Bjorn Andersson , "Konrad Dybcio" , Rob Herring , Krzysztof Kozlowski , Felipe Balbi CC: , , , , , , , , , , , Krishna Kurapati Subject: [PATCH 4/8] usb: dwc3: core: Refactor PHY logic to support Multiport Controller Date: Fri, 10 Mar 2023 22:04:16 +0530 Message-ID: <20230310163420.7582-5-quic_kriskura@quicinc.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230310163420.7582-1-quic_kriskura@quicinc.com> References: <20230310163420.7582-1-quic_kriskura@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: IfKzgKqNnEAK6DIvjRhKLNa1Z5JrihSZ X-Proofpoint-ORIG-GUID: IfKzgKqNnEAK6DIvjRhKLNa1Z5JrihSZ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-10_07,2023-03-10_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 mlxscore=0 malwarescore=0 phishscore=0 mlxlogscore=914 bulkscore=0 spamscore=0 adultscore=0 suspectscore=0 impostorscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2303100130 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759999612958019375?= X-GMAIL-MSGID: =?utf-8?q?1759999612958019375?= Currently the DWC3 driver supports only single port controller which requires at most one HS and one SS PHY. But the DWC3 USB controller can be connected to multiple ports and each port can have their own PHYs. Each port of the multiport controller can either be HS+SS capable or HS only capable Proper quantification of them is required to modify GUSB2PHYCFG and GUSB3PIPECTL registers appropriately. Add support for detecting, obtaining and configuring phy's supported by a multiport controller and limit the max number of ports supported to 4. Signed-off-by: Harsh Agarwal Signed-off-by: Krishna Kurapati --- drivers/usb/dwc3/core.c | 279 +++++++++++++++++++++++++++++----------- drivers/usb/dwc3/core.h | 11 +- drivers/usb/dwc3/drd.c | 13 +- 3 files changed, 219 insertions(+), 84 deletions(-) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 1ca9fa40a66e..936f1cfd4770 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -122,6 +122,7 @@ static void __dwc3_set_mode(struct work_struct *work) struct dwc3 *dwc = work_to_dwc(work); unsigned long flags; int ret; + int i; u32 reg; u32 desired_dr_role; @@ -201,8 +202,10 @@ static void __dwc3_set_mode(struct work_struct *work) } else { if (dwc->usb2_phy) otg_set_vbus(dwc->usb2_phy->otg, true); - phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); - phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); + for (i = 0; i < dwc->num_ports; i++) { + phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST); + phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST); + } if (dwc->dis_split_quirk) { reg = dwc3_readl(dwc->regs, DWC3_GUCTL3); reg |= DWC3_GUCTL3_SPLITDISABLE; @@ -217,8 +220,8 @@ static void __dwc3_set_mode(struct work_struct *work) if (dwc->usb2_phy) otg_set_vbus(dwc->usb2_phy->otg, false); - phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); - phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE); + phy_set_mode(dwc->usb2_generic_phy[0], PHY_MODE_USB_DEVICE); + phy_set_mode(dwc->usb3_generic_phy[0], PHY_MODE_USB_DEVICE); ret = dwc3_gadget_init(dwc); if (ret) @@ -660,22 +663,14 @@ static int dwc3_core_ulpi_init(struct dwc3 *dwc) return ret; } -/** - * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core - * @dwc: Pointer to our controller context structure - * - * Returns 0 on success. The USB PHY interfaces are configured but not - * initialized. The PHY interfaces and the PHYs get initialized together with - * the core in dwc3_core_init. - */ -static int dwc3_phy_setup(struct dwc3 *dwc) +static int dwc3_ss_phy_setup(struct dwc3 *dwc, int index) { unsigned int hw_mode; u32 reg; hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); - reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); + reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(index)); /* * Make sure UX_EXIT_PX is cleared as that causes issues with some @@ -730,9 +725,19 @@ static int dwc3_phy_setup(struct dwc3 *dwc) if (dwc->dis_del_phy_power_chg_quirk) reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE; - dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); + dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(index), reg); + + return 0; +} + +static int dwc3_hs_phy_setup(struct dwc3 *dwc, int index) +{ + unsigned int hw_mode; + u32 reg; - reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); + hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); + + reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(index)); /* Select the HS PHY interface */ switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) { @@ -744,7 +749,7 @@ static int dwc3_phy_setup(struct dwc3 *dwc) } else if (dwc->hsphy_interface && !strncmp(dwc->hsphy_interface, "ulpi", 4)) { reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI; - dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); + dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(index), reg); } else { /* Relying on default value. */ if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI)) @@ -801,7 +806,35 @@ static int dwc3_phy_setup(struct dwc3 *dwc) if (dwc->dis_u2_freeclk_exists_quirk || dwc->gfladj_refclk_lpm_sel) reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS; - dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); + dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(index), reg); + + return 0; +} + +/** + * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core + * @dwc: Pointer to our controller context structure + * + * Returns 0 on success. The USB PHY interfaces are configured but not + * initialized. The PHY interfaces and the PHYs get initialized together with + * the core in dwc3_core_init. + */ +static int dwc3_phy_setup(struct dwc3 *dwc) +{ + int i; + int ret; + + for (i = 0; i < dwc->num_ss_ports; i++) { + ret = dwc3_ss_phy_setup(dwc, i); + if (ret) + return ret; + } + + for (i = 0; i < dwc->num_ports; i++) { + ret = dwc3_hs_phy_setup(dwc, i); + if (ret) + return ret; + } return 0; } @@ -840,6 +873,7 @@ static void dwc3_clk_disable(struct dwc3 *dwc) static void dwc3_core_exit(struct dwc3 *dwc) { + int i; unsigned int hw_mode; hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); @@ -848,13 +882,18 @@ static void dwc3_core_exit(struct dwc3 *dwc) usb_phy_set_suspend(dwc->usb2_phy, 1); usb_phy_set_suspend(dwc->usb3_phy, 1); - phy_power_off(dwc->usb2_generic_phy); - phy_power_off(dwc->usb3_generic_phy); + for (i = 0; i < dwc->num_ports; i++) { + phy_power_off(dwc->usb2_generic_phy[i]); + phy_power_off(dwc->usb3_generic_phy[i]); + } usb_phy_shutdown(dwc->usb2_phy); usb_phy_shutdown(dwc->usb3_phy); - phy_exit(dwc->usb2_generic_phy); - phy_exit(dwc->usb3_generic_phy); + + for (i = 0; i < dwc->num_ports; i++) { + phy_exit(dwc->usb2_generic_phy[i]); + phy_exit(dwc->usb3_generic_phy[i]); + } dwc3_clk_disable(dwc); reset_control_assert(dwc->reset); @@ -1090,6 +1129,7 @@ static int dwc3_core_init(struct dwc3 *dwc) unsigned int hw_mode; u32 reg; int ret; + int i, j; hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); @@ -1124,14 +1164,27 @@ static int dwc3_core_init(struct dwc3 *dwc) usb_phy_init(dwc->usb2_phy); usb_phy_init(dwc->usb3_phy); - ret = phy_init(dwc->usb2_generic_phy); - if (ret < 0) - goto err0a; - ret = phy_init(dwc->usb3_generic_phy); - if (ret < 0) { - phy_exit(dwc->usb2_generic_phy); - goto err0a; + for (i = 0; i < dwc->num_ports; i++) { + ret = phy_init(dwc->usb2_generic_phy[i]); + if (ret < 0) { + /* clean up prior initialized HS PHYs */ + for (j = 0; j < i; j++) + phy_exit(dwc->usb2_generic_phy[j]); + goto err0a; + } + } + + for (i = 0; i < dwc->num_ports; i++) { + ret = phy_init(dwc->usb3_generic_phy[i]); + if (ret < 0) { + /* clean up prior initialized SS PHYs */ + for (j = 0; j < i; j++) + phy_exit(dwc->usb3_generic_phy[j]); + for (j = 0; j < dwc->num_ports; j++) + phy_exit(dwc->usb2_generic_phy[j]); + goto err0a; + } } ret = dwc3_core_soft_reset(dwc); @@ -1141,15 +1194,19 @@ static int dwc3_core_init(struct dwc3 *dwc) if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD && !DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) { if (!dwc->dis_u3_susphy_quirk) { - reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); - reg |= DWC3_GUSB3PIPECTL_SUSPHY; - dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); + for (i = 0; i < dwc->num_ss_ports; i++) { + reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(i)); + reg |= DWC3_GUSB3PIPECTL_SUSPHY; + dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(i), reg); + } } if (!dwc->dis_u2_susphy_quirk) { - reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); - reg |= DWC3_GUSB2PHYCFG_SUSPHY; - dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); + for (i = 0; i < dwc->num_ports; i++) { + reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i)); + reg |= DWC3_GUSB2PHYCFG_SUSPHY; + dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg); + } } } @@ -1173,13 +1230,24 @@ static int dwc3_core_init(struct dwc3 *dwc) usb_phy_set_suspend(dwc->usb2_phy, 0); usb_phy_set_suspend(dwc->usb3_phy, 0); - ret = phy_power_on(dwc->usb2_generic_phy); - if (ret < 0) - goto err2; - ret = phy_power_on(dwc->usb3_generic_phy); - if (ret < 0) - goto err3; + for (i = 0; i < dwc->num_ports; i++) { + ret = phy_power_on(dwc->usb2_generic_phy[i]); + if (ret < 0) { + for (j = 0; j < i; j++) + phy_power_off(dwc->usb2_generic_phy[j]); + goto err2; + } + } + + for (i = 0; i < dwc->num_ports; i++) { + ret = phy_power_on(dwc->usb3_generic_phy[i]); + if (ret < 0) { + for (j = 0; j < i; j++) + phy_power_off(dwc->usb3_generic_phy[j]); + goto err3; + } + } if (hw_mode != DWC3_GHWPARAMS0_MODE_HOST) { ret = dwc3_event_buffers_setup(dwc); @@ -1304,10 +1372,12 @@ static int dwc3_core_init(struct dwc3 *dwc) return 0; err4: - phy_power_off(dwc->usb3_generic_phy); + for (i = 0; i < dwc->num_ports; i++) + phy_power_off(dwc->usb3_generic_phy[i]); err3: - phy_power_off(dwc->usb2_generic_phy); + for (i = 0; i < dwc->num_ports; i++) + phy_power_off(dwc->usb2_generic_phy[i]); err2: usb_phy_set_suspend(dwc->usb2_phy, 1); @@ -1316,8 +1386,11 @@ static int dwc3_core_init(struct dwc3 *dwc) err1: usb_phy_shutdown(dwc->usb2_phy); usb_phy_shutdown(dwc->usb3_phy); - phy_exit(dwc->usb2_generic_phy); - phy_exit(dwc->usb3_generic_phy); + + for (i = 0; i < dwc->num_ports; i++) { + phy_exit(dwc->usb2_generic_phy[i]); + phy_exit(dwc->usb3_generic_phy[i]); + } err0a: dwc3_ulpi_exit(dwc); @@ -1326,6 +1399,38 @@ static int dwc3_core_init(struct dwc3 *dwc) return ret; } +static int dwc3_get_multiport_phys(struct dwc3 *dwc) +{ + int ret; + struct device *dev = dwc->dev; + int i; + char phy_name[11]; + + for (i = 0; i < dwc->num_ports; i++) { + sprintf(phy_name, "usb2-port%d", i); + dwc->usb2_generic_phy[i] = devm_phy_get(dev, phy_name); + if (IS_ERR(dwc->usb2_generic_phy[i])) { + ret = PTR_ERR(dwc->usb2_generic_phy[i]); + if (ret == -ENOSYS || ret == -ENODEV) + dwc->usb2_generic_phy[i] = NULL; + else + return dev_err_probe(dev, ret, "usb2 phy: %s not configured\n", phy_name); + } + + sprintf(phy_name, "usb3-port%d", i); + dwc->usb3_generic_phy[i] = devm_phy_get(dev, phy_name); + if (IS_ERR(dwc->usb3_generic_phy[i])) { + ret = PTR_ERR(dwc->usb3_generic_phy[i]); + if (ret == -ENOSYS || ret == -ENODEV) + dwc->usb3_generic_phy[i] = NULL; + else + return dev_err_probe(dev, ret, "usb3 phy: %s not configured\n", phy_name); + } + } + + return 0; +} + static int dwc3_core_get_phy(struct dwc3 *dwc) { struct device *dev = dwc->dev; @@ -1356,20 +1461,24 @@ static int dwc3_core_get_phy(struct dwc3 *dwc) return dev_err_probe(dev, ret, "no usb3 phy configured\n"); } - dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy"); - if (IS_ERR(dwc->usb2_generic_phy)) { - ret = PTR_ERR(dwc->usb2_generic_phy); + if (dwc->num_ports > 1) + return dwc3_get_multiport_phys(dwc); + + + dwc->usb2_generic_phy[0] = devm_phy_get(dev, "usb2-phy"); + if (IS_ERR(dwc->usb2_generic_phy[0])) { + ret = PTR_ERR(dwc->usb2_generic_phy[0]); if (ret == -ENOSYS || ret == -ENODEV) - dwc->usb2_generic_phy = NULL; + dwc->usb2_generic_phy[0] = NULL; else return dev_err_probe(dev, ret, "no usb2 phy configured\n"); } - dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy"); - if (IS_ERR(dwc->usb3_generic_phy)) { - ret = PTR_ERR(dwc->usb3_generic_phy); + dwc->usb3_generic_phy[0] = devm_phy_get(dev, "usb3-phy"); + if (IS_ERR(dwc->usb3_generic_phy[0])) { + ret = PTR_ERR(dwc->usb3_generic_phy[0]); if (ret == -ENOSYS || ret == -ENODEV) - dwc->usb3_generic_phy = NULL; + dwc->usb3_generic_phy[0] = NULL; else return dev_err_probe(dev, ret, "no usb3 phy configured\n"); } @@ -1381,6 +1490,7 @@ static int dwc3_core_init_mode(struct dwc3 *dwc) { struct device *dev = dwc->dev; int ret; + int i; switch (dwc->dr_mode) { case USB_DR_MODE_PERIPHERAL: @@ -1388,8 +1498,8 @@ static int dwc3_core_init_mode(struct dwc3 *dwc) if (dwc->usb2_phy) otg_set_vbus(dwc->usb2_phy->otg, false); - phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); - phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE); + phy_set_mode(dwc->usb2_generic_phy[0], PHY_MODE_USB_DEVICE); + phy_set_mode(dwc->usb3_generic_phy[0], PHY_MODE_USB_DEVICE); ret = dwc3_gadget_init(dwc); if (ret) @@ -1400,8 +1510,10 @@ static int dwc3_core_init_mode(struct dwc3 *dwc) if (dwc->usb2_phy) otg_set_vbus(dwc->usb2_phy->otg, true); - phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); - phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); + for (i = 0; i < dwc->num_ports; i++) { + phy_set_mode(dwc->usb2_generic_phy[i], PHY_MODE_USB_HOST); + phy_set_mode(dwc->usb3_generic_phy[i], PHY_MODE_USB_HOST); + } ret = dwc3_host_init(dwc); if (ret) @@ -1823,6 +1935,7 @@ static int dwc3_probe(struct platform_device *pdev) struct dwc3 *dwc; int ret; + int i; unsigned int hw_mode; void __iomem *regs; @@ -2020,13 +2133,19 @@ static int dwc3_probe(struct platform_device *pdev) usb_phy_set_suspend(dwc->usb2_phy, 1); usb_phy_set_suspend(dwc->usb3_phy, 1); - phy_power_off(dwc->usb2_generic_phy); - phy_power_off(dwc->usb3_generic_phy); + + for (i = 0; i < dwc->num_ports; i++) { + phy_power_off(dwc->usb2_generic_phy[i]); + phy_power_off(dwc->usb3_generic_phy[i]); + } usb_phy_shutdown(dwc->usb2_phy); usb_phy_shutdown(dwc->usb3_phy); - phy_exit(dwc->usb2_generic_phy); - phy_exit(dwc->usb3_generic_phy); + + for (i = 0; i < dwc->num_ports; i++) { + phy_exit(dwc->usb2_generic_phy[i]); + phy_exit(dwc->usb3_generic_phy[i]); + } dwc3_ulpi_exit(dwc); @@ -2108,6 +2227,7 @@ static int dwc3_core_init_for_resume(struct dwc3 *dwc) static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg) { + int i; unsigned long flags; u32 reg; @@ -2128,17 +2248,21 @@ static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg) /* Let controller to suspend HSPHY before PHY driver suspends */ if (dwc->dis_u2_susphy_quirk || dwc->dis_enblslpm_quirk) { - reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); - reg |= DWC3_GUSB2PHYCFG_ENBLSLPM | - DWC3_GUSB2PHYCFG_SUSPHY; - dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); + for (i = 0; i < dwc->num_ports; i++) { + reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i)); + reg |= DWC3_GUSB2PHYCFG_ENBLSLPM | + DWC3_GUSB2PHYCFG_SUSPHY; + dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg); + } /* Give some time for USB2 PHY to suspend */ usleep_range(5000, 6000); } - phy_pm_runtime_put_sync(dwc->usb2_generic_phy); - phy_pm_runtime_put_sync(dwc->usb3_generic_phy); + for (i = 0; i < dwc->num_ports; i++) { + phy_pm_runtime_put_sync(dwc->usb2_generic_phy[i]); + phy_pm_runtime_put_sync(dwc->usb3_generic_phy[i]); + } break; case DWC3_GCTL_PRTCAP_OTG: /* do nothing during runtime_suspend */ @@ -2167,6 +2291,7 @@ static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg) { unsigned long flags; int ret; + int i; u32 reg; switch (dwc->current_dr_role) { @@ -2187,17 +2312,21 @@ static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg) break; } /* Restore GUSB2PHYCFG bits that were modified in suspend */ - reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); - if (dwc->dis_u2_susphy_quirk) - reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; + for (i = 0; i < dwc->num_ports; i++) { + reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(i)); + if (dwc->dis_u2_susphy_quirk) + reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; - if (dwc->dis_enblslpm_quirk) - reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; + if (dwc->dis_enblslpm_quirk) + reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; - dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); + dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(i), reg); + } - phy_pm_runtime_get_sync(dwc->usb2_generic_phy); - phy_pm_runtime_get_sync(dwc->usb3_generic_phy); + for (i = 0; i < dwc->num_ports; i++) { + phy_pm_runtime_get_sync(dwc->usb2_generic_phy[i]); + phy_pm_runtime_get_sync(dwc->usb3_generic_phy[i]); + } break; case DWC3_GCTL_PRTCAP_OTG: /* nothing to do on runtime_resume */ diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 74386d6a0277..e63e6b514d0d 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -35,6 +35,9 @@ #define DWC3_MSG_MAX 500 +/* Numer of ports supported by a multiport controller */ +#define MAX_PORTS_SUPPORTED 4 + /* XHCI Reg constants */ #define DWC3_XHCI_HCSPARAMS1 0x04 @@ -1030,8 +1033,8 @@ struct dwc3_scratchpad_array { * presuming each port is atleast HS capable * @num_ss_ports: Indicates the number of USB ports present on HW that are * SS Capable - * @usb2_generic_phy: pointer to USB2 PHY - * @usb3_generic_phy: pointer to USB3 PHY + * @usb2_generic_phy: pointer to array of USB2 PHY + * @usb3_generic_phy: pointer to array of USB3 PHY * @phys_ready: flag to indicate that PHYs are ready * @ulpi: pointer to ulpi interface * @ulpi_ready: flag to indicate that ULPI is initialized @@ -1167,8 +1170,8 @@ struct dwc3 { u32 num_ports; u32 num_ss_ports; - struct phy *usb2_generic_phy; - struct phy *usb3_generic_phy; + struct phy *usb2_generic_phy[MAX_PORTS_SUPPORTED]; + struct phy *usb3_generic_phy[MAX_PORTS_SUPPORTED]; bool phys_ready; diff --git a/drivers/usb/dwc3/drd.c b/drivers/usb/dwc3/drd.c index 039bf241769a..b34260b627fe 100644 --- a/drivers/usb/dwc3/drd.c +++ b/drivers/usb/dwc3/drd.c @@ -328,6 +328,7 @@ static void dwc3_otg_device_exit(struct dwc3 *dwc) void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus) { int ret; + int i; u32 reg; int id; unsigned long flags; @@ -386,9 +387,11 @@ void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus) } else { if (dwc->usb2_phy) otg_set_vbus(dwc->usb2_phy->otg, true); - if (dwc->usb2_generic_phy) - phy_set_mode(dwc->usb2_generic_phy, - PHY_MODE_USB_HOST); + for (i = 0; i < dwc->num_ports; i++) { + if (dwc->usb2_generic_phy[i]) + phy_set_mode(dwc->usb2_generic_phy[i], + PHY_MODE_USB_HOST); + } } break; case DWC3_OTG_ROLE_DEVICE: @@ -400,8 +403,8 @@ void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus) if (dwc->usb2_phy) otg_set_vbus(dwc->usb2_phy->otg, false); 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Add support for configuring PWR_EVENT_IRQ's for all the ports during suspend/resume. Signed-off-by: Krishna Kurapati --- drivers/usb/dwc3/dwc3-qcom.c | 28 ++++++++++++++++++++++------ 1 file changed, 22 insertions(+), 6 deletions(-) diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c index 959fc925ca7c..0396f3e9bbe9 100644 --- a/drivers/usb/dwc3/dwc3-qcom.c +++ b/drivers/usb/dwc3/dwc3-qcom.c @@ -37,7 +37,10 @@ #define PIPE3_PHYSTATUS_SW BIT(3) #define PIPE_UTMI_CLK_DIS BIT(8) -#define PWR_EVNT_IRQ_STAT_REG 0x58 +#define PWR_EVNT_IRQ1_STAT_REG 0x58 +#define PWR_EVNT_IRQ2_STAT_REG 0x1dc +#define PWR_EVNT_IRQ3_STAT_REG 0x228 +#define PWR_EVNT_IRQ4_STAT_REG 0x238 #define PWR_EVNT_LPM_IN_L2_MASK BIT(4) #define PWR_EVNT_LPM_OUT_L2_MASK BIT(5) @@ -93,6 +96,13 @@ struct dwc3_qcom { struct icc_path *icc_path_apps; }; +static u32 pwr_evnt_irq_stat_reg_offset[4] = { + PWR_EVNT_IRQ1_STAT_REG, + PWR_EVNT_IRQ2_STAT_REG, + PWR_EVNT_IRQ3_STAT_REG, + PWR_EVNT_IRQ4_STAT_REG, +}; + static inline void dwc3_qcom_setbits(void __iomem *base, u32 offset, u32 val) { u32 reg; @@ -413,13 +423,16 @@ static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup) { u32 val; int i, ret; + struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3); if (qcom->is_suspended) return 0; - val = readl(qcom->qscratch_base + PWR_EVNT_IRQ_STAT_REG); - if (!(val & PWR_EVNT_LPM_IN_L2_MASK)) - dev_err(qcom->dev, "HS-PHY not in L2\n"); + for (i = 0; i < dwc->num_ports; i++) { + val = readl(qcom->qscratch_base + pwr_evnt_irq_stat_reg_offset[i]); + if (!(val & PWR_EVNT_LPM_IN_L2_MASK)) + dev_err(qcom->dev, "HS-PHY%d not in L2\n", i); + } for (i = qcom->num_clocks - 1; i >= 0; i--) clk_disable_unprepare(qcom->clks[i]); @@ -446,6 +459,7 @@ static int dwc3_qcom_resume(struct dwc3_qcom *qcom, bool wakeup) { int ret; int i; + struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3); if (!qcom->is_suspended) return 0; @@ -467,8 +481,10 @@ static int dwc3_qcom_resume(struct dwc3_qcom *qcom, bool wakeup) dev_warn(qcom->dev, "failed to enable interconnect: %d\n", ret); /* Clear existing events from PHY related to L2 in/out */ - dwc3_qcom_setbits(qcom->qscratch_base, PWR_EVNT_IRQ_STAT_REG, - PWR_EVNT_LPM_IN_L2_MASK | PWR_EVNT_LPM_OUT_L2_MASK); + for (i = 0; i < dwc->num_ports; i++) + dwc3_qcom_setbits(qcom->qscratch_base, + pwr_evnt_irq_stat_reg_offset[i], + PWR_EVNT_LPM_IN_L2_MASK | PWR_EVNT_LPM_OUT_L2_MASK); qcom->is_suspended = false; From patchwork Fri Mar 10 16:34:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Kurapati X-Patchwork-Id: 67570 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp979978wrd; Fri, 10 Mar 2023 08:52:08 -0800 (PST) X-Google-Smtp-Source: AK7set+gcGZIAPCIiIU3F2gmuqckuJkXt3vxTkpC75BQ1cVQBglYU7CIChN4tHfT1TjzOMoa6dsC X-Received: by 2002:a05:6a20:729f:b0:cc:4058:82bd with SMTP id o31-20020a056a20729f00b000cc405882bdmr30475138pzk.13.1678467127812; Fri, 10 Mar 2023 08:52:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1678467127; cv=none; d=google.com; s=arc-20160816; b=co4fHjrWA7eNSChTBnyLSz3luMM51PKm2t2S/wg1qA4PYCqQ3sXcNk/EtuN/YBsk2u uPuiz9k85sROVSYF0aaLueqOwtgNwp7ff6dvnioJt2sxJBiKsgsiG/hVUOCFcLYP5P9k uGJroQ7zn/404JX4ToZKPG5JTTxeM1cXqzDZk7p7UUnHO1BVNjDc1nexnQgMqbQtC1wA VXa/vZUATRpjXE+xS0MHBk1nAqsL7lBZ80WEXlcGSBoR4ktyJ+NrnrH0DIjXN+8UQhmr Ls27C8jLufqn7cosFtvJX2+oZyNIfTJ3R++BolQ9AIEYee/NA5IdY5O3m0t4H4SW+gi+ EWhw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=hGlx65AGSJ98cyRhsWAq50yyWSopTFu2T5L537yAqZA=; b=n0jn79YVV4ahNAqxgXhwa008XE8erp31vTNCt1ktOgg1pFOGobMveW3kBmYTmVbZH/ vnRiCYD6McgcWZeWhrrtwt7qzBaf64DGi9jiR/vcJKyuynjjekNhUCRqV2+5ikLnooSj PbSW2IGIfaD1/rrsXQ5Pq4xniq4QW6a+LXY51SaV0qjidQOknG7dr+A3mR1mXL6bMf0y hLQfyBsyI61n/lYJUpEQT+56STFDX8IStAZd4ZTvtDHxZwVY36JMccewVrQJEDtQQVf9 OYI63LbUsHfprzTNK/YxKfs+PWeRcvByEdolLgoWKxS/MM42JLqedkRDKWUuYEeKvvay 2SYg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=M5YBVQmp; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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This will be used as a base for SA8295P and SA8295-Ride platforms. Signed-off-by: Krishna Kurapati --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 58 ++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 0d02599d8867..47e1f1da63a4 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -3108,6 +3108,64 @@ usb_1_role_switch: endpoint { }; }; + usb_2: usb@a4f8800 { + compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3"; + reg = <0 0x0a4f8800 0 0x400>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>, + <&gcc GCC_USB30_MP_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>, + <&gcc GCC_USB30_MP_SLEEP_CLK>, + <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, + <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, + <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, + <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, + <&gcc GCC_SYS_NOC_USB_AXI_CLK>; + clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", + "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; + + assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_MP_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + interrupts-extended = <&pdc 127 IRQ_TYPE_EDGE_RISING>, + <&pdc 126 IRQ_TYPE_EDGE_RISING>, + <&pdc 16 IRQ_TYPE_LEVEL_HIGH>; + + interrupt-names = "dp_hs_phy_irq", "dm_hs_phy_irq", + "ss_phy_irq"; + + power-domains = <&gcc USB30_MP_GDSC>; + + resets = <&gcc GCC_USB30_MP_BCR>; + + interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; + interconnect-names = "usb-ddr", "apps-usb"; + + required-opps = <&rpmhpd_opp_nom>; + + status = "disabled"; + + usb_2_dwc3: usb@a400000 { + compatible = "snps,dwc3"; + reg = <0 0x0a400000 0 0xcd00>; + interrupts = ; + iommus = <&apps_smmu 0x800 0x0>; + phys = <&usb_2_hsphy0>, <&usb_2_qmpphy0>, + <&usb_2_hsphy1>, <&usb_2_qmpphy1>, + <&usb_2_hsphy2>, + <&usb_2_hsphy3>; + phy-names = "usb2-port0", "usb3-port0", + "usb2-port1", "usb3-port1", + "usb2-port2", + "usb2-port3"; + }; + }; + mdss0: display-subsystem@ae00000 { compatible = "qcom,sc8280xp-mdss"; reg = <0 0x0ae00000 0 0x1000>; From patchwork Fri Mar 10 16:34:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Kurapati X-Patchwork-Id: 67565 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp979686wrd; Fri, 10 Mar 2023 08:51:30 -0800 (PST) X-Google-Smtp-Source: AK7set+EEK+2dpRxZpZx+G7uaoPY2py5eXj59M71EPRAg95YGmmmOiheXZY//F75H7BQhfS/l5u5 X-Received: by 2002:a05:6a20:7d8b:b0:cc:9b29:f621 with SMTP id v11-20020a056a207d8b00b000cc9b29f621mr33383913pzj.42.1678467090586; Fri, 10 Mar 2023 08:51:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1678467090; cv=none; d=google.com; s=arc-20160816; b=I7w3LyoFCqsrXCdfRpbLh//p6nwuMN+6mj46WGk9FjBzuk/E674kkQYYkVuxYwVH+P Ra+ksdthdH+ZNu0IAZ/j/ISL7Rtl96aIH8ggBRyZsdMahLO6cwAhajNhRSxqNwz8s3CD YRdiuodGE3hlgt4SJBZMD+Cxfk8je+r5U9ib6dDfC/GQW9ockH7ngzuDd7ro8yF4vOcY y1AMm+Eq6m6DuW4oovdbvKgmBezIRB/X3l9UCtiL0KZAyfdHM6U0vhrQc7FYEi8qiq7k +PsEHjC5q6vTLZwU4G3fjFHc00o4skFyZMfrAcv9GSg1gPkAbwnV/I7hei2RalWVm60V APxQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=5CYIAvq2RwK7h2JFXDkVkaMkq2+eWDd1wES9HRG3m9M=; b=WgYu5jhiKfXAFFeBFpckRYMcEibCFMczD1ZTJqvW9pH3xcVYLYE+rTJ71JCl6F/kFL j7RdRpUG2Km9Lp85SRoz2Vv9H1wBgUjY9EbtKuUJP/BOaoW4utWU+5mx83eAJAX76s6W JTtYtjRGBMwciOoD6Jd2TigtuhFTK+r5KBirpUFMNNHI3tzBwOAKwcthV+8B2qnYz3Xx Xy6iqKVWGCyAKDmLYbkqdjiECNDKS3L6fNH5SXpoJG829MA106XHblTpzQaSUMNVIvsY 4GabN57KgfZTewML4Hkc4/TUN9WOtqtSoVaVh9JXCqbe0kiruNTBrbmq5tQ//i5pohlJ klzQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=pgMgKwQV; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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Add pinctrl support for usb ports to provide VBUS to connected peripherals. Signed-off-by: Krishna Kurapati --- arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 47 ++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts index fd253942e5e5..7e6061c43835 100644 --- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts +++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts @@ -584,6 +584,19 @@ &usb_1_qmpphy { status = "okay"; }; +&usb_2 { + pinctrl-names = "default"; + pinctrl-0 = <&usb2_en_state>, + <&usb3_en_state>, + <&usb4_en_state>, + <&usb5_en_state>; + status = "okay"; +}; + +&usb_2_dwc3 { + dr_mode = "host"; +}; + &usb_2_hsphy0 { vdda-pll-supply = <&vreg_l5a>; vdda18-supply = <&vreg_l7g>; @@ -729,3 +742,37 @@ wake-n-pins { }; }; }; + +&pmm8540c_gpios { + usb2_en_state: usb2-en-state { + pins = "gpio9"; + function = "normal"; + output-high; + power-source = <0>; + }; +}; + +&pmm8540e_gpios { + usb3_en_state: usb3-en-state { + pins = "gpio5"; + function = "normal"; + output-high; + power-source = <0>; + }; +}; + +&pmm8540g_gpios { + usb4_en_state: usb4-en-state { + pins = "gpio5"; + function = "normal"; + output-high; + power-source = <0>; + }; + + usb5_en_state: usb5-en-state { + pins = "gpio9"; + function = "normal"; + output-high; + power-source = <0>; + }; +}; From patchwork Fri Mar 10 16:34:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Kurapati X-Patchwork-Id: 67560 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp979465wrd; Fri, 10 Mar 2023 08:51:02 -0800 (PST) X-Google-Smtp-Source: AK7set+08vqUcQ9T03Xq5ORkchekSUtKIqQhi52Nq8WqRA81RyRrMRrV3YZ2QWAS7hektCTpoYnE X-Received: by 2002:a05:6a20:a8a3:b0:cc:4a6f:ed8e with SMTP id ca35-20020a056a20a8a300b000cc4a6fed8emr22062859pzb.40.1678467062316; Fri, 10 Mar 2023 08:51:02 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1678467062; cv=none; d=google.com; s=arc-20160816; b=fG0DY58miS2uAu0XisNxBszc5JGZn4Cjcd/O2K3JTf5PqkCAydA0BRJSmaKyYW7iUq vwcyNiZX/TaXXgdxr0i1BCvsBhu1cZaANwjJUtg1sujF11PWXrwQhYod+PkjD6rCBftm 6BAStdLSXOFZ1Nxwer8tTLYdJCUWk5h26PaJepsEQ41v0KjSpXT50ve4Nq9XghlEf7OZ ktSfPyderod4OoQriKK+ThJOG6BHzdyaAa6f/UYuIIYhvlh09GqEtc896tgVSRkZvSLE BhM9vemrPk+Ki6tqZMD0rQqEWB6dSo9tnmz3A/DpkRnSSHnPcYqWrnrJ/4LWoYSDw7Gl ef6Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=X25k0ljmd07bmkdZ/R1kKNVU+KtTLV92UgIrOURq3sg=; b=bFhHLdQMZB5XN3iOxiRRpclD7Se2OioqzWYADvmO+kHmzaxgmlBA0/mnoS5nY5krlq jd8cb0bfoSY6DDOkKe225axGZwogFMhVGdtHQUvrUTqMZYATe5Jn1FXbyaBdY5rT1m3E ZwQbv7ieKmE8nICSclry7+rXUiMHYmI98AzlOWZ54tq+3hsEER0p+QYqKc/7YgJOQxCg c2giDEY8cO8bVL5Rs6sS/9zbO0IWht7n73b3bSMRWopoC5iX9FXyWvbS6ZCJGL5IrWCn IQl2F5FhaasmEoVOr4/QjnDQFqTqg3/Ixm07MfqgJ9fBwoqpN5Fv5PRHSDPgDYtYwPuu OvmA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=Rq84zF6c; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Krishna Kurapati --- arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts index 3ccb5ffdb3ca..46e9ca9c666e 100644 --- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts @@ -309,6 +309,19 @@ &usb_2_qmpphy0 { status = "okay"; }; +&usb_2 { + pinctrl-names = "default"; + pinctrl-0 = <&usb2_en_state>; + + status = "okay"; +}; + +&usb_2_dwc3 { + dr_mode = "host"; + phy-names = "usb2-port0", "usb3-port0"; + phys = <&usb_2_hsphy0>, <&usb_2_qmpphy0>; +}; + &xo_board_clk { clock-frequency = <38400000>; }; @@ -401,4 +414,13 @@ wake-pins { bias-pull-up; }; }; + + usb2_en_state: usb2-en-state { + /* TS3USB221A USB2.0 mux select */ + pins = "gpio24"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; };