From patchwork Fri Mar 10 13:21:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jianhua Lu X-Patchwork-Id: 67393 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp868659wrd; Fri, 10 Mar 2023 05:23:38 -0800 (PST) X-Google-Smtp-Source: AK7set9KlX9ermvcSzCYLLRmODfZJ13C2YCfz8JC29a37zl/OtrBnR1NtZcSApGZxewPGkIwRLMY X-Received: by 2002:a17:903:41c3:b0:19e:699e:9b64 with SMTP id u3-20020a17090341c300b0019e699e9b64mr32242192ple.65.1678454618677; Fri, 10 Mar 2023 05:23:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1678454618; cv=none; d=google.com; s=arc-20160816; b=Zcl2m1RHz8mXp6Kx162Kuc5Pq2r2KcGD8Bf7h22Qaj4XIdC7DEenTOR+0I4QaSyIUy rJL2roXJZO6FcSqxeQIdShpsRm0Jz1J2cfeNRFcEnxnPlpXcWUHfgjppCHitTjeiihQN N4Rym56RsB6F2GCcCYZBpR8cop/+ulIp+q/9OrfFJX9tiXLQfIcG5QWNfkJKXCCrlLlD xLbEz5YdpGyVhAwjQyGQxmA9h0VDRlcpJC4sOyMp7n0sTsvDcdlQyNyWUh7XtsUgosry Xafa65EYrD03RywvVuqwu02QSXWd4fFKf+dpjaY5ptVstBjkPCDMtuBdl/SBJkV362T+ voJw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=OfHCteNV7q+dsb4Bbdwo2yP63fJ16IUesnNAhcskNRU=; b=acj710T8VCJZ+cWqgRdMwg49UX4/fEb2ggul3Vj6I02Fq31xCqTgsyDJ30UQTpVlWp YDv/gaFSBC8RENXmsphS4P6dGmsMcz9O8adLt4VRa7mKrbmhDnAIwx6LrsUdnNRLmwd8 uCR2eXW3+DaEdnFWz2aRad6l2vxxyYkH5a6wyfwMrGlk+Vu+oRPTLJOJh/CQ5qtRxgln gZmHtpnZZeoTyk0fnZdGYYAL21Bo0HGQ3yyI651mz9ujOumi5mc2yWpQvEMXmVjHN6vQ JYVNYgKWhH++1V0hGJKlRlcObI8aDY488lEIw0t36gTvXLaBpAOBjvxhGastKHxDPxLW 5IXw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=KzoY5clJ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id ik21-20020a170902ab1500b0019b7766afdcsi1985835plb.554.2023.03.10.05.23.23; Fri, 10 Mar 2023 05:23:38 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=KzoY5clJ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229552AbjCJNWI (ORCPT + 99 others); Fri, 10 Mar 2023 08:22:08 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59590 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230124AbjCJNWB (ORCPT ); Fri, 10 Mar 2023 08:22:01 -0500 Received: from mail-pj1-x102f.google.com (mail-pj1-x102f.google.com [IPv6:2607:f8b0:4864:20::102f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 224CEF92FF; Fri, 10 Mar 2023 05:21:55 -0800 (PST) Received: by mail-pj1-x102f.google.com with SMTP id p3-20020a17090ad30300b0023a1cd5065fso5182781pju.0; Fri, 10 Mar 2023 05:21:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1678454514; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=OfHCteNV7q+dsb4Bbdwo2yP63fJ16IUesnNAhcskNRU=; b=KzoY5clJwBNute/PoW2MQ6oouocVxaydnQP7158oMa776/X3aRPhiTNkSB8lMxnzj4 DtVmyK9GibAPj9fImIEinHv4LbGohSYZgkq/WnghAlkhZfpMv/Vv/1bVQStzwiKFNgIC MdkJyaT8KcQ8P1UtvNaXwxulnHN5afDecv3Zi0r7xFYlVfI/Eo9sRGlTWSK7x9zGOXuy SCT7TwjU+oXvUjPwytDrRJjvB5rRsmiOQAZirKb6jAEHhwEYuXQditq6LB2emrxMw/D3 S1dkW1nt2jUC4+/Lc1/1qT4NCdnZ1fmO3nYQaWF6/4dlN3xYneRBZG+y6ixARyyMEVim a2lA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678454514; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=OfHCteNV7q+dsb4Bbdwo2yP63fJ16IUesnNAhcskNRU=; b=P0UEYNeJ2zCW85ZPwmmjBNdsfoadolxEXm/Q9Wngqe7A2RShua/3l2YrCGhH97OnbM NgqgsFr4kb8h2DBYq239f8hQDzRod5npBmCfF2jZkM9SpdBywkMnMrZ+ORPOnyaJeEzA fi6IzV22CNeDmgEojPAWYzjYZxyeV9Avc8fiNvnlKLQoTnqULIM2syzbev8/cJoEiXWf FKDvgW38/0yCpueYUcN1xyTiBKFO8vBd0XK0Xh5AWHCfOa43MbRo06ZRbNc7Bok20AW7 X3fF7kEW7KS0SGSKEgpB/APZ1lDDaCTFNQgvPFXkuxV762NAzikZa5JZiArPcbbhGDB0 KoZw== X-Gm-Message-State: AO0yUKUe/MrrGaVI8w+WIfm68ZSV0droITBqcgSp0yVqh2IScJP+1aeM /LDNXXGpmJ5oCMbDqjaYv1M= X-Received: by 2002:a17:902:c40d:b0:19e:6760:3a5d with SMTP id k13-20020a170902c40d00b0019e67603a5dmr30054230plk.18.1678454514624; Fri, 10 Mar 2023 05:21:54 -0800 (PST) Received: from localhost.localdomain (n220246252084.netvigator.com. [220.246.252.84]) by smtp.gmail.com with ESMTPSA id e6-20020a170902b78600b0019a95baaaa6sm1421711pls.222.2023.03.10.05.21.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Mar 2023 05:21:54 -0800 (PST) From: Jianhua Lu To: Thierry Reding , Sam Ravnborg , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Linus Walleij , Konrad Dybcio , Neil Armstrong Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, Jianhua Lu , Krzysztof Kozlowski Subject: [PATCH v4 1/2] dt-bindings: display: panel: Add Novatek NT36523 bindings Date: Fri, 10 Mar 2023 21:21:43 +0800 Message-Id: <20230310132144.2241-1-lujianhua000@gmail.com> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 X-Spam-Status: No, score=-1.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759987230583326251?= X-GMAIL-MSGID: =?utf-8?q?1759987230583326251?= Novatek NT36523 is a display driver IC used to drive DSI panels. Signed-off-by: Jianhua Lu Reviewed-by: Krzysztof Kozlowski --- No changes in v4 Changes in v3: - pick up Krzysztof's R-b - remove vddpos and vddneg supply Changes in v2: - Drop unnecessary description - dsi0 -> dsi - Correct indentation .../display/panel/novatek,nt36523.yaml | 85 +++++++++++++++++++ 1 file changed, 85 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/panel/novatek,nt36523.yaml diff --git a/Documentation/devicetree/bindings/display/panel/novatek,nt36523.yaml b/Documentation/devicetree/bindings/display/panel/novatek,nt36523.yaml new file mode 100644 index 000000000000..0039561ef04c --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/novatek,nt36523.yaml @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/novatek,nt36523.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Novatek NT36523 based DSI display Panels + +maintainers: + - Jianhua Lu + +description: | + The Novatek NT36523 is a generic DSI Panel IC used to drive dsi + panels. Support video mode panels from China Star Optoelectronics + Technology (CSOT) and BOE Technology. + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + items: + - enum: + - xiaomi,elish-boe-nt36523 + - xiaomi,elish-csot-nt36523 + - const: novatek,nt36523 + + reset-gpios: + maxItems: 1 + description: phandle of gpio for reset line - This should be 8mA + + vddio-supply: + description: regulator that supplies the I/O voltage + + reg: true + ports: true + backlight: true + +required: + - compatible + - reg + - vddio-supply + - reset-gpios + - ports + +unevaluatedProperties: false + +examples: + - | + #include + + dsi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "xiaomi,elish-csot-nt36523", "novatek,nt36523"; + reg = <0>; + + vddio-supply = <&vreg_l14a_1p88>; + reset-gpios = <&tlmm 75 GPIO_ACTIVE_LOW>; + backlight = <&backlight>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_0: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1{ + reg = <1>; + panel_in_1: endpoint { + remote-endpoint = <&dsi1_out>; + }; + }; + }; + }; + }; + +... From patchwork Fri Mar 10 13:21:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jianhua Lu X-Patchwork-Id: 67396 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp868753wrd; Fri, 10 Mar 2023 05:23:54 -0800 (PST) X-Google-Smtp-Source: AK7set/Z0ASYlsmOL+KrikubGuFURJ6LPrIPro1kqclRsc+0iJAA8uV+kDKWsOrJKWWcaSiAs3M3 X-Received: by 2002:a62:1dc8:0:b0:5a8:a250:bc16 with SMTP id d191-20020a621dc8000000b005a8a250bc16mr19175905pfd.3.1678454633673; Fri, 10 Mar 2023 05:23:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1678454633; cv=none; d=google.com; s=arc-20160816; b=RL5Vc9jQSU37kOMhcvN6PKOgShkHo2K+MwABmnmvr0qMmBky8k3ybU32EQ0WjnV+rl aBCIEn401FVNQzG6qlvsq9QMscgP7vd1ZeLD3AUy9zzKIqk/axCb42hkM4NCsC3uidSN ZJkuTt0cl9CHOrWxq+cwuL05oJsEhko10TlahzM/eWLLO9jHhj+ukyeDqzEcNc3mkBwf KanuBSpgEDbnXztDaGNwzeG3uRt919s/j6NXSvbwvQC+ePZHGPlZdtQtTh1XErys0Zpu s0xFcyxeuSyAhmAsF+sn9YK0VPDFdxNtiQg50xbEAT5cczedcIfJSMqOSAqCfOd0B/Rs ZLvg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=RFuEBi0J70joVxKiDRPF4xXfeQZMxlIMXCCNAKA6GJ4=; b=bBG4Y9GN6s45mMkmnxgzNy7efgc5PwwFOdJfyGZlcvM4xJkZFEZCtUAUiajKDHRXdZ /x0K3xzwOCr3FZsTfW3ZkLu411qMc00G9U9Sk6cEWj/LRvzgQVH2PyX5cQ+b71D0SgJI sx44p8mlcZ/IackqCNN+VL/lZF9Gi1srEq7I1XF+UVBq9pAoVn7WCEV6ZOKF5SEuiFta 4UmwX9whjfsMJ++Bgbyc+zJtqo2AKv7B42fEpvM5KvqIVtp3PmUT/vebTFqYyvU/X7rD u26dPiIcwwOoBo+zHV3ERYIGJVp0NiVgCop5RgQIl6Ql8dwsyR/KSVivXRiYu4YLc7cC UjNQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=NHsZupeJ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id g16-20020aa79dd0000000b0058d97ce5372si1858440pfq.249.2023.03.10.05.23.38; Fri, 10 Mar 2023 05:23:53 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=NHsZupeJ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230242AbjCJNWb (ORCPT + 99 others); Fri, 10 Mar 2023 08:22:31 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59920 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229916AbjCJNWG (ORCPT ); Fri, 10 Mar 2023 08:22:06 -0500 Received: from mail-pj1-x1036.google.com (mail-pj1-x1036.google.com [IPv6:2607:f8b0:4864:20::1036]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 25DF5F92FF; Fri, 10 Mar 2023 05:22:02 -0800 (PST) Received: by mail-pj1-x1036.google.com with SMTP id h17-20020a17090aea9100b0023739b10792so5153539pjz.1; Fri, 10 Mar 2023 05:22:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1678454521; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RFuEBi0J70joVxKiDRPF4xXfeQZMxlIMXCCNAKA6GJ4=; b=NHsZupeJdJpwJdVTU8d+XPNt3HUTAxIiWCZ/eqwxblu72DfpF0sOHWNotParOrFL1f tbjo/6G2nMKbTHbxN+3lPNyvo9C5GALFSKoLsYjtcCk0BwXYPHp8G6u+5nbvhUE/spoO K2ivEDSz5FLYtHrLmnCwDkiAhS6CJzJ4xnkaVxByFPQStkQuMOQAYQDfgQMuuL6WJC2v ZaEuhlWrG9y2wb9mKPacjXLlfM2+eAGur83aCX1B4oiA7ALwAvLP/r1hklO/FSgiBH/x rvbVbFxBXtC+HjhxvKYbnY2zSkpsfJLFM6PZXDSPWr7IdAbNIQpUi5Gb/LGoVdLBWXRy m9Tg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678454521; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RFuEBi0J70joVxKiDRPF4xXfeQZMxlIMXCCNAKA6GJ4=; b=xp/74GoLjTxvf5QoJ9b+MXgI39LzdgYXvJSZEvwjMvPOB1P77TgBP/gP0yN/16TJ4I nB73/+BU+HD4JKJnydqu0okftuwTQEtJTaaFEyeFJcnPerAyIKQt3CuiPF2azP6eop6h NAwjkIJ+mbF6rgy6WWg4oK5gSv6GOupPsKZQMjVQJ47zJ8VFp+JPEzG+i8K1CBbHdAA3 0rKxHqF/uOFEDy9+PjI6frUknUzWxmB6YRbBmQHCMEyu1unr5HQPiPl7LKOH399BZ2o7 aNQYBZtycP6Z7LdAOJGmGPWT6tUG6ynlyky0Q9W0flCiTIbUu/M0cqHdUfQuvyObe/9F y9Ug== X-Gm-Message-State: AO0yUKU1oMsf7/1JOx+qlW/5v77w/kgRySf/pgJ9yJM6ZEem/IzKJZZ4 MW3NfF0a+dN0OAB/WSe5y9E+4OIi224= X-Received: by 2002:a17:902:a70a:b0:19d:1898:5b89 with SMTP id w10-20020a170902a70a00b0019d18985b89mr20203827plq.7.1678454521388; Fri, 10 Mar 2023 05:22:01 -0800 (PST) Received: from localhost.localdomain (n220246252084.netvigator.com. [220.246.252.84]) by smtp.gmail.com with ESMTPSA id e6-20020a170902b78600b0019a95baaaa6sm1421711pls.222.2023.03.10.05.21.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Mar 2023 05:22:01 -0800 (PST) From: Jianhua Lu To: Thierry Reding , Sam Ravnborg , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Linus Walleij , Konrad Dybcio , Neil Armstrong Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, Jianhua Lu Subject: [PATCH v4 2/2] drm/panel: Add driver for Novatek NT36523 Date: Fri, 10 Mar 2023 21:21:44 +0800 Message-Id: <20230310132144.2241-2-lujianhua000@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230310132144.2241-1-lujianhua000@gmail.com> References: <20230310132144.2241-1-lujianhua000@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759987246032223077?= X-GMAIL-MSGID: =?utf-8?q?1759987246032223077?= Add a driver for panels using the Novatek NT36523 display driver IC. Signed-off-by: Jianhua Lu --- Changes in v4: - add multiple modes support - use dev_err_probe helper - fix dsi_info type string - reimplement mipi_dsi_dual_dcs_write_seq() macro Changes in v3: - Refactor source code Changes in v2: - Refactor and clean up source code MAINTAINERS | 7 + drivers/gpu/drm/panel/Kconfig | 10 + drivers/gpu/drm/panel/Makefile | 1 + drivers/gpu/drm/panel/panel-novatek-nt36523.c | 771 ++++++++++++++++++ 4 files changed, 789 insertions(+) create mode 100644 drivers/gpu/drm/panel/panel-novatek-nt36523.c diff --git a/MAINTAINERS b/MAINTAINERS index 5383af5d3b45..3586248bb05d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -6537,6 +6537,13 @@ T: git git://anongit.freedesktop.org/drm/drm-misc F: Documentation/devicetree/bindings/display/panel/sony,acx424akp.yaml F: drivers/gpu/drm/panel/panel-novatek-nt35560.c +DRM DRIVER FOR NOVATEK NT36523 PANELS +M: Jianhua Lu +S: Maintained +T: git git://anongit.freedesktop.org/drm/drm-misc +F: Documentation/devicetree/bindings/display/panel/novatek,nt36523.yaml +F: drivers/gpu/drm/panel/panel-novatek-nt36523.c + DRM DRIVER FOR NOVATEK NT36672A PANELS M: Sumit Semwal S: Maintained diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig index 8eeee71c0000..268508743b5c 100644 --- a/drivers/gpu/drm/panel/Kconfig +++ b/drivers/gpu/drm/panel/Kconfig @@ -377,6 +377,16 @@ config DRM_PANEL_NOVATEK_NT35950 Sharp panels used in Sony Xperia Z5 Premium and XZ Premium mobile phones. +config DRM_PANEL_NOVATEK_NT36523 + tristate "Novatek NT36523 panel driver" + depends on OF + depends on DRM_MIPI_DSI + depends on BACKLIGHT_CLASS_DEVICE + help + Say Y here if you want to enable support for the panels built + around the Novatek NT36523 display controller, such as some + Boe panels used in Xiaomi Mi Pad 5 and 5 Pro tablets. + config DRM_PANEL_NOVATEK_NT36672A tristate "Novatek NT36672A DSI panel" depends on OF diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile index c05aa9e23907..570eab8bf2b2 100644 --- a/drivers/gpu/drm/panel/Makefile +++ b/drivers/gpu/drm/panel/Makefile @@ -35,6 +35,7 @@ obj-$(CONFIG_DRM_PANEL_NEWVISION_NV3052C) += panel-newvision-nv3052c.o obj-$(CONFIG_DRM_PANEL_NOVATEK_NT35510) += panel-novatek-nt35510.o obj-$(CONFIG_DRM_PANEL_NOVATEK_NT35560) += panel-novatek-nt35560.o obj-$(CONFIG_DRM_PANEL_NOVATEK_NT35950) += panel-novatek-nt35950.o +obj-$(CONFIG_DRM_PANEL_NOVATEK_NT36523) += panel-novatek-nt36523.o obj-$(CONFIG_DRM_PANEL_NOVATEK_NT36672A) += panel-novatek-nt36672a.o obj-$(CONFIG_DRM_PANEL_NOVATEK_NT39016) += panel-novatek-nt39016.o obj-$(CONFIG_DRM_PANEL_MANTIX_MLAF057WE51) += panel-mantix-mlaf057we51.o diff --git a/drivers/gpu/drm/panel/panel-novatek-nt36523.c b/drivers/gpu/drm/panel/panel-novatek-nt36523.c new file mode 100644 index 000000000000..78232c2735ff --- /dev/null +++ b/drivers/gpu/drm/panel/panel-novatek-nt36523.c @@ -0,0 +1,771 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Novatek NT36523 DriverIC panels driver + * + * Copyright (c) 2022, 2023 Jianhua Lu + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#define DSI_NUM_MIN 1 + +#define mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, cmd, seq...) \ + do { \ + mipi_dsi_dcs_write_seq(dsi0, cmd, seq); \ + mipi_dsi_dcs_write_seq(dsi1, cmd, seq); \ + } while (0) + +struct panel_info { + struct drm_panel panel; + struct mipi_dsi_device *dsi[2]; + const struct panel_desc *desc; + + struct gpio_desc *reset_gpio; + struct backlight_device *backlight; + struct regulator *vddio; + + bool prepared; +}; + +struct panel_desc { + unsigned int width_mm; + unsigned int height_mm; + + unsigned int bpc; + unsigned int lanes; + unsigned long mode_flags; + enum mipi_dsi_pixel_format format; + + const struct drm_display_mode *modes; + unsigned int num_modes; + const struct mipi_dsi_device_info dsi_info; + int (*init_sequence)(struct panel_info *pinfo); + + bool is_dual_dsi; +}; + +static inline struct panel_info *to_panel_info(struct drm_panel *panel) +{ + return container_of(panel, struct panel_info, panel); +} + +static int elish_boe_init_sequence(struct panel_info *pinfo) +{ + struct mipi_dsi_device *dsi0 = pinfo->dsi[0]; + struct mipi_dsi_device *dsi1 = pinfo->dsi[1]; + /* No datasheet, so write magic init sequence directly */ + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFF, 0x10); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFB, 0x01); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xB9, 0x05); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFF, 0x20); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFB, 0x01); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x18, 0x40); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFF, 0x10); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFB, 0x01); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xB9, 0x02); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFF, 0x23); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFB, 0x01); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x00, 0x80); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x01, 0x84); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x05, 0x2D); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x06, 0x00); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x07, 0x00); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x08, 0x01); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x09, 0x45); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x11, 0x02); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x12, 0x80); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x15, 0x83); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x16, 0x0C); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x29, 0x0A); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x30, 0xFF); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x31, 0xFE); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x32, 0xFD); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x33, 0xFB); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x34, 0xF8); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x35, 0xF5); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x36, 0xF3); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x37, 0xF2); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x38, 0xF2); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x39, 0xF2); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x3A, 0xEF); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x3B, 0xEC); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x3D, 0xE9); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x3F, 0xE5); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x40, 0xE5); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x41, 0xE5); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x2A, 0x13); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x45, 0xFF); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x46, 0xF4); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x47, 0xE7); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x48, 0xDA); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x49, 0xCD); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x4A, 0xC0); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x4B, 0xB3); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x4C, 0xB2); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x4D, 0xB2); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x4E, 0xB2); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x4F, 0x99); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x50, 0x80); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x51, 0x68); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x52, 0x66); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x53, 0x66); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x54, 0x66); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x2B, 0x0E); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x58, 0xFF); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x59, 0xFB); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x5A, 0xF7); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x5B, 0xF3); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x5C, 0xEF); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x5D, 0xE3); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x5E, 0xDA); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x5F, 0xD8); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x60, 0xD8); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x61, 0xD8); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x62, 0xCB); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x63, 0xBF); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x64, 0xB3); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x65, 0xB2); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x66, 0xB2); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x67, 0xB2); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFF, 0x2A); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFB, 0x01); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x25, 0x47); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x30, 0x47); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x39, 0x47); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFF, 0x26); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFB, 0x01); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x19, 0x10); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x1A, 0xE0); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x1B, 0x10); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x1C, 0x00); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x2A, 0x10); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x2B, 0xE0); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFF, 0x10); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFB, 0x01); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFF, 0xF0); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFB, 0x01); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x84, 0x08); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x85, 0x0C); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFF, 0x20); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFB, 0x01); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x51, 0x00); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFF, 0x25); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFB, 0x01); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x91, 0x1F); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x92, 0x0F); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x93, 0x01); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x94, 0x18); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x95, 0x03); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x96, 0x01); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFF, 0x10); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xB0, 0x01); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFF, 0x25); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFB, 0x01); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x19, 0x1F); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x1B, 0x1B); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFF, 0x24); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFB, 0x01); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xB8, 0x28); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFF, 0x27); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFB, 0x01); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xD0, 0x31); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xD1, 0x20); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xD2, 0x30); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xD4, 0x08); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xDE, 0x80); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xDF, 0x02); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFF, 0x26); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFB, 0x01); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x00, 0x81); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x01, 0xB0); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFF, 0x22); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFB, 0x01); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x9F, 0x50); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x6F, 0x01); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x70, 0x11); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x73, 0x01); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x74, 0x49); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x76, 0x01); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x77, 0x49); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xA0, 0x3F); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xA9, 0x50); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xAA, 0x28); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xAB, 0x28); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xAD, 0x10); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xB8, 0x00); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xB9, 0x49); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xBA, 0x49); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xBB, 0x49); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xBE, 0x04); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xBF, 0x49); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xC0, 0x04); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xC1, 0x59); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xC2, 0x00); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xC5, 0x00); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xC6, 0x01); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xC7, 0x48); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xCA, 0x43); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xCB, 0x3C); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xCE, 0x00); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xCF, 0x43); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xD0, 0x3C); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xD3, 0x43); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xD4, 0x3C); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xD7, 0x00); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xDC, 0x43); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xDD, 0x3C); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xE1, 0x43); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xE2, 0x3C); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xF2, 0x00); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xF3, 0x01); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xF4, 0x48); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFF, 0x25); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFB, 0x01); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x13, 0x01); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x14, 0x23); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xBC, 0x01); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xBD, 0x23); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFF, 0x2A); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFB, 0x01); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x97, 0x3C); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x98, 0x02); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x99, 0x95); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x9A, 0x03); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x9B, 0x00); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x9C, 0x0B); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x9D, 0x0A); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x9E, 0x90); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFF, 0x22); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFB, 0x01); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x9F, 0x50); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFF, 0x23); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFB, 0x01); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xA3, 0x50); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFF, 0xE0); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFB, 0x01); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x14, 0x60); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x16, 0xC0); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x4F, 0x02); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFF, 0xF0); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFB, 0x01); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x3A, 0x08); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFF, 0xD0); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFB, 0x01); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x02, 0xAF); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x09, 0xEE); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x1C, 0x99); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x1D, 0x09); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFF, 0x10); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFB, 0x01); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x51, 0x0F, 0xFF); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x53, 0x2C); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x35, 0x00); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xBB, 0x13); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x3B, 0x03, 0xAC, 0x1A, 0x04, 0x04); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x11); + msleep(70); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x29); + return 0; +} + +static int elish_csot_init_sequence(struct panel_info *pinfo) +{ + struct mipi_dsi_device *dsi0 = pinfo->dsi[0]; + struct mipi_dsi_device *dsi1 = pinfo->dsi[1]; + /* No datasheet, so write magic init sequence directly */ + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFF, 0x10); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFB, 0x01); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xB9, 0x05); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFF, 0x20); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFB, 0x01); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x18, 0x40); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFF, 0x10); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFB, 0x01); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xB9, 0x02); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFF, 0xD0); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFB, 0x01); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x02, 0xAF); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x00, 0x30); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x09, 0xEE); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x1C, 0x99); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x1D, 0x09); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFF, 0xF0); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFB, 0x01); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x3A, 0x08); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFF, 0xE0); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFB, 0x01); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x4F, 0x02); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFF, 0x20); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFB, 0x01); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x58, 0x40); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFF, 0x10); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFB, 0x01); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x35, 0x00); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFF, 0x23); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFB, 0x01); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x00, 0x80); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x01, 0x84); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x05, 0x2D); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x06, 0x00); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x07, 0x00); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x08, 0x01); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x09, 0x45); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x11, 0x02); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x12, 0x80); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x15, 0x83); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x16, 0x0C); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x29, 0x0A); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x30, 0xFF); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x31, 0xFE); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x32, 0xFD); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x33, 0xFB); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x34, 0xF8); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x35, 0xF5); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x36, 0xF3); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x37, 0xF2); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x38, 0xF2); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x39, 0xF2); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x3A, 0xEF); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x3B, 0xEC); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x3D, 0xE9); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x3F, 0xE5); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x40, 0xE5); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x41, 0xE5); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x2A, 0x13); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x45, 0xFF); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x46, 0xF4); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x47, 0xE7); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x48, 0xDA); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x49, 0xCD); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x4A, 0xC0); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x4B, 0xB3); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x4C, 0xB2); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x4D, 0xB2); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x4E, 0xB2); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x4F, 0x99); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x50, 0x80); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x51, 0x68); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x52, 0x66); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x53, 0x66); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x54, 0x66); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x2B, 0x0E); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x58, 0xFF); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x59, 0xFB); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x5A, 0xF7); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x5B, 0xF3); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x5C, 0xEF); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x5D, 0xE3); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x5E, 0xDA); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x5F, 0xD8); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x60, 0xD8); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x61, 0xD8); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x62, 0xCB); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x63, 0xBF); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x64, 0xB3); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x65, 0xB2); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x66, 0xB2); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x67, 0xB2); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFF, 0x10); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFB, 0x01); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x51, 0x0F, 0xFF); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x53, 0x2C); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x55, 0x00); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xBB, 0x13); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x3B, 0x03, 0xAC, 0x1A, 0x04, 0x04); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFF, 0x2A); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFB, 0x01); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x25, 0x46); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x30, 0x46); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x39, 0x46); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFF, 0x26); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFB, 0x01); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x01, 0xB0); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x19, 0x10); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x1A, 0xE0); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x1B, 0x10); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x1C, 0x00); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x2A, 0x10); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x2B, 0xE0); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFF, 0xF0); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFB, 0x01); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x84, 0x08); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x85, 0x0C); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFF, 0x20); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFB, 0x01); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x51, 0x00); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFF, 0x25); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFB, 0x01); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x91, 0x1F); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x92, 0x0F); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x93, 0x01); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x94, 0x18); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x95, 0x03); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x96, 0x01); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFF, 0x10); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xB0, 0x01); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFF, 0x25); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFB, 0x01); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x19, 0x1F); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x1B, 0x1B); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFF, 0x24); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFB, 0x01); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xB8, 0x28); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFF, 0x27); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFB, 0x01); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xD0, 0x31); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xD1, 0x20); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xD4, 0x08); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xDE, 0x80); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xDF, 0x02); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFF, 0x26); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFB, 0x01); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x00, 0x81); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x01, 0xB0); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFF, 0x22); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFB, 0x01); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x6F, 0x01); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x70, 0x11); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x73, 0x01); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x74, 0x4D); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xA0, 0x3F); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xA9, 0x50); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xAA, 0x28); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xAB, 0x28); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xAD, 0x10); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xB8, 0x00); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xB9, 0x4B); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xBA, 0x96); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xBB, 0x4B); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xBE, 0x07); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xBF, 0x4B); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xC0, 0x07); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xC1, 0x5C); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xC2, 0x00); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xC5, 0x00); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xC6, 0x3F); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xC7, 0x00); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xCA, 0x08); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xCB, 0x40); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xCE, 0x00); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xCF, 0x08); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xD0, 0x40); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xD3, 0x08); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xD4, 0x40); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFF, 0x25); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFB, 0x01); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xBC, 0x01); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xBD, 0x1C); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFF, 0x2A); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFB, 0x01); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x9A, 0x03); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0xFF, 0x10); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x11); + msleep(70); + mipi_dsi_dual_dcs_write_seq(dsi0, dsi1, 0x29); + return 0; +} + +static const struct drm_display_mode elish_boe_modes[] = { + { + /* There is only one 120 Hz timing, but it doesn't work perfectly, 104 Hz prefered */ + .clock = (1600 + 60 + 8 + 60) * (2560 + 26 + 4 + 168) * 104 / 1000, + .hdisplay = 1600, + .hsync_start = 1600 + 60, + .hsync_end = 1600 + 60 + 8, + .htotal = 1600 + 60 + 8 + 60, + .vdisplay = 2560, + .vsync_start = 2560 + 26, + .vsync_end = 2560 + 26 + 4, + .vtotal = 2560 + 26 + 4 + 168, + }, +}; + +static const struct drm_display_mode elish_csot_modes[] = { + { + /* There is only one 120 Hz timing, but it doesn't work perfectly, 104 Hz prefered */ + .clock = (1600 + 200 + 40 + 52) * (2560 + 26 + 4 + 168) * 104 / 1000, + .hdisplay = 1600, + .hsync_start = 1600 + 200, + .hsync_end = 1600 + 200 + 40, + .htotal = 1600 + 200 + 40 + 52, + .vdisplay = 2560, + .vsync_start = 2560 + 26, + .vsync_end = 2560 + 26 + 4, + .vtotal = 2560 + 26 + 4 + 168, + }, +}; + +static const struct panel_desc elish_boe_desc = { + .modes = elish_boe_modes, + .num_modes = ARRAY_SIZE(elish_boe_modes), + .dsi_info = { + .type = "BOE-elish", + .channel = 0, + .node = NULL, + }, + .width_mm = 127, + .height_mm = 203, + .bpc = 8, + .lanes = 3, + .format = MIPI_DSI_FMT_RGB888, + .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS | MIPI_DSI_MODE_LPM, + .init_sequence = elish_boe_init_sequence, + .is_dual_dsi = true, +}; + +static const struct panel_desc elish_csot_desc = { + .modes = elish_csot_modes, + .num_modes = ARRAY_SIZE(elish_csot_modes), + .dsi_info = { + .type = "CSOT-elish", + .channel = 0, + .node = NULL, + }, + .width_mm = 127, + .height_mm = 203, + .bpc = 8, + .lanes = 3, + .format = MIPI_DSI_FMT_RGB888, + .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS | MIPI_DSI_MODE_LPM, + .init_sequence = elish_csot_init_sequence, + .is_dual_dsi = true, +}; + +static void nt36523_reset(struct panel_info *pinfo) +{ + gpiod_set_value_cansleep(pinfo->reset_gpio, 1); + usleep_range(12000, 13000); + gpiod_set_value_cansleep(pinfo->reset_gpio, 0); + usleep_range(12000, 13000); + gpiod_set_value_cansleep(pinfo->reset_gpio, 1); + usleep_range(12000, 13000); + gpiod_set_value_cansleep(pinfo->reset_gpio, 0); + usleep_range(12000, 13000); +} + +static int nt36523_prepare(struct drm_panel *panel) +{ + struct panel_info *pinfo = to_panel_info(panel); + int ret; + + if (pinfo->prepared) + return 0; + + ret = regulator_enable(pinfo->vddio); + if (ret) { + dev_err(panel->dev, "failed to enable vddio regulator: %d\n", ret); + return ret; + } + + nt36523_reset(pinfo); + + ret = pinfo->desc->init_sequence(pinfo); + if (ret < 0) { + regulator_disable(pinfo->vddio); + dev_err(panel->dev, "failed to initialize panel: %d\n", ret); + return ret; + } + + pinfo->prepared = true; + + return 0; +} + +static int nt36523_disable(struct drm_panel *panel) +{ + struct panel_info *pinfo = to_panel_info(panel); + int i, ret; + + for (i = 0; i < DSI_NUM_MIN + pinfo->desc->is_dual_dsi; i++) { + ret = mipi_dsi_dcs_set_display_off(pinfo->dsi[i]); + if (ret < 0) + dev_err(&pinfo->dsi[i]->dev, "failed to set display off: %d\n", ret); + } + + for (i = 0; i < DSI_NUM_MIN + pinfo->desc->is_dual_dsi; i++) { + ret = mipi_dsi_dcs_enter_sleep_mode(pinfo->dsi[i]); + if (ret < 0) + dev_err(&pinfo->dsi[i]->dev, "failed to enter sleep mode: %d\n", ret); + } + + msleep(70); + + return 0; +} + +static int nt36523_unprepare(struct drm_panel *panel) +{ + struct panel_info *pinfo = to_panel_info(panel); + + if (!pinfo->prepared) + return 0; + + gpiod_set_value_cansleep(pinfo->reset_gpio, 1); + regulator_disable(pinfo->vddio); + + pinfo->prepared = false; + + return 0; +} + +static void nt36523_remove(struct mipi_dsi_device *dsi) +{ + struct panel_info *pinfo = mipi_dsi_get_drvdata(dsi); + int ret; + + ret = mipi_dsi_detach(pinfo->dsi[0]); + if (ret < 0) + dev_err(&dsi->dev, "failed to detach from DSI0 host: %d\n", ret); + + if (pinfo->desc->is_dual_dsi) { + ret = mipi_dsi_detach(pinfo->dsi[1]); + if (ret < 0) + dev_err(&pinfo->dsi[1]->dev, "failed to detach from DSI1 host: %d\n", ret); + mipi_dsi_device_unregister(pinfo->dsi[1]); + } + + drm_panel_remove(&pinfo->panel); +} + +static int nt36523_get_modes(struct drm_panel *panel, + struct drm_connector *connector) +{ + struct panel_info *pinfo = to_panel_info(panel); + int i; + + for (i =0; i < pinfo->desc->num_modes; i++) { + const struct drm_display_mode *m = &pinfo->desc->modes[i]; + struct drm_display_mode *mode; + mode = drm_mode_duplicate(connector->dev, m); + if (!mode) { + dev_err(panel->dev, "failed to add mode %ux%u@%u\n", + m->hdisplay, m->vdisplay, drm_mode_vrefresh(m)); + return -ENOMEM; + } + mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED; + drm_mode_set_name(mode); + drm_mode_probed_add(connector, mode); + } + + connector->display_info.width_mm = pinfo->desc->width_mm; + connector->display_info.height_mm = pinfo->desc->height_mm; + connector->display_info.bpc = pinfo->desc->bpc; + + return pinfo->desc->num_modes; +} + +static const struct drm_panel_funcs nt36523_panel_funcs = { + .disable = nt36523_disable, + .prepare = nt36523_prepare, + .unprepare = nt36523_unprepare, + .get_modes = nt36523_get_modes, +}; + +static int nt36523_probe(struct mipi_dsi_device *dsi) +{ + struct device *dev = &dsi->dev; + struct device_node *dsi1; + struct mipi_dsi_host *dsi1_host; + struct panel_info *pinfo; + const struct mipi_dsi_device_info *info; + int i, ret; + + pinfo = devm_kzalloc(dev, sizeof(*pinfo), GFP_KERNEL); + if (!pinfo) + return -ENOMEM; + + pinfo->vddio = devm_regulator_get(dev, "vddio"); + if (IS_ERR(pinfo->vddio)) + return dev_err_probe(dev, PTR_ERR(pinfo->vddio), "failed to get vddio regulator\n"); + + pinfo->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH); + if (IS_ERR(pinfo->reset_gpio)) + return dev_err_probe(dev, PTR_ERR(pinfo->reset_gpio), "failed to get reset gpio\n"); + + pinfo->desc = of_device_get_match_data(dev); + if (!pinfo->desc) + return -ENODEV; + + /* If the panel is dual dsi, register DSI1 */ + if (pinfo->desc->is_dual_dsi) { + info = &pinfo->desc->dsi_info; + + dsi1 = of_graph_get_remote_node(dsi->dev.of_node, 1, -1); + if (!dsi1) { + dev_err(dev, "cannot get secondary DSI node.\n"); + return -ENODEV; + } + + dsi1_host = of_find_mipi_dsi_host_by_node(dsi1); + of_node_put(dsi1); + if (!dsi1_host) { + return dev_err_probe(dev, -EPROBE_DEFER, "cannot get secondary DSI host\n"); + } + + pinfo->dsi[1] = mipi_dsi_device_register_full(dsi1_host, info); + if (!pinfo->dsi[1]) { + dev_err(dev, "cannot get secondary DSI device\n"); + return -ENODEV; + } + } + + pinfo->dsi[0] = dsi; + mipi_dsi_set_drvdata(dsi, pinfo); + drm_panel_init(&pinfo->panel, dev, &nt36523_panel_funcs, DRM_MODE_CONNECTOR_DSI); + + ret = drm_panel_of_backlight(&pinfo->panel); + if (ret) + return dev_err_probe(dev, ret, "failed to get backlight\n"); + + drm_panel_add(&pinfo->panel); + + for (i = 0; i < DSI_NUM_MIN + pinfo->desc->is_dual_dsi; i++) { + pinfo->dsi[i]->lanes = pinfo->desc->lanes; + pinfo->dsi[i]->format = pinfo->desc->format; + pinfo->dsi[i]->mode_flags = pinfo->desc->mode_flags; + + ret = mipi_dsi_attach(pinfo->dsi[i]); + if (ret < 0) + return dev_err_probe(dev, ret, "cannot attach to DSI%d host.\n", i); + } + + return 0; +} + +static const struct of_device_id nt36523_of_match[] = { + { + .compatible = "xiaomi,elish-boe-nt36523", + .data = &elish_boe_desc, + }, + { + .compatible = "xiaomi,elish-csot-nt36523", + .data = &elish_csot_desc, + }, + {}, +}; +MODULE_DEVICE_TABLE(of, nt36523_of_match); + +static struct mipi_dsi_driver nt36523_driver = { + .probe = nt36523_probe, + .remove = nt36523_remove, + .driver = { + .name = "panel-novatek-nt36523", + .of_match_table = nt36523_of_match, + }, +}; +module_mipi_dsi_driver(nt36523_driver); + +MODULE_AUTHOR("Jianhua Lu "); +MODULE_DESCRIPTION("DRM driver for Novatek NT36523 based MIPI DSI panels"); +MODULE_LICENSE("GPL");