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[2620:137:e000::1:20]) by mx.google.com with ESMTP id d17-20020a63f251000000b004fbe30d869esi1749125pgk.268.2023.03.10.02.57.14; Fri, 10 Mar 2023 02:57:30 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=DEtHjBAd; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230062AbjCJKyc (ORCPT + 99 others); Fri, 10 Mar 2023 05:54:32 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46472 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229981AbjCJKyQ (ORCPT ); Fri, 10 Mar 2023 05:54:16 -0500 Received: from mail-pl1-x62e.google.com (mail-pl1-x62e.google.com [IPv6:2607:f8b0:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D6850E34B1; Fri, 10 Mar 2023 02:54:06 -0800 (PST) Received: by mail-pl1-x62e.google.com with SMTP id i5so5149454pla.2; Fri, 10 Mar 2023 02:54:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1678445646; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=r8Hr3QtIgBczYQFBm2I7OLr4pniDkf51aghVy6gKg5k=; b=DEtHjBAdk+4Ao8ILVr17mBoLdOTmMBfX95K/sEkKsjA1mMSQkbhefJH838YtAqHSZF lm2VOPMYBKHibdK5A1y/S/rO39ah85Mt1fK/TMYpV5OlXehyihRnKrgI7ljcWtc32+fQ 4oN135uBZPPgRJhnw76rGxH/9MtHM13G0LPWbmtspEqtjze349O62oVwF70O5tTo+HnF O+ftDtFH+yR1odivSVCcX+yGzuSoq/3AIefgMypbKG1eXOZb8kc6cLV6ypYdFFtuSAJo 3r3VwfSQpLKYQRtuW6L8B8eu6iTFTwFNkgBpicGk0aWaIF2a0f4Wqgtb2ujc/h7ejHRR 00eg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678445646; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=r8Hr3QtIgBczYQFBm2I7OLr4pniDkf51aghVy6gKg5k=; b=l18hLU7bmgThKa4cS+Ie+Fq7JkhkiIiBoy1KoC6VTHiHsoWj8DUAKYubwwhedbx14Z 69SXfK2s++wvEmoAa8OCopxxbY6Fu2CCxqamLSJNW6nnj4BQ9dCEx8g4gYcS6JbUmVhC iu50+vFlPojuAtZA7uAhHETynp7DO1Z6NB/Kj1RiNxvV9ee3g1NSVjtqn2rOduq+LMok xANF2e6jpcz7rQmTZSinE7GCWWA2FCT23gFDtdZ7SoD1BS9XIFzC39ZMoEiPXzQ0oBVd QjRFY+T5HUvu+PMjaCNbMaQTJthim9lbcpU+mF0yP3DUVTqWN6oe+9A0Cc3Z6tBmaeTW Y09g== X-Gm-Message-State: AO0yUKV5PD/Q/Z7tl/t8lHi1LXEVM41aqWSjUeL6YXVdJ3zsuU02K5Vq eyA0y4628VyZ7I9Bznbv8as= X-Received: by 2002:a17:903:283:b0:19e:b9f8:1fca with SMTP id j3-20020a170903028300b0019eb9f81fcamr20596720plr.10.1678445646322; Fri, 10 Mar 2023 02:54:06 -0800 (PST) Received: from localhost.localdomain ([103.7.29.32]) by smtp.gmail.com with ESMTPSA id ks3-20020a170903084300b0019cbabf127dsm1174167plb.182.2023.03.10.02.54.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Mar 2023 02:54:06 -0800 (PST) From: Like Xu X-Google-Original-From: Like Xu To: Sean Christopherson Cc: Paolo Bonzini , Ravi Bangoria , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/5] KVM: x86/pmu: Emulate CTR overflow directly in kvm_pmu_handle_event() Date: Fri, 10 Mar 2023 18:53:42 +0800 Message-Id: <20230310105346.12302-2-likexu@tencent.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230310105346.12302-1-likexu@tencent.com> References: <20230310105346.12302-1-likexu@tencent.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759978036375299940?= X-GMAIL-MSGID: =?utf-8?q?1759978036375299940?= From: Like Xu More and more vPMU emulations are deferred to kvm_pmu_handle_event() as it reduces the overhead of repeated execution. The reprogram_counter() is only responsible for creating the required perf_event, and naturally doesn't include the counter overflow part from emulated instruction events. Prior to this change, the assignment of pmc->prev_counter always occurred after pmc was enabled, and to keep the same semantics, pmc->prev_counter always needed to be reset after it has taken effect. No functional change intended. Signed-off-by: Like Xu --- arch/x86/kvm/pmu.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index a1a79b5f49d7..d1c89a6625a0 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c @@ -418,9 +418,6 @@ static void reprogram_counter(struct kvm_pmc *pmc) if (!event_is_allowed(pmc)) goto reprogram_complete; - if (pmc->counter < pmc->prev_counter) - __kvm_perf_overflow(pmc, false); - if (eventsel & ARCH_PERFMON_EVENTSEL_PIN_CONTROL) printk_once("kvm pmu: pin control bit is ignored\n"); @@ -458,6 +455,13 @@ static void reprogram_counter(struct kvm_pmc *pmc) reprogram_complete: clear_bit(pmc->idx, (unsigned long *)&pmc_to_pmu(pmc)->reprogram_pmi); +} + +static inline void kvm_pmu_handle_pmc_overflow(struct kvm_pmc *pmc) +{ + if (pmc->counter < pmc->prev_counter) + __kvm_perf_overflow(pmc, false); + pmc->prev_counter = 0; } @@ -475,6 +479,7 @@ void kvm_pmu_handle_event(struct kvm_vcpu *vcpu) } reprogram_counter(pmc); + kvm_pmu_handle_pmc_overflow(pmc); } /* From patchwork Fri Mar 10 10:53:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Like Xu X-Patchwork-Id: 67354 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp800881wrd; Fri, 10 Mar 2023 02:55:30 -0800 (PST) X-Google-Smtp-Source: AK7set9Ntv1O/UaWeANNUxyfvWpyaCpmE7h9QfvRT9j6Hp2VwGoN2pkoIVlIPNJ+aZufZRGT2QOg X-Received: by 2002:a17:902:ec91:b0:19b:2332:18cb with SMTP id x17-20020a170902ec9100b0019b233218cbmr31190875plg.1.1678445729708; Fri, 10 Mar 2023 02:55:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1678445729; cv=none; d=google.com; s=arc-20160816; b=J/nKjwFsq3oUbdfe16gSsRni/JdB9GqkRBGLu0CdTrKGg4dcQ5M49ebMv77CXVZuVf Ag1AObBGksOaw2a9h/74gpRkKowg9dNcC3/bZFoTdMCXVvdN3gdG1gIaAGHfAwYwapSz ZHBSms5pIZzK8OqsFZ8d/1uxFW22WLzRVfITKX+M6X7Fdd8RSMVu/GvF3XqG17+Hr3Sp lOjFJusRBkrVH7/VR7tWu9m+MoEaRTG1w547U5C4fjh/+ySHOp6JgkjHRxjY9Yh9mF1K rSxRPI8Co0qaNPmcDbB1KXxOvhpEsq8lC7eePidkiV3cfbqMNDasgCNXObCCEwTf6bno Cilw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=G4nlGjUeIFU1ciO0H/3MLCy3YXN9ZRSdwoj+bqo8KVo=; b=TxAdfZMWyjYAVkoY5McnhB6UAwL26sTc30iWI6w4LssLiafoXXiS3GEIzrQLv884ls g7Sxhxk/9RCtGoXaHeib7kdtjX8NJ7aXaaDZAyK+LOqrt1Ggx0dMII5YTDjAYGTKr5TL Rlpcut3KT5ehkTdMYivMbVWHT1vSYt/rwpIFO6EbGCsfNEXosjAu2YaE3gOFJ0y1C3vo I5qJtSVjS3FyAKVHe7OBFtenPIHZD5cwSssDQ+YnhqxLtWPctY7m7jPYKL7l+MP2H7nm H2gnIO1ont/cP2G8plIZeTm0Suv2EG5v7qEcrwDSAT8ceSlM02UK85mQZLG41IEXTc4u OeHQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=eHN8RTG6; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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No functional change intended. Signed-off-by: Like Xu --- arch/x86/kvm/pmu.c | 3 +-- arch/x86/kvm/pmu.h | 7 +++++++ 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index d1c89a6625a0..01a6b7ffa9b1 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c @@ -191,7 +191,6 @@ static int pmc_reprogram_counter(struct kvm_pmc *pmc, u32 type, u64 config, bool exclude_user, bool exclude_kernel, bool intr) { - struct kvm_pmu *pmu = pmc_to_pmu(pmc); struct perf_event *event; struct perf_event_attr attr = { .type = type, @@ -203,7 +202,7 @@ static int pmc_reprogram_counter(struct kvm_pmc *pmc, u32 type, u64 config, .exclude_kernel = exclude_kernel, .config = config, }; - bool pebs = test_bit(pmc->idx, (unsigned long *)&pmu->pebs_enable); + bool pebs = pebs_is_enabled(pmc); attr.sample_period = get_sample_period(pmc, pmc->counter); diff --git a/arch/x86/kvm/pmu.h b/arch/x86/kvm/pmu.h index cff0651b030b..db4262fe8814 100644 --- a/arch/x86/kvm/pmu.h +++ b/arch/x86/kvm/pmu.h @@ -189,6 +189,13 @@ static inline void kvm_pmu_request_counter_reprogram(struct kvm_pmc *pmc) kvm_make_request(KVM_REQ_PMU, pmc->vcpu); } +static inline bool pebs_is_enabled(struct kvm_pmc *pmc) +{ + struct kvm_pmu *pmu = pmc_to_pmu(pmc); + + return test_bit(pmc->idx, (unsigned long *)&pmu->pebs_enable); +} + void kvm_pmu_deliver_pmi(struct kvm_vcpu *vcpu); void kvm_pmu_handle_event(struct kvm_vcpu *vcpu); int kvm_pmu_rdpmc(struct kvm_vcpu *vcpu, unsigned pmc, u64 *data); From patchwork Fri Mar 10 10:53:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Like Xu X-Patchwork-Id: 67358 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp801682wrd; Fri, 10 Mar 2023 02:58:14 -0800 (PST) X-Google-Smtp-Source: AK7set8LH/WqTCVYi9fjfuhVWhWoYpAc12kElXZ0Q5mVo93ZrQ6gXpR6V4OHO7ggC/NLdPCe7rTh X-Received: by 2002:a05:6a20:7290:b0:b8:a0e1:2739 with SMTP id o16-20020a056a20729000b000b8a0e12739mr26505078pzk.3.1678445894466; Fri, 10 Mar 2023 02:58:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1678445894; cv=none; d=google.com; s=arc-20160816; b=HAyjIZJmri2qNv03Ms9NUWfCpo5VL2eWDoi/l+PXcbkZXY0z5bdSXb1WzfQIfdJAld 9z0SKB3wGQvLUEGSOcMXVM+oIkkRBX9A2nbcifJMP6rEO6YoJDrVpE09/313yuMP1zyJ Wy5C/0MI+YA51hFV2+d38wYUpubeK1w6cvcBxQxX8AsZz62ZZh4MP3DQok312r/p1Igl WTBLYpqTFqfofpsD72L9jBrUAqg0uBUoN4c8QLSrEL9e0piXNHkACC5GeDaXTpcL0jxH SiVGz4AsCl2EEL8tFewA3+GQFe5IxrOzDys1jvKPa8hoQRyUNQieHlkUgJujI03q0c+2 oM3Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=TuKuJgCQ/AJK9oB9PxBqMc3IiOj3CxcIYL84H7LCcFk=; b=NDx1yw+hEze/ttRuh6ykOVf5uhsrXiCBDVwpQ6KfF1qMatTkNPC0yw63tuZ1aecqtF Z2JJNk1sEi+qfAs8pXsY/RHwtVJ5Q97G8WVUF3LePp52WyWu/0on0qzvuKgaBnZROI3c emr5+Q/J/3inyI0WvWPVCNvh6RHjP1Xx7+87ZOaJNqMSLr4lwtCGirRWnVJ1AZiZRSzq 5UzvBi0gogkMcpqPy4oXFgXGqaDXb5hZ5t7zFOHPNfPdqR+B+bdDelIJDZ2/aNyk8pL9 1uqQL5ZOTbt0xSUnF5iPuCf4ifFz7DbE4IVw0mPeTWtJ5QQo/TH9D2UY8RgnAwDOFuk2 vc4Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=oP2GQg1n; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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The guest counter overflow emulation only depends on whether pmc->counter has an overflow or not. Plus the counter overflow generated by the emulation instruction has been delayed and not been handled in the PMI context. This part of the logic can be unified by reusing pmc->prev_counter for a normal counter. However for a PEBS counter, its buffer overflow irq still requires hardware to trigger PMI. Signed-off-by: Like Xu --- arch/x86/kvm/pmu.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index 01a6b7ffa9b1..81c7cc4ceadf 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c @@ -160,7 +160,10 @@ static void kvm_perf_overflow(struct perf_event *perf_event, if (test_and_set_bit(pmc->idx, pmc_to_pmu(pmc)->reprogram_pmi)) return; - __kvm_perf_overflow(pmc, true); + if (pebs_is_enabled(pmc)) + __kvm_perf_overflow(pmc, true); + else + pmc->prev_counter = pmc->counter; kvm_make_request(KVM_REQ_PMU, pmc->vcpu); } From patchwork Fri Mar 10 10:53:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Like Xu X-Patchwork-Id: 67357 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp801529wrd; Fri, 10 Mar 2023 02:57:43 -0800 (PST) X-Google-Smtp-Source: AK7set/k7a+Pmqr6K6erAVf/UoMJmuZS5nznIqWafc0WxZ/FQOnBziE16TD/oDOpv90i3mXmPLDu X-Received: by 2002:a17:90a:7489:b0:230:7a3a:d4cc with SMTP id p9-20020a17090a748900b002307a3ad4ccmr26009897pjk.43.1678445863555; Fri, 10 Mar 2023 02:57:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1678445863; cv=none; d=google.com; s=arc-20160816; b=Ked/GLkk43vDaK7wKpEs2nrdoYhEk6y+3l3hngH2TEIF7G+/6cUu3719Rng/nrLnqn yp0/OyZAHzyHIuzOhdjN6+KKBuB6ZFGFdQ6mnAquGnfroNWaRKMueM8U63nSOhVtGwue S6MbXnI4VpZkAXgZS1k1mxc0GHONgtkTZy673bZzcREh9VTtdQgsW6aDbmxOrh1OiEgD 7OkApA7d2hoULYgNChughD5jwLBsbNUfVSLR28M/zN7jCjsu91mrlqOGCD/cGJNGJ7lL qP3XHDe106IARSn7/dtIfBCd0u/diBlbdTnXHYQYPFl0noal32njYyksYSwkOUsz8Hrd 2ypw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=EEzHwUubKyQzeZbhTkJFVtBrjdYEyf0DVFK0mJ5dj7w=; b=iNrjK+SkBkXQ3lm++hJCxyttFhQBuJ6bvrbh5pUCKz4WkDPrnf+rfrZeLZjTOo40ej E/GLg38SkZLHi3Z+4+OeCkx/kUVLjbt20kCuyrjMmCSS9RjsGkC9ce7J9neY0B0xYJWc /1SHVER++xePCFVL7MPnx7xcfA9cAJ6w0aXeK4DTeiicouUZATueYy36faB54Xlir9oX 1cyZHFdW5cqJeQ2NZa7VtMeLZ4lXtqcU5EAC4Z+7B9lZEgw9Gp9ybbDM0tr0iQvyNoEL A30cqjGAKkvH3eH1BEucbHc2I1F1tVBC3Zsv84K9F8NNTGwNkHkx5dE4HkLzPvK1GMgB Z+xw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=ZINmPDTb; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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The same motivation is applied to kvm_pmu_request_counter_reprogram(), as it is the trigger for any emulations delay. No functional change intended. Signed-off-by: Like Xu --- arch/x86/kvm/pmu.c | 52 +++++++++++++++++++++++----------------------- arch/x86/kvm/pmu.h | 12 +++++------ 2 files changed, 32 insertions(+), 32 deletions(-) diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index 81c7cc4ceadf..2a0504732966 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c @@ -467,32 +467,6 @@ static inline void kvm_pmu_handle_pmc_overflow(struct kvm_pmc *pmc) pmc->prev_counter = 0; } -void kvm_pmu_handle_event(struct kvm_vcpu *vcpu) -{ - struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); - int bit; - - for_each_set_bit(bit, pmu->reprogram_pmi, X86_PMC_IDX_MAX) { - struct kvm_pmc *pmc = static_call(kvm_x86_pmu_pmc_idx_to_pmc)(pmu, bit); - - if (unlikely(!pmc)) { - clear_bit(bit, pmu->reprogram_pmi); - continue; - } - - reprogram_counter(pmc); - kvm_pmu_handle_pmc_overflow(pmc); - } - - /* - * Unused perf_events are only released if the corresponding MSRs - * weren't accessed during the last vCPU time slice. kvm_arch_sched_in - * triggers KVM_REQ_PMU if cleanup is needed. - */ - if (unlikely(pmu->need_cleanup)) - kvm_pmu_cleanup(vcpu); -} - /* check if idx is a valid index to access PMU */ bool kvm_pmu_is_valid_rdpmc_ecx(struct kvm_vcpu *vcpu, unsigned int idx) { @@ -847,3 +821,29 @@ int kvm_vm_ioctl_set_pmu_event_filter(struct kvm *kvm, void __user *argp) kfree(filter); return r; } + +void kvm_pmu_handle_event(struct kvm_vcpu *vcpu) +{ + struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); + int bit; + + for_each_set_bit(bit, pmu->reprogram_pmi, X86_PMC_IDX_MAX) { + struct kvm_pmc *pmc = static_call(kvm_x86_pmu_pmc_idx_to_pmc)(pmu, bit); + + if (unlikely(!pmc)) { + clear_bit(bit, pmu->reprogram_pmi); + continue; + } + + reprogram_counter(pmc); + kvm_pmu_handle_pmc_overflow(pmc); + } + + /* + * Unused perf_events are only released if the corresponding MSRs + * weren't accessed during the last vCPU time slice. kvm_arch_sched_in + * triggers KVM_REQ_PMU if cleanup is needed. + */ + if (unlikely(pmu->need_cleanup)) + kvm_pmu_cleanup(vcpu); +} diff --git a/arch/x86/kvm/pmu.h b/arch/x86/kvm/pmu.h index db4262fe8814..a47b579667c6 100644 --- a/arch/x86/kvm/pmu.h +++ b/arch/x86/kvm/pmu.h @@ -48,6 +48,12 @@ static inline u64 pmc_bitmask(struct kvm_pmc *pmc) return pmu->counter_bitmask[pmc->type]; } +static inline void kvm_pmu_request_counter_reprogram(struct kvm_pmc *pmc) +{ + set_bit(pmc->idx, pmc_to_pmu(pmc)->reprogram_pmi); + kvm_make_request(KVM_REQ_PMU, pmc->vcpu); +} + static inline u64 pmc_read_counter(struct kvm_pmc *pmc) { u64 counter, enabled, running; @@ -183,12 +189,6 @@ static inline void kvm_init_pmu_capability(const struct kvm_pmu_ops *pmu_ops) KVM_PMC_MAX_FIXED); } -static inline void kvm_pmu_request_counter_reprogram(struct kvm_pmc *pmc) -{ - set_bit(pmc->idx, pmc_to_pmu(pmc)->reprogram_pmi); - kvm_make_request(KVM_REQ_PMU, pmc->vcpu); -} - static inline bool pebs_is_enabled(struct kvm_pmc *pmc) { struct kvm_pmu *pmu = pmc_to_pmu(pmc); From patchwork Fri Mar 10 10:53:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Like Xu X-Patchwork-Id: 67355 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp801015wrd; Fri, 10 Mar 2023 02:55:58 -0800 (PST) X-Google-Smtp-Source: AK7set/Lifkh32p3ZQAMxJF7NGySObHUCCHn1PFI6ghd25WV5kPjSRCP6srAfmd0OpBv9O41ULl9 X-Received: by 2002:a05:6a20:9147:b0:cc:da74:9c5e with SMTP id x7-20020a056a20914700b000ccda749c5emr29012445pzc.35.1678445758446; Fri, 10 Mar 2023 02:55:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1678445758; cv=none; d=google.com; s=arc-20160816; b=JJGLNotEWEH77CxcrcZd8ahRp0Ntf2qwaZfuJ5CEOmcyy+ZzGmyF6DLq5gH6RAWQTd DPOvH34L/xZIkfE1ZIxma7FQus4Ls8vfqwfhdYXic8ymRWflsyY+/AHEVRk71oDnGHWB Li2/UoHOsEUznfkk0T5f4rO9z6QXXNvKSVAaR6OuyNBYo+oxfhbdPCaGwS42CK0mutjP RTtRECxvpdzeqLDH27YOYEfNdKouZK6hjE/wsulmLPC4lOwuL0pXqCiPAxWiseuj33TV GCnrcyVQ8t+Jkda7RwqJhcBkZUPmsblmp95S2IH2PBHIKFi7hrGCg+HnGPrgTXvYoGWJ /4Tg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=0wyg7PPl9oMWqL20HC/bqjAELVsUWzLxhdgpFsSisLM=; b=EMbE4qP0cPhyvhZg64jjfs6g9mwsui+v99ZeoAO/9WUQnuZtyCvfLwsFMU+foqPYLJ 5euflT3L/ttUbJHBu36Bd0PPuMzeixcxMmzPQujKdKZhty3hsD7EADUsgZmRmM9/P7o2 t2Hr1UD7q7ZvZEa9B8fMFKasWIbYoLAce46wX8M7fnO3Y7A1D0xRX4eVTeq2B+1HIRpw Ryab77q4lmDEPWUbzrwMk0cpI1z3NHUKqpgurQbvxo+tYlC2ET0aZ4/MZKcf0H3I9tdC 1THbgxiPn5xTjDbqeYDb8CGxGqaDr2XWakHHcZWngpRecUS5q6S1renwsJThQOXDSjXm vIzw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b="jn/kMMaN"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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Based on a number of micro observations (also the reason why x86_64/ pmu_event_filter_test fails on AMD Zen platforms), each VMRUN will increment all hw-(branch)-instructions counters by 1, even if they are only enabled for guest code. This issue seriously affects the performance understanding of guest developers based on (branch) instruction events. If the current physical register value on the hardware is ~0x0, it triggers an overflow in the guest world right after running VMRUN. Although this cannot be avoided on mainstream released hardware, the resulting PMI (if configured) will not be incorrectly injected into the guest by vPMU, since the delayed injection mechanism for a normal counter overflow depends only on the change of pmc->counter values. The pmu_hide_vmrun() is called before each VMRUN and its overhead depends on the number of counters enabled by the guest and is negligible when none of the counters are used. Cc: Ravi Bangoria Signed-off-by: Like Xu --- arch/x86/include/asm/kvm_host.h | 4 ++++ arch/x86/kvm/pmu.c | 18 ++++++++++++++++++ arch/x86/kvm/pmu.h | 24 +++++++++++++++++++++++- arch/x86/kvm/svm/pmu.c | 1 + arch/x86/kvm/svm/svm.c | 28 ++++++++++++++++++++++++++++ 5 files changed, 74 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h index adb92fc4d7c9..d6fcbf233cb3 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -561,6 +561,10 @@ struct kvm_pmu { */ u64 host_cross_mapped_mask; + /* Flags to track any HW quirks that need to be fixed by vPMU. */ + u64 quirk_flags; + DECLARE_BITMAP(hide_vmrun_pmc_idx, X86_PMC_IDX_MAX); + /* * The gate to release perf_events not marked in * pmc_in_use only once in a vcpu time slice. diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index 2a0504732966..315dca021d57 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c @@ -254,6 +254,7 @@ static void pmc_pause_counter(struct kvm_pmc *pmc) counter += perf_event_pause(pmc->perf_event, true); pmc->counter = counter & pmc_bitmask(pmc); pmc->is_paused = true; + kvm_mark_pmc_is_quirky(pmc); } static bool pmc_resume_counter(struct kvm_pmc *pmc) @@ -822,6 +823,19 @@ int kvm_vm_ioctl_set_pmu_event_filter(struct kvm *kvm, void __user *argp) return r; } +static inline bool event_is_branch_instruction(struct kvm_pmc *pmc) +{ + return eventsel_match_perf_hw_id(pmc, PERF_COUNT_HW_INSTRUCTIONS) || + eventsel_match_perf_hw_id(pmc, + PERF_COUNT_HW_BRANCH_INSTRUCTIONS); +} + +static inline bool quirky_pmc_will_count_vmrun(struct kvm_pmc *pmc) +{ + return event_is_branch_instruction(pmc) && event_is_allowed(pmc) && + !static_call(kvm_x86_get_cpl)(pmc->vcpu); +} + void kvm_pmu_handle_event(struct kvm_vcpu *vcpu) { struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); @@ -837,6 +851,10 @@ void kvm_pmu_handle_event(struct kvm_vcpu *vcpu) reprogram_counter(pmc); kvm_pmu_handle_pmc_overflow(pmc); + + if (vcpu_has_pmu_quirks(vcpu) && + quirky_pmc_will_count_vmrun(pmc)) + set_bit(pmc->idx, pmu->hide_vmrun_pmc_idx); } /* diff --git a/arch/x86/kvm/pmu.h b/arch/x86/kvm/pmu.h index a47b579667c6..30f6f58f4c38 100644 --- a/arch/x86/kvm/pmu.h +++ b/arch/x86/kvm/pmu.h @@ -18,6 +18,9 @@ #define VMWARE_BACKDOOR_PMC_REAL_TIME 0x10001 #define VMWARE_BACKDOOR_PMC_APPARENT_TIME 0x10002 +#define X86_PMU_COUNT_VMRUN BIT_ULL(0) +#define X86_PMU_QUIRKS_MASK X86_PMU_COUNT_VMRUN + struct kvm_pmu_ops { bool (*hw_event_available)(struct kvm_pmc *pmc); bool (*pmc_is_enabled)(struct kvm_pmc *pmc); @@ -54,14 +57,33 @@ static inline void kvm_pmu_request_counter_reprogram(struct kvm_pmc *pmc) kvm_make_request(KVM_REQ_PMU, pmc->vcpu); } +static inline bool vcpu_has_pmu_quirks(struct kvm_vcpu *vcpu) +{ + return vcpu_to_pmu(vcpu)->quirk_flags & X86_PMU_QUIRKS_MASK; +} + +/* + * The time to mark pmc is when the accumulation value returned + * by perf API based on a HW counter has just taken effect. + */ +static inline void kvm_mark_pmc_is_quirky(struct kvm_pmc *pmc) +{ + if (!vcpu_has_pmu_quirks(pmc->vcpu)) + return; + + kvm_pmu_request_counter_reprogram(pmc); +} + static inline u64 pmc_read_counter(struct kvm_pmc *pmc) { u64 counter, enabled, running; counter = pmc->counter; - if (pmc->perf_event && !pmc->is_paused) + if (pmc->perf_event && !pmc->is_paused) { counter += perf_event_read_value(pmc->perf_event, &enabled, &running); + kvm_mark_pmc_is_quirky(pmc); + } /* FIXME: Scaling needed? */ return counter & pmc_bitmask(pmc); } diff --git a/arch/x86/kvm/svm/pmu.c b/arch/x86/kvm/svm/pmu.c index 5fa939e411d8..130991a97f22 100644 --- a/arch/x86/kvm/svm/pmu.c +++ b/arch/x86/kvm/svm/pmu.c @@ -187,6 +187,7 @@ static void amd_pmu_refresh(struct kvm_vcpu *vcpu) pmu->nr_arch_fixed_counters = 0; pmu->global_status = 0; bitmap_set(pmu->all_valid_pmc_idx, 0, pmu->nr_arch_gp_counters); + pmu->quirk_flags |= X86_PMU_COUNT_VMRUN; } static void amd_pmu_init(struct kvm_vcpu *vcpu) diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index f41d96e638ef..f6b33d172481 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -3919,6 +3919,31 @@ static fastpath_t svm_exit_handlers_fastpath(struct kvm_vcpu *vcpu) return EXIT_FASTPATH_NONE; } +static void pmu_hide_vmrun(struct kvm_vcpu *vcpu) +{ + struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); + struct kvm_pmc *pmc; + unsigned int i; + + for_each_set_bit(i, pmu->hide_vmrun_pmc_idx, X86_PMC_IDX_MAX) { + clear_bit(i, pmu->hide_vmrun_pmc_idx); + + /* AMD doesn't have fixed counters at now. */ + if (i >= pmu->nr_arch_gp_counters) + continue; + + /* + * The prerequisite for fixing HW quirks is that there is indeed + * HW working and perf has no chance to retrieve the counter. + */ + pmc = &pmu->gp_counters[i]; + if (!pmc->perf_event || pmc->perf_event->hw.idx < 0) + continue; + + pmc->counter--; + } +} + static noinstr void svm_vcpu_enter_exit(struct kvm_vcpu *vcpu, bool spec_ctrl_intercepted) { struct vcpu_svm *svm = to_svm(vcpu); @@ -3986,6 +4011,9 @@ static __no_kcsan fastpath_t svm_vcpu_run(struct kvm_vcpu *vcpu) kvm_wait_lapic_expire(vcpu); + if (vcpu->kvm->arch.enable_pmu && vcpu_has_pmu_quirks(vcpu)) + pmu_hide_vmrun(vcpu); + /* * If this vCPU has touched SPEC_CTRL, restore the guest's value if * it's non-zero. Since vmentry is serialising on affected CPUs, there