From patchwork Fri Mar 10 09:23:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrzej Hajda X-Patchwork-Id: 67306 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp770969wrd; Fri, 10 Mar 2023 01:29:53 -0800 (PST) X-Google-Smtp-Source: AK7set9EwDualOjTrfp4JFy3oqTTg0kZ3iIlGBA+cwrnPcM+mYHib3X3JU3eqSxBrYJuCtAcHQVM X-Received: by 2002:a17:90b:4a04:b0:233:d10f:5236 with SMTP id kk4-20020a17090b4a0400b00233d10f5236mr25655455pjb.28.1678440593339; Fri, 10 Mar 2023 01:29:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1678440593; cv=none; d=google.com; s=arc-20160816; b=E8nsRX+FQGTRHSy0OP/mg23dJsPTul3SYx1InEaJJMKupYFuNQVikVabpW2xn2oajY jboSM9d1UkEE1mQVqiv9WRrPeezaViNrPXp5ojCsYZU294dkQxdfKDDHIL9MTAYynCh6 8vSe/1BpxRSOZj2O1GbZI3GPsR3hX5dFo6KzK6NQ2gR+hqPaYZ0Rmh/ofqUpm6Xu10WC T4oQdCGXkEIqVa7FeZjIQiOLHLqWPvi8Jw1Ck+Cg+nNdMKinAe7dIXeG/RhHdxfFxk7D 9G5ZsirXMnGb4R9GN96bhbSGOMQT9fsNl4OUQa1gU95aLRDN5LELMaRVqOPvnFpGEE/6 409A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=BmyslXwd+Lp9O2JJH6wH9MmaIujKa8lfRzTJM0jedB0=; b=UaoySnDkHasfsZn2XSTt9WJ7n7RAhUjlYJ/sL0FPIqmxLnndzWyWWlcr2bPyRH2i86 52xGr14a1dwbH9mPNPncvnTx52sdkcUUD3In1TT7lwMPk+xOXJCW6lFV9ZiLm6Qcia8s mWsKQ/v0L8I2hgUGprbb/Smt6rgD9PM2KJtfK8K2Tt8r3LK0vLdgMzsNIgDRLfqVFCNx VulYjiUtejZchwkCCfkbG/enFaYtzNIpvW/RRPbuCDkw6tJkBY7qkeICkCFgfewHhgph +foXX1K9pZmM5eTleOtjwQUnfRf9ThxRP6Q1WshZVy8v4+8M7Cgi+Lsp2eq0t+yYKHA+ QCbg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=NOOZitZp; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id lp11-20020a17090b4a8b00b002333adf6321si2331811pjb.47.2023.03.10.01.29.41; Fri, 10 Mar 2023 01:29:53 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=NOOZitZp; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230293AbjCJJ1r (ORCPT + 99 others); Fri, 10 Mar 2023 04:27:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56640 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230186AbjCJJ1Z (ORCPT ); Fri, 10 Mar 2023 04:27:25 -0500 Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 72C6C7DD19 for ; Fri, 10 Mar 2023 01:24:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1678440246; x=1709976246; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=R0AdssSd3MB0iqXVxNOU/ybf/QikA5OF/cilaWGDpiE=; b=NOOZitZptuOnfV8F29tlt81r5EOEakCc+IfinoUSwF+KNkniV/bticyx BwJx8vrXthpDjhC9ndNgE5jgUup91xIb5exXLW1ZDrs+H0OVBOC5bbURF S3T1X8Ukw0zstLMwfeoyVK14vj8zHS5LcKMQzv3ssfxr55OqyPqT3oG9H yNAR6TJ3aaLwWqv33/8QteQWghoZMVFLvx4l4sQj7F7+SvllFgX3G78U/ GctM+5dyOiG7Jtd6lM2wp1u3sRaOItNXyntF1t7gaxg8JJhXhw2e6TEye 6IaOExhRMLc6Etv5Ko01lzJhzm1VcBZQUIhsgQDKTO7Mm0maN33wkygCp g==; X-IronPort-AV: E=McAfee;i="6500,9779,10644"; a="334164680" X-IronPort-AV: E=Sophos;i="5.98,249,1673942400"; d="scan'208";a="334164680" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Mar 2023 01:24:06 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10644"; a="801513244" X-IronPort-AV: E=Sophos;i="5.98,249,1673942400"; d="scan'208";a="801513244" Received: from lab-ah.igk.intel.com ([10.102.42.211]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Mar 2023 01:24:03 -0800 From: Andrzej Hajda Date: Fri, 10 Mar 2023 10:23:49 +0100 Subject: [PATCH v6 1/2] drm/i915/gt: introduce vm->scratch_range callback MIME-Version: 1.0 Message-Id: <20230308-guard_error_capture-v6-1-1b5f31422563@intel.com> References: <20230308-guard_error_capture-v6-0-1b5f31422563@intel.com> In-Reply-To: <20230308-guard_error_capture-v6-0-1b5f31422563@intel.com> To: Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Andi Shyti , Chris Wilson , Nirmoy Das , Andrzej Hajda X-Mailer: b4 0.11.1 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759972523558107270?= X-GMAIL-MSGID: =?utf-8?q?1759972523558107270?= The callback will be responsible for setting scratch page PTEs for specified range. In contrast to clear_range it cannot be optimized to nop. It will be used by code adding guard pages. Signed-off-by: Andrzej Hajda Reviewed-by: Nirmoy Das Reviewed-by: Andi Shyti --- drivers/gpu/drm/i915/gt/intel_ggtt.c | 23 +++++++++++++++++++++++ drivers/gpu/drm/i915/gt/intel_ggtt_gmch.c | 1 + drivers/gpu/drm/i915/gt/intel_gtt.h | 2 ++ 3 files changed, 26 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c index 842e69c7b21e49..38e6f0b207fe0c 100644 --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c @@ -291,6 +291,27 @@ static void gen8_ggtt_insert_entries(struct i915_address_space *vm, ggtt->invalidate(ggtt); } +static void gen8_ggtt_clear_range(struct i915_address_space *vm, + u64 start, u64 length) +{ + struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); + unsigned int first_entry = start / I915_GTT_PAGE_SIZE; + unsigned int num_entries = length / I915_GTT_PAGE_SIZE; + const gen8_pte_t scratch_pte = vm->scratch[0]->encode; + gen8_pte_t __iomem *gtt_base = + (gen8_pte_t __iomem *)ggtt->gsm + first_entry; + const int max_entries = ggtt_total_entries(ggtt) - first_entry; + int i; + + if (WARN(num_entries > max_entries, + "First entry = %d; Num entries = %d (max=%d)\n", + first_entry, num_entries, max_entries)) + num_entries = max_entries; + + for (i = 0; i < num_entries; i++) + gen8_set_pte(>t_base[i], scratch_pte); +} + static void gen6_ggtt_insert_page(struct i915_address_space *vm, dma_addr_t addr, u64 offset, @@ -919,6 +940,7 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt) ggtt->vm.cleanup = gen6_gmch_remove; ggtt->vm.insert_page = gen8_ggtt_insert_page; ggtt->vm.clear_range = nop_clear_range; + ggtt->vm.scratch_range = gen8_ggtt_clear_range; ggtt->vm.insert_entries = gen8_ggtt_insert_entries; @@ -1082,6 +1104,7 @@ static int gen6_gmch_probe(struct i915_ggtt *ggtt) ggtt->vm.clear_range = nop_clear_range; if (!HAS_FULL_PPGTT(i915)) ggtt->vm.clear_range = gen6_ggtt_clear_range; + ggtt->vm.scratch_range = gen6_ggtt_clear_range; ggtt->vm.insert_page = gen6_ggtt_insert_page; ggtt->vm.insert_entries = gen6_ggtt_insert_entries; ggtt->vm.cleanup = gen6_gmch_remove; diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_gmch.c b/drivers/gpu/drm/i915/gt/intel_ggtt_gmch.c index 77c793812eb46a..d6a74ae2527bd9 100644 --- a/drivers/gpu/drm/i915/gt/intel_ggtt_gmch.c +++ b/drivers/gpu/drm/i915/gt/intel_ggtt_gmch.c @@ -102,6 +102,7 @@ int intel_ggtt_gmch_probe(struct i915_ggtt *ggtt) ggtt->vm.insert_page = gmch_ggtt_insert_page; ggtt->vm.insert_entries = gmch_ggtt_insert_entries; ggtt->vm.clear_range = gmch_ggtt_clear_range; + ggtt->vm.scratch_range = gmch_ggtt_clear_range; ggtt->vm.cleanup = gmch_ggtt_remove; ggtt->invalidate = gmch_ggtt_invalidate; diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h index 5a775310d3fcb5..69ce55f517f567 100644 --- a/drivers/gpu/drm/i915/gt/intel_gtt.h +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h @@ -298,6 +298,8 @@ struct i915_address_space { u64 start, u64 length); void (*clear_range)(struct i915_address_space *vm, u64 start, u64 length); + void (*scratch_range)(struct i915_address_space *vm, + u64 start, u64 length); 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If this PTE points to invalid address DMAR errors will occur. This behaviour was observed on ADL and RPL platforms. To avoid it, guard scratch page should be added after error_capture. The patch fixes the most annoying issue with error capture but since WC reads are used also in other places there is a risk similar problem can affect them as well. v2: - modified commit message (I hope the diagnosis is correct), - added bug checks to ensure scratch is initialized on gen3 platforms. CI produces strange stacktrace for it suggesting scratch[0] is NULL, to be removed after resolving the issue with gen3 platforms. v3: - removed bug checks, replaced with gen check. v4: - change code for scratch page insertion to support all platforms, - add info in commit message there could be more similar issues v5: - check for nop_clear_range instead of gen8 (Tvrtko), - re-insert scratch pages on resume (Tvrtko) v6: - use scratch_range callback to set scratch pages (Chris) Signed-off-by: Andrzej Hajda Reviewed-by: Andi Shyti Acked-by: Nirmoy Das --- drivers/gpu/drm/i915/gt/intel_ggtt.c | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c index 38e6f0b207fe0c..5ef7e03b11c8e6 100644 --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c @@ -572,8 +572,12 @@ static int init_ggtt(struct i915_ggtt *ggtt) * paths, and we trust that 0 will remain reserved. However, * the only likely reason for failure to insert is a driver * bug, which we expect to cause other failures... + * + * Since CPU can perform speculative reads on error capture + * (write-combining allows it) add scratch page after error + * capture to avoid DMAR errors. */ - ggtt->error_capture.size = I915_GTT_PAGE_SIZE; + ggtt->error_capture.size = 2 * I915_GTT_PAGE_SIZE; ggtt->error_capture.color = I915_COLOR_UNEVICTABLE; if (drm_mm_reserve_node(&ggtt->vm.mm, &ggtt->error_capture)) drm_mm_insert_node_in_range(&ggtt->vm.mm, @@ -583,11 +587,15 @@ static int init_ggtt(struct i915_ggtt *ggtt) 0, ggtt->mappable_end, DRM_MM_INSERT_LOW); } - if (drm_mm_node_allocated(&ggtt->error_capture)) + if (drm_mm_node_allocated(&ggtt->error_capture)) { + u64 start = ggtt->error_capture.start; + u64 size = ggtt->error_capture.size; + + ggtt->vm.scratch_range(&ggtt->vm, start, size); drm_dbg(&ggtt->vm.i915->drm, "Reserved GGTT:[%llx, %llx] for use by error capture\n", - ggtt->error_capture.start, - ggtt->error_capture.start + ggtt->error_capture.size); + start, start + size); + } /* * The upper portion of the GuC address space has a sizeable hole @@ -1280,6 +1288,10 @@ void i915_ggtt_resume(struct i915_ggtt *ggtt) flush = i915_ggtt_resume_vm(&ggtt->vm); + if (drm_mm_node_allocated(&ggtt->error_capture)) + ggtt->vm.scratch_range(&ggtt->vm, ggtt->error_capture.start, + ggtt->error_capture.size); + ggtt->invalidate(ggtt); if (flush)