From patchwork Fri Mar 10 04:07:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 67204 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp678348wrd; Thu, 9 Mar 2023 20:21:16 -0800 (PST) X-Google-Smtp-Source: AK7set+vPVmynYBqCzu66nfa6R3Hbes9S9gr61YPW8IBwmbiA28djPSY3xWaMoNYpjYp/hUns23y X-Received: by 2002:aa7:9f1a:0:b0:5a8:ae60:eb4a with SMTP id g26-20020aa79f1a000000b005a8ae60eb4amr18535622pfr.28.1678422076494; Thu, 09 Mar 2023 20:21:16 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1678422076; cv=none; d=google.com; s=arc-20160816; b=P3BHRo9OPFzlUQ6evgg2naKsJgjKyToiEXBhBru7DwGnyQljjS69Ot/Vt9oAhYqqNz LCSL2K002yekiBPhc7PUrcTEVnxB+BbXnyG+0MijGqauDNGoHXeMG8FIGJVJQFoHiah8 DZsrNdMwUUol3vcM23vjvC9LAOnR9IlFGmDAveIAc3KxEj5pcUYr4Q9+0JRWbWjQ/ck0 pBaQAE0z8Z9I/OkE5whfcChOsFkBSqZgkSo8mqi5dIWJRB6icWPtt7cHfsfWWkp5soWr Mu+XtZAvfyDUR6IbOeLjyY+5yrZFJDe4sLrgna52JFpdwiJbiK+6aizRtCIrnqDu6AoU 9Sig== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=LgcUg9KBFxgyL7R+Ko0NRVJoBGhkBXsnNvmn89JO8A8=; b=ZzVk4uStWT0p+AQsBAvR0yBxiS3V/BFPl6cMhjSACTMe1h5akVbSLpGQ3K3JjuznNu xAA9u3OdEZ46N3zpxTZuTEw2nNXqIm38QuQZ2LYOGeQ8qhp+LhMgmfsdjFCb55p/YZu+ +4WpmHpJ0Arm7YLTMwbwyZ1TFCSPhTHpmasEmcRms2b2VeukT0ta15RMsrkHB5rYsCX2 xC5VzsMqh9OQ4jGJwttoTc+RY1PdEH/CN20+QEc7eAi8pzXA33CUmpVELPutJTz0hf3q L+kkA6J277wyykm5t0CpbUXBWLsv79g+Zhln312MXSesYRgNsWem1Umb+Xvn7+5jxG3t AM9g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=c3qGIoLr; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id x12-20020aa78f0c000000b005a8a4675cecsi975776pfr.6.2023.03.09.20.21.04; Thu, 09 Mar 2023 20:21:16 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=c3qGIoLr; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230221AbjCJEIt (ORCPT + 99 others); Thu, 9 Mar 2023 23:08:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57468 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230162AbjCJEIl (ORCPT ); Thu, 9 Mar 2023 23:08:41 -0500 Received: from mail-pf1-x434.google.com (mail-pf1-x434.google.com [IPv6:2607:f8b0:4864:20::434]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4E2DF2128E for ; Thu, 9 Mar 2023 20:08:36 -0800 (PST) Received: by mail-pf1-x434.google.com with SMTP id b20so2866867pfo.6 for ; Thu, 09 Mar 2023 20:08:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678421316; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LgcUg9KBFxgyL7R+Ko0NRVJoBGhkBXsnNvmn89JO8A8=; b=c3qGIoLrGp1PdUOM+WA3hZ8dx6qyhOgNnZQ72Tc6ea161qzbjzXiN9QhbjdjhuYJCx MFfFiP+7JYyLJZczXFRpzMvKWgdtb8izRkg2AxKOK06w6XUntcwwSuYIs8ZHSKn43LNp CRp6kCXQf/4LLWAkZsRNROgyHHkipfUSDMN1LkS4Q6WAuBccC3Wwd7+k5aVk3LHETYgZ uogLSKPWxZjjegDwdO3X2FWabIe96r+aerQc0jmZgx3FjeWUk3jHuOI/ujkEKBV0tiV5 FSfUc3TgZPyu6oc0LyVdYbBYJlY2cguWMc45qsdasxopUBKwlFB+XvCRkmuKMXOd2KUD r1Bw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678421316; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LgcUg9KBFxgyL7R+Ko0NRVJoBGhkBXsnNvmn89JO8A8=; b=PfFTTFCG+HEUCBFN6SJBAhgY14T/U31yDtMRdawgxLWb+zs6Uw/szdRRFKhG8/lKCH S8VEgFIBZ0XBG4B+burdF/RIgLK9yw8kIBHLxz9PMrlCqF44vmUiu80CWfhM04V2OBYs WkSM2Blc3yO2FU9Yrl4ddZQJTrW5qE09lnLGPBJDe6+9xC1tvx1EdyT4LwAhWalOVWyr Ujkw26w4G0VrTRMZYFQe84rZiC0Qh62GfmShHvcl8jiF0XZTaCLX/Z924IUs38nesLie YfH4mC5no4eN6+3MX6YpVdIDTVIEUwzHs9q1F7w4CuIvCU+J4CL9CIFcmfLuEIN8ZsII sLvg== X-Gm-Message-State: AO0yUKXvrucmfF+Jq9zymcpBelfXI8S6l0izi/nGrFQcvFCvlkyspRMd 2zxgYkTqlQN8x9/ZB/WLXjrp X-Received: by 2002:a62:5258:0:b0:5a9:bd0c:4704 with SMTP id g85-20020a625258000000b005a9bd0c4704mr22251248pfb.14.1678421315671; Thu, 09 Mar 2023 20:08:35 -0800 (PST) Received: from localhost.localdomain ([27.111.75.67]) by smtp.gmail.com with ESMTPSA id y26-20020aa7855a000000b0058d92d6e4ddsm361846pfn.5.2023.03.09.20.08.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Mar 2023 20:08:34 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, quic_srichara@quicinc.com, Manivannan Sadhasivam Subject: [PATCH v3 01/19] PCI: qcom: Remove PCIE20_ prefix from register definitions Date: Fri, 10 Mar 2023 09:37:58 +0530 Message-Id: <20230310040816.22094-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230310040816.22094-1-manivannan.sadhasivam@linaro.org> References: <20230310040816.22094-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759953107387504544?= X-GMAIL-MSGID: =?utf-8?q?1759953107387504544?= The PCIE part is redundant and 20 doesn't represent anything across the SoCs supported now. So let's get rid of the prefix. This involves adding the IP version suffix to one definition of PARF_SLV_ADDR_SPACE_SIZE that defines offset specific to that version. The other definition is generic for the rest of the versions. Also, the register PCIE20_LNK_CONTROL2_LINK_STATUS2 is not used anywhere, hence removed. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 184 ++++++++++++------------- 1 file changed, 91 insertions(+), 93 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index a232b04af048..6930bc9ceeb5 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -33,7 +33,7 @@ #include "../../pci.h" #include "pcie-designware.h" -#define PCIE20_PARF_SYS_CTRL 0x00 +#define PARF_SYS_CTRL 0x00 #define MST_WAKEUP_EN BIT(13) #define SLV_WAKEUP_EN BIT(12) #define MSTR_ACLK_CGC_DIS BIT(10) @@ -43,39 +43,39 @@ #define L23_CLK_RMV_DIS BIT(2) #define L1_CLK_RMV_DIS BIT(1) -#define PCIE20_PARF_PM_CTRL 0x20 +#define PARF_PM_CTRL 0x20 #define REQ_NOT_ENTR_L1 BIT(5) -#define PCIE20_PARF_PHY_CTRL 0x40 +#define PARF_PHY_CTRL 0x40 #define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK GENMASK(20, 16) #define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) ((x) << 16) -#define PCIE20_PARF_PHY_REFCLK 0x4C +#define PARF_PHY_REFCLK 0x4C #define PHY_REFCLK_SSP_EN BIT(16) #define PHY_REFCLK_USE_PAD BIT(12) -#define PCIE20_PARF_DBI_BASE_ADDR 0x168 -#define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16C -#define PCIE20_PARF_MHI_CLOCK_RESET_CTRL 0x174 +#define PARF_DBI_BASE_ADDR 0x168 +#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3 0x16C /* Register offset specific to IP rev 2.3.3 */ +#define PARF_MHI_CLOCK_RESET_CTRL 0x174 #define AHB_CLK_EN BIT(0) #define MSTR_AXI_CLK_EN BIT(1) #define BYPASS BIT(4) -#define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT 0x178 -#define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1A8 -#define PCIE20_PARF_LTSSM 0x1B0 -#define PCIE20_PARF_SID_OFFSET 0x234 -#define PCIE20_PARF_BDF_TRANSLATE_CFG 0x24C -#define PCIE20_PARF_DEVICE_TYPE 0x1000 -#define PCIE20_PARF_BDF_TO_SID_TABLE_N 0x2000 +#define PARF_AXI_MSTR_WR_ADDR_HALT 0x178 +#define PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1A8 +#define PARF_LTSSM 0x1B0 +#define PARF_SID_OFFSET 0x234 +#define PARF_BDF_TRANSLATE_CFG 0x24C +#define PARF_DEVICE_TYPE 0x1000 +#define PARF_BDF_TO_SID_TABLE_N 0x2000 -#define PCIE20_ELBI_SYS_CTRL 0x04 -#define PCIE20_ELBI_SYS_CTRL_LT_ENABLE BIT(0) +#define ELBI_SYS_CTRL 0x04 +#define ELBI_SYS_CTRL_LT_ENABLE BIT(0) -#define PCIE20_AXI_MSTR_RESP_COMP_CTRL0 0x818 +#define AXI_MSTR_RESP_COMP_CTRL0 0x818 #define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K 0x4 #define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_4K 0x5 -#define PCIE20_AXI_MSTR_RESP_COMP_CTRL1 0x81c +#define AXI_MSTR_RESP_COMP_CTRL1 0x81c #define CFG_BRIDGE_SB_INIT BIT(0) #define PCIE_CAP_SLOT_POWER_LIMIT_VAL FIELD_PREP(PCI_EXP_SLTCAP_SPLV, \ @@ -93,30 +93,28 @@ PCIE_CAP_SLOT_POWER_LIMIT_VAL | \ PCIE_CAP_SLOT_POWER_LIMIT_SCALE) -#define PCIE20_PARF_Q2A_FLUSH 0x1AC +#define PARF_Q2A_FLUSH 0x1AC -#define PCIE20_MISC_CONTROL_1_REG 0x8BC +#define MISC_CONTROL_1_REG 0x8BC #define DBI_RO_WR_EN 1 #define PERST_DELAY_US 1000 /* PARF registers */ -#define PCIE20_PARF_PCS_DEEMPH 0x34 +#define PARF_PCS_DEEMPH 0x34 #define PCS_DEEMPH_TX_DEEMPH_GEN1(x) ((x) << 16) #define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) ((x) << 8) #define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) ((x) << 0) -#define PCIE20_PARF_PCS_SWING 0x38 +#define PARF_PCS_SWING 0x38 #define PCS_SWING_TX_SWING_FULL(x) ((x) << 8) #define PCS_SWING_TX_SWING_LOW(x) ((x) << 0) -#define PCIE20_PARF_CONFIG_BITS 0x50 +#define PARF_CONFIG_BITS 0x50 #define PHY_RX0_EQ(x) ((x) << 24) -#define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358 +#define PARF_SLV_ADDR_SPACE_SIZE 0x358 #define SLV_ADDR_SPACE_SZ 0x10000000 -#define PCIE20_LNK_CONTROL2_LINK_STATUS2 0xa0 - #define DEVICE_TYPE_RC 0x4 #define QCOM_PCIE_2_1_0_MAX_SUPPLY 3 @@ -261,9 +259,9 @@ static void qcom_pcie_2_1_0_ltssm_enable(struct qcom_pcie *pcie) u32 val; /* enable link training */ - val = readl(pcie->elbi + PCIE20_ELBI_SYS_CTRL); - val |= PCIE20_ELBI_SYS_CTRL_LT_ENABLE; - writel(val, pcie->elbi + PCIE20_ELBI_SYS_CTRL); + val = readl(pcie->elbi + ELBI_SYS_CTRL); + val |= ELBI_SYS_CTRL_LT_ENABLE; + writel(val, pcie->elbi + ELBI_SYS_CTRL); } static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie) @@ -333,7 +331,7 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie) reset_control_assert(res->ext_reset); reset_control_assert(res->phy_reset); - writel(1, pcie->parf + PCIE20_PARF_PHY_CTRL); + writel(1, pcie->parf + PARF_PHY_CTRL); regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); } @@ -423,9 +421,9 @@ static int qcom_pcie_post_init_2_1_0(struct qcom_pcie *pcie) int ret; /* enable PCIe clocks and resets */ - val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL); + val = readl(pcie->parf + PARF_PHY_CTRL); val &= ~BIT(0); - writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); + writel(val, pcie->parf + PARF_PHY_CTRL); ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); if (ret) @@ -436,37 +434,37 @@ static int qcom_pcie_post_init_2_1_0(struct qcom_pcie *pcie) writel(PCS_DEEMPH_TX_DEEMPH_GEN1(24) | PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(24) | PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(34), - pcie->parf + PCIE20_PARF_PCS_DEEMPH); + pcie->parf + PARF_PCS_DEEMPH); writel(PCS_SWING_TX_SWING_FULL(120) | PCS_SWING_TX_SWING_LOW(120), - pcie->parf + PCIE20_PARF_PCS_SWING); - writel(PHY_RX0_EQ(4), pcie->parf + PCIE20_PARF_CONFIG_BITS); + pcie->parf + PARF_PCS_SWING); + writel(PHY_RX0_EQ(4), pcie->parf + PARF_CONFIG_BITS); } if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) { /* set TX termination offset */ - val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL); + val = readl(pcie->parf + PARF_PHY_CTRL); val &= ~PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK; val |= PHY_CTRL_PHY_TX0_TERM_OFFSET(7); - writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); + writel(val, pcie->parf + PARF_PHY_CTRL); } /* enable external reference clock */ - val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK); + val = readl(pcie->parf + PARF_PHY_REFCLK); /* USE_PAD is required only for ipq806x */ if (!of_device_is_compatible(node, "qcom,pcie-apq8064")) val &= ~PHY_REFCLK_USE_PAD; val |= PHY_REFCLK_SSP_EN; - writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK); + writel(val, pcie->parf + PARF_PHY_REFCLK); /* wait for clock acquisition */ usleep_range(1000, 1500); /* Set the Max TLP size to 2K, instead of using default of 4K */ writel(CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K, - pci->dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL0); + pci->dbi_base + AXI_MSTR_RESP_COMP_CTRL0); writel(CFG_BRIDGE_SB_INIT, - pci->dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL1); + pci->dbi_base + AXI_MSTR_RESP_COMP_CTRL1); return 0; } @@ -574,13 +572,13 @@ static int qcom_pcie_init_1_0_0(struct qcom_pcie *pcie) static int qcom_pcie_post_init_1_0_0(struct qcom_pcie *pcie) { /* change DBI base address */ - writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR); + writel(0, pcie->parf + PARF_DBI_BASE_ADDR); if (IS_ENABLED(CONFIG_PCI_MSI)) { - u32 val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT); + u32 val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT); val |= BIT(31); - writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT); + writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT); } return 0; @@ -591,9 +589,9 @@ static void qcom_pcie_2_3_2_ltssm_enable(struct qcom_pcie *pcie) u32 val; /* enable link training */ - val = readl(pcie->parf + PCIE20_PARF_LTSSM); + val = readl(pcie->parf + PARF_LTSSM); val |= BIT(8); - writel(val, pcie->parf + PCIE20_PARF_LTSSM); + writel(val, pcie->parf + PARF_LTSSM); } static int qcom_pcie_get_resources_2_3_2(struct qcom_pcie *pcie) @@ -698,25 +696,25 @@ static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie) u32 val; /* enable PCIe clocks and resets */ - val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL); + val = readl(pcie->parf + PARF_PHY_CTRL); val &= ~BIT(0); - writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); + writel(val, pcie->parf + PARF_PHY_CTRL); /* change DBI base address */ - writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR); + writel(0, pcie->parf + PARF_DBI_BASE_ADDR); /* MAC PHY_POWERDOWN MUX DISABLE */ - val = readl(pcie->parf + PCIE20_PARF_SYS_CTRL); + val = readl(pcie->parf + PARF_SYS_CTRL); val &= ~BIT(29); - writel(val, pcie->parf + PCIE20_PARF_SYS_CTRL); + writel(val, pcie->parf + PARF_SYS_CTRL); - val = readl(pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL); + val = readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); val |= BIT(4); - writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL); + writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); - val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2); + val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); val |= BIT(31); - writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2); + writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); return 0; } @@ -977,25 +975,25 @@ static int qcom_pcie_post_init_2_4_0(struct qcom_pcie *pcie) u32 val; /* enable PCIe clocks and resets */ - val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL); + val = readl(pcie->parf + PARF_PHY_CTRL); val &= ~BIT(0); - writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); + writel(val, pcie->parf + PARF_PHY_CTRL); /* change DBI base address */ - writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR); + writel(0, pcie->parf + PARF_DBI_BASE_ADDR); /* MAC PHY_POWERDOWN MUX DISABLE */ - val = readl(pcie->parf + PCIE20_PARF_SYS_CTRL); + val = readl(pcie->parf + PARF_SYS_CTRL); val &= ~BIT(29); - writel(val, pcie->parf + PCIE20_PARF_SYS_CTRL); + writel(val, pcie->parf + PARF_SYS_CTRL); - val = readl(pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL); + val = readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); val |= BIT(4); - writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL); + writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); - val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2); + val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); val |= BIT(31); - writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2); + writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); return 0; } @@ -1140,22 +1138,22 @@ static int qcom_pcie_post_init_2_3_3(struct qcom_pcie *pcie) u32 val; writel(SLV_ADDR_SPACE_SZ, - pcie->parf + PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE); + pcie->parf + PARF_SLV_ADDR_SPACE_SIZE_2_3_3); - val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL); + val = readl(pcie->parf + PARF_PHY_CTRL); val &= ~BIT(0); - writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); + writel(val, pcie->parf + PARF_PHY_CTRL); - writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR); + writel(0, pcie->parf + PARF_DBI_BASE_ADDR); writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS | SLV_ACLK_CGC_DIS | CORE_CLK_CGC_DIS | AUX_PWR_DET | L23_CLK_RMV_DIS | L1_CLK_RMV_DIS, - pcie->parf + PCIE20_PARF_SYS_CTRL); - writel(0, pcie->parf + PCIE20_PARF_Q2A_FLUSH); + pcie->parf + PARF_SYS_CTRL); + writel(0, pcie->parf + PARF_Q2A_FLUSH); writel(PCI_COMMAND_MASTER, pci->dbi_base + PCI_COMMAND); - writel(DBI_RO_WR_EN, pci->dbi_base + PCIE20_MISC_CONTROL_1_REG); + writel(DBI_RO_WR_EN, pci->dbi_base + MISC_CONTROL_1_REG); writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP); val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP); @@ -1255,34 +1253,34 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) usleep_range(1000, 1500); /* configure PCIe to RC mode */ - writel(DEVICE_TYPE_RC, pcie->parf + PCIE20_PARF_DEVICE_TYPE); + writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE); /* enable PCIe clocks and resets */ - val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL); + val = readl(pcie->parf + PARF_PHY_CTRL); val &= ~BIT(0); - writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); + writel(val, pcie->parf + PARF_PHY_CTRL); /* change DBI base address */ - writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR); + writel(0, pcie->parf + PARF_DBI_BASE_ADDR); /* MAC PHY_POWERDOWN MUX DISABLE */ - val = readl(pcie->parf + PCIE20_PARF_SYS_CTRL); + val = readl(pcie->parf + PARF_SYS_CTRL); val &= ~BIT(29); - writel(val, pcie->parf + PCIE20_PARF_SYS_CTRL); + writel(val, pcie->parf + PARF_SYS_CTRL); - val = readl(pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL); + val = readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); val |= BIT(4); - writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL); + writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); /* Enable L1 and L1SS */ - val = readl(pcie->parf + PCIE20_PARF_PM_CTRL); + val = readl(pcie->parf + PARF_PM_CTRL); val &= ~REQ_NOT_ENTR_L1; - writel(val, pcie->parf + PCIE20_PARF_PM_CTRL); + writel(val, pcie->parf + PARF_PM_CTRL); if (IS_ENABLED(CONFIG_PCI_MSI)) { - val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT); + val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT); val |= BIT(31); - writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT); + writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT); } return 0; @@ -1371,17 +1369,17 @@ static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie) int i; writel(SLV_ADDR_SPACE_SZ, - pcie->parf + PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE); + pcie->parf + PARF_SLV_ADDR_SPACE_SIZE); - val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL); + val = readl(pcie->parf + PARF_PHY_CTRL); val &= ~BIT(0); - writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); + writel(val, pcie->parf + PARF_PHY_CTRL); - writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR); + writel(0, pcie->parf + PARF_DBI_BASE_ADDR); - writel(DEVICE_TYPE_RC, pcie->parf + PCIE20_PARF_DEVICE_TYPE); + writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE); writel(BYPASS | MSTR_AXI_CLK_EN | AHB_CLK_EN, - pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL); + pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); writel(GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS | GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL, pci->dbi_base + GEN3_RELATED_OFF); @@ -1389,9 +1387,9 @@ static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie) writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS | SLV_ACLK_CGC_DIS | CORE_CLK_CGC_DIS | AUX_PWR_DET | L23_CLK_RMV_DIS | L1_CLK_RMV_DIS, - pcie->parf + PCIE20_PARF_SYS_CTRL); + pcie->parf + PARF_SYS_CTRL); - writel(0, pcie->parf + PCIE20_PARF_Q2A_FLUSH); + writel(0, pcie->parf + PARF_Q2A_FLUSH); dw_pcie_dbi_ro_wr_en(pci); writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP); @@ -1404,7 +1402,7 @@ static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie) PCI_EXP_DEVCTL2); for (i = 0; i < 256; i++) - writel(0, pcie->parf + PCIE20_PARF_BDF_TO_SID_TABLE_N + (4 * i)); + writel(0, pcie->parf + PARF_BDF_TO_SID_TABLE_N + (4 * i)); return 0; } @@ -1426,7 +1424,7 @@ static int qcom_pcie_config_sid_sm8250(struct qcom_pcie *pcie) u32 smmu_sid; u32 smmu_sid_len; } *map; - void __iomem *bdf_to_sid_base = pcie->parf + PCIE20_PARF_BDF_TO_SID_TABLE_N; + void __iomem *bdf_to_sid_base = pcie->parf + PARF_BDF_TO_SID_TABLE_N; struct device *dev = pcie->pci->dev; u8 qcom_pcie_crc8_table[CRC8_TABLE_SIZE]; int i, nr_map, size = 0; From patchwork Fri Mar 10 04:07:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 67208 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp678800wrd; Thu, 9 Mar 2023 20:22:46 -0800 (PST) X-Google-Smtp-Source: AK7set9YzmgDyjGpmOWdLdEjMIoEgydgxj6vyWGFkKLgzVNerpiICHc0kt8VxQs8Atyxa9iM/v/r X-Received: by 2002:a17:902:e801:b0:19e:839e:49d8 with SMTP id u1-20020a170902e80100b0019e839e49d8mr28359268plg.59.1678422166217; Thu, 09 Mar 2023 20:22:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1678422166; cv=none; d=google.com; s=arc-20160816; b=QaJwy4hibZBqcxA5atPwvUJsNIECAbczi1qQr3sqD+so51PbgPxiRz6eAlv+7hrgMp +T4lvuUOBRmEBzMPqDn6XykPgdDCscItPtQUkFUBhtoWcFBtU7YWqpPfOxMybCF8LE/C Olj+flyE4jGDAboBkCsEjr2/xlLWraYb3GsZutCQnxy5UwzBM33Un/XZS72G4aFAmCNz rFIHWpza7zNsOSWyr8l8TFLy6lO/jJqBhywAd0K4CM73O2RNKlyvKP23aeKF7Q0joVXz 0lJe8WKXWCcQ5vuN+110TK1YIndzT9Fq5KWRgc0+gHdsxvVbsoQaYPdJ5CbN9dGRN4Ad WS0A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=dmhzqQp9Bpxccy6mDdW3lTo4tjr71oQJII7ujI7fl58=; b=aClLJ9AkZHv8bOStjfsyxbx4Qq7458TbvrCHdwnKEaxp6lYi/hiFIt3vkEyNV1fXxE blOOO1eX1sWDNwGFcvQi/+yCVETiUzLTsvlIqzdaKOpTgC+FlZOBlYLAqFIEsRFuB4rY 8i1O47Q+FY8AAlpmAC4zrUkb5U+AELhn/FAdB1yYvBLJdRqh8+bJsH9oZSouBpS28Y3T hvGiZUtpSJx8SchJDiAU2ZUMSHGkN+z8HljVYiEwL6Mb/iYSY/IHFVI/ZDHbRlOMM4B6 aDGf1R/yCnqIWzEyBXCw1AsI2r1xZ8MKuRw9vzAPaGydf4zL5cddQk7mWwkAcl8G+xJm h3hw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=YevkCAV8; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id f1-20020a170902684100b0019d13e26ecasi1047138pln.355.2023.03.09.20.22.29; Thu, 09 Mar 2023 20:22:46 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=YevkCAV8; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230268AbjCJEIz (ORCPT + 99 others); Thu, 9 Mar 2023 23:08:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57654 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230192AbjCJEIm (ORCPT ); Thu, 9 Mar 2023 23:08:42 -0500 Received: from mail-pf1-x436.google.com (mail-pf1-x436.google.com [IPv6:2607:f8b0:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 088DAAB880 for ; Thu, 9 Mar 2023 20:08:40 -0800 (PST) Received: by mail-pf1-x436.google.com with SMTP id c10so2839032pfv.13 for ; Thu, 09 Mar 2023 20:08:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678421319; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dmhzqQp9Bpxccy6mDdW3lTo4tjr71oQJII7ujI7fl58=; b=YevkCAV8hfmQG3I7ja4XIthGMJPD71opmAev2roI1tNTKTXdcsBoXojX9UfPBQqoPg OwVHs9JWpJQzl61Kv3fnh1Q/CuBO5dDUsYMkiQ2nc3VNercXNpxBJ3yf5dqCa9bLdTZO HOAEWhiu0hlOdHFY/QEaj9w6KolJritE9m6zP0C6If/gDUYhxJgj0UXdn6lS2tH1qu3m dYgYXAYGpEufDdvYs/Z6l7/Opy8hGfgSGu2SLSaB8aNZdG52cRXvAM0Mp4e9pvYf5hTQ lD+lYOpJeew9zpnN9GmT8DeZgX+YkEQFc36tP/rRf4cudxf5Wcckqr7Sr3hLlOLiki5v Oquw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678421319; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dmhzqQp9Bpxccy6mDdW3lTo4tjr71oQJII7ujI7fl58=; b=lSJMKvRSPO/ZeEqQlF4KbKX7BAp34vIttrmr9fl7GzC9T6pKa2oowvJgIbWtFcfZp1 Zy4UN7WPeDgvMl4W8ZIOBnlnYbKrsT1yrmLBugTUNNR4msB1BaWiNiegL7+6rw6B1dTQ L4nTuQ7lPrN7e33mw3cLUAAPDdAYjHFRLc8AIv/i8CGh7I6yZZHo3UY3gjRO2o8HX2dM 2BupZxuhjeh7ceuVfk7REzoW4x+I8e4VYEy+jZLwBDzwKsAQypDD66TJYd+Vk3tYdJUd 0iOozG8cbYUJ29H3Wy/Bfw+3YA8vsix+1+WJ4nz0++iV6Ul1RvaOJXudm5iCxrWbc9oU q4pA== X-Gm-Message-State: AO0yUKU1vYBUvg2eRtfHhDl7G+CaWzdjRqMM9g6HGzEzmdMXKwt7YsPb GNNsOiaP1XI6XvliOuuLh3GRu3/1aak5DYPptg== X-Received: by 2002:aa7:9ac7:0:b0:5a9:c682:831d with SMTP id x7-20020aa79ac7000000b005a9c682831dmr20990047pfp.13.1678421319484; Thu, 09 Mar 2023 20:08:39 -0800 (PST) Received: from localhost.localdomain ([27.111.75.67]) by smtp.gmail.com with ESMTPSA id y26-20020aa7855a000000b0058d92d6e4ddsm361846pfn.5.2023.03.09.20.08.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Mar 2023 20:08:39 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, quic_srichara@quicinc.com, Manivannan Sadhasivam Subject: [PATCH v3 02/19] PCI: qcom: Sort and group registers and bitfield definitions Date: Fri, 10 Mar 2023 09:37:59 +0530 Message-Id: <20230310040816.22094-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230310040816.22094-1-manivannan.sadhasivam@linaro.org> References: <20230310040816.22094-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,UPPERCASE_50_75,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759953201193218540?= X-GMAIL-MSGID: =?utf-8?q?1759953201193218540?= Sorting the registers and their bit definitions will make it easier to add more definitions in the future and it also helps in maintenance. While at it, let's also group the registers and bit definitions separately as done in the pcie-qcom-ep driver. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 108 ++++++++++++++----------- 1 file changed, 63 insertions(+), 45 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 6930bc9ceeb5..9223ca76640d 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -33,7 +33,36 @@ #include "../../pci.h" #include "pcie-designware.h" +/* PARF registers */ #define PARF_SYS_CTRL 0x00 +#define PARF_PM_CTRL 0x20 +#define PARF_PCS_DEEMPH 0x34 +#define PARF_PCS_SWING 0x38 +#define PARF_PHY_CTRL 0x40 +#define PARF_PHY_REFCLK 0x4C +#define PARF_CONFIG_BITS 0x50 +#define PARF_DBI_BASE_ADDR 0x168 +#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3 0x16C /* Register offset specific to IP ver 2.3.3 */ +#define PARF_MHI_CLOCK_RESET_CTRL 0x174 +#define PARF_AXI_MSTR_WR_ADDR_HALT 0x178 +#define PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1A8 +#define PARF_Q2A_FLUSH 0x1AC +#define PARF_LTSSM 0x1B0 +#define PARF_SID_OFFSET 0x234 +#define PARF_BDF_TRANSLATE_CFG 0x24C +#define PARF_SLV_ADDR_SPACE_SIZE 0x358 +#define PARF_DEVICE_TYPE 0x1000 +#define PARF_BDF_TO_SID_TABLE_N 0x2000 + +/* ELBI registers */ +#define ELBI_SYS_CTRL 0x04 + +/* DBI registers */ +#define AXI_MSTR_RESP_COMP_CTRL0 0x818 +#define AXI_MSTR_RESP_COMP_CTRL1 0x81c +#define MISC_CONTROL_1_REG 0x8BC + +/* PARF_SYS_CTRL register fields */ #define MST_WAKEUP_EN BIT(13) #define SLV_WAKEUP_EN BIT(12) #define MSTR_ACLK_CGC_DIS BIT(10) @@ -43,45 +72,56 @@ #define L23_CLK_RMV_DIS BIT(2) #define L1_CLK_RMV_DIS BIT(1) -#define PARF_PM_CTRL 0x20 +/* PARF_PM_CTRL register fields */ #define REQ_NOT_ENTR_L1 BIT(5) -#define PARF_PHY_CTRL 0x40 +/* PARF_PCS_DEEMPH register fields */ +#define PCS_DEEMPH_TX_DEEMPH_GEN1(x) ((x) << 16) +#define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) ((x) << 8) +#define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) ((x) << 0) + +/* PARF_PCS_SWING register fields */ +#define PCS_SWING_TX_SWING_FULL(x) ((x) << 8) +#define PCS_SWING_TX_SWING_LOW(x) ((x) << 0) + +/* PARF_PHY_CTRL register fields */ #define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK GENMASK(20, 16) #define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) ((x) << 16) -#define PARF_PHY_REFCLK 0x4C +/* PARF_PHY_REFCLK register fields */ #define PHY_REFCLK_SSP_EN BIT(16) #define PHY_REFCLK_USE_PAD BIT(12) -#define PARF_DBI_BASE_ADDR 0x168 -#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3 0x16C /* Register offset specific to IP rev 2.3.3 */ -#define PARF_MHI_CLOCK_RESET_CTRL 0x174 +/* PARF_CONFIG_BITS register fields */ +#define PHY_RX0_EQ(x) ((x) << 24) + +/* PARF_SLV_ADDR_SPACE_SIZE register value */ +#define SLV_ADDR_SPACE_SZ 0x10000000 + +/* PARF_MHI_CLOCK_RESET_CTRL register fields */ #define AHB_CLK_EN BIT(0) #define MSTR_AXI_CLK_EN BIT(1) #define BYPASS BIT(4) -#define PARF_AXI_MSTR_WR_ADDR_HALT 0x178 -#define PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1A8 -#define PARF_LTSSM 0x1B0 -#define PARF_SID_OFFSET 0x234 -#define PARF_BDF_TRANSLATE_CFG 0x24C -#define PARF_DEVICE_TYPE 0x1000 -#define PARF_BDF_TO_SID_TABLE_N 0x2000 +/* PARF_DEVICE_TYPE register fields */ +#define DEVICE_TYPE_RC 0x4 -#define ELBI_SYS_CTRL 0x04 +/* ELBI_SYS_CTRL register fields */ #define ELBI_SYS_CTRL_LT_ENABLE BIT(0) -#define AXI_MSTR_RESP_COMP_CTRL0 0x818 +/* AXI_MSTR_RESP_COMP_CTRL0 register fields */ #define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K 0x4 #define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_4K 0x5 -#define AXI_MSTR_RESP_COMP_CTRL1 0x81c + +/* AXI_MSTR_RESP_COMP_CTRL1 register fields */ #define CFG_BRIDGE_SB_INIT BIT(0) -#define PCIE_CAP_SLOT_POWER_LIMIT_VAL FIELD_PREP(PCI_EXP_SLTCAP_SPLV, \ - 250) -#define PCIE_CAP_SLOT_POWER_LIMIT_SCALE FIELD_PREP(PCI_EXP_SLTCAP_SPLS, \ - 1) +/* MISC_CONTROL_1_REG register fields */ +#define DBI_RO_WR_EN 1 + +/* PCI_EXP_SLTCAP register fields */ +#define PCIE_CAP_SLOT_POWER_LIMIT_VAL FIELD_PREP(PCI_EXP_SLTCAP_SPLV, 250) +#define PCIE_CAP_SLOT_POWER_LIMIT_SCALE FIELD_PREP(PCI_EXP_SLTCAP_SPLS, 1) #define PCIE_CAP_SLOT_VAL (PCI_EXP_SLTCAP_ABP | \ PCI_EXP_SLTCAP_PCP | \ PCI_EXP_SLTCAP_MRLSP | \ @@ -93,34 +133,12 @@ PCIE_CAP_SLOT_POWER_LIMIT_VAL | \ PCIE_CAP_SLOT_POWER_LIMIT_SCALE) -#define PARF_Q2A_FLUSH 0x1AC - -#define MISC_CONTROL_1_REG 0x8BC -#define DBI_RO_WR_EN 1 - #define PERST_DELAY_US 1000 -/* PARF registers */ -#define PARF_PCS_DEEMPH 0x34 -#define PCS_DEEMPH_TX_DEEMPH_GEN1(x) ((x) << 16) -#define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) ((x) << 8) -#define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) ((x) << 0) - -#define PARF_PCS_SWING 0x38 -#define PCS_SWING_TX_SWING_FULL(x) ((x) << 8) -#define PCS_SWING_TX_SWING_LOW(x) ((x) << 0) - -#define PARF_CONFIG_BITS 0x50 -#define PHY_RX0_EQ(x) ((x) << 24) - -#define PARF_SLV_ADDR_SPACE_SIZE 0x358 -#define SLV_ADDR_SPACE_SZ 0x10000000 - -#define DEVICE_TYPE_RC 0x4 -#define QCOM_PCIE_2_1_0_MAX_SUPPLY 3 -#define QCOM_PCIE_2_1_0_MAX_CLOCKS 5 +#define QCOM_PCIE_2_1_0_MAX_SUPPLY 3 +#define QCOM_PCIE_2_1_0_MAX_CLOCKS 5 -#define QCOM_PCIE_CRC8_POLYNOMIAL (BIT(2) | BIT(1) | BIT(0)) +#define QCOM_PCIE_CRC8_POLYNOMIAL (BIT(2) | BIT(1) | BIT(0)) struct qcom_pcie_resources_2_1_0 { struct clk_bulk_data clks[QCOM_PCIE_2_1_0_MAX_CLOCKS]; From patchwork Fri Mar 10 04:08:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 67209 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp678937wrd; Thu, 9 Mar 2023 20:23:12 -0800 (PST) X-Google-Smtp-Source: AK7set844xf1QW0CQrfrqQJJjzyoVLSczjo5hebdZrBLUicpTAQWq0tEm7TIiLepAL+4XpwdJfjp X-Received: by 2002:a17:903:2441:b0:199:190c:3c0a with SMTP id l1-20020a170903244100b00199190c3c0amr29488305pls.31.1678422192479; Thu, 09 Mar 2023 20:23:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1678422192; cv=none; d=google.com; s=arc-20160816; b=nQyRVh1Trg2OeHBOSlSCbTZKHI1qwhR/yjbNl1/MXi84ANZ/cxNIflnZjHp/YPKDiq T0OMsH3jVb5xPsqdwEqziUirZaI3e7JITEUAJ4wAAlaqEIf5pVdovC2zks7wGq648Khg B0p3thK/hcfcYB3H41RTOpkKPCMWp+LOrYs8b0YmdRK3D6gOZIenOR28WNsm5naXlzuU tHaNICI4q0/o4eCtkkC418+iLC7LwLEfBiSMw1hmWabplnrifvPG/ZMVzWGyscve2Mme Z+AE3WPn0pQKvosAllDV5JxdZLnTz9iqxaTli3tWLXKkl+W1RV7bhlyt0hGYB6Zaa8Dl yevw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=3tT4IStfyTS7c0lPgVozml2BSLbP+qQslzAxoVdPoGM=; b=ZyzR1XKW4MNmaL/yld9DtIwaswUaryFwZLdZW4qjtHzs3KVVJdih+p8fGEsQEAWQiW dI+cJ0QoJvJfz117mR/iGDNLcCV2ecdiphV+Qn2doX6XRoinHYKj0jCFkgJU6m8Io3Ie DDl3t2FIfCoVAoGNOEQtowb+s0zNpgTPF0eEu6cJaN/CvqlPSZN3Mz6JU1FfRIIFcGSa iSKvy+lCU+llEqRnzYEcYHEdzMj8GCAtOmECrb1hqvpzap33TKEIDnQfDef6fe3BkIq6 apZlIAV5n5MvJJ7TcZdM7MaUsGtIk8/3zajZv9DnklYcGSvXTQz+jEf9k2NeQDsz8Fin EZ4Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mS8ca4KU; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id kc13-20020a17090333cd00b00186892f9f29si1026365plb.488.2023.03.09.20.23.00; Thu, 09 Mar 2023 20:23:12 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mS8ca4KU; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230237AbjCJEJL (ORCPT + 99 others); Thu, 9 Mar 2023 23:09:11 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59462 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230232AbjCJEIt (ORCPT ); Thu, 9 Mar 2023 23:08:49 -0500 Received: from mail-pg1-x536.google.com (mail-pg1-x536.google.com [IPv6:2607:f8b0:4864:20::536]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 62F96D00A0 for ; Thu, 9 Mar 2023 20:08:45 -0800 (PST) Received: by mail-pg1-x536.google.com with SMTP id 132so2335249pgh.13 for ; Thu, 09 Mar 2023 20:08:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678421325; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3tT4IStfyTS7c0lPgVozml2BSLbP+qQslzAxoVdPoGM=; b=mS8ca4KUr2oW5X7maBG1wnkmGrlRXMieICGs7WL15nmhwKqZnxDPkGMkDesTYkNAuR NdNUdiAPN7atsb9WUfUd8sg4EeATQ2uYIj75TFUAqruU+ZP5xXsxa1tl8JilZtM3Rpo5 Eyc9kTf0n8rbfpbq/VsYLpfIFxYB7VvJkCGVIi0KOOJ600ccqhQ6uZ946z6JEVF8kUHl GOBN4m2okj0pU8tdCt3sYUdh46x8Z7DTvdXS5yYgPnDfKhKBDGFQAhTOugNeZJRBu+7W 9iRstoNFMVeq4zx4VNZcecRu4rVMC5CNkqt8zTXBwsxLgxS8WD6asbBUlVi1Dmq6a4jh GT6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678421325; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3tT4IStfyTS7c0lPgVozml2BSLbP+qQslzAxoVdPoGM=; b=kqYB28zpKBJqSGM9WMa46m3FbuhOVfP8JMeCSRvBKgzrT66qh2jFEBEnIWNBVqFM/V XbwupmfcMYvBm+JoeGNpRb5n+1qstAKkHX/WbueqULgm4AVAqhpqNL/DGgvTNekovrGI 6tUSX9sMzLj2IZhtu0DXLCVzofmyQYAnlX5+hi5RezMpBd88mabshD5gCi5SrbXfzisL 4PsMDCoPSxexBktNvfDVidLzTYLjq1Zw88kMtlEL8ldK3BTd8aEdx/NQ7liVRNOKvQku eAhzKyfZV+qu6GUnYq7KhW/IwCvGx7e/rdUaDSeycC/7Tl+UJqiQgrZW3B/1uyogU/xL aXZg== X-Gm-Message-State: AO0yUKWNT/V6CAUP/WWOYmwwJ5SWGTpXEMbpM6dQVleRJuIbcFaKibUm ZA/Cj6ZL/dovW/tBLZnHFCcV X-Received: by 2002:aa7:941d:0:b0:5f1:f57a:b0c3 with SMTP id x29-20020aa7941d000000b005f1f57ab0c3mr21881195pfo.5.1678421324837; Thu, 09 Mar 2023 20:08:44 -0800 (PST) Received: from localhost.localdomain ([27.111.75.67]) by smtp.gmail.com with ESMTPSA id y26-20020aa7855a000000b0058d92d6e4ddsm361846pfn.5.2023.03.09.20.08.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Mar 2023 20:08:43 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, quic_srichara@quicinc.com, Manivannan Sadhasivam Subject: [PATCH v3 03/19] PCI: qcom: Use bitfield definitions for register fields Date: Fri, 10 Mar 2023 09:38:00 +0530 Message-Id: <20230310040816.22094-4-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230310040816.22094-1-manivannan.sadhasivam@linaro.org> References: <20230310040816.22094-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759953228981806963?= X-GMAIL-MSGID: =?utf-8?q?1759953228981806963?= To maintain uniformity throughout the driver and also to make the code easier to read, let's make use of bitfield definitions for register fields. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 9223ca76640d..e9f4c70b719a 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -76,24 +76,24 @@ #define REQ_NOT_ENTR_L1 BIT(5) /* PARF_PCS_DEEMPH register fields */ -#define PCS_DEEMPH_TX_DEEMPH_GEN1(x) ((x) << 16) -#define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) ((x) << 8) -#define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) ((x) << 0) +#define PCS_DEEMPH_TX_DEEMPH_GEN1(x) FIELD_PREP(GENMASK(21, 16), x) +#define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) FIELD_PREP(GENMASK(13, 8), x) +#define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) FIELD_PREP(GENMASK(5, 0), x) /* PARF_PCS_SWING register fields */ -#define PCS_SWING_TX_SWING_FULL(x) ((x) << 8) -#define PCS_SWING_TX_SWING_LOW(x) ((x) << 0) +#define PCS_SWING_TX_SWING_FULL(x) FIELD_PREP(GENMASK(14, 8), x) +#define PCS_SWING_TX_SWING_LOW(x) FIELD_PREP(GENMASK(6, 0), x) /* PARF_PHY_CTRL register fields */ #define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK GENMASK(20, 16) -#define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) ((x) << 16) +#define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) FIELD_PREP(PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK, x) /* PARF_PHY_REFCLK register fields */ #define PHY_REFCLK_SSP_EN BIT(16) #define PHY_REFCLK_USE_PAD BIT(12) /* PARF_CONFIG_BITS register fields */ -#define PHY_RX0_EQ(x) ((x) << 24) +#define PHY_RX0_EQ(x) FIELD_PREP(GENMASK(26, 24), x) /* PARF_SLV_ADDR_SPACE_SIZE register value */ #define SLV_ADDR_SPACE_SZ 0x10000000 From patchwork Fri Mar 10 04:08:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 67213 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp679640wrd; Thu, 9 Mar 2023 20:25:47 -0800 (PST) X-Google-Smtp-Source: AK7set9FHGOterQWPXd7Vn0XR1b49YAqTKqamy6DJpzfujXmpx0mnpoh/wIlv33jKHGArBpGNUK/ X-Received: by 2002:a62:6145:0:b0:5a8:d3d9:e03a with SMTP id v66-20020a626145000000b005a8d3d9e03amr1126221pfb.0.1678422347149; Thu, 09 Mar 2023 20:25:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1678422347; cv=none; d=google.com; s=arc-20160816; b=ZZcQS3tyoO2UC7yMFjr2yEh0x0gB/SdZJU1amWlzTsY2R5suvflFHwoFKdi939bK7D 6ZraWWqOds1GFdxxbaENNVw23uaL8r2cXUaeABQrMMSVH8wPCFjM8VS0QmjkXN7VbHR0 44A5FC7jZKOPmJEVD2jeefC27c+4EVwW/2RYK5CDGlkZwtwIXi4bcrWZqSMWehDCuEFQ 8mJPxNg0eizyHkrWWrbOqjxtSpgsJAR4p2TgvGVcFrBDaum9Rmtk6fFz3IsyDnxoVFS8 wAnWtLK1XzVJz7JzCqKuj/Ai87WwpCnhmLSNH3FHmlPjDGQY4YUUkzKOKNddv/MDrQN0 YpEg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=98/PwVeFNeIxQrm0IqUyAA3dXph0wAaYOEANDm444S8=; b=uI6+k0d0VzTkvKI4DB0uG/fPq094RFYfE5YK/Dsr3YQaRK7yEQc0cy8nkr7lG5+OIc C3OFDMO2+LFohxPsYEevppvXrS5oZ0kBiiOb6a0u71AJoWNw0ua0RjP2/gQgeitsGFnT hEc9eaZSJkM9G934MM69wTsLvkjkeRYlRh+BH+OdrgM4Iw0lr7LORUQ9dj60oMN1WiCL cAtKo49lZjUBN37Mi/oiXrSWmu05KUHl0/bmxXA9iYoqYxYMbv4V3UJjuRnVCAYd4M4f WBLV5ZzGyilGFA++XMwoa6AGz9RfPxNi8jx3cUXhYYt47JuGqhHjai20jCt7R8M7eeyj 9qqw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZWNNVduD; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id c186-20020a621cc3000000b005dde05007b8si995848pfc.18.2023.03.09.20.25.33; Thu, 09 Mar 2023 20:25:47 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZWNNVduD; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230261AbjCJEJQ (ORCPT + 99 others); Thu, 9 Mar 2023 23:09:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59630 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230251AbjCJEIw (ORCPT ); Thu, 9 Mar 2023 23:08:52 -0500 Received: from mail-pg1-x52e.google.com (mail-pg1-x52e.google.com [IPv6:2607:f8b0:4864:20::52e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 63751F20B3 for ; Thu, 9 Mar 2023 20:08:48 -0800 (PST) Received: by mail-pg1-x52e.google.com with SMTP id h31so2354832pgl.6 for ; Thu, 09 Mar 2023 20:08:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678421328; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=98/PwVeFNeIxQrm0IqUyAA3dXph0wAaYOEANDm444S8=; b=ZWNNVduDwGtJ5TdwbKO1n1b2ypwy+U+1Tk9jm+BA1f85DEMnw7dAOhNUfyhgXugxUU c4ginfdyq3W8UE/eo0CfYAMd3A8oYPa583WjnaMLNtpJNo2nxAQ6XUOg8/MJ9ADC97I/ tO0ygyaFmUkBKM/Lu56kyTKYxhRJ+Tteih0LcVpn7lE2OCzwINtbTd4rwnFKUObFecPy lyW8e8rNtVI8vvu509sEAIzteSyBTo8tcpwYsKW4bfGZGBSvVTy+grIpvpZpeBzGoefb YbFYT9gzmwK3P6dW9uevU5sfHRbfaoXM00O//rlYZ1FwSNryWV/g6WEbZ+MXL00m3hOP E7qw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678421328; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=98/PwVeFNeIxQrm0IqUyAA3dXph0wAaYOEANDm444S8=; b=7M6DxX3ArApDmlf840LomoL2faBBNf1xuQg2bHAvMHNpsqMjMz8C4Zel5yid020HDa XEISmdtAz8xsP8Nfd5TTjkiWbhZPVm45PE1WBh5RXh49I/1hsBu+/hKhBKOe5Q6p0K8N /Fi784iz8fUtpf5N5y8HuaexQKlVGV9Dlb2MRIgJSG2Bp7YHWQFJiZ8QOLXO7BKw/QIj DzuN5SIQGnBiIT/w3tH+q4VOWrGyXp2zYxR+WnOYlTbUxVo1au4Jx8WAs8vWefHr9FnQ V0tYvFyuF0mu87jeCqCukSWSNeH1szDfTgiDb6y2HuOyskdgDVcKDCJwtRRc4Y7v85xs Ktsw== X-Gm-Message-State: AO0yUKUkNe2tFVhbT4NN6XwdGrLou6kBTyTWD/59Y3nLIQCgrSKS1rWN zTFleYFMFdNQYyAVYLbblh/t X-Received: by 2002:a05:6a00:1312:b0:5a8:c469:e47c with SMTP id j18-20020a056a00131200b005a8c469e47cmr623609pfu.10.1678421328586; Thu, 09 Mar 2023 20:08:48 -0800 (PST) Received: from localhost.localdomain ([27.111.75.67]) by smtp.gmail.com with ESMTPSA id y26-20020aa7855a000000b0058d92d6e4ddsm361846pfn.5.2023.03.09.20.08.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Mar 2023 20:08:48 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, quic_srichara@quicinc.com, Manivannan Sadhasivam Subject: [PATCH v3 04/19] PCI: qcom: Add missing macros for register fields Date: Fri, 10 Mar 2023 09:38:01 +0530 Message-Id: <20230310040816.22094-5-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230310040816.22094-1-manivannan.sadhasivam@linaro.org> References: <20230310040816.22094-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759953390813956693?= X-GMAIL-MSGID: =?utf-8?q?1759953390813956693?= Some of the registers are changed using hardcoded bitfields without macros. This provides no information on what the register setting is about. So add the macros to those fields for making the code more understandable. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 42 +++++++++++++++----------- 1 file changed, 25 insertions(+), 17 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index e9f4c70b719a..926a531fda3a 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -63,6 +63,7 @@ #define MISC_CONTROL_1_REG 0x8BC /* PARF_SYS_CTRL register fields */ +#define MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN BIT(29) #define MST_WAKEUP_EN BIT(13) #define SLV_WAKEUP_EN BIT(12) #define MSTR_ACLK_CGC_DIS BIT(10) @@ -87,6 +88,7 @@ /* PARF_PHY_CTRL register fields */ #define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK GENMASK(20, 16) #define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) FIELD_PREP(PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK, x) +#define PHY_TEST_PWR_DOWN BIT(0) /* PARF_PHY_REFCLK register fields */ #define PHY_REFCLK_SSP_EN BIT(16) @@ -103,6 +105,12 @@ #define MSTR_AXI_CLK_EN BIT(1) #define BYPASS BIT(4) +/* PARF_AXI_MSTR_WR_ADDR_HALT register fields */ +#define EN BIT(31) + +/* PARF_LTSSM register fields */ +#define LTSSM_EN BIT(8) + /* PARF_DEVICE_TYPE register fields */ #define DEVICE_TYPE_RC 0x4 @@ -440,7 +448,7 @@ static int qcom_pcie_post_init_2_1_0(struct qcom_pcie *pcie) /* enable PCIe clocks and resets */ val = readl(pcie->parf + PARF_PHY_CTRL); - val &= ~BIT(0); + val &= ~PHY_TEST_PWR_DOWN; writel(val, pcie->parf + PARF_PHY_CTRL); ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); @@ -595,7 +603,7 @@ static int qcom_pcie_post_init_1_0_0(struct qcom_pcie *pcie) if (IS_ENABLED(CONFIG_PCI_MSI)) { u32 val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT); - val |= BIT(31); + val |= EN; writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT); } @@ -608,7 +616,7 @@ static void qcom_pcie_2_3_2_ltssm_enable(struct qcom_pcie *pcie) /* enable link training */ val = readl(pcie->parf + PARF_LTSSM); - val |= BIT(8); + val |= LTSSM_EN; writel(val, pcie->parf + PARF_LTSSM); } @@ -715,7 +723,7 @@ static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie) /* enable PCIe clocks and resets */ val = readl(pcie->parf + PARF_PHY_CTRL); - val &= ~BIT(0); + val &= ~PHY_TEST_PWR_DOWN; writel(val, pcie->parf + PARF_PHY_CTRL); /* change DBI base address */ @@ -723,15 +731,15 @@ static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie) /* MAC PHY_POWERDOWN MUX DISABLE */ val = readl(pcie->parf + PARF_SYS_CTRL); - val &= ~BIT(29); + val &= ~MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN; writel(val, pcie->parf + PARF_SYS_CTRL); val = readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); - val |= BIT(4); + val |= BYPASS; writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); - val |= BIT(31); + val |= EN; writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); return 0; @@ -994,7 +1002,7 @@ static int qcom_pcie_post_init_2_4_0(struct qcom_pcie *pcie) /* enable PCIe clocks and resets */ val = readl(pcie->parf + PARF_PHY_CTRL); - val &= ~BIT(0); + val &= ~PHY_TEST_PWR_DOWN; writel(val, pcie->parf + PARF_PHY_CTRL); /* change DBI base address */ @@ -1002,15 +1010,15 @@ static int qcom_pcie_post_init_2_4_0(struct qcom_pcie *pcie) /* MAC PHY_POWERDOWN MUX DISABLE */ val = readl(pcie->parf + PARF_SYS_CTRL); - val &= ~BIT(29); + val &= ~MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN; writel(val, pcie->parf + PARF_SYS_CTRL); val = readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); - val |= BIT(4); + val |= BYPASS; writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); - val |= BIT(31); + val |= EN; writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); return 0; @@ -1159,7 +1167,7 @@ static int qcom_pcie_post_init_2_3_3(struct qcom_pcie *pcie) pcie->parf + PARF_SLV_ADDR_SPACE_SIZE_2_3_3); val = readl(pcie->parf + PARF_PHY_CTRL); - val &= ~BIT(0); + val &= ~PHY_TEST_PWR_DOWN; writel(val, pcie->parf + PARF_PHY_CTRL); writel(0, pcie->parf + PARF_DBI_BASE_ADDR); @@ -1275,7 +1283,7 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) /* enable PCIe clocks and resets */ val = readl(pcie->parf + PARF_PHY_CTRL); - val &= ~BIT(0); + val &= ~PHY_TEST_PWR_DOWN; writel(val, pcie->parf + PARF_PHY_CTRL); /* change DBI base address */ @@ -1283,11 +1291,11 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) /* MAC PHY_POWERDOWN MUX DISABLE */ val = readl(pcie->parf + PARF_SYS_CTRL); - val &= ~BIT(29); + val &= ~MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN; writel(val, pcie->parf + PARF_SYS_CTRL); val = readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); - val |= BIT(4); + val |= BYPASS; writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); /* Enable L1 and L1SS */ @@ -1297,7 +1305,7 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) if (IS_ENABLED(CONFIG_PCI_MSI)) { val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT); - val |= BIT(31); + val |= EN; writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT); } @@ -1390,7 +1398,7 @@ static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie) pcie->parf + PARF_SLV_ADDR_SPACE_SIZE); val = readl(pcie->parf + PARF_PHY_CTRL); - val &= ~BIT(0); + val &= ~PHY_TEST_PWR_DOWN; writel(val, pcie->parf + PARF_PHY_CTRL); writel(0, pcie->parf + PARF_DBI_BASE_ADDR); From patchwork Fri Mar 10 04:08:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 67217 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp680091wrd; Thu, 9 Mar 2023 20:27:31 -0800 (PST) X-Google-Smtp-Source: AK7set9oUYCNI8voPoestoSYyvk/J2cIRab922orqzuUTEWXWz5bjh8rUAp9dIV5f3Ft6wX9NZZP X-Received: by 2002:a05:6a20:1446:b0:d0:4f09:219a with SMTP id a6-20020a056a20144600b000d04f09219amr13266826pzi.39.1678422451619; Thu, 09 Mar 2023 20:27:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1678422451; cv=none; d=google.com; s=arc-20160816; b=sNicy10NZaZJnVlaeICN1Hi338ieYx6erwuSWQw20iT0KTjfZSEvTgxIWQKh0XfuPG /b8Am51wiJQU73oKyXmRwrgpcoMkvh0ACRSphe0vLsseMIyJIgXnIsXq7iTtj0bPIppS hkvQumtgYNkzokimpZ/w41hC/g5Zb3AGG6HXnTq4jAHIkvlovCeclEedz9r94RbzgQm3 iQsAdipupMz7xBmmqVANJKqGblSS2rkbvKKCQHRbGUR2Sv4wALuKMPCulhTJEBLp4a/C wn3naE11J5e1bAXF8b/f38fb8KYfL2KTTMtmk/8y3qPCxXwC9gsqfsCz3/5bpim6I6h8 LJFw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=hS/BEmRpdBxk7z2vn4cP+VagM+gkHpiXxJLmHI41D7s=; b=larFFJpv2dTdotjLKYRx0V9ul6dBOKJBM4hpp5j5nWNgLHivoyQG+nUPL+2sD8eoS2 CL5yjTuvCWzILlCgWzH8X7qDQp2QQECTKxX/WGp7QpPTl2PAAZvaWpFWkP8eb7WcCJfN xCyvhR8rOl88DydZ59DgAAESTfX32W48hIOXIIjn1Ae6MXO0htoH28FpezL0nv/aoAzb 8SkMuGZYoJSbj98qXMHtrHMVNvTINMAcgZv5xylFQNr10NCspukOcbyHu50leiqZxOlr kTr4jIUmsYtxF0mprJhlXvqIVJnr402876XB1LKqs0I6E/yTWkgD/b94Zrx1RfEoGeWh g54g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="uxYxp0F/"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id e66-20020a621e45000000b005a904cfc3fcsi954351pfe.211.2023.03.09.20.27.19; Thu, 09 Mar 2023 20:27:31 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="uxYxp0F/"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230281AbjCJEKH (ORCPT + 99 others); Thu, 9 Mar 2023 23:10:07 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60948 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230337AbjCJEJN (ORCPT ); Thu, 9 Mar 2023 23:09:13 -0500 Received: from mail-pl1-x634.google.com (mail-pl1-x634.google.com [IPv6:2607:f8b0:4864:20::634]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 314ADF4B59 for ; Thu, 9 Mar 2023 20:09:01 -0800 (PST) Received: by mail-pl1-x634.google.com with SMTP id u5so4300844plq.7 for ; Thu, 09 Mar 2023 20:09:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678421334; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hS/BEmRpdBxk7z2vn4cP+VagM+gkHpiXxJLmHI41D7s=; b=uxYxp0F/05gIQ47D431qZsuL0ZqbDv4S6AOJRgbF/p10t1CxAXIexgDlZyssPyqQJO upkOLJnUn6S3efnNxZYGjsytvJjQqS3s/Osr6ZaO1/O0iX0YDB40opwuBFJ0bF71ejQx iT9mUrgkJl42RZYeJPPAjm6VB2ZSc0RkNPmrJqgV2g68szDQbAK1GqiKAcyxNy/o5FuF zv8/3LmzqSKYgbYs5P1nrb6SfYIhK/1CkmJ2JiNgHIP+tRRZG8Zhfh285EpBhllj1nkm lr1bzbvG58Hc15NSjcwk31bn39380FwPiT/grnNBW7cm2qJoG9Gb3EGKQiyo3VLmo3ax KkaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678421334; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hS/BEmRpdBxk7z2vn4cP+VagM+gkHpiXxJLmHI41D7s=; b=cD1Ct3ljDsafQysHttTiaLOV/aB59kGRwXigD9c8jmjqOXQmki/96eLgqCeI8+gHAY 4BTFRt7cA6jsirnKCCBmWe8j+QCx7QqT+ayhwGm0Enm8TcsuUlNmWxd9TCGf6956HIyq 1Hxq4UNQZL6cBa2Q22ufMGXIrYFFXtfS+nIEDJ+z1vDME/KSjzpLwa24LCaec2chgXcn 58rB1OJ+7NyCV4fkuATefSxsQk9MO3WbLE5vLhWAi5c5iNYm7zT7N+7YAs2EsnrhEzNo vWK/H12p0LxzbjLT1Bovt6lGQY34R6rhtV1Ov5rpWzXCLzGS5rLnVE4UAhK7dtPEg3G8 GmBQ== X-Gm-Message-State: AO0yUKVdgKnVcAHZK3pNRa+EywtSSCPZKbCJIAMDh8V/esbCVV2RqLzv 0Yx6FLYTK1DQIkKnM3QKfJH6 X-Received: by 2002:a05:6a20:bc98:b0:d0:76e3:16e5 with SMTP id fx24-20020a056a20bc9800b000d076e316e5mr8210613pzb.2.1678421333832; Thu, 09 Mar 2023 20:08:53 -0800 (PST) Received: from localhost.localdomain ([27.111.75.67]) by smtp.gmail.com with ESMTPSA id y26-20020aa7855a000000b0058d92d6e4ddsm361846pfn.5.2023.03.09.20.08.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Mar 2023 20:08:52 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, quic_srichara@quicinc.com, Manivannan Sadhasivam Subject: [PATCH v3 05/19] PCI: qcom: Use lower case for hex Date: Fri, 10 Mar 2023 09:38:02 +0530 Message-Id: <20230310040816.22094-6-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230310040816.22094-1-manivannan.sadhasivam@linaro.org> References: <20230310040816.22094-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759953500260285460?= X-GMAIL-MSGID: =?utf-8?q?1759953500260285460?= To maintain uniformity, let's use lower case for representing hexadecimal numbers. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 926a531fda3a..4179ac973147 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -39,17 +39,17 @@ #define PARF_PCS_DEEMPH 0x34 #define PARF_PCS_SWING 0x38 #define PARF_PHY_CTRL 0x40 -#define PARF_PHY_REFCLK 0x4C +#define PARF_PHY_REFCLK 0x4c #define PARF_CONFIG_BITS 0x50 #define PARF_DBI_BASE_ADDR 0x168 -#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3 0x16C /* Register offset specific to IP ver 2.3.3 */ +#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3 0x16c /* Register offset specific to IP ver 2.3.3 */ #define PARF_MHI_CLOCK_RESET_CTRL 0x174 #define PARF_AXI_MSTR_WR_ADDR_HALT 0x178 -#define PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1A8 -#define PARF_Q2A_FLUSH 0x1AC -#define PARF_LTSSM 0x1B0 +#define PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1a8 +#define PARF_Q2A_FLUSH 0x1ac +#define PARF_LTSSM 0x1b0 #define PARF_SID_OFFSET 0x234 -#define PARF_BDF_TRANSLATE_CFG 0x24C +#define PARF_BDF_TRANSLATE_CFG 0x24c #define PARF_SLV_ADDR_SPACE_SIZE 0x358 #define PARF_DEVICE_TYPE 0x1000 #define PARF_BDF_TO_SID_TABLE_N 0x2000 @@ -60,7 +60,7 @@ /* DBI registers */ #define AXI_MSTR_RESP_COMP_CTRL0 0x818 #define AXI_MSTR_RESP_COMP_CTRL1 0x81c -#define MISC_CONTROL_1_REG 0x8BC +#define MISC_CONTROL_1_REG 0x8bc /* PARF_SYS_CTRL register fields */ #define MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN BIT(29) From patchwork Fri Mar 10 04:08:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 67210 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp679060wrd; Thu, 9 Mar 2023 20:23:35 -0800 (PST) X-Google-Smtp-Source: AK7set+hzt7Vkh91sJ+L7QNeeZBrz2JK8Qo83fEF79het2v0ZWK+seNfBRtHfF0jlf1mnjyYhaFh X-Received: by 2002:a17:90b:1d8f:b0:237:161e:3329 with SMTP id pf15-20020a17090b1d8f00b00237161e3329mr24184801pjb.40.1678422214874; Thu, 09 Mar 2023 20:23:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1678422214; cv=none; d=google.com; s=arc-20160816; b=TlKAwadiqUWCD96Y75QDuwIOQ8yjMZys0InimWjEjqRQPnr2dCn+z0yXWBckDGg6Qc cdDag8bVm21sSxjGUXwHvgHfKijm+w3OcOV+yIoJ7HbSdchXvvXN0ecY2rWc5GfZz9jg Ch2JJ3vbbd8PY01VTlvGyGJv8yGUAwTV6AUSigHtjmVf3TENqfQLP3NxMD4FR149JuiP PytiSmebFonTe5/bB79x+fxN8jf2RALuDbolaw5Qv/4rixfeWY9BYS0TbD4sJovoFezT TcMalFcEe0A+Tr9wWqDVsy3M84PU4d/WtQ5Mb+wUiIMGJ2MhCH0aJBeViIWJO++liAOw ydJQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=UJ4Ik+ZoB8puIUL4lEznFsK6NoJYzy77sft3aaSqBZo=; b=uKAQnQRcsKAFss/CMG4QINaN8ARcOCj513O9e4ZWtT3GDfC6ewU0Y4+gGmMY9ZEh/O tXyko7+PGS+sZpW5kHihU7Zm9vJfpSHS4ctyrBtVGq34//1VcfBMtkkGR2akGhy2RVej RbQfystWJ+OUpwEokAOkyYt7gD+CXt8Tii76wgI3KmYnaCjlaHG4TetNW7l1k94G8IoO hWPHXe5hz6S93VY2uQs3KaelnwvPkzdKGWm007LQfnzVzR4hy5M6aUYRFSEv1XZ0812Q 2FViYkSTMwbahkP5pLrbOyvxAyNutJbhHVI4tYcgON1e84wuGrCrg85Lggjn1Ob5zzF/ qFdQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=F03nf17Q; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id a14-20020a17090a740e00b002340152a657si885691pjg.176.2023.03.09.20.23.20; Thu, 09 Mar 2023 20:23:34 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=F03nf17Q; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230328AbjCJEJr (ORCPT + 99 others); Thu, 9 Mar 2023 23:09:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59574 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230326AbjCJEJL (ORCPT ); Thu, 9 Mar 2023 23:09:11 -0500 Received: from mail-pf1-x434.google.com (mail-pf1-x434.google.com [IPv6:2607:f8b0:4864:20::434]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9CBC8F34DA for ; Thu, 9 Mar 2023 20:08:58 -0800 (PST) Received: by mail-pf1-x434.google.com with SMTP id fa28so2847714pfb.12 for ; Thu, 09 Mar 2023 20:08:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678421338; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UJ4Ik+ZoB8puIUL4lEznFsK6NoJYzy77sft3aaSqBZo=; b=F03nf17Q4rGh1wJBbuwIaY2JJgZUScNUAtHQp2iNxiIcAxZq1xNXoUkuro303qSmWH OCgnC/7xRV7LsWgoUBfTOY7/S3ijV/4bg+hu9LqUhJHJlPJK4QGrkuEDbOCkGE17ZXoB IZlQUDGOoM5NVS41rBZcxGZd0YW0VPl7WaJ64rVW+nNbN6YFEZ9QBgUiX7OxI83k5wz7 5IdgZe/ed489aN3fkCpDRxjE4iT4uVH2WSpufglmGRKjobrZt1Ts0gDu+tauSFMVzfyj rHDRL8Ma/sSY9HWa9vFyL3x1nI1yIgVt5xUC2shhvV6Qjf57n00p66+7QFJuRnbDlOvw N79A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678421338; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UJ4Ik+ZoB8puIUL4lEznFsK6NoJYzy77sft3aaSqBZo=; b=kZgBF6cq+LjwaYq6917TLG3b+2PIXQ0/gsRCopHvcDC+CUIbdGGVOS24CiaLFF8fpu +LHqPdq9HpLJP6X5yjal4yKp2Zqts2MgK6zsKyn0JcsoZnoqeJaNVQqAPEurYJ8D2cIM ATG4BpDHxzo3/bbfdOEAK3Yth65MMjPMhfz97REEaJcQOBHl1SCe3RiVC1OxckeVRib9 GVDZ/Ba4yT0YcYFZY3qbu6WouMG9CT9z4U6DEvYoK4l1cYsMPQq0QPgg5vLwVo4foe6T AXNJqFuXgSMH2mJCs/D7QxFmTU6GkPHAptkRauw+nhSRqNdQl2ABBDh+cN0zDEygYMOr qZSg== X-Gm-Message-State: AO0yUKWeD2uZvu4m9tYace9CPFv84SPzBaWmjYj3yY4zFVaY/5hob6ya qj/u5z30FDzrsDsjbTAXsIIPwat5nmZfYAuwiA== X-Received: by 2002:aa7:982d:0:b0:5a9:e8dd:80ea with SMTP id q13-20020aa7982d000000b005a9e8dd80eamr19973664pfl.17.1678421337782; Thu, 09 Mar 2023 20:08:57 -0800 (PST) Received: from localhost.localdomain ([27.111.75.67]) by smtp.gmail.com with ESMTPSA id y26-20020aa7855a000000b0058d92d6e4ddsm361846pfn.5.2023.03.09.20.08.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Mar 2023 20:08:57 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, quic_srichara@quicinc.com, Manivannan Sadhasivam Subject: [PATCH v3 06/19] PCI: qcom: Use bulk reset APIs for handling resets for IP rev 2.1.0 Date: Fri, 10 Mar 2023 09:38:03 +0530 Message-Id: <20230310040816.22094-7-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230310040816.22094-1-manivannan.sadhasivam@linaro.org> References: <20230310040816.22094-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759953252645401769?= X-GMAIL-MSGID: =?utf-8?q?1759953252645401769?= All the resets are asserted and deasserted at the same time. So the bulk reset APIs can be used to handle them together. This simplifies the code a lot. While at it, let's also move the qcom_pcie_resources_2_1_0 struct below qcom_pcie_resources_1_0_0 to keep it sorted. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 129 +++++++------------------ 1 file changed, 34 insertions(+), 95 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 4179ac973147..2d9116464842 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -143,22 +143,8 @@ #define PERST_DELAY_US 1000 -#define QCOM_PCIE_2_1_0_MAX_SUPPLY 3 -#define QCOM_PCIE_2_1_0_MAX_CLOCKS 5 - #define QCOM_PCIE_CRC8_POLYNOMIAL (BIT(2) | BIT(1) | BIT(0)) -struct qcom_pcie_resources_2_1_0 { - struct clk_bulk_data clks[QCOM_PCIE_2_1_0_MAX_CLOCKS]; - struct reset_control *pci_reset; - struct reset_control *axi_reset; - struct reset_control *ahb_reset; - struct reset_control *por_reset; - struct reset_control *phy_reset; - struct reset_control *ext_reset; - struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY]; -}; - struct qcom_pcie_resources_1_0_0 { struct clk *iface; struct clk *aux; @@ -168,6 +154,16 @@ struct qcom_pcie_resources_1_0_0 { struct regulator *vdda; }; +#define QCOM_PCIE_2_1_0_MAX_CLOCKS 5 +#define QCOM_PCIE_2_1_0_MAX_RESETS 6 +#define QCOM_PCIE_2_1_0_MAX_SUPPLY 3 +struct qcom_pcie_resources_2_1_0 { + struct clk_bulk_data clks[QCOM_PCIE_2_1_0_MAX_CLOCKS]; + struct reset_control_bulk_data resets[QCOM_PCIE_2_1_0_MAX_RESETS]; + int num_resets; + struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY]; +}; + #define QCOM_PCIE_2_3_2_MAX_SUPPLY 2 struct qcom_pcie_resources_2_3_2 { struct clk *aux_clk; @@ -295,6 +291,7 @@ static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie) struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; struct dw_pcie *pci = pcie->pci; struct device *dev = pci->dev; + bool is_apq = of_device_is_compatible(dev->of_node, "qcom,pcie-apq8064"); int ret; res->supplies[0].supply = "vdda"; @@ -321,28 +318,20 @@ static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie) if (ret < 0) return ret; - res->pci_reset = devm_reset_control_get_exclusive(dev, "pci"); - if (IS_ERR(res->pci_reset)) - return PTR_ERR(res->pci_reset); - - res->axi_reset = devm_reset_control_get_exclusive(dev, "axi"); - if (IS_ERR(res->axi_reset)) - return PTR_ERR(res->axi_reset); - - res->ahb_reset = devm_reset_control_get_exclusive(dev, "ahb"); - if (IS_ERR(res->ahb_reset)) - return PTR_ERR(res->ahb_reset); + res->resets[0].id = "pci"; + res->resets[1].id = "axi"; + res->resets[2].id = "ahb"; + res->resets[3].id = "por"; + res->resets[4].id = "phy"; + res->resets[5].id = "ext"; - res->por_reset = devm_reset_control_get_exclusive(dev, "por"); - if (IS_ERR(res->por_reset)) - return PTR_ERR(res->por_reset); - - res->ext_reset = devm_reset_control_get_optional_exclusive(dev, "ext"); - if (IS_ERR(res->ext_reset)) - return PTR_ERR(res->ext_reset); + /* ext is optional on APQ8016 */ + res->num_resets = is_apq ? 5 : 6; + ret = devm_reset_control_bulk_get_exclusive(dev, res->num_resets, res->resets); + if (ret < 0) + return ret; - res->phy_reset = devm_reset_control_get_exclusive(dev, "phy"); - return PTR_ERR_OR_ZERO(res->phy_reset); + return 0; } static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie) @@ -350,12 +339,7 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie) struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); - reset_control_assert(res->pci_reset); - reset_control_assert(res->axi_reset); - reset_control_assert(res->ahb_reset); - reset_control_assert(res->por_reset); - reset_control_assert(res->ext_reset); - reset_control_assert(res->phy_reset); + reset_control_bulk_assert(res->num_resets, res->resets); writel(1, pcie->parf + PARF_PHY_CTRL); @@ -370,12 +354,11 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) int ret; /* reset the PCIe interface as uboot can leave it undefined state */ - reset_control_assert(res->pci_reset); - reset_control_assert(res->axi_reset); - reset_control_assert(res->ahb_reset); - reset_control_assert(res->por_reset); - reset_control_assert(res->ext_reset); - reset_control_assert(res->phy_reset); + ret = reset_control_bulk_assert(res->num_resets, res->resets); + if (ret < 0) { + dev_err(dev, "cannot assert resets\n"); + return ret; + } ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies); if (ret < 0) { @@ -383,58 +366,14 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) return ret; } - ret = reset_control_deassert(res->ahb_reset); - if (ret) { - dev_err(dev, "cannot deassert ahb reset\n"); - goto err_deassert_ahb; - } - - ret = reset_control_deassert(res->ext_reset); - if (ret) { - dev_err(dev, "cannot deassert ext reset\n"); - goto err_deassert_ext; - } - - ret = reset_control_deassert(res->phy_reset); - if (ret) { - dev_err(dev, "cannot deassert phy reset\n"); - goto err_deassert_phy; - } - - ret = reset_control_deassert(res->pci_reset); - if (ret) { - dev_err(dev, "cannot deassert pci reset\n"); - goto err_deassert_pci; - } - - ret = reset_control_deassert(res->por_reset); - if (ret) { - dev_err(dev, "cannot deassert por reset\n"); - goto err_deassert_por; - } - - ret = reset_control_deassert(res->axi_reset); - if (ret) { - dev_err(dev, "cannot deassert axi reset\n"); - goto err_deassert_axi; + ret = reset_control_bulk_deassert(res->num_resets, res->resets); + if (ret < 0) { + dev_err(dev, "cannot deassert resets\n"); + regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); + return ret; } return 0; - -err_deassert_axi: - reset_control_assert(res->por_reset); -err_deassert_por: - reset_control_assert(res->pci_reset); -err_deassert_pci: - reset_control_assert(res->phy_reset); -err_deassert_phy: - reset_control_assert(res->ext_reset); -err_deassert_ext: - reset_control_assert(res->ahb_reset); -err_deassert_ahb: - regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); - - return ret; } static int qcom_pcie_post_init_2_1_0(struct qcom_pcie *pcie) From patchwork Fri Mar 10 04:08:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 67203 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp678171wrd; Thu, 9 Mar 2023 20:20:41 -0800 (PST) X-Google-Smtp-Source: AK7set+DkoxdbSH+rDjvvVlD0IfiSgcmaVP4hf3lZSp4014XDSKFlaxWsxnNssnfZ/tDKwKVxqrE X-Received: by 2002:a17:90b:4a4c:b0:237:9cc7:28a4 with SMTP id lb12-20020a17090b4a4c00b002379cc728a4mr25667395pjb.14.1678422041405; Thu, 09 Mar 2023 20:20:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1678422041; cv=none; d=google.com; s=arc-20160816; b=OEh2eEig5UHa6lSCeOUpp8tIPYCv8zN5h2pO2g56BxjuP6+8btqtR8DfO9RSanNGEa rw/5K0OMm2EiuU0dDUN3m5jLnhsc1lI4DUp/Rly/kS23xlV3+avRquVe2JDSiqo1duwX YqyBVlMc8aXyKiErY74E2/xljLbtGK3Md3IGa0kVIlSvgodCTyZiRwMnDJYPi9ixJl8e +XpXHXTVoWfer09Pcpvo32zGS5yv17gJykElwxVbtVVyYA7kWBJts2SRMRq2W/g/u/Ik FStb67a5Sn7J/h8M0lXe506ygci6DmtotQNiu5z0wZndeA9tOmq+ovCBjX2MorxeH+bJ 9Zpw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=TSFkykYkB7c0gJwp2FwEg/ye5mEGILHD2HLR3ehwkBA=; b=TZiqFSvAidWEQsaXYUefHdKM4jlxxSrYIOKPkpk2gIP0PlVcgLb7VvShtz4AjLfM37 CEGrGo1QTEnF4XEhWWBNYWRQxfCoZUbsFb3ZQLUxrD+em8D7OqZ4pt2fWzjhk1TepCiN ljPzT0JKrkyEcyuBesXJbGHGrL6UbIy20h6pQJx4aKbqYBGTxv7GORr3+Dn2UzThMQiF VowI9bjidwzWO/QGlrBxD4yfPKX8F06vFxOBo5UFaux/oZE+j7nQawiv9c3u8XYpbBQr 03PKM3OlDao5yj5Wpf789jcRhp33vD1q6RCoO2dka9Yb2ixVB7jA9cNcJgVgf4OGGgm0 7YRQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=oVXd7b4k; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id q16-20020a17090aa01000b00235563071d3si1544575pjp.75.2023.03.09.20.20.29; Thu, 09 Mar 2023 20:20:41 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=oVXd7b4k; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230330AbjCJEKN (ORCPT + 99 others); Thu, 9 Mar 2023 23:10:13 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59462 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230371AbjCJEJ2 (ORCPT ); Thu, 9 Mar 2023 23:09:28 -0500 Received: from mail-pj1-x102b.google.com (mail-pj1-x102b.google.com [IPv6:2607:f8b0:4864:20::102b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AA71BF5ABB for ; Thu, 9 Mar 2023 20:09:08 -0800 (PST) Received: by mail-pj1-x102b.google.com with SMTP id q31-20020a17090a17a200b0023750b69614so3994884pja.5 for ; Thu, 09 Mar 2023 20:09:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678421342; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TSFkykYkB7c0gJwp2FwEg/ye5mEGILHD2HLR3ehwkBA=; b=oVXd7b4kdJXE2amluOUwK2rOccTnxwOAz+X3RJz2cnGo1HefalrMrz6t14sziJg5q4 ofJaHZB9odTHGcjJjRZPBSIUiZcjCZMBchnYshU9CvJ+mmYgamjo9cgNKLdbpcSAepL3 Hs8chovDO71Wq1b+pxpX1grybkFKxsl7f0kWPCmba/LV2bX5ZDMyHn1BULT36M+J57Og dYB9mtzjcvFbHwh4MQ4Rbn0QveRr7m15aEddm9lHQSmC3sip6eoL8gRdCmYzegDVix+8 RzcaUvqNdi1Ba6jlNPCWHHRc0jGK4BuEnmunQSNLlS3MhoTjvBbN+Dv2HZZDUhqEqXwJ dl5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678421342; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TSFkykYkB7c0gJwp2FwEg/ye5mEGILHD2HLR3ehwkBA=; b=hdZDIGJrCbiCq/M2MXTLedeAw2utUEqrABJo6Yc6V5Jax1/3XOKTlEDfW9tZMyFIzm PENXzGhSIu/2ujDnZ3I3swUnySUcF7LsDUneC4mcszyrNDHgdkXavIJfXA5F353S5L8E AYmv02L6833U82BeM0HTcGi1MFGGBGoGdbo7QZjFHBf+lq5ozSpKhya+i+ujufUdC1Ur zKDOkJyqzV0KF9aRlplkvKSNB+/fQ6md2KE315ewq9S4XhFca/tUKePKsOHyC70OgjM0 nMSwGMn2g529APmrST1oCDuy7vWvsj24wQNn65bOidF/7NdDwjlCIbtDkmkMKUQRR39p VM4w== X-Gm-Message-State: AO0yUKWjb8P1iu9n7xQIS70Igw8IgU/TkkfKkGvUXJRRHLZ4p/QdBNfN WBm1Dmb5P0+v+/nhmqcfBbZ/ X-Received: by 2002:a05:6a20:6620:b0:c7:3209:f24d with SMTP id n32-20020a056a20662000b000c73209f24dmr18679656pzh.56.1678421341970; Thu, 09 Mar 2023 20:09:01 -0800 (PST) Received: from localhost.localdomain ([27.111.75.67]) by smtp.gmail.com with ESMTPSA id y26-20020aa7855a000000b0058d92d6e4ddsm361846pfn.5.2023.03.09.20.08.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Mar 2023 20:09:01 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, quic_srichara@quicinc.com, Manivannan Sadhasivam Subject: [PATCH v3 07/19] PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 1.0.0 Date: Fri, 10 Mar 2023 09:38:04 +0530 Message-Id: <20230310040816.22094-8-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230310040816.22094-1-manivannan.sadhasivam@linaro.org> References: <20230310040816.22094-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759953070684833931?= X-GMAIL-MSGID: =?utf-8?q?1759953070684833931?= All the clocks are enabled and disabled at the same time. So the bulk clock APIs can be used to handle them together. This simplifies the code a lot. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 72 +++++++------------------- 1 file changed, 19 insertions(+), 53 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 2d9116464842..0bb27d3c95a0 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -145,11 +145,9 @@ #define QCOM_PCIE_CRC8_POLYNOMIAL (BIT(2) | BIT(1) | BIT(0)) +#define QCOM_PCIE_1_0_0_MAX_CLOCKS 4 struct qcom_pcie_resources_1_0_0 { - struct clk *iface; - struct clk *aux; - struct clk *master_bus; - struct clk *slave_bus; + struct clk_bulk_data clks[QCOM_PCIE_1_0_0_MAX_CLOCKS]; struct reset_control *core; struct regulator *vdda; }; @@ -439,26 +437,20 @@ static int qcom_pcie_get_resources_1_0_0(struct qcom_pcie *pcie) struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0; struct dw_pcie *pci = pcie->pci; struct device *dev = pci->dev; + int ret; res->vdda = devm_regulator_get(dev, "vdda"); if (IS_ERR(res->vdda)) return PTR_ERR(res->vdda); - res->iface = devm_clk_get(dev, "iface"); - if (IS_ERR(res->iface)) - return PTR_ERR(res->iface); - - res->aux = devm_clk_get(dev, "aux"); - if (IS_ERR(res->aux)) - return PTR_ERR(res->aux); - - res->master_bus = devm_clk_get(dev, "master_bus"); - if (IS_ERR(res->master_bus)) - return PTR_ERR(res->master_bus); + res->clks[0].id = "iface"; + res->clks[1].id = "aux"; + res->clks[2].id = "master_bus"; + res->clks[3].id = "slave_bus"; - res->slave_bus = devm_clk_get(dev, "slave_bus"); - if (IS_ERR(res->slave_bus)) - return PTR_ERR(res->slave_bus); + ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks); + if (ret < 0) + return ret; res->core = devm_reset_control_get_exclusive(dev, "core"); return PTR_ERR_OR_ZERO(res->core); @@ -469,10 +461,7 @@ static void qcom_pcie_deinit_1_0_0(struct qcom_pcie *pcie) struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0; reset_control_assert(res->core); - clk_disable_unprepare(res->slave_bus); - clk_disable_unprepare(res->master_bus); - clk_disable_unprepare(res->iface); - clk_disable_unprepare(res->aux); + clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); regulator_disable(res->vdda); } @@ -489,46 +478,23 @@ static int qcom_pcie_init_1_0_0(struct qcom_pcie *pcie) return ret; } - ret = clk_prepare_enable(res->aux); - if (ret) { - dev_err(dev, "cannot prepare/enable aux clock\n"); - goto err_res; - } - - ret = clk_prepare_enable(res->iface); - if (ret) { - dev_err(dev, "cannot prepare/enable iface clock\n"); - goto err_aux; - } - - ret = clk_prepare_enable(res->master_bus); - if (ret) { - dev_err(dev, "cannot prepare/enable master_bus clock\n"); - goto err_iface; - } - - ret = clk_prepare_enable(res->slave_bus); + ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); if (ret) { - dev_err(dev, "cannot prepare/enable slave_bus clock\n"); - goto err_master; + dev_err(dev, "cannot prepare/enable clocks\n"); + goto err_assert_reset; } ret = regulator_enable(res->vdda); if (ret) { dev_err(dev, "cannot enable vdda regulator\n"); - goto err_slave; + goto err_disable_clks; } return 0; -err_slave: - clk_disable_unprepare(res->slave_bus); -err_master: - clk_disable_unprepare(res->master_bus); -err_iface: - clk_disable_unprepare(res->iface); -err_aux: - clk_disable_unprepare(res->aux); -err_res: + +err_disable_clks: + clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); +err_assert_reset: reset_control_assert(res->core); return ret; From patchwork Fri Mar 10 04:08:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 67207 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp678667wrd; Thu, 9 Mar 2023 20:22:26 -0800 (PST) X-Google-Smtp-Source: AK7set/Im1C/fShwbQA8cGTQy+Y3NcQ2Zjw0pCnVtLJvjX4rNznfvT4Gshgt07rPI2vy7pjsfHv4 X-Received: by 2002:a62:5258:0:b0:5a9:bd0c:4704 with SMTP id g85-20020a625258000000b005a9bd0c4704mr22287201pfb.14.1678422145717; Thu, 09 Mar 2023 20:22:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1678422145; cv=none; d=google.com; s=arc-20160816; b=c+ZbqAbsE1dmppTosiY/yt8XcegngsoV0UHvWFRAPsoD0mH0v0Qze+iqTYurYkQ/mI PJF81FS7vYeO6vUhQWZrim2UwS82T37rC0Z3BTGnQUQJ+on1W9ku1kuH8gUf/OZAdk3m VokCVAuzhRrV0jrNXsQjRvc+kfUIlHng5iqd9Y5vpnLK9Up9WtyagQ0DBE/YRL0Hg3nq YV7xu1biar+qaZ1PrQ9/CeuC5zbHFPmzyaofAUHJrgiVk8XLpG1XyxPJTMakkbmL8EnM c/+NIeJ0pvvuIBxiIc7mgr58EYxcj+tOFv5qqIpr46cgF5RvODW+Yj9GN1klJEnc4VwY y6GA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=amLlMnvqqV/ACQXsqFtaJlfI0hCQH92ixpD+YcVSgsE=; b=z/vgEATMY10+NRHot5C7W5gkAGgQJSdY8q2TzEMJpdEPiaT/upoy8xkbz/RYRUKNdD HV8+3fdNTnfCOKjy10qLRgaIx1kSPhc3vU+cPP/eO29SBKibyGeSt7ECxTLnUn+YLt8z X0KiQ/m7P2YM65DjmR+fLMGPM1i54yUIvR4OMsb8jU7nyggFn0e6qML/llc3jElnIEJw zRwk97Na+N7F3schTPtdSEpJE12xVTujJpyJcumbbNTMImgl/lXYqmVEDTxg690e8/Mv 3cWcsDQPg8U9Cx9wK7Oak2GhUjTpfvaE19NVDyqi3dqVCf8dVmkxpUiiRrlcL3sHC/m1 T/bg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FP48LLtv; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id j7-20020a625507000000b0059038315e75si1051293pfb.33.2023.03.09.20.22.12; Thu, 09 Mar 2023 20:22:25 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FP48LLtv; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230360AbjCJEK3 (ORCPT + 99 others); Thu, 9 Mar 2023 23:10:29 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33522 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230375AbjCJEJa (ORCPT ); Thu, 9 Mar 2023 23:09:30 -0500 Received: from mail-pf1-x42c.google.com (mail-pf1-x42c.google.com [IPv6:2607:f8b0:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 92147F5D10 for ; Thu, 9 Mar 2023 20:09:12 -0800 (PST) Received: by mail-pf1-x42c.google.com with SMTP id fd25so2878841pfb.1 for ; Thu, 09 Mar 2023 20:09:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678421346; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=amLlMnvqqV/ACQXsqFtaJlfI0hCQH92ixpD+YcVSgsE=; b=FP48LLtvmB4FaFSLBkCUq5YVkHxa0Vjh6dBPyRfarzzn+lhQDW8oUf2FSZrGo4INpP IKVV7Ul6PirWNx8o04YoBGYMkLL3Jbwv1mVqurmyEOzbnagBqDRS3KUCDRe0LY0vdiQV JwyzJykWtdCR9g8xRQjVtSB+9v11mFnqsDrP9Ljwl4ubwuKfPGwnSp3L5NgS063FZlot 2WjapDFno5ZOAy+P3b3fQW9ML0bKR/Gp6GMP2eQwzuRS9Lo+7nheWoUUI8Tm1h17XZM7 1ah6J62B5WCSTuxxe2WD1aw4tQNdV214w9khV9RuDZ/hKwDJPQKUfIui0Lt9yIP3Z1K1 rAEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678421346; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=amLlMnvqqV/ACQXsqFtaJlfI0hCQH92ixpD+YcVSgsE=; b=MAsKx8gAd51FB7KAp1jYFH4pGfklm1fy2gAkdKRj7GqEQkzFxzvP6oJ95mWicOmThu yMYzPUr7i2ECXUw3nlD8kh3SAumfNpi6BcWdopoNB4gGrbnRVCgvo5YvKkd6OTeibxLD 2+SD0danPK/p2Prvu5hSHO46ZX/jQ69TYHTPbKVxLBFDeEztCVUYRZ2ReHqPlPVzDvmW Tu9/BEfWfyyiBvQLVeIW3/FgDeofBb+74ZFTKS+Z3BjaJZWl9X8OxaqK9WM5SpYaIHex yAbxDjTFC/GLq9QQonulX6EnDFIXgyFjyLRsbEkblaqhMY0Gj5D6aw6YsLFnGJAVtX7m LCYw== X-Gm-Message-State: AO0yUKXi+pcra4K6UWrMoX6AOEqYNuFq1f0pFZSkSmFgHgFz9K7uUUs3 fPD8034vBZTTFlw7D1V+Tmkl X-Received: by 2002:a62:1bd0:0:b0:5e1:6a3b:61a1 with SMTP id b199-20020a621bd0000000b005e16a3b61a1mr18367746pfb.34.1678421346027; Thu, 09 Mar 2023 20:09:06 -0800 (PST) Received: from localhost.localdomain ([27.111.75.67]) by smtp.gmail.com with ESMTPSA id y26-20020aa7855a000000b0058d92d6e4ddsm361846pfn.5.2023.03.09.20.09.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Mar 2023 20:09:05 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, quic_srichara@quicinc.com, Manivannan Sadhasivam Subject: [PATCH v3 08/19] PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 2.3.2 Date: Fri, 10 Mar 2023 09:38:05 +0530 Message-Id: <20230310040816.22094-9-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230310040816.22094-1-manivannan.sadhasivam@linaro.org> References: <20230310040816.22094-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759953179807009963?= X-GMAIL-MSGID: =?utf-8?q?1759953179807009963?= All the clocks are enabled and disabled at the same time. So the bulk clock APIs can be used to handle them together. This simplifies the code a lot. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 72 ++++++-------------------- 1 file changed, 15 insertions(+), 57 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 0bb27d3c95a0..939973733a1e 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -162,12 +162,10 @@ struct qcom_pcie_resources_2_1_0 { struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY]; }; -#define QCOM_PCIE_2_3_2_MAX_SUPPLY 2 +#define QCOM_PCIE_2_3_2_MAX_CLOCKS 4 +#define QCOM_PCIE_2_3_2_MAX_SUPPLY 2 struct qcom_pcie_resources_2_3_2 { - struct clk *aux_clk; - struct clk *master_clk; - struct clk *slave_clk; - struct clk *cfg_clk; + struct clk_bulk_data clks[QCOM_PCIE_2_3_2_MAX_CLOCKS]; struct regulator_bulk_data supplies[QCOM_PCIE_2_3_2_MAX_SUPPLY]; }; @@ -539,21 +537,14 @@ static int qcom_pcie_get_resources_2_3_2(struct qcom_pcie *pcie) if (ret) return ret; - res->aux_clk = devm_clk_get(dev, "aux"); - if (IS_ERR(res->aux_clk)) - return PTR_ERR(res->aux_clk); - - res->cfg_clk = devm_clk_get(dev, "cfg"); - if (IS_ERR(res->cfg_clk)) - return PTR_ERR(res->cfg_clk); - - res->master_clk = devm_clk_get(dev, "bus_master"); - if (IS_ERR(res->master_clk)) - return PTR_ERR(res->master_clk); + res->clks[0].id = "aux"; + res->clks[1].id = "cfg"; + res->clks[2].id = "bus_master"; + res->clks[3].id = "bus_slave"; - res->slave_clk = devm_clk_get(dev, "bus_slave"); - if (IS_ERR(res->slave_clk)) - return PTR_ERR(res->slave_clk); + ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks); + if (ret < 0) + return ret; return 0; } @@ -562,11 +553,7 @@ static void qcom_pcie_deinit_2_3_2(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2; - clk_disable_unprepare(res->slave_clk); - clk_disable_unprepare(res->master_clk); - clk_disable_unprepare(res->cfg_clk); - clk_disable_unprepare(res->aux_clk); - + clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); } @@ -583,43 +570,14 @@ static int qcom_pcie_init_2_3_2(struct qcom_pcie *pcie) return ret; } - ret = clk_prepare_enable(res->aux_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable aux clock\n"); - goto err_aux_clk; - } - - ret = clk_prepare_enable(res->cfg_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable cfg clock\n"); - goto err_cfg_clk; - } - - ret = clk_prepare_enable(res->master_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable master clock\n"); - goto err_master_clk; - } - - ret = clk_prepare_enable(res->slave_clk); + ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); if (ret) { - dev_err(dev, "cannot prepare/enable slave clock\n"); - goto err_slave_clk; + dev_err(dev, "cannot prepare/enable clocks\n"); + regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); + return ret; } return 0; - -err_slave_clk: - clk_disable_unprepare(res->master_clk); -err_master_clk: - clk_disable_unprepare(res->cfg_clk); -err_cfg_clk: - clk_disable_unprepare(res->aux_clk); - -err_aux_clk: - regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); - - return ret; } static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie) From patchwork Fri Mar 10 04:08:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 67220 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp680363wrd; Thu, 9 Mar 2023 20:28:39 -0800 (PST) X-Google-Smtp-Source: AK7set+VsQ9HHMOcg+LDMONB62p3cNecE18HY78tn1+FdlgwOGp5wrMrcXBGxufezJvec6U9XlyP X-Received: by 2002:a17:902:720b:b0:19e:6cd8:84de with SMTP id ba11-20020a170902720b00b0019e6cd884demr19542150plb.24.1678422519335; Thu, 09 Mar 2023 20:28:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1678422519; cv=none; d=google.com; s=arc-20160816; b=NOh9x9RUSjt5h1jcW4R2IIsju1yWR1M2FrBQIQCPwjVgSFHyuFAjmCLabMaCux2109 ZHOZWiTHDQECl5wHs5pVHGYO0IF5veFDylR+LkPPbDsSqbe6PRwo4D+17hVgrfzmyS4h JqALgPn7wRAm9tbKtvKE3m3W8XDv1vSdoDnrWP6bMs1lO/+FLjEStD8SLay5XyfRVSSG J6tYHlfRi/zRuvDdDPRuCGRrpT7geAlIBzijQRIhsWMukS5jOJoPyEVmnkLOdxBmQH7q jzdAQUZaRav3ZDyPwnULPzPyRJdGOL/ebIJbb2UmtdgwPtcSXqtiy6FSWilHhc2kY8+y LgYQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=HLaHkNbeR3pTSpm3EckvQkVoLPurUbKikH/yYKtcjD0=; b=Dr+LOKpIxXWbTIy4CgS1K/i8O7zJ54eK5BQWYHYZjXGUU0qRD/5jkdjHX6Hg/hUZVX VzOGcbe8bso19S56+1R1mdgL7z+dcCXJbYIqmTl5GK6Nw4/zrB6hwe9cbW2kUCYacCHt /xu6k8hO2xGrbdRmunyFuH56YviHWy+SNuHaITsXTWAkAxS26Tw82abxPYDiYIwfbe0D SNXMmIL8NhOYxwiFje7c4sxUw8gE49IkxMWTdkpfD9uxAcCUzXRMaOHLMKslOUMfa6XP 58Hy5zaaBXWLN43LU19eZK1hMo9yeplG4aBWiGVbD0TbX6DAkuDgjGxOCMn9HDvL3YAC fvpA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FLaiNGtf; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id c19-20020a170902c1d300b0019ad7bad651si1082622plc.4.2023.03.09.20.28.27; Thu, 09 Mar 2023 20:28:39 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FLaiNGtf; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230378AbjCJEKc (ORCPT + 99 others); Thu, 9 Mar 2023 23:10:32 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33704 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230296AbjCJEJd (ORCPT ); Thu, 9 Mar 2023 23:09:33 -0500 Received: from mail-pg1-x529.google.com (mail-pg1-x529.google.com [IPv6:2607:f8b0:4864:20::529]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1D6EFD13E3 for ; Thu, 9 Mar 2023 20:09:13 -0800 (PST) Received: by mail-pg1-x529.google.com with SMTP id q23so2354082pgt.7 for ; Thu, 09 Mar 2023 20:09:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678421350; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HLaHkNbeR3pTSpm3EckvQkVoLPurUbKikH/yYKtcjD0=; b=FLaiNGtfenzg4g6Mbm7oxjaBUpioBOFkqZ/JmfPiiqIxihchNyEXTg+/ALMzvZiOMa AIUeAJr8uz3ikL5e0P0wxSqJWoHnXinYUGye8mhttjbihQ42Q32AnOaAUXa46+PP0G0X SfRWz/X4f5HTUUMTnE6APpg7aDQ8W8SUtC/oHjG03AQC7XzNNt0V2/1h9ePUL3rp6PdG XN84d1vPslDI9lPdzAc7w9MXdqT5JGxBL8rdXCV7+6L8WUp9pAcfQCd+NaxGkRhUKpE+ rAZV81CChcrvlC4ea3AjeBBuND/ueAc2YIAKoGtUmBoGFVlEeKgTHDmMDYFyopFOkk2P euXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678421350; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HLaHkNbeR3pTSpm3EckvQkVoLPurUbKikH/yYKtcjD0=; b=J7Xb/9V7gFBVQ6kKXbUejmBYhC+S0qGjhU2Z1wjv4L77VzAz826R23q77vDEhp7YM2 S4y3fMVy1l655mVxegB8QhodkoyyhsegD0EsesHOi5cQ2s4RJ7llPHeCIxLVeU5QleDs DEEIn3h51mr73lZLPylqsdliowoAEWFodeiZadvprHQm19GHAWGIRwaAwuElhz9KVCl6 S5/VDh426mk2FhDEIDFIHIaKuI/1jwygOY5SA90NF4LHnyeFyCvbWKf24cVCQAG3pakL n2MI5UcBb517/xyIV2j/a/njXyTJrZXCZwGwTjDeYpA6TqrU/cETF+UKTDiJdjyv4Tmd Kf2g== X-Gm-Message-State: AO0yUKUX+rwBY8mpjENHXWjwraP8Mm1judLi/QgN+dF1YZW7GshnwI3G bU1KnVZ9/Io+24tHdpMiSzUt X-Received: by 2002:a62:1a43:0:b0:5a8:ecb1:bf1 with SMTP id a64-20020a621a43000000b005a8ecb10bf1mr17304947pfa.19.1678421350259; Thu, 09 Mar 2023 20:09:10 -0800 (PST) Received: from localhost.localdomain ([27.111.75.67]) by smtp.gmail.com with ESMTPSA id y26-20020aa7855a000000b0058d92d6e4ddsm361846pfn.5.2023.03.09.20.09.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Mar 2023 20:09:09 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, quic_srichara@quicinc.com, Manivannan Sadhasivam Subject: [PATCH v3 09/19] PCI: qcom: Use bulk clock APIs for handling clocks for IP rev 2.3.3 Date: Fri, 10 Mar 2023 09:38:06 +0530 Message-Id: <20230310040816.22094-10-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230310040816.22094-1-manivannan.sadhasivam@linaro.org> References: <20230310040816.22094-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759953571929008676?= X-GMAIL-MSGID: =?utf-8?q?1759953571929008676?= All the clocks are enabled and disabled at the same time. So the bulk clock APIs can be used to handle them together. This simplifies the code a lot. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 88 ++++++-------------------- 1 file changed, 20 insertions(+), 68 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 939973733a1e..6b83e3627336 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -169,6 +169,12 @@ struct qcom_pcie_resources_2_3_2 { struct regulator_bulk_data supplies[QCOM_PCIE_2_3_2_MAX_SUPPLY]; }; +#define QCOM_PCIE_2_3_3_MAX_CLOCKS 5 +struct qcom_pcie_resources_2_3_3 { + struct clk_bulk_data clks[QCOM_PCIE_2_3_3_MAX_CLOCKS]; + struct reset_control *rst[7]; +}; + #define QCOM_PCIE_2_4_0_MAX_CLOCKS 4 struct qcom_pcie_resources_2_4_0 { struct clk_bulk_data clks[QCOM_PCIE_2_4_0_MAX_CLOCKS]; @@ -187,15 +193,6 @@ struct qcom_pcie_resources_2_4_0 { struct reset_control *phy_ahb_reset; }; -struct qcom_pcie_resources_2_3_3 { - struct clk *iface; - struct clk *axi_m_clk; - struct clk *axi_s_clk; - struct clk *ahb_clk; - struct clk *aux_clk; - struct reset_control *rst[7]; -}; - /* 6 clocks typically, 7 for sm8250 */ struct qcom_pcie_resources_2_7_0 { struct clk_bulk_data clks[12]; @@ -896,26 +893,17 @@ static int qcom_pcie_get_resources_2_3_3(struct qcom_pcie *pcie) const char *rst_names[] = { "axi_m", "axi_s", "pipe", "axi_m_sticky", "sticky", "ahb", "sleep", }; + int ret; - res->iface = devm_clk_get(dev, "iface"); - if (IS_ERR(res->iface)) - return PTR_ERR(res->iface); - - res->axi_m_clk = devm_clk_get(dev, "axi_m"); - if (IS_ERR(res->axi_m_clk)) - return PTR_ERR(res->axi_m_clk); - - res->axi_s_clk = devm_clk_get(dev, "axi_s"); - if (IS_ERR(res->axi_s_clk)) - return PTR_ERR(res->axi_s_clk); - - res->ahb_clk = devm_clk_get(dev, "ahb"); - if (IS_ERR(res->ahb_clk)) - return PTR_ERR(res->ahb_clk); + res->clks[0].id = "iface"; + res->clks[1].id = "axi_m"; + res->clks[2].id = "axi_s"; + res->clks[3].id = "ahb"; + res->clks[4].id = "aux"; - res->aux_clk = devm_clk_get(dev, "aux"); - if (IS_ERR(res->aux_clk)) - return PTR_ERR(res->aux_clk); + ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks); + if (ret < 0) + return ret; for (i = 0; i < ARRAY_SIZE(rst_names); i++) { res->rst[i] = devm_reset_control_get(dev, rst_names[i]); @@ -930,11 +918,7 @@ static void qcom_pcie_deinit_2_3_3(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3; - clk_disable_unprepare(res->iface); - clk_disable_unprepare(res->axi_m_clk); - clk_disable_unprepare(res->axi_s_clk); - clk_disable_unprepare(res->ahb_clk); - clk_disable_unprepare(res->aux_clk); + clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); } static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie) @@ -969,47 +953,15 @@ static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie) */ usleep_range(2000, 2500); - ret = clk_prepare_enable(res->iface); - if (ret) { - dev_err(dev, "cannot prepare/enable core clock\n"); - goto err_clk_iface; - } - - ret = clk_prepare_enable(res->axi_m_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable core clock\n"); - goto err_clk_axi_m; - } - - ret = clk_prepare_enable(res->axi_s_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable axi slave clock\n"); - goto err_clk_axi_s; - } - - ret = clk_prepare_enable(res->ahb_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable ahb clock\n"); - goto err_clk_ahb; - } - - ret = clk_prepare_enable(res->aux_clk); + ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); if (ret) { - dev_err(dev, "cannot prepare/enable aux clock\n"); - goto err_clk_aux; + dev_err(dev, "cannot prepare/enable clocks\n"); + goto err_assert_resets; } return 0; -err_clk_aux: - clk_disable_unprepare(res->ahb_clk); -err_clk_ahb: - clk_disable_unprepare(res->axi_s_clk); -err_clk_axi_s: - clk_disable_unprepare(res->axi_m_clk); -err_clk_axi_m: - clk_disable_unprepare(res->iface); -err_clk_iface: +err_assert_resets: /* * Not checking for failure, will anyway return * the original failure in 'ret'. From patchwork Fri Mar 10 04:08:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 67211 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp679500wrd; Thu, 9 Mar 2023 20:25:15 -0800 (PST) X-Google-Smtp-Source: AK7set8DK5eVR6wqlCbhLPSE4Bz25XcrBGE11auiAmB/TrEcYbJUuhI1aruUin2FWLYVG933LTr6 X-Received: by 2002:a05:6a20:a111:b0:cc:7967:8a71 with SMTP id q17-20020a056a20a11100b000cc79678a71mr25588776pzk.59.1678422315692; Thu, 09 Mar 2023 20:25:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1678422315; cv=none; d=google.com; s=arc-20160816; b=wVvLqtlTOYvTs3OY+xmDUWOPZxEp90QKWcp+TGSKyusOZnouyYTfjpgz2Rxn8ocF70 g4tuSwSIKj8w/gG7rYq2vi+NEEvTFmICljKxQW4mB9S6jGe4I8/g3thOVRab0e3fkYLA 3X2gJB3eT5pLpbVzl6tCasBtrR+e3Pta4Tf0vmIBB0apTpsWI1RZlDiYOCwNRRXjHd2L 418Ry1TO5QLDr3Sj9+ni/E55c/zFh9uzMXiViu8zRgGPRYtAiNEEsr5wkbitdiOq7waZ Hg+j4PMpIEwtVgdXF31auq8WYMD6Nvkh6L84pjZb698IbkrYjt8S/1cUBOgM//pHcl8p MbQg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=KBoZXs7oWaG22XZASLiUsiWHjHyRIoI/eDEhjgIXc7Q=; b=n21HTvWlXZw8+c1igtD+TLvLqEfIfiNSjF4EbS+CyLIuGofnHXPYAR8/EtiVAtB9y1 iGNehtCIngU3vG+mueyBME5r2TE/uJRoxtl5BhfQy9YF9Ss2s+J5M66qTsTBpG5tiVk7 9DLPsE4fDfcwvoXooK7dJnM2NE9J2QsHhBSatTLLfEunWuFFH+pUhRyfgyHkzSYqUYKw /vYv3z/MKv27BIk9rRhY/jGWV68YDNAcBU6Z9zqYidWtJv+8HTGCJXatnwKHhrMCoUlM 8kN8cSWM4PwQe/NDLHPsj9JeAQZO0rDvkbG2Qf2ONaaNWUD7tpboCKVdHyw2Ua8j9YAs ifRg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="m+C/YrwH"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id c20-20020a634e14000000b005034a4830cbsi952260pgb.181.2023.03.09.20.25.03; Thu, 09 Mar 2023 20:25:15 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="m+C/YrwH"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230242AbjCJEKs (ORCPT + 99 others); Thu, 9 Mar 2023 23:10:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60772 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230305AbjCJEJm (ORCPT ); Thu, 9 Mar 2023 23:09:42 -0500 Received: from mail-pf1-x430.google.com (mail-pf1-x430.google.com [IPv6:2607:f8b0:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 715B0F5D29 for ; Thu, 9 Mar 2023 20:09:16 -0800 (PST) Received: by mail-pf1-x430.google.com with SMTP id bd34so2875137pfb.3 for ; Thu, 09 Mar 2023 20:09:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678421354; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KBoZXs7oWaG22XZASLiUsiWHjHyRIoI/eDEhjgIXc7Q=; b=m+C/YrwHwt2i9/sGEdK99+vcNqF83EGmJ0/z8OiTYb6lKp60bIz/sMYHQCqg5FNrbJ iSmESv8doN6a3D2ie0bXRPD76AD78QJLwNXsGzuXp7UA+XHooI4aFObllYc0LpLc9SVy jTXrF2/Ziz3ZdSJ6KZK0GQO5ia05ylEgJyx8cpO4ndxSsj0VPkHqVd7JPigEgGEw5RYc Iu27AP/FFtrxv4WOdfCpTy1Ps2f4WecyAfm6UJEkISFEJs5O1XTiRc09I14LoTXZRM+x 7HXfKPkzL4yHSIuWsVCevdXUbW+LCCfYej8orKO4hqi7lj6rC6zkc5OQOmBAQ3gWN4H+ lxPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678421354; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KBoZXs7oWaG22XZASLiUsiWHjHyRIoI/eDEhjgIXc7Q=; b=7tT46BDU/YhxeBdlllok3W9ew12chKbInviFx8nv+2xC9Px4q4tCPZhDAbpSQ0PyPn J88NADHO5Ms0zBYWy2syQwRzI9lWROOMPZnjHour2MQuEUeMBMr8xECHqV7j7jocUdwF ae31jnHfonNK5lorBidlHukZLtE086DwoCog9YpM+mw3yDwDeyKLpU2DoJXFwkxFD6eV DBos+PWXv1cD2Hr+O4csRp58iMIja4tQlwi3n50/vzjyyTqjPkO+C3fVCPBPaI3jd4Cb +jS+yCgRQsOyIxTbzobp5k1V5Svm11qsbHiqH+k6Rr9C06pfSBa5enpvnLK1y2QSKian 9TYg== X-Gm-Message-State: AO0yUKVvj5fWmOnUK/kkY8ICIX/P8w/sXfoa1/4gouJ9LAHT6gJM80Fb G8e/lGw66dmCTir4BSIDnzlh X-Received: by 2002:aa7:942a:0:b0:5e0:1073:1f25 with SMTP id y10-20020aa7942a000000b005e010731f25mr20028021pfo.7.1678421354009; Thu, 09 Mar 2023 20:09:14 -0800 (PST) Received: from localhost.localdomain ([27.111.75.67]) by smtp.gmail.com with ESMTPSA id y26-20020aa7855a000000b0058d92d6e4ddsm361846pfn.5.2023.03.09.20.09.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Mar 2023 20:09:13 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, quic_srichara@quicinc.com, Manivannan Sadhasivam Subject: [PATCH v3 10/19] PCI: qcom: Use bulk reset APIs for handling resets for IP rev 2.3.3 Date: Fri, 10 Mar 2023 09:38:07 +0530 Message-Id: <20230310040816.22094-11-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230310040816.22094-1-manivannan.sadhasivam@linaro.org> References: <20230310040816.22094-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759953358204763645?= X-GMAIL-MSGID: =?utf-8?q?1759953358204763645?= All the resets are asserted and deasserted at the same time. So the bulk reset APIs can be used to handle them together. This simplifies the code a lot. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 49 ++++++++++++-------------- 1 file changed, 23 insertions(+), 26 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 6b83e3627336..8c39fc554a89 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -170,9 +170,10 @@ struct qcom_pcie_resources_2_3_2 { }; #define QCOM_PCIE_2_3_3_MAX_CLOCKS 5 +#define QCOM_PCIE_2_3_3_MAX_RESETS 7 struct qcom_pcie_resources_2_3_3 { struct clk_bulk_data clks[QCOM_PCIE_2_3_3_MAX_CLOCKS]; - struct reset_control *rst[7]; + struct reset_control_bulk_data rst[QCOM_PCIE_2_3_3_MAX_RESETS]; }; #define QCOM_PCIE_2_4_0_MAX_CLOCKS 4 @@ -889,10 +890,6 @@ static int qcom_pcie_get_resources_2_3_3(struct qcom_pcie *pcie) struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3; struct dw_pcie *pci = pcie->pci; struct device *dev = pci->dev; - int i; - const char *rst_names[] = { "axi_m", "axi_s", "pipe", - "axi_m_sticky", "sticky", - "ahb", "sleep", }; int ret; res->clks[0].id = "iface"; @@ -905,11 +902,17 @@ static int qcom_pcie_get_resources_2_3_3(struct qcom_pcie *pcie) if (ret < 0) return ret; - for (i = 0; i < ARRAY_SIZE(rst_names); i++) { - res->rst[i] = devm_reset_control_get(dev, rst_names[i]); - if (IS_ERR(res->rst[i])) - return PTR_ERR(res->rst[i]); - } + res->rst[0].id = "axi_m"; + res->rst[1].id = "axi_s"; + res->rst[2].id = "pipe"; + res->rst[3].id = "axi_m_sticky"; + res->rst[4].id = "sticky"; + res->rst[5].id = "ahb"; + res->rst[6].id = "sleep"; + + ret = devm_reset_control_bulk_get_exclusive(dev, ARRAY_SIZE(res->rst), res->rst); + if (ret < 0) + return ret; return 0; } @@ -926,25 +929,20 @@ static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie) struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3; struct dw_pcie *pci = pcie->pci; struct device *dev = pci->dev; - int i, ret; + int ret; - for (i = 0; i < ARRAY_SIZE(res->rst); i++) { - ret = reset_control_assert(res->rst[i]); - if (ret) { - dev_err(dev, "reset #%d assert failed (%d)\n", i, ret); - return ret; - } + ret = reset_control_bulk_assert(ARRAY_SIZE(res->rst), res->rst); + if (ret < 0) { + dev_err(dev, "cannot assert resets\n"); + return ret; } usleep_range(2000, 2500); - for (i = 0; i < ARRAY_SIZE(res->rst); i++) { - ret = reset_control_deassert(res->rst[i]); - if (ret) { - dev_err(dev, "reset #%d deassert failed (%d)\n", i, - ret); - return ret; - } + ret = reset_control_bulk_deassert(ARRAY_SIZE(res->rst), res->rst); + if (ret < 0) { + dev_err(dev, "cannot deassert resets\n"); + return ret; } /* @@ -966,8 +964,7 @@ static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie) * Not checking for failure, will anyway return * the original failure in 'ret'. */ - for (i = 0; i < ARRAY_SIZE(res->rst); i++) - reset_control_assert(res->rst[i]); + reset_control_bulk_assert(ARRAY_SIZE(res->rst), res->rst); return ret; } From patchwork Fri Mar 10 04:08:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 67205 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp678618wrd; Thu, 9 Mar 2023 20:22:16 -0800 (PST) X-Google-Smtp-Source: AK7set94uObSnvEx8h1AqGmna8bkYLcmIM/JTWAzNt7owoCbfjn0ZGcG9j5HXUo0FyUxG3FWUNRG X-Received: by 2002:a05:6a20:728b:b0:b8:5881:5c3b with SMTP id o11-20020a056a20728b00b000b858815c3bmr25357182pzk.58.1678422136017; Thu, 09 Mar 2023 20:22:16 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1678422135; cv=none; d=google.com; s=arc-20160816; b=f3Hwz85FXp3Jme9PgeehS4Bsm1FOVqqbvhePnKLc/nngynxLrJi+qhQd2ys09VY2wt FgyrNF8/yBA/2Bl4HYVQ9hyJc2D3N9XiSLsJZ7rar2EEkrljVkGea99CZWZjMmcQUmqB syHI1Qw23/RDcIAxLQaqCvmroCVPI6BRkB9C1woSlStvdh/WYOWSwgwdF7+SyctasKdC qIuMlLlSj4fmKHMM61ChfWTL47S0oKyQqtjAK+YT1UeGprVrGHJpT6f17fzndSQ9CH/2 9VdRxKzT/8jMpD/vIOcq/izPePUVKGT8hyigXwjg3qa1bkIbozilGFmsj8Iz3TLqDpHc CNGw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=KfdqQH4sC3T3WUlStmaUXFOPF8SZ60hxKnyQr7AYExQ=; b=FnFeQBbpExeZgcRre2L9WgDp0C8n5aEvCJSOGFHjLGoLY8y3/oW9LZJa04ueyIdQaR ybcanBZwmgdIEESOZ8NI74jFkSBiLSWECj+w8ca9yCEEVHu20ndcq4v6gqrXbwCCo0Oz elZk2P9HrJYMOP5VYGVcrTis2uxCUXA489n+e6o3jxibEsF9RnuHx0eY1rP5RmSNa4o/ FismVh1tBM1oUEFYDaxomUYBfB/IcmsmMxO46z6vZFEhfT4/Q8xqN188tQOM7OzWvZPu zThNWcRUJwZxb5hhcMNeFLO6e9LIDMaGnluoxGX6lxex39kcP9+Ulc7WjQ4+fM3H85UB LN0w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Ctg2sWK6; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id m3-20020a632603000000b004fb6aa26999si1027021pgm.232.2023.03.09.20.22.02; Thu, 09 Mar 2023 20:22:15 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Ctg2sWK6; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230455AbjCJEKw (ORCPT + 99 others); Thu, 9 Mar 2023 23:10:52 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60890 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230248AbjCJEJr (ORCPT ); Thu, 9 Mar 2023 23:09:47 -0500 Received: from mail-pg1-x536.google.com (mail-pg1-x536.google.com [IPv6:2607:f8b0:4864:20::536]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 842A9F6026 for ; Thu, 9 Mar 2023 20:09:20 -0800 (PST) Received: by mail-pg1-x536.google.com with SMTP id 132so2335729pgh.13 for ; Thu, 09 Mar 2023 20:09:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678421360; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KfdqQH4sC3T3WUlStmaUXFOPF8SZ60hxKnyQr7AYExQ=; b=Ctg2sWK6oW78Nn1XsT8tMQY2VBL57z++ZYkg/tcFGBJ0lXLBXe1ZyTr/OmswlXNT/k TB9VRCj0HQ8tuL4i5QW8cpsq6fKFEYqvgB8NUWSgqZq5tk9QdXB+F8Qlaj4Ih0eJoB96 MkB69u26gqYHMyoJqbqb2UOF7F3sGhaMLdB+vFCZiyN2SCO8mv1ZzGch3H4Ko9LdxOT+ Q1YSVKrIJucpw8N9xMMHMnHsJ7x1XjlfKV4EnCAouh8/CBwLeAbKyi/GnGbh0TfUTCuW sai+17jkiYtUnT2UobqEnq+jh0U+s/N9iNS12y3Psh154aDlF8g/u9j7PkuKyn2S8OrK JPVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678421360; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KfdqQH4sC3T3WUlStmaUXFOPF8SZ60hxKnyQr7AYExQ=; b=sj65It1XE3AP0sTYxanoZdGwZ4W6izTKKJ5TEOIsOhJsXMqtccDN7h9I98oi8ZzioP PjIoNrPb4wvABwVEssreDRykECRY+qPcVtcUatfrq28u+zgmeRDQGjJjUQ6Pq1KDsnRp QOYElY3KfRoPOIlL69+VzOVzB/RfCwUBkQxM7sdD3xIu+Y0zmdGeNcGBjVi73sqWHlZ1 9NGxtTeNftq7IkVlNrpqYdIEo6XONysBAHm/zIr4b2gxQBQr1ZQOXWjfxym6x1jS3PAj rQ4fUBH4RjkWW0DGjGXLCujXkHlg53cK/FZ4Fq1jNrHidK+Tu8x2/M1rRXBlwQgSQmtH NOgg== X-Gm-Message-State: AO0yUKUdl2V5oXlUKU3/N+VLVYptWw9msxXEz7zctjc8MXZPKeVHqVtX pkA1FMx1YBagtfnHTaeWRc4E X-Received: by 2002:aa7:948e:0:b0:5a8:b911:a264 with SMTP id z14-20020aa7948e000000b005a8b911a264mr21161895pfk.28.1678421359673; Thu, 09 Mar 2023 20:09:19 -0800 (PST) Received: from localhost.localdomain ([27.111.75.67]) by smtp.gmail.com with ESMTPSA id y26-20020aa7855a000000b0058d92d6e4ddsm361846pfn.5.2023.03.09.20.09.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Mar 2023 20:09:17 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, quic_srichara@quicinc.com, Manivannan Sadhasivam Subject: [PATCH v3 11/19] PCI: qcom: Use bulk reset APIs for handling resets for IP rev 2.4.0 Date: Fri, 10 Mar 2023 09:38:08 +0530 Message-Id: <20230310040816.22094-12-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230310040816.22094-1-manivannan.sadhasivam@linaro.org> References: <20230310040816.22094-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759953169665995771?= X-GMAIL-MSGID: =?utf-8?q?1759953169665995771?= All the resets are asserted and deasserted at the same time. So the bulk reset APIs can be used to handle them together. This simplifies the code a lot. It should be noted that there were delays in-between the reset asserts and deasserts. But going by the config used by other revisions, those delays are not really necessary. So a single delay after all asserts and one after deasserts is used. The total number of resets supported is 12 but only ipq4019 is using all of them. Tested-by: Sricharan Ramabadhran Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 238 ++++--------------------- 1 file changed, 30 insertions(+), 208 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 8c39fc554a89..ed43e03b972f 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -176,22 +176,13 @@ struct qcom_pcie_resources_2_3_3 { struct reset_control_bulk_data rst[QCOM_PCIE_2_3_3_MAX_RESETS]; }; -#define QCOM_PCIE_2_4_0_MAX_CLOCKS 4 +#define QCOM_PCIE_2_4_0_MAX_CLOCKS 4 +#define QCOM_PCIE_2_4_0_MAX_RESETS 12 struct qcom_pcie_resources_2_4_0 { struct clk_bulk_data clks[QCOM_PCIE_2_4_0_MAX_CLOCKS]; int num_clks; - struct reset_control *axi_m_reset; - struct reset_control *axi_s_reset; - struct reset_control *pipe_reset; - struct reset_control *axi_m_vmid_reset; - struct reset_control *axi_s_xpu_reset; - struct reset_control *parf_reset; - struct reset_control *phy_reset; - struct reset_control *axi_m_sticky_reset; - struct reset_control *pipe_sticky_reset; - struct reset_control *pwr_reset; - struct reset_control *ahb_reset; - struct reset_control *phy_ahb_reset; + struct reset_control_bulk_data resets[QCOM_PCIE_2_4_0_MAX_RESETS]; + int num_resets; }; /* 6 clocks typically, 7 for sm8250 */ @@ -626,65 +617,24 @@ static int qcom_pcie_get_resources_2_4_0(struct qcom_pcie *pcie) if (ret < 0) return ret; - res->axi_m_reset = devm_reset_control_get_exclusive(dev, "axi_m"); - if (IS_ERR(res->axi_m_reset)) - return PTR_ERR(res->axi_m_reset); - - res->axi_s_reset = devm_reset_control_get_exclusive(dev, "axi_s"); - if (IS_ERR(res->axi_s_reset)) - return PTR_ERR(res->axi_s_reset); - - if (is_ipq) { - /* - * These resources relates to the PHY or are secure clocks, but - * are controlled here for IPQ4019 - */ - res->pipe_reset = devm_reset_control_get_exclusive(dev, "pipe"); - if (IS_ERR(res->pipe_reset)) - return PTR_ERR(res->pipe_reset); - - res->axi_m_vmid_reset = devm_reset_control_get_exclusive(dev, - "axi_m_vmid"); - if (IS_ERR(res->axi_m_vmid_reset)) - return PTR_ERR(res->axi_m_vmid_reset); - - res->axi_s_xpu_reset = devm_reset_control_get_exclusive(dev, - "axi_s_xpu"); - if (IS_ERR(res->axi_s_xpu_reset)) - return PTR_ERR(res->axi_s_xpu_reset); - - res->parf_reset = devm_reset_control_get_exclusive(dev, "parf"); - if (IS_ERR(res->parf_reset)) - return PTR_ERR(res->parf_reset); - - res->phy_reset = devm_reset_control_get_exclusive(dev, "phy"); - if (IS_ERR(res->phy_reset)) - return PTR_ERR(res->phy_reset); - } - - res->axi_m_sticky_reset = devm_reset_control_get_exclusive(dev, - "axi_m_sticky"); - if (IS_ERR(res->axi_m_sticky_reset)) - return PTR_ERR(res->axi_m_sticky_reset); - - res->pipe_sticky_reset = devm_reset_control_get_exclusive(dev, - "pipe_sticky"); - if (IS_ERR(res->pipe_sticky_reset)) - return PTR_ERR(res->pipe_sticky_reset); - - res->pwr_reset = devm_reset_control_get_exclusive(dev, "pwr"); - if (IS_ERR(res->pwr_reset)) - return PTR_ERR(res->pwr_reset); - - res->ahb_reset = devm_reset_control_get_exclusive(dev, "ahb"); - if (IS_ERR(res->ahb_reset)) - return PTR_ERR(res->ahb_reset); + res->resets[0].id = "axi_m"; + res->resets[1].id = "axi_s"; + res->resets[2].id = "axi_m_sticky"; + res->resets[3].id = "pipe_sticky"; + res->resets[4].id = "pwr"; + res->resets[5].id = "ahb"; + res->resets[6].id = "pipe"; + res->resets[7].id = "axi_m_vmid"; + res->resets[8].id = "axi_s_xpu"; + res->resets[9].id = "parf"; + res->resets[10].id = "phy"; + res->resets[11].id = "phy_ahb"; + + res->num_resets = is_ipq ? 12 : 6; - if (is_ipq) { - res->phy_ahb_reset = devm_reset_control_get_exclusive(dev, "phy_ahb"); - if (IS_ERR(res->phy_ahb_reset)) - return PTR_ERR(res->phy_ahb_reset); - } + ret = devm_reset_control_bulk_get_exclusive(dev, res->num_resets, res->resets); + if (ret < 0) + return ret; return 0; } @@ -693,15 +643,7 @@ static void qcom_pcie_deinit_2_4_0(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0; - reset_control_assert(res->axi_m_reset); - reset_control_assert(res->axi_s_reset); - reset_control_assert(res->pipe_reset); - reset_control_assert(res->pipe_sticky_reset); - reset_control_assert(res->phy_reset); - reset_control_assert(res->phy_ahb_reset); - reset_control_assert(res->axi_m_sticky_reset); - reset_control_assert(res->pwr_reset); - reset_control_assert(res->ahb_reset); + reset_control_bulk_assert(res->num_resets, res->resets); clk_bulk_disable_unprepare(res->num_clks, res->clks); } @@ -712,149 +654,29 @@ static int qcom_pcie_init_2_4_0(struct qcom_pcie *pcie) struct device *dev = pci->dev; int ret; - ret = reset_control_assert(res->axi_m_reset); - if (ret) { - dev_err(dev, "cannot assert axi master reset\n"); - return ret; - } - - ret = reset_control_assert(res->axi_s_reset); - if (ret) { - dev_err(dev, "cannot assert axi slave reset\n"); - return ret; - } - - usleep_range(10000, 12000); - - ret = reset_control_assert(res->pipe_reset); - if (ret) { - dev_err(dev, "cannot assert pipe reset\n"); - return ret; - } - - ret = reset_control_assert(res->pipe_sticky_reset); - if (ret) { - dev_err(dev, "cannot assert pipe sticky reset\n"); - return ret; - } - - ret = reset_control_assert(res->phy_reset); - if (ret) { - dev_err(dev, "cannot assert phy reset\n"); - return ret; - } - - ret = reset_control_assert(res->phy_ahb_reset); - if (ret) { - dev_err(dev, "cannot assert phy ahb reset\n"); + ret = reset_control_bulk_assert(res->num_resets, res->resets); + if (ret < 0) { + dev_err(dev, "cannot assert resets\n"); return ret; } usleep_range(10000, 12000); - ret = reset_control_assert(res->axi_m_sticky_reset); - if (ret) { - dev_err(dev, "cannot assert axi master sticky reset\n"); - return ret; - } - - ret = reset_control_assert(res->pwr_reset); - if (ret) { - dev_err(dev, "cannot assert power reset\n"); - return ret; - } - - ret = reset_control_assert(res->ahb_reset); - if (ret) { - dev_err(dev, "cannot assert ahb reset\n"); + ret = reset_control_bulk_deassert(res->num_resets, res->resets); + if (ret < 0) { + dev_err(dev, "cannot deassert resets\n"); return ret; } usleep_range(10000, 12000); - ret = reset_control_deassert(res->phy_ahb_reset); + ret = clk_bulk_prepare_enable(res->num_clks, res->clks); if (ret) { - dev_err(dev, "cannot deassert phy ahb reset\n"); + reset_control_bulk_assert(res->num_resets, res->resets); return ret; } - ret = reset_control_deassert(res->phy_reset); - if (ret) { - dev_err(dev, "cannot deassert phy reset\n"); - goto err_rst_phy; - } - - ret = reset_control_deassert(res->pipe_reset); - if (ret) { - dev_err(dev, "cannot deassert pipe reset\n"); - goto err_rst_pipe; - } - - ret = reset_control_deassert(res->pipe_sticky_reset); - if (ret) { - dev_err(dev, "cannot deassert pipe sticky reset\n"); - goto err_rst_pipe_sticky; - } - - usleep_range(10000, 12000); - - ret = reset_control_deassert(res->axi_m_reset); - if (ret) { - dev_err(dev, "cannot deassert axi master reset\n"); - goto err_rst_axi_m; - } - - ret = reset_control_deassert(res->axi_m_sticky_reset); - if (ret) { - dev_err(dev, "cannot deassert axi master sticky reset\n"); - goto err_rst_axi_m_sticky; - } - - ret = reset_control_deassert(res->axi_s_reset); - if (ret) { - dev_err(dev, "cannot deassert axi slave reset\n"); - goto err_rst_axi_s; - } - - ret = reset_control_deassert(res->pwr_reset); - if (ret) { - dev_err(dev, "cannot deassert power reset\n"); - goto err_rst_pwr; - } - - ret = reset_control_deassert(res->ahb_reset); - if (ret) { - dev_err(dev, "cannot deassert ahb reset\n"); - goto err_rst_ahb; - } - - usleep_range(10000, 12000); - - ret = clk_bulk_prepare_enable(res->num_clks, res->clks); - if (ret) - goto err_clks; - return 0; - -err_clks: - reset_control_assert(res->ahb_reset); -err_rst_ahb: - reset_control_assert(res->pwr_reset); -err_rst_pwr: - reset_control_assert(res->axi_s_reset); -err_rst_axi_s: - reset_control_assert(res->axi_m_sticky_reset); -err_rst_axi_m_sticky: - reset_control_assert(res->axi_m_reset); -err_rst_axi_m: - reset_control_assert(res->pipe_sticky_reset); -err_rst_pipe_sticky: - reset_control_assert(res->pipe_reset); -err_rst_pipe: - reset_control_assert(res->phy_reset); -err_rst_phy: - reset_control_assert(res->phy_ahb_reset); - return ret; } static int qcom_pcie_post_init_2_4_0(struct qcom_pcie *pcie) From patchwork Fri Mar 10 04:08:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 67215 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp679977wrd; Thu, 9 Mar 2023 20:27:04 -0800 (PST) X-Google-Smtp-Source: AK7set+LNeB19qPsmaeUAoX4J0XF064XB5FpH5Zct+190xjlKJcBLrmnJgWSnLRkJ0dGsRJMjvoK X-Received: by 2002:a62:7b48:0:b0:5ad:8c9:2c9a with SMTP id w69-20020a627b48000000b005ad08c92c9amr899771pfc.11.1678422424524; Thu, 09 Mar 2023 20:27:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1678422424; cv=none; d=google.com; s=arc-20160816; b=ED2CpZGOY1dbhhmjNnsZftgZnFdHV9Z54uIuvLbvXoWhHRTUBsGpdCm4kHAJHfk5So z5IViQx/NMQP/AxSZo8oXbPEMtsDSV/m7WBnV9Bxl3wwof2kcLHr74+yzi7dPTmOZOKd iP2lpwI59PTBQM6rgNPW6gmBXZAcYJK4+YSdTANtd37s7PCLeDoLh7CtZ4dcPbhLTG3W FCn7MimI1fp5KcftbhbfjYfhMcMCfELlz4xfl1Ifz9jv9LHMArzptiFxjeMzu2sTuPLd mK5axQ+jGSSMi/5I2mjYLy98WlimZ85eGBxVOqCXiNj8SPyLJmB38fAYEdE5ZSrj8atq xTEg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=gtO470wsQrdefT/eZbqt8rDglQCA1uZJNkLG9oF8ql8=; b=kbaMiZNQJccKdDhuGMGuc03Ibc4/AYygvx6UKaNgvNfhF6T0wpe+KIBUA2rgGHkozB scGW1BGPSLcg28dysu03k2Fokg7zSwFOu1f48FTMLA7B78P9P95QIFu0Ce1oITt0BEpE k7bWzE5Uyp1HvMuhExlP7VtZPlq65HRr5e1gZOoxUvZz8QWdfiBULcid1wCSwhJ8oZ5z 7x4jLF2R3oHSJY70O/u8uxvCFu+AP0MuLyWjuoc2eiYB0MEnNg5iWQSchcZH0NqvLihV tlMpiqWt2zonaKJs/cDDO9xw8bm8H7ut/h1DAsajwZHJhhN2izV03aD1+fP1VardG5ut GEnA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LrICSFqa; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id j7-20020a625507000000b0059038315e75si1051293pfb.33.2023.03.09.20.26.51; Thu, 09 Mar 2023 20:27:04 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LrICSFqa; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230492AbjCJELP (ORCPT + 99 others); Thu, 9 Mar 2023 23:11:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33388 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230479AbjCJEKE (ORCPT ); Thu, 9 Mar 2023 23:10:04 -0500 Received: from mail-pg1-x529.google.com (mail-pg1-x529.google.com [IPv6:2607:f8b0:4864:20::529]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 31993F2F92 for ; Thu, 9 Mar 2023 20:09:29 -0800 (PST) Received: by mail-pg1-x529.google.com with SMTP id p6so2384110pga.0 for ; Thu, 09 Mar 2023 20:09:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678421363; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gtO470wsQrdefT/eZbqt8rDglQCA1uZJNkLG9oF8ql8=; b=LrICSFqab9sa220RDrempiZSjRDQplgHv3z1kbyoEOT/ijTMZbLM4D1iwR2/pV4kvT 6rxEAOX1omwOTymgO3kQ0OScjnrpAvz5EKNFlZCBsibJqbuki3gsXUN/yRp/yXxzWUFI U+GilDA8TOvGpjqGcTNgnUkfQxDY+ysZAuD00bKyJSiJTegN3OqIjggofI5xVYY8FWii 9mBDYrsTssG08AKNvvoHaDkT1wOIdHlRYW6HADTWruc+comsXn90TdrdroFtjXUFS1NV nk84plpj2drw4dMxYjNZ9kWMRyAGkHr7fHTcTHUhaKYdEdI5rl0rEYDw0QDZg+H2m2k0 fwhw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678421363; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gtO470wsQrdefT/eZbqt8rDglQCA1uZJNkLG9oF8ql8=; b=Vok/piaewnF9TldxK9y+QsSfKbD9cBbdlQj6IgbebwgTClMJ7h2EAtQqGcWyoUdR7l yfCR0WVhTE9wF+FpPuXohmRZVJObcJrRtO5HAvXwp89oo3qd/7v/fYy8ft8v16Q9Jswx dcaAy3gpswESRh6rdY+Dx8pQcyRPpgig1B4SiPyeITwXV45Jk8N9IKXSPaQj2ZrVQh8j D/a0Jl+1KOQ2W+zHI3Zmmd7KgcXkHKenbntsqtyXaFjr0cXjE5O6QquSiaZDxMrJ2gCk A7y5GtTkg3jxi1fGIja0ShU+hqbaYyEkZlNPKOLG5ozJzu81HQ8WjgXYei2ptWfx3klk Grcw== X-Gm-Message-State: AO0yUKVTyKhKBB13NDRPmUszvBKx0zbv/j8tFYtl37L5KwXx6+Vuru2l N6v/T+gOoFht4RPZDWtTS0nK X-Received: by 2002:a05:6a00:4004:b0:5a8:4c8a:2ce4 with SMTP id by4-20020a056a00400400b005a84c8a2ce4mr608223pfb.3.1678421363481; Thu, 09 Mar 2023 20:09:23 -0800 (PST) Received: from localhost.localdomain ([27.111.75.67]) by smtp.gmail.com with ESMTPSA id y26-20020aa7855a000000b0058d92d6e4ddsm361846pfn.5.2023.03.09.20.09.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Mar 2023 20:09:23 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, quic_srichara@quicinc.com, Manivannan Sadhasivam Subject: [PATCH v3 12/19] PCI: qcom: Use macros for defining total no. of clocks & supplies Date: Fri, 10 Mar 2023 09:38:09 +0530 Message-Id: <20230310040816.22094-13-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230310040816.22094-1-manivannan.sadhasivam@linaro.org> References: <20230310040816.22094-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759953472039499027?= X-GMAIL-MSGID: =?utf-8?q?1759953472039499027?= To keep uniformity, let's use macros to define the total number of clocks and supplies in qcom_pcie_resources_{2_7_0/2_9_0} structs. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index ed43e03b972f..e1180c84f0fa 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -185,16 +185,18 @@ struct qcom_pcie_resources_2_4_0 { int num_resets; }; -/* 6 clocks typically, 7 for sm8250 */ +#define QCOM_PCIE_2_7_0_MAX_CLOCKS 12 +#define QCOM_PCIE_2_7_0_MAX_SUPPLIES 2 struct qcom_pcie_resources_2_7_0 { - struct clk_bulk_data clks[12]; + struct clk_bulk_data clks[QCOM_PCIE_2_7_0_MAX_CLOCKS]; int num_clks; - struct regulator_bulk_data supplies[2]; + struct regulator_bulk_data supplies[QCOM_PCIE_2_7_0_MAX_SUPPLIES]; struct reset_control *pci_reset; }; +#define QCOM_PCIE_2_9_0_MAX_CLOCKS 5 struct qcom_pcie_resources_2_9_0 { - struct clk_bulk_data clks[5]; + struct clk_bulk_data clks[QCOM_PCIE_2_9_0_MAX_CLOCKS]; struct reset_control *rst; }; From patchwork Fri Mar 10 04:08:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 67214 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp679753wrd; Thu, 9 Mar 2023 20:26:14 -0800 (PST) X-Google-Smtp-Source: AK7set/emfYe3QM29/VDGP04xzyNyzNukUXW5x2loHETyYJpeb12OPwXpsIfa3FgA2RKuH44lSzQ X-Received: by 2002:a17:903:2349:b0:19c:e046:d906 with SMTP id c9-20020a170903234900b0019ce046d906mr983661plh.24.1678422373856; Thu, 09 Mar 2023 20:26:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1678422373; cv=none; d=google.com; s=arc-20160816; b=YN7ejkl+ixtfaug7toNmvABt9SWdYoPgChDMTo5ckMdEM8A9MKJJCRIf2Sx4lEvht8 WZnMAhclkvuaVgGqTw0oLM/1cOXJA6LZB5pneXjThOTOVoukfT7+rBubgdjLSU0LV0Cs D1mwD1Ocu2RocW88ubHuHfxFEIGYUX8X6Z1N7epuSJlKipr8uAjmgBYv61fLZ9xUhNVj qWWa4woL3gpdHyj1cv880s848Pwy8/yGymlG/wxg5FrPLET3Re1fx9npi4htDlwhYRua 7HFytu3BxGc5PGllUiGAclaYj7lLs2RVdTqpeFyL1mGCv75UWwCdnaJHMAKFiOQFG5pM mZwg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=TwnOfx0fvyN0EVTsIZtRO7GfnRR3nR2D8SXkkwhJ4Fg=; b=GsjYiHt7hj33ExDqNi6GPuMWnxpuplLszxjQAcaBNPyPdCoOmpLbZSmuD2VwQdJrRu CMm9cu16o/f9nosx2/6kqbXW70oJ8bpCJXbcDCDJPVrDr/dCOgNDOwUwfrP7qWgOueQk Jki80sLzIIW9Tf2uoe/JmLoal7zH0fXuCHNJVEcLRSuBsGlnbv3zhRiB5yjQaEoLC2F0 okqtG40sM+1w77EBHXjqmnqzV7nnNM75nrUXdDGLCUKea68hOZt/7jZxU/3C2wkxEFdG FuNf84cp/m4+qFnBm4yC2fpJGHWNrokZjTFKl4DJx6wOcR/sVD9nWx7QjW1ssJZulnV8 bh4w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=o5wWWCRw; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id c19-20020a170902c1d300b0019ad7bad651si1082622plc.4.2023.03.09.20.26.01; Thu, 09 Mar 2023 20:26:13 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=o5wWWCRw; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230501AbjCJELe (ORCPT + 99 others); Thu, 9 Mar 2023 23:11:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33592 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230361AbjCJEK3 (ORCPT ); Thu, 9 Mar 2023 23:10:29 -0500 Received: from mail-pj1-x1036.google.com (mail-pj1-x1036.google.com [IPv6:2607:f8b0:4864:20::1036]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8345D102B79 for ; Thu, 9 Mar 2023 20:09:35 -0800 (PST) Received: by mail-pj1-x1036.google.com with SMTP id x20-20020a17090a8a9400b00233ba727724so7067173pjn.1 for ; Thu, 09 Mar 2023 20:09:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678421367; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TwnOfx0fvyN0EVTsIZtRO7GfnRR3nR2D8SXkkwhJ4Fg=; b=o5wWWCRwfCXHSDaJxzI5Mf0pLfNmuyFz7riyLzkoGymmZQfSSsmTjU+/5Mlp9ssne7 Ep95fbLjk6WW5RtwHDocEkWwpq0QL/sl0s+Nagd/8gKTsbf2G1h8Jn+RAqLWb1izc3uj NdVKgXjonyb+mTtpUY8PqCTMqgqcIX9/evmnxS1uoECVYoutQOT1Vfd9X1atz3pF6sny OjoTlHqIEY2s5Huxk/GYz8kgINIs0s6bbbzxw4A/QFa3Yq/MFcNHyQQmWalZcVXxVW5O mwADWZN5YQyi6s807g6yhpnxeCCYtSbmlwiuPbCIUxqSDqQfoPCxrWmyvOWy4MROTLnm OJ3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678421367; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TwnOfx0fvyN0EVTsIZtRO7GfnRR3nR2D8SXkkwhJ4Fg=; b=Vm9UlFWPI3je+WweFiFkJf9ysLUQA4LA4IWaTUY4QRoWcoc8O9C0sP4SQHpiRhVfQi D78Ov/Af6tOEETXVSb/NKkzqJPg/fH3j+PkB6SN5G3RlXRL/XYIyaoMtENIpaspIazh6 I+wX8FA6fLygX9tTMF338/kFknIso/VDQ2ouFvyCeotUMnBIBjZ6C//yldSDu270Bwcm U7ZTz8YIAgQcvFw3nR2I+fBVGUT5iOrBYkSmDk6vqnrbnEw3Pf/fIsIVvZE67jRkHKK7 Jimf+8/RZWHjvDr5Bkcl/lq0WQdpsd7Zrh9KgkKDtyQVIU5AfMe7pdlauR/GxqgNWhL8 NcGg== X-Gm-Message-State: AO0yUKWSHtkaA06KUJxSZ/llORh9Dqnfe+dbJvDsSx5hzrrs4UDHRp5E 5wM2Cy79c1QssltOuR3oGsQd X-Received: by 2002:a05:6a21:338f:b0:cb:b92c:b46e with SMTP id yy15-20020a056a21338f00b000cbb92cb46emr1056989pzb.9.1678421367512; Thu, 09 Mar 2023 20:09:27 -0800 (PST) Received: from localhost.localdomain ([27.111.75.67]) by smtp.gmail.com with ESMTPSA id y26-20020aa7855a000000b0058d92d6e4ddsm361846pfn.5.2023.03.09.20.09.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Mar 2023 20:09:26 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, quic_srichara@quicinc.com, Manivannan Sadhasivam Subject: [PATCH v3 13/19] PCI: qcom: Rename qcom_pcie_config_sid_sm8250() to reflect IP version Date: Fri, 10 Mar 2023 09:38:10 +0530 Message-Id: <20230310040816.22094-14-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230310040816.22094-1-manivannan.sadhasivam@linaro.org> References: <20230310040816.22094-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759953418847609152?= X-GMAIL-MSGID: =?utf-8?q?1759953418847609152?= qcom_pcie_config_sid_sm8250() function no longer applies only to SM8250. So let's rename it to reflect the actual IP version and also move its definition to keep it sorted as per IP revisions. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 144 ++++++++++++------------- 1 file changed, 72 insertions(+), 72 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index e1180c84f0fa..52f09ee8dd48 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -963,6 +963,77 @@ static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie) regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); } +static int qcom_pcie_config_sid_1_9_0(struct qcom_pcie *pcie) +{ + /* iommu map structure */ + struct { + u32 bdf; + u32 phandle; + u32 smmu_sid; + u32 smmu_sid_len; + } *map; + void __iomem *bdf_to_sid_base = pcie->parf + PARF_BDF_TO_SID_TABLE_N; + struct device *dev = pcie->pci->dev; + u8 qcom_pcie_crc8_table[CRC8_TABLE_SIZE]; + int i, nr_map, size = 0; + u32 smmu_sid_base; + + of_get_property(dev->of_node, "iommu-map", &size); + if (!size) + return 0; + + map = kzalloc(size, GFP_KERNEL); + if (!map) + return -ENOMEM; + + of_property_read_u32_array(dev->of_node, + "iommu-map", (u32 *)map, size / sizeof(u32)); + + nr_map = size / (sizeof(*map)); + + crc8_populate_msb(qcom_pcie_crc8_table, QCOM_PCIE_CRC8_POLYNOMIAL); + + /* Registers need to be zero out first */ + memset_io(bdf_to_sid_base, 0, CRC8_TABLE_SIZE * sizeof(u32)); + + /* Extract the SMMU SID base from the first entry of iommu-map */ + smmu_sid_base = map[0].smmu_sid; + + /* Look for an available entry to hold the mapping */ + for (i = 0; i < nr_map; i++) { + __be16 bdf_be = cpu_to_be16(map[i].bdf); + u32 val; + u8 hash; + + hash = crc8(qcom_pcie_crc8_table, (u8 *)&bdf_be, sizeof(bdf_be), + 0); + + val = readl(bdf_to_sid_base + hash * sizeof(u32)); + + /* If the register is already populated, look for next available entry */ + while (val) { + u8 current_hash = hash++; + u8 next_mask = 0xff; + + /* If NEXT field is NULL then update it with next hash */ + if (!(val & next_mask)) { + val |= (u32)hash; + writel(val, bdf_to_sid_base + current_hash * sizeof(u32)); + } + + val = readl(bdf_to_sid_base + hash * sizeof(u32)); + } + + /* BDF [31:16] | SID [15:8] | NEXT [7:0] */ + val = map[i].bdf << 16 | (map[i].smmu_sid - smmu_sid_base) << 8 | 0; + writel(val, bdf_to_sid_base + hash * sizeof(u32)); + } + + kfree(map); + + return 0; +} + static int qcom_pcie_get_resources_2_9_0(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0; @@ -1077,77 +1148,6 @@ static int qcom_pcie_link_up(struct dw_pcie *pci) return !!(val & PCI_EXP_LNKSTA_DLLLA); } -static int qcom_pcie_config_sid_sm8250(struct qcom_pcie *pcie) -{ - /* iommu map structure */ - struct { - u32 bdf; - u32 phandle; - u32 smmu_sid; - u32 smmu_sid_len; - } *map; - void __iomem *bdf_to_sid_base = pcie->parf + PARF_BDF_TO_SID_TABLE_N; - struct device *dev = pcie->pci->dev; - u8 qcom_pcie_crc8_table[CRC8_TABLE_SIZE]; - int i, nr_map, size = 0; - u32 smmu_sid_base; - - of_get_property(dev->of_node, "iommu-map", &size); - if (!size) - return 0; - - map = kzalloc(size, GFP_KERNEL); - if (!map) - return -ENOMEM; - - of_property_read_u32_array(dev->of_node, - "iommu-map", (u32 *)map, size / sizeof(u32)); - - nr_map = size / (sizeof(*map)); - - crc8_populate_msb(qcom_pcie_crc8_table, QCOM_PCIE_CRC8_POLYNOMIAL); - - /* Registers need to be zero out first */ - memset_io(bdf_to_sid_base, 0, CRC8_TABLE_SIZE * sizeof(u32)); - - /* Extract the SMMU SID base from the first entry of iommu-map */ - smmu_sid_base = map[0].smmu_sid; - - /* Look for an available entry to hold the mapping */ - for (i = 0; i < nr_map; i++) { - __be16 bdf_be = cpu_to_be16(map[i].bdf); - u32 val; - u8 hash; - - hash = crc8(qcom_pcie_crc8_table, (u8 *)&bdf_be, sizeof(bdf_be), - 0); - - val = readl(bdf_to_sid_base + hash * sizeof(u32)); - - /* If the register is already populated, look for next available entry */ - while (val) { - u8 current_hash = hash++; - u8 next_mask = 0xff; - - /* If NEXT field is NULL then update it with next hash */ - if (!(val & next_mask)) { - val |= (u32)hash; - writel(val, bdf_to_sid_base + current_hash * sizeof(u32)); - } - - val = readl(bdf_to_sid_base + hash * sizeof(u32)); - } - - /* BDF [31:16] | SID [15:8] | NEXT [7:0] */ - val = map[i].bdf << 16 | (map[i].smmu_sid - smmu_sid_base) << 8 | 0; - writel(val, bdf_to_sid_base + hash * sizeof(u32)); - } - - kfree(map); - - return 0; -} - static int qcom_pcie_host_init(struct dw_pcie_rp *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); @@ -1268,7 +1268,7 @@ static const struct qcom_pcie_ops ops_1_9_0 = { .init = qcom_pcie_init_2_7_0, .deinit = qcom_pcie_deinit_2_7_0, .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, - .config_sid = qcom_pcie_config_sid_sm8250, + .config_sid = qcom_pcie_config_sid_1_9_0, }; /* Qcom IP rev.: 2.9.0 Synopsys IP rev.: 5.00a */ From patchwork Fri Mar 10 04:08:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 67219 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp680278wrd; Thu, 9 Mar 2023 20:28:23 -0800 (PST) X-Google-Smtp-Source: AK7set/mEkM05DuS0mCsRNha0PWHDFTiLHjzWpGtN3SL5mN4j3L448bwvo1VC9l4lyrI4L83XW00 X-Received: by 2002:a17:903:2601:b0:19d:1fe3:4941 with SMTP id jd1-20020a170903260100b0019d1fe34941mr21064717plb.2.1678422503469; Thu, 09 Mar 2023 20:28:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1678422503; cv=none; d=google.com; s=arc-20160816; b=XjsnEr26z8sCNwo+rO0EI0je5MKPYyMza30In6rakU5eKyhaz2uyI94KHQcxHQlHRh 3z8oflIlzB3JN7nWeJc2T1lYalB1/0zkD94fpMX3PAnbEzZyCpBsyULjbbvQ7sMGHEK2 2QsVkYKsIL6gyQf42DBa3YM5Y+0wNFpxv4SHVwVMnejDSjxPRHXlABfZD+R4zZq7YYn7 DjkVmXu+H0mSpWMxS4vaIMZYS1mqx9rtEbJ6dOh0J+3Unu9ENFaG2LZIoaiRzP5X2Uzh 8pivbOMWc8IrvTAtdb2g133F1OgSQ3LTPcwg9sAko63rwxVf4pYQBoIzZAHpX465kpTP 5WzQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=5EYpDut5qXdF8PJg7sJ4kHxpp0TN8JiS9nsevzfwY0E=; b=LW/3T77CH585hirUpdknSo7ZTw22Lt8CKGRYJp6hhCVk3uhadP944gV0jnCzcBXr5g RMP307GwvaBkpJH+I7ZF99/KvUQfSOK7GAgzX1KWf+MjWoZNKmTrlXDHe/16fL6Y7E3O qTis3TC77pUGmcTilJvTQflPdEHbMOJS4gYuNlKYzr3xfXqZetmwlp9gGtTXsnqmeojI pi46yQFI1HUOuWILEBb67J4XFGu8uF7ofLJUNvz06Ae9vzJv4spun+tTVorBT1g7z0GE 90UI5dovACNXiNMtfqV6W5MHvE0BOyyMAeFrgESWF3WoXjdldCYjO7E7MXD/FghaXoyA y54A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=wmdZ32gS; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id ji17-20020a170903325100b0019eaa00e5cesi1043382plb.270.2023.03.09.20.28.10; Thu, 09 Mar 2023 20:28:23 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=wmdZ32gS; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230513AbjCJELk (ORCPT + 99 others); Thu, 9 Mar 2023 23:11:40 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33762 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230297AbjCJEKb (ORCPT ); Thu, 9 Mar 2023 23:10:31 -0500 Received: from mail-pl1-x62d.google.com (mail-pl1-x62d.google.com [IPv6:2607:f8b0:4864:20::62d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DDED0EA023 for ; Thu, 9 Mar 2023 20:09:37 -0800 (PST) Received: by mail-pl1-x62d.google.com with SMTP id i10so4294715plr.9 for ; Thu, 09 Mar 2023 20:09:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678421371; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5EYpDut5qXdF8PJg7sJ4kHxpp0TN8JiS9nsevzfwY0E=; b=wmdZ32gSVCiRRr4O74cEm3Ao939vIeHxhN/ziyCMfrkXbpPhBdLtJUdythTAweA6DD lzD5zCJSJxMNaEn2OgIxRKYJ7Wk83k1gPLuqZaWFvjhxoipHk0nHHtnpqSMjuIpL30o9 seqvgpIs+kTIKUE4a0pfFNCNe2+X7O9x/MCeM3+EjqpdWD3YVtH5ctOXA/CvREeH33Xy ZAmWpXN1pZhD9NcnGHQuOJ1TWy55ZTMq0k2Q7B5kLfRjJDeZT/AC9+zgm0Eib3STTaqm OHjDHD7Ul70Nk8ol1Dp5IFHX0bpTFVnlKVtknSjaHiuVLtSqqQ3ZadiI6m4E+ASI8qpA Oimw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678421371; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5EYpDut5qXdF8PJg7sJ4kHxpp0TN8JiS9nsevzfwY0E=; b=HAILfx1V7bCOJbgRjoW9v3fznl8a4WzxQNyvcSvLNa0lzYx4czYQo+X/2oe9rRRoIC 2/txUKK2FYoCrnovoNUdMOUfgKSeoLu3JHqcop2L98tkC/PCmjjzPjcuZaiJ41fz9IfZ wvVHRZeApHfko/ks218eaHmnZCV4MKdtGsCCyTKLkPgu8qe198DbAH83viCjdzrrlO4B 8UXhx8o00iSyvTLC0rQM+n4D7KChojJnR2QwA6jhk15LZE/8IiSUgnIamYsMXRGTVWXX /nqo++Y8b7ouK9JIVJpjcHbcxJfmyta9RNXeceB4YpMK8DvCCt0XA9FgsePKBssuEZZE oNpQ== X-Gm-Message-State: AO0yUKVL7s8aV6wyAvSlbMxnYO6Eq9yqa5WNzPSf9gvhWPsS6FbtIrpg MZaGfQaZXhzkg3hzL5ZV6qtN/VQ5qviAa59wfQ== X-Received: by 2002:a05:6a20:a8a5:b0:cb:a64b:6e1b with SMTP id ca37-20020a056a20a8a500b000cba64b6e1bmr19814986pzb.58.1678421371170; Thu, 09 Mar 2023 20:09:31 -0800 (PST) Received: from localhost.localdomain ([27.111.75.67]) by smtp.gmail.com with ESMTPSA id y26-20020aa7855a000000b0058d92d6e4ddsm361846pfn.5.2023.03.09.20.09.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Mar 2023 20:09:30 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, quic_srichara@quicinc.com, Manivannan Sadhasivam Subject: [PATCH v3 14/19] dt-bindings: PCI: qcom: Add "mhi" register region to supported SoCs Date: Fri, 10 Mar 2023 09:38:11 +0530 Message-Id: <20230310040816.22094-15-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230310040816.22094-1-manivannan.sadhasivam@linaro.org> References: <20230310040816.22094-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759953555188063189?= X-GMAIL-MSGID: =?utf-8?q?1759953555188063189?= "mhi" register region contains the MHI registers that could be used by the PCIe controller drivers to get debug information like PCIe link transition counts on newer SoCs. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index fb32c43dd12d..ecbb0f9efa21 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -44,11 +44,11 @@ properties: reg: minItems: 4 - maxItems: 5 + maxItems: 6 reg-names: minItems: 4 - maxItems: 5 + maxItems: 6 interrupts: minItems: 1 @@ -185,13 +185,15 @@ allOf: properties: reg: minItems: 4 - maxItems: 4 + maxItems: 5 reg-names: + minItems: 4 items: - const: parf # Qualcomm specific registers - const: dbi # DesignWare PCIe registers - const: elbi # External local bus interface registers - const: config # PCIe configuration space + - const: mhi # MHI registers - if: properties: @@ -209,14 +211,16 @@ allOf: properties: reg: minItems: 5 - maxItems: 5 + maxItems: 6 reg-names: + minItems: 5 items: - const: parf # Qualcomm specific registers - const: dbi # DesignWare PCIe registers - const: elbi # External local bus interface registers - const: atu # ATU address space - const: config # PCIe configuration space + - const: mhi # MHI registers - if: properties: From patchwork Fri Mar 10 04:08:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 67206 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp678628wrd; Thu, 9 Mar 2023 20:22:18 -0800 (PST) X-Google-Smtp-Source: AK7set+RZ/4vHFxXpm5kSqpRtFhOjctKMmbnix3aBOpqD5P0r7b3Wx+sOENsB0DaMEVxlBHCfjGS X-Received: by 2002:a17:90b:3b90:b0:234:b35b:f905 with SMTP id pc16-20020a17090b3b9000b00234b35bf905mr26172897pjb.2.1678422138202; Thu, 09 Mar 2023 20:22:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1678422138; cv=none; d=google.com; s=arc-20160816; b=G5kXVVMBvrvoD7mlWL4MrvFBQ99YKd/WT6SirAOCK+6QC3FIG6UXxZ/lcrwv56bJMQ KFuo6lfxpATk+/txQb+Oao+wGlceECKZjta4hqJ56hBGMOitKCX8SIZxD+KtBKlU48VE 9ddz8Z+8mMWvUqaW0qM7B7lFsVGaNa+t6wr4iQuMjYedB0D5CyuF0UR54OGJMAtEiHXh nfC6LGn9NNO9WDO3hrOF1O63L/vDGc5lUBVy/Jxl52BtF8PauWa4KZJRje+k9AzxC8Au FFxdnjcEDzfaBC5Zn8mbQh2JjjLKjiw89UbRwEeodBZF1muyj+ayOlVo88Mklg1+znQj xS+g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=azG6rPTW4OW7MpxRM4BYmIziHm2wpGO0S0WPmax4BIQ=; b=hGwZ/T9jUaGYj3OcUnryStvg8eUBHQI6wkKsX/scwt3AqhpXpqsrDOZ5PatA3Lk238 tJGovjRBW7tH661s0x1/PTS63sx1hQfAXSeCkFRNXH/2rjP2Cim2oMkh1auzHsQ3uDM3 dVU8X9+/ftTuhUqnEYoG3DmXg1O1VgeOn7ZPAUI+q7JXlftKVsIrKK/hK5G2soRZE5se 9XJqOtUh0r4IwNqwV+xNcAzgEsKzDaqNPR2b4ZJD72z27ODC8azOdanuUcHIaupRqYey KWINxigQr2GFOjro5GAtUPrIfMMGQ+0xqyUXbf6m0Ix4y224cpZRYC2Ym7ibWpDSNtMW Lyww== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=T838p+Gk; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id o2-20020a17090a678200b00234b66e3df3si846140pjj.153.2023.03.09.20.22.05; Thu, 09 Mar 2023 20:22:18 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=T838p+Gk; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231128AbjCJELy (ORCPT + 99 others); Thu, 9 Mar 2023 23:11:54 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60820 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230407AbjCJEKp (ORCPT ); Thu, 9 Mar 2023 23:10:45 -0500 Received: from mail-pg1-x532.google.com (mail-pg1-x532.google.com [IPv6:2607:f8b0:4864:20::532]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 40B25103ED3 for ; Thu, 9 Mar 2023 20:09:41 -0800 (PST) Received: by mail-pg1-x532.google.com with SMTP id bn17so2344050pgb.10 for ; Thu, 09 Mar 2023 20:09:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678421375; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=azG6rPTW4OW7MpxRM4BYmIziHm2wpGO0S0WPmax4BIQ=; b=T838p+Gk/zYv4/Qevbgh+Dc7eZumK6aAMJLP/Z15+n29Gc5V+aodL4yew5LU25+JUr cvVvBkeOLmKXSMPcLJ3jvvHdE6q11Ml8iUw5zmnRGPPHki3j72e/pTojc9Cp5Dk7p+z8 SAvYgUhlJkJhgBeXwzeLc+jqmed25ZnhigQlb4sI3uEUUFsyXDCkJ5A0rgueFGeF/170 RC7AYR2Nz9f2qnLSIWgp4PYjLkP8fBuFh4S4RVnQlzX0+jHZY4b7GkzqG5cjnnEUXLNB JDtE3O9hRDBX553kJrMBIGZIopzvggE4DhGBYdK67YcPYN2jX5mC3UzzTpFWf8zzvlGK Fk2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678421375; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=azG6rPTW4OW7MpxRM4BYmIziHm2wpGO0S0WPmax4BIQ=; b=Yw+Zt1CUP9HxvsF3xPytQWcLjJIFYi7loH2pyXdeOIG+5f97hkISUT3tuHdbpr+uO6 aN6kunyZ61vzq1m4cj/JsV349G0SlIY3FOmc3OXvCmo7WNJBoqYqdOeDbYsC/z7H5N/o ViwixrjtfNQp/J1ToaL6LT9lYgCgfp3Dv09zOK9/j2IwBcwzIhIqOrDXRq4pa+V6Zfn4 xksQkVDag/wZoMYZCvBmnwO8Ej8TN1ZIQpvgmpXpUBq1jYvdeMYoke3PgX6JL0WGIJu1 R+ns8wUyDQvEpioyM+tofhTMA6D1cBEylLLvCMOy41Ui2sB02yFE5aFl+WOiT3aZ9EBk Kr1Q== X-Gm-Message-State: AO0yUKWwQU7mz0cEhW89aEsTpquC1arO5tROE6U7cV9g9JjCIg3TaES6 jr0zUyp9xJ6Djk3JN8r9HSkT X-Received: by 2002:aa7:96e2:0:b0:5a9:cbc3:ca70 with SMTP id i2-20020aa796e2000000b005a9cbc3ca70mr22595640pfq.24.1678421375186; Thu, 09 Mar 2023 20:09:35 -0800 (PST) Received: from localhost.localdomain ([27.111.75.67]) by smtp.gmail.com with ESMTPSA id y26-20020aa7855a000000b0058d92d6e4ddsm361846pfn.5.2023.03.09.20.09.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Mar 2023 20:09:34 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, quic_srichara@quicinc.com, Manivannan Sadhasivam Subject: [PATCH v3 15/19] arm64: dts: qcom: sdm845: Add "mhi" region to the PCIe nodes Date: Fri, 10 Mar 2023 09:38:12 +0530 Message-Id: <20230310040816.22094-16-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230310040816.22094-1-manivannan.sadhasivam@linaro.org> References: <20230310040816.22094-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759953172151334484?= X-GMAIL-MSGID: =?utf-8?q?1759953172151334484?= The "mhi" region contains the debug registers that could be used to monitor the PCIe link transitions. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 479859bd8ab3..46caac9acc95 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2282,8 +2282,9 @@ pcie0: pci@1c00000 { reg = <0 0x01c00000 0 0x2000>, <0 0x60000000 0 0xf1d>, <0 0x60000f20 0 0xa8>, - <0 0x60100000 0 0x100000>; - reg-names = "parf", "dbi", "elbi", "config"; + <0 0x60100000 0 0x100000>, + <0 0x01c07000 0 0x1000>; + reg-names = "parf", "dbi", "elbi", "config", "mhi"; device_type = "pci"; linux,pci-domain = <0>; bus-range = <0x00 0xff>; @@ -2387,8 +2388,9 @@ pcie1: pci@1c08000 { reg = <0 0x01c08000 0 0x2000>, <0 0x40000000 0 0xf1d>, <0 0x40000f20 0 0xa8>, - <0 0x40100000 0 0x100000>; - reg-names = "parf", "dbi", "elbi", "config"; + <0 0x40100000 0 0x100000>, + <0 0x01c0c000 0 0x1000>; + reg-names = "parf", "dbi", "elbi", "config", "mhi"; device_type = "pci"; linux,pci-domain = <1>; bus-range = <0x00 0xff>; From patchwork Fri Mar 10 04:08:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 67216 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp680010wrd; Thu, 9 Mar 2023 20:27:14 -0800 (PST) X-Google-Smtp-Source: AK7set85WCgEBMQ6cSN00Yr/VUkHnSuN2LVvwS0igY8yGRSmcfRJbbKX1mfW5/WBs18EVAD/wIPk X-Received: by 2002:aa7:96d8:0:b0:5ef:b4e1:db0e with SMTP id h24-20020aa796d8000000b005efb4e1db0emr20516764pfq.16.1678422433866; Thu, 09 Mar 2023 20:27:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1678422433; cv=none; d=google.com; s=arc-20160816; b=kQW1EoGOjPZ8IKQCVQ9cVktShkYWjL0Bxr1HmvIDg3Sy/ZUWNa6JfqLIEIz0JxQsgU +EImaQi7wVZrOJ8hDfmnAe/L3wqPTYMzbwpG0aXhfbzOzQvZM12WRaT9Tjpiynh0zO9T q6iwzE/8YsVljvOIztxLnY+eKnfIecf0Ksg4DUN6EjffqXprr8U2wX11bWgK0FwXwJmd LTbBqSqMD2UWFfLfKuk5Q40tiu6ln9I7bg/KjqiIrOE/2sym4oSWuCC74d7Kz5TNNMwj rvn6dRqmDgqV2MxHwVo00+hdr8IXIIiMIyMaaET+jChZaTzsqyVWYwOYB1s4JBmjaNUm Ob/w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=u4buO9u/YEJ2XslOs7PK/sn8ZofMZxzKI+5s+2aMPGs=; b=KtVI0QPDDGMvDXoQ0YXwUtFLj34GsyWTnJ5nDk/yudim6eCYH4TXVeemS/cQinW3OE pA0JvXRN6c/c4s4GDqnl5rs+A3D67BDydsl6hOX4VQzp8OUhcKRXQoYcQEOmR5RQYLnK l7TSs3cxx8H3etKV8rIublXsUEXEIYrtgaG6vi+8j6i92yP7fjuIlCEhCWk0onPAB+2R 8tqgtycxVKrEa+BYMRSG4J1NO5iwV4RGDC1q1Q/vuv7+o+2tn1fgi3YIXGWjQOyyy+bk 30znQs2ahPHHEMZAiOAfFIs+ro4wqDBR9xb6S7tjmV7NYQfKnHqD2MeOtOzvCCcmJWXB QaMg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Yhgo+Kzh; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id a8-20020a63d408000000b00502ffff6533si970207pgh.88.2023.03.09.20.27.01; Thu, 09 Mar 2023 20:27:13 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Yhgo+Kzh; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231140AbjCJEMB (ORCPT + 99 others); Thu, 9 Mar 2023 23:12:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60890 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230243AbjCJEKt (ORCPT ); Thu, 9 Mar 2023 23:10:49 -0500 Received: from mail-pj1-x1034.google.com (mail-pj1-x1034.google.com [IPv6:2607:f8b0:4864:20::1034]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 188C6102B73 for ; Thu, 9 Mar 2023 20:09:44 -0800 (PST) Received: by mail-pj1-x1034.google.com with SMTP id me6-20020a17090b17c600b0023816b0c7ceso8536430pjb.2 for ; Thu, 09 Mar 2023 20:09:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678421379; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=u4buO9u/YEJ2XslOs7PK/sn8ZofMZxzKI+5s+2aMPGs=; b=Yhgo+KzhV0XGUvfnd/Fy/ekOzTIPp2EImzqeI1nddn4PntdIRUwETkoIDUdfennjHu zb+B8aPivUyLWAZCbQkWh3FjcJOWOlzcAr/1VAD3R1q/IaE9qg6l55hlw3/bhNd5/gPt DQKMt4pSb8K57TkbduoD0O4YwRXFwL4HvqlO3vNQ/00Dbvbpa737iBf+uRsYQnPQ9Lis JtNDDpSiqu9kuG+W7EVSHdhrI32yDUK6AaO5LAbkuOrQtqcpSWgYGuGGGS1xYQW8baBS WgoyxYlCC4ei3OkBhF2qvc4L2MISmdkkc41xu10m8PeDznWt+PI9bqgpLrjg0qhGF9dt +mTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678421379; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=u4buO9u/YEJ2XslOs7PK/sn8ZofMZxzKI+5s+2aMPGs=; b=KzcgycKJfGNzpA6knpw1hSF1B0U7Dx571/uvElQcqLXJjMfmgNY5f7qt4LJ2ZGO28T F9PL6kh2q6hegVK5kpJ+2tEh8oPlrVkxIMnPrtPoMnzCB5wSh7nRsJMhb19I5FtM/CwH og4C+4dBFdNFZopi5/r/3pxY2OSLcJZKuUsmHhlJNp+rXIZUtc6lzdcHlHIY7qpX97ax 72ZC6NgYp/7E3UxuE+hQYSg5qWHnLK26ofqWkCOfQn1WuYTBz3UiHDdBkEOvAFWhcGSL T1viyHFKNWsQkL9HIcZvahVH/pKJIF91A1GSZZnz7xGizyVmjV8TEpwdzRaP3QSMt6K/ eXyw== X-Gm-Message-State: AO0yUKWaE9T5Hj2CopOC5V6xtZ+mPEzDIFH3dwQ2NmRkryJDLK5Wx4Qa Mds8zI3zTyJNN7SeeHKtWAlJ X-Received: by 2002:a05:6a20:6712:b0:cb:ec3d:4783 with SMTP id q18-20020a056a20671200b000cbec3d4783mr21448427pzh.21.1678421379004; Thu, 09 Mar 2023 20:09:39 -0800 (PST) Received: from localhost.localdomain ([27.111.75.67]) by smtp.gmail.com with ESMTPSA id y26-20020aa7855a000000b0058d92d6e4ddsm361846pfn.5.2023.03.09.20.09.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Mar 2023 20:09:38 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, quic_srichara@quicinc.com, Manivannan Sadhasivam Subject: [PATCH v3 16/19] arm64: dts: qcom: sm8250: Add "mhi" region to the PCIe nodes Date: Fri, 10 Mar 2023 09:38:13 +0530 Message-Id: <20230310040816.22094-17-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230310040816.22094-1-manivannan.sadhasivam@linaro.org> References: <20230310040816.22094-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759953482177931810?= X-GMAIL-MSGID: =?utf-8?q?1759953482177931810?= The "mhi" region contains the debug registers that could be used to monitor the PCIe link transitions. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 2f0e460acccd..81383e20d3d9 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -1824,8 +1824,9 @@ pcie0: pci@1c00000 { <0 0x60000000 0 0xf1d>, <0 0x60000f20 0 0xa8>, <0 0x60001000 0 0x1000>, - <0 0x60100000 0 0x100000>; - reg-names = "parf", "dbi", "elbi", "atu", "config"; + <0 0x60100000 0 0x100000>, + <0 0x01c03000 0 0x1000>; + reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; device_type = "pci"; linux,pci-domain = <0>; bus-range = <0x00 0xff>; @@ -1933,8 +1934,9 @@ pcie1: pci@1c08000 { <0 0x40000000 0 0xf1d>, <0 0x40000f20 0 0xa8>, <0 0x40001000 0 0x1000>, - <0 0x40100000 0 0x100000>; - reg-names = "parf", "dbi", "elbi", "atu", "config"; + <0 0x40100000 0 0x100000>, + <0 0x01c0b000 0 0x1000>; + reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; device_type = "pci"; linux,pci-domain = <1>; bus-range = <0x00 0xff>; @@ -2041,8 +2043,9 @@ pcie2: pci@1c10000 { <0 0x64000000 0 0xf1d>, <0 0x64000f20 0 0xa8>, <0 0x64001000 0 0x1000>, - <0 0x64100000 0 0x100000>; - reg-names = "parf", "dbi", "elbi", "atu", "config"; + <0 0x64100000 0 0x100000>, + <0 0x01c13000 0 0x1000>; + reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; device_type = "pci"; linux,pci-domain = <2>; bus-range = <0x00 0xff>; From patchwork Fri Mar 10 04:08:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 67218 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp680122wrd; Thu, 9 Mar 2023 20:27:40 -0800 (PST) X-Google-Smtp-Source: AK7set80n27S4gw2zpenY1XtTvr6t0CpywisFijqrSmWuxZ6mGACYWIInt+Jh8QhzMN+L/8NDSwk X-Received: by 2002:a17:90a:19c8:b0:234:236f:1a8d with SMTP id 8-20020a17090a19c800b00234236f1a8dmr24510499pjj.14.1678422460478; Thu, 09 Mar 2023 20:27:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1678422460; cv=none; d=google.com; s=arc-20160816; b=Sj27LQudPN96WntN3zJfl2a7bJI6Eo4kBcbVLkfBOjeRSqLDvbybam9IgKxkoLrj4J oZ4kWPhN3uAuDy/S1JtvrYIdY/F+dTd4hCVACXZGE9BM/M+E0Qg+KPVkG3PNBN8EULhj tauyC1BEDiut1NNVw169r+9ageJW4SGzfv11Am+zN5lVc+0Z2VDd6TOr9+aVvaBMCNB3 GYjezF7I5cs/hyqm20E+UrOsuYs4mRvqPzO+dENNp+pVdIw+/cet0rMV8IhgU57Vs7P1 dw7ZeI96Sb5tQTaIxOiKdQNAtT3xV4/Tv7ZHHhYtS2CJB+8vQ4JShRn39x6yIKfvOiNv RqlA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=TfGaCzEutI1ZxAuEhg+K1BmQaCq/7g5+zrL93kp+oys=; b=xV1sobKGIB26VG7tpfRgi70Q81gmDLmBLY2Q1Q/PzIKsyQbmr8IYdTLgWf9Nw6+WGf BT+vjS6o1ihxh/U21WGFdyPuIF91USiRoYCbRiK99CAQLLmN4QQ1VLED7LlKkizIRH2d hJ1t6C3vSikWPjRvW0vsz51YbepgeUTi3CKa/lUwjF6C83qIHr5dD88FTx99hD+BmEyg IHpwv2EMlz9xEUEn+eCENNSlkJWG5YEMBTcFwlrPTQ0w93JLKPDThSQ3/ZE4rO1LnyxH 1w3Z8AC9eGomMigNRL1TbzAiVJpV6LbUoU68UPnuFvbFfwmtrB1okVgQr6uuIJvXHYGC LCVw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hYP3bxNU; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id a8-20020a63d408000000b00502ffff6533si970207pgh.88.2023.03.09.20.27.27; Thu, 09 Mar 2023 20:27:40 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hYP3bxNU; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230401AbjCJEMF (ORCPT + 99 others); Thu, 9 Mar 2023 23:12:05 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59658 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230431AbjCJEKv (ORCPT ); Thu, 9 Mar 2023 23:10:51 -0500 Received: from mail-pg1-x52e.google.com (mail-pg1-x52e.google.com [IPv6:2607:f8b0:4864:20::52e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 75C3F103EDD for ; Thu, 9 Mar 2023 20:09:44 -0800 (PST) Received: by mail-pg1-x52e.google.com with SMTP id h31so2355637pgl.6 for ; Thu, 09 Mar 2023 20:09:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678421384; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TfGaCzEutI1ZxAuEhg+K1BmQaCq/7g5+zrL93kp+oys=; b=hYP3bxNUWN+cDM56wIW5jHqBMTGJY5MpDds/b+AcTuqU6Tl+GBM8Hdk/iy+xZLDU2Q LcFhkkJUAtLBLgGDQ/FBdnvsSeBT6rNX/xwSUH1Rw3FpovXy0cg2cJnZ62a4hOB7CUYr i/I6hUAVAvdnO3eTnp0gu2SIlf4teIBioRdcUFmuFXjrIRdsDwRgYCKetGSr2/5aV/5z 1wVtpdwJ/4DwFiDh2SM4QxN6b+zAb+uGIkW6e7mIZnZJj+dMwzJaLw2no2q+DGqEzwi1 77nXkAWzhmrDqYE27e+rkYYSXkqql9u66ySYgu9LSWUcxl85iKlXBqoMtHTTGum4a+7V e9iQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678421384; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TfGaCzEutI1ZxAuEhg+K1BmQaCq/7g5+zrL93kp+oys=; b=lmu3sOOwPXN5+XvqLsn7g8bEKe1EX3iO0BZNWT7HzP8e4ddiowbP0JP3T32q1m9fAj YbP5JeMHC32nbKRO0sPpMJxNVn27Cw4bMBJ6U1+j+FANLzYCwGHuZ8GdtKwmujlFGHrQ X9Z9BIvjOvJC1SBD83obRmWpuV0T3sw3WRzmKGC+p1UfnX0RlBPIh0WcTP25eLQgDIAi bFcTB+iqDCO2kMGBf0jhx3RssZZgKlXBOFdWLpZVWDpnd/z711yCj1fwrJrV0UGDzIXv icd/mU82JARMg9bIs9CKAID3roijyd0r8nhX4t5y8Pd6Tsx9YQKISP5iuyEcqJpC70g4 EPUA== X-Gm-Message-State: AO0yUKW9RIgyq2nMpXt+c3BFUhf2jI3RbVuHPzo4xB7VlScNrySTC3CI lD4n96Hthmxjq4HY9nPCaT3g X-Received: by 2002:aa7:968e:0:b0:5a9:bba9:f25b with SMTP id f14-20020aa7968e000000b005a9bba9f25bmr23736644pfk.17.1678421384135; Thu, 09 Mar 2023 20:09:44 -0800 (PST) Received: from localhost.localdomain ([27.111.75.67]) by smtp.gmail.com with ESMTPSA id y26-20020aa7855a000000b0058d92d6e4ddsm361846pfn.5.2023.03.09.20.09.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Mar 2023 20:09:42 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, quic_srichara@quicinc.com, Manivannan Sadhasivam Subject: [PATCH v3 17/19] arm64: dts: qcom: sc8280xp: Add "mhi" region to the PCIe nodes Date: Fri, 10 Mar 2023 09:38:14 +0530 Message-Id: <20230310040816.22094-18-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230310040816.22094-1-manivannan.sadhasivam@linaro.org> References: <20230310040816.22094-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759953509943406727?= X-GMAIL-MSGID: =?utf-8?q?1759953509943406727?= The "mhi" region contains the debug registers that could be used to monitor the PCIe link transitions. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 0d02599d8867..eb87c3e5d2bc 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -1653,8 +1653,9 @@ pcie4: pcie@1c00000 { <0x0 0x30000000 0x0 0xf1d>, <0x0 0x30000f20 0x0 0xa8>, <0x0 0x30001000 0x0 0x1000>, - <0x0 0x30100000 0x0 0x100000>; - reg-names = "parf", "dbi", "elbi", "atu", "config"; + <0x0 0x30100000 0x0 0x100000>, + <0x0 0x01c03000 0x0 0x1000>; + reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0x0 0x30200000 0x0 0x30200000 0x0 0x100000>, @@ -1752,8 +1753,9 @@ pcie3b: pcie@1c08000 { <0x0 0x32000000 0x0 0xf1d>, <0x0 0x32000f20 0x0 0xa8>, <0x0 0x32001000 0x0 0x1000>, - <0x0 0x32100000 0x0 0x100000>; - reg-names = "parf", "dbi", "elbi", "atu", "config"; + <0x0 0x32100000 0x0 0x100000>, + <0x0 0x01c0b000 0x0 0x1000>; + reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0x0 0x32200000 0x0 0x32200000 0x0 0x100000>, @@ -1849,8 +1851,9 @@ pcie3a: pcie@1c10000 { <0x0 0x34000000 0x0 0xf1d>, <0x0 0x34000f20 0x0 0xa8>, <0x0 0x34001000 0x0 0x1000>, - <0x0 0x34100000 0x0 0x100000>; - reg-names = "parf", "dbi", "elbi", "atu", "config"; + <0x0 0x34100000 0x0 0x100000>, + <0x0 0x01c13000 0x0 0x1000>; + reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0x0 0x34200000 0x0 0x34200000 0x0 0x100000>, @@ -1949,8 +1952,9 @@ pcie2b: pcie@1c18000 { <0x0 0x38000000 0x0 0xf1d>, <0x0 0x38000f20 0x0 0xa8>, <0x0 0x38001000 0x0 0x1000>, - <0x0 0x38100000 0x0 0x100000>; - reg-names = "parf", "dbi", "elbi", "atu", "config"; + <0x0 0x38100000 0x0 0x100000>, + <0x0 0x01c1b000 0x0 0x1000>; + reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0x0 0x38200000 0x0 0x38200000 0x0 0x100000>, @@ -2046,8 +2050,9 @@ pcie2a: pcie@1c20000 { <0x0 0x3c000000 0x0 0xf1d>, <0x0 0x3c000f20 0x0 0xa8>, <0x0 0x3c001000 0x0 0x1000>, - <0x0 0x3c100000 0x0 0x100000>; - reg-names = "parf", "dbi", "elbi", "atu", "config"; + <0x0 0x3c100000 0x0 0x100000>, + <0x0 0x01c23000 0x0 0x1000>; + reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0x0 0x3c200000 0x0 0x3c200000 0x0 0x100000>, From patchwork Fri Mar 10 04:08:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 67212 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp679635wrd; Thu, 9 Mar 2023 20:25:46 -0800 (PST) X-Google-Smtp-Source: AK7set+0Yvqgwk1WAP9k2cEwUKVH88lrhnikQwxz29s4snUKitUrBUEzROnsOXcPPXigpUipCpcV X-Received: by 2002:a17:902:db02:b0:19c:edcd:26cf with SMTP id m2-20020a170902db0200b0019cedcd26cfmr25913466plx.61.1678422345781; Thu, 09 Mar 2023 20:25:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1678422345; cv=none; d=google.com; s=arc-20160816; b=egS8UomcVukrzLaFd7o1DdfNOZstGVOKhos06U9APGPvT/PjpLLet2mORCHbjCmkWC qGqgk5qL1//N52k5BvEKJ1KqPjlm7G7KiY8sTfmO59SoBnutWkkSewYOo9S65zL8AfH3 Z7bXyc+3GHFTMiexyGDHy+0y+sfk6PCbkrAZN8LaC+p4m66QaXiso0gOJalOdAc1anfa 8uOYEVIsl5ULl0Ys6lASQzTek3WO8GqbZAhP9A0whTydxlRf+dcAvZsoHpizu2aVvrv6 0fhIpvYH3YzvxseK9guE4BYf+0TCaYxn7bXXlgfFju3gzFu7Lksl2vRgN9B0dpBViF+W OBbQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=SyhF4Lknyw7VhB+OiPeq4AnEmul/Wt/H/6qIG9Bjj1E=; b=RsCOyDERJ2W9x//rcs3ig5i2E2UJfTtHUhEPhkHJtrNfAm2RA4jJ22doNQynQ8Lj/o 8uBxiNPsNuwqYN3NfVLNoIgtfCGV0WQZUlM/W5V2lbP+fpup3JPayCOeFahtCN23IS/N 4NRZobIvijmXdwymmCgIFGl2zJXznsGmtBCT2yGxzD6EgP/JOJ31CQZbor3zvXnFEK5A pRMN+aJZzN71QGbFgH3JNdT8+Qo+iQ4i+vi0EdKBhKViTYjHKdrh0oMca8I5Gzz3QNTd DU4t/5ssVMqNDzYMCWLk1xOMEp8dU4U1zyhUqq/M4hOIR917Nuxk6NyHhq2ULbfXvfjL JFaA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jnxoVqzy; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id bd6-20020a170902830600b0019af153b740si1016517plb.625.2023.03.09.20.25.32; Thu, 09 Mar 2023 20:25:45 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jnxoVqzy; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230496AbjCJEMj (ORCPT + 99 others); Thu, 9 Mar 2023 23:12:39 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60582 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230488AbjCJELO (ORCPT ); Thu, 9 Mar 2023 23:11:14 -0500 Received: from mail-pf1-x435.google.com (mail-pf1-x435.google.com [IPv6:2607:f8b0:4864:20::435]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D8828F601A for ; Thu, 9 Mar 2023 20:09:56 -0800 (PST) Received: by mail-pf1-x435.google.com with SMTP id bd34so2875598pfb.3 for ; Thu, 09 Mar 2023 20:09:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678421388; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SyhF4Lknyw7VhB+OiPeq4AnEmul/Wt/H/6qIG9Bjj1E=; b=jnxoVqzy+QhCv5b6dfN9qTqFUJp/2zsKEmrMDPkxUmM2VqMsWxFw17benA1A6OJaZp Tvtv5QhYUBJiyYIFZ9calAKmFteyHK/4Ka6Wa41Z2KrW95Af54If1saMvLiATqu2CQ2w EfRjnyjtDAPporuSvaC+Cj7wbQqqEBJFwixudI2f8GKOe45Y7Nc6iXQOkex0e9sypie5 P+YEtYUvk6AsrgNgd4erokttTOpWmv4tfMztvd2wXjsmFxJJIDIl2RgVSGJC1fQDZbwV S44vHWrLLdam+t/fcqvQot6v/umkFD3oPQhxzKXKfbzQqP+LxYakoenPzBz16vniDUd/ dYgw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678421388; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SyhF4Lknyw7VhB+OiPeq4AnEmul/Wt/H/6qIG9Bjj1E=; b=raXM1ipFgu7wKha9jEYO5nv5jkKaXEpisjesExjgWEIGSR2olwnWWwnB+Atz8X82UQ 8zyOgi4jjGhPqsx1FEtdP37lmL3EZPI6Na9IPalRDRIdPDduXzOxX8IVazKBdPt09lM5 GJmbrxDoxxbQD82Q+PAbH+oVL8INA3aScRxVw4Dro25YkVUMwW11f1O8aMInZGfcFDp1 uhnNUKIUihCgfGFQsM2ok1HveidhzU8h2iUSkAbl6DfckjjmdKg0FZul/uCUpO9i6x5d sZ4e9DfKEOLDLIp4gR/rcA94ATaXRuYO6lKhQDXJvEoyUFM9BHnXh7I0EBX3brFg8P2W MbdQ== X-Gm-Message-State: AO0yUKUlxp3AuezlwbFCb67rDOy5YwQfTEQf8rXY5RkyVRjOjDlfQQzs 3Aaop5fCJ7ZFWG9mTpec5UMD X-Received: by 2002:a62:4ecb:0:b0:593:f191:966 with SMTP id c194-20020a624ecb000000b00593f1910966mr18792008pfb.1.1678421388038; Thu, 09 Mar 2023 20:09:48 -0800 (PST) Received: from localhost.localdomain ([27.111.75.67]) by smtp.gmail.com with ESMTPSA id y26-20020aa7855a000000b0058d92d6e4ddsm361846pfn.5.2023.03.09.20.09.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Mar 2023 20:09:47 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, quic_srichara@quicinc.com, Manivannan Sadhasivam Subject: [PATCH v3 18/19] PCI: qcom: Expose link transition counts via debugfs for v1.9.0 & v2.7.0 Date: Fri, 10 Mar 2023 09:38:15 +0530 Message-Id: <20230310040816.22094-19-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230310040816.22094-1-manivannan.sadhasivam@linaro.org> References: <20230310040816.22094-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759953389685928497?= X-GMAIL-MSGID: =?utf-8?q?1759953389685928497?= Qualcomm PCIe controllers of versions v1.9.0 and v2.7.0 have debug registers in the MHI region that count PCIe link transitions. Expose them over debugfs to userspace to help debug the low power issues. Note that even though the registers are prefixed as PARF_, they don't live under the "parf" register region. The register naming is following the Qualcomm's internal documentation as like other registers. The debugfs interface is added using per config callback because the register interface for accessing debug info varies between IP versions. While at it, let's arrange the local variables in probe function to follow reverse XMAS tree order. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 77 +++++++++++++++++++++++++- 1 file changed, 75 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 52f09ee8dd48..f99b7e7f3f73 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -10,6 +10,7 @@ #include #include +#include #include #include #include @@ -62,6 +63,13 @@ #define AXI_MSTR_RESP_COMP_CTRL1 0x81c #define MISC_CONTROL_1_REG 0x8bc +/* MHI registers */ +#define PARF_DEBUG_CNT_PM_LINKST_IN_L2 0xc04 +#define PARF_DEBUG_CNT_PM_LINKST_IN_L1 0xc0c +#define PARF_DEBUG_CNT_PM_LINKST_IN_L0S 0xc10 +#define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1 0xc84 +#define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2 0xc88 + /* PARF_SYS_CTRL register fields */ #define MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN BIT(29) #define MST_WAKEUP_EN BIT(13) @@ -219,6 +227,7 @@ struct qcom_pcie_ops { void (*deinit)(struct qcom_pcie *pcie); void (*ltssm_enable)(struct qcom_pcie *pcie); int (*config_sid)(struct qcom_pcie *pcie); + void (*init_debugfs)(struct qcom_pcie *pcie); }; struct qcom_pcie_cfg { @@ -229,11 +238,13 @@ struct qcom_pcie { struct dw_pcie *pci; void __iomem *parf; /* DT parf */ void __iomem *elbi; /* DT elbi */ + void __iomem *mhi; union qcom_pcie_resources res; struct phy *phy; struct gpio_desc *reset; struct icc_path *icc_mem; const struct qcom_pcie_cfg *cfg; + struct dentry *debugfs; }; #define to_qcom_pcie(x) dev_get_drvdata((x)->dev) @@ -263,6 +274,23 @@ static int qcom_pcie_start_link(struct dw_pcie *pci) return 0; } +static void qcom_pcie_init_debugfs(struct qcom_pcie *pcie, + int (*debugfs_func)(struct seq_file *s, void *data)) +{ + struct dw_pcie *pci = pcie->pci; + struct device *dev = pci->dev; + char *name; + + name = devm_kasprintf(dev, GFP_KERNEL, "%pOFP", dev->of_node); + if (!name) + return; + + pcie->debugfs = debugfs_create_dir(name, NULL); + + debugfs_create_devm_seqfile(pci->dev, "link_transition_count", + pcie->debugfs, debugfs_func); +} + static void qcom_pcie_2_1_0_ltssm_enable(struct qcom_pcie *pcie) { u32 val; @@ -963,6 +991,35 @@ static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie) regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); } +static int qcom_pcie_debugfs_func_2_7_0(struct seq_file *s, void *data) +{ + struct qcom_pcie *pcie = (struct qcom_pcie *) dev_get_drvdata(s->private); + + seq_printf(s, "L0s transition count: %u\n", + readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_PM_LINKST_IN_L0S)); + + seq_printf(s, "L1 transition count: %u\n", + readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_PM_LINKST_IN_L1)); + + seq_printf(s, "L1.1 transition count: %u\n", + readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1)); + + seq_printf(s, "L1.2 transition count: %u\n", + readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2)); + + seq_printf(s, "L2 transition count: %u\n", + readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_PM_LINKST_IN_L2)); + + return 0; +} + + +static void qcom_pcie_init_debugfs_2_7_0(struct qcom_pcie *pcie) +{ + if (pcie->mhi) + qcom_pcie_init_debugfs(pcie, qcom_pcie_debugfs_func_2_7_0); +} + static int qcom_pcie_config_sid_1_9_0(struct qcom_pcie *pcie) { /* iommu map structure */ @@ -1260,6 +1317,7 @@ static const struct qcom_pcie_ops ops_2_7_0 = { .init = qcom_pcie_init_2_7_0, .deinit = qcom_pcie_deinit_2_7_0, .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, + .init_debugfs = qcom_pcie_init_debugfs_2_7_0, }; /* Qcom IP rev.: 1.9.0 */ @@ -1269,6 +1327,7 @@ static const struct qcom_pcie_ops ops_1_9_0 = { .deinit = qcom_pcie_deinit_2_7_0, .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, .config_sid = qcom_pcie_config_sid_1_9_0, + .init_debugfs = qcom_pcie_init_debugfs_2_7_0, }; /* Qcom IP rev.: 2.9.0 Synopsys IP rev.: 5.00a */ @@ -1387,11 +1446,12 @@ static void qcom_pcie_icc_update(struct qcom_pcie *pcie) static int qcom_pcie_probe(struct platform_device *pdev) { + const struct qcom_pcie_cfg *pcie_cfg; struct device *dev = &pdev->dev; + struct qcom_pcie *pcie; struct dw_pcie_rp *pp; + struct resource *res; struct dw_pcie *pci; - struct qcom_pcie *pcie; - const struct qcom_pcie_cfg *pcie_cfg; int ret; pcie_cfg = of_device_get_match_data(dev); @@ -1439,6 +1499,16 @@ static int qcom_pcie_probe(struct platform_device *pdev) goto err_pm_runtime_put; } + /* MHI region is optional */ + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mhi"); + if (res) { + pcie->mhi = devm_ioremap_resource(dev, res); + if (IS_ERR(pcie->mhi)) { + ret = PTR_ERR(pcie->mhi); + goto err_pm_runtime_put; + } + } + pcie->phy = devm_phy_optional_get(dev, "pciephy"); if (IS_ERR(pcie->phy)) { ret = PTR_ERR(pcie->phy); @@ -1469,6 +1539,9 @@ static int qcom_pcie_probe(struct platform_device *pdev) qcom_pcie_icc_update(pcie); + if (pcie->cfg->ops->init_debugfs) + pcie->cfg->ops->init_debugfs(pcie); + return 0; err_phy_exit: From patchwork Fri Mar 10 04:08:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 67221 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp680493wrd; Thu, 9 Mar 2023 20:29:06 -0800 (PST) X-Google-Smtp-Source: AK7set9qghtymnFbyxypz1CDmWppDmTeGdk0aTBgXw2bX+qiH/Sce0qvCwtt+7VspkEbeqhkiPu+ X-Received: by 2002:a05:6a21:9992:b0:cd:2ed3:b7f8 with SMTP id ve18-20020a056a21999200b000cd2ed3b7f8mr26830345pzb.40.1678422546285; Thu, 09 Mar 2023 20:29:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1678422546; cv=none; d=google.com; s=arc-20160816; b=KsSfoz1NpVwtnnRtFOvlx9ciStg3KZBMaoJKyiUJYQaq9tcLVGXiRMnSiCi8YzQlZm urMoCWqkNZ9PWswGUP0Z2TSRDDbQ1uUpYpt47poP+TkfC7Q9iXqNxHUXcN395wkrF9Wj ShtyoQgTpAB7V2IJi0dAkJcYvGoiVTio8W+7NV9Entilo14LvnQmfXQbI8to01nJp0NR mXxWCD0fY7c7Uv8Jj6x2zgcLsMSunMt0C4YUn0/uMMwLWodHweb2xazK9ba6n2ZXX26E EBaa1HP9jvErJRFPasriamAQuevHR2koq/NnMRpoTrEw43b4BuTkRslDLLEXx4Biszkh M2Ng== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Cfp/acTiWdK8wUm8C9dXVBGQPGUivfzPYcratFFfeXU=; b=XfG9NKcvD10r2ZqnZVHRuRX9WS10lNQxqWLqAgM+dnqeJVhJ/t2/npEDBUV107oe7c 0ht26IDzDZs6n4XPDewB8wz8yyQcKwNVydd7vibqRUvF7fR7ENjWwyMzNLVcetQkeQ7Z 5tDYC1iTNHMkNLozJpbEabDh2Dza5ka7rzJfEqkLhCnk1xbWFhx8M1FyIRGTrhQXpZUj nu2SPbZuDBqBGtyJ6nGAyNz7XELvF7R6d+mz6JHpMCIScZ/ncDXluy0pw1CbX7ruNKFv z1Kelw0HAXkO/yzMOf/tLEckrkqZ64FJDIoT1O4a+InmrW7QG6lNeJqPxCcu70Z6vlPa PSkQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IS3acGy5; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id a8-20020a63d408000000b00502ffff6533si970207pgh.88.2023.03.09.20.28.53; Thu, 09 Mar 2023 20:29:06 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IS3acGy5; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230337AbjCJEMn (ORCPT + 99 others); Thu, 9 Mar 2023 23:12:43 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59462 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230251AbjCJELO (ORCPT ); Thu, 9 Mar 2023 23:11:14 -0500 Received: from mail-pl1-x632.google.com (mail-pl1-x632.google.com [IPv6:2607:f8b0:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 92AFA103EE1 for ; Thu, 9 Mar 2023 20:09:57 -0800 (PST) Received: by mail-pl1-x632.google.com with SMTP id v11so4297360plz.8 for ; Thu, 09 Mar 2023 20:09:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678421392; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Cfp/acTiWdK8wUm8C9dXVBGQPGUivfzPYcratFFfeXU=; b=IS3acGy5v+D1VrXLpVM4lVMitkBA6ZuCnc6t6WwzHNiDo99e6PL6fuhKYY/+Yq/yMZ LdZat7BftgHuO2RraexQ1g77BV+Iz7iCa5UrrspEL6OT7wykulaC0h6Yd4h/JTBCz30J FCSJMwZARxsKLBmXk5AzY9vcsd7hnx9Q47KT+pLYE0FOJEArcER7cOWmMZP6K9zgbs15 KJSMQv5e+JhI+WA4xdf1Yfxy1dDLvzbSMhivgV8JqxUd86wnhq6JfNkZ/XnrI77uK0+W 0kQ1oFhSV33XY1D0/YTfp42tBnyEsgYoxF6R8pAELjDFhsnAHB9hv9R6Vh6vSROBErEE 62KQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678421392; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Cfp/acTiWdK8wUm8C9dXVBGQPGUivfzPYcratFFfeXU=; b=bMURQ9o1Aq4OzVT+dN+mk/iEP5XFvoQ5Lhkl4cO8VpGnwYzSCgt5iUfgdGR+uF0nCH 6n6XYuMDi19mf6rppwPuRSlyIS69GQ5bPMWyUmOI37zZ1yCumAyDU1Ph7cU30C2ngpCj U1wshPPBWoepWzvk5vl5QjsJ2U2nFxOio8uraJ+T4kNGpgk2ti+jis0RbcNHTp+Ry45m Ay+C9WAm842FppABSA26wcYftf65FcvNh2rosdw851hSobdZ4yoqqfbOsju6ayWaKlzr l4XavnilPuGSz2WgpKi0SY+3Le5T3W/7ewKsaFY3T3014Kr+6x/YUzCMlf3J8pruMaCd iugw== X-Gm-Message-State: AO0yUKUZbfkbLHBd+ZVLc1vH2Q6R+0FkUD/0pPzdyxEmWiNHD8bFgi+R PoedMx1ZIAv8LQKZF6XiWdvK X-Received: by 2002:a05:6a20:548a:b0:cc:d891:b2b1 with SMTP id i10-20020a056a20548a00b000ccd891b2b1mr31419746pzk.35.1678421392094; Thu, 09 Mar 2023 20:09:52 -0800 (PST) Received: from localhost.localdomain ([27.111.75.67]) by smtp.gmail.com with ESMTPSA id y26-20020aa7855a000000b0058d92d6e4ddsm361846pfn.5.2023.03.09.20.09.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Mar 2023 20:09:51 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, lpieralisi@kernel.org, kw@linux.com, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, quic_srichara@quicinc.com, Manivannan Sadhasivam Subject: [PATCH v3 19/19] PCI: qcom: Expose link transition counts via debugfs for v2.4.0 Date: Fri, 10 Mar 2023 09:38:16 +0530 Message-Id: <20230310040816.22094-20-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230310040816.22094-1-manivannan.sadhasivam@linaro.org> References: <20230310040816.22094-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759953600043730754?= X-GMAIL-MSGID: =?utf-8?q?1759953600043730754?= Qualcomm PCIe controllers of version v2.4.0 have debug registers in the PARF region that count PCIe link transitions. Expose them over debugfs to userspace to help debug the low power issues. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 33 ++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index f99b7e7f3f73..0b41f007fa90 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -37,6 +37,7 @@ /* PARF registers */ #define PARF_SYS_CTRL 0x00 #define PARF_PM_CTRL 0x20 +#define PARF_PM_STTS 0x24 #define PARF_PCS_DEEMPH 0x34 #define PARF_PCS_SWING 0x38 #define PARF_PHY_CTRL 0x40 @@ -84,6 +85,12 @@ /* PARF_PM_CTRL register fields */ #define REQ_NOT_ENTR_L1 BIT(5) +/* PARF_PM_STTS register fields */ +#define PM_LINKST_IN_L1SUB BIT(8) +#define PM_LINKST_IN_L0S BIT(7) +#define PM_LINKST_IN_L2 BIT(5) +#define PM_LINKST_IN_L1 BIT(4) + /* PARF_PCS_DEEMPH register fields */ #define PCS_DEEMPH_TX_DEEMPH_GEN1(x) FIELD_PREP(GENMASK(21, 16), x) #define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) FIELD_PREP(GENMASK(13, 8), x) @@ -737,6 +744,31 @@ static int qcom_pcie_post_init_2_4_0(struct qcom_pcie *pcie) return 0; } +static int qcom_pcie_debugfs_func_2_4_0(struct seq_file *s, void *data) +{ + struct qcom_pcie *pcie = (struct qcom_pcie *) dev_get_drvdata(s->private); + + seq_printf(s, "L0s transition count: %u\n", + readl_relaxed(pcie->parf + PM_LINKST_IN_L0S)); + + seq_printf(s, "L1 transition count: %u\n", + readl_relaxed(pcie->parf + PM_LINKST_IN_L1)); + + seq_printf(s, "L1.1 transition count: %u\n", + readl_relaxed(pcie->parf + PM_LINKST_IN_L1SUB)); + + seq_printf(s, "L2 transition count: %u\n", + readl_relaxed(pcie->parf + PM_LINKST_IN_L2)); + + return 0; +} + + +static void qcom_pcie_init_debugfs_2_4_0(struct qcom_pcie *pcie) +{ + qcom_pcie_init_debugfs(pcie, qcom_pcie_debugfs_func_2_4_0); +} + static int qcom_pcie_get_resources_2_3_3(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3; @@ -1300,6 +1332,7 @@ static const struct qcom_pcie_ops ops_2_4_0 = { .post_init = qcom_pcie_post_init_2_4_0, .deinit = qcom_pcie_deinit_2_4_0, .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, + .init_debugfs = qcom_pcie_init_debugfs_2_4_0, }; /* Qcom IP rev.: 2.3.3 Synopsys IP rev.: 4.30a */