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Thu, 9 Mar 2023 02:54:34 -0800 Received: from drhqmail201.nvidia.com (10.126.190.180) by drhqmail202.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37; Thu, 9 Mar 2023 02:54:33 -0800 Received: from Asurada-Nvidia.nvidia.com (10.127.8.11) by mail.nvidia.com (10.126.190.180) with Microsoft SMTP Server id 15.2.986.37 via Frontend Transport; Thu, 9 Mar 2023 02:54:33 -0800 From: Nicolin Chen To: , , CC: , , , , , , , , Subject: [PATCH v1 01/14] iommu: Add iommu_get_unmanaged_domain helper Date: Thu, 9 Mar 2023 02:53:37 -0800 Message-ID: <9b1077601cace998533129327f5e7ad946752d29.1678348754.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF000108E9:EE_|CH0PR12MB5234:EE_ X-MS-Office365-Filtering-Correlation-Id: d0d3ea8f-7eb0-491f-397a-08db208cafdc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Mar 2023 10:54:41.8981 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d0d3ea8f-7eb0-491f-397a-08db208cafdc X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF000108E9.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5234 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759887451775717068?= X-GMAIL-MSGID: =?utf-8?q?1759887451775717068?= The nature of ITS virtualization on ARM is done via hypercalls, so kernel handles all IOVA mappings for the MSI doorbell in iommu_dma_prepare_msi() and iommu_dma_compose_msi_msg(). The current virtualization solution with a 2-stage nested translation setup is to do 1:1 IOVA mappings at stage-1 guest-level IO page table via a RMR region in guest-level IORT, aligning with an IOVA region that's predefined and mapped in the host kernel: [stage-2 host level] #define MSI_IOVA_BASE 0x8000000 #define MSI_IOVA_LENGTH 0x100000 ... iommu_get_msi_cookie(): cookie->msi_iova = MSI_IOVA_BASE; ... iommu_dma_prepare_msi(its_pa): domain = iommu_get_domain_for_dev(dev); iommu_dma_get_msi_page(its_pa, domain): cookie = domain->iova_cookie; iova = iommu_dma_alloc_iova(): return cookie->msi_iova - size; iommu_map(iova, its_pa, ...); [stage-1 guest level] // Define in IORT a RMR [MSI_IOVA_BASE, MSI_IOVA_LENGTH] ... iommu_create_device_direct_mappings(): iommu_map(iova=MSI_IOVA_BASE, pa=MSI_IOVA_BASE, len=MSI_IOVA_LENGTH); This solution calling iommu_get_domain_for_dev() needs the device to get attached to a host-level iommu_domain that has the msi_cookie. On the other hand, IOMMUFD designs two iommu_domain objects to represent the two stages: a stage-1 domain (IOMMU_DOMAIN_NESTED type) and a stage-2 domain (IOMMU_DOMAIN_UNMANAGED type). In this design, the device will be attached to the stage-1 domain representing a guest-level IO page table, or a Context Descriptor Table in SMMU's term. This is obviously a mismatch, as the iommu_get_domain_for_dev() does not return the correct domain pointer in iommu_dma_prepare_msi(). Add an iommu_get_unmanaged_domain helper to allow drivers to return the correct IOMMU_DOMAIN_UNMANAGED iommu_domain having the IOVA mappings for the msi_cookie. Keep it in the iommu-priv header for internal use only. Suggested-by: Jason Gunthorpe Signed-off-by: Nicolin Chen Signed-off-by: Robin Murphy --- drivers/iommu/dma-iommu.c | 5 +++-- drivers/iommu/iommu-priv.h | 15 +++++++++++++++ include/linux/iommu.h | 2 ++ 3 files changed, 20 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c index 99b2646cb5c7..6b0409d0ff85 100644 --- a/drivers/iommu/dma-iommu.c +++ b/drivers/iommu/dma-iommu.c @@ -31,6 +31,7 @@ #include #include "dma-iommu.h" +#include "iommu-priv.h" struct iommu_dma_msi_page { struct list_head list; @@ -1652,7 +1653,7 @@ static struct iommu_dma_msi_page *iommu_dma_get_msi_page(struct device *dev, int iommu_dma_prepare_msi(struct msi_desc *desc, phys_addr_t msi_addr) { struct device *dev = msi_desc_to_dev(desc); - struct iommu_domain *domain = iommu_get_domain_for_dev(dev); + struct iommu_domain *domain = iommu_get_unmanaged_domain(dev); struct iommu_dma_msi_page *msi_page; static DEFINE_MUTEX(msi_prepare_lock); /* see below */ @@ -1685,7 +1686,7 @@ int iommu_dma_prepare_msi(struct msi_desc *desc, phys_addr_t msi_addr) void iommu_dma_compose_msi_msg(struct msi_desc *desc, struct msi_msg *msg) { struct device *dev = msi_desc_to_dev(desc); - const struct iommu_domain *domain = iommu_get_domain_for_dev(dev); + const struct iommu_domain *domain = iommu_get_unmanaged_domain(dev); const struct iommu_dma_msi_page *msi_page; msi_page = msi_desc_get_iommu_cookie(desc); diff --git a/drivers/iommu/iommu-priv.h b/drivers/iommu/iommu-priv.h index a6e694f59f64..da8044da9ad8 100644 --- a/drivers/iommu/iommu-priv.h +++ b/drivers/iommu/iommu-priv.h @@ -15,6 +15,21 @@ static inline const struct iommu_ops *dev_iommu_ops(struct device *dev) return dev->iommu->iommu_dev->ops; } +static inline struct iommu_domain *iommu_get_unmanaged_domain(struct device *dev) +{ + const struct iommu_ops *ops; + + if (!dev->iommu || !dev->iommu->iommu_dev) + goto attached_domain; + + ops = dev_iommu_ops(dev); + if (ops->get_unmanaged_domain) + return ops->get_unmanaged_domain(dev); + +attached_domain: + return iommu_get_domain_for_dev(dev); +} + int iommu_group_replace_domain(struct iommu_group *group, struct iommu_domain *new_domain); diff --git a/include/linux/iommu.h b/include/linux/iommu.h index 080278c8154d..76c65cc4fc15 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -275,6 +275,8 @@ struct iommu_ops { struct iommu_domain *parent, const void *user_data); + struct iommu_domain *(*get_unmanaged_domain)(struct device *dev); + struct iommu_device *(*probe_device)(struct device *dev); void (*release_device)(struct device *dev); void (*probe_finalize)(struct device *dev); From patchwork Thu Mar 9 10:53:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 66773 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp221354wrd; Thu, 9 Mar 2023 02:58:22 -0800 (PST) X-Google-Smtp-Source: AK7set/vKn0vaPJpx2f9r2k6uuvMaGCs4smEjYLzACsBGFIpLpnk2DeZTGITs0uhPnVyeV67Q8Qn X-Received: by 2002:a17:903:48d:b0:19c:ff0a:2c7e with SMTP id jj13-20020a170903048d00b0019cff0a2c7emr17948047plb.33.1678359502314; Thu, 09 Mar 2023 02:58:22 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1678359502; cv=pass; d=google.com; s=arc-20160816; b=N9AfzXHhHLC88uAZFHTVAovF59uY8XlrUWxwU1VXTZrR9AGzr7LsaPq6w40oxtFZsd 7jkr04zzn4NRqJQ0gmgytdPDztY46uTECph0QVEtscYvu1P+nXUmlqOJJhhE+6CVvk0P akrDCUM6K1sf5b1zKa7b+XHWnzNUT5kbLXwkxR4XIJuK2nNc+dRFMvriahw8cByekPfz a/iMDcRFzz1IONhDV3Mi5KudlNsI8E2Swgdq2odFMn4l3Wct9+pWjQQ2cHdYap3diP4H uvJHX6b0/aOs/4Hw8GHJkEwA3I8gwn1jVokEGKxc23Av1Z+rjnUibDfrXBFxPPYZyRk4 Y58A== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=4oQ6kddw9272X4EaqFsjJqO46o5w+MkB4mjzLJs4WdY=; b=tn5ydStVvnf+bZanqCFG8lgNZ9pre4QzrZp1Pv0PKdhlgYOLjl/Zw8U3uNb2s9Gqci cDM28d+b19jMvMi7RFOlqROH4efU65ZS3NpUKGfUZibMccfIvEEFDsaWVHdeDt1/KI8A bzb7wR+oatU0COOi1NhihiLKzOFxUcOjXeOcaCNy2ycLQySVpNlx0G7qekamUDnm1a6M nZdCJhWRW+nMZzj3j4UO2Y91UGgyiwberp1ccVp/PQPAnWKQkdTr0osIcc/V0oM93k2r vr9pB+80UruaJrXxijZo1xHsUJcInmyVN+97Vfi+IOzyMA/ah1EKi418qEiGY8HVApOI GJfQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b=Kt7XPqNi; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Nicolin Chen --- drivers/iommu/iommufd/hw_pagetable.c | 4 +++ drivers/iommu/iommufd/main.c | 1 + include/uapi/linux/iommufd.h | 50 ++++++++++++++++++++++++++++ 3 files changed, 55 insertions(+) diff --git a/drivers/iommu/iommufd/hw_pagetable.c b/drivers/iommu/iommufd/hw_pagetable.c index 8f9985bddeeb..5e798b2f9a3a 100644 --- a/drivers/iommu/iommufd/hw_pagetable.c +++ b/drivers/iommu/iommufd/hw_pagetable.c @@ -173,6 +173,7 @@ iommufd_hw_pagetable_alloc(struct iommufd_ctx *ictx, struct iommufd_ioas *ioas, static const size_t iommufd_hwpt_alloc_data_size[] = { [IOMMU_HWPT_TYPE_DEFAULT] = 0, [IOMMU_HWPT_TYPE_VTD_S1] = sizeof(struct iommu_hwpt_intel_vtd), + [IOMMU_HWPT_TYPE_ARM_SMMUV3] = sizeof(struct iommu_hwpt_arm_smmuv3), }; /* @@ -183,6 +184,8 @@ const u64 iommufd_hwpt_type_bitmaps[] = { [IOMMU_HW_INFO_TYPE_DEFAULT] = BIT_ULL(IOMMU_HWPT_TYPE_DEFAULT), [IOMMU_HW_INFO_TYPE_INTEL_VTD] = BIT_ULL(IOMMU_HWPT_TYPE_DEFAULT) | BIT_ULL(IOMMU_HWPT_TYPE_VTD_S1), + [IOMMU_HW_INFO_TYPE_ARM_SMMUV3] = BIT_ULL(IOMMU_HWPT_TYPE_DEFAULT) | + BIT_ULL(IOMMU_HWPT_TYPE_ARM_SMMUV3), }; /* Return true if type is supported, otherwise false */ @@ -329,6 +332,7 @@ int iommufd_hwpt_alloc(struct iommufd_ucmd *ucmd) */ static const size_t iommufd_hwpt_invalidate_info_size[] = { [IOMMU_HWPT_TYPE_VTD_S1] = sizeof(struct iommu_hwpt_invalidate_intel_vtd), + [IOMMU_HWPT_TYPE_ARM_SMMUV3] = sizeof(struct iommu_hwpt_invalidate_arm_smmuv3), }; int iommufd_hwpt_invalidate(struct iommufd_ucmd *ucmd) diff --git a/drivers/iommu/iommufd/main.c b/drivers/iommu/iommufd/main.c index 514db4c26927..0b0097af7c86 100644 --- a/drivers/iommu/iommufd/main.c +++ b/drivers/iommu/iommufd/main.c @@ -280,6 +280,7 @@ union ucmd_buffer { * path. */ struct iommu_hwpt_invalidate_intel_vtd vtd; + struct iommu_hwpt_invalidate_arm_smmuv3 smmuv3; }; struct iommufd_ioctl_op { diff --git a/include/uapi/linux/iommufd.h b/include/uapi/linux/iommufd.h index 2a6c326391b2..0d5551b1b2be 100644 --- a/include/uapi/linux/iommufd.h +++ b/include/uapi/linux/iommufd.h @@ -352,10 +352,13 @@ struct iommu_vfio_ioas { * enum iommu_hwpt_type - IOMMU HWPT Type * @IOMMU_HWPT_TYPE_DEFAULT: default * @IOMMU_HWPT_TYPE_VTD_S1: Intel VT-d stage-1 page table + * @IOMMU_HWPT_TYPE_ARM_SMMUV3: ARM SMMUv3 stage-1 Context Descriptor + * table */ enum iommu_hwpt_type { IOMMU_HWPT_TYPE_DEFAULT, IOMMU_HWPT_TYPE_VTD_S1, + IOMMU_HWPT_TYPE_ARM_SMMUV3, }; /** @@ -411,6 +414,28 @@ struct iommu_hwpt_intel_vtd { __u32 __reserved; }; +/** + * struct iommu_hwpt_arm_smmuv3 - ARM SMMUv3 specific page table data + * + * @flags: page table entry attributes + * @s2vmid: Virtual machine identifier + * @s1ctxptr: Stage-1 context descriptor pointer + * @s1cdmax: Number of CDs pointed to by s1ContextPtr + * @s1fmt: Stage-1 Format + * @s1dss: Default substream + */ +struct iommu_hwpt_arm_smmuv3 { +#define IOMMU_SMMUV3_FLAG_S2 (1 << 0) /* if unset, stage-1 */ +#define IOMMU_SMMUV3_FLAG_VMID (1 << 1) /* vmid override */ + __u64 flags; + __u32 s2vmid; + __u32 __reserved; + __u64 s1ctxptr; + __u64 s1cdmax; + __u64 s1fmt; + __u64 s1dss; +}; + /** * struct iommu_hwpt_alloc - ioctl(IOMMU_HWPT_ALLOC) * @size: sizeof(struct iommu_hwpt_alloc) @@ -446,6 +471,8 @@ struct iommu_hwpt_intel_vtd { * +------------------------------+-------------------------------------+-----------+ * | IOMMU_HWPT_TYPE_VTD_S1 | struct iommu_hwpt_intel_vtd | HWPT | * +------------------------------+-------------------------------------+-----------+ + * | IOMMU_HWPT_TYPE_ARM_SMMUV3 | struct iommu_hwpt_arm_smmuv3 | IOAS/HWPT | + * +------------------------------+-------------------------------------------------+ */ struct iommu_hwpt_alloc { __u32 size; @@ -463,10 +490,12 @@ struct iommu_hwpt_alloc { /** * enum iommu_hw_info_type - IOMMU Hardware Info Types * @IOMMU_HW_INFO_TYPE_INTEL_VTD: Intel VT-d iommu info type + * @IOMMU_HW_INFO_TYPE_ARM_SMMUV3: ARM SMMUv3 iommu info type */ enum iommu_hw_info_type { IOMMU_HW_INFO_TYPE_DEFAULT, IOMMU_HW_INFO_TYPE_INTEL_VTD, + IOMMU_HW_INFO_TYPE_ARM_SMMUV3, }; /** @@ -591,6 +620,25 @@ struct iommu_hwpt_invalidate_intel_vtd { __u64 nb_granules; }; +/** + * struct iommu_hwpt_invalidate_arm_smmuv3 - ARM SMMUv3 cahce invalidation info + * @flags: boolean attributes of cache invalidation command + * @opcode: opcode of cache invalidation command + * @ssid: SubStream ID + * @granule_size: page/block size of the mapping in bytes + * @range: IOVA range to invalidate + */ +struct iommu_hwpt_invalidate_arm_smmuv3 { +#define IOMMU_SMMUV3_CMDQ_TLBI_VA_LEAF (1 << 0) + __u64 flags; + __u8 opcode; + __u8 padding[3]; + __u32 asid; + __u32 ssid; + __u32 granule_size; + struct iommu_iova_range range; +}; + /** * struct iommu_hwpt_invalidate - ioctl(IOMMU_HWPT_INVALIDATE) * @size: sizeof(struct iommu_hwpt_invalidate) @@ -609,6 +657,8 @@ struct iommu_hwpt_invalidate_intel_vtd { * +------------------------------+----------------------------------------+ * | IOMMU_HWPT_TYPE_VTD_S1 | struct iommu_hwpt_invalidate_intel_vtd | * +------------------------------+----------------------------------------+ + * | IOMMU_HWPT_TYPE_ARM_SMMUV3 | struct iommu_hwpt_invalidate_arm_smmuv3| + * +------------------------------+----------------------------------------+ */ struct iommu_hwpt_invalidate { __u32 size; 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So, it should be only setup on a kernel-managed domain only. If the attaching domain is a user-managed domain, redirect the hwpt to hwpt->parent to do it correctly. Signed-off-by: Nicolin Chen --- drivers/iommu/iommufd/device.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/iommufd/device.c b/drivers/iommu/iommufd/device.c index f95b558f5e95..a3e7d2889164 100644 --- a/drivers/iommu/iommufd/device.c +++ b/drivers/iommu/iommufd/device.c @@ -350,7 +350,8 @@ static int iommufd_group_setup_msi(struct iommufd_group *igroup, * call iommu_get_msi_cookie() on its behalf. This is necessary to setup * the MSI window so iommu_dma_prepare_msi() can install pages into our * domain after request_irq(). If it is not done interrupts will not - * work on this domain. + * work on this domain. And the msi_cookie should be always set into the + * kernel-managed (parent) domain. * * FIXME: This is conceptually broken for iommufd since we want to allow * userspace to change the domains, eg switch from an identity IOAS to a @@ -358,6 +359,8 @@ static int iommufd_group_setup_msi(struct iommufd_group *igroup, * matches what the IRQ layer actually expects in a newly created * domain. */ + if (hwpt->parent) + hwpt = hwpt->parent; if (sw_msi_start != PHYS_ADDR_MAX && !hwpt->msi_cookie) { rc = iommu_get_msi_cookie(hwpt->domain, sw_msi_start); if (rc) From patchwork Thu Mar 9 10:53:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 66795 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp230371wrd; Thu, 9 Mar 2023 03:18:32 -0800 (PST) X-Google-Smtp-Source: AK7set8SspUbNfqa9n/9UJHhsSxiX8VyUqW5QEdEY1KABGFFB+TciPWsX6DPoDsKxU7+XuuMoifW X-Received: by 2002:a17:902:dacd:b0:19a:96f0:b0f with SMTP id q13-20020a170902dacd00b0019a96f00b0fmr22501929plx.28.1678360712389; Thu, 09 Mar 2023 03:18:32 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1678360712; cv=pass; d=google.com; s=arc-20160816; b=fKAR2ac90eGyBdrgfu98j1i55A7qAvwEd++/CoQWHaxDOVZ1emeBMQaOfuJ8W7dk+p dsRwPjg4balnBLP6Ic5WKKM634lu8yElhzjZ3ybLmSMK6N2TWz7OrnrAOYm8dc1Fef9I PoPdhynPTlxw89EBkviZoFmquEaMLxcmllUhqcKZpxj3CivU5d7lORQn0kht75byuxsr D1mLDhkBOjMnuO/rhNudmVFyJyTITDC21qPmtIJoFwCVteYMbyMc5KOyU6B0u34QWq09 +bpnYVqjaGUyMy1k0cQXOCn0Ux1Fh06j4X2ErM9j9LpH7Y7dTYB5sbk50N1ReWrk/8T9 Fojw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=APls1b12/0qHWZdaJX+Nl4MRhtKgoUW4jTruISisK5Y=; b=ljfCpfHuSpXfyQcWdmJkgPGq2E2V1gfYSdryV9n4SFuh1SLZ6NJh/skSgRRGJs3moS RDC+z6xqsBsdEKxVoCHAUDp8IQ+w/KrkxqAdZBgMuCQAI9T63lYyX/esA7b5SH23d5Bv tMoQHpVAa1CPWfiJHyz/2W4T1mFwS9e0UF8EomSdfoZvByhSucvUAQOlkhhHxjbIiRGi nGM/OqtUJN57TbT5+YGWrwzyshsU4TLzEvNmaRxmm3RnV/slQAFZsXFvBkk80oKwqAhp wbhBzpuv9X6EkIsuAJDDaZ4lGHK+Q2mxzFDBVFIgrsmtuerb17KhGNFeUKp8jMGpesfC Jirg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b=Nczxip5c; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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Also, set the driver_type to IOMMU_HW_INFO_TYPE_ARM_SMMUV3 to pass the corresponding type sanity in the core. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 25 +++++++++++++++++++++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 2 ++ include/uapi/linux/iommufd.h | 14 ++++++++++++ 3 files changed, 41 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index f2425b0f0cd6..c1aac695ae0d 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2005,6 +2005,29 @@ static bool arm_smmu_capable(struct device *dev, enum iommu_cap cap) } } +static void *arm_smmu_hw_info(struct device *dev, u32 *length) +{ + struct arm_smmu_master *master = dev_iommu_priv_get(dev); + struct iommu_hw_info_smmuv3 *info; + void *base_idr; + int i; + + if (!master || !master->smmu) + return ERR_PTR(-ENODEV); + + info = kzalloc(sizeof(*info), GFP_KERNEL); + if (!info) + return ERR_PTR(-ENOMEM); + + base_idr = master->smmu->base + ARM_SMMU_IDR0; + for (i = 0; i <= 5; i++) + info->idr[i] = readl_relaxed(base_idr + 0x4 * i); + + *length = sizeof(*info); + + return info; +} + static struct iommu_domain *arm_smmu_domain_alloc(unsigned type) { struct arm_smmu_domain *smmu_domain; @@ -2845,6 +2868,7 @@ static void arm_smmu_remove_dev_pasid(struct device *dev, ioasid_t pasid) static struct iommu_ops arm_smmu_ops = { .capable = arm_smmu_capable, + .hw_info = arm_smmu_hw_info, .domain_alloc = arm_smmu_domain_alloc, .probe_device = arm_smmu_probe_device, .release_device = arm_smmu_release_device, @@ -2857,6 +2881,7 @@ static struct iommu_ops arm_smmu_ops = { .page_response = arm_smmu_page_response, .def_domain_type = arm_smmu_def_domain_type, .pgsize_bitmap = -1UL, /* Restricted during device attach */ + .driver_type = IOMMU_HW_INFO_TYPE_ARM_SMMUV3, .owner = THIS_MODULE, .default_domain_ops = &(const struct iommu_domain_ops) { .attach_dev = arm_smmu_attach_dev, diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 8d772ea8a583..ba2b4562f4b2 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -14,6 +14,8 @@ #include #include +#include + /* MMIO registers */ #define ARM_SMMU_IDR0 0x0 #define IDR0_ST_LVL GENMASK(28, 27) diff --git a/include/uapi/linux/iommufd.h b/include/uapi/linux/iommufd.h index 0d5551b1b2be..c7a37915b49c 100644 --- a/include/uapi/linux/iommufd.h +++ b/include/uapi/linux/iommufd.h @@ -519,6 +519,20 @@ struct iommu_hw_info_vtd { __aligned_u64 ecap_reg; }; +/** + * struct iommu_hw_info_smmuv3 - ARM SMMUv3 device info + * + * @flags: Must be set to 0 + * @__reserved: Must be 0 + * @idr: Implemented features for the SMMU Non-secure programming interface. + * Please refer to the chapters from 6.3.1 to 6.3.6 in the SMMUv3 Spec. + */ +struct iommu_hw_info_smmuv3 { + __u32 flags; + __u32 __reserved; + __u32 idr[6]; +}; + /** * struct iommu_hw_info - ioctl(IOMMU_DEVICE_GET_HW_INFO) * @size: sizeof(struct iommu_hw_info) From patchwork Thu Mar 9 10:53:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 66780 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp224920wrd; Thu, 9 Mar 2023 03:06:11 -0800 (PST) X-Google-Smtp-Source: AK7set+Jgbz1UKicwFZClT46SHQcGVJf2Ho0eP2d7P9Q3PG8ndTMx+Tg/HqfGHcUy0LEKV1y/xMV X-Received: by 2002:a05:6a20:6699:b0:cb:6f9c:166d with SMTP id o25-20020a056a20669900b000cb6f9c166dmr20422679pzh.43.1678359971258; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Mar 2023 10:54:46.9315 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: df00ed52-7200-42a6-deee-08db208cb2d9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF000100D1.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5748 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759887984886063574?= X-GMAIL-MSGID: =?utf-8?q?1759887984886063574?= IOMMUFD designs two iommu_domain pointers to represent two stages. The S1 iommu_domain (IOMMU_DOMAIN_NESTED type) represents the Context Descriptor table in the user space. The S2 iommu_domain (IOMMU_DOMAIN_UNMANAGED type) represents the translation table in the kernel, owned by a hypervisor. So there comes to no use case of the ARM_SMMU_DOMAIN_NESTED. Drop it, and use the type IOMMU_DOMAIN_NESTED instead. Also drop the unused arm_smmu_enable_nesting(). One following patche will configure the correct smmu_domain->stage. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 18 ------------------ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 1 - 2 files changed, 19 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index c1aac695ae0d..c5616145e2a3 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1279,7 +1279,6 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid, s1_cfg = &smmu_domain->s1_cfg; break; case ARM_SMMU_DOMAIN_S2: - case ARM_SMMU_DOMAIN_NESTED: s2_cfg = &smmu_domain->s2_cfg; break; default: @@ -2220,7 +2219,6 @@ static int arm_smmu_domain_finalise(struct iommu_domain *domain, fmt = ARM_64_LPAE_S1; finalise_stage_fn = arm_smmu_domain_finalise_s1; break; - case ARM_SMMU_DOMAIN_NESTED: case ARM_SMMU_DOMAIN_S2: ias = smmu->ias; oas = smmu->oas; @@ -2747,21 +2745,6 @@ static struct iommu_group *arm_smmu_device_group(struct device *dev) return group; } -static int arm_smmu_enable_nesting(struct iommu_domain *domain) -{ - struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); - int ret = 0; - - mutex_lock(&smmu_domain->init_mutex); - if (smmu_domain->smmu) - ret = -EPERM; - else - smmu_domain->stage = ARM_SMMU_DOMAIN_NESTED; - mutex_unlock(&smmu_domain->init_mutex); - - return ret; -} - static int arm_smmu_of_xlate(struct device *dev, struct of_phandle_args *args) { return iommu_fwspec_add_ids(dev, args->args, 1); @@ -2890,7 +2873,6 @@ static struct iommu_ops arm_smmu_ops = { .flush_iotlb_all = arm_smmu_flush_iotlb_all, .iotlb_sync = arm_smmu_iotlb_sync, .iova_to_phys = arm_smmu_iova_to_phys, - .enable_nesting = arm_smmu_enable_nesting, .free = arm_smmu_domain_free, } }; diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index ba2b4562f4b2..233bfc377267 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -704,7 +704,6 @@ struct arm_smmu_master { enum arm_smmu_domain_stage { ARM_SMMU_DOMAIN_S1 = 0, ARM_SMMU_DOMAIN_S2, - ARM_SMMU_DOMAIN_NESTED, ARM_SMMU_DOMAIN_BYPASS, }; From patchwork Thu Mar 9 10:53:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 66775 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp222829wrd; Thu, 9 Mar 2023 03:01:55 -0800 (PST) X-Google-Smtp-Source: AK7set8M89+2IYtlHe2K8DeK2IMgMGcCakWoXNLvLVWYDx/tM2neNXrHn7KBdMBrTbtMCr/VY20I X-Received: by 2002:a17:902:c946:b0:19c:be03:d1ba with SMTP id i6-20020a170902c94600b0019cbe03d1bamr24425901pla.6.1678359714909; Thu, 09 Mar 2023 03:01:54 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1678359714; cv=pass; d=google.com; s=arc-20160816; b=BOLg91W3rdBQ8J4Uq049L0oOTQyfJ9GuZUV8uIwhfUY8DuH7J7jBAideF5u5sflOaN iX52YieoomhcKO1/j5qsmr7fAeel2hrcNWiJHLVIoa4EeAqihmqR08Dx28aIobYxwdrL kwAFvoT4uCPdWYWHk6smgQh4PbTNbCBt+UIHxRokYLDchGus2h/F+O/mu85pF47u7GhT 46uV+OuXrtBEairW4Hu1xbqI3l66MKeTNLgF67apqBrDfbHUMwR3gJpmRKJVvbTypGEs NpILhHKv4PFHjq0wuzco8LLR11J/PPDrWd/5JKSluJCtHqQAlNMx/jy46f1ir6K9YUr2 klSg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=I5uh0txpedJi0zm1j3xWje6fBmSfQB17NuXIZ/aesMg=; b=pHBq0NGBNZ4Oj0oe146HDSzpVVUSHIXaieYRcAGPWgSpqaXRCwvB4Hkz4Quo1vq2SS iXwk1SRflysGbwUMxf37WoTnXT9DAEsidBGxlcHcANzY2jbIx3qHOu0Q8sJ/7TNTI3Qr HUVkPTIeUwmulkWXeyQoBD7zoAgzQ79djqxSWEeK/WKyesoXMhAf3nUkUVbaKA3oCPAS WkXWw7qPO9NO+ifuSV8Z4VyMGa8gB0gN4i82igT8gwdaF4+Wqquj+uvgG8241pyI3zsS 49755X+3UeOSAZ7N11fS2ecvKavisgw5SF5gEOpckbgMPtJRVAEb0sM5TkBzHLFBbw8C 3LBA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b=lUd7p+yk; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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Thu, 9 Mar 2023 02:54:38 -0800 Received: from drhqmail201.nvidia.com (10.126.190.180) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37; Thu, 9 Mar 2023 02:54:37 -0800 Received: from Asurada-Nvidia.nvidia.com (10.127.8.11) by mail.nvidia.com (10.126.190.180) with Microsoft SMTP Server id 15.2.986.37 via Frontend Transport; Thu, 9 Mar 2023 02:54:37 -0800 From: Nicolin Chen To: , , CC: , , , , , , , , Subject: [PATCH v1 06/14] iommu/arm-smmu-v3: Unset corresponding STE fields when s2_cfg is NULL Date: Thu, 9 Mar 2023 02:53:42 -0800 Message-ID: <995e48fe6eb9e31c71dbe8bb80d445aa34a51819.1678348754.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF000100D3:EE_|SN7PR12MB6888:EE_ X-MS-Office365-Filtering-Correlation-Id: 5644ae0f-0c37-4b76-806d-08db208cb3af X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Mar 2023 10:54:48.3315 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5644ae0f-0c37-4b76-806d-08db208cb3af X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF000100D3.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB6888 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759887716469756505?= X-GMAIL-MSGID: =?utf-8?q?1759887716469756505?= From: Eric Auger Despite the spec does not seem to mention this, on some implementations, when the STE configuration switches from an S1+S2 cfg to an S1 only one, a C_BAD_STE error would happen if dst[3] (S2TTB) is not reset. Explicitly reset those two higher 64b fields, to prevent that. Note that this is not a bug at this moment, since a 2-stage translation setup is not yet enabled, until the following patches add its support. Reported-by: Shameer Kolothum Signed-off-by: Eric Auger Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index c5616145e2a3..29e36448d23b 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1361,6 +1361,9 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid, dst[3] = cpu_to_le64(s2_cfg->vttbr & STRTAB_STE_3_S2TTB_MASK); val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_S2_TRANS); + } else { + dst[2] = 0; + dst[3] = 0; } if (master->ats_enabled) From patchwork Thu Mar 9 10:53:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 66781 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp225246wrd; Thu, 9 Mar 2023 03:06:47 -0800 (PST) X-Google-Smtp-Source: AK7set8B9IwmGtDtcEiuq5QCG3Sh18DrtnC6PEIkr90FpRpP9FYPdsJWi2a7QDltynKDBRlCj25B X-Received: by 2002:a05:6e02:1705:b0:316:f941:dbca with SMTP id u5-20020a056e02170500b00316f941dbcamr20458641ill.27.1678360007169; Thu, 09 Mar 2023 03:06:47 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1678360007; cv=pass; d=google.com; s=arc-20160816; b=lOe+MQkYjdmjgI3PxVtLCF6BRqwZ7TkJi/uBWNQPFF9H4y/X2k6v83hxscEYE8Yq3E 3BDAyetuFQ2rywSbdJNfnxgv6NGFx6n5SftygeaZBTnvWa/O1CtpsqJnu8m0IITTrND8 gQXVA1sdZss6jBS0qf9zQoL7LR9jFQ30CHzVm4zX7x09MDZ06gytSrY2DivQXiht4ZqU o0XaUNyHPEkTgZq1Cjud8vo23ETE84/CXoImGnhB7OgCyUmZTTK71EYMpXCQUHxWtdoW IWsMfXzfKFWTRIUe72VItrVWcsUnD76RhaUgBd26ZqZkoJWREsCSx3OgQDW3G/yzj5C8 W2JQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Oy679PsGKRdgAaCm07/ByNB8RFd7Yujq/wr7apZd26s=; b=ERAFOlVbBWSP8EDV3+IB8kPZinELdqUBZSe242rbRV40MV4jFIULrHf0ERXgjdu+Y6 8aOoedRzkRYLflEvJ1+9J0Yrh9BGpc0XSv9+iGrNpP4GNW0z7l/uImF/IxCd5IEoIIJn 9ZROX4tZdfsrAiU5r55JO2zVq8xkDYrcSa4BaLCaYTyCoO4l8CWezDQhx2gyGZRlIUKj lZSq55LP87xLrdCnpBmvbXzfLXjKnQLHTQQV11cyDqMq3NAaYYqgFH/m4+hB8KFt88/0 8zPYoyZhFzFdvijZ1Mf251L6fduuq7He/21sV8gyFHFLLi3DHFKe0J1D9KgS14c4YPHy mSVQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b=slVVUN6l; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Mar 2023 10:54:49.9784 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3059bac4-fc4b-462c-cc6d-08db208cb4aa X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF000100D1.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB8966 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759888022804056030?= X-GMAIL-MSGID: =?utf-8?q?1759888022804056030?= From: Eric Auger The value of the STRTAB_STE_0_CFG field can be 0b111 as the configuration for a 2-stage translation, meaning that both S1 and S2 are valid. Add it and mark the ste_live accordingly. Signed-off-by: Eric Auger Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 1 + drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 29e36448d23b..21d819979865 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1292,6 +1292,7 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid, break; case STRTAB_STE_0_CFG_S1_TRANS: case STRTAB_STE_0_CFG_S2_TRANS: + case STRTAB_STE_0_CFG_NESTED: ste_live = true; break; case STRTAB_STE_0_CFG_ABORT: diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 233bfc377267..1a93eeb993ea 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -208,6 +208,7 @@ #define STRTAB_STE_0_CFG_BYPASS 4 #define STRTAB_STE_0_CFG_S1_TRANS 5 #define STRTAB_STE_0_CFG_S2_TRANS 6 +#define STRTAB_STE_0_CFG_NESTED 7 #define STRTAB_STE_0_S1FMT GENMASK_ULL(5, 4) #define STRTAB_STE_0_S1FMT_LINEAR 0 From patchwork Thu Mar 9 10:53:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 66774 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp221541wrd; Thu, 9 Mar 2023 02:59:04 -0800 (PST) X-Google-Smtp-Source: AK7set+rDL6cdRbk8CbY3EjSebX470j8bVVbBgwNtjhXT2sK//qjMFiQQxH9CmNcP1m33hFjsHgU X-Received: by 2002:a17:903:2cb:b0:19c:f747:2517 with SMTP id s11-20020a17090302cb00b0019cf7472517mr25194256plk.1.1678359544495; Thu, 09 Mar 2023 02:59:04 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1678359544; cv=pass; d=google.com; s=arc-20160816; b=CAW8DoWHtToBHH0vUjlPig1KJWjODpnEdCYgNuYuKELAvQ024rhStgs0YthuyKdDoa BifpHVvYCBykaiaeCwpcQH0bg12ET1FzYeBu+DYGQL+ph6qzzw6D5ikh8mKKajUnU3QV YBLUBBb04hVVeAqt3GOWlLa4p6hj71wqoC2zbDVzOzl4irOFlodQG3NneNnz4QDTjGDr sKPBWnrO9B+8HovU+o5L3DV+2k7JEEDIKngbQOMZLCOKx1SbsglXj4i3oZFQpv4QMTxA 84i7fEMo3IG7OOdJqq8ZZtfAvoSkWEEJnsuoufDEddbY654Gz3N7DVxz06LJg9vlTpZz ORPw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=U6mV0v4fbbmz39mZPKbnbHbmd90snt/MKRfL1nKdO9I=; b=BubukUksD80zz+3dhfx+B/aZ2ctDOsp8ngXUg0V62yCfzrP4FFVS/yTIidsJuF7KI5 dM3BKZpQ7v7kV7CaM6rTpgLepusQbDWGgSRUmtjrNm8sydMUYICBD9RQTyPulpESODfE zNOnNVtlItma7dGIiCDmxH9Eo3ekGs88iC/zbM89ZSUpXNB7pOTU34M14Uqcp3nL70Mm bFoheZq76TDV+dDn+UtAsKOkhGh0p5xxeH3cGCWSTEfZBqTTwcxxWiq308XNHsXtsnm4 /P0hDb/dDOv19cpdP4mWgY4DSqZlVW9vROyvzePyTvO94gZI1GCoF2Ejin+I3SPz7fgL Tsig== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b=Z24a2LaK; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Mar 2023 10:54:48.3569 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: be2ff6f0-63a3-4ba8-619f-08db208cb3b3 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF000108E8.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6154 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759887538076096578?= X-GMAIL-MSGID: =?utf-8?q?1759887538076096578?= In a nested translation setup, the device is attached to a stage-1 domain that represents the guest-level Context Descriptor table. A Stream Table Entry for a 2-stage translation needs both the stage-1 Context Descriptor table info and the stage-2 Translation table information, i.e. a pair of s1_cfg and s2_cfg. Add an "s2" pointer in struct arm_smmu_domain, so a nested stage-1 domain can simply navigate its stage-2 domain for the s2_cfg pointer. Also, add a to_s2_cfg() helper for this purpose, and use it at proper places. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 25 +++++++++++++++++++-- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 1 + 2 files changed, 24 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 21d819979865..fee5977feef3 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -100,6 +100,24 @@ static void parse_driver_options(struct arm_smmu_device *smmu) } while (arm_smmu_options[++i].opt); } +static struct arm_smmu_s2_cfg *to_s2_cfg(struct arm_smmu_domain *smmu_domain) +{ + if (!smmu_domain) + return NULL; + + switch (smmu_domain->stage) { + case ARM_SMMU_DOMAIN_S1: + if (smmu_domain->s2) + return &smmu_domain->s2->s2_cfg; + return NULL; + case ARM_SMMU_DOMAIN_S2: + return &smmu_domain->s2_cfg; + case ARM_SMMU_DOMAIN_BYPASS: + default: + return NULL; + } +} + /* Low-level queue manipulation functions */ static bool queue_has_space(struct arm_smmu_ll_queue *q, u32 n) { @@ -1277,6 +1295,7 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid, switch (smmu_domain->stage) { case ARM_SMMU_DOMAIN_S1: s1_cfg = &smmu_domain->s1_cfg; + s2_cfg = to_s2_cfg(smmu_domain); break; case ARM_SMMU_DOMAIN_S2: s2_cfg = &smmu_domain->s2_cfg; @@ -1846,6 +1865,7 @@ int arm_smmu_atc_inv_domain(struct arm_smmu_domain *smmu_domain, int ssid, static void arm_smmu_tlb_inv_context(void *cookie) { struct arm_smmu_domain *smmu_domain = cookie; + struct arm_smmu_s2_cfg *s2_cfg = to_s2_cfg(smmu_domain); struct arm_smmu_device *smmu = smmu_domain->smmu; struct arm_smmu_cmdq_ent cmd; @@ -1860,7 +1880,7 @@ static void arm_smmu_tlb_inv_context(void *cookie) arm_smmu_tlb_inv_asid(smmu, smmu_domain->s1_cfg.cd.asid); } else { cmd.opcode = CMDQ_OP_TLBI_S12_VMALL; - cmd.tlbi.vmid = smmu_domain->s2_cfg.vmid; + cmd.tlbi.vmid = s2_cfg->vmid; arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); } arm_smmu_atc_inv_domain(smmu_domain, 0, 0, 0); @@ -1931,6 +1951,7 @@ static void arm_smmu_tlb_inv_range_domain(unsigned long iova, size_t size, size_t granule, bool leaf, struct arm_smmu_domain *smmu_domain) { + struct arm_smmu_s2_cfg *s2_cfg = to_s2_cfg(smmu_domain); struct arm_smmu_cmdq_ent cmd = { .tlbi = { .leaf = leaf, @@ -1943,7 +1964,7 @@ static void arm_smmu_tlb_inv_range_domain(unsigned long iova, size_t size, cmd.tlbi.asid = smmu_domain->s1_cfg.cd.asid; } else { cmd.opcode = CMDQ_OP_TLBI_S2_IPA; - cmd.tlbi.vmid = smmu_domain->s2_cfg.vmid; + cmd.tlbi.vmid = s2_cfg->vmid; } __arm_smmu_tlb_inv_range(&cmd, iova, size, granule, smmu_domain); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 1a93eeb993ea..6cf516852721 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -709,6 +709,7 @@ enum arm_smmu_domain_stage { }; struct arm_smmu_domain { + struct arm_smmu_domain *s2; struct arm_smmu_device *smmu; struct mutex init_mutex; /* Protects smmu pointer */ From patchwork Thu Mar 9 10:53:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 66777 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp224644wrd; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Mar 2023 10:54:50.0132 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 47f1d7c0-8736-4fbf-1a93-08db208cb4b0 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF000108E8.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM8PR12MB5495 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759887945335526084?= X-GMAIL-MSGID: =?utf-8?q?1759887945335526084?= In a 1-stage translation setup, a device is attached to an iommu_domain (ARM_SMMU_DOMAIN_S1) that is IOMMU_DOMAIN_UNMANAGED type. In a 2-stage translation setup, a device is attached to an iommu_domain (ARM_SMMU_DOMAIN_S1) that is IOMMU_DOMAIN_NESTED type, which must have a valid "s2" pointer for an iommu_domain (ARM_SMMU_DOMAIN_S2) that is IOMMU_DOMAIN_UNMANAGED type. Add a function to return the correct iommu_domain pointer accordingly. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index fee5977feef3..18ab5d516cf2 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2082,6 +2082,17 @@ static struct iommu_domain *arm_smmu_domain_alloc(unsigned type) return &smmu_domain->domain; } +static struct iommu_domain *arm_smmu_get_unmanaged_domain(struct device *dev) +{ + struct arm_smmu_master *master = dev_iommu_priv_get(dev); + struct arm_smmu_domain *smmu_domain = master->domain; + + if (smmu_domain->s2) + return &smmu_domain->s2->domain; + + return &smmu_domain->domain; +} + static int arm_smmu_bitmap_alloc(unsigned long *map, int span) { int idx, size = 1 << span; @@ -2878,6 +2889,7 @@ static struct iommu_ops arm_smmu_ops = { .capable = arm_smmu_capable, .hw_info = arm_smmu_hw_info, .domain_alloc = arm_smmu_domain_alloc, + .get_unmanaged_domain = arm_smmu_get_unmanaged_domain, .probe_device = arm_smmu_probe_device, .release_device = arm_smmu_release_device, .device_group = arm_smmu_device_group, From patchwork Thu Mar 9 10:53:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 66785 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp226789wrd; Thu, 9 Mar 2023 03:10:08 -0800 (PST) X-Google-Smtp-Source: AK7set9oP+gt6s+Ckg8MUKVsbtHM3yExP0nsAgf1IfiV0LEz6chrLduL7avSefvgW7KvHeoRvT1n X-Received: by 2002:a05:6a20:3b85:b0:cc:fced:f715 with SMTP id b5-20020a056a203b8500b000ccfcedf715mr18617120pzh.22.1678360208325; Thu, 09 Mar 2023 03:10:08 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1678360208; cv=pass; d=google.com; s=arc-20160816; b=gKvsY6gOOyyKvS/jlDeIIALrDTj6WlSWKChM0xUBIfWS6kbANiSCRW5eetQfaIH8s+ P4RcSm8ucKTMTDVMAUBFg95hX9xjoPN+dEWlL5lCc+IgCwJA4Yqd60FAKUoF5GORT6RQ NnY25gK8kmsZ8AIBG2tccv3wIKiUZrunDpfG6/1K7EXw7PI8cgqHw3lUqejy09KohKSr T8IA2cS8QcFecs7MW2jNH0TlMusAjN2Gq89SSa450GTkaC8q7NlmG0Hnnc7ik4k4uE6k fsCCEQrzfnKiEXyfZo9u+m5C2wIwhFXFNACb7bBFPnK/uyz5u9cQ6uMCm0gIIiqLBh6G hWbQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=qu2hNAgMKUWJWkJKPV/u8sJ3QMgIzwQ7mZzx+VX3FjM=; b=M0t7Ima5cb+wLafGyicSRf4X9AZhaIN71YTwoNlrm+PjgezO3weqq7DwQC54Kh1KVW lPgLiGHaHAO8hJSEgMdvYnTG3wKlsEmIbvUNebvB7dJk/Z+30hv3XElp+L/UOqsFPa3i cmEOZuM/GELFiaSC+Q7xDVBJMlOzEzNeSdeFGr4ml+b38UUNM8bwGSVVMIDL7/PMc4wT cCQ6a5/LSd7JmrETYzbLvGgheaM+EbOytqwykDxHetdfAumEoKAITGaMqSC9fC+NE1ti 4qjpkYGFPdwx3cpi+PkXnY1m0nOWuSueFKmy/cRXUKLCZdY5Z1vk5FVOkraJUrn0/pGg vBEw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b=NmXYk98Q; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Mar 2023 10:54:53.7753 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c4cdb2f8-ec02-4917-2953-08db208cb6ee X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF000100D1.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8365 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759888233798848294?= X-GMAIL-MSGID: =?utf-8?q?1759888233798848294?= The struct iommu_hwpt_arm_smmuv3 contains the userspace Stream Table Entry info (for ARM_SMMU_DOMAIN_S1) and an "S2" flag (for ARM_SMMU_DOMAIN_S2). Pass in a valid user_cfg pointer, so arm_smmu_domain_finalise() can handle both types of user domain finalizations. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 18ab5d516cf2..2d29f7320570 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -26,6 +26,7 @@ #include #include #include +#include #include "arm-smmu-v3.h" #include "../../dma-iommu.h" @@ -2223,7 +2224,8 @@ static int arm_smmu_domain_finalise_s2(struct arm_smmu_domain *smmu_domain, } static int arm_smmu_domain_finalise(struct iommu_domain *domain, - struct arm_smmu_master *master) + struct arm_smmu_master *master, + const struct iommu_hwpt_arm_smmuv3 *user_cfg) { int ret; unsigned long ias, oas; @@ -2235,12 +2237,18 @@ static int arm_smmu_domain_finalise(struct iommu_domain *domain, struct io_pgtable_cfg *); struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); struct arm_smmu_device *smmu = smmu_domain->smmu; + bool user_cfg_s2 = user_cfg && (user_cfg->flags & IOMMU_SMMUV3_FLAG_S2); if (domain->type == IOMMU_DOMAIN_IDENTITY) { smmu_domain->stage = ARM_SMMU_DOMAIN_BYPASS; return 0; } + if (user_cfg_s2 && !(smmu->features & ARM_SMMU_FEAT_TRANS_S2)) + return -EINVAL; + if (user_cfg_s2) + smmu_domain->stage = ARM_SMMU_DOMAIN_S2; + /* Restrict the stage to what we can actually support */ if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S1)) smmu_domain->stage = ARM_SMMU_DOMAIN_S2; @@ -2484,7 +2492,7 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) if (!smmu_domain->smmu) { smmu_domain->smmu = smmu; - ret = arm_smmu_domain_finalise(domain, master); + ret = arm_smmu_domain_finalise(domain, master, NULL); if (ret) { smmu_domain->smmu = NULL; goto out_unlock; From patchwork Thu Mar 9 10:53:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 66786 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp227327wrd; Thu, 9 Mar 2023 03:11:25 -0800 (PST) X-Google-Smtp-Source: AK7set+tE1JjWANFxIRu5aPli2fs0Qu7+nyz4guUp/qFzQuPSPe7A2KOVHR7c7j9+kMUch0bwe+v X-Received: by 2002:a17:90b:4c02:b0:23a:ad68:25a9 with SMTP id na2-20020a17090b4c0200b0023aad6825a9mr14669574pjb.43.1678360284814; Thu, 09 Mar 2023 03:11:24 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1678360284; cv=pass; d=google.com; s=arc-20160816; b=r2jj3SPHS2RYXnFl4Scl14R+pG9JBYTTllmhbdCwhOdV1u5/WoMc3bniT8dPf10bgX EygFBEESDmsw0olVATCF2tC2lAGVQnIBzRVShvAq+E5IotFHnGs5di46S8lFSVSTW/iF 4m/2wodBMh08S5wpJ0uCpO8ap7s5inWpChOM9zdbxZ2aNATLIZ4ysVlqpvFYmQAIkXoB JNxZXZIkL43kVisRCgwdNguAzCRTV2bWRyXCUDjMcULS+RBzyr8kINbSwjrrQyb5ofeg ns9hGH6R103Do6WKigbMkRw5z3OZ60ZgerJR/RlbY2Au/GMcwHWz0zktsNEpea/VvD31 dbLQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=2ZVXA4L9BTJ0E+4M8b1F5QLwtubB6Sh0NdsH8STRMr8=; b=l4/reoyoOrDxDHwbWudFUF1MG1X3w4r4pXjwMk97TSqckL5v3q5BnhxArFets6neQb 9jUFUJ23zfYapSB/aJ1XdJ+LLtW4SeRdRYthWS1ZnYj6KDfMlB2aeFaDbO/pmNXVQP7y hMXz+yCr2l/Kbuy1MgKFRTY+6uJRo6ZBgEO/Cvcm0Qoh3GL0mHbOicHPBIARQKJwIfUy rs7phQ87hXozQWQ/Bp5UOGy3eTGA5juyuOHdizOandg4wDH9Se0If/UuzsYlhoJgs5li /sM8kon6yIkn8LtD5CCNi27G6pzGkqsmztLfac56LfNi6PRfAFdPWdn2URhGvuX61COk 9sNQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b=EBzQXLRo; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Mar 2023 10:54:52.1382 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 753e7895-e0be-4266-bcd3-08db208cb5f6 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF000108E8.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6422 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759888314167839046?= X-GMAIL-MSGID: =?utf-8?q?1759888314167839046?= The arm_smmu_domain_alloc_user callback function is used for userspace to allocate iommu_domains, such as standalone stage-1 domain, nested stage-1 domain, and nested stage-2 domain. The input user_data is in the type of struct iommu_hwpt_arm_smmuv3 that contains the configurations of a nested stage-1 or a nested stage-2 iommu_domain. A NULL user_data will just opt in a standalone stage-1 domain allocation. Add a constitutive function __arm_smmu_domain_alloc to support that. Since ops->domain_alloc_user has a valid dev pointer, the master pointer is available when calling __arm_smmu_domain_alloc() in this case, meaning that arm_smmu_domain_finalise() can be done at the allocation stage. This allows IOMMUFD to initialize the hw_pagetable for the domain. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 95 ++++++++++++++------- 1 file changed, 65 insertions(+), 30 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 2d29f7320570..5ff74edfbd68 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2053,36 +2053,6 @@ static void *arm_smmu_hw_info(struct device *dev, u32 *length) return info; } -static struct iommu_domain *arm_smmu_domain_alloc(unsigned type) -{ - struct arm_smmu_domain *smmu_domain; - - if (type == IOMMU_DOMAIN_SVA) - return arm_smmu_sva_domain_alloc(); - - if (type != IOMMU_DOMAIN_UNMANAGED && - type != IOMMU_DOMAIN_DMA && - type != IOMMU_DOMAIN_DMA_FQ && - type != IOMMU_DOMAIN_IDENTITY) - return NULL; - - /* - * Allocate the domain and initialise some of its data structures. - * We can't really do anything meaningful until we've added a - * master. - */ - smmu_domain = kzalloc(sizeof(*smmu_domain), GFP_KERNEL); - if (!smmu_domain) - return NULL; - - mutex_init(&smmu_domain->init_mutex); - INIT_LIST_HEAD(&smmu_domain->devices); - spin_lock_init(&smmu_domain->devices_lock); - INIT_LIST_HEAD(&smmu_domain->mmu_notifiers); - - return &smmu_domain->domain; -} - static struct iommu_domain *arm_smmu_get_unmanaged_domain(struct device *dev) { struct arm_smmu_master *master = dev_iommu_priv_get(dev); @@ -2893,10 +2863,75 @@ static void arm_smmu_remove_dev_pasid(struct device *dev, ioasid_t pasid) arm_smmu_sva_remove_dev_pasid(domain, dev, pasid); } +static struct iommu_domain * +__arm_smmu_domain_alloc(unsigned type, + struct arm_smmu_domain *s2, + struct arm_smmu_master *master, + const struct iommu_hwpt_arm_smmuv3 *user_cfg) +{ + struct arm_smmu_domain *smmu_domain; + struct iommu_domain *domain; + int ret = 0; + + if (type == IOMMU_DOMAIN_SVA) + return arm_smmu_sva_domain_alloc(); + + if (type != IOMMU_DOMAIN_UNMANAGED && + type != IOMMU_DOMAIN_DMA && + type != IOMMU_DOMAIN_DMA_FQ && + type != IOMMU_DOMAIN_IDENTITY) + return NULL; + + /* + * Allocate the domain and initialise some of its data structures. + * We can't really finalise the domain unless a master is given. + */ + smmu_domain = kzalloc(sizeof(*smmu_domain), GFP_KERNEL); + if (!smmu_domain) + return NULL; + domain = &smmu_domain->domain; + + domain->type = type; + domain->ops = arm_smmu_ops.default_domain_ops; + + mutex_init(&smmu_domain->init_mutex); + INIT_LIST_HEAD(&smmu_domain->devices); + spin_lock_init(&smmu_domain->devices_lock); + INIT_LIST_HEAD(&smmu_domain->mmu_notifiers); + + if (master) { + smmu_domain->smmu = master->smmu; + ret = arm_smmu_domain_finalise(domain, master, user_cfg); + if (ret) { + kfree(smmu_domain); + return NULL; + } + } + + return domain; +} + +static struct iommu_domain *arm_smmu_domain_alloc(unsigned type) +{ + return __arm_smmu_domain_alloc(type, NULL, NULL, NULL); +} + +static struct iommu_domain * +arm_smmu_domain_alloc_user(struct device *dev, struct iommu_domain *parent, + const void *user_data) +{ + const struct iommu_hwpt_arm_smmuv3 *user_cfg = user_data; + struct arm_smmu_master *master = dev_iommu_priv_get(dev); + unsigned type = IOMMU_DOMAIN_UNMANAGED; + + return __arm_smmu_domain_alloc(type, NULL, master, user_cfg); +} + static struct iommu_ops arm_smmu_ops = { .capable = arm_smmu_capable, .hw_info = arm_smmu_hw_info, .domain_alloc = arm_smmu_domain_alloc, + .domain_alloc_user = arm_smmu_domain_alloc_user, .get_unmanaged_domain = arm_smmu_get_unmanaged_domain, .probe_device = arm_smmu_probe_device, .release_device = arm_smmu_release_device, From patchwork Thu Mar 9 10:53:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 66783 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp225248wrd; Thu, 9 Mar 2023 03:06:48 -0800 (PST) X-Google-Smtp-Source: AK7set+HE44xOEdJroyUuUbLxD04jCaQPZO5LMKpbIeLmp48SzD2yL/irp3TlJy+nvCr0D7GyucF X-Received: by 2002:a17:902:ea0d:b0:199:4be8:be48 with SMTP id s13-20020a170902ea0d00b001994be8be48mr22035807plg.19.1678360007935; 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This includes the "finalise" part to log in the user space Stream Table Entry info. Co-developed-by: Eric Auger Signed-off-by: Eric Auger Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 38 +++++++++++++++++++-- 1 file changed, 36 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 5ff74edfbd68..1f318b5e0921 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2214,6 +2214,19 @@ static int arm_smmu_domain_finalise(struct iommu_domain *domain, return 0; } + if (domain->type == IOMMU_DOMAIN_NESTED) { + if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S1) || + !(smmu->features & ARM_SMMU_FEAT_TRANS_S2)) { + dev_dbg(smmu->dev, "does not implement two stages\n"); + return -EINVAL; + } + smmu_domain->stage = ARM_SMMU_DOMAIN_S1; + smmu_domain->s1_cfg.s1fmt = user_cfg->s1fmt; + smmu_domain->s1_cfg.s1cdmax = user_cfg->s1cdmax; + smmu_domain->s1_cfg.cdcfg.cdtab_dma = user_cfg->s1ctxptr; + return 0; + } + if (user_cfg_s2 && !(smmu->features & ARM_SMMU_FEAT_TRANS_S2)) return -EINVAL; if (user_cfg_s2) @@ -2863,6 +2876,11 @@ static void arm_smmu_remove_dev_pasid(struct device *dev, ioasid_t pasid) arm_smmu_sva_remove_dev_pasid(domain, dev, pasid); } +static const struct iommu_domain_ops arm_smmu_nested_domain_ops = { + .attach_dev = arm_smmu_attach_dev, + .free = arm_smmu_domain_free, +}; + static struct iommu_domain * __arm_smmu_domain_alloc(unsigned type, struct arm_smmu_domain *s2, @@ -2877,11 +2895,15 @@ __arm_smmu_domain_alloc(unsigned type, return arm_smmu_sva_domain_alloc(); if (type != IOMMU_DOMAIN_UNMANAGED && + type != IOMMU_DOMAIN_NESTED && type != IOMMU_DOMAIN_DMA && type != IOMMU_DOMAIN_DMA_FQ && type != IOMMU_DOMAIN_IDENTITY) return NULL; + if (s2 && s2->stage != ARM_SMMU_DOMAIN_S2) + return NULL; + /* * Allocate the domain and initialise some of its data structures. * We can't really finalise the domain unless a master is given. @@ -2889,10 +2911,14 @@ __arm_smmu_domain_alloc(unsigned type, smmu_domain = kzalloc(sizeof(*smmu_domain), GFP_KERNEL); if (!smmu_domain) return NULL; + smmu_domain->s2 = s2; domain = &smmu_domain->domain; domain->type = type; - domain->ops = arm_smmu_ops.default_domain_ops; + if (s2) + domain->ops = &arm_smmu_nested_domain_ops; + else + domain->ops = arm_smmu_ops.default_domain_ops; mutex_init(&smmu_domain->init_mutex); INIT_LIST_HEAD(&smmu_domain->devices); @@ -2923,8 +2949,16 @@ arm_smmu_domain_alloc_user(struct device *dev, struct iommu_domain *parent, const struct iommu_hwpt_arm_smmuv3 *user_cfg = user_data; struct arm_smmu_master *master = dev_iommu_priv_get(dev); unsigned type = IOMMU_DOMAIN_UNMANAGED; + struct arm_smmu_domain *s2 = NULL; + + if (parent) { + if (parent->ops != arm_smmu_ops.default_domain_ops) + return NULL; + type = IOMMU_DOMAIN_NESTED; + s2 = to_smmu_domain(parent); + } - return __arm_smmu_domain_alloc(type, NULL, master, user_cfg); + return __arm_smmu_domain_alloc(type, s2, master, user_cfg); } static struct iommu_ops arm_smmu_ops = { From patchwork Thu Mar 9 10:53:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 66784 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp225272wrd; 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Thu, 9 Mar 2023 02:54:44 -0800 Received: from drhqmail201.nvidia.com (10.126.190.180) by drhqmail202.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37; Thu, 9 Mar 2023 02:54:44 -0800 Received: from Asurada-Nvidia.nvidia.com (10.127.8.11) by mail.nvidia.com (10.126.190.180) with Microsoft SMTP Server id 15.2.986.37 via Frontend Transport; Thu, 9 Mar 2023 02:54:43 -0800 From: Nicolin Chen To: , , CC: , , , , , , , , Subject: [PATCH v1 13/14] iommu/arm-smmu-v3: Add CMDQ_OP_TLBI_NH_VAA and CMDQ_OP_TLBI_NH_ALL Date: Thu, 9 Mar 2023 02:53:49 -0800 Message-ID: <3b059f4b0bda1e83d402248114a774186f678387.1678348754.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF000100D1:EE_|DM6PR12MB4925:EE_ X-MS-Office365-Filtering-Correlation-Id: e29bf047-9f56-4d24-76e3-08db208cb8e0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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So, the kernel driver should not assume that the guest OS will use a user space device driver that doesn't support TLBI_NH_VAA and TLBI_NH_ALL commands. Add them in the arm_smmu_cmdq_build_cmd(), to prepare for support of these two TLBI invalidation requests from the guest level. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 4 ++++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 2 ++ 2 files changed, 6 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 1f318b5e0921..ac63185ae268 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -277,6 +277,9 @@ static int arm_smmu_cmdq_build_cmd(u64 *cmd, struct arm_smmu_cmdq_ent *ent) /* Cover the entire SID range */ cmd[1] |= FIELD_PREP(CMDQ_CFGI_1_RANGE, 31); break; + case CMDQ_OP_TLBI_NH_VAA: + ent->tlbi.asid = 0; + fallthrough; case CMDQ_OP_TLBI_NH_VA: cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_VMID, ent->tlbi.vmid); fallthrough; @@ -301,6 +304,7 @@ static int arm_smmu_cmdq_build_cmd(u64 *cmd, struct arm_smmu_cmdq_ent *ent) case CMDQ_OP_TLBI_NH_ASID: cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_ASID, ent->tlbi.asid); fallthrough; + case CMDQ_OP_TLBI_NH_ALL: case CMDQ_OP_TLBI_S12_VMALL: cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_VMID, ent->tlbi.vmid); break; diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 6cf516852721..6181d6cd8b51 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -454,8 +454,10 @@ struct arm_smmu_cmdq_ent { }; } cfgi; + #define CMDQ_OP_TLBI_NH_ALL 0x10 #define CMDQ_OP_TLBI_NH_ASID 0x11 #define CMDQ_OP_TLBI_NH_VA 0x12 + #define CMDQ_OP_TLBI_NH_VAA 0x13 #define CMDQ_OP_TLBI_EL2_ALL 0x20 #define CMDQ_OP_TLBI_EL2_ASID 0x21 #define CMDQ_OP_TLBI_EL2_VA 0x22 From patchwork Thu Mar 9 10:53:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 66792 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp230261wrd; Thu, 9 Mar 2023 03:18:14 -0800 (PST) X-Google-Smtp-Source: AK7set+4kuiqX3AB/V7JGC9nUTUJLnQ+i4M+Lv3wHa9geTV9QYgYr7l0oUs1FVpKb7hHcO9YNfMB X-Received: by 2002:a17:903:451:b0:19e:73f6:9f3f with SMTP id iw17-20020a170903045100b0019e73f69f3fmr19683487plb.57.1678360694676; Thu, 09 Mar 2023 03:18:14 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1678360694; cv=pass; d=google.com; s=arc-20160816; b=M47jHu/QbTjTO3vU9bHTUHOiQ85932HsiwNS8VQQMSAsIZp1jLsX9tubXybmOQMCWo f0IKux+lKtxJJou3BnsCs1Hz2A0g1+GEh/ROvynpyAW9rLVkWH+ETVXGzEJL29zBNoSA X+BXA4BhjzxhSw/GQ9j4eIMCrvrm+33d76MrJDKWjB3oGIRBmlAmh9l+RQBnR9dXBzKu lL5KGM8NrgucPAIPqujWX+vqixvzvICmLeo4quIlwvBrrbRnYzic1bhxoi8QBq/tdE2N jVz8MG/l3fVbLHMwb6qVKqv6Jjly/X5X6mx7G74FKV82ua7XGcOzOebO//kAKkeQlqJv cY+g== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=rBztAGL4Dhn5vTJ1Bs0zPepM3SJkBS2uuAlsDyd2xI4=; b=Np2ZBaZEHXVmeGoVDW9bZ1Ju22TVW63a1lacS2w7xKk/Hazw3QsT8rryTDAoii3jTV zwz4nw1bMHLx7Q0szrvzbVdeT13s6yS3Yi+iTdkc2nU5/e0iSWbGievWOqNxSlilLFSB b9iDmZnzmsp8ueLXbEsBz8Z/zxE8IE7ZbR2d87WcUnmccQjslpqzEQm6YIp0vgtvjRHk 0F4YsfsxSVArrLm8hxqjwQfHqZ1g+Rb1X1vecbvh1RrQsk8IkifqVj3AIssOSpuMv2Zr rtGWk4C/NVruNqJBTTmOCB0iTKO6Yt7+Goxo01hzhGFxnTPhkv7Q7nj4YUkKWksmZW16 plHg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@Nvidia.com header.s=selector2 header.b=td0QXMoo; arc=pass (i=1 spf=pass spfdomain=nvidia.com dmarc=pass fromdomain=nvidia.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=nvidia.com Received: from out1.vger.email (out1.vger.email. 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The input user_data is defined in "struct iommu_hwpt_invalidate_arm_smmuv3" that contains the essential data for corresponding invalidation commands. Co-developed-by: Eric Auger Signed-off-by: Eric Auger Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 56 +++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index ac63185ae268..7d73eab5e7f4 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2880,9 +2880,65 @@ static void arm_smmu_remove_dev_pasid(struct device *dev, ioasid_t pasid) arm_smmu_sva_remove_dev_pasid(domain, dev, pasid); } +static void arm_smmu_cache_invalidate_user(struct iommu_domain *domain, + void *user_data) +{ + struct iommu_hwpt_invalidate_arm_smmuv3 *inv_info = user_data; + struct arm_smmu_cmdq_ent cmd = { .opcode = inv_info->opcode }; + struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); + struct arm_smmu_device *smmu = smmu_domain->smmu; + size_t granule_size = inv_info->granule_size; + unsigned long iova = 0; + size_t size = 0; + int ssid = 0; + + if (!smmu || !smmu_domain->s2 || domain->type != IOMMU_DOMAIN_NESTED) + return; + + switch (inv_info->opcode) { + case CMDQ_OP_CFGI_CD: + case CMDQ_OP_CFGI_CD_ALL: + return arm_smmu_sync_cd(smmu_domain, inv_info->ssid, true); + case CMDQ_OP_TLBI_NH_VA: + cmd.tlbi.asid = inv_info->asid; + fallthrough; + case CMDQ_OP_TLBI_NH_VAA: + if (!granule_size || !(granule_size & smmu->pgsize_bitmap) || + granule_size & ~(1ULL << __ffs(granule_size))) + return; + + iova = inv_info->range.start; + size = inv_info->range.last - inv_info->range.start + 1; + if (!size) + return; + + cmd.tlbi.vmid = smmu_domain->s2->s2_cfg.vmid; + cmd.tlbi.leaf = inv_info->flags & IOMMU_SMMUV3_CMDQ_TLBI_VA_LEAF; + __arm_smmu_tlb_inv_range(&cmd, iova, size, granule_size, smmu_domain); + break; + case CMDQ_OP_TLBI_NH_ASID: + cmd.tlbi.asid = inv_info->asid; + fallthrough; + case CMDQ_OP_TLBI_NH_ALL: + cmd.tlbi.vmid = smmu_domain->s2->s2_cfg.vmid; + arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); + break; + case CMDQ_OP_ATC_INV: + ssid = inv_info->ssid; + iova = inv_info->range.start; + size = inv_info->range.last - inv_info->range.start + 1; + break; + default: + return; + } + + arm_smmu_atc_inv_domain(smmu_domain, ssid, iova, size); +} + static const struct iommu_domain_ops arm_smmu_nested_domain_ops = { .attach_dev = arm_smmu_attach_dev, .free = arm_smmu_domain_free, + .cache_invalidate_user = arm_smmu_cache_invalidate_user, }; static struct iommu_domain *