From patchwork Wed Mar 8 07:33:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2 via Gcc-patches" X-Patchwork-Id: 66049 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp190129wrd; Tue, 7 Mar 2023 23:34:25 -0800 (PST) X-Google-Smtp-Source: AK7set8UMGPSknbS5fbI+aB7atyyPkoO6pcQXi06f+B27xLVEEoV9f5D+8hxQl2N/b2mW7kCmtP+ X-Received: by 2002:a17:906:fe07:b0:879:ab3:93d1 with SMTP id wy7-20020a170906fe0700b008790ab393d1mr24856707ejb.4.1678260865751; Tue, 07 Mar 2023 23:34:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1678260865; cv=none; d=google.com; s=arc-20160816; b=kQjlKy3GtyLADIWSbARWoFCXsKkheya0lvH0svrJ52H/aM3rrttM7qX/05yZC67Rpa tq8zpIAYnqqsOCKfGDxHSHXVxeiGpIRZSrPUm2SIXG6ja6WpycX0m66a3XBpY5fLBwj2 Xcjlt/rSFRTJLsurfYZLpm5XxA2jF93sZ9PL8nr2SdM+QKl0lmViRdR/lMevgLJMiNLi s4dCr2kTmOvmZ7nxrPaSY+4ZwYkNrOYFfkJkfIKYZEc0W2vYfdUsCJn+0bnvBN4Hzl+Y 0dbNePfa0P4/ymj9OQvKxGZcpqze6YEMT9rq1iQNHTSffptUWFZP7mI/aiYYEuvxUp6E 2dXQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:message-id:date:subject:cc :to:dmarc-filter:delivered-to:dkim-signature:dkim-filter; bh=4lpUQriuw9P9NBt0N0Bnuc5xMW1GjGKGtY67JOqLUk8=; b=jqWMGVvEThillob7ucOvFvii7jdrZXqTj0P1Vuh4jJFmmNzz9rHmd9EMpfCVRTj7yV i0Mpt4EQzr7ONdrZA+sCTJnaNAfe8UjEJ88/MaB1fh+V9KNcjBaHauOgBlZcxwIBXZqJ TlR5rqoY8c46vNP8oTjJO/ADJFb1vhNXmLX4VAypKK29kFAZj8+Ra6TVaXuF55rg+RVQ PyNEU58noWd3ncTAad01pdv5Qj6xA3MZfk45vA/BgrnTe/M9EvJy50qSVmkentYPMPJt ExdmPlJ65P5PI/dnHMNJpTCCvI5EQtWg3yPXSxc/547lfqAvIc+0nMtRcLj0NakJLpYD V8vA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=hvrzttA2; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from sourceware.org (ip-8-43-85-97.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id a18-20020a17090682d200b008c7ec130e89si4778460ejy.79.2023.03.07.23.34.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Mar 2023 23:34:25 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=hvrzttA2; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id BB15D38582B0 for ; Wed, 8 Mar 2023 07:34:24 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org BB15D38582B0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1678260864; bh=4lpUQriuw9P9NBt0N0Bnuc5xMW1GjGKGtY67JOqLUk8=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=hvrzttA2tLu4+6UG6BrZFzFxoBg5sF1mO6/AlCEwH2MbfWxn+wf52Ib+/FiCCuz0z MfL3uTDAtnEX3WHD8rWLayVFsbYsFAJSEv01g5I9/hytTtljCBTdtwXYa7kDR8QAtv ir8E7kY2g7F+Nfv0mW6UFyLR/H9siOm1TDA8CD2w= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by sourceware.org (Postfix) with ESMTPS id B428D3858C30 for ; Wed, 8 Mar 2023 07:33:39 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B428D3858C30 X-IronPort-AV: E=McAfee;i="6500,9779,10642"; a="316486679" X-IronPort-AV: E=Sophos;i="5.98,243,1673942400"; d="scan'208";a="316486679" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Mar 2023 23:33:38 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10642"; a="707085570" X-IronPort-AV: E=Sophos;i="5.98,243,1673942400"; d="scan'208";a="707085570" Received: from pli-ubuntu.sh.intel.com ([10.239.46.88]) by orsmga008.jf.intel.com with ESMTP; 07 Mar 2023 23:33:36 -0800 To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@sifive.com, rguenther@suse.de, pan2.li@intel.com Subject: [PATCH] RISC-V: Bugfix for rvv bool mode size adjustment Date: Wed, 8 Mar 2023 15:33:33 +0800 Message-Id: <20230308073333.814033-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-10.3 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SCC_5_SHORT_WORD_LINES, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: "pan2.li--- via Gcc-patches" From: "Li, Pan2 via Gcc-patches" Reply-To: pan2.li@intel.com Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759784065571135448?= X-GMAIL-MSGID: =?utf-8?q?1759784065571135448?= From: yes Fix the bug of the rvv bool mode size by the adjustment. Besides the mode precision (aka bit size [1, 2, 4, 8, 16, 32, 64]) of the vbool*_t, the mode size (aka byte size) will be adjusted to [1, 1, 1, 1, 2, 4, 8] according to the rvv spec 1.0 isa. The adjustment will provide correct information for the underlying redundant instruction elimiation. Given the below sample code: { vbool1_t v1 = *(vbool1_t*)in; vbool64_t v2 = *(vbool64_t*)in; *(vbool1_t*)(out + 100) = v1; *(vbool64_t*)(out + 200) = v2; } Before the size adjustment: csrr t0,vlenb slli t1,t0,1 csrr a3,vlenb sub sp,sp,t1 slli a4,a3,1 add a4,a4,sp addi a2,a1,100 vsetvli a5,zero,e8,m8,ta,ma sub a3,a4,a3 vlm.v v24,0(a0) vsm.v v24,0(a2) vsm.v v24,0(a3) addi a1,a1,200 csrr t0,vlenb vsetvli a4,zero,e8,mf8,ta,ma slli t1,t0,1 vlm.v v24,0(a3) vsm.v v24,0(a1) add sp,sp,t1 jr ra After the size adjustment: addi a3,a1,100 vsetvli a4,zero,e8,m8,ta,ma addi a1,a1,200 vlm.v v24,0(a0) vsm.v v24,0(a3) vsetvli a5,zero,e8,mf8,ta,ma vlm.v v24,0(a0) vsm.v v24,0(a1) ret Additionally, the size adjust cannot cover all possible combinations of the vbool*_t code pattern like above. We will take a look into it in another patches. PR 108185 PR 108654 gcc/ChangeLog: * config/riscv/riscv-modes.def (ADJUST_BYTESIZE): * config/riscv/riscv.cc (riscv_v_adjust_bytesize): * config/riscv/riscv.h (riscv_v_adjust_bytesize): gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pr108185-1.c: * gcc.target/riscv/rvv/base/pr108185-2.c: * gcc.target/riscv/rvv/base/pr108185-3.c: Signed-off-by: Pan Li Co-authored-by: Ju-Zhe Zhong Signed-off-by: Pan Li Signed-off-by: Pan Li --- gcc/config/riscv/riscv-modes.def | 14 ++++++------ gcc/config/riscv/riscv.cc | 22 +++++++++++++++++++ gcc/config/riscv/riscv.h | 1 + .../gcc.target/riscv/rvv/base/pr108185-1.c | 2 +- .../gcc.target/riscv/rvv/base/pr108185-2.c | 2 +- .../gcc.target/riscv/rvv/base/pr108185-3.c | 2 +- 6 files changed, 33 insertions(+), 10 deletions(-) diff --git a/gcc/config/riscv/riscv-modes.def b/gcc/config/riscv/riscv-modes.def index 110bddce851..4cf7cf8b1c6 100644 --- a/gcc/config/riscv/riscv-modes.def +++ b/gcc/config/riscv/riscv-modes.def @@ -64,13 +64,13 @@ ADJUST_ALIGNMENT (VNx16BI, 1); ADJUST_ALIGNMENT (VNx32BI, 1); ADJUST_ALIGNMENT (VNx64BI, 1); -ADJUST_BYTESIZE (VNx1BI, riscv_vector_chunks * riscv_bytes_per_vector_chunk); -ADJUST_BYTESIZE (VNx2BI, riscv_vector_chunks * riscv_bytes_per_vector_chunk); -ADJUST_BYTESIZE (VNx4BI, riscv_vector_chunks * riscv_bytes_per_vector_chunk); -ADJUST_BYTESIZE (VNx8BI, riscv_vector_chunks * riscv_bytes_per_vector_chunk); -ADJUST_BYTESIZE (VNx16BI, riscv_vector_chunks * riscv_bytes_per_vector_chunk); -ADJUST_BYTESIZE (VNx32BI, riscv_vector_chunks * riscv_bytes_per_vector_chunk); -ADJUST_BYTESIZE (VNx64BI, riscv_v_adjust_nunits (VNx64BImode, 8)); +ADJUST_BYTESIZE (VNx1BI, riscv_v_adjust_bytesize (VNx1BImode, 1)); +ADJUST_BYTESIZE (VNx2BI, riscv_v_adjust_bytesize (VNx2BImode, 1)); +ADJUST_BYTESIZE (VNx4BI, riscv_v_adjust_bytesize (VNx4BImode, 1)); +ADJUST_BYTESIZE (VNx8BI, riscv_v_adjust_bytesize (VNx8BImode, 1)); +ADJUST_BYTESIZE (VNx16BI, riscv_v_adjust_bytesize (VNx16BImode, 2)); +ADJUST_BYTESIZE (VNx32BI, riscv_v_adjust_bytesize (VNx32BImode, 4)); +ADJUST_BYTESIZE (VNx64BI, riscv_v_adjust_bytesize (VNx64BImode, 8)); ADJUST_PRECISION (VNx1BI, riscv_v_adjust_precision (VNx1BImode, 1)); ADJUST_PRECISION (VNx2BI, riscv_v_adjust_precision (VNx2BImode, 2)); diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index e7b7d87cebc..428fbb28fae 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -1003,6 +1003,28 @@ riscv_v_adjust_nunits (machine_mode mode, int scale) return scale; } +/* Call from ADJUST_BYTESIZE in riscv-modes.def. Return the correct + BYTE size for corresponding machine_mode. */ + +poly_int64 +riscv_v_adjust_bytesize (machine_mode mode, int scale) +{ + if (riscv_v_ext_vector_mode_p (mode)) + { + poly_uint16 mode_size = GET_MODE_SIZE (mode); + + if (maybe_eq (mode_size, (uint16_t)-1)) + mode_size = riscv_vector_chunks * scale; + + if (known_gt (mode_size, BYTES_PER_RISCV_VECTOR)) + mode_size = BYTES_PER_RISCV_VECTOR; + + return mode_size; + } + + return scale; +} + /* Call from ADJUST_PRECISION in riscv-modes.def. Return the correct PRECISION size for corresponding machine_mode. */ diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index 15b9317a8ce..66fb07d6652 100644 --- a/gcc/config/riscv/riscv.h +++ b/gcc/config/riscv/riscv.h @@ -1026,6 +1026,7 @@ extern unsigned riscv_bytes_per_vector_chunk; extern poly_uint16 riscv_vector_chunks; extern poly_int64 riscv_v_adjust_nunits (enum machine_mode, int); extern poly_int64 riscv_v_adjust_precision (enum machine_mode, int); +extern poly_int64 riscv_v_adjust_bytesize (enum machine_mode, int); /* The number of bits and bytes in a RVV vector. */ #define BITS_PER_RISCV_VECTOR (poly_uint16 (riscv_vector_chunks * riscv_bytes_per_vector_chunk * 8)) #define BYTES_PER_RISCV_VECTOR (poly_uint16 (riscv_vector_chunks * riscv_bytes_per_vector_chunk)) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c index e70960c5b6d..c3d0b10271a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c @@ -65,4 +65,4 @@ test_vbool1_then_vbool64(int8_t * restrict in, int8_t * restrict out) { /* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */ /* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */ /* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */ -/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 18 } } */ +/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-2.c index dcc7a644a88..bd13ba916da 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-2.c @@ -65,4 +65,4 @@ test_vbool2_then_vbool64(int8_t * restrict in, int8_t * restrict out) { /* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */ /* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */ /* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */ -/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 17 } } */ +/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-3.c index 3af0513e006..99928f7b1cc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-3.c @@ -65,4 +65,4 @@ test_vbool4_then_vbool64(int8_t * restrict in, int8_t * restrict out) { /* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */ /* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */ /* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */ -/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 16 } } */ +/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */