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[34.125.176.30]) by smtp.gmail.com with ESMTPSA id h3-20020aa796c3000000b0055fc0a132aasm9863407pfq.92.2022.10.18.12.01.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Oct 2022 12:01:38 -0700 (PDT) From: Rishabh Agrawal To: LKML , len.brown@intel.com, drake@endlessm.com, rafael.j.wysocki@intel.com, mingo@redhat.com, tglx@linutronix.de Cc: vaibhav.shankar@intel.com, biernacki@google.com, zwisler@google.com, mattedavis@google.com, Rishabh Agrawal , Borislav Petkov , Dave Hansen , Feng Tang , Greg Kroah-Hartman , "H. Peter Anvin" , Peter Zijlstra , x86@kernel.org Subject: [PATCH v2] Add hardcoded crystal clock for KabyLake Date: Tue, 18 Oct 2022 19:01:32 +0000 Message-Id: <20221018190124.v2.1.I918ccc908c5c836c1e21e01d2cf6f59b0157bcc3@changeid> X-Mailer: git-send-email 2.38.0.413.g74048e4d9e-goog MIME-Version: 1.0 X-Spam-Status: No, score=-2.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747053701126162884?= X-GMAIL-MSGID: =?utf-8?q?1747053701126162884?= Set KabyLake crystal clock manually since the TSC calibration is off by 0.5%. All the tests that are based on the timer/clock will fail in this case. The HPET has been disabled by upstream due to PC10 issue causing the 3 hatch devices, dratini, jinlon, and kohaku to not calibrate the clock precisely. These 3 devices are KabyLake devices. Intel team has verified that all KBL devices have 24.0 MHz clock frequency, therefore this change is valid. Signed-off-by: Rishabh Agrawal --- Changes in v2: - Adding Thomas Gleixner, Daniel Drake, Rafael Wysocki, Len brown and Ingo to review since you worked on this. arch/x86/kernel/tsc.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index cafacb2e58cc..63a06224fa48 100644 --- a/arch/x86/kernel/tsc.c +++ b/arch/x86/kernel/tsc.c @@ -644,10 +644,21 @@ unsigned long native_calibrate_tsc(void) * Denverton SoCs don't report crystal clock, and also don't support * CPUID.0x16 for the calculation below, so hardcode the 25MHz crystal * clock. + * + * Intel KabyLake devices' clocks are off by 0.5% when using the below + * calculation, so hardcode 24.0 MHz crystal clock. */ - if (crystal_khz == 0 && - boot_cpu_data.x86_model == INTEL_FAM6_ATOM_GOLDMONT_D) - crystal_khz = 25000; + if (crystal_khz == 0) { + switch (boot_cpu_data.x86_model) { + case INTEL_FAM6_ATOM_GOLDMONT_D: + crystal_khz = 25000; + break; + case INTEL_FAM6_KABYLAKE_L: + crystal_khz = 24000; + break; + } + + } /* * TSC frequency reported directly by CPUID is a "hardware reported"