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[90.63.244.31]) by smtp.googlemail.com with ESMTPSA id o2-20020a05600c510200b003e208cec49bsm23156746wms.3.2023.03.06.07.14.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Mar 2023 07:14:04 -0800 (PST) From: Jerome Brunet To: Neil Armstrong , Kevin Hilman , linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org Cc: Jerome Brunet , Rob Herring , Krzysztof Kozlowski , linux-kernel@vger.kernel.org Subject: [PATCH] arm64: dts: amlogic: gxl: use gxl mdio multiplexer Date: Mon, 6 Mar 2023 16:13:54 +0100 Message-Id: <20230306151354.132973-1-jbrunet@baylibre.com> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 X-Patchwork-Bot: notify X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759632516320504206?= X-GMAIL-MSGID: =?utf-8?q?1759632516320504206?= So the far, GXL SoCs were using the generic mmio register based mdio multiplexer. This properly sets one of the glue register but the SoC actually has 3 of those registers. One of them sets the ID under which the internal phy will advertise itself. If nothing sets this register before linux boots (like u-boot), the internal phy path is broken. To address this problem, a dedicated MDIO mux driver has been introduced. Switch to this new driver. Signed-off-by: Jerome Brunet --- arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 25 +++++++++++----------- 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi index 6f3c2bc36919..17bcfa4702e1 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi @@ -773,16 +773,23 @@ mux { }; }; - eth-phy-mux@55c { - compatible = "mdio-mux-mmioreg", "mdio-mux"; + eth_phy_mux: mdio@558 { + reg = <0x0 0x558 0x0 0xc>; + compatible = "amlogic,gxl-mdio-mux"; #address-cells = <1>; #size-cells = <0>; - reg = <0x0 0x55c 0x0 0x4>; - mux-mask = <0xffffffff>; + clocks = <&clkc CLKID_FCLK_DIV4>; + clock-names = "ref"; mdio-parent-bus = <&mdio0>; - internal_mdio: mdio@e40908ff { - reg = <0xe40908ff>; + external_mdio: mdio@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + internal_mdio: mdio@1 { + reg = <0x1>; #address-cells = <1>; #size-cells = <0>; @@ -793,12 +800,6 @@ internal_phy: ethernet-phy@8 { max-speed = <100>; }; }; - - external_mdio: mdio@2009087f { - reg = <0x2009087f>; - #address-cells = <1>; - #size-cells = <0>; - }; }; };