From patchwork Mon Mar 6 09:52:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Minda Chen X-Patchwork-Id: 64564 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp1760609wrd; Mon, 6 Mar 2023 02:25:19 -0800 (PST) X-Google-Smtp-Source: AK7set9lVmwPbGpjUzqJAk3Vxfz4LLkynEqkiMXn2jGd9q6QHav9taYAAv9cB2Yn44RrTBxuRSd1 X-Received: by 2002:a17:906:fe44:b0:88f:8a5:b4cd with SMTP id wz4-20020a170906fe4400b0088f08a5b4cdmr11577759ejb.1.1678098319544; Mon, 06 Mar 2023 02:25:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1678098319; cv=none; d=google.com; s=arc-20160816; b=wqXYnM9UEKzSjOSEllO4O9sqN7UxEX3/+fo/ODt4fmW3TBtOzWgoCe1q9Z+JRrcKJx xZF//x9xAsXh4ynYRHpZHuI6Bw41I6yt8wExbEGuWZNsAKENvEqHY3mWXE85gooyPcpf 2FvBEUNM7US6ANBlyBl2NlsTS+uygGaBSRr9qC/PXnWMgNvahrcQ9b53lUW5nbfo6G7d I47dLhBi2vM2YflVkMAZaV2No+H4wk/viPqXYFsUt7depDARYR30gwNvwwCzjN/McH2Y Oy06fjZLXP2AZPQcXj+JjXUEgVBJiyxvWzzVNK3VWolUV4HkPzkb+Rpi+CKWy7EAJkZu Qx/A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:message-id:date:subject:cc:to:from; bh=u8wUq6pUZ1l6dZlMKukFMXuRD+BORAM2bdE6p8Lo3oA=; b=gI/hYOzcwNg8hgZwDbEDLACit4K3Dr4OsOG4MwqF16p+mvqwBcOmODeWPYQiup8PTX ZlGiuHxT3wMOHml43AfRjz0L+Ae9heKrkisIibDvXCuhBrrTafYSLI+D5tazps6gkBJe qGYGxIFMFR5FLCk8/bgDPfjcIzLPgCeaZuHI3853thMleTLBdeu49YhApnX2VCwcpSEz 3TTUnETt2ipsZSim2M5hAYrQTDYQVpZsaPtbsaPRXAv9fxNN5SAtzTVilYaBIY46mKvJ MzzJZ1QburyMzoQGoz7PZHZcgR5PoDZThdrYxciZtVNJ+hKghanV/p5WBIbMyBbBI0Qb Bw7Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id x17-20020a1709064a9100b008df5a5088ccsi2434797eju.94.2023.03.06.02.24.56; Mon, 06 Mar 2023 02:25:19 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230019AbjCFJxH (ORCPT + 99 others); Mon, 6 Mar 2023 04:53:07 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40396 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229842AbjCFJxE (ORCPT ); Mon, 6 Mar 2023 04:53:04 -0500 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 11557D516; Mon, 6 Mar 2023 01:53:01 -0800 (PST) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id BCDE024E2EE; Mon, 6 Mar 2023 17:52:59 +0800 (CST) Received: from EXMBX071.cuchost.com (172.16.6.81) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 6 Mar 2023 17:52:59 +0800 Received: from ubuntu.localdomain (183.27.97.46) by EXMBX071.cuchost.com (172.16.6.81) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 6 Mar 2023 17:52:59 +0800 From: Minda Chen To: Emil Renner Berthing , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski CC: , , , Minda Chen Subject: [PATCH 1/3] dt-bindings: phy: Add StarFive JH7110 USB dt-binding Date: Mon, 6 Mar 2023 17:52:57 +0800 Message-ID: <20230306095257.25957-1-minda.chen@starfivetech.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-Originating-IP: [183.27.97.46] X-ClientProxiedBy: EXCAS064.cuchost.com (172.16.6.24) To EXMBX071.cuchost.com (172.16.6.81) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,RCVD_IN_MSPIKE_H2, SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759613623769672499?= X-GMAIL-MSGID: =?utf-8?q?1759613623769672499?= Add StarFive JH7110 SoC USB 3.0 phy dt-binding. USB controller is cadence USB 3.0 IP. Signed-off-by: Minda Chen --- .../bindings/phy/starfive,jh7110-usb-phy.yaml | 116 ++++++++++++++++++ 1 file changed, 116 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml b/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml new file mode 100644 index 000000000000..05b6c47d4a86 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml @@ -0,0 +1,116 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/starfive,jh7110-usb-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive USB 2.0 and 3.0 PHY + +maintainers: + - Minda Chen + +properties: + compatible: + items: + - const: starfive,jh7110-usb-phy + + reg: + maxItems: 2 + + reg-names: + items: + - const: usb3 + - const: usb2 + + clocks: + maxItems: 8 + + clock-names: + items: + - const: usb_125m + - const: usb0_app_125 + - const: usb0_lpm + - const: usb0_stb + - const: usb0_apb + - const: usb0_axi + - const: usb0_utmi_apb + + resets: + items: + - description: USB0_PWRUP reset + - description: USB0_APB reset + - description: USB0_AXI reset + - description: USB0_UTMI_APB reset + + starfive,sys-syscon: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + items: + - description: phandle to System Register Controller sys_syscon node. + - description: offset of SYS_SYSCONSAIF__SYSCFG register for USB. + description: + The phandle to System Register Controller syscon node and the offset + of SYS_SYSCONSAIF__SYSCFG register for USB. + + starfive,stg-syscon: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - description: phandle to System Register Controller stg_syscon node. + - description: offset of STG_SYSCONSAIF__SYSCFG register for USB. + description: + The phandle to System Register Controller syscon node and the offset + of STG_SYSCONSAIF__SYSCFG register for USB. Total 4 regsisters offset + for USB. + + dr_mode: + description: PHY mode. + enum: + - host + - peripheral + - otg + + starfive,usb2-only + description: Set USB using usb 2.0 phy. Supprt USB 2.0 only + + '#phy-cells': + const: 0 + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - reset + - starfive,sys-syscon + - starfive,stg-syscon + - dr_mode + - '#phy-cells' + +additionalProperties: false + +examples: + - | + usbphy@10200000 { + compatible = "starfive,jh7110-usb"; + reg = <0x0 0x10210000 0x0 0x1000>, + <0x0 0x10200000 0x0 0x1000>; + reg-names = "usb3", "usb2"; + clocks = <&syscrg 95>, + <&stgcrg 6>, + <&stgcrg 4>, + <&stgcrg 5>, + <&stgcrg 1>, + <&stgcrg 3>, + <&stgcrg 2>; + clock-names = "usb_125m", "usb0_app_125", "usb0_lpm", + "usb0_stb", "usb0_apb", "usb0_axi", "usb0_utmi_apb"; + resets = <&stgcrg 10>, + <&stgcrg 8>, + <&stgcrg 7>, + <&stgcrg 9>; + starfive,stg-syscon = <&stg_syscon 0x4 0xc4 0x148 0x1f4>; + starfive,sys-syscon = <&sys_syscon 0x18>; + dr_mode = "host"; + #phy-cells = <0>; + }; From patchwork Mon Mar 6 09:53:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Minda Chen X-Patchwork-Id: 64550 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp1758482wrd; Mon, 6 Mar 2023 02:18:50 -0800 (PST) X-Google-Smtp-Source: AK7set/LfBZPV8pHGEbxqS1bWXa/rjfZmkIrBVXRwoXO/eg5UdLN4fMxhIi+kArWluYSd+d8I6by X-Received: by 2002:a17:902:7285:b0:19e:7bcf:b32 with SMTP id d5-20020a170902728500b0019e7bcf0b32mr8599478pll.24.1678097930349; Mon, 06 Mar 2023 02:18:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1678097930; cv=none; d=google.com; s=arc-20160816; b=u5gbrM/AZTWtvrd/hcVD2f8FhIeRDRCO4XS57LMy0PvqnKmLsPJoJ0ltUf0G5XSbq3 W8kAxXNZvBNIWPGjlW4FmB1/2CsFEAsZVEjPXAcCWl9i5C7FsYO8JntLgm2m9SZ5OLiR eFlyYY4oe+WPOpkHzesfXQjEK7vSgkc3ARPTWGdkapPvf0PDfmsoXwEYimpVAvR1m5CD WCl+d3ve+r1l3Z6JPT6G1vZNL0jmBSgcAk9Ggi5Wz//yxxaNUO9GZMk9dhiHS6gcNjup ocn5CV5jdQwINhdjTypB0/JWQbZwIE3zyqYvyrxq++kS8/eUVVmQ5OuU4wWYzzTiGBoo tq3w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:message-id:date:subject:cc:to:from; bh=/4nTc5ReJt2VnU9PrmxC1LkWZteZ0QlNOwK6CwzRUsw=; b=pL2Y/E6ogo5c1EgfDsjgVn5DAM+XvoAIKwoFxb7y+nemgNzFiIXKPlHfBeuK0abmcP UVfduWAmyE66B6IqgB8Kg8KJKt3gJQMmrY/tYEzIhLLn3uegTuzLhvikETUr0s6VAZYB 4PtZTgb9HIVdIxM/wLfrVis4Ar56fQIHJce0Ui4STV/CPHAWFGe0gsKTUkkVgjQ/6Q3f 0HLIxTNI/zOrsLJLtMMJ84wFDrETb8yi7qyBmL1oaJrw8SDcA1sLsfZTj8go/1IKrS3Z p8QqDGzKFtm3wDCUToFvq1+g7LmmTy4/GnE9l2de36GKa99hoD9I1g3QfV2womadi9VZ bLUA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id kc7-20020a17090333c700b0019cd6d11f0fsi8455958plb.377.2023.03.06.02.18.25; Mon, 06 Mar 2023 02:18:50 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229742AbjCFJxz (ORCPT + 99 others); Mon, 6 Mar 2023 04:53:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41892 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229634AbjCFJxw (ORCPT ); Mon, 6 Mar 2023 04:53:52 -0500 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4C7952128E; Mon, 6 Mar 2023 01:53:43 -0800 (PST) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 1E4CD24DBBD; Mon, 6 Mar 2023 17:53:42 +0800 (CST) Received: from EXMBX071.cuchost.com (172.16.6.81) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 6 Mar 2023 17:53:42 +0800 Received: from ubuntu.localdomain (183.27.97.46) by EXMBX071.cuchost.com (172.16.6.81) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 6 Mar 2023 17:53:41 +0800 From: Minda Chen To: Emil Renner Berthing , Pawel Laszczak , Greg Kroah-Hartman , "Peter Chen" , Roger Quadros , "Aswath Govindraju" , Philipp Zabel CC: , , , Minda Chen Subject: [PATCH 2/3] usb: cdns3: add StarFive JH7110 USB glue layer Date: Mon, 6 Mar 2023 17:53:39 +0800 Message-ID: <20230306095339.26006-1-minda.chen@starfivetech.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-Originating-IP: [183.27.97.46] X-ClientProxiedBy: EXCAS064.cuchost.com (172.16.6.24) To EXMBX071.cuchost.com (172.16.6.81) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759613215308226485?= X-GMAIL-MSGID: =?utf-8?q?1759613215308226485?= There is a Cadence USB3 core for JH7110 SoCs, the cdns core is the child for this glue layer device. Signed-off-by: Minda Chen --- MAINTAINERS | 7 + drivers/usb/cdns3/Kconfig | 11 + drivers/usb/cdns3/Makefile | 1 + drivers/usb/cdns3/cdns3-starfive.c | 399 +++++++++++++++++++++++++++++ 4 files changed, 418 insertions(+) create mode 100644 drivers/usb/cdns3/cdns3-starfive.c diff --git a/MAINTAINERS b/MAINTAINERS index ee21213d4388..2a9e89922cad 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19957,6 +19957,13 @@ M: William Qiu S: Supported F: Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml +STARFIVE JH71X0 USB PHY DRIVERS +M: Emil Renner Berthing +M: Minda Chen +S: Maintained +F: Documentation/devicetree/bindings/phy/starfive,jh7110-usb*.yaml +F: drivers/usb/cdns3/cdns3-starfive.c + STATIC BRANCH/CALL M: Peter Zijlstra M: Josh Poimboeuf diff --git a/drivers/usb/cdns3/Kconfig b/drivers/usb/cdns3/Kconfig index b98ca0a1352a..a0b0a2c5430b 100644 --- a/drivers/usb/cdns3/Kconfig +++ b/drivers/usb/cdns3/Kconfig @@ -78,6 +78,17 @@ config USB_CDNS3_IMX For example, imx8qm and imx8qxp. +config USB_CDNS3_STARFIVE + tristate "Cadence USB3 support on StarFive SoC platforms" + depends on SOC_STARFIVE || COMPILE_TEST || USB_CDNS3 + help + Say 'Y' or 'M' here if you are building for StarFive SoCs + platforms that contain Cadence USB3 controller core. + + e.g. JH7110. + + If you choose to build this driver as module it will + be dynamically linked and module will be called cdns3-starfive.ko endif if USB_CDNS_SUPPORT diff --git a/drivers/usb/cdns3/Makefile b/drivers/usb/cdns3/Makefile index 61edb2f89276..48dfae75b5aa 100644 --- a/drivers/usb/cdns3/Makefile +++ b/drivers/usb/cdns3/Makefile @@ -24,6 +24,7 @@ endif obj-$(CONFIG_USB_CDNS3_PCI_WRAP) += cdns3-pci-wrap.o obj-$(CONFIG_USB_CDNS3_TI) += cdns3-ti.o obj-$(CONFIG_USB_CDNS3_IMX) += cdns3-imx.o +obj-$(CONFIG_USB_CDNS3_STARFIVE) += cdns3-starfive.o cdnsp-udc-pci-y := cdnsp-pci.o diff --git a/drivers/usb/cdns3/cdns3-starfive.c b/drivers/usb/cdns3/cdns3-starfive.c new file mode 100644 index 000000000000..54d9978cfa59 --- /dev/null +++ b/drivers/usb/cdns3/cdns3-starfive.c @@ -0,0 +1,399 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * cdns-starfive.c - StarFive specific Glue layer for Cadence USB Controller + * + * Copyright (C) 2022 Starfive, Inc. + * Author: yanhong + * Author: Mason Huo + * Author: Minda Chen + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "core.h" + +#define USB_STRAP_HOST BIT(17) +#define USB_STRAP_DEVICE BIT(18) +#define USB_STRAP_MASK GENMASK(18, 16) + +#define USB_SUSPENDM_HOST BIT(19) +#define USB_SUSPENDM_DEVICE (0 << 19) +#define USB_SUSPENDM_MASK BIT(19) + +#define USB_SUSPENDM_BYPS BIT(20) +#define USB_REFCLK_MODE BIT(23) +#define USB_PLL_EN BIT(22) +#define USB_PDRSTN_SPLIT BIT(17) + +#define PCIE_CKREF_SRC_MASK GENMASK(19, 18) +#define PCIE_CLK_SEL_MASK GENMASK(21, 20) +#define PCIE_PHY_MODE BIT(20) +#define PCIE_PHY_MODE_MASK GENMASK(21, 20) +#define PCIE_USB3_BUS_WIDTH_MASK GENMASK(3, 2) +#define PCIE_USB3_RATE_MASK GENMASK(6, 5) +#define PCIE_USB3_RX_STANDBY_MASK BIT(7) +#define PCIE_USB3_PHY_ENABLE BIT(4) +#define PCIE_USB3_PHY_PLL_CTL_OFF (0x1f * 4) + +#define USB_125M_CLK_RATE 125000000 + +#define USB_LS_KEEPALIVE_OFF 0x4 +#define USB_LS_KEEPALIVE_ENABLE BIT(4) + +#define USB3_DOWN_SS_MODE BIT(4) + +struct cdns_starfive { + struct device *dev; + struct regmap *stg_syscon; + struct regmap *sys_syscon; + struct reset_control *resets; + struct clk_bulk_data *clks; + int num_clks; + struct clk *usb_125m_clk; + u32 sys_offset; + u32 stg_offset_4; + u32 stg_offset_196; + u32 stg_offset_328; + u32 stg_offset_500; + bool usb2_only; + enum usb_dr_mode mode; + void __iomem *phybase_20; + void __iomem *phybase_30; +}; + +static int cdns_mode_init(struct platform_device *pdev, + struct cdns_starfive *data) +{ + enum usb_dr_mode mode; + + /* Init usb 2.0 utmi phy */ + regmap_update_bits(data->stg_syscon, data->stg_offset_4, + USB_SUSPENDM_BYPS, USB_SUSPENDM_BYPS); + regmap_update_bits(data->stg_syscon, data->stg_offset_4, + USB_PLL_EN, USB_PLL_EN); + regmap_update_bits(data->stg_syscon, data->stg_offset_4, + USB_REFCLK_MODE, USB_REFCLK_MODE); + + if (data->usb2_only) { + /* Disconnect usb 3.0 phy mode */ + regmap_update_bits(data->sys_syscon, data->sys_offset, + USB_PDRSTN_SPLIT, USB_PDRSTN_SPLIT); + } else { + /* Config usb 3.0 pipe phy */ + regmap_update_bits(data->stg_syscon, data->stg_offset_196, + PCIE_CKREF_SRC_MASK, 0); + regmap_update_bits(data->stg_syscon, data->stg_offset_196, + PCIE_CLK_SEL_MASK, 0); + regmap_update_bits(data->stg_syscon, data->stg_offset_328, + PCIE_PHY_MODE_MASK, PCIE_PHY_MODE); + regmap_update_bits(data->stg_syscon, data->stg_offset_500, + PCIE_USB3_BUS_WIDTH_MASK, 0); + regmap_update_bits(data->stg_syscon, data->stg_offset_500, + PCIE_USB3_RATE_MASK, 0); + regmap_update_bits(data->stg_syscon, data->stg_offset_500, + PCIE_USB3_RX_STANDBY_MASK, 0); + regmap_update_bits(data->stg_syscon, data->stg_offset_500, + PCIE_USB3_PHY_ENABLE, PCIE_USB3_PHY_ENABLE); + + /* Connect usb 3.0 phy mode */ + regmap_update_bits(data->sys_syscon, data->sys_offset, + USB_PDRSTN_SPLIT, 0); + } + mode = usb_get_dr_mode(&pdev->dev); + data->mode = mode; + + switch (mode) { + case USB_DR_MODE_HOST: + regmap_update_bits(data->stg_syscon, + data->stg_offset_4, + USB_STRAP_MASK, + USB_STRAP_HOST); + regmap_update_bits(data->stg_syscon, + data->stg_offset_4, + USB_SUSPENDM_MASK, + USB_SUSPENDM_HOST); + break; + + case USB_DR_MODE_PERIPHERAL: + regmap_update_bits(data->stg_syscon, data->stg_offset_4, + USB_STRAP_MASK, USB_STRAP_DEVICE); + regmap_update_bits(data->stg_syscon, data->stg_offset_4, + USB_SUSPENDM_MASK, USB_SUSPENDM_DEVICE); + break; + + case USB_DR_MODE_UNKNOWN: + case USB_DR_MODE_OTG: + default: + break; + } + + return 0; +} + + +static int cdns_clk_rst_init(struct cdns_starfive *data) +{ + int ret; + + data->usb_125m_clk = devm_clk_get(data->dev, "usb_125m"); + if (IS_ERR(data->usb_125m_clk)) { + dev_err(data->dev, "Failed to get usb 125m clock\n"); + ret = PTR_ERR(data->usb_125m_clk); + goto exit; + } + + data->num_clks = devm_clk_bulk_get_all(data->dev, &data->clks); + if (data->num_clks < 0) { + dev_err(data->dev, "Failed to get usb clocks\n"); + ret = -ENODEV; + goto exit; + } + + /* Needs to set the USB_125M clock explicitly, + * since it's divided from pll0 clock, and the pll0 clock + * changes per the cpu frequency. + */ + ret = clk_set_rate(data->usb_125m_clk, USB_125M_CLK_RATE); + if (ret) { + dev_err(data->dev, "Failed to set usb 125m clock\n"); + goto exit; + } + ret = clk_bulk_prepare_enable(data->num_clks, data->clks); + if (ret) { + dev_err(data->dev, "Failed to enable clocks\n"); + goto exit; + } + + data->resets = devm_reset_control_array_get_exclusive(data->dev); + if (IS_ERR(data->resets)) { + ret = PTR_ERR(data->resets); + dev_err(data->dev, "Failed to get usb resets"); + goto err_clk_init; + } + ret = reset_control_deassert(data->resets); + goto exit; + +err_clk_init: + clk_bulk_disable_unprepare(data->num_clks, data->clks); +exit: + return ret; +} + +static void cdns_starfive_set_phy(struct cdns_starfive *data) +{ + unsigned int val; + + if (data->mode != USB_DR_MODE_PERIPHERAL) { + /* Enable the LS speed keep-alive signal */ + val = readl(data->phybase_20 + USB_LS_KEEPALIVE_OFF); + val |= USB_LS_KEEPALIVE_ENABLE; + writel(val, data->phybase_20 + USB_LS_KEEPALIVE_OFF); + } + + if (!data->usb2_only) { + /* Configuare spread-spectrum mode: down-spread-spectrum */ + writel(USB3_DOWN_SS_MODE, data->phybase_30 + PCIE_USB3_PHY_PLL_CTL_OFF); + } +} + +static int cdns_starfive_phy_init(struct platform_device *pdev, + struct cdns_starfive *data) +{ + struct device *dev = &pdev->dev; + int ret = 0; + + data->phybase_20 = devm_platform_ioremap_resource_byname(pdev, "usb2"); + if (IS_ERR(data->phybase_20)) { + dev_err(dev, "Can't map phybase_20 IOMEM resource\n"); + ret = PTR_ERR(data->phybase_20); + goto get_res_err; + } + + data->phybase_30 = devm_platform_ioremap_resource_byname(pdev, "usb3"); + if (IS_ERR(data->phybase_30)) { + dev_err(dev, "Can't map phybase_30 IOMEM resource\n"); + ret = PTR_ERR(data->phybase_30); + goto get_res_err; + } + + cdns_starfive_set_phy(data); + +get_res_err: + return ret; +} + +static int cdns_starfive_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *node = pdev->dev.of_node; + struct cdns_starfive *data; + struct of_phandle_args args; + int ret; + + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + platform_set_drvdata(pdev, data); + + data->dev = dev; + + data->usb2_only = device_property_read_bool(dev, "starfive,usb2-only"); + ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node, + "starfive,stg-syscon", 4, 0, &args); + if (ret < 0) { + dev_err(dev, "Failed to parse starfive,stg-syscon\n"); + return -EINVAL; + } + + data->stg_syscon = syscon_node_to_regmap(args.np); + of_node_put(args.np); + if (IS_ERR(data->stg_syscon)) + return PTR_ERR(data->stg_syscon); + data->stg_offset_4 = args.args[0]; + data->stg_offset_196 = args.args[1]; + data->stg_offset_328 = args.args[2]; + data->stg_offset_500 = args.args[3]; + + ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node, + "starfive,sys-syscon", 1, 0, &args); + if (ret < 0) { + dev_err(dev, "Failed to parse starfive,sys-syscon\n"); + return -EINVAL; + } + + data->sys_syscon = syscon_node_to_regmap(args.np); + of_node_put(args.np); + if (IS_ERR(data->sys_syscon)) + return PTR_ERR(data->sys_syscon); + data->sys_offset = args.args[0]; + + cdns_mode_init(pdev, data); + + ret = cdns_clk_rst_init(data); + if (ret < 0) { + dev_err(&pdev->dev, "Failed to init usb clk reset: %d\n", ret); + goto exit; + } + + ret = cdns_starfive_phy_init(pdev, data); + if (ret) { + dev_err(dev, "Failed to init sratfive usb phy: %d\n", ret); + goto exit; + } + + ret = of_platform_populate(node, NULL, NULL, dev); + if (ret) { + dev_err(dev, "Failed to create children: %d\n", ret); + goto exit; + } + + device_set_wakeup_capable(dev, true); + pm_runtime_set_active(dev); + pm_runtime_enable(dev); + + dev_info(dev, "usb mode %d %s probe success\n", + data->mode, data->usb2_only ? "2.0" : "3.0"); + + return 0; +exit: + return ret; +} + +static int cdns_starfive_remove_core(struct device *dev, void *c) +{ + struct platform_device *pdev = to_platform_device(dev); + + platform_device_unregister(pdev); + + return 0; +} + +static int cdns_starfive_remove(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct cdns_starfive *data = dev_get_drvdata(dev); + + pm_runtime_get_sync(dev); + device_for_each_child(dev, NULL, cdns_starfive_remove_core); + + reset_control_assert(data->resets); + clk_bulk_disable_unprepare(data->num_clks, data->clks); + pm_runtime_disable(dev); + pm_runtime_put_noidle(dev); + platform_set_drvdata(pdev, NULL); + + return 0; +} + +#ifdef CONFIG_PM +static int cdns_starfive_resume(struct device *dev) +{ + struct cdns_starfive *data = dev_get_drvdata(dev); + int ret; + + ret = clk_set_rate(data->usb_125m_clk, USB_125M_CLK_RATE); + if (ret) + goto err; + + ret = clk_bulk_prepare_enable(data->num_clks, data->clks); + if (ret) + goto err; + + ret = reset_control_deassert(data->resets); + if (ret) + goto err; + + cdns_starfive_set_phy(data); +err: + return ret; +} + +static int cdns_starfive_suspend(struct device *dev) +{ + struct cdns_starfive *data = dev_get_drvdata(dev); + + clk_bulk_disable_unprepare(data->num_clks, data->clks); + reset_control_assert(data->resets); + + return 0; +} +#endif + +static const struct dev_pm_ops cdns_starfive_pm_ops = { + SET_RUNTIME_PM_OPS(cdns_starfive_suspend, cdns_starfive_resume, NULL) + SET_SYSTEM_SLEEP_PM_OPS(cdns_starfive_suspend, cdns_starfive_resume) +}; + +static const struct of_device_id cdns_starfive_of_match[] = { + { .compatible = "starfive,jh7110-usb", }, + {}, +}; +MODULE_DEVICE_TABLE(of, cdns_starfive_of_match); + +static struct platform_driver cdns_starfive_driver = { + .probe = cdns_starfive_probe, + .remove = cdns_starfive_remove, + .driver = { + .name = "cdns3-starfive", + .of_match_table = cdns_starfive_of_match, + .pm = &cdns_starfive_pm_ops, + }, +}; + +module_platform_driver(cdns_starfive_driver); + +MODULE_ALIAS("platform:cdns3-starfive"); +MODULE_AUTHOR("YanHong Wang "); +MODULE_AUTHOR("Mason Huo "); +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("Cadence USB3 StarFive Glue Layer"); From patchwork Mon Mar 6 09:54:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Minda Chen X-Patchwork-Id: 64566 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp1760807wrd; Mon, 6 Mar 2023 02:25:49 -0800 (PST) X-Google-Smtp-Source: AK7set/94k6O+7hbTe6WLSbao3kz8Wi3OF4VooMsr6FDNDYEe4yN1ha88GTu+3Xb72nL9AQV8YcR X-Received: by 2002:a17:906:fe0c:b0:8b3:b74:aeb5 with SMTP id wy12-20020a170906fe0c00b008b30b74aeb5mr13403231ejb.30.1678098349620; Mon, 06 Mar 2023 02:25:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1678098349; cv=none; d=google.com; s=arc-20160816; b=RDVFzuBkwq4lrkzZXk0BrYQTCJq8wAEc7XfRS0BAZDi4wc1sxSSBDqaeehoA/MDkTV 3PW0qebaLZTENi165nQQwXEfEraGmCQ20taLBV/oPPFLP2njSInRLacU5iHrXf/y8y16 KjrvtD/IGAndUIIK1QMrS2TcanTgkI4C6YXhQOA/yAy5qVUv/iJ8iqJDWSOGQ9BikCVu UrasZYwr+iuVfkuNIf+Lwo0vd/j2eOV3yOiYTllYptqgsORvgeXU35iYyK1+JuxNAkFv eN/uBwVNeXZCILCq+1HSoIBcw1HMnmAITFa6cG54prtc/9SPnV8PA5FU1zDseI/4MsRP HgRw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:message-id:date:subject:cc:to:from; bh=EfCVX4rHjCmG7jNbrZX35hDqwKNRkKruugLzdWrHUPg=; b=mKAlraTonODVsFvsvErg2be4sGw0gemUOiw7NtfD3JBEhUl2SJN6u3QjYwyh2juwKy Hik09IlrRMUL5nBwOl+s4nzAThiDyGJrSiGwRnjvMsY4i7yfPZYHkB5x4SansNypWxvM sld+O1o85aqbDTkDaWYtur/NVGxyjbSOFiHQFcE0t5aFJqtrpY2873+9qu7ldkzE4z3f Co0Bj69SPAGbYaG4l886XgX+qqqDHHkZqw4RggPQclBIGRtK0e+CuviluLlDLqhwF3K/ E9GczHY+qV+QAB3c9RTn8nun4F8q7OByWTbscvmYuNKosooWPK9MqubCzZJ3XIre2c+/ pg7w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id le16-20020a170907171000b008d21d51c307si8321768ejc.383.2023.03.06.02.25.06; Mon, 06 Mar 2023 02:25:49 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229960AbjCFJyW (ORCPT + 99 others); Mon, 6 Mar 2023 04:54:22 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42658 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229634AbjCFJyU (ORCPT ); Mon, 6 Mar 2023 04:54:20 -0500 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B2F351EBD0; Mon, 6 Mar 2023 01:54:11 -0800 (PST) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 4F44724DBBD; Mon, 6 Mar 2023 17:54:10 +0800 (CST) Received: from EXMBX071.cuchost.com (172.16.6.81) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 6 Mar 2023 17:54:10 +0800 Received: from ubuntu.localdomain (183.27.97.46) by EXMBX071.cuchost.com (172.16.6.81) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 6 Mar 2023 17:54:09 +0800 From: Minda Chen To: Emil Renner Berthing , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou CC: , , , Minda Chen Subject: [PATCH 3/3] dts: usb: add StarFive JH7110 USB dts configuration. Date: Mon, 6 Mar 2023 17:54:08 +0800 Message-ID: <20230306095408.26057-1-minda.chen@starfivetech.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-Originating-IP: [183.27.97.46] X-ClientProxiedBy: EXCAS064.cuchost.com (172.16.6.24) To EXMBX071.cuchost.com (172.16.6.81) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759613655446762645?= X-GMAIL-MSGID: =?utf-8?q?1759613655446762645?= USB phy dts configuration. Also includes Cadence USB subnode configuration. Signed-off-by: Minda Chen --- .../jh7110-starfive-visionfive-2.dtsi | 6 +++ arch/riscv/boot/dts/starfive/jh7110.dtsi | 39 +++++++++++++++++++ 2 files changed, 45 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi index e8b8f4346fdd..2a9ed8b9ee25 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi @@ -244,3 +244,9 @@ }; }; }; + +&usb0 { + starfive,usb2-only; + dr_mode = "peripheral"; + status = "okay"; +}; diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index be180f23963e..ee665cdc3510 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -628,5 +628,44 @@ starfive,sysreg = <&sys_syscon 0x9c 0x1 0x3e>; status = "disabled"; }; + + usb0: usbphy@10200000 { + compatible = "starfive,jh7110-usb"; + reg = <0x0 0x10210000 0x0 0x1000>, + <0x0 0x10200000 0x0 0x1000>; + reg-names = "usb3", "usb2"; + clocks = <&syscrg JH7110_SYSCLK_USB_125M>, + <&stgcrg JH7110_STGCLK_USB0_APP_125>, + <&stgcrg JH7110_STGCLK_USB0_LPM>, + <&stgcrg JH7110_STGCLK_USB0_STB>, + <&stgcrg JH7110_STGCLK_USB0_APB>, + <&stgcrg JH7110_STGCLK_USB0_AXI>, + <&stgcrg JH7110_STGCLK_USB0_UTMI_APB>; + clock-names = "usb_125m", "usb0_app_125", "usb0_lpm", + "usb0_stb", "usb0_apb", "usb0_axi", "usb0_utmi_apb"; + resets = <&stgcrg JH7110_STGRST_USB0_PWRUP>, + <&stgcrg JH7110_STGRST_USB0_APB>, + <&stgcrg JH7110_STGRST_USB0_AXI>, + <&stgcrg JH7110_STGRST_USB0_UTMI_APB>; + starfive,stg-syscon = <&stg_syscon 0x4 0xc4 0x148 0x1f4>; + starfive,sys-syscon = <&sys_syscon 0x18>; + status = "disabled"; + #address-cells = <2>; + #size-cells = <2>; + #interrupt-cells = <1>; + #phy-cells = <0>; + ranges; + usbdrd_cdns3: usb@10100000 { + compatible = "cdns,usb3"; + reg = <0x0 0x10100000 0x0 0x10000>, + <0x0 0x10110000 0x0 0x10000>, + <0x0 0x10120000 0x0 0x10000>; + reg-names = "otg", "xhci", "dev"; + interrupts = <100>, <108>, <110>; + interrupt-names = "host", "peripheral", "otg"; + phy-names = "cdns3,usb3-phy", "cnds3,usb2-phy"; + maximum-speed = "super-speed"; + }; + }; }; };