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[72.83.177.149]) by smtp.gmail.com with ESMTPSA id do20-20020a05620a2b1400b006ec9f5e3396sm2694658qkb.72.2022.10.18.08.55.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Oct 2022 08:55:03 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Linus Walleij , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH v3 1/3] arm64: dts: qcom: msm8994: Correct SPI10 CS pin Date: Tue, 18 Oct 2022 11:54:48 -0400 Message-Id: <20221018155450.39816-1-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747041509407541692?= X-GMAIL-MSGID: =?utf-8?q?1747041509407541692?= The GPIO55 is part of SPI10 pins, not its chip-select. Probably the intention was to use one of dedicated chip-select GPIOs: 47 or 67. GPIO47 is used for UART2, so choose GPIO67. Signed-off-by: Krzysztof Kozlowski --- Changes since v2: 1. None Changes since v1: 1. None Not tested on hardware. --- arch/arm64/boot/dts/qcom/msm8994.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index ded5b7ceeaf9..7a582a5fe3a8 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -897,7 +897,7 @@ default { }; cs { function = "gpio"; - pins = "gpio55"; + pins = "gpio67"; drive-strength = <2>; bias-disable; }; From patchwork Tue Oct 18 15:54:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 4238 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp2032456wrs; Tue, 18 Oct 2022 08:57:57 -0700 (PDT) X-Google-Smtp-Source: AMsMyM41yQx87dbT7ePzNbntgmU3ka0ANB3aVT3tQbff/OcNCTNbITIOQEwLPBQqayU+uTwYGJcp X-Received: by 2002:a17:90b:4b42:b0:20d:954e:28d with SMTP id mi2-20020a17090b4b4200b0020d954e028dmr37304640pjb.93.1666108677548; Tue, 18 Oct 2022 08:57:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666108677; cv=none; d=google.com; s=arc-20160816; b=xEHoUDIUYsBVb4cp+dTpck2DfkWgLaY2wB1GGclpxH3VlAmSETGfGKO1ucPptTZbhP IcwF9H9+swU2GpjXaIBGX0CXPhziqWjZIbBj70sahd/USyoULSlBjh6DfbNkR38mKdAx JsrUCWUqPRl12DnvATbBvBNliSa+sGQ+46ocOVRVR4Ulus1ZozTg/zGBLu+GjIFfmztx AW5FAwAsIZY4FSkjvVMxBZZ8V/DV7Pt3RMUjENVtnXUk1RXElLVAYMed1T0F9o616cWc 1DLhZUWFPXNGgQmqYpBWh57yI9SlkfkspqbnF23VuyKUlMsZQWd5MejR2FYUlfrE0vxE oAiw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Xc2NVIS+up6/c37L1B/Cw/y4CrJluRmxAFhRc2VwdXI=; b=flq/mTWCn2wY/QTgZu2s8E0HFIoPA4JEdSdbhPPk/EvfQG/kTFr1vVrMAeHJ/zzG6A zOoyPSKeCGDnwuizZ45S/EBPmwYDQMT7U0zyneAsZqBWSFhLSa+zpyJp2Fyex2jGfe66 /xNDGSGuIaKVl/exSVWsjJzBVVZhK2B51lEn7qRS0Tb/ZD+d2PmCMdTx36lDW2KpulgY cO30i2Fg6qjLl2UNEL9G+Nc8q3JkBXA4pUzaNriI1PzZfiyeldmRMf5KZmBgOPuSuxBP 7l/RgTKATYmrYm1LR3PvWm2h2ZnZTV0jx7BK0awYiLTscnkjH5QtFgOVxeUmHpa2AORW eACg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Qi5d3gmp; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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[72.83.177.149]) by smtp.gmail.com with ESMTPSA id do20-20020a05620a2b1400b006ec9f5e3396sm2694658qkb.72.2022.10.18.08.55.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Oct 2022 08:55:08 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Linus Walleij , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH v3 2/3] arm64: dts: qcom: msm8994: Align TLMM pin configuration with DT schema Date: Tue, 18 Oct 2022 11:54:49 -0400 Message-Id: <20221018155450.39816-2-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221018155450.39816-1-krzysztof.kozlowski@linaro.org> References: <20221018155450.39816-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747041572713948736?= X-GMAIL-MSGID: =?utf-8?q?1747041572713948736?= DT schema expects TLMM pin configuration nodes to be named with '-state' suffix and their optional children with '-pins' suffix. Order the "function" and "pins" property to match other DTS. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio --- Changes since v2: 1. None Changes since v1: 1. Add Rb tag. --- .../dts/qcom/msm8994-msft-lumia-octagon.dtsi | 8 +- .../qcom/msm8994-sony-xperia-kitakami.dtsi | 6 +- arch/arm64/boot/dts/qcom/msm8994.dtsi | 130 +++++++++--------- 3 files changed, 74 insertions(+), 70 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi index f9d8bd09e074..63568f73e9d3 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi @@ -881,28 +881,28 @@ &sdhc2 { }; &tlmm { - grip_default: grip-default { + grip_default: grip-default-state { pins = "gpio39"; function = "gpio"; drive-strength = <6>; bias-pull-down; }; - grip_sleep: grip-sleep { + grip_sleep: grip-sleep-state { pins = "gpio39"; function = "gpio"; drive-strength = <2>; bias-pull-down; }; - hall_front_default: hall-front-default { + hall_front_default: hall-front-default-state { pins = "gpio42"; function = "gpio"; drive-strength = <2>; bias-disable; }; - hall_back_default: hall-back-default { + hall_back_default: hall-back-default-state { pins = "gpio75"; function = "gpio"; drive-strength = <2>; diff --git a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi index ff60b7004d26..a390af54c715 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi @@ -477,15 +477,17 @@ &sdhc2 { }; &tlmm { - ts_int_active: ts-int-active { + ts_int_active: ts-int-active-state { pins = "gpio42"; + function = "gpio"; drive-strength = <2>; bias-disable; input-enable; }; - ts_reset_active: ts-reset-active { + ts_reset_active: ts-reset-active-state { pins = "gpio109"; + function = "gpio"; drive-strength = <2>; bias-disable; output-low; diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index 7a582a5fe3a8..ba687e64ba3c 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -773,254 +773,256 @@ tlmm: pinctrl@fd510000 { interrupt-controller; #interrupt-cells = <2>; - blsp1_uart2_default: blsp1-uart2-default { - function = "blsp_uart2"; + blsp1_uart2_default: blsp1-uart2-default-state { pins = "gpio4", "gpio5"; + function = "blsp_uart2"; drive-strength = <16>; bias-disable; }; - blsp1_uart2_sleep: blsp1-uart2-sleep { - function = "gpio"; + blsp1_uart2_sleep: blsp1-uart2-sleep-state { pins = "gpio4", "gpio5"; + function = "gpio"; drive-strength = <2>; bias-pull-down; }; - blsp2_uart2_default: blsp2-uart2-default { + blsp2_uart2_default: blsp2-uart2-default-state { + pins = "gpio45", "gpio46", "gpio47", "gpio48"; function = "blsp_uart8"; - pins = "gpio45", "gpio46", - "gpio47", "gpio48"; drive-strength = <16>; bias-disable; }; - blsp2_uart2_sleep: blsp2-uart2-sleep { + blsp2_uart2_sleep: blsp2-uart2-sleep-state { + pins = "gpio45", "gpio46", "gpio47", "gpio48"; function = "gpio"; - pins = "gpio45", "gpio46", - "gpio47", "gpio48"; drive-strength = <2>; bias-disable; }; - i2c1_default: i2c1-default { - function = "blsp_i2c1"; + i2c1_default: i2c1-default-state { pins = "gpio2", "gpio3"; + function = "blsp_i2c1"; drive-strength = <2>; bias-disable; }; - i2c1_sleep: i2c1-sleep { - function = "gpio"; + i2c1_sleep: i2c1-sleep-state { pins = "gpio2", "gpio3"; + function = "gpio"; drive-strength = <2>; bias-disable; }; - i2c2_default: i2c2-default { - function = "blsp_i2c2"; + i2c2_default: i2c2-default-state { pins = "gpio6", "gpio7"; + function = "blsp_i2c2"; drive-strength = <2>; bias-disable; }; - i2c2_sleep: i2c2-sleep { - function = "gpio"; + i2c2_sleep: i2c2-sleep-state { pins = "gpio6", "gpio7"; + function = "gpio"; drive-strength = <2>; bias-disable; }; - i2c4_default: i2c4-default { - function = "blsp_i2c4"; + i2c4_default: i2c4-default-state { pins = "gpio19", "gpio20"; + function = "blsp_i2c4"; drive-strength = <2>; bias-disable; }; - i2c4_sleep: i2c4-sleep { - function = "gpio"; + i2c4_sleep: i2c4-sleep-state { pins = "gpio19", "gpio20"; + function = "gpio"; drive-strength = <2>; bias-pull-down; input-enable; }; - i2c5_default: i2c5-default { - function = "blsp_i2c5"; + i2c5_default: i2c5-default-state { pins = "gpio23", "gpio24"; + function = "blsp_i2c5"; drive-strength = <2>; bias-disable; }; - i2c5_sleep: i2c5-sleep { - function = "gpio"; + i2c5_sleep: i2c5-sleep-state { pins = "gpio23", "gpio24"; + function = "gpio"; drive-strength = <2>; bias-disable; }; - i2c6_default: i2c6-default { - function = "blsp_i2c6"; + i2c6_default: i2c6-default-state { pins = "gpio28", "gpio27"; + function = "blsp_i2c6"; drive-strength = <2>; bias-disable; }; - i2c6_sleep: i2c6-sleep { - function = "gpio"; + i2c6_sleep: i2c6-sleep-state { pins = "gpio28", "gpio27"; + function = "gpio"; drive-strength = <2>; bias-disable; }; - i2c7_default: i2c7-default { - function = "blsp_i2c7"; + i2c7_default: i2c7-default-state { pins = "gpio44", "gpio43"; + function = "blsp_i2c7"; drive-strength = <2>; bias-disable; }; - i2c7_sleep: i2c7-sleep { - function = "gpio"; + i2c7_sleep: i2c7-sleep-state { pins = "gpio44", "gpio43"; + function = "gpio"; drive-strength = <2>; bias-disable; }; - blsp2_spi10_default: blsp2-spi10-default { - default { - function = "blsp_spi10"; + blsp2_spi10_default: blsp2-spi10-default-state { + default-pins { pins = "gpio53", "gpio54", "gpio55"; + function = "blsp_spi10"; drive-strength = <10>; bias-pull-down; }; - cs { - function = "gpio"; + + cs-pins { pins = "gpio67"; + function = "gpio"; drive-strength = <2>; bias-disable; }; }; - blsp2_spi10_sleep: blsp2-spi10-sleep { + blsp2_spi10_sleep: blsp2-spi10-sleep-state { pins = "gpio53", "gpio54", "gpio55"; + function = "gpio"; drive-strength = <2>; bias-disable; }; - i2c11_default: i2c11-default { - function = "blsp_i2c11"; + i2c11_default: i2c11-default-state { pins = "gpio83", "gpio84"; + function = "blsp_i2c11"; drive-strength = <2>; bias-disable; }; - i2c11_sleep: i2c11-sleep { - function = "gpio"; + i2c11_sleep: i2c11-sleep-state { pins = "gpio83", "gpio84"; + function = "gpio"; drive-strength = <2>; bias-disable; }; - blsp1_spi1_default: blsp1-spi1-default { - default { - function = "blsp_spi1"; + blsp1_spi1_default: blsp1-spi1-default-state { + default-pins { pins = "gpio0", "gpio1", "gpio3"; + function = "blsp_spi1"; drive-strength = <10>; bias-pull-down; }; - cs { - function = "gpio"; + + cs-pins { pins = "gpio8"; + function = "gpio"; drive-strength = <2>; bias-disable; }; }; - blsp1_spi1_sleep: blsp1-spi1-sleep { + blsp1_spi1_sleep: blsp1-spi1-sleep-state { pins = "gpio0", "gpio1", "gpio3"; + function = "gpio"; drive-strength = <2>; bias-disable; }; - sdc1_clk_on: clk-on { + sdc1_clk_on: clk-on-state { pins = "sdc1_clk"; bias-disable; drive-strength = <16>; }; - sdc1_clk_off: clk-off { + sdc1_clk_off: clk-off-state { pins = "sdc1_clk"; bias-disable; drive-strength = <2>; }; - sdc1_cmd_on: cmd-on { + sdc1_cmd_on: cmd-on-state { pins = "sdc1_cmd"; bias-pull-up; drive-strength = <8>; }; - sdc1_cmd_off: cmd-off { + sdc1_cmd_off: cmd-off-state { pins = "sdc1_cmd"; bias-pull-up; drive-strength = <2>; }; - sdc1_data_on: data-on { + sdc1_data_on: data-on-state { pins = "sdc1_data"; bias-pull-up; drive-strength = <8>; }; - sdc1_data_off: data-off { + sdc1_data_off: data-off-state { pins = "sdc1_data"; bias-pull-up; drive-strength = <2>; }; - sdc1_rclk_on: rclk-on { + sdc1_rclk_on: rclk-on-state { pins = "sdc1_rclk"; bias-pull-down; }; - sdc1_rclk_off: rclk-off { + sdc1_rclk_off: rclk-off-state { pins = "sdc1_rclk"; bias-pull-down; }; - sdc2_clk_on: sdc2-clk-on { + sdc2_clk_on: sdc2-clk-on-state { pins = "sdc2_clk"; bias-disable; drive-strength = <10>; }; - sdc2_clk_off: sdc2-clk-off { + sdc2_clk_off: sdc2-clk-off-state { pins = "sdc2_clk"; bias-disable; drive-strength = <2>; }; - sdc2_cmd_on: sdc2-cmd-on { + sdc2_cmd_on: sdc2-cmd-on-state { pins = "sdc2_cmd"; bias-pull-up; drive-strength = <10>; }; - sdc2_cmd_off: sdc2-cmd-off { + sdc2_cmd_off: sdc2-cmd-off-state { pins = "sdc2_cmd"; bias-pull-up; drive-strength = <2>; }; - sdc2_data_on: sdc2-data-on { + sdc2_data_on: sdc2-data-on-state { pins = "sdc2_data"; bias-pull-up; drive-strength = <10>; }; - sdc2_data_off: sdc2-data-off { + sdc2_data_off: sdc2-data-off-state { pins = "sdc2_data"; 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[72.83.177.149]) by smtp.gmail.com with ESMTPSA id do20-20020a05620a2b1400b006ec9f5e3396sm2694658qkb.72.2022.10.18.08.55.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Oct 2022 08:55:12 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Linus Walleij , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski , Rob Herring Subject: [PATCH v3 3/3] dt-bindings: pinctrl: qcom,msm8994: convert to dtschema Date: Tue, 18 Oct 2022 11:54:50 -0400 Message-Id: <20221018155450.39816-3-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221018155450.39816-1-krzysztof.kozlowski@linaro.org> References: <20221018155450.39816-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747041525321203650?= X-GMAIL-MSGID: =?utf-8?q?1747041525321203650?= Convert Qualcomm MSM8994 pin controller bindings to DT schema. Keep the parsing of pin configuration subnodes consistent with other Qualcomm schemas (children named with '-state' suffix, their children with '-pins'). Signed-off-by: Krzysztof Kozlowski Reviewed-by: Rob Herring --- Changes since v2: 1. Add Rb tag. 2. Drop entire drive-strength (not needed, brought by common TLMM schema). Changes since v1: 1. Drop default:2 for drive strength --- .../bindings/pinctrl/qcom,msm8994-pinctrl.txt | 186 ------------------ .../pinctrl/qcom,msm8994-pinctrl.yaml | 162 +++++++++++++++ 2 files changed, 162 insertions(+), 186 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,msm8994-pinctrl.txt create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,msm8994-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8994-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,msm8994-pinctrl.txt deleted file mode 100644 index da52df6273bc..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8994-pinctrl.txt +++ /dev/null @@ -1,186 +0,0 @@ -Qualcomm MSM8994 TLMM block - -This binding describes the Top Level Mode Multiplexer block found in the -MSM8994 platform. - -- compatible: - Usage: required - Value type: - Definition: Should contain one of: - "qcom,msm8992-pinctrl", - "qcom,msm8994-pinctrl". - -- reg: - Usage: required - Value type: - Definition: the base address and size of the TLMM register space. - -- interrupts: - Usage: required - Value type: - Definition: should specify the TLMM summary IRQ. - -- interrupt-controller: - Usage: required - Value type: - Definition: identifies this node as an interrupt controller - -- #interrupt-cells: - Usage: required - Value type: - Definition: must be 2. Specifying the pin number and flags, as defined - in - -- gpio-controller: - Usage: required - Value type: - Definition: identifies this node as a gpio controller - -- #gpio-cells: - Usage: required - Value type: - Definition: must be 2. Specifying the pin number and flags, as defined - in - -- gpio-ranges: - Usage: required - Definition: see ../gpio/gpio.txt - -- gpio-reserved-ranges: - Usage: optional - Definition: see ../gpio/gpio.txt - -Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for -a general description of GPIO and interrupt bindings. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -The pin configuration nodes act as a container for an arbitrary number of -subnodes. Each of these subnodes represents some desired configuration for a -pin, a group, or a list of pins or groups. This configuration can include the -mux function to select on those pin(s)/group(s), and various pin configuration -parameters, such as pull-up, drive strength, etc. - - -PIN CONFIGURATION NODES: - -The name of each subnode is not important; all subnodes should be enumerated -and processed purely based on their content. - -Each subnode only affects those parameters that are explicitly listed. In -other words, a subnode that lists a mux function but no pin configuration -parameters implies no information about any pin configuration parameters. -Similarly, a pin subnode that describes a pullup parameter implies no -information about e.g. the mux function. - - -The following generic properties as defined in pinctrl-bindings.txt are valid -to specify in a pin configuration subnode: - -- pins: - Usage: required - Value type: - Definition: List of gpio pins affected by the properties specified in - this subnode. - - Valid pins are: - gpio0-gpio145 - Supports mux, bias and drive-strength - - sdc1_clk, sdc1_cmd, sdc1_data sdc1_rclk, sdc2_clk, - sdc2_cmd, sdc2_data - Supports bias and drive-strength - -- function: - Usage: required - Value type: - Definition: Specify the alternative function to be configured for the - specified pins. Functions are only valid for gpio pins. - Valid values are: - - audio_ref_clk, blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c4, blsp_i2c5, - blsp_i2c6, blsp_i2c7, blsp_i2c8, blsp_i2c9, blsp_i2c10, blsp_i2c11, - blsp_i2c12, blsp_spi1, blsp_spi1_cs1, blsp_spi1_cs2, blsp_spi1_cs3, - blsp_spi2, blsp_spi2_cs1, blsp_spi2_cs2, blsp_spi2_cs3, blsp_spi3, - blsp_spi4, blsp_spi5, blsp_spi6, blsp_spi7, blsp_spi8, blsp_spi9, - blsp_spi10, blsp_spi10_cs1, blsp_spi10_cs2, blsp_spi10_cs3, blsp_spi11, - blsp_spi12, blsp_uart1, blsp_uart2, blsp_uart3, blsp_uart4, blsp_uart5, - blsp_uart6, blsp_uart7, blsp_uart8, blsp_uart9, blsp_uart10, blsp_uart11, - blsp_uart12, blsp_uim1, blsp_uim2, blsp_uim3, blsp_uim4, blsp_uim5, - blsp_uim6, blsp_uim7, blsp_uim8, blsp_uim9, blsp_uim10, blsp_uim11, - blsp_uim12, blsp11_i2c_scl_b, blsp11_i2c_sda_b, blsp11_uart_rx_b, - blsp11_uart_tx_b, cam_mclk0, cam_mclk1, cam_mclk2, cam_mclk3, - cci_async_in0, cci_async_in1, cci_async_in2, cci_i2c0, cci_i2c1, - cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4, - gcc_gp1_clk_a, gcc_gp1_clk_b, gcc_gp2_clk_a, gcc_gp2_clk_b, gcc_gp3_clk_a, - gcc_gp3_clk_b, gp_mn, gp_pdm0, gp_pdm1, gp_pdm2, gp0_clk, - gp1_clk, gps_tx, gsm_tx, hdmi_cec, hdmi_ddc, hdmi_hpd, hdmi_rcv, - mdp_vsync, mss_lte, nav_pps, nav_tsync, qdss_cti_trig_in_a, - qdss_cti_trig_in_b, qdss_cti_trig_in_c, qdss_cti_trig_in_d, - qdss_cti_trig_out_a, qdss_cti_trig_out_b, qdss_cti_trig_out_c, - qdss_cti_trig_out_d, qdss_traceclk_a, qdss_traceclk_b, qdss_tracectl_a, - qdss_tracectl_b, qdss_tracedata_a, qdss_tracedata_b, qua_mi2s, pci_e0, - pci_e1, pri_mi2s, sdc4, sec_mi2s, slimbus, spkr_i2s, ter_mi2s, tsif1, - tsif2, uim_batt_alarm, uim1, uim2, uim3, uim4, gpio - -- bias-disable: - Usage: optional - Value type: - Definition: The specified pins should be configured as no pull. - -- bias-pull-down: - Usage: optional - Value type: - Definition: The specified pins should be configured as pull down. - -- bias-pull-up: - Usage: optional - Value type: - Definition: The specified pins should be configured as pull up. - -- output-high: - Usage: optional - Value type: - Definition: The specified pins are configured in output mode, driven - high. - Not valid for sdc pins. - -- output-low: - Usage: optional - Value type: - Definition: The specified pins are configured in output mode, driven - low. - Not valid for sdc pins. - -- drive-strength: - Usage: optional - Value type: - Definition: Selects the drive strength for the specified pins, in mA. - Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16 - -Example: - - msmgpio: pinctrl@fd510000 { - compatible = "qcom,msm8994-pinctrl"; - reg = <0xfd510000 0x4000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&msmgpio 0 0 146>; - interrupt-controller; - #interrupt-cells = <2>; - - blsp1_uart2_default: blsp1_uart2_default { - pinmux { - pins = "gpio4", "gpio5"; - function = "blsp_uart2"; - }; - pinconf { - pins = "gpio4", "gpio5"; - drive-strength = <16>; - bias-disable; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8994-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8994-pinctrl.yaml new file mode 100644 index 000000000000..55d5439c6c24 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8994-pinctrl.yaml @@ -0,0 +1,162 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,msm8994-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm MSM8994 TLMM pin controller + +maintainers: + - Bjorn Andersson + - Krzysztof Kozlowski + +description: + Top Level Mode Multiplexer pin controller in Qualcomm MSM8994 SoC. + +properties: + compatible: + enum: + - qcom,msm8992-pinctrl + - qcom,msm8994-pinctrl + + reg: + maxItems: 1 + + interrupts: true + interrupt-controller: true + "#interrupt-cells": true + gpio-controller: true + "#gpio-cells": true + gpio-ranges: true + wakeup-parent: true + + gpio-reserved-ranges: + minItems: 1 + maxItems: 75 + + gpio-line-names: + maxItems: 150 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-msm8994-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-msm8994-tlmm-state" + additionalProperties: false + +$defs: + qcom-msm8994-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9])$" + - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, sdc2_clk, + sdc2_cmd, sdc2_data, sdc3_clk, sdc3_cmd, sdc3_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ gpio, audio_ref_clk, blsp_i2c1, blsp_i2c2, blsp_i2c3, + blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_i2c7, blsp_i2c8, + blsp_i2c9, blsp_i2c10, blsp_i2c11, blsp_i2c12, blsp_spi1, + blsp_spi1_cs1, blsp_spi1_cs2, blsp_spi1_cs3, blsp_spi2, + blsp_spi2_cs1, blsp_spi2_cs2, blsp_spi2_cs3, blsp_spi3, + blsp_spi4, blsp_spi5, blsp_spi6, blsp_spi7, blsp_spi8, + blsp_spi9, blsp_spi10, blsp_spi10_cs1, blsp_spi10_cs2, + blsp_spi10_cs3, blsp_spi11, blsp_spi12, blsp_uart1, blsp_uart2, + blsp_uart3, blsp_uart4, blsp_uart5, blsp_uart6, blsp_uart7, + blsp_uart8, blsp_uart9, blsp_uart10, blsp_uart11, blsp_uart12, + blsp_uim1, blsp_uim2, blsp_uim3, blsp_uim4, blsp_uim5, + blsp_uim6, blsp_uim7, blsp_uim8, blsp_uim9, blsp_uim10, + blsp_uim11, blsp_uim12, blsp11_i2c_scl_b, blsp11_i2c_sda_b, + blsp11_uart_rx_b, blsp11_uart_tx_b, cam_mclk0, cam_mclk1, + cam_mclk2, cam_mclk3, cci_async_in0, cci_async_in1, + cci_async_in2, cci_i2c0, cci_i2c1, cci_timer0, cci_timer1, + cci_timer2, cci_timer3, cci_timer4, gcc_gp1_clk_a, + gcc_gp1_clk_b, gcc_gp2_clk_a, gcc_gp2_clk_b, gcc_gp3_clk_a, + gcc_gp3_clk_b, gp_mn, gp_pdm0, gp_pdm1, gp_pdm2, gp0_clk, + gp1_clk, gps_tx, gsm_tx, hdmi_cec, hdmi_ddc, hdmi_hpd, + hdmi_rcv, mdp_vsync, mss_lte, nav_pps, nav_tsync, + qdss_cti_trig_in_a, qdss_cti_trig_in_b, qdss_cti_trig_in_c, + qdss_cti_trig_in_d, qdss_cti_trig_out_a, qdss_cti_trig_out_b, + qdss_cti_trig_out_c, qdss_cti_trig_out_d, qdss_traceclk_a, + qdss_traceclk_b, qdss_tracectl_a, qdss_tracectl_b, + qdss_tracedata_a, qdss_tracedata_b, qua_mi2s, pci_e0, pci_e1, + pri_mi2s, sdc4, sec_mi2s, slimbus, spkr_i2s, ter_mi2s, tsif1, + tsif2, uim_batt_alarm, uim1, uim2, uim3, uim4 ] + + bias-pull-down: true + bias-pull-up: true + bias-disable: true + drive-strength: true + input-enable: true + output-high: true + output-low: true + + required: + - pins + + additionalProperties: false + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + + tlmm: pinctrl@fd510000 { + compatible = "qcom,msm8994-pinctrl"; + reg = <0xfd510000 0x4000>; + interrupts = ; + gpio-controller; + gpio-ranges = <&tlmm 0 0 146>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + blsp1-uart2-default-state { + function = "blsp_uart2"; + pins = "gpio4", "gpio5"; + drive-strength = <16>; + bias-disable; + }; + + blsp1-spi1-default-state { + default-pins { + pins = "gpio0", "gpio1", "gpio3"; + function = "blsp_spi1"; + drive-strength = <10>; + bias-pull-down; + }; + + cs-pins { + pins = "gpio8"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; + };