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Wysocki" , Len Brown , Thomas Gleixner , Marc Zyngier , Daniel Lezcano , Jonathan Corbet , Anup Patel , Andrew Jones , Atish Patra , 'Conor Dooley ' , Jisheng Zhang , Anup Patel Subject: [PATCH V3 01/20] riscv: move sbi_init() earlier before jump_label_init() Date: Fri, 3 Mar 2023 19:06:28 +0530 Message-Id: <20230303133647.845095-2-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230303133647.845095-1-sunilvl@ventanamicro.com> References: <20230303133647.845095-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759353955400710952?= X-GMAIL-MSGID: =?utf-8?q?1759353955400710952?= From: Jisheng Zhang We call jump_label_init() in setup_arch() is to use static key mechanism earlier, but riscv jump label relies on the sbi functions, If we enable static key before sbi_init(), the code path looks like: static_branch_enable() .. arch_jump_label_transform() patch_text_nosync() flush_icache_range() flush_icache_all() sbi_remote_fence_i() for CONFIG_RISCV_SBI case __sbi_rfence() Since sbi isn't initialized, so NULL deference! Here is a typical panic log: [ 0.000000] Unable to handle kernel NULL pointer dereference at virtual address 0000000000000000 [ 0.000000] Oops [#1] [ 0.000000] Modules linked in: [ 0.000000] CPU: 0 PID: 0 Comm: swapper Not tainted 5.18.0-rc7+ #79 [ 0.000000] Hardware name: riscv-virtio,qemu (DT) [ 0.000000] epc : 0x0 [ 0.000000] ra : sbi_remote_fence_i+0x1e/0x26 [ 0.000000] epc : 0000000000000000 ra : ffffffff80005826 sp : ffffffff80c03d50 [ 0.000000] gp : ffffffff80ca6178 tp : ffffffff80c0ad80 t0 : 6200000000000000 [ 0.000000] t1 : 0000000000000000 t2 : 62203a6b746e6972 s0 : ffffffff80c03d60 [ 0.000000] s1 : ffffffff80001af6 a0 : 0000000000000000 a1 : 0000000000000000 [ 0.000000] a2 : 0000000000000000 a3 : 0000000000000000 a4 : 0000000000000000 [ 0.000000] a5 : 0000000000000000 a6 : 0000000000000000 a7 : 0000000000080200 [ 0.000000] s2 : ffffffff808b3e48 s3 : ffffffff808bf698 s4 : ffffffff80cb2818 [ 0.000000] s5 : 0000000000000001 s6 : ffffffff80c9c345 s7 : ffffffff80895aa0 [ 0.000000] s8 : 0000000000000001 s9 : 000000000000007f s10: 0000000000000000 [ 0.000000] s11: 0000000000000000 t3 : ffffffff80824d08 t4 : 0000000000000022 [ 0.000000] t5 : 000000000000003d t6 : 0000000000000000 [ 0.000000] status: 0000000000000100 badaddr: 0000000000000000 cause: 000000000000000c [ 0.000000] ---[ end trace 0000000000000000 ]--- [ 0.000000] Kernel panic - not syncing: Attempted to kill the idle task! [ 0.000000] ---[ end Kernel panic - not syncing: Attempted to kill the idle task! ]--- Fix this issue by moving sbi_init() earlier before jump_label_init() Signed-off-by: Jisheng Zhang Reviewed-by: Anup Patel Reviewed-by: Atish Patra --- arch/riscv/kernel/setup.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c index 376d2827e736..2d45a416d283 100644 --- a/arch/riscv/kernel/setup.c +++ b/arch/riscv/kernel/setup.c @@ -270,6 +270,7 @@ void __init setup_arch(char **cmdline_p) *cmdline_p = boot_command_line; early_ioremap_setup(); + sbi_init(); jump_label_init(); parse_early_param(); @@ -287,7 +288,6 @@ void __init setup_arch(char **cmdline_p) misc_mem_init(); init_resources(); - sbi_init(); #ifdef CONFIG_KASAN kasan_init(); From patchwork Fri Mar 3 13:36:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 63917 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp412003wrd; Fri, 3 Mar 2023 05:38:22 -0800 (PST) X-Google-Smtp-Source: AK7set/TToAKtCb0fS4EG6VgdkpCvfL72z1KTwqOWSed6g9CGoiYKuAaILIvYM9xsCKZvDXrdW1W X-Received: by 2002:a17:903:11cc:b0:19e:79f7:f318 with SMTP id q12-20020a17090311cc00b0019e79f7f318mr2120780plh.35.1677850701885; Fri, 03 Mar 2023 05:38:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677850701; cv=none; d=google.com; s=arc-20160816; b=Sa0M6gdw4PVX+UDrI3va6XeTf003nxhybRHGivTdGnmXMa9rnNbyC2Hn8/tDbTI8zM n7NLXemz5U6PivXPKLUX2fBwHVEpaCC/FOW0HS4FJmfofrP/PTZOzy4fPSu10DH2mCWY uN6JjOk6t38kIXepck3+oXAa7hli1F4b9MJBEDL2NW8pQkm9TroOFao8pLNObw3RhzBL bK13XAz4YqNZFkbuQ/bx/FSvgOkJ5gIV/I3ZC7BFZ2z9ei0FIXpufhaxdF1D4yaWmLv0 McomBy0GXy3fwBzvVoU8HA3FfvBX4QQzFuCRpfJENflgiSBxXR6gMrXHooQXMMdLEaSO V/cA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=3T/9WMqfcgE40kVyTz05I09P0F9v/Zdvsnucdf4/Z5g=; b=lF688Ur7yquKlZ+kd0Dg1SI6zyOkhJPc85H4EpYfqsdKDv0M0NKpMP3yTTxvZicYXN vGw1dnZN0d4BTc/FC83cTPDGm19QRHEsXuMg7j7uiOrbOfbswILtMUj8Gjwiq3Ukc4+g GJjlg3j2cJz45r+hw1Pug2IL+UE824it+87yk/3lS+Y68KsffVlp11cHUGknIWA8rZ5N 567hS+hxk3dcMiWix8J1V3JWH53pAcuxX8hi0Ctt7x1favSgQH/F3NdmiVY9r2XDYk1c IajKdO6U3c8K2tNqMRgzxJiBj4qRyIiV/2G6p9L3s+1y6fAUs61Vs377rCkBt4sdjtJD 90PA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=NsVd952i; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Wysocki" , Len Brown , Thomas Gleixner , Marc Zyngier , Daniel Lezcano , Jonathan Corbet , Anup Patel , Andrew Jones , Atish Patra , 'Conor Dooley ' , Sunil V L , Robert Moore , acpica-devel@lists.linuxfoundation.org, "Rafael J . Wysocki" Subject: [PATCH V3 02/20] ACPICA: MADT: Add RISC-V INTC interrupt controller Date: Fri, 3 Mar 2023 19:06:29 +0530 Message-Id: <20230303133647.845095-3-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230303133647.845095-1-sunilvl@ventanamicro.com> References: <20230303133647.845095-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759353977543298775?= X-GMAIL-MSGID: =?utf-8?q?1759353977543298775?= The ECR to add RISC-V INTC interrupt controller is approved by the UEFI forum and will be available in the next revision of the ACPI specification. This patch is not yet merged in ACPICA but a PR is raised. ACPICA PR: https://github.com/acpica/acpica/pull/804 Reference: Mantis ID: 2348 Cc: Robert Moore Cc: acpica-devel@lists.linuxfoundation.org Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki --- include/acpi/actbl2.h | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/include/acpi/actbl2.h b/include/acpi/actbl2.h index b2973dbe37ee..abb700d246df 100644 --- a/include/acpi/actbl2.h +++ b/include/acpi/actbl2.h @@ -891,7 +891,8 @@ enum acpi_madt_type { ACPI_MADT_TYPE_MSI_PIC = 21, ACPI_MADT_TYPE_BIO_PIC = 22, ACPI_MADT_TYPE_LPC_PIC = 23, - ACPI_MADT_TYPE_RESERVED = 24, /* 24 to 0x7F are reserved */ + ACPI_MADT_TYPE_RINTC = 24, + ACPI_MADT_TYPE_RESERVED = 25, /* 25 to 0x7F are reserved */ ACPI_MADT_TYPE_OEM_RESERVED = 0x80 /* 0x80 to 0xFF are reserved for OEM use */ }; @@ -1250,6 +1251,24 @@ enum acpi_madt_lpc_pic_version { ACPI_MADT_LPC_PIC_VERSION_RESERVED = 2 /* 2 and greater are reserved */ }; +/* 24: RISC-V INTC */ +struct acpi_madt_rintc { + struct acpi_subtable_header header; + u8 version; + u8 reserved; + u32 flags; + u64 hart_id; + u32 uid; /* ACPI processor UID */ +}; + +/* Values for RISC-V INTC Version field above */ + +enum acpi_madt_rintc_version { + ACPI_MADT_RINTC_VERSION_NONE = 0, + ACPI_MADT_RINTC_VERSION_V1 = 1, + ACPI_MADT_RINTC_VERSION_RESERVED = 2 /* 2 and greater are reserved */ +}; + /* 80: OEM data */ struct acpi_madt_oem_data { From patchwork Fri Mar 3 13:36:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 63916 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp411990wrd; Fri, 3 Mar 2023 05:38:19 -0800 (PST) X-Google-Smtp-Source: AK7set9yrbepFtgvRpDmh7AdcrR6FRhrwGYczZNivftYcBHP6cGBMkFv2RWgM2CqHPiL6WbERZLK X-Received: by 2002:a05:6a20:9146:b0:bb:b903:d836 with SMTP id x6-20020a056a20914600b000bbb903d836mr2515402pzc.54.1677850699507; Fri, 03 Mar 2023 05:38:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677850699; cv=none; d=google.com; s=arc-20160816; b=df87rSKf9h5NRg9DeW2f1UOb0MkIK0SrgwuDoNUur7FY2FFI2Z6wTmIBzCiN6+Tc7b fSIvnJHLoTRlzzeFRr1XvBK6clVCqYFy11LRiCDjdcnpVhCblu+GtiVG95E1DLlHnwKp U4eL911mbM++fLB9b970JwVsCd5ZWUxrEzzD+eGhlHh3HrA9Fdfw9UZqR4YMDlMD3W/6 pnfKF7e5Q05O2w/di926qkQbycZuhAdJ+HVhNkG2STEkGdDTvjRz/Ij+vdsLfmDConkw mWU88GGr5DvgqMOjkhG81PgLV058tX0ieZX3zUTl13Vo3lQ9RlHjx1nZPakOmtT9gdHx mGGg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=pfyzZGOgFR8JpdppLMBGRahWign1okVbjuzaxShQLj4=; b=hkR5s2kHjjzM6D2bTMNxkIF88uXDTC/3cdrvGlRM5paf0gG07Y55JfUt/1re7kV2Kv Z+BATV267XLKgAoS6q9ylPNH9JpVMmrK1CorAKPOvNrbOh1S/GNrfvcWXvtNN21Ot9nQ Wq3db9/QGKYR8vP9GIOVtVxvvr/bXyH9WdoZU2A3Lo7jOM9rMmo4LEms+2qUZUWDKn6x 2Y4IFXWpJnYs0t1mp/1PGdMHXPfdLrWbwR+b3QNa19GMIIp6u5j+XsnVyR7dta7hsDIf sD6SVEpshyeiZVPZs86TIOFz1lz/FUPOKSPKHYW2D83saIykJa0B7DjpzMzf0xGKZdqj MPrg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=QbfGLwIu; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Wysocki" , Len Brown , Thomas Gleixner , Marc Zyngier , Daniel Lezcano , Jonathan Corbet , Anup Patel , Andrew Jones , Atish Patra , 'Conor Dooley ' , Sunil V L , Robert Moore , acpica-devel@lists.linuxfoundation.org, "Rafael J . Wysocki" Subject: [PATCH V3 03/20] ACPICA: Add structure definitions for RISC-V RHCT Date: Fri, 3 Mar 2023 19:06:30 +0530 Message-Id: <20230303133647.845095-4-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230303133647.845095-1-sunilvl@ventanamicro.com> References: <20230303133647.845095-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759353974970776929?= X-GMAIL-MSGID: =?utf-8?q?1759353974970776929?= RISC-V Hart Capabilities Table (RHCT) is a new static table. The ECR to add RHCT is approved by the UEFI forum and will be available in the next version of the ACPI spec. This patch is not yet merged in ACPICA but a PR is raised. ACPICA PR: https://github.com/acpica/acpica/pull/804 Reference: Mantis: 2349 Cc: Robert Moore Cc: acpica-devel@lists.linuxfoundation.org Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki --- include/acpi/actbl2.h | 47 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/include/acpi/actbl2.h b/include/acpi/actbl2.h index abb700d246df..0715e937a453 100644 --- a/include/acpi/actbl2.h +++ b/include/acpi/actbl2.h @@ -47,6 +47,7 @@ #define ACPI_SIG_PRMT "PRMT" /* Platform Runtime Mechanism Table */ #define ACPI_SIG_RASF "RASF" /* RAS Feature table */ #define ACPI_SIG_RGRT "RGRT" /* Regulatory Graphics Resource Table */ +#define ACPI_SIG_RHCT "RHCT" /* RISC-V Hart Capabilities Table */ #define ACPI_SIG_SBST "SBST" /* Smart Battery Specification Table */ #define ACPI_SIG_SDEI "SDEI" /* Software Delegated Exception Interface Table */ #define ACPI_SIG_SDEV "SDEV" /* Secure Devices table */ @@ -2606,6 +2607,52 @@ enum acpi_rgrt_image_type { /******************************************************************************* * + * RHCT - RISC-V Hart Capabilities Table + * Version 1 + * + ******************************************************************************/ + +struct acpi_table_rhct { + struct acpi_table_header header; /* Common ACPI table header */ + u32 reserved; + u64 time_base_freq; + u32 node_count; + u32 node_offset; +}; + +/* + * RHCT subtables + */ +struct acpi_rhct_node_header { + u16 type; + u16 length; + u16 revision; +}; + +/* Values for RHCT subtable Type above */ + +enum acpi_rhct_node_type { + ACPI_RHCT_NODE_TYPE_ISA_STRING = 0x0000, + ACPI_RHCT_NODE_TYPE_HART_INFO = 0xFFFF, +}; + +/* + * RHCT node specific subtables + */ + +/* ISA string node structure */ +struct acpi_rhct_isa_string { + u16 isa_length; + char isa[]; +}; + +/* Hart Info node structure */ +struct acpi_rhct_hart_info { + u16 num_offsets; + u32 uid; /* ACPI processor UID */ +}; + +/******************************************************************************* * SBST - Smart Battery Specification Table * Version 1 * From patchwork Fri Mar 3 13:36:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 63918 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp412038wrd; Fri, 3 Mar 2023 05:38:26 -0800 (PST) X-Google-Smtp-Source: AK7set/ZWvuy2FMf4EQKbVTfvw65SwN7IwGGinyohvHTkMp7NZfRFcuwihsPLmBsvvtHArKJiwLY X-Received: by 2002:a17:903:32cb:b0:19e:7f89:b3a7 with SMTP id i11-20020a17090332cb00b0019e7f89b3a7mr2161402plr.31.1677850706036; Fri, 03 Mar 2023 05:38:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677850706; cv=none; d=google.com; s=arc-20160816; b=jD9M7Bn9bQDU7CPex7zwmckIGnuCebMVkbVodPXaclWuXGURu2GH5ULaXgfYowbfSX /U+Dr2JS3Jp2YL1aH+DxN5tmcEK2K7LfWXSTjB8T9Zs1z7p/4Qoxhr1KF3NAYs5YM66f Go1t8INhvWzUiPcMyu++LEy9pPikFWuIjf0vpNj/0X88Qod+laGuS4UCzzNkpivNWTyP C7AcEapOUxA3Q+wKEgRKgKMk6MmoRPGMXLN8TI6+0bMBErXAnW4U28fJlTc+0x2nqQEb oDESYmkNuOxxg6MPDeG/p+LIYlQrKbM5c+6Ue5RslsJ1VhJZtOzbtZivkMV2zfPhirI/ XPAw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=OjsYubhOT8xU6uZ8EboYvG8E1YP64zOg4cL5+jWYP1s=; b=q7NGVIOTn2IzXLSRyAWYpmrpowKTCKRK54oylV2Mu5kyAZwxid3dlcEj2ipoNfX6vi 3wRjb7AI/GBIqwurYVVv80PWsbfCfhLt7QLQryabK/QvNcQgPNjD3atrwauNtLBsFTln wD1AidCS7KudRKIol6GnzJTu1qq8fnCxtZ2XHsNdKl1xdwir3odUz88S04HoMtmjFiU9 LQ24O7bgbqUfRZTpJDkLgKQOnC874yRaauZWhG5KUGm4NyrOROQGFDr7bLLk5xudM8k8 95XbwJZZ1opQKkO3aWtnjthkcFmxtvZbvk60wGKLHQsy6SHaGa53QMQJ0hsAUUxF0BPk ckEg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=Hvr+Hc1X; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Wysocki" , Len Brown , Thomas Gleixner , Marc Zyngier , Daniel Lezcano , Jonathan Corbet , Anup Patel , Andrew Jones , Atish Patra , 'Conor Dooley ' , Sunil V L , "Rafael J . Wysocki" Subject: [PATCH V3 04/20] ACPI: tables: Print RINTC information when MADT is parsed Date: Fri, 3 Mar 2023 19:06:31 +0530 Message-Id: <20230303133647.845095-5-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230303133647.845095-1-sunilvl@ventanamicro.com> References: <20230303133647.845095-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759353981834830816?= X-GMAIL-MSGID: =?utf-8?q?1759353981834830816?= When MADT is parsed, print RINTC information as below: ACPI: RISC-V INTC (acpi_uid[0x0000] hart_id[0x0] enabled) ACPI: RISC-V INTC (acpi_uid[0x0001] hart_id[0x1] enabled) ... ACPI: RISC-V INTC (acpi_uid[0x000f] hart_id[0xf] enabled) This debug information will be very helpful during bring up. Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki Reviewed-by: Andrew Jones --- drivers/acpi/tables.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/acpi/tables.c b/drivers/acpi/tables.c index 7b4680da57d7..8ab0a82b4da4 100644 --- a/drivers/acpi/tables.c +++ b/drivers/acpi/tables.c @@ -220,6 +220,16 @@ void acpi_table_print_madt_entry(struct acpi_subtable_header *header) } break; + case ACPI_MADT_TYPE_RINTC: + { + struct acpi_madt_rintc *p = (struct acpi_madt_rintc *)header; + + pr_debug("RISC-V INTC (acpi_uid[0x%04x] hart_id[0x%llx] %s)\n", + p->uid, p->hart_id, + (p->flags & ACPI_MADT_ENABLED) ? "enabled" : "disabled"); + } + break; + default: pr_warn("Found unsupported MADT entry (type = 0x%x)\n", header->type); From patchwork Fri Mar 3 13:36:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 63919 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp412122wrd; Fri, 3 Mar 2023 05:38:40 -0800 (PST) X-Google-Smtp-Source: AK7set8B3jw+12OPl6k/XZRWvaO/eqH/Et/1OViFvFdupH6AskK3SwQb+55RY8jsjyyiKQO0MXOY X-Received: by 2002:a17:90b:4c50:b0:236:73e8:f53 with SMTP id np16-20020a17090b4c5000b0023673e80f53mr5882105pjb.19.1677850720390; Fri, 03 Mar 2023 05:38:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677850720; cv=none; d=google.com; s=arc-20160816; b=seqgYvLrqxTH44tWIrDL4KPgdtM0a4+b9hB7IpuLaWpqrl+jChdIx1ygHixjYm8Y/3 K+u5k9LFazyL2Otluas1wVM9hrU8JPa2J67mHI7r43Qe3l/gEViR0cj3SK9q+2dP7yAN 7sWIhXNbv8Abtc3CFAdnMHN96F+sdGI44aEnG7gX9rsUoncOzxJ2jiWnPABP/g18s+Jw rPy95eLZEwzN7Z3ve/hT+kYc4I0CLiA+4d49sdQGouUT1gKTyp1UsvAxnyELs24UoYhC Hm04awIvJm2m1YY/DN3aN2+3IWdcgVeNV5zpbk1Ycos3fiGRnsVKr4z4w37nfPaWeQ4j CHoQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=g9sxg5LZ/1sJSiDItv56ESM72UWoohRRXZed1vK0StQ=; b=KlCSrPOPPsQajVV4m1mHRjsv3IGdlG9bs3GXVr1tbvyuRx/Zj9uPrv+kiy1VxBpz/g Xq7VJEBo+2Tj/JwvKPzMM81pghi0Xo75XcaIDZs346+SIiSVyZxi5miW0IrxIjEdc2QG aAnsFuod8wDphn4wBGHM2RJIV0zlB2nrK4DV0kFSdklKz36HVC12sPHWPUbc8AUEcqPi FFhK8b5tcgeHeTmNkM8gDVkHEkFWPkUtr53QcNz99V/kFho2vEZpt6EcLsG4tRtMySPN YskON8Yezp37LGLwbt0MM0UR1vLE/wSeQJVGd/WROJVRitvMkvCncKfPJCV8VF+1pJbU 6vIg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=Zsc6LaeJ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Wysocki" , Len Brown , Thomas Gleixner , Marc Zyngier , Daniel Lezcano , Jonathan Corbet , Anup Patel , Andrew Jones , Atish Patra , 'Conor Dooley ' , Sunil V L , "Rafael J . Wysocki" Subject: [PATCH V3 05/20] ACPI: OSL: Make should_use_kmap() 0 for RISC-V Date: Fri, 3 Mar 2023 19:06:32 +0530 Message-Id: <20230303133647.845095-6-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230303133647.845095-1-sunilvl@ventanamicro.com> References: <20230303133647.845095-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759353996847644728?= X-GMAIL-MSGID: =?utf-8?q?1759353996847644728?= Without this, if the tables are larger than 4K, acpi_map() will fail. Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki --- drivers/acpi/osl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/acpi/osl.c b/drivers/acpi/osl.c index 3269a888fb7a..f725813d0cce 100644 --- a/drivers/acpi/osl.c +++ b/drivers/acpi/osl.c @@ -276,7 +276,7 @@ acpi_map_lookup_virt(void __iomem *virt, acpi_size size) return NULL; } -#if defined(CONFIG_IA64) || defined(CONFIG_ARM64) +#if defined(CONFIG_IA64) || defined(CONFIG_ARM64) || defined(CONFIG_RISCV) /* ioremap will take care of cache attributes */ #define should_use_kmap(pfn) 0 #else From patchwork Fri Mar 3 13:36:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 63920 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp412197wrd; Fri, 3 Mar 2023 05:38:49 -0800 (PST) X-Google-Smtp-Source: AK7set/j7kW5/r0Wu7NKxeYM0ump0KSWb0AjK1upgACh1gBFgBMax9RBL6hpED43cYnJ/9/t/eFo X-Received: by 2002:a17:902:f646:b0:19c:d796:9ab5 with SMTP id m6-20020a170902f64600b0019cd7969ab5mr1855130plg.52.1677850729241; Fri, 03 Mar 2023 05:38:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677850729; cv=none; d=google.com; s=arc-20160816; b=NGnHyuaAMr+c1q34DrqpOtADnm1TUOmTW+6xLKVyGpG7QmI4M8zoPjLevMPyOAZ8Sb IOuGj+TfyB4EqONcuhqa4Cijtbj7kPnhwiLh+NqE2pxpOe86vaQmtbi9Ph4UqackoiTw CE5qJF3PPR5Ep7kQYcVAH636InmuSeRJpajtfyHN0X0YHDBl1Yi5+tAuu7Hg+/P0xSeV bQJdtHUG3VteVZyl040TwHwfMDApcO6x0S/0JtqgnIQ1GivRVkqm9yLw2Swqr/kqutIV aiwdoOKfjik4gHypcncUxMBbv/atpkI0+pu8SQMf8U5w51dTyCg3WfEINaq09v+aGsQw XyyA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=c0/qtS4GxFzKHtxYMaq70AM3hWYMvwiY43suIuXOFxs=; b=qCJ/Gi7FeZN2u9vInHhnf71MPwKsucqhcNKOvJnymNI7Mu6yR41Lnrc+GIZwZHAyxZ BQoaOAzscy5T/wB0mYvlq3YWQf9Yu26dh/DQACO03ad41ah/EZN5rZzuTszip4E7OpP8 By+MSA5KQzSbF72lg5ssmh3zO3QhJHGLV7PcCLXxTYp7I9X8KNlvjZjgZAkmkGZ/xV4g /w4TG6FJ0XlR8s/+x++HJyFCvu5HV3EtgsWrS+PUVtkiMJ3Af7c/a7Py2HLxADdEsAxx mDnd2mWqEXRrEoDynrxm6huZ8F1XLeLXDA+G5EUvnz1D8uhEpN3WkQe93kSd3Ybothkg 16vA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=hz6Fj36H; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Wysocki" , Len Brown , Thomas Gleixner , Marc Zyngier , Daniel Lezcano , Jonathan Corbet , Anup Patel , Andrew Jones , Atish Patra , 'Conor Dooley ' , Sunil V L , "Rafael J . Wysocki" Subject: [PATCH V3 06/20] RISC-V: Add support to build the ACPI core Date: Fri, 3 Mar 2023 19:06:33 +0530 Message-Id: <20230303133647.845095-7-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230303133647.845095-1-sunilvl@ventanamicro.com> References: <20230303133647.845095-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759354006228984454?= X-GMAIL-MSGID: =?utf-8?q?1759354006228984454?= Enable ACPI core for RISC-V after adding architecture-specific interfaces and header files required to build the ACPI core. 1) Couple of header files are required unconditionally by the ACPI core. Add empty acenv.h and cpu.h header files. 2) If CONFIG_PCI is enabled, a few PCI related interfaces need to be provided by the architecture. Define dummy interfaces for now so that build succeeds. Actual implementation will be added when PCI support is added for ACPI along with external interrupt controller support. 3) A few globals and memory mapping related functions specific to the architecture need to be provided. Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki Reviewed-by: Andrew Jones Reviewed-by: Conor Dooley --- arch/riscv/Kconfig | 5 +++ arch/riscv/include/asm/acenv.h | 11 +++++ arch/riscv/include/asm/acpi.h | 61 ++++++++++++++++++++++++++ arch/riscv/include/asm/cpu.h | 8 ++++ arch/riscv/kernel/Makefile | 2 + arch/riscv/kernel/acpi.c | 80 ++++++++++++++++++++++++++++++++++ 6 files changed, 167 insertions(+) create mode 100644 arch/riscv/include/asm/acenv.h create mode 100644 arch/riscv/include/asm/acpi.h create mode 100644 arch/riscv/include/asm/cpu.h create mode 100644 arch/riscv/kernel/acpi.c diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 71754eb32ee6..f3108c7e19d8 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -12,6 +12,8 @@ config 32BIT config RISCV def_bool y + select ACPI_GENERIC_GSI if ACPI + select ACPI_REDUCED_HARDWARE_ONLY if ACPI select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE @@ -617,6 +619,7 @@ config EFI depends on OF && !XIP_KERNEL depends on MMU default y + select ARCH_SUPPORTS_ACPI if 64BIT select EFI_GENERIC_STUB select EFI_PARAMS_FROM_FDT select EFI_RUNTIME_WRAPPERS @@ -720,3 +723,5 @@ source "drivers/cpufreq/Kconfig" endmenu # "CPU Power Management" source "arch/riscv/kvm/Kconfig" + +source "drivers/acpi/Kconfig" diff --git a/arch/riscv/include/asm/acenv.h b/arch/riscv/include/asm/acenv.h new file mode 100644 index 000000000000..22123c5a4883 --- /dev/null +++ b/arch/riscv/include/asm/acenv.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * RISC-V specific ACPICA environments and implementation + */ + +#ifndef _ASM_ACENV_H +#define _ASM_ACENV_H + +/* It is required unconditionally by ACPI core */ + +#endif /* _ASM_ACENV_H */ diff --git a/arch/riscv/include/asm/acpi.h b/arch/riscv/include/asm/acpi.h new file mode 100644 index 000000000000..0b52a190f71a --- /dev/null +++ b/arch/riscv/include/asm/acpi.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2013-2014, Linaro Ltd. + * Author: Al Stone + * Author: Graeme Gregory + * Author: Hanjun Guo + * + * Copyright (C) 2021-2023, Ventana Micro Systems Inc. + * Author: Sunil V L + */ + +#ifndef _ASM_ACPI_H +#define _ASM_ACPI_H + +/* Basic configuration for ACPI */ +#ifdef CONFIG_ACPI + +/* ACPI table mapping after acpi_permanent_mmap is set */ +void *acpi_os_ioremap(acpi_physical_address phys, acpi_size size); +#define acpi_os_ioremap acpi_os_ioremap + +#define acpi_strict 1 /* No out-of-spec workarounds on RISC-V */ +extern int acpi_disabled; +extern int acpi_noirq; +extern int acpi_pci_disabled; + +static inline void disable_acpi(void) +{ + acpi_disabled = 1; + acpi_pci_disabled = 1; + acpi_noirq = 1; +} + +static inline void enable_acpi(void) +{ + acpi_disabled = 0; + acpi_pci_disabled = 0; + acpi_noirq = 0; +} + +/* + * The ACPI processor driver for ACPI core code needs this macro + * to find out this cpu was already mapped (mapping from CPU hardware + * ID to CPU logical ID) or not. + */ +#define cpu_physical_id(cpu) cpuid_to_hartid_map(cpu) + +/* + * Since MADT must provide at least one RINTC structure, the + * CPU will be always available in MADT on RISC-V. + */ +static inline bool acpi_has_cpu_in_madt(void) +{ + return true; +} + +static inline void arch_fix_phys_package_id(int num, u32 slot) { } + +#endif /* CONFIG_ACPI */ + +#endif /*_ASM_ACPI_H*/ diff --git a/arch/riscv/include/asm/cpu.h b/arch/riscv/include/asm/cpu.h new file mode 100644 index 000000000000..ea1a88b3d5f2 --- /dev/null +++ b/arch/riscv/include/asm/cpu.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _ASM_CPU_H +#define _ASM_CPU_H + +/* It is required unconditionally by ACPI core */ + +#endif /* _ASM_CPU_H */ diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile index 67f542be1bea..f979dc8cf47d 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile @@ -90,3 +90,5 @@ obj-$(CONFIG_EFI) += efi.o obj-$(CONFIG_COMPAT) += compat_syscall_table.o obj-$(CONFIG_COMPAT) += compat_signal.o obj-$(CONFIG_COMPAT) += compat_vdso/ + +obj-$(CONFIG_ACPI) += acpi.o diff --git a/arch/riscv/kernel/acpi.c b/arch/riscv/kernel/acpi.c new file mode 100644 index 000000000000..81d448c41714 --- /dev/null +++ b/arch/riscv/kernel/acpi.c @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * RISC-V Specific Low-Level ACPI Boot Support + * + * Copyright (C) 2013-2014, Linaro Ltd. + * Author: Al Stone + * Author: Graeme Gregory + * Author: Hanjun Guo + * Author: Tomasz Nowicki + * Author: Naresh Bhat + * + * Copyright (C) 2021-2023, Ventana Micro Systems Inc. + * Author: Sunil V L + */ + +#include +#include +#include + +int acpi_noirq = 1; /* skip ACPI IRQ initialization */ +int acpi_disabled = 1; +EXPORT_SYMBOL(acpi_disabled); + +int acpi_pci_disabled = 1; /* skip ACPI PCI scan and IRQ initialization */ +EXPORT_SYMBOL(acpi_pci_disabled); + +/* + * __acpi_map_table() will be called before paging_init(), so early_ioremap() + * or early_memremap() should be called here to for ACPI table mapping. + */ +void __init __iomem *__acpi_map_table(unsigned long phys, unsigned long size) +{ + if (!size) + return NULL; + + return early_memremap(phys, size); +} + +void __init __acpi_unmap_table(void __iomem *map, unsigned long size) +{ + if (!map || !size) + return; + + early_memunmap(map, size); +} + +void *acpi_os_ioremap(acpi_physical_address phys, acpi_size size) +{ + return memremap(phys, size, MEMREMAP_WB); +} + +#ifdef CONFIG_PCI + +/* + * These interfaces are defined just to enable building ACPI core. + * TODO: Update it with actual implementation when external interrupt + * controller support is added in RISC-V ACPI. + */ +int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, + int reg, int len, u32 *val) +{ + return PCIBIOS_DEVICE_NOT_FOUND; +} + +int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn, + int reg, int len, u32 val) +{ + return PCIBIOS_DEVICE_NOT_FOUND; +} + +int acpi_pci_bus_find_domain_nr(struct pci_bus *bus) +{ + return -1; +} + +struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root) +{ + return NULL; +} +#endif /* CONFIG_PCI */ From patchwork Fri Mar 3 13:36:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 63924 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp412438wrd; Fri, 3 Mar 2023 05:39:23 -0800 (PST) X-Google-Smtp-Source: AK7set8LlETgbFI2s6QF1dQVKCld5YYLzhrS5te0JG3xqNng32BG2yHJnH6AFAS70gFDCpvvH04X X-Received: by 2002:a17:90b:3ec2:b0:237:a500:eca6 with SMTP id rm2-20020a17090b3ec200b00237a500eca6mr5766508pjb.22.1677850763091; Fri, 03 Mar 2023 05:39:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677850763; cv=none; d=google.com; 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Wysocki" , Len Brown , Thomas Gleixner , Marc Zyngier , Daniel Lezcano , Jonathan Corbet , Anup Patel , Andrew Jones , Atish Patra , 'Conor Dooley ' , Sunil V L , "Rafael J . Wysocki" Subject: [PATCH V3 07/20] ACPI: processor_core: RISC-V: Enable mapping processor to the hartid Date: Fri, 3 Mar 2023 19:06:34 +0530 Message-Id: <20230303133647.845095-8-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230303133647.845095-1-sunilvl@ventanamicro.com> References: <20230303133647.845095-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759354041518302179?= X-GMAIL-MSGID: =?utf-8?q?1759354041518302179?= processor_core needs arch-specific functions to map the ACPI ID to the physical ID. In RISC-V platforms, hartid is the physical id and RINTC structure in MADT provides this mapping. Add arch-specific function to get this mapping from RINTC. Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki Reviewed-by: Andrew Jones --- arch/riscv/include/asm/acpi.h | 3 +++ drivers/acpi/processor_core.c | 29 +++++++++++++++++++++++++++++ 2 files changed, 32 insertions(+) diff --git a/arch/riscv/include/asm/acpi.h b/arch/riscv/include/asm/acpi.h index 0b52a190f71a..7671c401f4ec 100644 --- a/arch/riscv/include/asm/acpi.h +++ b/arch/riscv/include/asm/acpi.h @@ -15,6 +15,9 @@ /* Basic configuration for ACPI */ #ifdef CONFIG_ACPI +typedef u64 phys_cpuid_t; +#define PHYS_CPUID_INVALID INVALID_HARTID + /* ACPI table mapping after acpi_permanent_mmap is set */ void *acpi_os_ioremap(acpi_physical_address phys, acpi_size size); #define acpi_os_ioremap acpi_os_ioremap diff --git a/drivers/acpi/processor_core.c b/drivers/acpi/processor_core.c index 2ac48cda5b20..d6606a9f2da6 100644 --- a/drivers/acpi/processor_core.c +++ b/drivers/acpi/processor_core.c @@ -106,6 +106,32 @@ static int map_gicc_mpidr(struct acpi_subtable_header *entry, return -EINVAL; } +/* + * Retrieve the RISC-V hartid for the processor + */ +static int map_rintc_hartid(struct acpi_subtable_header *entry, + int device_declaration, u32 acpi_id, + phys_cpuid_t *hartid) +{ + struct acpi_madt_rintc *rintc = + container_of(entry, struct acpi_madt_rintc, header); + + if (!(rintc->flags & ACPI_MADT_ENABLED)) + return -ENODEV; + + /* device_declaration means Device object in DSDT, in the + * RISC-V, logical processors are required to + * have a Processor Device object in the DSDT, so we should + * check device_declaration here + */ + if (device_declaration && rintc->uid == acpi_id) { + *hartid = rintc->hart_id; + return 0; + } + + return -EINVAL; +} + static phys_cpuid_t map_madt_entry(struct acpi_table_madt *madt, int type, u32 acpi_id) { @@ -136,6 +162,9 @@ static phys_cpuid_t map_madt_entry(struct acpi_table_madt *madt, } else if (header->type == ACPI_MADT_TYPE_GENERIC_INTERRUPT) { if (!map_gicc_mpidr(header, type, acpi_id, &phys_id)) break; + } else if (header->type == ACPI_MADT_TYPE_RINTC) { + if (!map_rintc_hartid(header, type, acpi_id, &phys_id)) + break; } entry += header->length; } From patchwork Fri Mar 3 13:36:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 63922 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp412325wrd; Fri, 3 Mar 2023 05:39:08 -0800 (PST) X-Google-Smtp-Source: AK7set+o/QzlUeUh0GwQoSh++VZaYCs99vmcyMv8AKnos4H/ywle1Gzz2wr71sMrQMH6kOs8AJDh X-Received: by 2002:a17:90a:cd:b0:234:b35b:f8e7 with SMTP id v13-20020a17090a00cd00b00234b35bf8e7mr1702575pjd.7.1677850748476; Fri, 03 Mar 2023 05:39:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677850748; cv=none; d=google.com; s=arc-20160816; b=kaaXRwn+p+misfrZ+2b4asjYQ0e5EOccZKYsMQUs19gqtn1rTn8rZXuCnWNRYWI24e nuErtCvU6A6P7hU6olxoZatPBFgxZkaLIJM8Z+yMsMJR8lBjMHCJuNMS3/NjqTKM1ab6 Q9O+in8oPZwhoHKwZw2NBUUKi8+Y086esBZDFzXwXe9GCgZgmmm4lJGsZY5TiTOlIY4E ye21pF4MCpjC4yLcCulLZ+ETH8gYLlhQLpQqONH+0kFEGkhA5KsifQwbXYCSmxqhb4ku vtBcWJA7CZ0T0irsrTpGHuFflq91efGDCznplgciduNJDs8gpM4SV1Vcj3UlJ7BXz8Kd ajIw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=opcZr20KXnvjkMyYCnmLSprA9lMTCGLgPDByb/r4X5s=; b=HipaVezadNuoZS45O+d5aLc3Qt/LxSJ8lCkS801U+nxQ8Ld8F40QQwH7kyFdNm1iWw pljp86zqMvqkoKxPby4g4EMqJ3IferWQ3pKCTrb8fdJ+ciw2NYlGzhv4nyDpSdHLylzu xrStxjVu5AC9EdENfFmKb99SovJHiIAlS2inIEYVwfoVFykIQcDNohR7jafrJUCiuRoz 21vEV0Mmjww7y8uCLvsuPI6KD3niDgMAmpcQfF/OVc6BoyibfGCSqR/jIU8zio94HBNx klopC9zSwn2BQp21AYrGG9Z09ejM196UOYYj3uf1MMYqvwm1elkvI4g7XrwwLRKCHdMW QM9g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=mtzaNcwo; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Wysocki" , Len Brown , Thomas Gleixner , Marc Zyngier , Daniel Lezcano , Jonathan Corbet , Anup Patel , Andrew Jones , Atish Patra , 'Conor Dooley ' , Sunil V L , "Rafael J . Wysocki" Subject: [PATCH V3 08/20] drivers/acpi: RISC-V: Add RHCT related code Date: Fri, 3 Mar 2023 19:06:35 +0530 Message-Id: <20230303133647.845095-9-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230303133647.845095-1-sunilvl@ventanamicro.com> References: <20230303133647.845095-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759354026822693962?= X-GMAIL-MSGID: =?utf-8?q?1759354026822693962?= RHCT is a new table defined for RISC-V to communicate the features of the CPU to the OS. Create a new architecture folder in drivers/acpi and add RHCT parsing code. Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki Reviewed-by: Andrew Jones --- arch/riscv/include/asm/acpi.h | 9 ++++ drivers/acpi/Makefile | 2 + drivers/acpi/riscv/Makefile | 2 + drivers/acpi/riscv/rhct.c | 82 +++++++++++++++++++++++++++++++++++ 4 files changed, 95 insertions(+) create mode 100644 drivers/acpi/riscv/Makefile create mode 100644 drivers/acpi/riscv/rhct.c diff --git a/arch/riscv/include/asm/acpi.h b/arch/riscv/include/asm/acpi.h index 7671c401f4ec..111a8ed10af1 100644 --- a/arch/riscv/include/asm/acpi.h +++ b/arch/riscv/include/asm/acpi.h @@ -59,6 +59,15 @@ static inline bool acpi_has_cpu_in_madt(void) static inline void arch_fix_phys_package_id(int num, u32 slot) { } +int acpi_get_riscv_isa(struct acpi_table_header *table, + unsigned int cpu, const char **isa); +#else +static inline int acpi_get_riscv_isa(struct acpi_table_header *table, + unsigned int cpu, const char **isa) +{ + return -EINVAL; +} + #endif /* CONFIG_ACPI */ #endif /*_ASM_ACPI_H*/ diff --git a/drivers/acpi/Makefile b/drivers/acpi/Makefile index feb36c0b9446..3fc5a0d54f6e 100644 --- a/drivers/acpi/Makefile +++ b/drivers/acpi/Makefile @@ -131,3 +131,5 @@ obj-y += dptf/ obj-$(CONFIG_ARM64) += arm64/ obj-$(CONFIG_ACPI_VIOT) += viot.o + +obj-$(CONFIG_RISCV) += riscv/ diff --git a/drivers/acpi/riscv/Makefile b/drivers/acpi/riscv/Makefile new file mode 100644 index 000000000000..8b3b126e0b94 --- /dev/null +++ b/drivers/acpi/riscv/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-y += rhct.o diff --git a/drivers/acpi/riscv/rhct.c b/drivers/acpi/riscv/rhct.c new file mode 100644 index 000000000000..2e2aeb7cae49 --- /dev/null +++ b/drivers/acpi/riscv/rhct.c @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2022-2023, Ventana Micro Systems Inc + * Author: Sunil V L + * + */ + +#define pr_fmt(fmt) "ACPI: RHCT: " fmt + +#include + +static struct acpi_table_header *acpi_get_rhct(void) +{ + static struct acpi_table_header *rhct; + acpi_status status; + + /* + * RHCT will be used at runtime on every CPU, so we + * don't need to call acpi_put_table() to release the table mapping. + */ + if (!rhct) { + status = acpi_get_table(ACPI_SIG_RHCT, 0, &rhct); + if (ACPI_FAILURE(status)) { + pr_warn_once("No RHCT table found\n"); + return NULL; + } + } + + return rhct; +} + +/* + * During early boot, the caller should call acpi_get_table() and pass its pointer to + * these functions(and free up later). At run time, since this table can be used + * multiple times, NULL may be passed in order to use the cached table. + */ +int acpi_get_riscv_isa(struct acpi_table_header *table, unsigned int acpi_cpu_id, const char **isa) +{ + struct acpi_rhct_node_header *node, *ref_node, *end; + u32 size_hdr = sizeof(struct acpi_rhct_node_header); + u32 size_hartinfo = sizeof(struct acpi_rhct_hart_info); + struct acpi_rhct_hart_info *hart_info; + struct acpi_rhct_isa_string *isa_node; + struct acpi_table_rhct *rhct; + u32 *hart_info_node_offset; + + BUG_ON(acpi_disabled); + + if (!table) { + rhct = (struct acpi_table_rhct *)acpi_get_rhct(); + if (!rhct) + return -ENOENT; + } else { + rhct = (struct acpi_table_rhct *)table; + } + + end = ACPI_ADD_PTR(struct acpi_rhct_node_header, rhct, rhct->header.length); + + for (node = ACPI_ADD_PTR(struct acpi_rhct_node_header, rhct, rhct->node_offset); + node < end; + node = ACPI_ADD_PTR(struct acpi_rhct_node_header, node, node->length)) { + if (node->type == ACPI_RHCT_NODE_TYPE_HART_INFO) { + hart_info = ACPI_ADD_PTR(struct acpi_rhct_hart_info, node, size_hdr); + hart_info_node_offset = ACPI_ADD_PTR(u32, hart_info, size_hartinfo); + if (acpi_cpu_id != hart_info->uid) + continue; + + for (int i = 0; i < hart_info->num_offsets; i++) { + ref_node = ACPI_ADD_PTR(struct acpi_rhct_node_header, + rhct, hart_info_node_offset[i]); + if (ref_node->type == ACPI_RHCT_NODE_TYPE_ISA_STRING) { + isa_node = ACPI_ADD_PTR(struct acpi_rhct_isa_string, + ref_node, size_hdr); + *isa = isa_node->isa; + return 0; + } + } + } + } + + return -1; +} From patchwork Fri Mar 3 13:36:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 63921 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp412309wrd; Fri, 3 Mar 2023 05:39:06 -0800 (PST) X-Google-Smtp-Source: AK7set/7d/eiWzkBUQ0kd705wYTn8U3WzQ6D/qaZfG+Md27ssagpVKyXcl0MHsTBXr4KbnA9mI/M X-Received: by 2002:aa7:9528:0:b0:58d:be61:4859 with SMTP id c8-20020aa79528000000b0058dbe614859mr2064697pfp.11.1677850745928; Fri, 03 Mar 2023 05:39:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677850745; cv=none; d=google.com; s=arc-20160816; b=OD4j3OY/rLZJJ59K67g8iLFkZ1jR3Rj0roImLhp6ofEIUWSU/ZcRMWhlQZ+8m+Lk6T 7XUGo57KS3yD/C9JicryBNBVfK3B3lmBtUCscLuOQjFtS+Xolfs1WCrTS9vBiuFdGVLq x2w7NpWvYnHo0PNqeWy+XAJL4g9vJm+gwlIlnGMe6UzETI+ya7VcJhU5mmaWhkGrhoRZ 18ILvSNgjFAL8oRSTqwTwpT712JXvwUBV8gPf5dzkfs/0q2Vc6w97ECNZJGoWVxrSjYs 3my7tmSdnVr/wbxstXvhHTF2lZ8wLug+TXC//EI6yICsaUEOubQQZEBM2SP3pFXTBYzu kGSg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=5pi8xH0IxXrFGj4CxsC9boyEOiTx1Qa4CmKA7c/Mr88=; b=F6KnFkEl0RiS3rYby93ZXZgYGRfQVkXpPZfBQdFLV83vfzZTUj8JvxXMvzCPsJI+WZ umWbBicnVqG0vmLEk2aCBx0IMf1GWj/qcpaNg3QmdIfDJGW/KVa0ZR6AhRRnWnvc74R9 9aSNgxkeVPHgDhGRPPGp51np94GCW5t7s2ewkB6Yyivl4xfmscNoJIN74EviXLr/qDSK cUq8qmxnY4fANHdcMNHs5VTxuS1EJJyVBJQ69rbYqhBk4Da76XaEAE7u68mP6CgY/Jhm Tzolby02pEkSsj4vIwYrnJchCnU3kHVBfmr2PEqHreFMuGlpe5IQqUdZHi6+J+V8pamW u8sg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=ospJEN1H; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Wysocki" , Len Brown , Thomas Gleixner , Marc Zyngier , Daniel Lezcano , Jonathan Corbet , Anup Patel , Andrew Jones , Atish Patra , 'Conor Dooley ' , Sunil V L , "Rafael J . Wysocki" Subject: [PATCH V3 09/20] RISC-V: smpboot: Create wrapper smp_setup() Date: Fri, 3 Mar 2023 19:06:36 +0530 Message-Id: <20230303133647.845095-10-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230303133647.845095-1-sunilvl@ventanamicro.com> References: <20230303133647.845095-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759354024114018481?= X-GMAIL-MSGID: =?utf-8?q?1759354024114018481?= smp_setup() currently assumes DT-based platforms. To enable ACPI, first make this a wrapper function and move existing code to a separate DT-specific function. Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki Reviewed-by: Conor Dooley Reviewed-by: Andrew Jones --- arch/riscv/kernel/smpboot.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c index 00b53913d4c6..26214ddefaa4 100644 --- a/arch/riscv/kernel/smpboot.c +++ b/arch/riscv/kernel/smpboot.c @@ -70,7 +70,7 @@ void __init smp_prepare_cpus(unsigned int max_cpus) } } -void __init setup_smp(void) +static void __init of_parse_and_init_cpus(void) { struct device_node *dn; unsigned long hart; @@ -116,6 +116,11 @@ void __init setup_smp(void) } } +void __init setup_smp(void) +{ + of_parse_and_init_cpus(); +} + static int start_secondary_cpu(int cpu, struct task_struct *tidle) { if (cpu_ops[cpu]->cpu_start) From patchwork Fri Mar 3 13:36:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 63923 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp412412wrd; Fri, 3 Mar 2023 05:39:20 -0800 (PST) X-Google-Smtp-Source: AK7set8flG5rgHFNGW9C/WeONKNQHfNmZbBMJ4PXEZ7KskqqdHL/2fGdGmh/WTnWJa/YQthlcuTa X-Received: by 2002:a17:90a:1a0b:b0:234:190d:e636 with SMTP id 11-20020a17090a1a0b00b00234190de636mr1836458pjk.8.1677850759957; Fri, 03 Mar 2023 05:39:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677850759; cv=none; d=google.com; s=arc-20160816; b=r3RR1HZqRiBS4D7io1JtiJBG+qSMCalzeTjdRYLF/9qj+PJb5ZJ5IxFad80A7NJHXY bEKXno9R1EVAZWRHy03oJ5w0vMck+6j9Cb6zmJf8wu2gQChUZYtCHhX+/8vNECa5xTRY 7TGFHmLX8YNZSVp5mhyizNAV7VvX9iva6m9FAD6O+JxQEJURaaFOIhMxEUWZ1amER8ZJ MQPIwrwfUadKKcCtXmcOuQbGo6quZNYK4N3o3S1t3auE6g5IA/Px/d2xEBFuNs2RuY4m Lk6cXtt1PkCDQhGlEoNspkj2BBQTXmUu1aEN5yND/QZI/gCYYIC1cZ6Fbnub4hhtpB8T yPWA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=V8QTnerj7bYskLlpj17RAvWj070+do7b32kQaiggteA=; b=PXDtEh2vnoaUzuMcwzp9B4TfJdJ+pRnK1Vc9Z2gqwHHF6cgIKEWycPyAm3KaXNCCca St1wPr1IRBDpKtKu/io8RysMkTiWhxTtm1Re6j6/TcJBCYpy9TgcyE7eQJLdGoFaN4K3 hGAy3EIhi+jTANMnmVnaLTP3SpKz0CnRfFF8TPkTKTeLqhhTai1OBSP16dN+JXXbaFD5 aC1dIOY+q/w5a9pVB+ABfGWEIbUXyoi9SiWd7DNbpVZhq/HhtoRy0qodWdMWpWr2lLWZ uCWnseBEIdBHFq/IgWuud3z7JQNJsrKSoJanak7b1t2Ug9uQuuLcoEk+gY19GlntxKwt Ojpg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=RgJqREjh; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Wysocki" , Len Brown , Thomas Gleixner , Marc Zyngier , Daniel Lezcano , Jonathan Corbet , Anup Patel , Andrew Jones , Atish Patra , 'Conor Dooley ' , Sunil V L , "Rafael J . Wysocki" Subject: [PATCH V3 10/20] RISC-V: smpboot: Add ACPI support in smp_setup() Date: Fri, 3 Mar 2023 19:06:37 +0530 Message-Id: <20230303133647.845095-11-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230303133647.845095-1-sunilvl@ventanamicro.com> References: <20230303133647.845095-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759354038351795533?= X-GMAIL-MSGID: =?utf-8?q?1759354038351795533?= Enable SMP boot on ACPI based platforms by using the RINTC structures in the MADT table. Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki Reviewed-by: Conor Dooley --- arch/riscv/kernel/smpboot.c | 72 ++++++++++++++++++++++++++++++++++++- 1 file changed, 71 insertions(+), 1 deletion(-) diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c index 26214ddefaa4..27047322d3bb 100644 --- a/arch/riscv/kernel/smpboot.c +++ b/arch/riscv/kernel/smpboot.c @@ -8,6 +8,7 @@ * Copyright (C) 2017 SiFive */ +#include #include #include #include @@ -70,6 +71,72 @@ void __init smp_prepare_cpus(unsigned int max_cpus) } } +#ifdef CONFIG_ACPI +static unsigned int cpu_count = 1; + +static int __init acpi_parse_rintc(union acpi_subtable_headers *header, const unsigned long end) +{ + unsigned long hart; + static bool found_boot_cpu; + struct acpi_madt_rintc *processor = (struct acpi_madt_rintc *)header; + + /* + * Each RINTC structure in MADT will have a flag. If ACPI_MADT_ENABLED + * bit in the flag is not enabled, it means OS should not try to enable + * the cpu to which RINTC belongs. + */ + if (!(processor->flags & ACPI_MADT_ENABLED)) + return 0; + + if (BAD_MADT_ENTRY(processor, end)) + return -EINVAL; + + acpi_table_print_madt_entry(&header->common); + + hart = processor->hart_id; + if (hart == INVALID_HARTID) { + pr_warn("Invalid hartid\n"); + return 0; + } + + if (hart == cpuid_to_hartid_map(0)) { + BUG_ON(found_boot_cpu); + found_boot_cpu = true; + early_map_cpu_to_node(0, NUMA_NO_NODE); + return 0; + } + + if (cpu_count >= NR_CPUS) { + pr_warn("NR_CPUS is too small for the number of ACPI tables.\n"); + return 0; + } + + cpuid_to_hartid_map(cpu_count) = hart; + early_map_cpu_to_node(cpu_count, NUMA_NO_NODE); + cpu_count++; + + return 0; +} + +static void __init acpi_parse_and_init_cpus(void) +{ + int cpuid; + + cpu_set_ops(0); + + acpi_table_parse_madt(ACPI_MADT_TYPE_RINTC, acpi_parse_rintc, 0); + + for (cpuid = 1; cpuid < nr_cpu_ids; cpuid++) { + if (cpuid_to_hartid_map(cpuid) != INVALID_HARTID) { + cpu_set_ops(cpuid); + set_cpu_possible(cpuid, true); + } + } +} +#else +#define acpi_parse_and_init_cpus(...) do { } while (0) +#endif + static void __init of_parse_and_init_cpus(void) { struct device_node *dn; @@ -118,7 +185,10 @@ static void __init of_parse_and_init_cpus(void) void __init setup_smp(void) { - of_parse_and_init_cpus(); + if (acpi_disabled) + of_parse_and_init_cpus(); + else + acpi_parse_and_init_cpus(); } static int start_secondary_cpu(int cpu, struct task_struct *tidle) From patchwork Fri Mar 3 13:36:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 63926 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp412523wrd; Fri, 3 Mar 2023 05:39:33 -0800 (PST) X-Google-Smtp-Source: AK7set9NT9I2LyCAIvUsvA1N/cvqjfDm+bNkniksJY6wjamfOHS/R1HfEgBahgLAGnMp3F33xfFl X-Received: by 2002:a05:6a00:338d:b0:5a8:d438:c72 with SMTP id cm13-20020a056a00338d00b005a8d4380c72mr5713849pfb.5.1677850772702; Fri, 03 Mar 2023 05:39:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677850772; cv=none; d=google.com; s=arc-20160816; b=QBqNAwhpcHUCgI6baZdiATmi7L0RcIIIha/tD8O7eXtZZOC24h5KGIiVSX8mxtOjEd jNqdiNeeANthOroUKZPwDQcvr/J3FZwjyLTjRKbXuB0IfgJViojA4l4EVQa6zEY9J8Hd ruhhjuUFxO0cFeKTVt9AzOlTRBnNVnjiWAbPabsroRuRZdlMVgPuMnCj1UGstZg7JJUi Oi12ecB/DYdQUtPFkgraLwMYLztP/p7xA88jZA9He40Pr2VDoZ5e4mWYElSa3fTwbE2e 4+MD57qlEXgXPwdryhKnT9rE6mnLdyINv7b0DC+UF6n73+1G2gxbN10uBCCTxy8SlVA1 CCUg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=hQCnSR2uhLGdQyOkOFgSQ8VeHxY3xwdVpRHCeTeD8ew=; b=k1ltj6b6fT7RXjTAr33jT3l9p4ous51bXfywR6rHrCEsQIWtySpMQZKLy385mcDkmd qR+2QaAO/WKtcurtwX3MnQSrO6WeC3Yf+U2wEe6Q8h+sIScVfwRLgJeElWP6zwB+Mc/K qaCXtNhx+YqegqCNZ0/JTvCm2pE1afFqtErtQQsGSbBnJiQwdzgSbIDUUy9I7IQ8w84r uoiQHw+1cRHpYyPaaG1JEClVvWsLh/mO50a9ebU6TF45mwlrn00Hwwf9RussYSIOiRB3 z+MMa6dZ6Veieop3NRBBNJSIk7Cp+UzeG0MYW5+AUUncROcd+0d6VfmfNLWOC8jqku/X PUdA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=NMLEUSb8; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Wysocki" , Len Brown , Thomas Gleixner , Marc Zyngier , Daniel Lezcano , Jonathan Corbet , Anup Patel , Andrew Jones , Atish Patra , 'Conor Dooley ' , Sunil V L , "Rafael J . Wysocki" Subject: [PATCH V3 11/20] RISC-V: ACPI: Cache and retrieve the RINTC structure Date: Fri, 3 Mar 2023 19:06:38 +0530 Message-Id: <20230303133647.845095-12-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230303133647.845095-1-sunilvl@ventanamicro.com> References: <20230303133647.845095-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759354051890005845?= X-GMAIL-MSGID: =?utf-8?q?1759354051890005845?= RINTC structures in the MADT provide mapping between the hartid and the CPU. This is required many times even at run time like cpuinfo. So, instead of parsing the ACPI table every time, cache the RINTC structures and provide a function to get the correct RINTC structure for a given cpu. Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki --- arch/riscv/include/asm/acpi.h | 9 ++++++ arch/riscv/kernel/acpi.c | 56 +++++++++++++++++++++++++++++++++++ 2 files changed, 65 insertions(+) diff --git a/arch/riscv/include/asm/acpi.h b/arch/riscv/include/asm/acpi.h index 111a8ed10af1..8be16c1ef7da 100644 --- a/arch/riscv/include/asm/acpi.h +++ b/arch/riscv/include/asm/acpi.h @@ -61,6 +61,10 @@ static inline void arch_fix_phys_package_id(int num, u32 slot) { } int acpi_get_riscv_isa(struct acpi_table_header *table, unsigned int cpu, const char **isa); + +struct acpi_madt_rintc *acpi_cpu_get_madt_rintc(int cpu); + +u32 get_acpi_id_for_cpu(int cpu); #else static inline int acpi_get_riscv_isa(struct acpi_table_header *table, unsigned int cpu, const char **isa) @@ -68,6 +72,11 @@ static inline int acpi_get_riscv_isa(struct acpi_table_header *table, return -EINVAL; } +static inline u32 get_acpi_id_for_cpu(int cpu) +{ + return -1; +} + #endif /* CONFIG_ACPI */ #endif /*_ASM_ACPI_H*/ diff --git a/arch/riscv/kernel/acpi.c b/arch/riscv/kernel/acpi.c index 81d448c41714..8b3d68d8225f 100644 --- a/arch/riscv/kernel/acpi.c +++ b/arch/riscv/kernel/acpi.c @@ -24,6 +24,62 @@ EXPORT_SYMBOL(acpi_disabled); int acpi_pci_disabled = 1; /* skip ACPI PCI scan and IRQ initialization */ EXPORT_SYMBOL(acpi_pci_disabled); +static struct acpi_madt_rintc cpu_madt_rintc[NR_CPUS]; + +static int acpi_parse_madt_rintc(union acpi_subtable_headers *header, const unsigned long end) +{ + struct acpi_madt_rintc *rintc = (struct acpi_madt_rintc *)header; + int cpuid; + + if (!(rintc->flags & ACPI_MADT_ENABLED)) + return 0; + + cpuid = riscv_hartid_to_cpuid(rintc->hart_id); + if (cpuid >= 0 && cpuid < NR_CPUS) + cpu_madt_rintc[cpuid] = *rintc; + + return 0; +} + +static int acpi_init_rintc_array(void) +{ + if (acpi_table_parse_madt(ACPI_MADT_TYPE_RINTC, acpi_parse_madt_rintc, 0) > 0) + return 0; + + return -ENODEV; +} + +/* + * Instead of parsing (and freeing) the ACPI table, cache + * the RINTC structures since they are frequently used + * like in cpuinfo. + */ +struct acpi_madt_rintc *acpi_cpu_get_madt_rintc(int cpu) +{ + static bool rintc_init_done; + + if (!rintc_init_done) { + if (acpi_init_rintc_array()) { + pr_err("No valid RINTC entries exist\n"); + return NULL; + } + + rintc_init_done = true; + } + + return &cpu_madt_rintc[cpu]; +} + +u32 get_acpi_id_for_cpu(int cpu) +{ + struct acpi_madt_rintc *rintc = acpi_cpu_get_madt_rintc(cpu); + + if (!rintc) + return -1; + + return rintc->uid; +} + /* * __acpi_map_table() will be called before paging_init(), so early_ioremap() * or early_memremap() should be called here to for ACPI table mapping. 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Wysocki" , Len Brown , Thomas Gleixner , Marc Zyngier , Daniel Lezcano , Jonathan Corbet , Anup Patel , Andrew Jones , Atish Patra , 'Conor Dooley ' , Sunil V L , "Rafael J . Wysocki" Subject: [PATCH V3 12/20] RISC-V: cpufeature: Add ACPI support in riscv_fill_hwcap() Date: Fri, 3 Mar 2023 19:06:39 +0530 Message-Id: <20230303133647.845095-13-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230303133647.845095-1-sunilvl@ventanamicro.com> References: <20230303133647.845095-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759354047785404656?= X-GMAIL-MSGID: =?utf-8?q?1759354047785404656?= On ACPI based systems, the information about the hart like ISA is provided by the RISC-V Hart Capabilities Table (RHCT). Enable filling up hwcap structure based on the information in RHCT. Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki Reviewed-by: Andrew Jones Reviewed-by: Conor Dooley --- arch/riscv/kernel/cpufeature.c | 41 ++++++++++++++++++++++++++-------- 1 file changed, 32 insertions(+), 9 deletions(-) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 59d58ee0f68d..478dbf129922 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -6,6 +6,7 @@ * Copyright (C) 2017 SiFive */ +#include #include #include #include @@ -13,6 +14,8 @@ #include #include #include +#include +#include #include #include #include @@ -91,7 +94,9 @@ void __init riscv_fill_hwcap(void) char print_str[NUM_ALPHA_EXTS + 1]; int i, j, rc; unsigned long isa2hwcap[26] = {0}; - unsigned long hartid; + struct acpi_table_header *rhct; + acpi_status status; + unsigned int cpu; isa2hwcap['i' - 'a'] = COMPAT_HWCAP_ISA_I; isa2hwcap['m' - 'a'] = COMPAT_HWCAP_ISA_M; @@ -104,18 +109,33 @@ void __init riscv_fill_hwcap(void) bitmap_zero(riscv_isa, RISCV_ISA_EXT_MAX); - for_each_of_cpu_node(node) { + if (!acpi_disabled) { + status = acpi_get_table(ACPI_SIG_RHCT, 0, &rhct); + if (ACPI_FAILURE(status)) + return; + } + + for_each_possible_cpu(cpu) { unsigned long this_hwcap = 0; DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX); const char *temp; - rc = riscv_of_processor_hartid(node, &hartid); - if (rc < 0) - continue; - - if (of_property_read_string(node, "riscv,isa", &isa)) { - pr_warn("Unable to find \"riscv,isa\" devicetree entry\n"); - continue; + if (acpi_disabled) { + node = of_cpu_device_node_get(cpu); + if (node) { + rc = of_property_read_string(node, "riscv,isa", &isa); + of_node_put(node); + if (rc) { + pr_warn("Unable to find \"riscv,isa\" devicetree entry\n"); + continue; + } + } + } else { + rc = acpi_get_riscv_isa(rhct, get_acpi_id_for_cpu(cpu), &isa); + if (rc < 0) { + pr_warn("Unable to get ISA for the hart - %d\n", cpu); + continue; + } } temp = isa; @@ -248,6 +268,9 @@ void __init riscv_fill_hwcap(void) bitmap_and(riscv_isa, riscv_isa, this_isa, RISCV_ISA_EXT_MAX); } + if (!acpi_disabled && rhct) + acpi_put_table((struct acpi_table_header *)rhct); + /* We don't support systems with F but without D, so mask those out * here. */ if ((elf_hwcap & COMPAT_HWCAP_ISA_F) && !(elf_hwcap & COMPAT_HWCAP_ISA_D)) { From patchwork Fri Mar 3 13:36:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 63928 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp412704wrd; Fri, 3 Mar 2023 05:39:53 -0800 (PST) X-Google-Smtp-Source: AK7set8n8clAjhjAIPnKTQa9VaBpfld62j3dGkDnO56cLHZidR0LaEwxP/k6lfB/ptgqz+i5et/G X-Received: by 2002:a17:902:b781:b0:19c:eb9a:770d with SMTP id e1-20020a170902b78100b0019ceb9a770dmr1703730pls.53.1677850793618; Fri, 03 Mar 2023 05:39:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677850793; cv=none; d=google.com; s=arc-20160816; b=nZBxUFvwA/a7EzO15J8t5boJOcBDWPymwRJtKZQ1XG8Rn2aqOs7JRTFspUrBE4GrVw sPKNjozhf42J9uHnBvZj6LnfE8aNtBs+S6JVgukOPlEbv95ZYxELt3vMxpMT1HPpL0/W vps5VbStaixYWLSgvVkrmgCJr13inInVE40SfI6sGUQKalsYAFhTO+uJrxIGCbKLGLfs l1AAnH+9w40aZPMrf7MXuwMpUuuADzq7GTEf2JEI3rqbKpwDTDLaAjbdoHmgaVrf4ENO 5ToPlNDzuPI09zYzIXAT6paxEK8UBqlCsjModtHe6eJ3uyhGt03d7HWQMj/8gh/lbVuZ 6FMQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=gcUANUnPmLAEK+XIpTGTIqkpKyb9BeUNqm/80XJY5vg=; b=yl7WzlRYrbbL57O3gLv+bmpj2M9tJGzeydjTzylEnjTlvl5b87BvNgOcz70gDyJl59 Bw+tSw8g0KzPrYRPzL1sn+lsStnqgeCVEA8iZARIfucDn3SabXaNCMP0nhzVACnASj4I kRmG7e97H1tCd0RBYKn+2cJ1upcL1fgKVO2rdnQ6FihP+sCJuvYU01UrX9s6axsCDXZT sA4ODTCoGq+eP0Jx2JN+Jp3ewaVCViepUZZVklbZtCeTqiEL/9ytqx2+dnGJEp9TeXFC wJ99Y7nb3KBVC4u8+u7rUIXrwa6XFPKlTi2y/HUZPgPaAHD2hjK+fjYokk63IQZYLCsC dnAA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=XkUA56V6; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Wysocki" , Len Brown , Thomas Gleixner , Marc Zyngier , Daniel Lezcano , Jonathan Corbet , Anup Patel , Andrew Jones , Atish Patra , 'Conor Dooley ' , Sunil V L , "Rafael J . Wysocki" Subject: [PATCH V3 13/20] RISC-V: cpu: Enable cpuinfo for ACPI systems Date: Fri, 3 Mar 2023 19:06:40 +0530 Message-Id: <20230303133647.845095-14-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230303133647.845095-1-sunilvl@ventanamicro.com> References: <20230303133647.845095-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759354074129189693?= X-GMAIL-MSGID: =?utf-8?q?1759354074129189693?= On ACPI based platforms, few details like ISA need to be read from the ACPI table. Enable cpuinfo on ACPI based systems. Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki Reviewed-by: Andrew Jones --- arch/riscv/kernel/cpu.c | 27 +++++++++++++++++++-------- 1 file changed, 19 insertions(+), 8 deletions(-) diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index 8400f0cc9704..80101bf77dab 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -3,10 +3,12 @@ * Copyright (C) 2012 Regents of the University of California */ +#include #include #include #include #include +#include #include #include #include @@ -283,23 +285,32 @@ static void c_stop(struct seq_file *m, void *v) static int c_show(struct seq_file *m, void *v) { unsigned long cpu_id = (unsigned long)v - 1; - struct device_node *node = of_get_cpu_node(cpu_id, NULL); struct riscv_cpuinfo *ci = per_cpu_ptr(&riscv_cpuinfo, cpu_id); + struct device_node *node; const char *compat, *isa; seq_printf(m, "processor\t: %lu\n", cpu_id); seq_printf(m, "hart\t\t: %lu\n", cpuid_to_hartid_map(cpu_id)); - if (!of_property_read_string(node, "riscv,isa", &isa)) - print_isa(m, isa); - print_mmu(m); - if (!of_property_read_string(node, "compatible", &compat) - && strcmp(compat, "riscv")) - seq_printf(m, "uarch\t\t: %s\n", compat); + + if (acpi_disabled) { + node = of_get_cpu_node(cpu_id, NULL); + if (!of_property_read_string(node, "riscv,isa", &isa)) + print_isa(m, isa); + print_mmu(m); + if (!of_property_read_string(node, "compatible", &compat) && + strcmp(compat, "riscv")) + seq_printf(m, "uarch\t\t: %s\n", compat); + of_node_put(node); + } else { + if (!acpi_get_riscv_isa(NULL, get_acpi_id_for_cpu(cpu_id), &isa)) + print_isa(m, isa); + print_mmu(m); + } + seq_printf(m, "mvendorid\t: 0x%lx\n", ci->mvendorid); seq_printf(m, "marchid\t\t: 0x%lx\n", ci->marchid); seq_printf(m, "mimpid\t\t: 0x%lx\n", ci->mimpid); seq_puts(m, "\n"); - of_node_put(node); return 0; } From patchwork Fri Mar 3 13:36:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 63927 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp412653wrd; Fri, 3 Mar 2023 05:39:46 -0800 (PST) X-Google-Smtp-Source: AK7set+OJKIQZP+DuIX3yu+Og1L0HoBSv08xdNgoAb+nNmpAWMxGL7Nj6ghKgxyBTb3yySD0kwyy X-Received: by 2002:aa7:990e:0:b0:5a8:4de2:e94e with SMTP id z14-20020aa7990e000000b005a84de2e94emr1905307pff.33.1677850785738; Fri, 03 Mar 2023 05:39:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677850785; cv=none; d=google.com; s=arc-20160816; b=EobjdJntWZ+1R0w8BVfohWNcRj4XShqSltFBpK9oNrDFSx32GgAfPr0zqHIptAH9AH l7L6Je15f68NznQpVF0MeWtQToHGd6khEQpOtfngk+qF/nJLc+GITkgnxdiqe9p4fHmZ mEAyZNFcb6W8t4Z6V6ZTGpOV1rn1Gm/+fkVtlUw6dAkXCA4n7Kvtlsy2Vjtr4EnMjOXy 754JLN8TxFZztHXX6pvM0haD+SYzfX8icPBypUiZZk2CYlNH6eHUzUA5wv1zPB5/wVUS fGE6J6Ti7DDwVZkyPwhP4UUFviiKQGSL6w6SuJ0683WSDow9/vLgyTQAJKxSNsGVUDxW dRYQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=0NTsYtUJNb7uS+HqQnID6st7LmlddjRj2NkYh86FZo0=; b=OZvRwFsM+Htpa9t8XELi26Zx6GctEOHpNG/JYUeH/n2MjtjimybvKtC8pniy3zDDTa tK17LD4GO2z925QhqjPTh4cOtueqwduWzC7z6tncJvYcbBrABiio5r0ubVQxBh/d2w0t qbDpctcKVixjB2BsrQ1Tx8lOSU0fOIzecmAp6EFULWrH84z79wkCsmthR4s94aKftu26 tQoCJ+LQmD8zQVdmYJzpC6Cv/kjJdTNQxB8+qNTTgLbCQ3FrLfrQXhPp/ZOZQyc04pae ZXi0buOCDgxvSX9HR9Ul2GxjLHb6Yv5dWOdeHBc+5qvbkpA5FQQI7+YovIcmvhBCNrBu /MKg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=M25owZtp; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Wysocki" , Len Brown , Thomas Gleixner , Marc Zyngier , Daniel Lezcano , Jonathan Corbet , Anup Patel , Andrew Jones , Atish Patra , 'Conor Dooley ' , Sunil V L , "Rafael J . Wysocki" Subject: [PATCH V3 14/20] irqchip/riscv-intc: Add ACPI support Date: Fri, 3 Mar 2023 19:06:41 +0530 Message-Id: <20230303133647.845095-15-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230303133647.845095-1-sunilvl@ventanamicro.com> References: <20230303133647.845095-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759354065556973960?= X-GMAIL-MSGID: =?utf-8?q?1759354065556973960?= Add support for initializing the RISC-V INTC driver on ACPI platforms. Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki Reviewed-by: Andrew Jones Reviewed-by: Conor Dooley --- drivers/irqchip/irq-riscv-intc.c | 77 +++++++++++++++++++++++++++----- 1 file changed, 65 insertions(+), 12 deletions(-) diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c index f229e3e66387..f522510dc1f3 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -6,6 +6,7 @@ */ #define pr_fmt(fmt) "riscv-intc: " fmt +#include #include #include #include @@ -112,6 +113,30 @@ static struct fwnode_handle *riscv_intc_hwnode(void) return intc_domain->fwnode; } +static int __init riscv_intc_init_common(struct fwnode_handle *fn) +{ + int rc; + + intc_domain = irq_domain_create_linear(fn, BITS_PER_LONG, + &riscv_intc_domain_ops, NULL); + if (!intc_domain) { + pr_err("unable to add IRQ domain\n"); + return -ENXIO; + } + + rc = set_handle_irq(&riscv_intc_irq); + if (rc) { + pr_err("failed to set irq handler\n"); + return rc; + } + + riscv_set_intc_hwnode_fn(riscv_intc_hwnode); + + pr_info("%d local interrupts mapped\n", BITS_PER_LONG); + + return 0; +} + static int __init riscv_intc_init(struct device_node *node, struct device_node *parent) { @@ -133,24 +158,52 @@ static int __init riscv_intc_init(struct device_node *node, if (riscv_hartid_to_cpuid(hartid) != smp_processor_id()) return 0; - intc_domain = irq_domain_add_linear(node, BITS_PER_LONG, - &riscv_intc_domain_ops, NULL); - if (!intc_domain) { - pr_err("unable to add IRQ domain\n"); - return -ENXIO; - } - - rc = set_handle_irq(&riscv_intc_irq); + rc = riscv_intc_init_common(of_node_to_fwnode(node)); if (rc) { - pr_err("failed to set irq handler\n"); + pr_err("failed to initialize INTC\n"); return rc; } - riscv_set_intc_hwnode_fn(riscv_intc_hwnode); + return 0; +} - pr_info("%d local interrupts mapped\n", BITS_PER_LONG); +IRQCHIP_DECLARE(riscv, "riscv,cpu-intc", riscv_intc_init); + +#ifdef CONFIG_ACPI + +static int __init riscv_intc_acpi_init(union acpi_subtable_headers *header, + const unsigned long end) +{ + int rc; + struct fwnode_handle *fn; + struct acpi_madt_rintc *rintc; + + rintc = (struct acpi_madt_rintc *)header; + + /* + * The ACPI MADT will have one INTC for each CPU (or HART) + * so riscv_intc_acpi_init() function will be called once + * for each INTC. We only do INTC initialization + * for the INTC belonging to the boot CPU (or boot HART). + */ + if (riscv_hartid_to_cpuid(rintc->hart_id) != smp_processor_id()) + return 0; + + fn = irq_domain_alloc_named_fwnode("RISCV-INTC"); + if (!fn) { + pr_err("unable to allocate INTC FW node\n"); + return -ENOMEM; + } + + rc = riscv_intc_init_common(fn); + if (rc) { + pr_err("failed to initialize INTC\n"); + return rc; + } return 0; } -IRQCHIP_DECLARE(riscv, "riscv,cpu-intc", riscv_intc_init); +IRQCHIP_ACPI_DECLARE(riscv_intc, ACPI_MADT_TYPE_RINTC, NULL, + ACPI_MADT_RINTC_VERSION_V1, riscv_intc_acpi_init); +#endif From patchwork Fri Mar 3 13:36:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 63929 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp412745wrd; Fri, 3 Mar 2023 05:39:59 -0800 (PST) X-Google-Smtp-Source: AK7set8LxjHaMJpulopuifJBXVk+9/PjrI108MziG2ptpe5DUDWEzS8e39edqVbgQCJd4blRKVQT X-Received: by 2002:a05:6a20:ba9d:b0:bf:6cd3:9510 with SMTP id fb29-20020a056a20ba9d00b000bf6cd39510mr1842606pzb.24.1677850799261; Fri, 03 Mar 2023 05:39:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677850799; cv=none; d=google.com; s=arc-20160816; b=j5fADl56ZcXlBzW1xKfRHNiLe7baPX1IjHHNQw+7QQSmnb7a7XhGIvlrPuW57AOTcW nVMH1GTQndI75UHuxnaTB4FAWrjQzQ9Ai5SVEWWHe/cgdv2K/4CjNqJvRx7ZwsPeLvd3 hHDg35sGgLOwDcnV75cs4SVAXOrCiFKmX5D0l2r2ojzHRIVaYYHZUH+Ew1B72wEJai0o YFzkwrU1xQLJGSPbtCwFBVD6lEmcp+cr445gyIYponKMBNOnLfQKiK20DIeb5Crnbqig cGcwxKn0XYbYfz+1B/jCjEucnLgX/i6d/8n4lBGkuSk/HRycETOOA9+ueTkcS03bmrDC xNTA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=7z6bEMhbWIxvIOeCxyJDoCOcsyBkr0Sn2VEh+xkIGVw=; b=YWkO8zruk76EEkoPae1OYkvru6Q5lu9eJLTl/xlAnTErXTYJkH3D/vOUp/jmTO5Uut ClrMM9Nn42QrxJd4zQids2k8tLsYzryw2MaMOaU3neyCxeiABNOXgO3V12gW6ZQR68ZH /lEy8UR29e2hhcBEOOFJKy2dMVTSReUuvi8I10kUpTxDlWCVnZP4y/XcCWQXHph5qG+L hko4cSJa97ZTBsppYk/NgMuES1zgaoPlQY/tJ4DCO0hNg3/lAmsQDPX4Ll4InBm18mRJ UzqNBSrWB+MP6fTXdd8kXyxsFI1ZsboKVEKvHtzumO8n4k4uqoUhNKtExE/xjSvg1o9n oVjg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=L1+t7UFo; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Wysocki" , Len Brown , Thomas Gleixner , Marc Zyngier , Daniel Lezcano , Jonathan Corbet , Anup Patel , Andrew Jones , Atish Patra , 'Conor Dooley ' , Sunil V L , "Rafael J . Wysocki" Subject: [PATCH V3 15/20] clocksource/timer-riscv: Refactor riscv_timer_init_dt() Date: Fri, 3 Mar 2023 19:06:42 +0530 Message-Id: <20230303133647.845095-16-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230303133647.845095-1-sunilvl@ventanamicro.com> References: <20230303133647.845095-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759354079748720307?= X-GMAIL-MSGID: =?utf-8?q?1759354079748720307?= Refactor the timer init function such that few things can be shared by both DT and ACPI based platforms. Co-developed-by: Anup Patel Signed-off-by: Anup Patel Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki Reviewed-by: Andrew Jones Reviewed-by: Conor Dooley --- drivers/clocksource/timer-riscv.c | 81 +++++++++++++++---------------- 1 file changed, 40 insertions(+), 41 deletions(-) diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c index 5f0f10c7e222..cecc4662293b 100644 --- a/drivers/clocksource/timer-riscv.c +++ b/drivers/clocksource/timer-riscv.c @@ -124,61 +124,28 @@ static irqreturn_t riscv_timer_interrupt(int irq, void *dev_id) return IRQ_HANDLED; } -static int __init riscv_timer_init_dt(struct device_node *n) +static int __init riscv_timer_init_common(void) { - int cpuid, error; - unsigned long hartid; - struct device_node *child; + int error; struct irq_domain *domain; + struct fwnode_handle *intc_fwnode = riscv_get_intc_hwnode(); - error = riscv_of_processor_hartid(n, &hartid); - if (error < 0) { - pr_warn("Not valid hartid for node [%pOF] error = [%lu]\n", - n, hartid); - return error; - } - - cpuid = riscv_hartid_to_cpuid(hartid); - if (cpuid < 0) { - pr_warn("Invalid cpuid for hartid [%lu]\n", hartid); - return cpuid; - } - - if (cpuid != smp_processor_id()) - return 0; - - child = of_find_compatible_node(NULL, NULL, "riscv,timer"); - if (child) { - riscv_timer_cannot_wake_cpu = of_property_read_bool(child, - "riscv,timer-cannot-wake-cpu"); - of_node_put(child); - } - - domain = NULL; - child = of_get_compatible_child(n, "riscv,cpu-intc"); - if (!child) { - pr_err("Failed to find INTC node [%pOF]\n", n); - return -ENODEV; - } - domain = irq_find_host(child); - of_node_put(child); + domain = irq_find_matching_fwnode(intc_fwnode, DOMAIN_BUS_ANY); if (!domain) { - pr_err("Failed to find IRQ domain for node [%pOF]\n", n); + pr_err("Failed to find irq_domain for INTC node [%pfwP]\n", + intc_fwnode); return -ENODEV; } riscv_clock_event_irq = irq_create_mapping(domain, RV_IRQ_TIMER); if (!riscv_clock_event_irq) { - pr_err("Failed to map timer interrupt for node [%pOF]\n", n); + pr_err("Failed to map timer interrupt for node [%pfwP]\n", intc_fwnode); return -ENODEV; } - pr_info("%s: Registering clocksource cpuid [%d] hartid [%lu]\n", - __func__, cpuid, hartid); error = clocksource_register_hz(&riscv_clocksource, riscv_timebase); if (error) { - pr_err("RISCV timer register failed [%d] for cpu = [%d]\n", - error, cpuid); + pr_err("RISCV timer registration failed [%d]\n", error); return error; } @@ -207,4 +174,36 @@ static int __init riscv_timer_init_dt(struct device_node *n) return error; } +static int __init riscv_timer_init_dt(struct device_node *n) +{ + int cpuid, error; + unsigned long hartid; + struct device_node *child; + + error = riscv_of_processor_hartid(n, &hartid); + if (error < 0) { + pr_warn("Invalid hartid for node [%pOF] error = [%lu]\n", + n, hartid); + return error; + } + + cpuid = riscv_hartid_to_cpuid(hartid); + if (cpuid < 0) { + pr_warn("Invalid cpuid for hartid [%lu]\n", hartid); + return cpuid; + } + + if (cpuid != smp_processor_id()) + return 0; + + child = of_find_compatible_node(NULL, NULL, "riscv,timer"); + if (child) { + riscv_timer_cannot_wake_cpu = of_property_read_bool(child, + "riscv,timer-cannot-wake-cpu"); + of_node_put(child); + } + + return riscv_timer_init_common(); +} + TIMER_OF_DECLARE(riscv_timer, "riscv", riscv_timer_init_dt); From patchwork Fri Mar 3 13:36:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 63930 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp412810wrd; Fri, 3 Mar 2023 05:40:07 -0800 (PST) X-Google-Smtp-Source: AK7set8NgGw5pw39Orrx5NlQBe2mcvQ8PoplcdMbkUGYivaQXTyxOpuoCw1I7RMXdUyhDVlB2FSr X-Received: by 2002:a17:902:a511:b0:19c:fd9e:f88c with SMTP id s17-20020a170902a51100b0019cfd9ef88cmr1706528plq.18.1677850807515; Fri, 03 Mar 2023 05:40:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677850807; cv=none; d=google.com; s=arc-20160816; b=GtBLodXSihyBjKzOztNLydn+NpurrtsRbPcAGu+wO7pCZodIyR4DWyGEWKzqW455iE SiL2Q/wwm3xywvPL5I88wEFPT4Tptj/vAhmL+f7zeyUAWb9Ty8jaS3unxEaDrihg3gaw bfjXosSXcDgPKs2unD5oq5Yr3IJyZWNlWsYlxyHnkNlNJ0GEnb7wbGFi0BbvWLsXhTV7 l9tB0oD2fPlrEXNyT6PzjN5oLw/kEyaaoPM5hSmodyuFjDPkq/VH4QRrdMkGXMg3vAgB /j75mxDLBAPfXcwNG8ZmSd1WtT0JgEqQinCgqSDcUIzXHSilyquA/xdZiIwD0UlQAi5z i1ww== ARC-Message-Signature: i=1; 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Wysocki" , Len Brown , Thomas Gleixner , Marc Zyngier , Daniel Lezcano , Jonathan Corbet , Anup Patel , Andrew Jones , Atish Patra , 'Conor Dooley ' , Sunil V L , "Rafael J . Wysocki" Subject: [PATCH V3 16/20] clocksource/timer-riscv: Add ACPI support Date: Fri, 3 Mar 2023 19:06:43 +0530 Message-Id: <20230303133647.845095-17-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230303133647.845095-1-sunilvl@ventanamicro.com> References: <20230303133647.845095-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759354088429377612?= X-GMAIL-MSGID: =?utf-8?q?1759354088429377612?= Initialize the timer driver based on RHCT table on ACPI based platforms. Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki Reviewed-by: Andrew Jones --- drivers/clocksource/timer-riscv.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c index cecc4662293b..da3071b387eb 100644 --- a/drivers/clocksource/timer-riscv.c +++ b/drivers/clocksource/timer-riscv.c @@ -10,6 +10,7 @@ #define pr_fmt(fmt) "riscv-timer: " fmt +#include #include #include #include @@ -207,3 +208,13 @@ static int __init riscv_timer_init_dt(struct device_node *n) } TIMER_OF_DECLARE(riscv_timer, "riscv", riscv_timer_init_dt); + +#ifdef CONFIG_ACPI +static int __init riscv_timer_acpi_init(struct acpi_table_header *table) +{ + return riscv_timer_init_common(); +} + +TIMER_ACPI_DECLARE(aclint_mtimer, ACPI_SIG_RHCT, riscv_timer_acpi_init); + +#endif From patchwork Fri Mar 3 13:36:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 63932 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp412941wrd; Fri, 3 Mar 2023 05:40:27 -0800 (PST) X-Google-Smtp-Source: AK7set9e/aIXX/m+Tnjdwrm0gi+Jb31XJkMSEfU0jGbzlshD7VTxmudbvO5hzRFdZQZeKv1PIdV6 X-Received: by 2002:aa7:9ae9:0:b0:5a8:a973:450a with SMTP id y9-20020aa79ae9000000b005a8a973450amr1933500pfp.2.1677850827343; Fri, 03 Mar 2023 05:40:27 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677850827; cv=none; d=google.com; s=arc-20160816; b=eHiWXbTVz+Cgjay3ifFY15WzJp1EQqnAdvUjtteMOIPsz8cvICkTpOiRZ1bHqMhdw4 w20SUL6vksAHB4jdXpinfL29xxghmxzuGKC+qEB2O9bP2VGw+KLRsvhv3hodfR7524xY JUGSQk6+gjzzUxzAC481q3b/M9nbnEr30QZVLr2U9zgZ4Nx/OITGSBCRM7rpgAMIBwiC 8WcAhXufWTXSNxYsvd2phRecSV7+gIOhGz+UYHefohjJuMTdKqN5fjyHTLzHQELZh4Y6 ewcNUXOZw5ylczJOJgJJam3NdkEUiLpojVPH/EdxZqdLMeEqw+hhtO+6jBL98JQC90wR oYvg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=VUObxxi7Z2aUmCgcrqeWxF5lW/0L9jWTmCmlO9qrT1Q=; b=csl3i6O9L9zmTqdKrRCjclXxPqk+U9BgPGFqayl73+QENYd56Trg04BsM7m9Tx7MMT eCtGhvn6Er3fstbmsl6gnta24LJKzrgikAOb1bPj+wgEzlie5CoQHfyZ/9L6JhB7A9wD yFKvH+u1H15Dw9Os14nUEl9qBoFDb9NyHLzmnpMmfmSg/jfJRGNkUqthjN/LnMTpQiO3 49tDiY4j8eLNS1/jOEjWUuaF0SntzDVwAYBUnAISX9IAnGVKuQqb9mNxfz9vSkgAk1iF Obg6j1Oyjw6NDB4s9/L3M5rRfwxgwhNos67F4luAXpLbjHqHjJtdwdH48cCfy24gi6l6 Bp6w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=h9zxegf8; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Wysocki" , Len Brown , Thomas Gleixner , Marc Zyngier , Daniel Lezcano , Jonathan Corbet , Anup Patel , Andrew Jones , Atish Patra , 'Conor Dooley ' , Sunil V L , "Rafael J . Wysocki" Subject: [PATCH V3 17/20] RISC-V: time.c: Add ACPI support for time_init() Date: Fri, 3 Mar 2023 19:06:44 +0530 Message-Id: <20230303133647.845095-18-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230303133647.845095-1-sunilvl@ventanamicro.com> References: <20230303133647.845095-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759354109091521616?= X-GMAIL-MSGID: =?utf-8?q?1759354109091521616?= On ACPI based platforms, timer related information is available in RHCT. Add ACPI based probe support to the timer initialization. Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki Reviewed-by: Andrew Jones Reviewed-by: Conor Dooley --- arch/riscv/kernel/time.c | 23 +++++++++++++++++------ 1 file changed, 17 insertions(+), 6 deletions(-) diff --git a/arch/riscv/kernel/time.c b/arch/riscv/kernel/time.c index babaf3b48ba8..2c29543549c3 100644 --- a/arch/riscv/kernel/time.c +++ b/arch/riscv/kernel/time.c @@ -4,6 +4,7 @@ * Copyright (C) 2017 SiFive */ +#include #include #include #include @@ -18,17 +19,27 @@ EXPORT_SYMBOL_GPL(riscv_timebase); void __init time_init(void) { struct device_node *cpu; + struct acpi_table_rhct *rhct; + acpi_status status; u32 prop; - cpu = of_find_node_by_path("/cpus"); - if (!cpu || of_property_read_u32(cpu, "timebase-frequency", &prop)) - panic(KERN_WARNING "RISC-V system with no 'timebase-frequency' in DTS\n"); - of_node_put(cpu); - riscv_timebase = prop; + if (acpi_disabled) { + cpu = of_find_node_by_path("/cpus"); + if (!cpu || of_property_read_u32(cpu, "timebase-frequency", &prop)) + panic("RISC-V system with no 'timebase-frequency' in DTS\n"); + of_node_put(cpu); + riscv_timebase = prop; + of_clk_init(NULL); + } else { + status = acpi_get_table(ACPI_SIG_RHCT, 0, (struct acpi_table_header **)&rhct); + if (ACPI_FAILURE(status)) + panic("RISC-V ACPI system with no RHCT table\n"); + riscv_timebase = rhct->time_base_freq; + acpi_put_table((struct acpi_table_header *)rhct); + } lpj_fine = riscv_timebase / HZ; - of_clk_init(NULL); timer_probe(); tick_setup_hrtimer_broadcast(); From patchwork Fri Mar 3 13:36:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 63931 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp412859wrd; Fri, 3 Mar 2023 05:40:15 -0800 (PST) X-Google-Smtp-Source: AK7set9LfvkrmEx37JzfxGxYP9AVUeVpfjkRzpe1JRYTQxXlY1V4FVdReQg2BBsieeDihGvp2LUk X-Received: by 2002:aa7:8f04:0:b0:5a9:d58e:796f with SMTP id x4-20020aa78f04000000b005a9d58e796fmr2007274pfr.29.1677850814774; Fri, 03 Mar 2023 05:40:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677850814; cv=none; d=google.com; s=arc-20160816; b=C53CejyK2/LFfOwTfI9FVmMbqLOYZitRYvcJeWxZGHP9yMFOgW4kwUuPvjJ1s1kqZj gB3En3kI76HskHWkyqIltt23IOyJ1Xzj6mtQ3C1g/tQbXs/uy3RzcsCGUO5cbXMZlu1H OMoM7OUi5jAH06zIe0QFPYmQ2wrctnVdWEs2v4CD6dHKQXNOH995b7BuXCkm3+6JcBsC +FuY3fTXutAta7ZNBKMT9hORJZjMMFxf2trnM56lX6SdDc5+tJ3VnLrNp4BVpeJ9+2WZ fjrC+oLg2/AGNHOmAAw1qcpG1Cdnc9K3ljppiKSqYjoXjqP3Ae47oE2uBL/9z/lxVp0D ZxIQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=PnWMRVmSE/FRN1G4jePLo7NyPHxO3nOfwGFEZAQeYgw=; b=xI1bXaneX9XT2rll6CkTAvZh0eatlbvhy7Qu/djvrAWBhqARERjiGSdCXBoZxB98i4 7mcF4jEx+4+ZtGJGjYi3GZcMdL63hOVykEknpGIH8IioTa74e61CNp6njYoHkRXDxY94 7PS1IBHiwC8KejGz/usht3n239+/vCtJgu+yJjft67CiD0gu3NcrdLTPaKd121+NDqIE V6FhdGvj13oyfdMUD4h8LAUTgEB8CUYuzAMIwCFoTiiJe3YNpzUQjYtU3L3hVAZkhUw7 JTSjvgPs7TgNWO+TpjXzVy2ysMaG3qSEk5hiSho0jvE4pAzijgpzSLDE5xdK+u8dSS8H 8qNA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b="AG/Tf51+"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Wysocki" , Len Brown , Thomas Gleixner , Marc Zyngier , Daniel Lezcano , Jonathan Corbet , Anup Patel , Andrew Jones , Atish Patra , 'Conor Dooley ' , Sunil V L , "Rafael J . Wysocki" Subject: [PATCH V3 18/20] RISC-V: Add ACPI initialization in setup_arch() Date: Fri, 3 Mar 2023 19:06:45 +0530 Message-Id: <20230303133647.845095-19-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230303133647.845095-1-sunilvl@ventanamicro.com> References: <20230303133647.845095-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759354096118690570?= X-GMAIL-MSGID: =?utf-8?q?1759354096118690570?= Initialize the ACPI core for RISC-V during boot. ACPI tables and interpreter are initialized based on the information passed from the firmware and the value of the kernel parameter 'acpi'. With ACPI support added for RISC-V, the kernel parameter 'acpi' is also supported on RISC-V. Hence, update the documentation. Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki Reviewed-by: Andrew Jones Acked-by: Conor Dooley --- .../admin-guide/kernel-parameters.txt | 8 +- arch/riscv/kernel/acpi.c | 126 ++++++++++++++++++ arch/riscv/kernel/setup.c | 25 ++-- 3 files changed, 147 insertions(+), 12 deletions(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 6221a1d057dd..047679554453 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -1,17 +1,17 @@ - acpi= [HW,ACPI,X86,ARM64] + acpi= [HW,ACPI,X86,ARM64,RISCV64] Advanced Configuration and Power Interface Format: { force | on | off | strict | noirq | rsdt | copy_dsdt } force -- enable ACPI if default was off - on -- enable ACPI but allow fallback to DT [arm64] + on -- enable ACPI but allow fallback to DT [arm64,riscv64] off -- disable ACPI if default was on noirq -- do not use ACPI for IRQ routing strict -- Be less tolerant of platforms that are not strictly ACPI specification compliant. rsdt -- prefer RSDT over (default) XSDT copy_dsdt -- copy DSDT to memory - For ARM64, ONLY "acpi=off", "acpi=on" or "acpi=force" - are available + For ARM64 and RISCV64, ONLY "acpi=off", "acpi=on" or + "acpi=force" are available See also Documentation/power/runtime_pm.rst, pci=noacpi diff --git a/arch/riscv/kernel/acpi.c b/arch/riscv/kernel/acpi.c index 8b3d68d8225f..9b6841700e30 100644 --- a/arch/riscv/kernel/acpi.c +++ b/arch/riscv/kernel/acpi.c @@ -16,6 +16,7 @@ #include #include #include +#include int acpi_noirq = 1; /* skip ACPI IRQ initialization */ int acpi_disabled = 1; @@ -25,6 +26,131 @@ int acpi_pci_disabled = 1; /* skip ACPI PCI scan and IRQ initialization */ EXPORT_SYMBOL(acpi_pci_disabled); static struct acpi_madt_rintc cpu_madt_rintc[NR_CPUS]; +static bool param_acpi_off __initdata; +static bool param_acpi_on __initdata; +static bool param_acpi_force __initdata; + +static int __init parse_acpi(char *arg) +{ + if (!arg) + return -EINVAL; + + /* "acpi=off" disables both ACPI table parsing and interpreter */ + if (strcmp(arg, "off") == 0) + param_acpi_off = true; + else if (strcmp(arg, "on") == 0) /* prefer ACPI over DT */ + param_acpi_on = true; + else if (strcmp(arg, "force") == 0) /* force ACPI to be enabled */ + param_acpi_force = true; + else + return -EINVAL; /* Core will print when we return error */ + + return 0; +} +early_param("acpi", parse_acpi); + +/* + * acpi_fadt_sanity_check() - Check FADT presence and carry out sanity + * checks on it + * + * Return 0 on success, <0 on failure + */ +static int __init acpi_fadt_sanity_check(void) +{ + struct acpi_table_header *table; + struct acpi_table_fadt *fadt; + acpi_status status; + int ret = 0; + + /* + * FADT is required on riscv; retrieve it to check its presence + * and carry out revision and ACPI HW reduced compliancy tests + */ + status = acpi_get_table(ACPI_SIG_FADT, 0, &table); + if (ACPI_FAILURE(status)) { + const char *msg = acpi_format_exception(status); + + pr_err("Failed to get FADT table, %s\n", msg); + return -ENODEV; + } + + fadt = (struct acpi_table_fadt *)table; + + /* + * Revision in table header is the FADT Major revision, and there + * is a minor revision of FADT. + * + * TODO: Currently, we check for 6.5 as the minimum version to check + * for HW_REDUCED flag. However, once RISC-V updates are released in + * the ACPI spec, we need to update this check for exact minor revision + */ + if (table->revision < 6 || (table->revision == 6 && fadt->minor_revision < 5)) { + pr_err(FW_BUG "Unsupported FADT revision %d.%d, should be 6.5+\n", + table->revision, fadt->minor_revision); + } + + if (!(fadt->flags & ACPI_FADT_HW_REDUCED)) { + pr_err("FADT not ACPI hardware reduced compliant\n"); + ret = -EINVAL; + } + + /* + * acpi_get_table() creates FADT table mapping that + * should be released after parsing and before resuming boot + */ + acpi_put_table(table); + return ret; +} + +/* + * acpi_boot_table_init() called from setup_arch(), always. + * 1. find RSDP and get its address, and then find XSDT + * 2. extract all tables and checksums them all + * 3. check ACPI FADT HW reduced flag + * + * We can parse ACPI boot-time tables such as MADT after + * this function is called. + * + * On return ACPI is enabled if either: + * + * - ACPI tables are initialized and sanity checks passed + * - acpi=force was passed in the command line and ACPI was not disabled + * explicitly through acpi=off command line parameter + * + * ACPI is disabled on function return otherwise + */ +void __init acpi_boot_table_init(void) +{ + /* + * Enable ACPI instead of device tree unless + * - ACPI has been disabled explicitly (acpi=off), or + * - firmware has not populated ACPI ptr in EFI system table + * and ACPI has not been [force] enabled (acpi=on|force) + */ + if (param_acpi_off || + (!param_acpi_on && !param_acpi_force && + efi.acpi20 == EFI_INVALID_TABLE_ADDR)) + return; + + /* + * ACPI is disabled at this point. Enable it in order to parse + * the ACPI tables and carry out sanity checks + */ + enable_acpi(); + + /* + * If ACPI tables are initialized and FADT sanity checks passed, + * leave ACPI enabled and carry on booting; otherwise disable ACPI + * on initialization error. + * If acpi=force was passed on the command line it forces ACPI + * to be enabled even if its initialization failed. + */ + if (acpi_table_init() || acpi_fadt_sanity_check()) { + pr_err("Failed to init ACPI tables\n"); + if (!param_acpi_force) + disable_acpi(); + } +} static int acpi_parse_madt_rintc(union acpi_subtable_headers *header, const unsigned long end) { diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c index 2d45a416d283..7b2b065a9f70 100644 --- a/arch/riscv/kernel/setup.c +++ b/arch/riscv/kernel/setup.c @@ -8,6 +8,7 @@ * Nick Kossifidis */ +#include #include #include #include @@ -276,14 +277,22 @@ void __init setup_arch(char **cmdline_p) efi_init(); paging_init(); -#if IS_ENABLED(CONFIG_BUILTIN_DTB) - unflatten_and_copy_device_tree(); -#else - if (early_init_dt_verify(__va(XIP_FIXUP(dtb_early_pa)))) - unflatten_device_tree(); - else - pr_err("No DTB found in kernel mappings\n"); -#endif + + /* Parse the ACPI tables for possible boot-time configuration */ + acpi_boot_table_init(); + if (acpi_disabled) { + if (IS_ENABLED(CONFIG_BUILTIN_DTB)) { + unflatten_and_copy_device_tree(); + } else { + if (early_init_dt_verify(__va(XIP_FIXUP(dtb_early_pa)))) + unflatten_device_tree(); + else + pr_err("No DTB found in kernel mappings\n"); + } + } else { + early_init_dt_verify(__va(XIP_FIXUP(dtb_early_pa))); + } + early_init_fdt_scan_reserved_mem(); misc_mem_init(); From patchwork Fri Mar 3 13:36:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 63935 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp425926wrd; Fri, 3 Mar 2023 06:05:35 -0800 (PST) X-Google-Smtp-Source: AK7set/oLQgYAsE04soJ735rcTmqIymuIAhCZHDeZEgCegPvfRcPn/RgnULAs5RHKPFZkqreC7m2 X-Received: by 2002:a17:903:124d:b0:19e:7477:9cb4 with SMTP id u13-20020a170903124d00b0019e74779cb4mr2404290plh.44.1677852335603; Fri, 03 Mar 2023 06:05:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677852335; cv=none; d=google.com; s=arc-20160816; b=n/92GuNrjwSTDuQFPhdQXeHPxbo/CRnQBdIguiRKvSyFHkDezIhyTnLmCNo6BQXZme io4T/M3PHcudOSnBtVWXhUqIgPIGOILSUC+vb5J9c0RRMUWLrPlyb4QW8VvZk3CVkPX4 oZDRZqsRjtsn1JTKJRinTwD39+5eyAwvE37L0r72MYtxX9btPyyko7HfB+butU42oeAa MDrqrMxaYcSEnPVTa9jFYATUiNtjB9aL8xXxFdbUKSqGw7pCxBPXunJ92r5vgVyOm1o7 fCUmizvdGH41NcA3p2OI7jMZxlliwd9xGU78p+W/m2b+AQTsHKmGVHKhTzEYIt4HHON8 EAuA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=owG1+TzWR6HEJY+37PeJPSBafU3Oc/UAH6XvLtB/Z/0=; b=l8sgzGa+4VvUZW/EdrJ7tfUG/+1khhj0TWhGfXaYyhdOR3P6Ug301LvpCM7iDxMP7s oiCrvA90/wcT06xiNXaap34nIU4EfCVofqaERqSSZubOhqRwfNDuEZIhDm0AR1eg4f4V hkCRn7Ol2C6QQ6sjRDK9qfoEjhkg3SF66RH6GkwtmCZwrvCRtIjvtIJUhFCE0o08SHoz 7CDpumZbk0rMG2hGDZxAUP3EhWmbbNnFxa3dE4CEvTNKLAp5gaT57+Z7nrVPvQKCcTkv 9vnmLXIix+4voNdiVXavXJ8rYcT06nPb8VokU8wk3UbHcaUJXCe3rtDcGBI170RKC5AY WCFw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=ALnrkent; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Wysocki" , Len Brown , Thomas Gleixner , Marc Zyngier , Daniel Lezcano , Jonathan Corbet , Anup Patel , Andrew Jones , Atish Patra , 'Conor Dooley ' , Sunil V L , "Rafael J . Wysocki" Subject: [PATCH V3 19/20] RISC-V: Enable ACPI in defconfig Date: Fri, 3 Mar 2023 19:06:46 +0530 Message-Id: <20230303133647.845095-20-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230303133647.845095-1-sunilvl@ventanamicro.com> References: <20230303133647.845095-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759355690145192869?= X-GMAIL-MSGID: =?utf-8?q?1759355690145192869?= Add support to build ACPI subsystem in defconfig. Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki Reviewed-by: Andrew Jones Reviewed-by: Conor Dooley --- arch/riscv/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index d98d6e90b2b8..8822b49ddb59 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -238,3 +238,4 @@ CONFIG_RCU_EQS_DEBUG=y # CONFIG_FTRACE is not set # CONFIG_RUNTIME_TESTING_MENU is not set CONFIG_MEMTEST=y +CONFIG_ACPI=y From patchwork Fri Mar 3 13:36:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 63937 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp427218wrd; Fri, 3 Mar 2023 06:07:35 -0800 (PST) X-Google-Smtp-Source: AK7set8HHlzs2ZtQIsDRsJ86EjR8G5c01WXjzOqNSB2M/6EXw4waszuXKHfjwMFzA9ksaTAH/2Un X-Received: by 2002:a17:906:f143:b0:8b1:2d0e:281 with SMTP id gw3-20020a170906f14300b008b12d0e0281mr1698254ejb.18.1677852454968; Fri, 03 Mar 2023 06:07:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677852454; cv=none; d=google.com; s=arc-20160816; b=TRYAyxNSr6Y7Mq0BndJIwhB6FgwJ0MU+XGvCPjVK+K6cLySLAmxN6oGhFaUQaS2BVM kfdNicAB7O8dmW9h7mK1UvWuPdSvKW+FIdZm/KW4cKz0eqfU7NMO2JS70NhrLeOfCaUN hf1tqL7SZOD9+uKoUIYHSF2n1w2pJBZCLfRbEIHgNfHK85OVG+TRcLm/WNhjfGvVozou tgwFj9tp+CjLERKoqA8cVvUwxTeq2iacli3/KATNa/xZvCNu1IrVg/7mB4AaEBILV7IK 5iGaOpkhQKY81RWXM5+K524s0nZffVJn+hX8ImXyzLPpy6U3m17wbMqz7Vo3wvyNpssw HDtA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=2Vlvg0s0GLD+Fr0ivx6kMGA1aXXCTSFKFG2h3P4PYF0=; b=hIc24lzGRx4XXiHX1LPrDYuGUhCkQhDfv/3SmtoLkCSO/qMzgEVf7+syXp3gjFIyMw pwy/oK8/zAfA7CMHzF7glUD4zzQHvZSmJA+H6rIXpCpIJRcq2mHuYmYAuKAFDCbSiUqn pw6Ajndxh93bB0pHvqDmWgNccmFusvMhWaJzNTvzKF31Tca2V2w6OVBLpV9/vpGj7IzB 3Utwk6EzSB69wH0zTdRU/MSFsLW4rkh378FCdHQLSGs1Wt4JznWq6Jf07EHKzOG9LnRV hBF97exc9aZjs5w3/PKJCVH/qXi1gCnE4vXCIWefLpd9ReAbjroz4gOoARZWhWtyr1XH 1++g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=exWsSVAj; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Wysocki" , Len Brown , Thomas Gleixner , Marc Zyngier , Daniel Lezcano , Jonathan Corbet , Anup Patel , Andrew Jones , Atish Patra , 'Conor Dooley ' , Sunil V L , "Rafael J . Wysocki" Subject: [PATCH V3 20/20] MAINTAINERS: Add entry for drivers/acpi/riscv Date: Fri, 3 Mar 2023 19:06:47 +0530 Message-Id: <20230303133647.845095-21-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230303133647.845095-1-sunilvl@ventanamicro.com> References: <20230303133647.845095-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759355816018115489?= X-GMAIL-MSGID: =?utf-8?q?1759355816018115489?= ACPI defines few RISC-V specific tables which need parsing code added in drivers/acpi/riscv. Add maintainer entries for this newly created folder. Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index b0db911207ba..c299f88cb212 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -406,6 +406,14 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained F: drivers/acpi/arm64 +ACPI FOR RISC-V (ACPI/riscv) +M: Sunil V L +L: linux-acpi@vger.kernel.org +L: linux-riscv@lists.infradead.org +S: Maintained +F: arch/riscv/kernel/acpi.c +F: drivers/acpi/riscv + ACPI SERIAL MULTI INSTANTIATE DRIVER M: Hans de Goede L: platform-driver-x86@vger.kernel.org