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[2620:137:e000::1:20]) by mx.google.com with ESMTP id md8-20020a17090b23c800b0023082ccac58si1312037pjb.7.2023.03.02.19.18.25; Thu, 02 Mar 2023 19:18:38 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=E50r4WW2; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229809AbjCCDRn (ORCPT + 99 others); Thu, 2 Mar 2023 22:17:43 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36734 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229455AbjCCDRj (ORCPT ); Thu, 2 Mar 2023 22:17:39 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 358A414E89; Thu, 2 Mar 2023 19:17:35 -0800 (PST) X-UUID: ef320d66b97111ed945fc101203acc17-20230303 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=zIlJ7NybosfQq5qKIS3xQ+78hBjmgkGkVjNteGRkKmo=; b=E50r4WW2doidIVpBONyCS326BLm3tgiJVzhXgTZGRSe30mQDBjedESnN4W0xLe05W3n1KrwdQThIC18YMS0o28KLqbb16nnMrEi4qYzC7dEus7aCnPTyHe9DxU6RsXLIa20OfB3JNF1q46emUrbTLNLWR+iXkLkt7pnSgvcAt/0=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.20,REQID:f592460b-2aa3-4d94-afc9-67ecb8a47a5d,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:25b5999,CLOUDID:64b13027-564d-42d9-9875-7c868ee415ec,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0 X-CID-BVR: 0,NGT X-UUID: ef320d66b97111ed945fc101203acc17-20230303 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 262018460; Fri, 03 Mar 2023 11:17:31 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.25; Fri, 3 Mar 2023 11:17:30 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.25 via Frontend Transport; Fri, 3 Mar 2023 11:17:29 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , Krzysztof Kozlowski , Stephen Boyd , AngeloGioacchino Del Regno CC: , , , , , , Allen-KH Cheng Subject: [PATCH v3 1/7] arm64: dts: mediatek: mt8186: Add MTU3 nodes Date: Fri, 3 Mar 2023 11:17:22 +0800 Message-ID: <20230303031728.24251-2-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230303031728.24251-1-allen-kh.cheng@mediatek.com> References: <20230303031728.24251-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS, SPF_PASS,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759314988776428035?= X-GMAIL-MSGID: =?utf-8?q?1759314988776428035?= Add MTU3 nodes for MT8186 SoC. Signed-off-by: Allen-KH Cheng Tested-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 68 ++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi index a0d3e1f731bd..178421fd8380 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -981,6 +981,40 @@ status = "disabled"; }; + ssusb0: usb@11201000 { + compatible = "mediatek,mt8186-mtu3", "mediatek,mtu3"; + reg = <0 0x11201000 0 0x2dff>, <0 0x11203e00 0 0x0100>; + reg-names = "mac", "ippc"; + clocks = <&topckgen CLK_TOP_USB_TOP>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_HCLK>, + <&infracfg_ao CLK_INFRA_AO_ICUSB>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; + interrupts = ; + phys = <&u2port0 PHY_TYPE_USB2>; + power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + usb_host0: usb@11200000 { + compatible = "mediatek,mt8186-xhci", "mediatek,mtk-xhci"; + reg = <0 0x11200000 0 0x1000>; + reg-names = "mac"; + clocks = <&topckgen CLK_TOP_USB_TOP>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_REF>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_HCLK>, + <&infracfg_ao CLK_INFRA_AO_ICUSB>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_XHCI>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; + interrupts = ; + mediatek,syscon-wakeup = <&pericfg 0x420 2>; + wakeup-source; + status = "disabled"; + }; + }; + mmc0: mmc@11230000 { compatible = "mediatek,mt8186-mmc", "mediatek,mt8183-mmc"; @@ -1012,6 +1046,40 @@ status = "disabled"; }; + ssusb1: usb@11281000 { + compatible = "mediatek,mt8186-mtu3", "mediatek,mtu3"; + reg = <0 0x11281000 0 0x2dff>, <0 0x11283e00 0 0x0100>; + reg-names = "mac", "ippc"; + clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_HCLK>, + <&clk26m>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; + interrupts = ; + phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>; + power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB_P1>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + usb_host1: usb@11280000 { + compatible = "mediatek,mt8186-xhci", "mediatek,mtk-xhci"; + reg = <0 0x11280000 0 0x1000>; + reg-names = "mac"; + clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_SYS>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_REF>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_HCLK>, + <&clk26m>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_XHCI>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck","xhci_ck"; + interrupts = ; + mediatek,syscon-wakeup = <&pericfg 0x424 2>; + wakeup-source; + status = "disabled"; + }; + }; + u3phy0: t-phy@11c80000 { compatible = "mediatek,mt8186-tphy", "mediatek,generic-tphy-v2"; From patchwork Fri Mar 3 03:17:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Allen-KH Cheng X-Patchwork-Id: 63744 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp199541wrd; Thu, 2 Mar 2023 19:18:54 -0800 (PST) X-Google-Smtp-Source: AK7set+kCxQWWmfubaLIWqNGvqAQ8CMu/Y2RfpVbfS8xOldGngzeXGJg73e6PQ0PRVIv94oyCb7K X-Received: by 2002:a17:90a:d905:b0:234:190d:e649 with SMTP id c5-20020a17090ad90500b00234190de649mr98012pjv.19.1677813534402; Thu, 02 Mar 2023 19:18:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677813534; cv=none; d=google.com; s=arc-20160816; b=X+7s5wvXH2u6C9TYtsSz35CEijY/8kPWqnoqiF1ORaAgglVwYZUIT9qcdlD4Wjxy1s ZTQq7VJX0r6kqoXYFI8wuEhB/aY+cALqFuxfg8FBdwX5t5/r/zmVMsok0UmxJCCRIwFT Ddnz1Tf5u6+KUkQEckznHO781994xD3DW0mXBhjc0ggRldKSctbozfgTKJMhr4xtqQf5 ttZJWsxHl7olzka5l6m83tudvS6knmMr1CzZXGgkTZbSeQEdq4W53YstLIbkg/45om5U 4Aa4BbKReXvtoESqo5nlodabXEjPvbYcNTOo25/NNk0h7jWeoUuLHr6BvMpWI6orPtvG 66bg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=goIbo3K+z0Hxyibw+E8BXKuErUNw5ptKNsoK8dl9Ed0=; b=Wr1U8XF5hiGcGObnupoK7kKhKTksuOerDPFTA6vuNNRZnekn9oGyv8n/mN1tf2uBTe bmkDQsahZEWt/zym/tt53/ceQQ89yZ+MACMJXiUZALppH7xHK631WT01Xz14pw/7ZlF9 AUau20N1jIqITtuFQxkMCTuGlT4zUUp3Jn1XR+i5LhVbwLz2Zm6yvXjQjfE4i3DEGlnY PJTrtFzMW38H1wICVExE9r/SvSVYtvvRLwUXy1Fm9H/PU46kpw0dJs4ycjOPjBrkltPp 8ck6ogPdi9HejpSZDBnll6cToHDh9n/BXepLZTYdRb9vALmOqDZvVx3hkYs6H5hl2Shp mAwQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=e59GAwr3; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Allen-KH Cheng Reviewed-by: Rob Herring Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Matthias Brugger --- .../devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml b/Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml index abcbbe13723f..e4f465abcfe9 100644 --- a/Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml +++ b/Documentation/devicetree/bindings/spmi/mtk,spmi-mtk-pmif.yaml @@ -18,9 +18,14 @@ allOf: properties: compatible: - enum: - - mediatek,mt6873-spmi - - mediatek,mt8195-spmi + oneOf: + - enum: + - mediatek,mt6873-spmi + - mediatek,mt8195-spmi + - items: + - enum: + - mediatek,mt8186-spmi + - const: mediatek,mt8195-spmi reg: maxItems: 2 From patchwork Fri Mar 3 03:17:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Allen-KH Cheng X-Patchwork-Id: 63748 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp199739wrd; Thu, 2 Mar 2023 19:19:31 -0800 (PST) X-Google-Smtp-Source: AK7set9IUbK8ptW0S4+/Z1YLJ2fZi93VXuS1oicy82qSO8uiII6ggjtk/fjcE+1Gbl3+91qSHiyn X-Received: by 2002:a17:902:e752:b0:19e:748c:d419 with SMTP id p18-20020a170902e75200b0019e748cd419mr586003plf.46.1677813571513; Thu, 02 Mar 2023 19:19:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677813571; cv=none; d=google.com; s=arc-20160816; b=vO4u0IKFmx3Nu6pFCl9CGhWVbOpUZSv2NOMXrGrFoa1aowkmEI4OG8IGjGU6lTrFGN vCykk874KrNQZJvNBQ54myveOj4h8xfUsGyviGWS4UFx4hrIFSc90d1AeEj0oyqsodMK eNb53ALgKuf25scqBe1wvxYvhaqUBkv/XCIcYYT80DCKLew7UR1PvChM2tQqTjY8EAbb fP4TGC9t/iG5fQW945QRrfrklUS6iuA6fGDjDLK3YTW5R48S3V2G1S87jsfjf6WChwFT QYg+jjcmOLugQVUzJJzFDS8ow5G9RbKpUpPRBjMYa00w04+pDk4OSJpyB+NTh5HJc+lK EkOQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=qvEI8FN3wBwu6ZlVwOeje29yYcekRLOHCPmieBrV1IY=; b=ySN6sHFqoqe2NHg8a2ph/j2Rviqqt1s9eJAz6tOcFrEOZOe3NHYJ78JtQG37+bdK75 zLNehVb9vP3X6vc1QiL6eyEFfQpA+VoCh7iY28UN62a8PUhID6qi2JP4pJKCkIqY98BK zwSnKzNevIaBG89vRyRjQ+uYdggLErq2tqug+HUV1hcwsh54Udjmh7P7LhFIEc3uinsm +yhK4RowjrY3Baq2oYyeyXwXUwRPff9kl1x8L59tFV/kaxXfkfHwLITr5Ve2Zi1RcJ9E aLdcNj5izggrFuWUg6PGZ8YIeO1i1pBB4TsWLJNVAEzRCh0Xui+FCGITYz8/HkVaziBr V6ig== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=U5KMhvsE; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi index 178421fd8380..0e42bdbd2cb6 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -602,6 +602,21 @@ clock-names = "spi", "wrap"; }; + spmi: spmi@10015000 { + compatible = "mediatek,mt8186-spmi", "mediatek,mt8195-spmi"; + reg = <0 0x10015000 0 0x000e00>, <0 0x1001B000 0 0x000100>; + reg-names = "pmif", "spmimst"; + clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, + <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>, + <&topckgen CLK_TOP_SPMI_MST>; + clock-names = "pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux"; + assigned-clocks = <&topckgen CLK_TOP_SPMI_MST>; + assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; + interrupts = , + ; + status = "disabled"; + }; + systimer: timer@10017000 { compatible = "mediatek,mt8186-timer", "mediatek,mt6765-timer"; From patchwork Fri Mar 3 03:17:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Allen-KH Cheng X-Patchwork-Id: 63745 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp199714wrd; Thu, 2 Mar 2023 19:19:27 -0800 (PST) X-Google-Smtp-Source: AK7set/wBZDACCyb/sfvfwdVRzEcEn7LaKsSmXXuCv8pGQqDWIOIibyUh4doVoflI/n3ay+fP8ua X-Received: by 2002:a17:902:ec8a:b0:19d:138b:7c4a with SMTP id x10-20020a170902ec8a00b0019d138b7c4amr679713plg.3.1677813567030; Thu, 02 Mar 2023 19:19:27 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677813567; cv=none; d=google.com; s=arc-20160816; b=tRbpj80hWDmiW4H5shgdSuC3VulHCqX2xYWch915n1xHwjD0iSbxoS/TKPUfTlgFN2 fg4vzu9hn1yc0nryCbEueIkwLPDW/0I1Xky3JRRUrsDXseV3FOC3i3OgC29wkvkg6td6 wiJwYYGqm1SPqqCC0Ikbp4WDBK0AnB8gZXU6pHNS1VaeMYE9ghG/DtXuiLtmGDQhL3HY Tv1Csk8t9p6kI+3dgzv8rO6oWHbFIf8tNk4pfI3PAPAOczTf08cLUTqxoswYuTu1V/Qu pkCe8ridBbTOyZlzqrtVNhndJy7/zvFkXO2ODdjqd/w+jDvC3lcqmj/ymQRM/idDXoqm XVAA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=oaloW61vYsYhb9woC0pGOBCyeLOtwht+oMl/dWqapWk=; b=c1ifFdzr3uUgcWIpcUQYd41NW+m618zRVA6uEWFzZEe5KF8fIe4VhLUq37tyZ5BH+6 F/emINf+ndNL0jyyR0L1HQgdpB9uuTSAERorBNTR+rjkjkxiY11+1PThidSXDhtHXIsz Dllo4+tlJlFEr/zE4Gie4HVeEryNrWk/LQs41/wRrRxjv2gTkjPXZhSH3ISx6cOLZ+M1 rnLovMjdc/4UjPrR89eQCgief4KZfeKm+UU75RhQuvUV+MWI8tmzA2xu1ntH+tEmQDmy bm0M124x4dD2PKggzzTaxNHXb0+UoZq/os0w+mU38UEOPNd0eER08PhP2To4csvuPD9V EvZQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=glsV0qyl; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Allen-KH Cheng --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi index 0e42bdbd2cb6..337bcf3c1571 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -633,6 +633,22 @@ interrupts = ; }; + adsp: adsp@10680000 { + compatible = "mediatek,mt8186-dsp"; + reg = <0 0x10680000 0 0x2000>, <0 0x10800000 0 0x100000>, + <0 0x1068b000 0 0x100>, <0 0x1068f000 0 0x1000>; + reg-names = "cfg", "sram", "sec", "bus"; + clocks = <&topckgen CLK_TOP_AUDIODSP>, <&topckgen CLK_TOP_ADSP_BUS>; + clock-names = "audiodsp", "adsp_bus"; + assigned-clocks = <&topckgen CLK_TOP_AUDIODSP>, + <&topckgen CLK_TOP_ADSP_BUS>; + assigned-clock-parents = <&clk26m>, <&topckgen CLK_TOP_MAINPLL_D2_D2>; + mbox-names = "rx", "tx"; + mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>; + power-domains = <&spm MT8186_POWER_DOMAIN_ADSP_TOP>; + status = "disabled"; + }; + adsp_mailbox0: mailbox@10686000 { compatible = "mediatek,mt8186-adsp-mbox"; #mbox-cells = <0>; From patchwork Fri Mar 3 03:17:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Allen-KH Cheng X-Patchwork-Id: 63742 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp199460wrd; Thu, 2 Mar 2023 19:18:36 -0800 (PST) X-Google-Smtp-Source: AK7set8YiCAJKG64hE24SxlJAvirQoMiuRdIjGGE9xwRrEKoDKYk5LoaoOOQmrBLuyuNas/el3Fj X-Received: by 2002:a05:6a21:328d:b0:cc:6b15:2bd6 with SMTP id yt13-20020a056a21328d00b000cc6b152bd6mr890431pzb.25.1677813515678; Thu, 02 Mar 2023 19:18:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677813515; cv=none; d=google.com; s=arc-20160816; b=Zb1HqV0pp6n8mQ6QTSeBo7TgmZPJTzS9asEKivYCNkVZMJdRM+WsKy/YalAVDcybER 4ID4qa+zktd2Tiev7pzhFz5WwR2i/SFKHvbbr3REsTwAqiaRCU1EpKY5E+MqUdqc4OKu S/88Z518ei+7MtS93gQSd91WUjUFhlb1b/YOaKSDVtYZatMMShc0sN41jLetLvwbWBlL sDtN8UFVEo8dgHbWEAAH7q74gDZlW+VaCkGwoiRxjYedaTMjMT71Sg0NKDuMGWaF+tiy TaTPS400nN2j5ZZVRz8q/+h0zlTU2z/S4uN5TB5uR7o8d4coKnxfx44AQFeIUB4HNEQi 31wA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=D94WFA3SndeHGVIdcLs2oaCrSr2lE/+uRTmXDF6D3iM=; b=JMlhPqfq7QDIzVIyOs/a/c+Ff3OytFtKDrU/GgY0n5gEbDNIlovjdEJQjNz3YEOwjc N5Grl2kL0AiwfZaM+qMfuVeD7MniwSigdH+cfUlNCS5szyyKQop1Ea6fQFfZQa+jyG2T ZHfwCY5S8YEGhX+dtaXZ51JZWi6FtECoAotz9lQ+DEubYMh97OcWLacsoze77ECazwA4 Dk+xrYJch2ZCcfigOe2PBSowWT+XBETD8VYe8jBHWJAwPAqTtIJ7bRP2wS4lZoatTwwo Vd02Xf2gt0eXd/U0kNzj3eahQilfX5LbW78c4YT+XmHLcwLLn5qb2yrkvRDODU4pOhUm rjoA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=eJman8+H; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id e15-20020a63f54f000000b00502f13f32c5si963702pgk.862.2023.03.02.19.18.22; Thu, 02 Mar 2023 19:18:35 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=eJman8+H; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229893AbjCCDRx (ORCPT + 99 others); Thu, 2 Mar 2023 22:17:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36762 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229714AbjCCDRl (ORCPT ); Thu, 2 Mar 2023 22:17:41 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 23C9014E89; Thu, 2 Mar 2023 19:17:40 -0800 (PST) X-UUID: f1316a62b97111eda06fc9ecc4dadd91-20230303 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=D94WFA3SndeHGVIdcLs2oaCrSr2lE/+uRTmXDF6D3iM=; b=eJman8+H9rJwAqisCIedJ60Ud0yQCxTh+5gr2lgdy5OwnKHrlETBkYiGFgQc3rtHEHpnR280XQxj3HEFOcYUyvEYqstjO8N/GueAi2Jxma+lMWrN94MV/bG/PDmVqYlJDEhwRrmWajLKNpu0m/1KZ0Hgg68iCIgRz/Wtpv/Jo5M=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.20,REQID:03969ae1-dc0e-47c0-acc3-c13c484eb405,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-5 X-CID-META: VersionHash:25b5999,CLOUDID:ce4511b2-beed-4dfc-bd9c-e1b22fa6ccc4,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0 X-CID-BVR: 0 X-UUID: f1316a62b97111eda06fc9ecc4dadd91-20230303 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 631483533; Fri, 03 Mar 2023 11:17:34 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.25; Fri, 3 Mar 2023 11:17:33 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.25 via Frontend Transport; Fri, 3 Mar 2023 11:17:33 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , Krzysztof Kozlowski , Stephen Boyd , AngeloGioacchino Del Regno CC: , , , , , , Allen-KH Cheng Subject: [PATCH v3 5/7] arm64: dts: mediatek: mt8186: Add audio controller node Date: Fri, 3 Mar 2023 11:17:26 +0800 Message-ID: <20230303031728.24251-6-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230303031728.24251-1-allen-kh.cheng@mediatek.com> References: <20230303031728.24251-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS, SPF_PASS,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759314985060887559?= X-GMAIL-MSGID: =?utf-8?q?1759314985060887559?= Add audio controller node for MT8186 SoC. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 62 ++++++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi index 337bcf3c1571..f198fd8abc1d 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -1046,6 +1046,68 @@ }; }; + afe: audio-controller@11210000 { + compatible = "mediatek,mt8186-sound"; + reg = <0 0x11210000 0 0x2000>; + clocks = <&infracfg_ao CLK_INFRA_AO_AUDIO>, + <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_BCLK>, + <&topckgen CLK_TOP_AUDIO>, + <&topckgen CLK_TOP_AUD_INTBUS>, + <&topckgen CLK_TOP_MAINPLL_D2_D4>, + <&topckgen CLK_TOP_AUD_1>, + <&apmixedsys CLK_APMIXED_APLL1>, + <&topckgen CLK_TOP_AUD_2>, + <&apmixedsys CLK_APMIXED_APLL2>, + <&topckgen CLK_TOP_AUD_ENGEN1>, + <&topckgen CLK_TOP_APLL1_D8>, + <&topckgen CLK_TOP_AUD_ENGEN2>, + <&topckgen CLK_TOP_APLL2_D8>, + <&topckgen CLK_TOP_APLL_I2S0_MCK_SEL>, + <&topckgen CLK_TOP_APLL_I2S1_MCK_SEL>, + <&topckgen CLK_TOP_APLL_I2S2_MCK_SEL>, + <&topckgen CLK_TOP_APLL_I2S4_MCK_SEL>, + <&topckgen CLK_TOP_APLL_TDMOUT_MCK_SEL>, + <&topckgen CLK_TOP_APLL12_CK_DIV0>, + <&topckgen CLK_TOP_APLL12_CK_DIV1>, + <&topckgen CLK_TOP_APLL12_CK_DIV2>, + <&topckgen CLK_TOP_APLL12_CK_DIV4>, + <&topckgen CLK_TOP_APLL12_CK_DIV_TDMOUT_M>, + <&topckgen CLK_TOP_AUDIO_H>, + <&clk26m>; + clock-names = "aud_infra_clk", + "mtkaif_26m_clk", + "top_mux_audio", + "top_mux_audio_int", + "top_mainpll_d2_d4", + "top_mux_aud_1", + "top_apll1_ck", + "top_mux_aud_2", + "top_apll2_ck", + "top_mux_aud_eng1", + "top_apll1_d8", + "top_mux_aud_eng2", + "top_apll2_d8", + "top_i2s0_m_sel", + "top_i2s1_m_sel", + "top_i2s2_m_sel", + "top_i2s4_m_sel", + "top_tdm_m_sel", + "top_apll12_div0", + "top_apll12_div1", + "top_apll12_div2", + "top_apll12_div4", + "top_apll12_div_tdm", + "top_mux_audio_h", + "top_clk26m_clk"; + interrupts = ; + mediatek,apmixedsys = <&apmixedsys>; + mediatek,infracfg = <&infracfg_ao>; + mediatek,topckgen = <&topckgen>; + resets = <&watchdog MT8186_TOPRGU_AUDIO_SW_RST>; + reset-names = "audiosys"; + status = "disabled"; + }; + mmc0: mmc@11230000 { compatible = "mediatek,mt8186-mmc", "mediatek,mt8183-mmc"; From patchwork Fri Mar 3 03:17:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Allen-KH Cheng X-Patchwork-Id: 63746 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp199729wrd; Thu, 2 Mar 2023 19:19:29 -0800 (PST) X-Google-Smtp-Source: AK7set9EQWGkrcrDeVLu5LUbrLWgjmFoCSKnEZdL4xXg9OuyXOXgeAzz1+L3jj6FmP45j+sHNM+f X-Received: by 2002:a17:902:e848:b0:19e:6a6a:ddf4 with SMTP id t8-20020a170902e84800b0019e6a6addf4mr642962plg.51.1677813569397; Thu, 02 Mar 2023 19:19:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677813569; cv=none; d=google.com; s=arc-20160816; b=yBWoggx8Hvn4jk4Luha+CVKl71V0E5J/1BJkPQ8Q/cuCjQSiC8NExlWOCa4Q5iA5Av raV752MGFYYx2SmjPYUYVNROBXyIBbdJyr8oB68uQDv3MjUYO1hPkM0ojY0oP44g0KzC KVOW7zO3/ASdapCYPuJlZIckCpGS4ewtYlGiSAGxKC8zQpUTMsR6Eb/yhnPx0+2Ug/PD 5vUMIAmd+H/XpSS2yNNyAu6guJDmLKf0+B2Fe/3CK/LSlMtiNVy+G543UCA8PAG8oKOT 5IQ84Zq5kAGN6Rq2HI9OF1O10Ikj005XOuH/FkTFwJ48C3BSuyeZP9IBN/3yrV4yfrYU hn0g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=vpA7VnRboPQD/e1e4JhZRMkqXlZ620Cx2M7FaW0GNbA=; b=oUgrYPFEwa06tQ8WX61wLWwVPj9iRPkJtILtHgM2Ts6hQbK1jm1mfUw91Nov9oQIuP LCnNFchGD1PJn+6/G1uXw8s4e0z4MSs2Csf0jhYFZuGL8MOY0WdKwj7wFhIchp15i2h6 tCj75NTfjeqBW4z4nuPD1BvZW81TBJuXuC2pfBfIKBLQO4l2oJlFKKbkevY7s3bKXuiY MCIoRvf+ODNUnT3/yWbfWCnbx2e29CZU9UqdThpR579hcJbuvpoOIN+bKY1ys3/QmC+S hEdzH4XNldSFzHbw/mdQlO+hyRDY/MH65JcmJrjjfjtoSvZHERHjE2XkB/rDE6W4PFcL GGTw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=UpT+nUlD; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (out1.vger.email. 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Fri, 03 Mar 2023 11:17:35 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.25; Fri, 3 Mar 2023 11:17:34 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.25 via Frontend Transport; Fri, 3 Mar 2023 11:17:34 +0800 From: Allen-KH Cheng To: Matthias Brugger , Rob Herring , Krzysztof Kozlowski , Stephen Boyd , AngeloGioacchino Del Regno CC: , , , , , , Allen-KH Cheng Subject: [PATCH v3 6/7] arm64: dts: mediatek: mt8186: Add GCE node Date: Fri, 3 Mar 2023 11:17:27 +0800 Message-ID: <20230303031728.24251-7-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230303031728.24251-1-allen-kh.cheng@mediatek.com> References: <20230303031728.24251-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS, SPF_PASS,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759315041356209840?= X-GMAIL-MSGID: =?utf-8?q?1759315041356209840?= Add the Global Command Engine (GCE) node for MT8186 SoC Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi index f198fd8abc1d..b9d5af26771e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -5,6 +5,7 @@ */ /dts-v1/; #include +#include #include #include #include @@ -625,6 +626,15 @@ clocks = <&clk13m>; }; + gce: mailbox@1022c000 { + compatible = "mediatek,mt8186-gce"; + reg = <0 0X1022c000 0 0x4000>; + clocks = <&infracfg_ao CLK_INFRA_AO_GCE>; + clock-names = "gce"; + interrupts = ; + #mbox-cells = <2>; + }; + scp: scp@10500000 { compatible = "mediatek,mt8186-scp"; reg = <0 0x10500000 0 0x40000>, From patchwork Fri Mar 3 03:17:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Allen-KH Cheng X-Patchwork-Id: 63747 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp199727wrd; Thu, 2 Mar 2023 19:19:29 -0800 (PST) X-Google-Smtp-Source: AK7set95Gww94kWzKWMmKif5tYVVV11MVUhNl7i7l9g6KovQk/8OtysfuYkjz7+rZQpqNrGePQIs X-Received: by 2002:a17:90a:1957:b0:237:659a:a44d with SMTP id 23-20020a17090a195700b00237659aa44dmr119834pjh.9.1677813569242; Thu, 02 Mar 2023 19:19:29 -0800 (PST) ARC-Seal: i=1; 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Signed-off-by: Allen-KH Cheng --- arch/arm64/boot/dts/mediatek/mt8186.dtsi | 125 +++++++++++++++++++++++ 1 file changed, 125 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi index b9d5af26771e..909f1a6ae108 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi @@ -20,6 +20,13 @@ #address-cells = <2>; #size-cells = <2>; + aliases { + ovl = &ovl; + ovl_2l= &ovl_2l; + rdma0 = &rdma0; + rdma1 = &rdma1; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -1251,6 +1258,20 @@ reg = <0 0x14000000 0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; + mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, + <&gce 1 CMDQ_THR_PRIO_HIGHEST>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; + }; + + mutex: mutex@14001000 { + compatible = "mediatek,mt8186-disp-mutex"; + reg = <0 0x14001000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_MUTEX0>; + interrupts = ; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>; + mediatek,gce-events = , + ; + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; }; smi_common: smi@14002000 { @@ -1284,6 +1305,49 @@ power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; }; + ovl: ovl@14005000 { + compatible = "mediatek,mt8186-disp-ovl", + "mediatek,mt8192-disp-ovl"; + reg = <0 0x14005000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_OVL0>; + interrupts = ; + iommus = <&iommu_mm IOMMU_PORT_L0_OVL_RDMA0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>; + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; + }; + + ovl_2l: ovl@14006000 { + compatible = "mediatek,mt8186-disp-ovl-2l", + "mediatek,mt8192-disp-ovl-2l"; + reg = <0 0x14006000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; + interrupts = ; + iommus = <&iommu_mm IOMMU_PORT_L1_OVL_2L_RDMA0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>; + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; + }; + + rdma0: rdma@14007000 { + compatible = "mediatek,mt8186-disp-rdma", + "mediatek,mt8183-disp-rdma"; + reg = <0 0x14007000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_RDMA0>; + interrupts = ; + iommus = <&iommu_mm IOMMU_PORT_L1_DISP_RDMA0>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>; + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; + }; + + color: color@14009000 { + compatible = "mediatek,mt8186-disp-color", + "mediatek,mt8173-disp-color"; + reg = <0 0x14009000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_COLOR0>; + interrupts = ; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>; + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; + }; + dpi: dpi@1400a000 { compatible = "mediatek,mt8186-dpi"; reg = <0 0x1400a000 0 0x1000>; @@ -1301,6 +1365,56 @@ }; }; + ccorr: ccorr@1400b000 { + compatible = "mediatek,mt8186-disp-ccorr", + "mediatek,mt8192-disp-ccorr"; + reg = <0 0x1400b000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_CCORR0>; + interrupts = ; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>; + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; + }; + + aal: aal@1400c000 { + compatible = "mediatek,mt8186-disp-aal", + "mediatek,mt8183-disp-aal"; + reg = <0 0x1400c000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_AAL0>; + interrupts = ; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; + }; + + gamma: gamma@1400d000 { + compatible = "mediatek,mt8186-disp-gamma", + "mediatek,mt8183-disp-gamma"; + reg = <0 0x1400d000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_GAMMA0>; + interrupts = ; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>; + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; + }; + + postmask: postmask@1400e000 { + compatible = "mediatek,mt8186-disp-postmask", + "mediatek,mt8192-disp-postmask"; + reg = <0 0x1400e000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_POSTMASK0>; + interrupts = ; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; + }; + + dither: dither@1400f000 { + compatible = "mediatek,mt8186-disp-dither", + "mediatek,mt8183-disp-dither"; + reg = <0 0x1400f000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_DITHER0>; + interrupts = ; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>; + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; + }; + dsi0: dsi@14013000 { compatible = "mediatek,mt8186-dsi"; reg = <0 0x14013000 0 0x1000>; @@ -1334,6 +1448,17 @@ #iommu-cells = <1>; }; + rdma1: rdma@1401f000 { + compatible = "mediatek,mt8186-disp-rdma", + "mediatek,mt8183-disp-rdma"; + reg = <0 0x1401f000 0 0x1000>; + clocks = <&mmsys CLK_MM_DISP_RDMA1>; + interrupts = ; + iommus = <&iommu_mm IOMMU_PORT_L1_DISP_RDMA1>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xf000 0x1000>; + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>; + }; + wpesys: clock-controller@14020000 { compatible = "mediatek,mt8186-wpesys"; reg = <0 0x14020000 0 0x1000>;