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[2620:137:e000::1:20]) by mx.google.com with ESMTP id a9-20020a17090680c900b008d6b51de6bdsi16690482ejx.616.2023.03.02.04.28.54; Thu, 02 Mar 2023 04:29:17 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=JWQNsh3+; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229505AbjCBM1d (ORCPT + 99 others); Thu, 2 Mar 2023 07:27:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52424 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229658AbjCBM1b (ORCPT ); Thu, 2 Mar 2023 07:27:31 -0500 Received: from mail-ed1-x530.google.com (mail-ed1-x530.google.com [IPv6:2a00:1450:4864:20::530]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 34BD247425; Thu, 2 Mar 2023 04:27:30 -0800 (PST) Received: by mail-ed1-x530.google.com with SMTP id u9so17395102edd.2; Thu, 02 Mar 2023 04:27:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1677760048; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kaMxf79DO1CQ15GwbjLqNx3nQuf5cG/QHn3WlZsqaEo=; b=JWQNsh3+31Tt7qB7PNgYAQWcgUPJrfYp9gpYmeh9aDdpnjXrCH86wNNA1uOOg6HMpJ Cx/2Rfgw1qEinj5wcrH5WVW6UOjguGMfDIJwUGsfNSnW9sL55kjLQyzFGItGedUmEUyj GkH++vbp9y9P8EbBTToGqgJ25ShBysUpkg7Ta4oIB5yWBRh8+T9k/3PhxDS2OTWZb4a4 xLGb0SrXjLspD2HiRrPodyXQoI3nST0iWveorQu4l1QqfN8VNQGKP+FqG6sXksWqP7ej 748GU4nT3+RC5Zo17tZNCy480PstybSX5yqwclTeQ6P7LpH9kEzm+dKj9u5RU9nNJRWM BKzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1677760048; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kaMxf79DO1CQ15GwbjLqNx3nQuf5cG/QHn3WlZsqaEo=; b=FxoVjSMx490VXm076xtRwl1VLqTGlGBngqIMX8Xv9EXAjDjIYaaUan8zkeuTfBU3gg CAGZoiwokp3LGYCkZrotydeHEhhN+5SoEx5uha1q91/4bdXJblW6Z9bj2Vtk6bs7fPbd Ui5UaIonvfDQt/3Q1A8G7a4B7MCCfqgXTTLZHknC9f6Yl0sVWz71HVss6NjKk4O5f6kn Pfugude7s6iq/f1H65sMKNKTZsvAwablTfORpk2dhG5jR7K0fceuN8CleX2U43mNuNvj DDRyPDl9/DgICEbabMGLkEKGQtrY/cbl6KJ4GADr2wtnVy7+xhzLHFDd8tO4ftuuubJD ayaQ== X-Gm-Message-State: AO0yUKVgG9IezbKp9XTns1P/0pRDpYqvg5cUYOJVS7xewDH+HiqOk4sB ESkEjxlr5dOGVqSk69mF1yM= X-Received: by 2002:a17:906:4d87:b0:878:72d0:2817 with SMTP id s7-20020a1709064d8700b0087872d02817mr10773308eju.29.1677760048812; Thu, 02 Mar 2023 04:27:28 -0800 (PST) Received: from localhost.localdomain ([95.183.227.97]) by smtp.gmail.com with ESMTPSA id qc17-20020a170906d8b100b008ca37f3eae9sm7038375ejb.131.2023.03.02.04.27.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Mar 2023 04:27:28 -0800 (PST) From: Yassine Oudjana X-Google-Original-From: Yassine Oudjana To: Rob Herring , Krzysztof Kozlowski , Matthias Brugger , AngeloGioacchino Del Regno , Tinghan Shen , "Garmin.Chang" , MandyJH Liu Cc: Yassine Oudjana , Yassine Oudjana , devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/2] dt-bindings: power: Add binding for MediaTek MT6735 power controller Date: Thu, 2 Mar 2023 15:27:07 +0300 Message-Id: <20230302122708.73848-2-y.oudjana@protonmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230302122708.73848-1-y.oudjana@protonmail.com> References: <20230302122708.73848-1-y.oudjana@protonmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1759259034761519709?= X-GMAIL-MSGID: =?utf-8?q?1759259034761519709?= From: Yassine Oudjana Add DT binding for MediaTek MT6735 SCPSYS power controller. Signed-off-by: Yassine Oudjana Reviewed-by: AngeloGioacchino Del Regno --- .../bindings/power/mediatek,power-controller.yaml | 2 ++ .../devicetree/bindings/soc/mediatek/scpsys.txt | 1 + include/dt-bindings/power/mt6735-power.h | 14 ++++++++++++++ 3 files changed, 17 insertions(+) create mode 100644 include/dt-bindings/power/mt6735-power.h diff --git a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml index c9acef80f452..710db61cab53 100644 --- a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml +++ b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml @@ -23,6 +23,7 @@ properties: compatible: enum: + - mediatek,mt6735-power-controller - mediatek,mt6795-power-controller - mediatek,mt8167-power-controller - mediatek,mt8173-power-controller @@ -81,6 +82,7 @@ $defs: reg: description: | Power domain index. Valid values are defined in: + "include/dt-bindings/power/mt6735-power.h" - for MT6735 type power domain. "include/dt-bindings/power/mt6795-power.h" - for MT8167 type power domain. "include/dt-bindings/power/mt8167-power.h" - for MT8167 type power domain. "include/dt-bindings/power/mt8173-power.h" - for MT8173 type power domain. diff --git a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt index 2bc367793aec..3530a6668b48 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt +++ b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt @@ -20,6 +20,7 @@ Required properties: - compatible: Should be one of: - "mediatek,mt2701-scpsys" - "mediatek,mt2712-scpsys" + - "mediatek,mt6735-scpsys" - "mediatek,mt6765-scpsys" - "mediatek,mt6797-scpsys" - "mediatek,mt7622-scpsys" diff --git a/include/dt-bindings/power/mt6735-power.h b/include/dt-bindings/power/mt6735-power.h new file mode 100644 index 000000000000..782b49a88773 --- /dev/null +++ b/include/dt-bindings/power/mt6735-power.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_POWER_MT6735_POWER_H +#define _DT_BINDINGS_POWER_MT6735_POWER_H + +#define MT6735_POWER_DOMAIN_MD1 0 +#define MT6735_POWER_DOMAIN_CONN 1 +#define MT6735_POWER_DOMAIN_DIS 2 +#define MT6735_POWER_DOMAIN_MFG 3 +#define MT6735_POWER_DOMAIN_ISP 4 +#define MT6735_POWER_DOMAIN_VDE 5 +#define MT6735_POWER_DOMAIN_VEN 6 + +#endif From patchwork Thu Mar 2 12:27:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yassine Oudjana X-Patchwork-Id: 63394 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:5915:0:0:0:0:0 with SMTP id v21csp4207079wrd; Thu, 2 Mar 2023 04:30:01 -0800 (PST) X-Google-Smtp-Source: AK7set/4chbgE0w5fiOoa+cp1qzbmLu921EKXBKTQFFQrBOyXH0noMHR/ikzfcXJ/psMrsU0Kxo5 X-Received: by 2002:a17:906:7c8:b0:8b1:a3c7:a9c9 with SMTP id m8-20020a17090607c800b008b1a3c7a9c9mr8967291ejc.70.1677760201841; Thu, 02 Mar 2023 04:30:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1677760201; cv=none; d=google.com; s=arc-20160816; b=tlQPKNL0tiQRPtvDg5+LBk8pme3EKbRGgkM2nWKb01ZFLnGA1bG837rub6qWYB3fOI 3UxxmY5ax9DmxaGLwM6skOjUeFljZJSCWrZrZpsxRfLj0HufhXJOW3LqOaeVnVTk3pAW aw9nwFkEyfqgiXR153tXVyeJQE6JQrQ+SHksgLLj5OEFfUozFkYnMhE4yn00+YLriVJ3 HlgZrXIcnt8cKOOykpUadNY1seU68h1HQCXNBzF4aacKkTRrljbuyNbnJ/dpRNeMjnOx uENADjf5HF4fyn0ffNwx2z1h+0/W4L9XjM3RrjtCc45utZjvjcxuyFFkNO0eWDaTOqWo TSqQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=B0YVPdDle1NaFco5UbTAMJ63K0C79g/uIPg380c+Gdo=; b=yu54XTtkM9/IlzbGpbGTbWZpDOXJTanKY0tlcN1YYn06bjG148gUQ95KdyCdOuKmCL zOCC+Z9Mj6y+FdF0uWqGQOaBdQPw+5uysQu4ASuXhZoYfw4bh1dGeC75w8uVZAWVjrLm 9BwdDM71dBfKEKdbiLYkv2YqJbEbvXScDVrS1ebS7ta+WVrmRpmi/hQ4/FqWrw3YyqbJ RmAq6NtQpdqQiX/4zqyZPkVGR3hfLiIEfUUP34p/arsk3OyGAczCJ/SGfNVKzOVgnIu0 xQ4LFnCGHXMkT9XE02Jbimz/6BJiQcCHfuRJXX3o6+481YsvyYDV1/NSwIFCpSU6+7Lw tatg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=Qv7Kkabr; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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All non-CPU power domains are added except for MD2 (C2K modem), which is left out due to issues with powering it on. Signed-off-by: Yassine Oudjana Reviewed-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mt6735-pm-domains.h | 96 ++++++++++++++++++++++++ drivers/soc/mediatek/mtk-pm-domains.c | 5 ++ drivers/soc/mediatek/mtk-pm-domains.h | 2 + include/linux/soc/mediatek/infracfg.h | 5 ++ 4 files changed, 108 insertions(+) create mode 100644 drivers/soc/mediatek/mt6735-pm-domains.h diff --git a/drivers/soc/mediatek/mt6735-pm-domains.h b/drivers/soc/mediatek/mt6735-pm-domains.h new file mode 100644 index 000000000000..59e830fc354b --- /dev/null +++ b/drivers/soc/mediatek/mt6735-pm-domains.h @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT6735_PM_DOMAINS_H +#define __SOC_MEDIATEK_MT6735_PM_DOMAINS_H + +#include "mtk-pm-domains.h" +#include + +/* + * MT6735 power domain support + */ + +static const struct scpsys_domain_data scpsys_domain_data_mt6735[] = { + [MT6735_POWER_DOMAIN_MD1] = { + .name = "md1", + .sta_mask = PWR_STATUS_MD1, + .ctl_offs = SPM_MD1_PWR_CON, + .pwr_sta_offs = SPM_PWR_STATUS, + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = 0, + .bp_infracfg = { + BUS_PROT_UPDATE_TOPAXI(MT6735_TOP_AXI_PROT_EN_MD1), + }, + }, + [MT6735_POWER_DOMAIN_CONN] = { + .name = "conn", + .sta_mask = PWR_STATUS_CONN, + .ctl_offs = SPM_CONN_PWR_CON, + .pwr_sta_offs = SPM_PWR_STATUS, + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = 0, + .bp_infracfg = { + BUS_PROT_UPDATE_TOPAXI(MT6735_TOP_AXI_PROT_EN_CONN), + }, + }, + [MT6735_POWER_DOMAIN_DIS] = { + .name = "dis", + .sta_mask = PWR_STATUS_DISP, + .ctl_offs = SPM_DIS_PWR_CON, + .pwr_sta_offs = SPM_PWR_STATUS, + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_infracfg = { + BUS_PROT_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MM_M0), + }, + }, + [MT6735_POWER_DOMAIN_MFG] = { + .name = "mfg", + .sta_mask = PWR_STATUS_MFG, + .ctl_offs = SPM_MFG_PWR_CON, + .pwr_sta_offs = SPM_PWR_STATUS, + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_infracfg = { + BUS_PROT_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MFG_S), + }, + }, + [MT6735_POWER_DOMAIN_ISP] = { + .name = "isp", + .sta_mask = PWR_STATUS_ISP, + .ctl_offs = SPM_ISP_PWR_CON, + .pwr_sta_offs = SPM_PWR_STATUS, + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(13, 12), + }, + [MT6735_POWER_DOMAIN_VDE] = { + .name = "vde", + .sta_mask = PWR_STATUS_VDEC, + .ctl_offs = SPM_VDE_PWR_CON, + .pwr_sta_offs = SPM_PWR_STATUS, + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + }, + [MT6735_POWER_DOMAIN_VEN] = { + .name = "ven", + .sta_mask = BIT(8), + .ctl_offs = SPM_VEN_PWR_CON, + .pwr_sta_offs = SPM_PWR_STATUS, + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(15, 12), + }, +}; + +static const struct scpsys_soc_data mt6735_scpsys_data = { + .domains_data = scpsys_domain_data_mt6735, + .num_domains = ARRAY_SIZE(scpsys_domain_data_mt6735), +}; + +#endif /* __SOC_MEDIATEK_MT6735_PM_DOMAINS_H */ diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c index 354249cc1b12..0ade6b8cafff 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.c +++ b/drivers/soc/mediatek/mtk-pm-domains.c @@ -16,6 +16,7 @@ #include #include +#include "mt6735-pm-domains.h" #include "mt6795-pm-domains.h" #include "mt8167-pm-domains.h" #include "mt8173-pm-domains.h" @@ -568,6 +569,10 @@ static void scpsys_domain_cleanup(struct scpsys *scpsys) } static const struct of_device_id scpsys_of_match[] = { + { + .compatible = "mediatek,mt6735-power-controller", + .data = &mt6735_scpsys_data, + }, { .compatible = "mediatek,mt6795-power-controller", .data = &mt6795_scpsys_data, diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/mtk-pm-domains.h index 5ec53ee073c4..4aa37dc57ac7 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.h +++ b/drivers/soc/mediatek/mtk-pm-domains.h @@ -19,6 +19,7 @@ #define SPM_ISP_PWR_CON 0x0238 #define SPM_DIS_PWR_CON 0x023c #define SPM_CONN_PWR_CON 0x0280 +#define SPM_MD1_PWR_CON 0x0284 #define SPM_VEN2_PWR_CON 0x0298 #define SPM_AUDIO_PWR_CON 0x029c #define SPM_MFG_2D_PWR_CON 0x02c0 @@ -28,6 +29,7 @@ #define SPM_PWR_STATUS 0x060c #define SPM_PWR_STATUS_2ND 0x0610 +#define PWR_STATUS_MD1 BIT(0) #define PWR_STATUS_CONN BIT(1) #define PWR_STATUS_DISP BIT(3) #define PWR_STATUS_MFG BIT(4) diff --git a/include/linux/soc/mediatek/infracfg.h b/include/linux/soc/mediatek/infracfg.h index 07f67b3d8e97..c60f8e7e976e 100644 --- a/include/linux/soc/mediatek/infracfg.h +++ b/include/linux/soc/mediatek/infracfg.h @@ -393,6 +393,11 @@ #define MT7622_TOP_AXI_PROT_EN_WB (BIT(2) | BIT(6) | \ BIT(7) | BIT(8)) +#define MT6735_TOP_AXI_PROT_EN_CONN (BIT(2) | BIT(8)) +#define MT6735_TOP_AXI_PROT_EN_MD1 (BIT(24) | BIT(25) | \ + BIT(26) | BIT(27) | \ + BIT(28)) + #define INFRA_TOPAXI_PROTECTEN 0x0220 #define INFRA_TOPAXI_PROTECTSTA1 0x0228 #define INFRA_TOPAXI_PROTECTEN_SET 0x0260